add EMAC driver.
This commit is contained in:
aozima
parent
a8106442e1
commit
ff4fcd5b56
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@ -14,7 +14,7 @@ LR_IROM1 (0) (1024 * 128)
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}
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; RW data
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RW_IRAM1 0x20000000 (1024 * 64)
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RW_IRAM1 0x20000000 (1024 * 48)
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{
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.ANY (+RW +ZI)
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}
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@ -20,6 +20,14 @@
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void rt_init_thread_entry(void* parameter)
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{
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rt_components_init();
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rt_kprintf("new");
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#ifdef RT_USING_LWIP
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cme_m7_eth_init();
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//set_if("e0", "192.168.3.99", "192.168.1.1", "255.255.255.0");
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#endif /* RT_USING_LWIP */
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}
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int rt_application_init()
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@ -39,10 +47,4 @@ int rt_application_init()
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return 0;
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}
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void NMI_Handler(void)
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{
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rt_kprintf("NMI_Handler\n");
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}
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/*@}*/
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@ -3,7 +3,16 @@ Import('rtconfig')
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from building import *
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cwd = os.path.join(str(Dir('#')), 'drivers')
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src = Glob('*.c')
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src = ['board.c']
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# add uart driver.
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src += ['uart.c']
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# add EMAC driver for Lwip.
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if GetDepend('RT_USING_LWIP') == True:
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src += ['emac.c', 'app_phy.c']
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CPPPATH = [cwd]
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group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
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@ -0,0 +1,121 @@
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#include <stdio.h>
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#include "app_phy.h"
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#define PHY_BASE_ADDR 0x7
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#define PHY_REG_CONTROL 0x0
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#define PHY_REG_STATUS 0x1
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#define PHY_REG_ANE 0x6
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#define PHY_REG_SPEC_STATUS 0x11
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#define PHY_REG_EXTEND_STATUS 0x1B
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#define PHY_BIT_CONTROL_RESET 0x8000 /*!< Control reg : reset */
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#define PHY_BIT_CONTROL_ANEN 0x1000 /*!< Control reg : auto-negotiation enable */
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#define PHY_BIT_CONTROL_RSAN 0x0200 /*!< Control reg : auto-negotiation restart */
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#define PHY_BIT_STATUS_ANC 0x0020 /*!< Status reg : auto-negotiation complete */
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#define PHY_BIT_STATUS_LINK 0x0004 /*!< Status reg : link is up */
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#define PHY_BIT_ANE_LPAN 0x0001 /*!< ANE reg : link partner can auto-neg */
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#define PHY_BIT_SPEED 0xC000 /*!< specific status reg : speed */
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#define PHY_BIT_DUPLEX 0x2000 /*!< specific status reg : duplex */
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#define PHY_BIT_AUTO_MEDIA_DISABLE 0x8000 /*!< extended status reg : auto media select disable */
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#define PHY_BIT_AUTO_MEDIA_REG_DISABLE 0x0200 /*!< extended status reg : auto media register select disable */
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void phy_Reset() {
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ETH_PhyWrite(PHY_BASE_ADDR, PHY_REG_CONTROL, PHY_BIT_CONTROL_RESET);
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while (1) {
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uint32_t ret = ETH_PhyRead(PHY_BASE_ADDR, PHY_REG_CONTROL);
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if ((ret & PHY_BIT_CONTROL_RESET) == 0) {
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break;
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}
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}
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}
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void phy_AutoMediaSelect() {
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uint32_t data;
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// auto media and auto media register selection
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data = ETH_PhyRead(PHY_BASE_ADDR, PHY_REG_EXTEND_STATUS);
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data &= ~PHY_BIT_AUTO_MEDIA_DISABLE;
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data &= ~PHY_BIT_AUTO_MEDIA_REG_DISABLE;
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ETH_PhyWrite(PHY_BASE_ADDR, PHY_REG_EXTEND_STATUS, data);
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}
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void phy_AutoNeg() {
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uint32_t data;
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data = ETH_PhyRead(PHY_BASE_ADDR, PHY_REG_CONTROL);
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data |= (PHY_BIT_CONTROL_ANEN | PHY_BIT_CONTROL_RSAN);
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ETH_PhyWrite(PHY_BASE_ADDR, PHY_REG_CONTROL, data);
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while (1) {
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uint32_t ret = ETH_PhyRead(PHY_BASE_ADDR, PHY_REG_STATUS);
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if ((ret & PHY_BIT_STATUS_ANC) == PHY_BIT_STATUS_ANC) {
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break;
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}
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}
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}
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BOOL phy_IsLink() {
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uint32_t ret = ETH_PhyRead(PHY_BASE_ADDR, PHY_REG_STATUS);
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return (ret & PHY_BIT_STATUS_LINK) ? TRUE : FALSE;
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}
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BOOL phy_PartnerCanAutoNeg() {
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uint32_t ret = ETH_PhyRead(PHY_BASE_ADDR, PHY_REG_ANE);
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return (ret & PHY_BIT_ANE_LPAN) ? TRUE : FALSE;
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}
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uint32_t phy_GetSpeed() {
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uint32_t ret = ETH_PhyRead(PHY_BASE_ADDR, PHY_REG_SPEC_STATUS);
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return ((ret & PHY_BIT_SPEED) >> 14);
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}
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uint32_t phy_GetDuplex() {
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uint32_t ret = ETH_PhyRead(PHY_BASE_ADDR, PHY_REG_SPEC_STATUS);
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return ((ret & PHY_BIT_DUPLEX) >> 13);
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}
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BOOL phy_Init() {
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phy_AutoMediaSelect();
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phy_AutoNeg();
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if (!phy_PartnerCanAutoNeg()) {
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printf("Warning:: PHY's partner can't do auto-negotiation\n");
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}
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if (!phy_IsLink()) {
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printf("link is down\n");
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return FALSE;
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}
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{
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uint32_t speed = phy_GetSpeed();
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if (speed == PHY_SPEED_10) {
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speed = 10;
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} else if (speed == PHY_SPEED_100) {
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speed = 100;
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} else if (speed == PHY_SPEED_1000) {
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speed = 1000;
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}
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printf("PHY runs in %dM speed %s duplex\n",
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speed, (phy_GetDuplex() == PHY_DUPLEX_HALF) ? "half" : "full");
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}
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// After auto-negcioation, Mawell PHY need some
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// time to initial itself.
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// So we have to delay some time since different
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// connection way, such as direct wire, hub, switch.
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// If not to delay, the first several sent frame
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// may be lost.
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// Please according to actual environment to tune
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// this delay.
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udelay(200000);
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return TRUE;
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}
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@ -0,0 +1,32 @@
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#ifndef __APP_PHY_H
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#define __APP_PHY_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "cmem7_includes.h"
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#define PHY_SPEED_10 0x0 /*!< SPEED : 10M */
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#define PHY_SPEED_100 0x1 /*!< SPEED : 100M */
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#define PHY_SPEED_1000 0x2 /*!< SPEED : 1000M */
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#define PHY_DUPLEX_HALF 0x0 /*!< DUPLEX : half */
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#define PHY_DUPLEX_FULL 0x1 /*!< DUPLEX : full */
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void phy_Reset(void);
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void phy_AutoNeg(void);
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BOOL phy_IsLink(void);
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BOOL phy_PartnerCanAutoNeg(void);
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uint32_t phy_GetSpeed(void);
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uint32_t phy_GetDuplex(void);
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BOOL phy_Init(void);
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#ifdef __cplusplus
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}
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#endif
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#endif
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@ -49,7 +49,10 @@ static void idle_hook(void)
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*/
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void rt_hw_board_init()
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{
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rt_thread_idle_sethook(idle_hook);
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//rt_thread_idle_sethook(idle_hook);
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/* Configure the NVIC Preemption Priority Bits */
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NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
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SysTick_Config(SYSTEM_CLOCK_FREQ / RT_TICK_PER_SECOND);
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@ -0,0 +1,457 @@
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/*
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* File : emac.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006-2014, RT-Thread Develop Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://openlab.rt-thread.com/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2014-08-29 aozima first implementation
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*/
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#include <rtthread.h>
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#include <netif/ethernetif.h>
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#include "lwipopts.h"
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#include "board.h"
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#include "app_phy.h"
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//#include "app_bufferpool.h"
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//#include "app_bufferqueue.h"
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/* debug option */
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#define ETH_DEBUG
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//#define ETH_RX_DUMP
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//#define ETH_TX_DUMP
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#ifdef ETH_DEBUG
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#define CME_ETH_PRINTF rt_kprintf
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#else
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#define CME_ETH_PRINTF(...)
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#endif
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#define MAX_ADDR_LEN 6
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struct rt_cme_eth
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{
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/* inherit from ethernet device */
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struct eth_device parent;
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/* interface address info. */
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rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */
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uint32_t ETH_Speed;
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uint32_t ETH_Mode;
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struct rt_semaphore tx_buf_free;
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struct rt_mutex lock;
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};
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static struct rt_cme_eth cme_eth_device;
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#if defined(ETH_RX_DUMP) || defined(ETH_TX_DUMP)
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static void packet_dump(const char * msg, const struct pbuf* p)
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{
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const struct pbuf* q;
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rt_uint32_t i,j;
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rt_uint8_t *ptr;
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rt_kprintf("%s %d byte\n", msg, p->tot_len);
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i=0;
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for(q=p; q != RT_NULL; q= q->next)
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{
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ptr = q->payload;
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for(j=0; j<q->len; j++)
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{
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if( (i%8) == 0 )
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{
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rt_kprintf(" ");
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}
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if( (i%16) == 0 )
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{
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rt_kprintf("\r\n");
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}
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rt_kprintf("%02x ",*ptr);
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i++;
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ptr++;
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}
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}
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rt_kprintf("\n\n");
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}
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#else
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#define packet_dump(...)
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#endif /* dump */
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/////////////////////////////////////////////////////////////////
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uint32_t rxTotalMemory = 0x2000;
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uint32_t rxDescNum = 3;
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uint32_t rxBufSize = 0x400;
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uint32_t rxBaseAddr = 0x2000C000;// C000-48K
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uint32_t txBaseAddr = 0x2000E000;// E000-56K
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uint32_t txTotalMemory = 0x2000;
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BOOL isRxNoBuf = FALSE;
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#define ETH_MAX_PACKET_SIZE 1520 /* ETH_HEADER + ETH_EXTRA + MAX_ETH_PAYLOAD + ETH_CRC */
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#define ETH_RXBUFNB 4
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#define ETH_TXBUFNB 2
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struct eth_rx_buffer
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{
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ETH_RX_DESC desc;
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uint32_t buffer[ETH_MAX_PACKET_SIZE/4];
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};
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struct eth_tx_buffer
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{
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ETH_TX_DESC desc;
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uint32_t buffer[ETH_MAX_PACKET_SIZE/4];
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};
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static struct eth_rx_buffer rx_buffer[ETH_RXBUFNB];
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static struct eth_tx_buffer tx_buffer[ETH_TXBUFNB];
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static void RxDescChainInit(void)
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{
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uint32_t i;
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// initialize rx descriptor
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ETH_RX_DESC *desc = &rx_buffer[0].desc;
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for (i = 0; i < ETH_RXBUFNB; i++)
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{
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desc->RX_1.RX1_b.SIZE = ETH_MAX_PACKET_SIZE;
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desc->bufAddr = (uint32_t)rx_buffer[i].buffer;
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if((i+1) == ETH_RXBUFNB)
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desc->nextDescAddr = (uint32_t)&rx_buffer[0].desc;
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else
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desc->nextDescAddr = (uint32_t)&rx_buffer[i+1].desc;
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desc = (ETH_RX_DESC *)desc->nextDescAddr;
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}
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ETH_SetRxDescRing(&rx_buffer[0].desc);
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}
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static void TxDescChainInit(void)
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{
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uint32_t i;
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// initialize tx descriptor
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ETH_TX_DESC *desc = &tx_buffer[0].desc;
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for (i = 0; i < ETH_TXBUFNB; i++)
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{
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desc->TX_1.TX1_b.SIZE = ETH_MAX_PACKET_SIZE;
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desc->bufAddr = (uint32_t)tx_buffer[i].buffer;
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if((i+1) == ETH_TXBUFNB)
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desc->nextDescAddr = (uint32_t)&tx_buffer[0].desc;
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else
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desc->nextDescAddr = (uint32_t)&tx_buffer[i+1].desc;
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desc = (ETH_TX_DESC *)desc->nextDescAddr;
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}
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ETH_SetTxDescRing(&tx_buffer[0].desc);
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}
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/////////////////////////////////////////////////////////////////
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/* initialize the interface */
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static rt_err_t rt_cme_eth_init(rt_device_t dev)
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{
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struct rt_cme_eth * cme_eth = (struct rt_cme_eth *)dev;
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ETH_InitTypeDef init;
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ETH_FrameFilter flt;
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init.ETH_Speed = phy_GetSpeed();
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init.ETH_Duplex = phy_GetDuplex();
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init.ETH_LinkUp = phy_IsLink();
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init.ETH_RxEn = TRUE;
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init.ETH_TxEn = TRUE;
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init.ETH_ChecksumOffload = FALSE;
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init.ETH_JumboFrame = FALSE;
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memcpy(init.ETH_MacAddr, cme_eth->dev_addr, sizeof(init.ETH_MacAddr));
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// init.ETH_MacAddr[0] = 0x00;
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// init.ETH_MacAddr[1] = 0x1E;
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// init.ETH_MacAddr[2] = 0xC9;
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// init.ETH_MacAddr[3] = 0x3B;
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// init.ETH_MacAddr[4] = 0x11;
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// init.ETH_MacAddr[5] = 0xF8;
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// Disable broadcast;
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flt.ETH_BroadcastFilterEnable = FALSE;
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flt.ETH_OwnFilterEnable = FALSE;
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flt.ETH_SelfDrop = FALSE;
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flt.ETH_SourceFilterEnable = FALSE;
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flt.ETH_SourceDrop = FALSE;
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flt.ETH_SourceMacAddr[0] = 0x00;
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flt.ETH_SourceMacAddr[1] = 0x1E;
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flt.ETH_SourceMacAddr[2] = 0xC9;
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flt.ETH_SourceMacAddr[3] = 0x3B;
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flt.ETH_SourceMacAddr[4] = 0x11;
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flt.ETH_SourceMacAddr[5] = 0xF9;
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init.ETH_Filter = &flt;
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if (!phy_Init())
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{
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rt_kprintf("phy_Init failed!\n");
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while (1);
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}
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if (!ETH_Init(&init))
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{
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rt_kprintf("ETH_Init failed!\n");
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while (1);
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}
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RxDescChainInit();
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TxDescChainInit();
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ETH_EnableInt(ETH_INT_BUS_FATAL_ERROR, TRUE);
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ETH_EnableInt(ETH_INT_RX_COMPLETE_FRAME, TRUE);
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ETH_EnableInt(ETH_INT_RX_BUF_UNAVAI, TRUE);
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ETH_EnableInt(ETH_INT_RX_STOP, TRUE);
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ETH_StartRx();
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ETH_EnableInt(ETH_INT_TX_COMPLETE_FRAME, TRUE);
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ETH_StartTx();
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return RT_EOK;
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}
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static rt_err_t rt_cme_eth_open(rt_device_t dev, rt_uint16_t oflag)
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{
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return RT_EOK;
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}
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static rt_err_t rt_cme_eth_close(rt_device_t dev)
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{
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return RT_EOK;
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}
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static rt_size_t rt_cme_eth_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
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{
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rt_set_errno(-RT_ENOSYS);
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return 0;
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}
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static rt_size_t rt_cme_eth_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
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{
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rt_set_errno(-RT_ENOSYS);
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return 0;
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}
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static rt_err_t rt_cme_eth_control(rt_device_t dev, rt_uint8_t cmd, void *args)
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{
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switch(cmd)
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{
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case NIOCTL_GADDR:
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/* get mac address */
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if(args) rt_memcpy(args, cme_eth_device.dev_addr, 6);
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else return -RT_ERROR;
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break;
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default :
|
||||
break;
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
/* ethernet device interface */
|
||||
/* transmit packet. */
|
||||
rt_err_t rt_cme_eth_tx( rt_device_t dev, struct pbuf* p)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
ETH_TX_DESC *desc;
|
||||
struct rt_cme_eth * cme_eth = (struct rt_cme_eth *)dev;
|
||||
|
||||
rt_mutex_take(&cme_eth->lock, RT_WAITING_FOREVER);
|
||||
|
||||
#ifdef ETH_TX_DUMP
|
||||
packet_dump("TX dump", p);
|
||||
#endif /* ETH_TX_DUMP */
|
||||
|
||||
/* get free tx buffer */
|
||||
{
|
||||
rt_err_t result;
|
||||
result = rt_sem_take(&cme_eth->tx_buf_free, RT_TICK_PER_SECOND/10);
|
||||
if (result != RT_EOK)
|
||||
{
|
||||
result = -RT_ERROR;
|
||||
goto _exit;
|
||||
}
|
||||
}
|
||||
|
||||
desc = ETH_AcquireFreeTxDesc();
|
||||
if(desc == RT_NULL)
|
||||
{
|
||||
CME_ETH_PRINTF("TxDesc not ready!\n");
|
||||
RT_ASSERT(0);
|
||||
result = -RT_ERROR;
|
||||
goto _exit;
|
||||
}
|
||||
|
||||
desc->TX_0.TX0_b.FS = TRUE;
|
||||
desc->TX_0.TX0_b.LS = TRUE;
|
||||
desc->TX_1.TX1_b.SIZE = p->tot_len;
|
||||
|
||||
pbuf_copy_partial(p, ( void *)(desc->bufAddr), p->tot_len, 0);
|
||||
|
||||
ETH_ReleaseTxDesc(desc);
|
||||
ETH_ResumeTx();
|
||||
|
||||
_exit:
|
||||
rt_mutex_release(&cme_eth->lock);
|
||||
return result;
|
||||
}
|
||||
|
||||
/* reception packet. */
|
||||
struct pbuf *rt_cme_eth_rx(rt_device_t dev)
|
||||
{
|
||||
struct pbuf* p = RT_NULL;
|
||||
ETH_RX_DESC *desc;
|
||||
uint32_t framelength;
|
||||
struct rt_cme_eth * cme_eth = (struct rt_cme_eth *)dev;
|
||||
|
||||
rt_mutex_take(&cme_eth->lock, RT_WAITING_FOREVER);
|
||||
|
||||
desc = ETH_AcquireFreeRxDesc();
|
||||
if(desc == RT_NULL)
|
||||
{
|
||||
ETH_EnableInt(ETH_INT_RX_COMPLETE_FRAME, TRUE);
|
||||
ETH_EnableInt(ETH_INT_RX_BUF_UNAVAI, TRUE);
|
||||
ETH_ResumeRx();
|
||||
goto _exit;
|
||||
}
|
||||
|
||||
framelength = desc->RX_0.RX0_b.FL;
|
||||
|
||||
/* allocate buffer */
|
||||
p = pbuf_alloc(PBUF_LINK, framelength, PBUF_RAM);
|
||||
if (p != RT_NULL)
|
||||
{
|
||||
pbuf_take(p, (const void *)(desc->bufAddr), framelength);
|
||||
#ifdef ETH_RX_DUMP
|
||||
packet_dump("RX dump", p);
|
||||
#endif /* ETH_RX_DUMP */
|
||||
}
|
||||
|
||||
ETH_ReleaseRxDesc(desc);
|
||||
|
||||
_exit:
|
||||
rt_mutex_release(&cme_eth->lock);
|
||||
return p;
|
||||
}
|
||||
|
||||
static void NVIC_Configuration(void)
|
||||
{
|
||||
NVIC_InitTypeDef NVIC_InitStructure;
|
||||
|
||||
/* Enable the USARTy Interrupt */
|
||||
NVIC_InitStructure.NVIC_IRQChannel = ETH_INT_IRQn;
|
||||
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
|
||||
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
|
||||
NVIC_InitStructure.NVIC_IRQChannelCmd = TRUE;
|
||||
NVIC_Init(&NVIC_InitStructure);
|
||||
}
|
||||
|
||||
int cme_m7_eth_init(void)
|
||||
{
|
||||
// /* PHY RESET: PA4 */
|
||||
// {
|
||||
// GPIO_ResetBits(GPIOA, GPIO_Pin_4);
|
||||
// rt_thread_delay(2);
|
||||
// GPIO_SetBits(GPIOA, GPIO_Pin_4);
|
||||
// rt_thread_delay(2);
|
||||
// }
|
||||
|
||||
// GPIO_Configuration();
|
||||
NVIC_Configuration();
|
||||
|
||||
// cme_eth_device.ETH_Speed = ETH_Speed_100M;
|
||||
// cme_eth_device.ETH_Mode = ETH_Mode_FullDuplex;
|
||||
|
||||
/* OUI 00-80-E1 STMICROELECTRONICS. */
|
||||
cme_eth_device.dev_addr[0] = 0x00;
|
||||
cme_eth_device.dev_addr[1] = 0x80;
|
||||
cme_eth_device.dev_addr[2] = 0xE1;
|
||||
/* generate MAC addr from 96bit unique ID (only for test). */
|
||||
// cme_eth_device.dev_addr[3] = *(rt_uint8_t*)(0x1FFF7A10+4);
|
||||
// cme_eth_device.dev_addr[4] = *(rt_uint8_t*)(0x1FFF7A10+2);
|
||||
// cme_eth_device.dev_addr[5] = *(rt_uint8_t*)(0x1FFF7A10+0);
|
||||
cme_eth_device.dev_addr[3] = 12;
|
||||
cme_eth_device.dev_addr[4] = 34;
|
||||
cme_eth_device.dev_addr[5] = 56;
|
||||
|
||||
cme_eth_device.parent.parent.init = rt_cme_eth_init;
|
||||
cme_eth_device.parent.parent.open = rt_cme_eth_open;
|
||||
cme_eth_device.parent.parent.close = rt_cme_eth_close;
|
||||
cme_eth_device.parent.parent.read = rt_cme_eth_read;
|
||||
cme_eth_device.parent.parent.write = rt_cme_eth_write;
|
||||
cme_eth_device.parent.parent.control = rt_cme_eth_control;
|
||||
cme_eth_device.parent.parent.user_data = RT_NULL;
|
||||
|
||||
cme_eth_device.parent.eth_rx = rt_cme_eth_rx;
|
||||
cme_eth_device.parent.eth_tx = rt_cme_eth_tx;
|
||||
|
||||
/* init EMAC lock */
|
||||
rt_mutex_init(&cme_eth_device.lock, "emac0", RT_IPC_FLAG_PRIO);
|
||||
|
||||
/* init tx buffer free semaphore */
|
||||
rt_sem_init(&cme_eth_device.tx_buf_free,
|
||||
"tx_buf",
|
||||
ETH_TXBUFNB,
|
||||
RT_IPC_FLAG_FIFO);
|
||||
|
||||
/* register eth device */
|
||||
eth_device_init(&(cme_eth_device.parent), "e0");
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
void ETH_IRQHandler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
if (ETH_GetIntStatus(ETH_INT_TX_COMPLETE_FRAME))
|
||||
{
|
||||
rt_sem_release(&cme_eth_device.tx_buf_free);
|
||||
ETH_ClearInt(ETH_INT_TX_COMPLETE_FRAME);
|
||||
}
|
||||
|
||||
if (ETH_GetIntStatus(ETH_INT_RX_STOP))
|
||||
{
|
||||
CME_ETH_PRINTF("ETH_INT_RX_STOP\n");
|
||||
ETH_ClearInt(ETH_INT_RX_STOP);
|
||||
}
|
||||
|
||||
if ((ETH_GetIntStatus(ETH_INT_RX_BUF_UNAVAI)) ||
|
||||
(ETH_GetIntStatus(ETH_INT_RX_COMPLETE_FRAME)))
|
||||
{
|
||||
/* a frame has been received */
|
||||
eth_device_ready(&(cme_eth_device.parent));
|
||||
|
||||
ETH_EnableInt(ETH_INT_RX_COMPLETE_FRAME, FALSE);
|
||||
ETH_EnableInt(ETH_INT_RX_BUF_UNAVAI, FALSE);
|
||||
ETH_ClearInt(ETH_INT_RX_BUF_UNAVAI);
|
||||
ETH_ClearInt(ETH_INT_RX_COMPLETE_FRAME);
|
||||
}
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
|
|
@ -63,13 +63,15 @@
|
|||
#define RT_CONSOLE_DEVICE_NAME "uart2"
|
||||
|
||||
/* SECTION: finsh, a C-Express shell */
|
||||
#define RT_USING_FINSH
|
||||
//#define RT_USING_FINSH
|
||||
/* Using symbol table */
|
||||
#define FINSH_USING_SYMTAB
|
||||
#define FINSH_USING_DESCRIPTION
|
||||
#define FINSH_USING_MSH
|
||||
#define FINSH_USING_MSH_ONLY
|
||||
|
||||
//#define RT_USING_NEWLIB
|
||||
//#define RT_USING_ARM_LIBC
|
||||
#define RT_USING_ARM_LIBC
|
||||
|
||||
/* SECTION: device filesystem */
|
||||
/* #define RT_USING_DFS */
|
||||
|
|
@ -87,7 +89,7 @@
|
|||
#define DFS_FD_MAX 4
|
||||
|
||||
/* SECTION: lwip, a lighwight TCP/IP protocol stack */
|
||||
//#define RT_USING_LWIP
|
||||
#define RT_USING_LWIP
|
||||
/* LwIP uses RT-Thread Memory Management */
|
||||
// #define RT_LWIP_USING_RT_MEM
|
||||
/* Enable ICMP protocol*/
|
||||
|
|
|
|||
Loading…
Reference in New Issue