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Rbb666 2022-07-05 16:59:20 +08:00 committed by guo
parent b9401f5fd4
commit fc5dfaf5c4
158 changed files with 2268 additions and 2470 deletions
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4
bsp/cypress/libraries/HAL_Drivers/SConscript
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@ -19,11 +19,11 @@ if GetDepend(['RT_USING_SERIAL']):
src += ['drv_uart.c']
if GetDepend(['RT_USING_I2C', 'RT_USING_I2C_BITOPS']):
if GetDepend('BSP_USING_I2C1') or GetDepend('BSP_USING_I2C2') or GetDepend('BSP_USING_I2C3') or GetDepend('BSP_USING_I2C4'):
if GetDepend('BSP_USING_I2C1') or GetDepend('BSP_USING_I2C2'):
src += ['drv_soft_i2c.c']
if GetDepend(['RT_USING_ADC']):
src += Glob('drv_adc.c')
src += ['drv_adc.c']
path = [cwd]
path += [cwd + '/config']

2
bsp/cypress/libraries/HAL_Drivers/drv_adc.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/cypress/libraries/HAL_Drivers/drv_log.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/cypress/libraries/HAL_Drivers/drv_uart.h
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@ -5,7 +5,7 @@
*
* Change Logs:
* Date Author Notes
* 2022-06-29 Rbb666 first version
* 2022-06-29 Rbb666 first version
*/
#ifndef __DRV_UART_H__

4
bsp/cypress/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h
View File

@ -320,8 +320,8 @@ extern "C" {
#if defined (CY_USING_HAL)
#define CYBSP_DEBUG_UART_TX (P5_1)
#define CYBSP_D1 CYBSP_DEBUG_UART_TX
#define CYBSP_DEBUG_UART_TX_PORT GPIO_PRT5
#define CYBSP_DEBUG_UART_TX_PIN 1U
#define CYBSP_DEBUG_UART_TX_PORT GPIO_PRT5
#define CYBSP_DEBUG_UART_TX_PIN 1U
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_DEBUG_UART_RTS (P5_2)

2
bsp/cypress/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/cybsp_doc.h
View File

@ -740,7 +740,7 @@ extern "C" {
/**
* \addtogroup group_bsp_pins_capsense Capsense
* \{
* Pins connected to CAPSENSE™ sensors on the board.
* Pins connected to CAPSENSEâ„¢ sensors on the board.
*/
#ifdef CYBSP_CSD_TX

2
bsp/cypress/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/include/cyhal.h
View File

@ -59,7 +59,7 @@
/**
* \addtogroup group_hal HAL Drivers
* This section documents the drivers which form the stable API of the ModusToolbox™ HAL.
* This section documents the drivers which form the stable API of the ModusToolboxâ„¢ HAL.
* In order to remain portable across platforms and HAL versions, applications should
* rely only on functionality documented in this section.
*/

2
bsp/cypress/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/include/cyhal_quaddec.h
View File

@ -41,7 +41,7 @@
* signals. The signals are typically provided by a speed/position feedback system mounted on
* a motor or trackball. The driver allows the user to invoke a callback function when a
* particular event occurs.
* The signals, typically called A and B, are positioned 90° out-of-phase, which results in a Gray
* The signals, typically called A and B, are positioned 90° out-of-phase, which results in a Gray
* code output (a sequence where only one bit changes on each count). It also allows detection of
* direction and relative position. A third optional signal, named index, is used as a reference
* to establish an absolute position once per rotation.

2
bsp/cypress/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/include/cyhal_spi.h
View File

@ -83,7 +83,7 @@
* \section subsection_spi_moreinfor More Information
*
* * <a href="https://github.com/infineon/mtb-example-psoc6-spi-master"><b>mtb-example-psoc6-spi-master</b></a>: This example project demonstrates
* use of SPI (HAL) resource in PSoC® 6 MCU in Master mode to write data to an SPI slave.
* use of SPI (HAL) resource in PSoC® 6 MCU in Master mode to write data to an SPI slave.
*
*/

2
bsp/cypress/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/include/cyhal_tdm.h
View File

@ -96,7 +96,7 @@
*
* <b>Code examples (Github)</b>
* * <a href="https://github.com/infineon/mtb-example-psoc6-tdm" ><b>
PSoC™ 6 MCU: Time Division Multiplexing (TDM)</b></a>
PSoCâ„¢ 6 MCU: Time Division Multiplexing (TDM)</b></a>
*/
#pragma once

2
bsp/cypress/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/include/cyhal_usb_dev.h
View File

@ -84,7 +84,7 @@
* The following section shows how to add endpoint to the USB device and configure the endpoint using
* \ref cyhal_usb_dev_endpoint_add. The interrupts associated with the endpoints are handled by a
* callback function registered using \ref cyhal_usb_dev_register_endpoint_callback.
* The endpoint can also be configured using <a href="https://www.cypress.com/ModusToolboxUSBConfig">ModusToolbox™ USB Configurator</a>
* The endpoint can also be configured using <a href="https://www.cypress.com/ModusToolboxUSBConfig">ModusToolboxâ„¢ USB Configurator</a>
*
* \snippet hal_usb_dev.c snippet_cyhal_usb_dev_endpoint
*/

2
bsp/cypress/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/include_pvt/cyhal_adc_impl.h
View File

@ -37,7 +37,7 @@ extern "C"
* \ingroup group_hal_impl_adc
* \{
* \section group_hal_impl_adc_interconnect Interconnect
* In PSoC™ each ADC has a single input trigger which, when activated, will
* In PSoCâ„¢ each ADC has a single input trigger which, when activated, will
* initiate an ADC scan. Each ADC also has an output trigger which will be
* activated when a scan is completed.
*/

6
bsp/cypress/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/include_pvt/cyhal_clock_impl.h
View File

@ -266,9 +266,9 @@ extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_HF[SRSS_NUM_HFROOT];
#if defined(PERI_PERI_PCLK_PCLK_GROUP_NR)
#define _CYHAL_CLOCK_PERI_GROUPS PERI_PERI_PCLK_PCLK_GROUP_NR
#define _CYHAL_CLOCK_PERI_GROUPS PERI_PERI_PCLK_PCLK_GROUP_NR
#else
#define _CYHAL_CLOCK_PERI_GROUPS 1
#define _CYHAL_CLOCK_PERI_GROUPS 1
#endif
cy_rslt_t _cyhal_clock_allocate_channel(cyhal_clock_t *clock, cyhal_clock_block_t block, const void* funcs);
@ -321,7 +321,7 @@ static inline cy_rslt_t _cyhal_clock_allocate_peri(cyhal_clock_t *clock, cyhal_c
return _cyhal_clock_allocate_channel(clock, block, funcs);
}
#define cyhal_clock_allocate(clock, block) _cyhal_clock_allocate(clock, block)
#define cyhal_clock_allocate(clock, block) _cyhal_clock_allocate(clock, block)
#if defined(__cplusplus)
}

2
bsp/cypress/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/include_pvt/cyhal_interconnect_impl.h
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@ -2,7 +2,7 @@
* \file cyhal_interconnect_impl.h
*
* \brief
* Implementation details for the PSoC™ 4/6 interconnect.
* Implementation details for the PSoCâ„¢ 4/6 interconnect.
*
********************************************************************************
* \copyright

2
bsp/cypress/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/include_pvt/cyhal_pwm_impl.h
View File

@ -38,7 +38,7 @@ extern "C" {
* \ingroup group_hal_impl
* \{
* \section group_hal_impl_pwm_interconnect Interconnect
* In PSoC™ PWM channels can configure multiple input and output triggers
* In PSoCâ„¢ PWM channels can configure multiple input and output triggers
* simultaneously. 1 or more input triggers can be configured to initiate
* different PWM actions (e.g start, stop, reload, etc) with configurable edge
* detection on that incoming signal. Output triggers are based on certain

2
bsp/cypress/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/include_pvt/cyhal_quaddec_impl.h
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@ -38,7 +38,7 @@ extern "C" {
* \ingroup group_hal_impl
* \{
* \section group_hal_impl_quaddec_interconnect Interconnect
* In PSoC™ Quadrature Decoder channels can configure multiple input and output
* In PSoCâ„¢ Quadrature Decoder channels can configure multiple input and output
* triggers simultaneously. 1 or more input triggers can be configured to
* initiate different PWM actions (e.g start, stop, reload, etc) with
* configurable edge detection on that incoming signal. Output triggers are

2
bsp/cypress/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/include_pvt/cyhal_system_impl.h
View File

@ -2,7 +2,7 @@
* \file cyhal_system_impl.h
*
* \brief
* Provides a PSoC™ Specific interface for interacting with the Infineon power
* Provides a PSoCâ„¢ Specific interface for interacting with the Infineon power
* management and system clock configuration. This interface abstracts out the
* chip specific details. If any chip specific functionality is necessary, or
* performance is critical the low level functions can be used directly.

2
bsp/cypress/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/include_pvt/cyhal_timer_impl.h
View File

@ -37,7 +37,7 @@
* range that is supported by \ref cyhal_timer_set_frequency is: 1526 hz -
* 100 Mhz
* \section group_hal_impl_timer_interconnect Interconnect
* In PSoC™ Timer channels can configure multiple input and output triggers
* In PSoCâ„¢ Timer channels can configure multiple input and output triggers
* simultaneously. 1 or more input triggers can be configured to initiate
* different Timer actions (e.g start, stop, reload, etc) with configurable
* edge detection on that incoming signal. Output triggers are based on certain

2
bsp/cypress/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/include_pvt/cyhal_trng_impl.h
View File

@ -2,7 +2,7 @@
* \file cyhal_trng_impl.h
*
* \brief
* Provides an implementation of the ModusToolbox™ TRNG HAL API.
* Provides an implementation of the ModusToolboxâ„¢ TRNG HAL API.
*
********************************************************************************
* \copyright

2
bsp/cypress/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/include_pvt/cyhal_wdt_impl.h
View File

@ -30,7 +30,7 @@
* \addtogroup group_hal_impl_wdt WDT (Watchdog Timer)
* \ingroup group_hal_impl
* \{
* The CAT1 (PSoC™ 6) WDT is only capable of supporting certain timeout ranges below its maximum timeout.
* The CAT1 (PSoCâ„¢ 6) WDT is only capable of supporting certain timeout ranges below its maximum timeout.
* As a result, any unsupported timeouts given to the HAL WDT are rounded up to the nearest supported value.
* The following table describes the unsupported ranges and the timeout values they are rounded to.
*

6
bsp/cypress/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/source/cyhal_audio_common.c
View File

@ -206,7 +206,7 @@ static uint8_t _cyhal_audioss_get_block_from_irqn(_cyhal_system_irq_t irqn)
}
}
#if defined(COMPONENT_CAT2) /* PSoC™ 4 uses a PCLK */
#if defined(COMPONENT_CAT2) /* PSoCâ„¢ 4 uses a PCLK */
#define _CYHAL_AUDIOSS_USES_PCLK
static const en_clk_dst_t _cyhal_audioss_clock[] =
{
@ -576,8 +576,8 @@ cy_rslt_t _cyhal_audioss_init(_cyhal_audioss_t *obj, const _cyhal_audioss_pins_t
mclk_map_rx = (NULL != rx_pins) ? _CYHAL_UTILS_GET_RESOURCE(rx_pins->mclk, cyhal_pin_map_audioss_clk_i2s_if) : NULL;
mclk_map_tx = (NULL != tx_pins) /* If non-null, we know the mclk pins must be the same, so can reuse the rx value */
? ((NULL != mclk_map_rx) ? mclk_map_rx : _CYHAL_UTILS_GET_RESOURCE(tx_pins->mclk, cyhal_pin_map_audioss_clk_i2s_if))
: NULL;
? ((NULL != mclk_map_rx) ? mclk_map_rx : _CYHAL_UTILS_GET_RESOURCE(tx_pins->mclk, cyhal_pin_map_audioss_clk_i2s_if))
: NULL;
uint8_t mclk_rx_dm = CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_CLK_I2S_IF;
#if defined(_CYHAL_AUDIOSS_RX_ENABLED)

118
bsp/cypress/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/source/cyhal_clock.c
View File

@ -2236,7 +2236,7 @@ static cy_rslt_t _cyhal_clock_set_divider_pump(cyhal_clock_t *clock, uint32_t di
Cy_SysClk_ClkPumpSetDivider(divVal);
return CY_RSLT_SUCCESS;
}
#define _cyhal_clock_get_sources_pump _cyhal_clock_get_sources_hf
#define _cyhal_clock_get_sources_pump _cyhal_clock_get_sources_hf
static cy_rslt_t _cyhal_clock_set_source_pump(cyhal_clock_t *clock, const cyhal_clock_t *source)
{
CY_UNUSED_PARAMETER(clock);
@ -2984,64 +2984,64 @@ const void* _cyhal_clock_get_funcs_peripheral(void) { return &FUNCS_EMPTY/*FUNCS
static const cyhal_clock_funcs_t* _cyhal_clock_get_funcs_all(cyhal_clock_block_t block)
{
switch (block)
{
case CYHAL_CLOCK_BLOCK_IMO:
return &FUNCS_IMO;
switch (block)
{
case CYHAL_CLOCK_BLOCK_IMO:
return &FUNCS_IMO;
#if SRSS_ECO_PRESENT
case CYHAL_CLOCK_BLOCK_ECO:
return &FUNCS_ECO;
case CYHAL_CLOCK_BLOCK_ECO:
return &FUNCS_ECO;
#endif
case CYHAL_CLOCK_BLOCK_EXT:
return &FUNCS_EXT;
case CYHAL_CLOCK_BLOCK_EXT:
return &FUNCS_EXT;
#if SRSS_ALTHF_PRESENT
case CYHAL_CLOCK_BLOCK_ALTHF:
return &FUNCS_ALTHF;
case CYHAL_CLOCK_BLOCK_ALTHF:
return &FUNCS_ALTHF;
#endif
#if SRSS_ALTLF_PRESENT
case CYHAL_CLOCK_BLOCK_ALTLF:
return &FUNCS_ALTLF;
case CYHAL_CLOCK_BLOCK_ALTLF:
return &FUNCS_ALTLF;
#endif
case CYHAL_CLOCK_BLOCK_ILO:
return &FUNCS_ILO;
case CYHAL_CLOCK_BLOCK_ILO:
return &FUNCS_ILO;
#if _CYHAL_SRSS_PILO_PRESENT
case CYHAL_CLOCK_BLOCK_PILO:
return &FUNCS_PILO;
case CYHAL_CLOCK_BLOCK_PILO:
return &FUNCS_PILO;
#endif
#if SRSS_BACKUP_PRESENT
case CYHAL_CLOCK_BLOCK_WCO:
return &FUNCS_WCO;
case CYHAL_CLOCK_BLOCK_WCO:
return &FUNCS_WCO;
#endif
#if defined(COMPONENT_CAT1B) || (SRSS_MFO_PRESENT)
case CYHAL_CLOCK_BLOCK_MFO:
return &FUNCS_MFO;
case CYHAL_CLOCK_BLOCK_MFO:
return &FUNCS_MFO;
#endif
case CYHAL_CLOCK_BLOCK_PATHMUX:
return &FUNCS_PATHMUX;
case CYHAL_CLOCK_BLOCK_PATHMUX:
return &FUNCS_PATHMUX;
#if defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1C) || (SRSS_FLL_PRESENT)
case CYHAL_CLOCK_BLOCK_FLL:
return &FUNCS_FLL;
case CYHAL_CLOCK_BLOCK_FLL:
return &FUNCS_FLL;
#endif
case CYHAL_CLOCK_BLOCK_LF:
return &FUNCS_LF;
case CYHAL_CLOCK_BLOCK_LF:
return &FUNCS_LF;
#if defined(COMPONENT_CAT1B) || (SRSS_MFO_PRESENT)
case CYHAL_CLOCK_BLOCK_MF:
return &FUNCS_MF;
case CYHAL_CLOCK_BLOCK_MF:
return &FUNCS_MF;
#endif
case CYHAL_CLOCK_BLOCK_HF:
return &FUNCS_HF;
case CYHAL_CLOCK_BLOCK_PUMP:
return &FUNCS_PUMP;
case CYHAL_CLOCK_BLOCK_BAK:
return &FUNCS_BAK;
case CYHAL_CLOCK_BLOCK_ALT_SYS_TICK:
return &FUNCS_ALT_SYS_TICK;
case CYHAL_CLOCK_BLOCK_PERI:
return &FUNCS_PERI;
case CYHAL_CLOCK_BLOCK_HF:
return &FUNCS_HF;
case CYHAL_CLOCK_BLOCK_PUMP:
return &FUNCS_PUMP;
case CYHAL_CLOCK_BLOCK_BAK:
return &FUNCS_BAK;
case CYHAL_CLOCK_BLOCK_ALT_SYS_TICK:
return &FUNCS_ALT_SYS_TICK;
case CYHAL_CLOCK_BLOCK_PERI:
return &FUNCS_PERI;
#if defined(COMPONENT_CAT1A)
#if (_CYHAL_SRSS_NUM_PLL > 0)
case CYHAL_CLOCK_BLOCK_PLL:
return &FUNCS_PLL;
case CYHAL_CLOCK_BLOCK_PLL:
return &FUNCS_PLL;
#endif
#endif
#if defined(COMPONENT_CAT1C)
@ -3050,42 +3050,42 @@ static const cyhal_clock_funcs_t* _cyhal_clock_get_funcs_all(cyhal_clock_block_t
#endif
#if defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1C)
#if defined(COMPONENT_CAT1A)
case CYHAL_CLOCK_BLOCK_TIMER:
return &FUNCS_TIMER;
case CYHAL_CLOCK_BLOCK_TIMER:
return &FUNCS_TIMER;
#endif
case CYHAL_CLOCK_BLOCK_FAST:
return &FUNCS_FAST;
case CYHAL_CLOCK_BLOCK_SLOW:
return &FUNCS_SLOW;
case CYHAL_CLOCK_BLOCK_FAST:
return &FUNCS_FAST;
case CYHAL_CLOCK_BLOCK_SLOW:
return &FUNCS_SLOW;
#endif
#if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C)
#if (_CYHAL_SRSS_NUM_PLL > 0)
case CYHAL_CLOCK_BLOCK_PLL200:
case CYHAL_CLOCK_BLOCK_PLL200:
return &FUNCS_PLL200;
case CYHAL_CLOCK_BLOCK_PLL400:
return &FUNCS_PLL400;
case CYHAL_CLOCK_BLOCK_PLL400:
return &FUNCS_PLL400;
#endif
#endif
#if defined(COMPONENT_CAT1B)
case CYHAL_CLOCK_BLOCK_IHO:
return &FUNCS_IHO;
case CYHAL_CLOCK_BLOCK_IHO:
return &FUNCS_IHO;
#if SRSS_ECO_PRESENT
case CYHAL_CLOCK_BLOCK_ECO_PRESCALER:
return &FUNCS_ECO_PRESCALER;
case CYHAL_CLOCK_BLOCK_ECO_PRESCALER:
return &FUNCS_ECO_PRESCALER;
#endif
#if SRSS_BACKUP_S40E_LPECO_PRESENT
case CY_SYSCLK_CLKLF_IN_LPECO_PRESCALER:
return &FUNCS_LPECO_PRESCALER;
return &FUNCS_LPECO_PRESCALER;
#endif
#endif
default:
return &FUNCS_PERIPHERAL;
}
default:
return &FUNCS_PERIPHERAL;
}
}
#define _CYHAL_CLOCK_CREATE(x,y) { .block = (CYHAL_CLOCK_BLOCK_##x), .channel = (y), .reserved = false, .funcs = &(FUNCS_##x) }
#define _CYHAL_CLOCK_CREATE(x,y) { .block = (CYHAL_CLOCK_BLOCK_##x), .channel = (y), .reserved = false, .funcs = &(FUNCS_##x) }
const cyhal_clock_t CYHAL_CLOCK_IMO = _CYHAL_CLOCK_CREATE(IMO, 0);
const cyhal_clock_t CYHAL_CLOCK_EXT = _CYHAL_CLOCK_CREATE(EXT, 0);

2
bsp/cypress/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/source/cyhal_dma_dmac.c
View File

@ -534,7 +534,7 @@ cy_rslt_t _cyhal_dma_dmac_configure(cyhal_dma_t *obj, const cyhal_dma_cfg_t *cfg
return CYHAL_DMA_RSLT_ERR_INVALID_TRANSFER_SIZE;
#if defined(CY_IP_M0S8CPUSSV3_DMAC)
// PSoC™ 4 devices do not support automatically disabling the channel on completion
// PSoCâ„¢ 4 devices do not support automatically disabling the channel on completion
if ((cfg->action == CYHAL_DMA_TRANSFER_BURST_DISABLE) ||
(cfg->action == CYHAL_DMA_TRANSFER_FULL_DISABLE))
{

2
bsp/cypress/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/source/cyhal_keyscan.c
View File

@ -29,7 +29,7 @@
* \addtogroup group_hal_impl_keyscan KeyScan
* \ingroup group_hal_impl
* \{
* On PSoC™ devices, the KeyScan peripheral is clocked from the shared source CLK_MF.
* On PSoCâ„¢ devices, the KeyScan peripheral is clocked from the shared source CLK_MF.
* If `NULL` is passed for the `clk` argument to \ref cyhal_keyscan_init, the KeyScan
* HAL will automatically reserve and enable CLK_MF. If the KeyScan driver needs to be
* used in combination with another driver that also requires CLK_MF, use the Clock

2
bsp/cypress/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/source/cyhal_qspi.c
View File

@ -967,7 +967,7 @@ cy_rslt_t cyhal_qspi_init(
CY_ASSERT(NULL != obj);
CY_ASSERT(NULL != pin_set);
/* mode (CPOL and CPHA) are not supported in CAT1 (PSoC™ 6) */
/* mode (CPOL and CPHA) are not supported in CAT1 (PSoCâ„¢ 6) */
CY_UNUSED_PARAMETER(mode);
#if defined(CY_DEVICE_CYW20829)

2
bsp/cypress/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/source/cyhal_quaddec.c
View File

@ -354,7 +354,7 @@ cy_rslt_t cyhal_quaddec_init(cyhal_quaddec_t *obj, cyhal_gpio_t phi_a, cyhal_gpi
if (rslt == CY_RSLT_SUCCESS)
{
#if defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) // already initialized above
obj->tcpwm.inputs[phy_a_idx] = phy_a_src;;
obj->tcpwm.inputs[phy_a_idx] = phy_a_src;;
rslt = cyhal_quaddec_connect_digital(obj, obj->tcpwm.inputs[phy_a_idx], CYHAL_QUADDEC_INPUT_PHI_A);
#else
rslt = _cyhal_quadec_pin_init(obj, phi_a, &(obj->phi_a), CYHAL_SIGNAL_TYPE_LEVEL, CYHAL_QUADDEC_INPUT_PHI_A);

2
bsp/cypress/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/source/cyhal_rtc.c
View File

@ -39,7 +39,7 @@
* \ingroup group_hal_impl
* \{
*
* Internally the CAT1 (PSoC™ 6) RTC only stores the year as a two digit BCD value
* Internally the CAT1 (PSoCâ„¢ 6) RTC only stores the year as a two digit BCD value
* (0-99); no century information is stored. On RTC initialization the HAL must,
* as a result, assume a default century. If cyhal_rtc_write has been called
* with a different century than the default, its value must be stored and that

2
bsp/cypress/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/source/cyhal_sdhc.c
View File

@ -2879,7 +2879,7 @@ cy_rslt_t cyhal_sdio_init(cyhal_sdio_t *obj, cyhal_gpio_t cmd, cyhal_gpio_t clk,
const cyhal_sdio_configurator_t cfg = {
.resource = NULL,
.host_config = &host_config,
.card_config = &card_config,
.card_config = &card_config,
.clock = NULL,
.gpios = {clk, cmd, { data0, data1, data2, data3 } }
};

2
bsp/cypress/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/source/cyhal_spi.c
View File

@ -179,7 +179,7 @@ static cy_rslt_t _cyhal_spi_int_frequency(cyhal_spi_t *obj, uint32_t hz, uint8_t
}
else
{
/* Slave requires such frequency: required_frequency = N / ((0.5 * desired_period) – 20 nsec - tDSI,
/* Slave requires such frequency: required_frequency = N / ((0.5 * desired_period) – 20 nsec - tDSI,
* N is 3 when "Enable Input Glitch Filter" is false and 4 when true.
* tDSI Is external master delay which is assumed to be 16.66 nsec */

5
bsp/cypress/psoc6-cy8cproto-4343w/.config
View File

@ -141,7 +141,7 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_I2C is not set
# CONFIG_RT_USING_PHY is not set
CONFIG_RT_USING_PIN=y
CONFIG_RT_USING_ADC=y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_DAC is not set
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
@ -679,8 +679,7 @@ CONFIG_BSP_USING_USB_TO_USART=y
CONFIG_BSP_USING_GPIO=y
CONFIG_BSP_USING_UART=y
CONFIG_BSP_USING_UART1=y
CONFIG_BSP_USING_ADC=y
CONFIG_BSP_USING_ADC1=y
# CONFIG_BSP_USING_ADC is not set
#
# Board extended module Drivers

28
bsp/cypress/psoc6-cy8cproto-4343w/.project Normal file
View File

@ -0,0 +1,28 @@
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>psoc6-pioneerkit_modus</name>
<comment></comment>
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
<triggers>clean,full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
<triggers>full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>org.eclipse.cdt.core.ccnature</nature>
<nature>com.cypress.studio.app.cymodusnature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
</natures>
</projectDescription>

9
bsp/cypress/psoc6-cy8cproto-4343w/EventRecorderStub.scvd Normal file
View File

@ -0,0 +1,9 @@
<?xml version="1.0" encoding="utf-8"?>
<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
<component name="EventRecorderStub" version="1.0.0"/> <!--name and version of the component-->
<events>
</events>
</component_viewer>

51
bsp/cypress/psoc6-cy8cproto-4343w/applications/main.c
View File

@ -13,7 +13,7 @@
#include "drv_gpio.h"
#define LED_PIN GET_PIN(13, 7)
#define LED_PIN GET_PIN(13, 7)
int main(void)
{
@ -27,52 +27,3 @@ int main(void)
rt_thread_mdelay(1000);
}
}
#define KEY0_PIN_NUM GET_PIN(0, 4)
void btn_test(void *args)
{
rt_kprintf("down button!\n");
}
static void pin_btn_sample(void)
{
rt_pin_mode(KEY0_PIN_NUM, PIN_MODE_INPUT_PULLUP);
rt_pin_attach_irq(KEY0_PIN_NUM, PIN_IRQ_MODE_FALLING, btn_test, RT_NULL);
rt_pin_irq_enable(KEY0_PIN_NUM, PIN_IRQ_ENABLE);
}
MSH_CMD_EXPORT(pin_btn_sample, pin button sample);
#if defined(BSP_USING_ADC1)
static int adc_vol_sample(int argc, char *argv[])
{
rt_adc_device_t adc_dev;
rt_uint32_t value, vol;
rt_err_t ret = RT_EOK;
adc_dev = (rt_adc_device_t)rt_device_find("adc1");
if (adc_dev == RT_NULL)
{
rt_kprintf("adc sample run failed! can't find %s device!\n", "adc1");
return RT_ERROR;
}
ret = rt_adc_enable(adc_dev, 10);
while (1)
{
value = rt_adc_read(adc_dev, 10);
rt_kprintf("the value is :%d \n", value);
vol = value * 330 / (1 << 12);
rt_kprintf("the voltage is :%d.%02d \n", vol / 100, vol % 100);
rt_thread_mdelay(500);
}
return ret;
}
MSH_CMD_EXPORT(adc_vol_sample, adc voltage convert sample);
#endif

4
bsp/cypress/psoc6-cy8cproto-4343w/board/board.h
View File

@ -5,7 +5,7 @@
*
* Change Logs:
* Date Author Notes
* 2022-06-29 Rbb666 first version
* 2022-06-29 Rbb666 first version
*/
#ifndef __BOARD_H__
@ -36,7 +36,7 @@
#define HEAP_END (void*)&__HeapLimit
#endif
#define HEAP_END IFX_SRAM_END
#define HEAP_END IFX_SRAM_END
void cy_bsp_all_init(void);

1108
bsp/cypress/psoc6-cy8cproto-4343w/project.uvoptx
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File diff suppressed because it is too large Load Diff

84
bsp/cypress/psoc6-cy8cproto-4343w/project.uvprojx
View File

@ -11,6 +11,7 @@
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pArmCC>6160000::V6.16::ARMCLANG</pArmCC>
<pCCUsed>6160000::V6.16::ARMCLANG</pCCUsed>
<uAC6>1</uAC6>
<TargetOption>
<TargetCommonOption>
@ -339,7 +340,7 @@
<MiscControls></MiscControls>
<Define>COMPONENT_CAT1A, RT_USING_LIBC, CY_USING_HAL, __CLK_TCK=RT_TICK_PER_SECOND, COMPONENT_BSP_DESIGN_MODUS, IFX_PSOC6_43012, __RTTHREAD__, COMPONENT_CAT1, RT_USING_ARM_LIBC</Define>
<Undefine></Undefine>
<IncludePath>applications;..\..\..\components\libc\compilers\common;..\..\..\components\libc\compilers\common\extension;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\components\dfs\include;..\..\..\components\finsh;.;..\..\..\include;..\libraries\IFX_PSOC6_HAL\capsense;..\libraries\IFX_PSOC6_HAL\core-lib\include;..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\include;..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\include_pvt;..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\COMPONENT_CAT1A\include;..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\include;..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\cmsis\include;..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\devices\COMPONENT_CAT1A\include;..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\devices\COMPONENT_CAT1B\include;..\libraries\IFX_PSOC6_HAL\psoc6cm0p;..\libraries\IFX_PSOC6_HAL\retarget-io;..\libraries\IFX_PSOC6_HAL\TARGET_CY8CKIT-062S2-43012;..\libraries\IFX_PSOC6_HAL\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\posix\io\stdio;..\..\..\components\libc\posix\ipc</IncludePath>
<IncludePath>applications;..\..\..\components\libc\compilers\common;..\..\..\components\libc\compilers\common\extension;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\components\dfs\include;..\..\..\components\finsh;.;..\..\..\include;..\libraries\IFX_PSOC6_HAL\capsense;..\libraries\IFX_PSOC6_HAL\psoc6cm0p;..\libraries\IFX_PSOC6_HAL\retarget-io;..\libraries\IFX_PSOC6_HAL\core-lib\include;..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\include;..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\include_pvt;..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\cmsis\include;..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\include;..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\COMPONENT_CAT1A\include;..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\devices\COMPONENT_CAT1A\include;..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\devices\COMPONENT_CAT1B\include;..\libraries\IFX_PSOC6_HAL\TARGET_CY8CKIT-062S2-43012;..\libraries\IFX_PSOC6_HAL\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\posix\io\stdio;..\..\..\components\libc\posix\ipc</IncludePath>
</VariousControls>
</Cads>
<Aads>
@ -483,11 +484,6 @@
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\ipc\workqueue.c</FilePath>
</File>
<File>
<FileName>adc.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\misc\adc.c</FilePath>
</File>
<File>
<FileName>pin.c</FileName>
<FileType>1</FileType>
@ -513,11 +509,6 @@
<FileType>1</FileType>
<FilePath>board\board.c</FilePath>
</File>
<File>
<FileName>drv_adc.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\HAL_Drivers\drv_adc.c</FilePath>
</File>
<File>
<FileName>drv_common.c</FileName>
<FileType>1</FileType>
@ -659,9 +650,9 @@
<GroupName>Libraries</GroupName>
<Files>
<File>
<FileName>cyhal_adc_sar.c</FileName>
<FileName>psoc6_02_cm0p_sleep.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_adc_sar.c</FilePath>
<FilePath>..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c</FilePath>
</File>
<File>
<FileName>cy_sysint.c</FileName>
@ -674,14 +665,14 @@
<FilePath>..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\COMPONENT_CAT1A\source\triggers\cyhal_triggers_psoc6_02.c</FilePath>
</File>
<File>
<FileName>psoc6_04_cm0p_sleep.c</FileName>
<FileName>cy_retarget_io.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c</FilePath>
<FilePath>..\libraries\IFX_PSOC6_HAL\retarget-io\cy_retarget_io.c</FilePath>
</File>
<File>
<FileName>cyhal_analog_common.c</FileName>
<FileName>psoc6_03_cm0p_sleep.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_analog_common.c</FilePath>
<FilePath>..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c</FilePath>
</File>
<File>
<FileName>cy_scb_i2c.c</FileName>
@ -708,11 +699,6 @@
<FileType>1</FileType>
<FilePath>..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_clock.c</FilePath>
</File>
<File>
<FileName>cyhal_dma_dmac.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_dma_dmac.c</FilePath>
</File>
<File>
<FileName>cy_scb_uart.c</FileName>
<FileType>1</FileType>
@ -728,11 +714,6 @@
<FileType>1</FileType>
<FilePath>..\libraries\IFX_PSOC6_HAL\TARGET_CY8CKIT-062S2-43012\cybsp.c</FilePath>
</File>
<File>
<FileName>cy_dmac.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_dmac.c</FilePath>
</File>
<File>
<FileName>cy_scb_common.c</FileName>
<FileType>1</FileType>
@ -748,6 +729,11 @@
<FileType>1</FileType>
<FilePath>..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_gpio.c</FilePath>
</File>
<File>
<FileName>psoc6_01_cm0p_sleep.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_01_cm0p_sleep.c</FilePath>
</File>
<File>
<FileName>cyhal_system.c</FileName>
<FileType>1</FileType>
@ -758,11 +744,6 @@
<FileType>1</FileType>
<FilePath>..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_ipc_sema.c</FilePath>
</File>
<File>
<FileName>cy_retarget_io.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\IFX_PSOC6_HAL\retarget-io\cy_retarget_io.c</FilePath>
</File>
<File>
<FileName>cyhal_utils_psoc.c</FileName>
<FileType>1</FileType>
@ -774,9 +755,9 @@
<FilePath>..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_utils.c</FilePath>
</File>
<File>
<FileName>psoc6_02_cm0p_sleep.c</FileName>
<FileName>psoc6_04_cm0p_sleep.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c</FilePath>
<FilePath>..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c</FilePath>
</File>
<File>
<FileName>cy_ipc_drv.c</FileName>
@ -828,31 +809,11 @@
<FileType>1</FileType>
<FilePath>..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_sysclk.c</FilePath>
</File>
<File>
<FileName>cyhal_dma.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_dma.c</FilePath>
</File>
<File>
<FileName>cyhal_dma_dw.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_dma_dw.c</FilePath>
</File>
<File>
<FileName>cyhal_syspm.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_syspm.c</FilePath>
</File>
<File>
<FileName>cy_dma.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_dma.c</FilePath>
</File>
<File>
<FileName>psoc6_01_cm0p_sleep.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_01_cm0p_sleep.c</FilePath>
</File>
<File>
<FileName>cycfg_pins.c</FileName>
<FileType>1</FileType>
@ -863,11 +824,6 @@
<FileType>1</FileType>
<FilePath>..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_uart.c</FilePath>
</File>
<File>
<FileName>cy_sar.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_sar.c</FilePath>
</File>
<File>
<FileName>cy_systick.c</FileName>
<FileType>1</FileType>
@ -908,16 +864,6 @@
<FileType>1</FileType>
<FilePath>..\libraries\IFX_PSOC6_HAL\TARGET_CY8CKIT-062S2-43012\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_system.c</FilePath>
</File>
<File>
<FileName>psoc6_03_cm0p_sleep.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c</FilePath>
</File>
<File>
<FileName>cy_sysanalog.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_sysanalog.c</FilePath>
</File>
<File>
<FileName>cycfg_clocks.c</FileName>
<FileType>1</FileType>

3
bsp/cypress/psoc6-cy8cproto-4343w/rtconfig.h
View File

@ -87,7 +87,6 @@
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_PIN
#define RT_USING_ADC
/* Using USB */
@ -200,8 +199,6 @@
#define BSP_USING_GPIO
#define BSP_USING_UART
#define BSP_USING_UART1
#define BSP_USING_ADC
#define BSP_USING_ADC1
/* Board extended module Drivers */