[bsp/stm32] add qspi flash and sdio for openmv h7plus (#5679)

* [console] fix bug of sdram, configure PA7(DRAM_WE) * [bsp/stm32] add qspi flash for openmv * [bsp/stm32] change sram1 to sram2 * [bsp/stm32] add sdio for openmv * [update] update README.md of openmv
2022-03-22 09:39:13 +08:00 · 2022-03-22 09:39:13 +08:00 · f6f6dae2d6
parent b906fe648f
commit f6f6dae2d6
19 changed files with 1362 additions and 217 deletions
--- a/bsp/stm32/stm32h743-openmv-h7plus/.config
+++ b/bsp/stm32/stm32h743-openmv-h7plus/.config
@ -98,6 +98,7 @@ CONFIG_RT_MAIN_THREAD_PRIORITY=10
 # C++ features
 #
 # CONFIG_RT_USING_CPLUSPLUS is not set
+# CONFIG_RT_USING_FAL is not set

 #
 # Command shell
@ -121,7 +122,39 @@ CONFIG_FINSH_ARG_MAX=10
 #
 # Device virtual file system
 #
-# CONFIG_RT_USING_DFS is not set
+CONFIG_RT_USING_DFS=y
+CONFIG_DFS_USING_POSIX=y
+CONFIG_DFS_USING_WORKDIR=y
+CONFIG_DFS_FILESYSTEMS_MAX=4
+CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
+CONFIG_DFS_FD_MAX=16
+# CONFIG_RT_USING_DFS_MNTTABLE is not set
+CONFIG_RT_USING_DFS_ELMFAT=y
+
+#
+# elm-chan's FatFs, Generic FAT Filesystem Module
+#
+CONFIG_RT_DFS_ELM_CODE_PAGE=437
+CONFIG_RT_DFS_ELM_WORD_ACCESS=y
+# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set
+# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
+# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
+CONFIG_RT_DFS_ELM_USE_LFN_3=y
+CONFIG_RT_DFS_ELM_USE_LFN=3
+CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y
+# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set
+# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set
+# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set
+CONFIG_RT_DFS_ELM_LFN_UNICODE=0
+CONFIG_RT_DFS_ELM_MAX_LFN=255
+CONFIG_RT_DFS_ELM_DRIVES=2
+CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=4096
+# CONFIG_RT_DFS_ELM_USE_ERASE is not set
+CONFIG_RT_DFS_ELM_REENTRANT=y
+CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000
+# CONFIG_RT_USING_DFS_DEVFS is not set
+# CONFIG_RT_USING_DFS_ROMFS is not set
+# CONFIG_RT_USING_DFS_RAMFS is not set

 #
 # Device Drivers
@ -146,8 +179,24 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_RT_USING_MTD_NAND is not set
 # CONFIG_RT_USING_PM is not set
 # CONFIG_RT_USING_RTC is not set
-# CONFIG_RT_USING_SDIO is not set
-# CONFIG_RT_USING_SPI is not set
+CONFIG_RT_USING_SDIO=y
+CONFIG_RT_SDIO_STACK_SIZE=512
+CONFIG_RT_SDIO_THREAD_PRIORITY=15
+CONFIG_RT_MMCSD_STACK_SIZE=1024
+CONFIG_RT_MMCSD_THREAD_PREORITY=22
+CONFIG_RT_MMCSD_MAX_PARTITION=16
+# CONFIG_RT_SDIO_DEBUG is not set
+CONFIG_RT_USING_SPI=y
+CONFIG_RT_USING_QSPI=y
+# CONFIG_RT_USING_SPI_MSD is not set
+CONFIG_RT_USING_SFUD=y
+CONFIG_RT_SFUD_USING_SFDP=y
+CONFIG_RT_SFUD_USING_FLASH_INFO_TABLE=y
+CONFIG_RT_SFUD_USING_QSPI=y
+CONFIG_RT_SFUD_SPI_MAX_HZ=50000000
+# CONFIG_RT_DEBUG_SFUD is not set
+# CONFIG_RT_USING_ENC28J60 is not set
+# CONFIG_RT_USING_SPI_WIFI is not set
 # CONFIG_RT_USING_WDT is not set
 # CONFIG_RT_USING_AUDIO is not set
 # CONFIG_RT_USING_SENSOR is not set
@ -172,7 +221,14 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 #
 # POSIX (Portable Operating System Interface) layer
 #
-# CONFIG_RT_USING_POSIX_FS is not set
+CONFIG_RT_USING_POSIX_FS=y
+# CONFIG_RT_USING_POSIX_DEVIO is not set
+# CONFIG_RT_USING_POSIX_STDIO is not set
+# CONFIG_RT_USING_POSIX_POLL is not set
+# CONFIG_RT_USING_POSIX_SELECT is not set
+# CONFIG_RT_USING_POSIX_TERMIOS is not set
+# CONFIG_RT_USING_POSIX_AIO is not set
+# CONFIG_RT_USING_POSIX_MMAN is not set
 # CONFIG_RT_USING_POSIX_DELAY is not set
 # CONFIG_RT_USING_POSIX_CLOCK is not set
 # CONFIG_RT_USING_POSIX_TIMER is not set
@ -193,25 +249,9 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 #
 # Network
 #
-
-#
-# Socket abstraction layer
-#
 # CONFIG_RT_USING_SAL is not set
-
-#
-# Network interface device
-#
 # CONFIG_RT_USING_NETDEV is not set
-
-#
-# light weight TCP/IP stack
-#
 # CONFIG_RT_USING_LWIP is not set
-
-#
-# AT commands
-#
 # CONFIG_RT_USING_AT is not set

 #
@ -241,6 +281,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 #
 # IoT - internet of things
 #
+# CONFIG_PKG_USING_LWIP is not set
 # CONFIG_PKG_USING_LORAWAN_DRIVER is not set
 # CONFIG_PKG_USING_PAHOMQTT is not set
 # CONFIG_PKG_USING_UMQTT is not set
@ -257,6 +298,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_FREEMODBUS is not set
 # CONFIG_PKG_USING_LJSON is not set
 # CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_SIMPLE_XML is not set
 # CONFIG_PKG_USING_NANOPB is not set

 #
@ -296,6 +338,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_JOYLINK is not set
 # CONFIG_PKG_USING_EZ_IOT_OS is not set
 # CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
 # CONFIG_PKG_USING_OTA_DOWNLOADER is not set
 # CONFIG_PKG_USING_IPMSG is not set
 # CONFIG_PKG_USING_LSSDP is not set
@ -478,7 +521,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_CAIRO is not set
 # CONFIG_PKG_USING_PIXMAN is not set
 # CONFIG_PKG_USING_PARTITION is not set
-# CONFIG_PKG_USING_FAL is not set
 # CONFIG_PKG_USING_FLASHDB is not set
 # CONFIG_PKG_USING_SQLITE is not set
 # CONFIG_PKG_USING_RTI is not set
@ -504,7 +546,8 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_ARM_2D is not set
 # CONFIG_PKG_USING_MCUBOOT is not set
 # CONFIG_PKG_USING_TINYUSB is not set
-# CONFIG_PKG_USING_USB_STACK is not set
+# CONFIG_PKG_USING_CHERRYUSB is not set
+# CONFIG_PKG_USING_KMULTI_RTIMER is not set

 #
 # peripheral libraries and drivers
@ -528,6 +571,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_WM_LIBRARIES is not set
 # CONFIG_PKG_USING_KENDRYTE_SDK is not set
 # CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_MULTI_INFRARED is not set
 # CONFIG_PKG_USING_AGILE_BUTTON is not set
 # CONFIG_PKG_USING_AGILE_LED is not set
 # CONFIG_PKG_USING_AT24CXX is not set
@ -584,6 +628,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_SOFT_SERIAL is not set
 # CONFIG_PKG_USING_MB85RS16 is not set
 # CONFIG_PKG_USING_CW2015 is not set
+# CONFIG_PKG_USING_RFM300 is not set

 #
 # AI packages
@ -602,6 +647,10 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # miscellaneous packages
 #

+#
+# project laboratory
+#
+
 #
 # samples: kernel and components samples
 #
@ -634,6 +683,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_CANFESTIVAL is not set
 # CONFIG_PKG_USING_ZLIB is not set
 # CONFIG_PKG_USING_MINIZIP is not set
+# CONFIG_PKG_USING_HEATSHRINK is not set
 # CONFIG_PKG_USING_DSTR is not set
 # CONFIG_PKG_USING_TINYFRAME is not set
 # CONFIG_PKG_USING_KENDRYTE_DEMO is not set
@ -651,6 +701,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_DESIGN_PATTERN is not set
 # CONFIG_PKG_USING_CONTROLLER is not set
 # CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
+# CONFIG_PKG_USING_MFBD is not set
 CONFIG_SOC_FAMILY_STM32=y
 CONFIG_SOC_SERIES_STM32H7=y

@ -668,7 +719,14 @@ CONFIG_BSP_USING_UART1=y
 # CONFIG_BSP_UART1_RX_USING_DMA is not set
 # CONFIG_BSP_USING_UART2 is not set
 # CONFIG_BSP_USING_LPUART1 is not set
-# CONFIG_BSP_USING_SDRAM is not set
+CONFIG_BSP_USING_QSPI=y
 # CONFIG_BSP_USING_CRC is not set
 # CONFIG_BSP_USING_RNG is not set
 # CONFIG_BSP_USING_UDID is not set
+
+#
+# Onboard Peripheral Drivers
+#
+CONFIG_BSP_USING_SDRAM=y
+# CONFIG_BSP_USING_QSPI_FLASH is not set
+# CONFIG_BSP_USING_SDMMC is not set
--- a/bsp/stm32/stm32h743-openmv-h7plus/README.md
+++ b/bsp/stm32/stm32h743-openmv-h7plus/README.md
@ -38,8 +38,10 @@ OPENMV4-H7-PLUS 是 OPENMV公司推出的一款针对 STM32H7系列设计的 Cor
 | **片上外设**      | **支持情况** | **备注**                              |
 | :----------------- | :----------: | :------------------------------------- |
 | GPIO              |     支持     |                                        |
-| UART              |     支持     | UART1(PB14 TX)(PB15 RX) |
+| USART             |     支持     | USART1(PB14 TX)(PB15 RX) |
 | SDRAM | 支持 | IS42S32800  BANK1 |
+| QSPI FLASH | 支持 | W25Q256JV |
+| SDIO | 支持 | USD-1040310811 |

 ## 使用说明

@ -70,9 +72,9 @@ OPENMV4-H7-PLUS 是 OPENMV公司推出的一款针对 STM32H7系列设计的 Cor

 #### 运行结果

-下载程序成功之后，系统会自动运行，蓝色的 LED_R 以 500MS 周期闪烁。
+下载程序成功之后，系统会自动运行，红色的 LED_R 以 500MS 周期闪烁。

-连接开发板ST-LINK到 PC , 会发现有串口, 在终端工具里打开相应的串口（115200-8-1-N）, 复位设备后，可以看到 RT-Thread 的输出信息:
+串口通信需要使用USB转TTL连接USART1。在终端工具里打开相应的串口（115200-8-1-N）, 复位设备后，可以看到 RT-Thread 的输出信息:

 ```bash
 \ | /
--- a/bsp/stm32/stm32h743-openmv-h7plus/applications/main.c
+++ b/bsp/stm32/stm32h743-openmv-h7plus/applications/main.c
@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2021, RT-Thread Development Team
+ * Copyright (c) 2006-2022, RT-Thread Development Team
 *
 * SPDX-License-Identifier: Apache-2.0
 *
--- a/bsp/stm32/stm32h743-openmv-h7plus/board/CubeMX_Config/.mxproject
+++ b/bsp/stm32/stm32h743-openmv-h7plus/board/CubeMX_Config/.mxproject
--- a/bsp/stm32/stm32h743-openmv-h7plus/board/CubeMX_Config/Core/Inc/stm32h7xx_hal_conf.h
+++ b/bsp/stm32/stm32h743-openmv-h7plus/board/CubeMX_Config/Core/Inc/stm32h7xx_hal_conf.h
@ -64,12 +64,12 @@
 /* #define HAL_IWDG_MODULE_ENABLED   */
 /* #define HAL_LPTIM_MODULE_ENABLED   */
 /* #define HAL_LTDC_MODULE_ENABLED   */
-/* #define HAL_QSPI_MODULE_ENABLED   */
+#define HAL_QSPI_MODULE_ENABLED
 /* #define HAL_RAMECC_MODULE_ENABLED   */
 /* #define HAL_RNG_MODULE_ENABLED   */
 /* #define HAL_RTC_MODULE_ENABLED   */
 /* #define HAL_SAI_MODULE_ENABLED   */
-/* #define HAL_SD_MODULE_ENABLED   */
+#define HAL_SD_MODULE_ENABLED
 /* #define HAL_MMC_MODULE_ENABLED   */
 /* #define HAL_SPDIFRX_MODULE_ENABLED   */
 /* #define HAL_SPI_MODULE_ENABLED   */
@ -168,7 +168,7 @@
 #define  TICK_INT_PRIORITY            (15UL) /*!< tick interrupt priority */
 #define  USE_RTOS                     0
 #define  USE_SD_TRANSCEIVER           0U               /*!< use uSD Transceiver */
-#define  USE_SPI_CRC	              0U               /*!< use CRC in SPI */
+#define  USE_SPI_CRC                  0U               /*!< use CRC in SPI */

 #define  USE_HAL_ADC_REGISTER_CALLBACKS     0U /* ADC register callback disabled     */
 #define  USE_HAL_CEC_REGISTER_CALLBACKS     0U /* CEC register callback disabled     */
--- a/bsp/stm32/stm32h743-openmv-h7plus/board/CubeMX_Config/Core/Inc/stm32h7xx_it.h
+++ b/bsp/stm32/stm32h743-openmv-h7plus/board/CubeMX_Config/Core/Inc/stm32h7xx_it.h
@ -55,6 +55,7 @@ void SVC_Handler(void);
 void DebugMon_Handler(void);
 void PendSV_Handler(void);
 void SysTick_Handler(void);
+void SDMMC1_IRQHandler(void);
 /* USER CODE BEGIN EFP */

 /* USER CODE END EFP */
--- a/bsp/stm32/stm32h743-openmv-h7plus/board/CubeMX_Config/Core/Src/main.c
+++ b/bsp/stm32/stm32h743-openmv-h7plus/board/CubeMX_Config/Core/Src/main.c
@ -40,6 +40,10 @@

 /* Private variables ---------------------------------------------------------*/

+QSPI_HandleTypeDef hqspi;
+
+SD_HandleTypeDef hsd1;
+
 UART_HandleTypeDef huart1;

 SDRAM_HandleTypeDef hsdram1;
@ -53,6 +57,8 @@ void SystemClock_Config(void);
 static void MX_GPIO_Init(void);
 static void MX_USART1_UART_Init(void);
 static void MX_FMC_Init(void);
+static void MX_QUADSPI_Init(void);
+static void MX_SDMMC1_SD_Init(void);
 /* USER CODE BEGIN PFP */

 /* USER CODE END PFP */
@ -72,6 +78,12 @@ int main(void)

  /* USER CODE END 1 */

+  /* Enable I-Cache---------------------------------------------------------*/
+  SCB_EnableICache();
+
+  /* Enable D-Cache---------------------------------------------------------*/
+  SCB_EnableDCache();
+
  /* MCU Configuration--------------------------------------------------------*/

  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
@ -92,6 +104,8 @@ int main(void)
  MX_GPIO_Init();
  MX_USART1_UART_Init();
  MX_FMC_Init();
+  MX_QUADSPI_Init();
+  MX_SDMMC1_SD_Init();
  /* USER CODE BEGIN 2 */

  /* USER CODE END 2 */
@ -134,7 +148,7 @@ void SystemClock_Config(void)
  RCC_OscInitStruct.PLL.PLLM = 3;
  RCC_OscInitStruct.PLL.PLLN = 200;
  RCC_OscInitStruct.PLL.PLLP = 2;
-  RCC_OscInitStruct.PLL.PLLQ = 2;
+  RCC_OscInitStruct.PLL.PLLQ = 4;
  RCC_OscInitStruct.PLL.PLLR = 2;
  RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
  RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
@ -162,6 +176,72 @@ void SystemClock_Config(void)
  }
 }

+/**
+  * @brief QUADSPI Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_QUADSPI_Init(void)
+{
+
+  /* USER CODE BEGIN QUADSPI_Init 0 */
+
+  /* USER CODE END QUADSPI_Init 0 */
+
+  /* USER CODE BEGIN QUADSPI_Init 1 */
+
+  /* USER CODE END QUADSPI_Init 1 */
+  /* QUADSPI parameter configuration*/
+  hqspi.Instance = QUADSPI;
+  hqspi.Init.ClockPrescaler = 1;
+  hqspi.Init.FifoThreshold = 3;
+  hqspi.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE;
+  hqspi.Init.FlashSize = 24;
+  hqspi.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_2_CYCLE;
+  hqspi.Init.ClockMode = QSPI_CLOCK_MODE_0;
+  hqspi.Init.FlashID = QSPI_FLASH_ID_1;
+  hqspi.Init.DualFlash = QSPI_DUALFLASH_DISABLE;
+  if (HAL_QSPI_Init(&hqspi) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN QUADSPI_Init 2 */
+
+  /* USER CODE END QUADSPI_Init 2 */
+
+}
+
+/**
+  * @brief SDMMC1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_SDMMC1_SD_Init(void)
+{
+
+  /* USER CODE BEGIN SDMMC1_Init 0 */
+
+  /* USER CODE END SDMMC1_Init 0 */
+
+  /* USER CODE BEGIN SDMMC1_Init 1 */
+
+  /* USER CODE END SDMMC1_Init 1 */
+  hsd1.Instance = SDMMC1;
+  hsd1.Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING;
+  hsd1.Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE;
+  hsd1.Init.BusWide = SDMMC_BUS_WIDE_4B;
+  hsd1.Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;
+  hsd1.Init.ClockDiv = 4;
+  if (HAL_SD_Init(&hsd1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN SDMMC1_Init 2 */
+
+  /* USER CODE END SDMMC1_Init 2 */
+
+}
+
 /**
  * @brief USART1 Initialization Function
  * @param None
@ -236,7 +316,7 @@ static void MX_FMC_Init(void)
  hsdram1.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_2;
  hsdram1.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
  hsdram1.Init.SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2;
-  hsdram1.Init.ReadBurst = FMC_SDRAM_RBURST_DISABLE;
+  hsdram1.Init.ReadBurst = FMC_SDRAM_RBURST_ENABLE;
  hsdram1.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0;
  /* SdramTiming */
  SdramTiming.LoadToActiveDelay = 2;
@ -268,12 +348,13 @@ static void MX_GPIO_Init(void)

  /* GPIO Ports Clock Enable */
  __HAL_RCC_GPIOE_CLK_ENABLE();
+  __HAL_RCC_GPIOC_CLK_ENABLE();
  __HAL_RCC_GPIOG_CLK_ENABLE();
  __HAL_RCC_GPIOD_CLK_ENABLE();
  __HAL_RCC_GPIOI_CLK_ENABLE();
  __HAL_RCC_GPIOH_CLK_ENABLE();
  __HAL_RCC_GPIOF_CLK_ENABLE();
-  __HAL_RCC_GPIOC_CLK_ENABLE();
+  __HAL_RCC_GPIOA_CLK_ENABLE();
  __HAL_RCC_GPIOB_CLK_ENABLE();

  /*Configure GPIO pin Output Level */
--- a/bsp/stm32/stm32h743-openmv-h7plus/board/CubeMX_Config/Core/Src/stm32h7xx_hal_msp.c
+++ b/bsp/stm32/stm32h743-openmv-h7plus/board/CubeMX_Config/Core/Src/stm32h7xx_hal_msp.c
@ -77,6 +77,207 @@ void HAL_MspInit(void)
  /* USER CODE END MspInit 1 */
 }

+/**
+* @brief QSPI MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hqspi: QSPI handle pointer
+* @retval None
+*/
+void HAL_QSPI_MspInit(QSPI_HandleTypeDef* hqspi)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+  if(hqspi->Instance==QUADSPI)
+  {
+  /* USER CODE BEGIN QUADSPI_MspInit 0 */
+
+  /* USER CODE END QUADSPI_MspInit 0 */
+  /** Initializes the peripherals clock
+  */
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_QSPI;
+    PeriphClkInitStruct.QspiClockSelection = RCC_QSPICLKSOURCE_D1HCLK;
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    /* Peripheral clock enable */
+    __HAL_RCC_QSPI_CLK_ENABLE();
+
+    __HAL_RCC_GPIOG_CLK_ENABLE();
+    __HAL_RCC_GPIOF_CLK_ENABLE();
+    /**QUADSPI GPIO Configuration
+    PG6     ------> QUADSPI_BK1_NCS
+    PF7     ------> QUADSPI_BK1_IO2
+    PF6     ------> QUADSPI_BK1_IO3
+    PF10     ------> QUADSPI_CLK
+    PF9     ------> QUADSPI_BK1_IO1
+    PF8     ------> QUADSPI_BK1_IO0
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_6;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI;
+    HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_6|GPIO_PIN_10;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI;
+    HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_8;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI;
+    HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN QUADSPI_MspInit 1 */
+
+  /* USER CODE END QUADSPI_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief QSPI MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hqspi: QSPI handle pointer
+* @retval None
+*/
+void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef* hqspi)
+{
+  if(hqspi->Instance==QUADSPI)
+  {
+  /* USER CODE BEGIN QUADSPI_MspDeInit 0 */
+
+  /* USER CODE END QUADSPI_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_QSPI_CLK_DISABLE();
+
+    /**QUADSPI GPIO Configuration
+    PG6     ------> QUADSPI_BK1_NCS
+    PF7     ------> QUADSPI_BK1_IO2
+    PF6     ------> QUADSPI_BK1_IO3
+    PF10     ------> QUADSPI_CLK
+    PF9     ------> QUADSPI_BK1_IO1
+    PF8     ------> QUADSPI_BK1_IO0
+    */
+    HAL_GPIO_DeInit(GPIOG, GPIO_PIN_6);
+
+    HAL_GPIO_DeInit(GPIOF, GPIO_PIN_7|GPIO_PIN_6|GPIO_PIN_10|GPIO_PIN_9
+                          |GPIO_PIN_8);
+
+  /* USER CODE BEGIN QUADSPI_MspDeInit 1 */
+
+  /* USER CODE END QUADSPI_MspDeInit 1 */
+  }
+
+}
+
+/**
+* @brief SD MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hsd: SD handle pointer
+* @retval None
+*/
+void HAL_SD_MspInit(SD_HandleTypeDef* hsd)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+  if(hsd->Instance==SDMMC1)
+  {
+  /* USER CODE BEGIN SDMMC1_MspInit 0 */
+
+  /* USER CODE END SDMMC1_MspInit 0 */
+  /** Initializes the peripherals clock
+  */
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SDMMC;
+    PeriphClkInitStruct.SdmmcClockSelection = RCC_SDMMCCLKSOURCE_PLL;
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    /* Peripheral clock enable */
+    __HAL_RCC_SDMMC1_CLK_ENABLE();
+
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+    __HAL_RCC_GPIOD_CLK_ENABLE();
+    /**SDMMC1 GPIO Configuration
+    PC12     ------> SDMMC1_CK
+    PC11     ------> SDMMC1_D3
+    PC10     ------> SDMMC1_D2
+    PD2     ------> SDMMC1_CMD
+    PC9     ------> SDMMC1_D1
+    PC8     ------> SDMMC1_D0
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_9
+                          |GPIO_PIN_8;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF12_SDIO1;
+    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_2;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF12_SDIO1;
+    HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+    /* SDMMC1 interrupt Init */
+    HAL_NVIC_SetPriority(SDMMC1_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(SDMMC1_IRQn);
+  /* USER CODE BEGIN SDMMC1_MspInit 1 */
+
+  /* USER CODE END SDMMC1_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief SD MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hsd: SD handle pointer
+* @retval None
+*/
+void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd)
+{
+  if(hsd->Instance==SDMMC1)
+  {
+  /* USER CODE BEGIN SDMMC1_MspDeInit 0 */
+
+  /* USER CODE END SDMMC1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_SDMMC1_CLK_DISABLE();
+
+    /**SDMMC1 GPIO Configuration
+    PC12     ------> SDMMC1_CK
+    PC11     ------> SDMMC1_D3
+    PC10     ------> SDMMC1_D2
+    PD2     ------> SDMMC1_CMD
+    PC9     ------> SDMMC1_D1
+    PC8     ------> SDMMC1_D0
+    */
+    HAL_GPIO_DeInit(GPIOC, GPIO_PIN_12|GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_9
+                          |GPIO_PIN_8);
+
+    HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2);
+
+    /* SDMMC1 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(SDMMC1_IRQn);
+  /* USER CODE BEGIN SDMMC1_MspDeInit 1 */
+
+  /* USER CODE END SDMMC1_MspDeInit 1 */
+  }
+
+}
+
 /**
 * @brief UART MSP Initialization
 * This function configures the hardware resources used in this example
@ -202,7 +403,6 @@ static void HAL_FMC_MspInit(void){
  PG8   ------> FMC_SDCLK
  PF3   ------> FMC_A3
  PF4   ------> FMC_A4
-  PH5   ------> FMC_SDNWE
  PF5   ------> FMC_A5
  PH12   ------> FMC_D20
  PG5   ------> FMC_BA1
@ -228,6 +428,7 @@ static void HAL_FMC_MspInit(void){
  PE14   ------> FMC_D11
  PD9   ------> FMC_D14
  PD8   ------> FMC_D13
+  PA7   ------> FMC_SDNWE
  PF11   ------> FMC_SDNRAS
  PF14   ------> FMC_A8
  PE7   ------> FMC_D4
@ -269,9 +470,8 @@ static void HAL_FMC_MspInit(void){
  GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
  HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);

-  GPIO_InitStruct.Pin = GPIO_PIN_15|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_5
-                          |GPIO_PIN_12|GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_8
-                          |GPIO_PIN_9;
+  GPIO_InitStruct.Pin = GPIO_PIN_15|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_12
+                          |GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_8|GPIO_PIN_9;
  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
  GPIO_InitStruct.Pull = GPIO_PULLUP;
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
@ -294,6 +494,13 @@ static void HAL_FMC_MspInit(void){
  GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);

+  GPIO_InitStruct.Pin = GPIO_PIN_7;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_PULLUP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
  /* USER CODE BEGIN FMC_MspInit 1 */

  /* USER CODE END FMC_MspInit 1 */
@ -347,7 +554,6 @@ static void HAL_FMC_MspDeInit(void){
  PG8   ------> FMC_SDCLK
  PF3   ------> FMC_A3
  PF4   ------> FMC_A4
-  PH5   ------> FMC_SDNWE
  PF5   ------> FMC_A5
  PH12   ------> FMC_D20
  PG5   ------> FMC_BA1
@ -373,6 +579,7 @@ static void HAL_FMC_MspDeInit(void){
  PE14   ------> FMC_D11
  PD9   ------> FMC_D14
  PD8   ------> FMC_D13
+  PA7   ------> FMC_SDNWE
  PF11   ------> FMC_SDNRAS
  PF14   ------> FMC_A8
  PE7   ------> FMC_D4
@ -394,9 +601,8 @@ static void HAL_FMC_MspDeInit(void){
                          |GPIO_PIN_2|GPIO_PIN_9|GPIO_PIN_4|GPIO_PIN_1
                          |GPIO_PIN_10|GPIO_PIN_0);

-  HAL_GPIO_DeInit(GPIOH, GPIO_PIN_15|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_5
-                          |GPIO_PIN_12|GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_8
-                          |GPIO_PIN_9);
+  HAL_GPIO_DeInit(GPIOH, GPIO_PIN_15|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_12
+                          |GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_8|GPIO_PIN_9);

  HAL_GPIO_DeInit(GPIOF, GPIO_PIN_0|GPIO_PIN_2|GPIO_PIN_1|GPIO_PIN_3
                          |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_13|GPIO_PIN_12
@ -404,6 +610,8 @@ static void HAL_FMC_MspDeInit(void){

  HAL_GPIO_DeInit(GPIOC, GPIO_PIN_4|GPIO_PIN_5);

+  HAL_GPIO_DeInit(GPIOA, GPIO_PIN_7);
+
  /* USER CODE BEGIN FMC_MspDeInit 1 */

  /* USER CODE END FMC_MspDeInit 1 */
--- a/bsp/stm32/stm32h743-openmv-h7plus/board/CubeMX_Config/CubeMX_Config.ioc
+++ b/bsp/stm32/stm32h743-openmv-h7plus/board/CubeMX_Config/CubeMX_Config.ioc
@ -1,4 +1,7 @@
 #MicroXplorer Configuration settings - do not modify
+CORTEX_M7.CPU_DCache=Enabled
+CORTEX_M7.CPU_ICache=Enabled
+CORTEX_M7.IPParameters=CPU_ICache,CPU_DCache
 FMC.BankMapConfig=FMC_SWAPBMAP_DISABLE
 FMC.CASLatency1=FMC_SDRAM_CAS_LATENCY_2
 FMC.ColumnBitsNumber1=FMC_SDRAM_COLUMN_BITS_NUM_9
@ -15,95 +18,115 @@ FMC.WriteRecoveryTime1=3
 File.Version=6
 GPIO.groupedBy=Group By Peripherals
 KeepUserPlacement=false
+Mcu.CPN=STM32H743IIK6
 Mcu.Family=STM32H7
 Mcu.IP0=CORTEX_M7
 Mcu.IP1=FMC
 Mcu.IP2=NVIC
-Mcu.IP3=RCC
-Mcu.IP4=SYS
-Mcu.IP5=USART1
-Mcu.IPNb=6
+Mcu.IP3=QUADSPI
+Mcu.IP4=RCC
+Mcu.IP5=SDMMC1
+Mcu.IP6=SYS
+Mcu.IP7=USART1
+Mcu.IPNb=8
 Mcu.Name=STM32H743IIKx
 Mcu.Package=UFBGA176
 Mcu.Pin0=PE1
 Mcu.Pin1=PE0
-Mcu.Pin10=PI9
-Mcu.Pin11=PI4
-Mcu.Pin12=PH15
-Mcu.Pin13=PI1
-Mcu.Pin14=PF0
-Mcu.Pin15=PI10
-Mcu.Pin16=PH13
-Mcu.Pin17=PH14
-Mcu.Pin18=PI0
-Mcu.Pin19=PH0-OSC_IN (PH0)
-Mcu.Pin2=PG15
-Mcu.Pin20=PH1-OSC_OUT (PH1)
-Mcu.Pin21=PF2
-Mcu.Pin22=PF1
-Mcu.Pin23=PG8
-Mcu.Pin24=PF3
-Mcu.Pin25=PF4
-Mcu.Pin26=PH5
-Mcu.Pin27=PF5
-Mcu.Pin28=PH12
-Mcu.Pin29=PG5
-Mcu.Pin3=PD0
-Mcu.Pin30=PG4
-Mcu.Pin31=PH11
-Mcu.Pin32=PH10
-Mcu.Pin33=PD15
-Mcu.Pin34=PC0
-Mcu.Pin35=PG1
-Mcu.Pin36=PH8
-Mcu.Pin37=PH9
-Mcu.Pin38=PD14
-Mcu.Pin39=PC4
-Mcu.Pin4=PI7
-Mcu.Pin40=PF13
-Mcu.Pin41=PG0
-Mcu.Pin42=PE13
-Mcu.Pin43=PD10
-Mcu.Pin44=PC5
-Mcu.Pin45=PF12
-Mcu.Pin46=PF15
-Mcu.Pin47=PE8
-Mcu.Pin48=PE9
-Mcu.Pin49=PE11
-Mcu.Pin5=PI6
-Mcu.Pin50=PE14
-Mcu.Pin51=PD9
-Mcu.Pin52=PD8
-Mcu.Pin53=PF11
-Mcu.Pin54=PF14
-Mcu.Pin55=PE7
-Mcu.Pin56=PE10
-Mcu.Pin57=PE12
-Mcu.Pin58=PE15
-Mcu.Pin59=PB14
-Mcu.Pin6=PI5
-Mcu.Pin60=PB15
-Mcu.Pin61=VP_SYS_VS_Systick
-Mcu.Pin7=PD1
-Mcu.Pin8=PI3
-Mcu.Pin9=PI2
-Mcu.PinsNb=62
+Mcu.Pin10=PD1
+Mcu.Pin11=PI3
+Mcu.Pin12=PI2
+Mcu.Pin13=PI9
+Mcu.Pin14=PI4
+Mcu.Pin15=PD2
+Mcu.Pin16=PH15
+Mcu.Pin17=PI1
+Mcu.Pin18=PF0
+Mcu.Pin19=PI10
+Mcu.Pin2=PC12
+Mcu.Pin20=PH13
+Mcu.Pin21=PH14
+Mcu.Pin22=PI0
+Mcu.Pin23=PC9
+Mcu.Pin24=PH0-OSC_IN (PH0)
+Mcu.Pin25=PC8
+Mcu.Pin26=PH1-OSC_OUT (PH1)
+Mcu.Pin27=PF2
+Mcu.Pin28=PF1
+Mcu.Pin29=PG8
+Mcu.Pin3=PG15
+Mcu.Pin30=PF3
+Mcu.Pin31=PF4
+Mcu.Pin32=PG6
+Mcu.Pin33=PF7
+Mcu.Pin34=PF6
+Mcu.Pin35=PF5
+Mcu.Pin36=PH12
+Mcu.Pin37=PG5
+Mcu.Pin38=PG4
+Mcu.Pin39=PF10
+Mcu.Pin4=PD0
+Mcu.Pin40=PF9
+Mcu.Pin41=PF8
+Mcu.Pin42=PH11
+Mcu.Pin43=PH10
+Mcu.Pin44=PD15
+Mcu.Pin45=PC0
+Mcu.Pin46=PG1
+Mcu.Pin47=PH8
+Mcu.Pin48=PH9
+Mcu.Pin49=PD14
+Mcu.Pin5=PC11
+Mcu.Pin50=PC4
+Mcu.Pin51=PF13
+Mcu.Pin52=PG0
+Mcu.Pin53=PE13
+Mcu.Pin54=PD10
+Mcu.Pin55=PC5
+Mcu.Pin56=PF12
+Mcu.Pin57=PF15
+Mcu.Pin58=PE8
+Mcu.Pin59=PE9
+Mcu.Pin6=PC10
+Mcu.Pin60=PE11
+Mcu.Pin61=PE14
+Mcu.Pin62=PD9
+Mcu.Pin63=PD8
+Mcu.Pin64=PA7
+Mcu.Pin65=PF11
+Mcu.Pin66=PF14
+Mcu.Pin67=PE7
+Mcu.Pin68=PE10
+Mcu.Pin69=PE12
+Mcu.Pin7=PI7
+Mcu.Pin70=PE15
+Mcu.Pin71=PB14
+Mcu.Pin72=PB15
+Mcu.Pin73=VP_SYS_VS_Systick
+Mcu.Pin8=PI6
+Mcu.Pin9=PI5
+Mcu.PinsNb=74
 Mcu.ThirdPartyNb=0
 Mcu.UserConstants=
 Mcu.UserName=STM32H743IIKx
 MxCube.Version=6.4.0
 MxDb.Version=DB.6.0.40
-NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
-NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
 NVIC.ForceEnableDMAVector=true
-NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
-NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
-NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
-NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
 NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
-NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
-NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true
-NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SDMMC1_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
+NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
+PA7.GPIOParameters=GPIO_PuPd
+PA7.GPIO_PuPd=GPIO_PULLUP
+PA7.Locked=true
+PA7.Signal=FMC_SDNWE
 PB14.Locked=true
 PB14.Mode=Asynchronous
 PB14.Signal=USART1_TX
@ -114,6 +137,12 @@ PC0.GPIOParameters=GPIO_Label
 PC0.GPIO_Label=LED_RED
 PC0.Locked=true
 PC0.Signal=GPIO_Output
+PC10.Mode=SD_4_bits_Wide_bus
+PC10.Signal=SDMMC1_D2
+PC11.Mode=SD_4_bits_Wide_bus
+PC11.Signal=SDMMC1_D3
+PC12.Mode=SD_4_bits_Wide_bus
+PC12.Signal=SDMMC1_CK
 PC4.GPIOParameters=GPIO_PuPd
 PC4.GPIO_PuPd=GPIO_PULLUP
 PC4.Locked=true
@ -124,6 +153,10 @@ PC5.GPIO_PuPd=GPIO_PULLUP
 PC5.Locked=true
 PC5.Mode=SdramChipSelect1_1
 PC5.Signal=FMC_SDCKE0
+PC8.Mode=SD_4_bits_Wide_bus
+PC8.Signal=SDMMC1_D0
+PC9.Mode=SD_4_bits_Wide_bus
+PC9.Signal=SDMMC1_D1
 PD0.GPIOParameters=GPIO_PuPd
 PD0.GPIO_PuPd=GPIO_PULLUP
 PD0.Signal=FMC_D2_DA2
@ -139,6 +172,8 @@ PD14.Signal=FMC_D0_DA0
 PD15.GPIOParameters=GPIO_PuPd
 PD15.GPIO_PuPd=GPIO_PULLUP
 PD15.Signal=FMC_D1_DA1
+PD2.Mode=SD_4_bits_Wide_bus
+PD2.Signal=SDMMC1_CMD
 PD8.GPIOParameters=GPIO_PuPd
 PD8.GPIO_PuPd=GPIO_PULLUP
 PD8.Signal=FMC_D13_DA13
@ -184,6 +219,11 @@ PF0.Signal=FMC_A0
 PF1.GPIOParameters=GPIO_PuPd
 PF1.GPIO_PuPd=GPIO_PULLUP
 PF1.Signal=FMC_A1
+PF10.GPIOParameters=GPIO_Speed
+PF10.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PF10.Locked=true
+PF10.Mode=Single Bank 1
+PF10.Signal=QUADSPI_CLK
 PF11.GPIOParameters=GPIO_PuPd
 PF11.GPIO_PuPd=GPIO_PULLUP
 PF11.Signal=FMC_SDNRAS
@ -211,6 +251,26 @@ PF4.Signal=FMC_A4
 PF5.GPIOParameters=GPIO_PuPd
 PF5.GPIO_PuPd=GPIO_PULLUP
 PF5.Signal=FMC_A5
+PF6.GPIOParameters=GPIO_Speed
+PF6.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PF6.Locked=true
+PF6.Mode=Single Bank 1
+PF6.Signal=QUADSPI_BK1_IO3
+PF7.GPIOParameters=GPIO_Speed
+PF7.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PF7.Locked=true
+PF7.Mode=Single Bank 1
+PF7.Signal=QUADSPI_BK1_IO2
+PF8.GPIOParameters=GPIO_Speed
+PF8.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PF8.Locked=true
+PF8.Mode=Single Bank 1
+PF8.Signal=QUADSPI_BK1_IO0
+PF9.GPIOParameters=GPIO_Speed
+PF9.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PF9.Locked=true
+PF9.Mode=Single Bank 1
+PF9.Signal=QUADSPI_BK1_IO1
 PG0.GPIOParameters=GPIO_PuPd
 PG0.GPIO_PuPd=GPIO_PULLUP
 PG0.Signal=FMC_A10
@ -226,6 +286,11 @@ PG4.Signal=FMC_A14_BA0
 PG5.GPIOParameters=GPIO_PuPd
 PG5.GPIO_PuPd=GPIO_PULLUP
 PG5.Signal=FMC_A15_BA1
+PG6.GPIOParameters=GPIO_PuPd
+PG6.GPIO_PuPd=GPIO_PULLUP
+PG6.Locked=true
+PG6.Mode=Single Bank 1
+PG6.Signal=QUADSPI_BK1_NCS
 PG8.GPIOParameters=GPIO_PuPd
 PG8.GPIO_PuPd=GPIO_PULLUP
 PG8.Signal=FMC_SDCLK
@ -251,9 +316,6 @@ PH14.Signal=FMC_D22
 PH15.GPIOParameters=GPIO_PuPd
 PH15.GPIO_PuPd=GPIO_PULLUP
 PH15.Signal=FMC_D23
-PH5.GPIOParameters=GPIO_PuPd
-PH5.GPIO_PuPd=GPIO_PULLUP
-PH5.Signal=FMC_SDNWE
 PH8.GPIOParameters=GPIO_PuPd
 PH8.GPIO_PuPd=GPIO_PULLUP
 PH8.Signal=FMC_D16
@ -306,7 +368,7 @@ ProjectManager.FreePins=false
 ProjectManager.HalAssertFull=false
 ProjectManager.HeapSize=0x200
 ProjectManager.KeepUserCode=true
-ProjectManager.LastFirmware=false
+ProjectManager.LastFirmware=true
 ProjectManager.LibraryCopy=1
 ProjectManager.MainLocation=Core/Src
 ProjectManager.NoMain=false
@ -319,7 +381,13 @@ ProjectManager.StackSize=0x400
 ProjectManager.TargetToolchain=MDK-ARM V5.32
 ProjectManager.ToolChainLocation=
 ProjectManager.UnderRoot=false
-ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_FMC_Init-FMC-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_FMC_Init-FMC-false-HAL-true,5-MX_QUADSPI_Init-QUADSPI-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true
+QUADSPI.ChipSelectHighTime=QSPI_CS_HIGH_TIME_2_CYCLE
+QUADSPI.ClockPrescaler=1
+QUADSPI.FifoThreshold=3
+QUADSPI.FlashSize=24
+QUADSPI.IPParameters=ClockPrescaler,FifoThreshold,SampleShifting,FlashSize,ChipSelectHighTime
+QUADSPI.SampleShifting=QSPI_SAMPLE_SHIFTING_HALFCYCLE
 RCC.ADCFreq_Value=24187500
 RCC.AHB12Freq_Value=200000000
 RCC.AHB4Freq_Value=200000000
@ -337,20 +405,21 @@ RCC.D1PPRE=RCC_APB3_DIV2
 RCC.D2PPRE1=RCC_APB1_DIV2
 RCC.D2PPRE2=RCC_APB2_DIV2
 RCC.D3PPRE=RCC_APB4_DIV2
-RCC.DFSDMACLkFreq_Value=400000000
+RCC.DFSDMACLkFreq_Value=200000000
 RCC.DFSDMFreq_Value=100000000
 RCC.DIVM1=3
 RCC.DIVN1=200
 RCC.DIVP1Freq_Value=400000000
 RCC.DIVP2Freq_Value=24187500
 RCC.DIVP3Freq_Value=24187500
-RCC.DIVQ1Freq_Value=400000000
+RCC.DIVQ1=4
+RCC.DIVQ1Freq_Value=200000000
 RCC.DIVQ2Freq_Value=24187500
 RCC.DIVQ3Freq_Value=24187500
 RCC.DIVR1Freq_Value=400000000
 RCC.DIVR2Freq_Value=24187500
 RCC.DIVR3Freq_Value=24187500
-RCC.FDCANFreq_Value=400000000
+RCC.FDCANFreq_Value=200000000
 RCC.FMCFreq_Value=200000000
 RCC.FamilyName=M
 RCC.HCLK3ClockFreq_Value=200000000
@ -360,7 +429,7 @@ RCC.HRTIMFreq_Value=200000000
 RCC.HSE_VALUE=12000000
 RCC.I2C123Freq_Value=100000000
 RCC.I2C4Freq_Value=100000000
-RCC.IPParameters=ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CECFreq_Value,CKPERFreq_Value,CortexFreq_Value,CpuClockFreq_Value,D1CPREFreq_Value,D1PPRE,D2PPRE1,D2PPRE2,D3PPRE,DFSDMACLkFreq_Value,DFSDMFreq_Value,DIVM1,DIVN1,DIVP1Freq_Value,DIVP2Freq_Value,DIVP3Freq_Value,DIVQ1Freq_Value,DIVQ2Freq_Value,DIVQ3Freq_Value,DIVR1Freq_Value,DIVR2Freq_Value,DIVR3Freq_Value,FDCANFreq_Value,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,HPRE,HRTIMFreq_Value,HSE_VALUE,I2C123Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM345Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,PLL2FRACN,PLL3FRACN,PLLFRACN,PLLSourceVirtual,QSPIFreq_Value,RNGFreq_Value,RTCFreq_Value,SAI1Freq_Value,SAI23Freq_Value,SAI4AFreq_Value,SAI4BFreq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI123Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16Freq_Value,USART234578Freq_Value,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value
+RCC.IPParameters=ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CECFreq_Value,CKPERFreq_Value,CortexFreq_Value,CpuClockFreq_Value,D1CPREFreq_Value,D1PPRE,D2PPRE1,D2PPRE2,D3PPRE,DFSDMACLkFreq_Value,DFSDMFreq_Value,DIVM1,DIVN1,DIVP1Freq_Value,DIVP2Freq_Value,DIVP3Freq_Value,DIVQ1,DIVQ1Freq_Value,DIVQ2Freq_Value,DIVQ3Freq_Value,DIVR1Freq_Value,DIVR2Freq_Value,DIVR3Freq_Value,FDCANFreq_Value,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,HPRE,HRTIMFreq_Value,HSE_VALUE,I2C123Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM345Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,PLL2FRACN,PLL3FRACN,PLLFRACN,PLLSourceVirtual,QSPIFreq_Value,RNGFreq_Value,RTCFreq_Value,SAI1Freq_Value,SAI23Freq_Value,SAI4AFreq_Value,SAI4BFreq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI123Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16Freq_Value,USART234578Freq_Value,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value
 RCC.LPTIM1Freq_Value=100000000
 RCC.LPTIM2Freq_Value=100000000
 RCC.LPTIM345Freq_Value=100000000
@ -375,13 +444,13 @@ RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
 RCC.QSPIFreq_Value=200000000
 RCC.RNGFreq_Value=48000000
 RCC.RTCFreq_Value=32000
-RCC.SAI1Freq_Value=400000000
-RCC.SAI23Freq_Value=400000000
-RCC.SAI4AFreq_Value=400000000
-RCC.SAI4BFreq_Value=400000000
-RCC.SDMMCFreq_Value=400000000
-RCC.SPDIFRXFreq_Value=400000000
-RCC.SPI123Freq_Value=400000000
+RCC.SAI1Freq_Value=200000000
+RCC.SAI23Freq_Value=200000000
+RCC.SAI4AFreq_Value=200000000
+RCC.SAI4BFreq_Value=200000000
+RCC.SDMMCFreq_Value=200000000
+RCC.SPDIFRXFreq_Value=200000000
+RCC.SPI123Freq_Value=200000000
 RCC.SPI45Freq_Value=100000000
 RCC.SPI6Freq_Value=100000000
 RCC.SWPMI1Freq_Value=100000000
@ -392,13 +461,15 @@ RCC.Tim2OutputFreq_Value=200000000
 RCC.TraceFreq_Value=64000000
 RCC.USART16Freq_Value=100000000
 RCC.USART234578Freq_Value=100000000
-RCC.USBFreq_Value=400000000
+RCC.USBFreq_Value=200000000
 RCC.VCO1OutputFreq_Value=800000000
 RCC.VCO2OutputFreq_Value=48375000
 RCC.VCO3OutputFreq_Value=48375000
 RCC.VCOInput1Freq_Value=4000000
 RCC.VCOInput2Freq_Value=375000
 RCC.VCOInput3Freq_Value=375000
+SDMMC1.ClockDiv=4
+SDMMC1.IPParameters=ClockDiv
 SH.FMC_A0.0=FMC_A0,12b-sda1
 SH.FMC_A0.ConfNb=1
 SH.FMC_A1.0=FMC_A1,12b-sda1
--- a/bsp/stm32/stm32h743-openmv-h7plus/board/Kconfig
+++ b/bsp/stm32/stm32h743-openmv-h7plus/board/Kconfig
@ -1,56 +1,83 @@
 menu "Hardware Drivers Config"

-config SOC_STM32H743II
-    bool
-    select SOC_SERIES_STM32H7
-    select RT_USING_COMPONENTS_INIT
-    select RT_USING_USER_MAIN
-    default y
-    
-menu "On-chip Peripheral Drivers"
-
-    config BSP_USING_GPIO
-        bool "Enable GPIO"
-        select RT_USING_PIN
+    config SOC_STM32H743II
+        bool
+        select SOC_SERIES_STM32H7
+        select RT_USING_COMPONENTS_INIT
+        select RT_USING_USER_MAIN
        default y
-    menuconfig BSP_USING_UART
-        bool "Enable UART"
-        default y
-        select RT_USING_SERIAL
-        if BSP_USING_UART
-            config BSP_USING_UART1
-                bool "Enable UART1"
-                default y
    
-            config BSP_UART1_RX_USING_DMA
-                bool "Enable UART1 RX DMA"
-                depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
+    menu "On-chip Peripheral Drivers"
+
+        config BSP_USING_GPIO
+            bool "Enable GPIO"
+            select RT_USING_PIN
+            default y
+
+        menuconfig BSP_USING_UART
+            bool "Enable UART"
+            default y
+            select RT_USING_SERIAL
+
+            if BSP_USING_UART
+                config BSP_USING_UART1
+                    bool "Enable UART1"
+                    default y
+
+                config BSP_UART1_RX_USING_DMA
+                    bool "Enable UART1 RX DMA"
+                    depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
+                    default n
+
+                config BSP_USING_UART2
+                    bool "Enable UART2"
+                    default n
+
+                config BSP_UART2_RX_USING_DMA
+                    bool "Enable UART2 RX DMA"
+                    depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
+                    default n
+                    
+                config BSP_USING_LPUART1
+                    bool "Enable LPUART1"
+                    default n
+
+                config BSP_LPUART1_RX_USING_DMA
+                    bool "Enable LPUART1 RX DMA"
+                    depends on BSP_USING_LPUART1 && RT_SERIAL_USING_DMA
+                    default n
+            endif
+            
+            config BSP_USING_QSPI
+                bool "Enable QSPI BUS"
+                select RT_USING_QSPI
+                select RT_USING_SPI
                default n

-            config BSP_USING_UART2
-                bool "Enable UART2"
-                default n
+        source "../libraries/HAL_Drivers/Kconfig"
            
-            config BSP_UART2_RX_USING_DMA
-                bool "Enable UART2 RX DMA"
-                depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
-                default n
+    endmenu

-			config BSP_USING_LPUART1
-                bool "Enable LPUART1"
-                default n
+    menu "Onboard Peripheral Drivers"

-            config BSP_LPUART1_RX_USING_DMA
-                bool "Enable LPUART1 RX DMA"
-                depends on BSP_USING_LPUART1 && RT_SERIAL_USING_DMA
-                default n
-        endif
-    config BSP_USING_SDRAM
-        bool "Enable SDRAM"
-        default n
+        config BSP_USING_SDRAM
+            bool "Enable SDRAM"
+            default n

-    source "../libraries/HAL_Drivers/Kconfig"
-    
-endmenu
+        config BSP_USING_QSPI_FLASH
+            bool "Enable QSPI FLASH (W25Q256 qspi)"
+            select BSP_USING_QSPI
+            select RT_USING_SFUD
+            select RT_SFUD_USING_QSPI
+            default n
+
+        config BSP_USING_SDMMC
+            bool "Enable SDMMC (SD card)"
+            select RT_USING_SDIO
+            select RT_USING_DFS
+            select RT_USING_DFS_ELMFAT
+            default n
+
+    endmenu

 endmenu
--- a/bsp/stm32/stm32h743-openmv-h7plus/board/SConscript
+++ b/bsp/stm32/stm32h743-openmv-h7plus/board/SConscript
@ -16,6 +16,11 @@ path =  [cwd]
 path += [cwd + '/CubeMX_Config/Core/Inc']
 path += [cwd + '/ports']

+if GetDepend(['BSP_USING_QSPI_FLASH']):
+    src += Glob('ports/drv_qspi_flash.c')
+if GetDepend(['BSP_USING_SDMMC']):
+    src += Glob('ports/drv_sdio.c')
+
 startup_path_prefix = SDK_LIB

 if rtconfig.CROSS_TOOL == 'gcc':
--- a/bsp/stm32/stm32h743-openmv-h7plus/board/board.c
+++ b/bsp/stm32/stm32h743-openmv-h7plus/board/board.c
@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2021, RT-Thread Development Team
+ * Copyright (c) 2006-2022, RT-Thread Development Team
 *
 * SPDX-License-Identifier: Apache-2.0
 *
--- a/bsp/stm32/stm32h743-openmv-h7plus/board/board.h
+++ b/bsp/stm32/stm32h743-openmv-h7plus/board/board.h
@ -1,11 +1,12 @@
 /*
- * Copyright (c) 2006-2021, RT-Thread Development Team
+ * Copyright (c) 2006-2022, RT-Thread Development Team
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Change Logs:
 * Date           Author       Notes
 * 2021-12-14     supperthomas first version
+ * 2022-03-16     Miaowulue    add sram2
 */


@ -29,6 +30,10 @@ extern "C" {
 #define STM32_SRAM1_START              (0x20000000)
 #define STM32_SRAM1_END                (STM32_SRAM1_START + STM32_SRAM1_SIZE * 1024)

+#define STM32_SRAM2_SIZE               (512)
+#define STM32_SRAM2_START              (0x24000000)
+#define STM32_SRAM2_END                (STM32_SRAM2_START + STM32_SRAM2_SIZE * 1024)
+
 #if defined(__ARMCC_VERSION)
 extern int Image$$RW_IRAM1$$ZI$$Limit;
 #define HEAP_BEGIN      ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
@ -40,7 +45,7 @@ extern int __bss_end;
 #define HEAP_BEGIN      ((void *)&__bss_end)
 #endif

-#define HEAP_END                       STM32_SRAM1_END
+#define HEAP_END                       STM32_SRAM2_END

 void SystemClock_Config(void);

--- a/bsp/stm32/stm32h743-openmv-h7plus/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32h743-openmv-h7plus/board/linker_scripts/link.lds
@ -89,7 +89,7 @@ SECTIONS
        . = ALIGN(4);
        /* This is used by the startup in order to initialize the .data secion */
        _edata = . ;
-    } >RAM1
+    } >RAM2

    .stack : 
    {
@ -98,7 +98,7 @@ SECTIONS
        . = . + _system_stack_size;
        . = ALIGN(4);
        _estack = .;
-    } >RAM1
+    } >RAM2

    __bss_start = .;
    .bss :
@ -116,7 +116,7 @@ SECTIONS
        _ebss = . ;
        
        *(.bss.init)
-    } > RAM1
+    } > RAM2
    __bss_end = .;

    _end = .;
--- a/bsp/stm32/stm32h743-openmv-h7plus/board/ports/drv_qspi_flash.c
+++ b/bsp/stm32/stm32h743-openmv-h7plus/board/ports/drv_qspi_flash.c
@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-27     zylx         first version
+ * 2022-03-16     Miaowulue    add dfs mount
+ */
+
+#include <board.h>
+#include <drv_qspi.h>
+#include <rtdevice.h>
+#include <rthw.h>
+#include <finsh.h>
+#include <dfs_elm.h>
+#include <dfs_fs.h>
+
+#ifdef BSP_USING_QSPI_FLASH
+
+#include "spi_flash.h"
+#include "spi_flash_sfud.h"
+
+char w25qxx_read_status_register2(struct rt_qspi_device *device)
+{
+    /* 0x35 read status register2 */
+    char instruction = 0x35, status;
+
+    rt_qspi_send_then_recv(device, &instruction, 1, &status, 1);
+
+    return status;
+}
+
+void w25qxx_write_enable(struct rt_qspi_device *device)
+{
+    /* 0x06 write enable */
+    char instruction = 0x06;
+
+    rt_qspi_send(device, &instruction, 1);
+}
+
+void w25qxx_enter_qspi_mode(struct rt_qspi_device *device)
+{
+    char status = 0;
+    /* 0x38 enter qspi mode */
+    char instruction = 0x38;
+    char write_status2_buf[2] = {0};
+
+    /* 0x31 write status register2 */
+    write_status2_buf[0] = 0x31;
+
+    status = w25qxx_read_status_register2(device);
+    if (!(status & 0x02))
+    {
+        status |= 1 << 1;
+        w25qxx_write_enable(device);
+        write_status2_buf[1] = status;
+        rt_qspi_send(device, &write_status2_buf, 2);
+        rt_qspi_send(device, &instruction, 1);
+        rt_kprintf("flash already enter qspi mode\n");
+        rt_thread_mdelay(10);
+    }
+}
+
+static int rt_hw_qspi_flash_with_sfud_init(void)
+{
+    stm32_qspi_bus_attach_device("qspi1", "qspi10", RT_NULL, 4, w25qxx_enter_qspi_mode, RT_NULL);
+
+    /* init W25Q256 */
+    if (RT_NULL == rt_sfud_flash_probe("W25Q256", "qspi10"))
+    {
+        return -RT_ERROR;
+    }
+
+    return RT_EOK;
+}
+INIT_DEVICE_EXPORT(rt_hw_qspi_flash_with_sfud_init);
+
+static int mnt_qspi_flash_init(void)
+{
+    if (dfs_mount("W25Q256", "/", "elm", 0, 0) == RT_EOK)
+    {
+        rt_kprintf("Mount spi flash successfully!\n");
+        return RT_EOK;
+    }
+    else
+    {
+        rt_kprintf("Mount spi flash fail!\n");
+        return -RT_ERROR;
+    }
+}
+INIT_APP_EXPORT(mnt_qspi_flash_init);
+
+#endif/* BSP_USING_QSPI_FLASH */
--- a/bsp/stm32/stm32h743-openmv-h7plus/board/ports/drv_sdio.c
+++ b/bsp/stm32/stm32h743-openmv-h7plus/board/ports/drv_sdio.c
@ -0,0 +1,470 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-05-23     liuduanfei   first version
+ * 2022-03-16     Miaowulue    change prompt message
+ */
+
+#include "board.h"
+#include "drv_sdio.h"
+#include <dfs_fs.h>
+
+#ifdef BSP_USING_SDMMC
+
+#define DBG_TAG              "drv.sdio"
+#ifdef DRV_DEBUG
+#define DBG_LVL               DBG_LOG
+#else
+#define DBG_LVL               DBG_INFO
+#endif /* DRV_DEBUG */
+#include <rtdbg.h>
+
+static struct rt_mmcsd_host *host;
+#define SDIO_TX_RX_COMPLETE_TIMEOUT_LOOPS    (100000)
+
+struct sdio_pkg
+{
+    struct rt_mmcsd_cmd *cmd;
+    void *buff;
+    rt_uint32_t flag;
+};
+
+struct rthw_sdio
+{
+    struct rt_mmcsd_host *host;
+    struct stm32_sdio_des sdio_des;
+    struct rt_event event;
+    struct sdio_pkg *pkg;
+};
+
+ALIGN(SDIO_ALIGN_LEN)
+static rt_uint8_t cache_buf[SDIO_BUFF_SIZE];
+
+/**
+  * @brief  This function get order from sdio.
+  * @param  data
+  * @retval sdio order
+  */
+static int get_order(rt_uint32_t data)
+{
+    int order = 0;
+
+    switch (data)
+    {
+    case 1:
+        order = 0;
+        break;
+    case 2:
+        order = 1;
+        break;
+    case 4:
+        order = 2;
+        break;
+    case 8:
+        order = 3;
+        break;
+    case 16:
+        order = 4;
+        break;
+    case 32:
+        order = 5;
+        break;
+    case 64:
+        order = 6;
+        break;
+    case 128:
+        order = 7;
+        break;
+    case 256:
+        order = 8;
+        break;
+    case 512:
+        order = 9;
+        break;
+    case 1024:
+        order = 10;
+        break;
+    case 2048:
+        order = 11;
+        break;
+    case 4096:
+        order = 12;
+        break;
+    case 8192:
+        order = 13;
+        break;
+    case 16384:
+        order = 14;
+        break;
+    default :
+        order = 0;
+        break;
+    }
+    return order;
+}
+
+/**
+  * @brief  This function wait sdio cmd completed.
+  * @param  sdio rthw_sdio
+  * @retval None
+  */
+static void rthw_sdio_wait_completed(struct rthw_sdio *sdio)
+{
+    rt_uint32_t status;
+    struct rt_mmcsd_cmd *cmd = sdio->pkg->cmd;
+    struct stm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio;
+
+    if (rt_event_recv(&sdio->event, 0xffffffff, RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR,
+                      rt_tick_from_millisecond(5000), &status) != RT_EOK)
+    {
+        LOG_E("wait cmd completed timeout");
+        cmd->err = -RT_ETIMEOUT;
+        return;
+    }
+
+    cmd->resp[0] = hw_sdio->resp1;
+    if (resp_type(cmd) == RESP_R2)
+    {
+        cmd->resp[1] = hw_sdio->resp2;
+        cmd->resp[2] = hw_sdio->resp3;
+        cmd->resp[3] = hw_sdio->resp4;
+    }
+
+    if (status & SDIO_ERRORS)
+    {
+        if ((status & SDMMC_STA_CCRCFAIL) && (resp_type(cmd) & (RESP_R3 | RESP_R4)))
+        {
+            cmd->err = RT_EOK;
+        }
+        else
+        {
+            cmd->err = -RT_ERROR;
+        }
+    }
+
+    if (cmd->err == RT_EOK)
+    {
+        LOG_D("sta:0x%08X [%08X %08X %08X %08X]", status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
+    }
+    else
+    {
+        LOG_D("send command error = %d", cmd->err);
+    }
+}
+
+/**
+  * @brief  This function send command.
+  * @param  sdio rthw_sdio
+  * @param  pkg  sdio package
+  * @retval None
+  */
+static void rthw_sdio_send_command(struct rthw_sdio *sdio, struct sdio_pkg *pkg)
+{
+    struct rt_mmcsd_cmd *cmd = pkg->cmd;
+    struct rt_mmcsd_data *data = cmd->data;
+    struct stm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio;
+    rt_uint32_t reg_cmd;
+
+    /* save pkg */
+    sdio->pkg = pkg;
+
+    LOG_D("CMD:%d ARG:0x%08x RES:%s%s%s%s%s%s%s%s%s rw:%c len:%d blksize:%d\n",
+          cmd->cmd_code,
+          cmd->arg,
+          resp_type(cmd) == RESP_NONE ? "NONE"  : "",
+          resp_type(cmd) == RESP_R1  ? "R1"  : "",
+          resp_type(cmd) == RESP_R1B ? "R1B"  : "",
+          resp_type(cmd) == RESP_R2  ? "R2"  : "",
+          resp_type(cmd) == RESP_R3  ? "R3"  : "",
+          resp_type(cmd) == RESP_R4  ? "R4"  : "",
+          resp_type(cmd) == RESP_R5  ? "R5"  : "",
+          resp_type(cmd) == RESP_R6  ? "R6"  : "",
+          resp_type(cmd) == RESP_R7  ? "R7"  : "",
+          data ? (data->flags & DATA_DIR_WRITE ?  'w' : 'r') : '-',
+          data ? data->blks * data->blksize : 0,
+          data ? data->blksize : 0
+         );
+
+    hw_sdio->mask |= SDIO_MASKR_ALL;
+    reg_cmd = cmd->cmd_code | SDMMC_CMD_CPSMEN;
+
+    /* data pre configuration */
+    if (data != RT_NULL)
+    {
+        SCB_CleanInvalidateDCache();
+
+        reg_cmd |= SDMMC_CMD_CMDTRANS;
+        hw_sdio->mask &= ~(SDMMC_MASK_CMDRENDIE | SDMMC_MASK_CMDSENTIE);
+        hw_sdio->dtimer = HW_SDIO_DATATIMEOUT;
+        hw_sdio->dlen = data->blks * data->blksize;
+        hw_sdio->dctrl = (get_order(data->blksize)<<4) | (data->flags & DATA_DIR_READ ? SDMMC_DCTRL_DTDIR : 0);
+        hw_sdio->idmabase0r = (rt_uint32_t)cache_buf;
+        hw_sdio->idmatrlr = SDMMC_IDMA_IDMAEN;
+    }
+
+    if (resp_type(cmd) == RESP_R2)
+        reg_cmd |= SDMMC_CMD_WAITRESP;
+    else if(resp_type(cmd) != RESP_NONE)
+        reg_cmd |= SDMMC_CMD_WAITRESP_0;
+
+    hw_sdio->arg = cmd->arg;
+    hw_sdio->cmd = reg_cmd;
+    /* wait completed */
+    rthw_sdio_wait_completed(sdio);
+
+    /* Waiting for data to be sent to completion */
+    if (data != RT_NULL)
+    {
+        volatile rt_uint32_t count = SDIO_TX_RX_COMPLETE_TIMEOUT_LOOPS;
+
+        while (count && (hw_sdio->sta & SDMMC_STA_DPSMACT))
+        {
+            count--;
+        }
+        if ((count == 0) || (hw_sdio->sta & SDIO_ERRORS))
+        {
+            cmd->err = -RT_ERROR;
+        }
+    }
+
+    /* data post configuration */
+    if (data != RT_NULL)
+    {
+        if (data->flags & DATA_DIR_READ)
+        {
+            rt_memcpy(data->buf, cache_buf, data->blks * data->blksize);
+            SCB_CleanInvalidateDCache();
+        }
+    }
+}
+
+/**
+  * @brief  This function send sdio request.
+  * @param  sdio  rthw_sdio
+  * @param  req   request
+  * @retval None
+  */
+static void rthw_sdio_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
+{
+    struct sdio_pkg pkg;
+    struct rthw_sdio *sdio = host->private_data;
+    struct rt_mmcsd_data *data;
+
+    if (req->cmd != RT_NULL)
+    {
+        rt_memset(&pkg, 0, sizeof(pkg));
+        data = req->cmd->data;
+        pkg.cmd = req->cmd;
+
+        if (data != RT_NULL)
+        {
+            rt_uint32_t size = data->blks * data->blksize;
+
+            RT_ASSERT(size <= SDIO_BUFF_SIZE);
+
+            if (data->flags & DATA_DIR_WRITE)
+            {
+                rt_memcpy(cache_buf, data->buf, size);
+            }
+        }
+
+        rthw_sdio_send_command(sdio, &pkg);
+    }
+
+    if (req->stop != RT_NULL)
+    {
+        rt_memset(&pkg, 0, sizeof(pkg));
+        pkg.cmd = req->stop;
+        rthw_sdio_send_command(sdio, &pkg);
+    }
+
+    mmcsd_req_complete(sdio->host);
+}
+
+
+/**
+  * @brief  This function interrupt process function.
+  * @param  host  rt_mmcsd_host
+  * @retval None
+  */
+void rthw_sdio_irq_process(struct rt_mmcsd_host *host)
+{
+    struct rthw_sdio *sdio = host->private_data;
+    struct stm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio;
+    rt_uint32_t intstatus = hw_sdio->sta;
+
+    /* clear irq flag*/
+    hw_sdio->icr = intstatus;
+
+    rt_event_send(&sdio->event, intstatus);
+}
+
+/**
+  * @brief  This function config sdio.
+  * @param  host    rt_mmcsd_host
+  * @param  io_cfg  rt_mmcsd_io_cfg
+  * @retval None
+  */
+static void rthw_sdio_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg)
+{
+    rt_uint32_t temp, clk_src;
+    rt_uint32_t clk = io_cfg->clock;
+    struct rthw_sdio *sdio = host->private_data;
+    struct stm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio;
+
+    LOG_D("clk:%dK width:%s%s%s power:%s%s%s",
+          clk/1000,
+          io_cfg->bus_width == MMCSD_BUS_WIDTH_8 ? "8" : "",
+          io_cfg->bus_width == MMCSD_BUS_WIDTH_4 ? "4" : "",
+          io_cfg->bus_width == MMCSD_BUS_WIDTH_1 ? "1" : "",
+          io_cfg->power_mode == MMCSD_POWER_OFF ? "OFF" : "",
+          io_cfg->power_mode == MMCSD_POWER_UP ? "UP" : "",
+          io_cfg->power_mode == MMCSD_POWER_ON ? "ON" : ""
+         );
+
+    clk_src = SDIO_CLOCK_FREQ;
+
+    if (clk > 0)
+    {
+        if (clk > host->freq_max)
+            clk = host->freq_max;
+        temp = DIV_ROUND_UP(clk_src, 2 * clk);
+        if (temp > 0x3FF)
+         temp = 0x3FF;
+    }
+
+    if (io_cfg->bus_width == MMCSD_BUS_WIDTH_4)
+        temp |= SDMMC_CLKCR_WIDBUS_0;
+    else if (io_cfg->bus_width == MMCSD_BUS_WIDTH_8)
+        temp |= SDMMC_CLKCR_WIDBUS_1;
+
+    hw_sdio->clkcr = temp;
+
+    if (io_cfg->power_mode == MMCSD_POWER_ON)
+        hw_sdio->power |= SDMMC_POWER_PWRCTRL;
+}
+
+static const struct rt_mmcsd_host_ops ops =
+{
+    rthw_sdio_request,
+    rthw_sdio_iocfg,
+    RT_NULL,
+    RT_NULL,
+};
+
+/**
+  * @brief  This function create mmcsd host.
+  * @param  sdio_des stm32_sdio_des
+  * @retval rt_mmcsd_host
+  */
+struct rt_mmcsd_host *sdio_host_create(struct stm32_sdio_des *sdio_des)
+{
+    struct rt_mmcsd_host *host;
+    struct rthw_sdio *sdio = RT_NULL;
+
+    if (sdio_des == RT_NULL)
+    {
+        return RT_NULL;
+    }
+
+    sdio = rt_malloc(sizeof(struct rthw_sdio));
+    if (sdio == RT_NULL)
+    {
+        LOG_E("malloc rthw_sdio fail");
+        return RT_NULL;
+    }
+    rt_memset(sdio, 0, sizeof(struct rthw_sdio));
+
+    host = mmcsd_alloc_host();
+    if (host == RT_NULL)
+    {
+        LOG_E("alloc host fail");
+        goto err;
+    }
+
+    rt_memcpy(&sdio->sdio_des, sdio_des, sizeof(struct stm32_sdio_des));
+
+    sdio->sdio_des.hw_sdio = (struct stm32_sdio *)SDIO_BASE_ADDRESS;
+
+    rt_event_init(&sdio->event, "sdio", RT_IPC_FLAG_FIFO);
+
+    /* set host default attributes */
+    host->ops = &ops;
+    host->freq_min = 400 * 1000;
+    host->freq_max = SDIO_MAX_FREQ;
+    host->valid_ocr = VDD_32_33 | VDD_33_34;/* The voltage range supported is 3.2v-3.4v */
+#ifndef SDIO_USING_1_BIT
+    host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | MMCSD_SUP_HIGHSPEED;
+#else
+    host->flags = MMCSD_MUTBLKWRITE | MMCSD_SUP_HIGHSPEED;
+#endif
+
+    host->max_seg_size = SDIO_BUFF_SIZE;
+    host->max_dma_segs = 1;
+    host->max_blk_size = 512;
+    host->max_blk_count = 512;
+
+    /* link up host and sdio */
+    sdio->host = host;
+    host->private_data = sdio;
+
+    /* ready to change */
+    mmcsd_change(host);
+
+    return host;
+
+err:
+    if (sdio) rt_free(sdio);
+
+    return RT_NULL;
+}
+
+void SDMMC1_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+    /* Process All SDIO Interrupt Sources */
+    rthw_sdio_irq_process(host);
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+int rt_hw_sdio_init(void)
+{
+    struct stm32_sdio_des sdio_des;
+    SD_HandleTypeDef hsd;
+    hsd.Instance = SDMMC1;
+    HAL_SD_MspInit(&hsd);
+
+    host = sdio_host_create(&sdio_des);
+    if (host == RT_NULL)
+    {
+        LOG_E("host create fail");
+        return RT_NULL;
+    }
+    return 0;
+}
+INIT_DEVICE_EXPORT(rt_hw_sdio_init);
+
+int mnt_init(void)
+{
+    rt_thread_delay(RT_TICK_PER_SECOND);
+
+    if (dfs_mount("sd0", "/", "elm", 0, 0) != 0)
+    {
+        rt_kprintf("Mount sd card fail!\n");
+    }
+    else
+    {
+        rt_kprintf("Mount sd card successfully!\n");
+    }
+
+    return 0;
+}
+INIT_ENV_EXPORT(mnt_init);
+
+#endif /* BSP_USING_SDMMC */
--- a/bsp/stm32/stm32h743-openmv-h7plus/board/ports/drv_sdio.h
+++ b/bsp/stm32/stm32h743-openmv-h7plus/board/ports/drv_sdio.h
@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-05-23     liuduanfei   first version
+ */
+
+#ifndef __DRV_SDIO_H__
+#define __DRV_SDIO_H__
+
+#include <rtthread.h>
+#include "rtdevice.h"
+#include <rthw.h>
+#include <drv_common.h>
+#include <string.h>
+#include <drivers/mmcsd_core.h>
+#include <drivers/sdio.h>
+
+#define SDIO_BUFF_SIZE       4096
+#define SDIO_ALIGN_LEN       32
+
+#ifndef SDIO_BASE_ADDRESS
+#define SDIO_BASE_ADDRESS    (0x52007000)
+#endif
+
+#ifndef SDIO_CLOCK_FREQ
+#define SDIO_CLOCK_FREQ      (200U * 1000 * 1000)
+#endif
+
+#ifndef SDIO_BUFF_SIZE
+#define SDIO_BUFF_SIZE       (4096)
+#endif
+
+#ifndef SDIO_ALIGN_LEN
+#define SDIO_ALIGN_LEN       (32)
+#endif
+
+#ifndef SDIO_MAX_FREQ
+#define SDIO_MAX_FREQ        (25 * 1000 * 1000)
+#endif
+
+#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
+
+#define SDIO_ERRORS \
+    (SDMMC_STA_IDMATE | SDMMC_STA_ACKTIMEOUT | \
+     SDMMC_STA_RXOVERR | SDMMC_STA_TXUNDERR | \
+     SDMMC_STA_DTIMEOUT | SDMMC_STA_CTIMEOUT | \
+     SDMMC_STA_DCRCFAIL | SDMMC_STA_CCRCFAIL)
+
+#define SDIO_MASKR_ALL \
+    (SDMMC_MASK_CCRCFAILIE | SDMMC_MASK_DCRCFAILIE | SDMMC_MASK_CTIMEOUTIE | \
+     SDMMC_MASK_TXUNDERRIE | SDMMC_MASK_RXOVERRIE | SDMMC_MASK_CMDRENDIE | \
+     SDMMC_MASK_CMDSENTIE | SDMMC_MASK_DATAENDIE | SDMMC_MASK_ACKTIMEOUTIE)
+
+#define HW_SDIO_DATATIMEOUT                 (0xFFFFFFFFU)
+
+struct stm32_sdio
+{
+    volatile rt_uint32_t power;         /* offset 0x00 */
+    volatile rt_uint32_t clkcr;         /* offset 0x04 */
+    volatile rt_uint32_t arg;           /* offset 0x08 */
+    volatile rt_uint32_t cmd;           /* offset 0x0C */
+    volatile rt_uint32_t respcmd;       /* offset 0x10 */
+    volatile rt_uint32_t resp1;         /* offset 0x14 */
+    volatile rt_uint32_t resp2;         /* offset 0x18 */
+    volatile rt_uint32_t resp3;         /* offset 0x1C */
+    volatile rt_uint32_t resp4;         /* offset 0x20 */
+    volatile rt_uint32_t dtimer;        /* offset 0x24 */
+    volatile rt_uint32_t dlen;          /* offset 0x28 */
+    volatile rt_uint32_t dctrl;         /* offset 0x2C */
+    volatile rt_uint32_t dcount;        /* offset 0x30 */
+    volatile rt_uint32_t sta;           /* offset 0x34 */
+    volatile rt_uint32_t icr;           /* offset 0x38 */
+    volatile rt_uint32_t mask;          /* offset 0x3C */
+    volatile rt_uint32_t acktimer;      /* offset 0x40 */
+    volatile rt_uint32_t reserved0[3];  /* offset 0x44 ~ 0x4C */
+    volatile rt_uint32_t idmatrlr;      /* offset 0x50 */
+    volatile rt_uint32_t idmabsizer;    /* offset 0x54 */
+    volatile rt_uint32_t idmabase0r;    /* offset 0x58 */
+    volatile rt_uint32_t idmabase1r;    /* offset 0x5C */
+    volatile rt_uint32_t reserved1[8];  /* offset 0x60 ~ 7C */
+    volatile rt_uint32_t fifo;          /* offset 0x80 */
+};
+
+typedef rt_uint32_t (*sdio_clk_get)(struct stm32_sdio *hw_sdio);
+
+struct stm32_sdio_des
+{
+    struct stm32_sdio *hw_sdio;
+    sdio_clk_get clk_get;
+};
+
+/* stm32 sdio dirver class */
+struct stm32_sdio_class
+{
+    struct stm32_sdio_des *des;
+    const struct stm32_sdio_config *cfg;
+    struct rt_mmcsd_host host;
+};
+
+extern void stm32_mmcsd_change(void);
+
+#endif /* __DRV_SDIO_H__ */
--- a/bsp/stm32/stm32h743-openmv-h7plus/board/ports/sdram_port.h
+++ b/bsp/stm32/stm32h743-openmv-h7plus/board/ports/sdram_port.h
@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2021, RT-Thread Development Team
+ * Copyright (c) 2006-2022, RT-Thread Development Team
 *
 * SPDX-License-Identifier: Apache-2.0
 *
--- a/bsp/stm32/stm32h743-openmv-h7plus/rtconfig.h
+++ b/bsp/stm32/stm32h743-openmv-h7plus/rtconfig.h
@ -78,6 +78,27 @@

 /* Device virtual file system */

+#define RT_USING_DFS
+#define DFS_USING_POSIX
+#define DFS_USING_WORKDIR
+#define DFS_FILESYSTEMS_MAX 4
+#define DFS_FILESYSTEM_TYPES_MAX 4
+#define DFS_FD_MAX 16
+#define RT_USING_DFS_ELMFAT
+
+/* elm-chan's FatFs, Generic FAT Filesystem Module */
+
+#define RT_DFS_ELM_CODE_PAGE 437
+#define RT_DFS_ELM_WORD_ACCESS
+#define RT_DFS_ELM_USE_LFN_3
+#define RT_DFS_ELM_USE_LFN 3
+#define RT_DFS_ELM_LFN_UNICODE_0
+#define RT_DFS_ELM_LFN_UNICODE 0
+#define RT_DFS_ELM_MAX_LFN 255
+#define RT_DFS_ELM_DRIVES 2
+#define RT_DFS_ELM_MAX_SECTOR_SIZE 4096
+#define RT_DFS_ELM_REENTRANT
+#define RT_DFS_ELM_MUTEX_TIMEOUT 3000

 /* Device Drivers */

@ -87,6 +108,19 @@
 #define RT_SERIAL_USING_DMA
 #define RT_SERIAL_RB_BUFSZ 64
 #define RT_USING_PIN
+#define RT_USING_SDIO
+#define RT_SDIO_STACK_SIZE 512
+#define RT_SDIO_THREAD_PRIORITY 15
+#define RT_MMCSD_STACK_SIZE 1024
+#define RT_MMCSD_THREAD_PREORITY 22
+#define RT_MMCSD_MAX_PARTITION 16
+#define RT_USING_SPI
+#define RT_USING_QSPI
+#define RT_USING_SFUD
+#define RT_SFUD_USING_SFDP
+#define RT_SFUD_USING_FLASH_INFO_TABLE
+#define RT_SFUD_USING_QSPI
+#define RT_SFUD_SPI_MAX_HZ 50000000

 /* Using USB */

@ -97,6 +131,7 @@

 /* POSIX (Portable Operating System Interface) layer */

+#define RT_USING_POSIX_FS

 /* Interprocess Communication (IPC) */

@ -105,17 +140,6 @@

 /* Network */

-/* Socket abstraction layer */
-
-
-/* Network interface device */
-
-
-/* light weight TCP/IP stack */
-
-
-/* AT commands */
-

 /* VBUS(Virtual Software BUS) */

@ -187,6 +211,8 @@

 /* miscellaneous packages */

+/* project laboratory */
+
 /* samples: kernel and components samples */


@ -204,5 +230,10 @@
 #define BSP_USING_GPIO
 #define BSP_USING_UART
 #define BSP_USING_UART1
+#define BSP_USING_QSPI
+
+/* Onboard Peripheral Drivers */
+
+#define BSP_USING_SDRAM

 #endif