[libcpu][riscv]移除cv32e40p中部分文件，采用common中的文件
This commit is contained in:
Yaochenger
Man, Jianting (Meco)
parent
e97ba95f71
commit
f2a66e122f
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@ -49,7 +49,7 @@ if PLATFORM == 'gcc':
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LFLAGS = DEVICE
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LFLAGS += ' -Wl,--gc-sections,-cref,-Map=' + MAP_FILE
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LFLAGS += ' -T ' + LINK_FILE
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AFLAGS += ' -I. '
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CPATH = ''
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LPATH = ''
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@ -22,8 +22,6 @@ elif rtconfig.CPU == "ch32" :
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group = group
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elif rtconfig.CPU == "hpmicro":
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group = group
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elif rtconfig.CPU == "cv32e40p":
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group = group
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else :
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group = group + SConscript(os.path.join('common', 'SConscript'))
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@ -5,7 +5,7 @@ from building import *
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cwd = GetCurrentDir()
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src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
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CPPPATH = [cwd]
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ASFLAGS = ''
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ASFLAGS = ' -I ' + cwd
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group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
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@ -1,181 +0,0 @@
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/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018/10/28 Bernard The unify RISC-V porting implementation
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* 2018/12/27 Jesven Add SMP support
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*/
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#include "cpuport.h"
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#ifdef RT_USING_SMP
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#define rt_hw_interrupt_disable rt_hw_local_irq_disable
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#define rt_hw_interrupt_enable rt_hw_local_irq_enable
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#endif
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/*
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* rt_base_t rt_hw_interrupt_disable(void);
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*/
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.globl rt_hw_interrupt_disable
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rt_hw_interrupt_disable:
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csrrci a0, mstatus, 8
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ret
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/*
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* void rt_hw_interrupt_enable(rt_base_t level);
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*/
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.globl rt_hw_interrupt_enable
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rt_hw_interrupt_enable:
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csrw mstatus, a0
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ret
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/*
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* #ifdef RT_USING_SMP
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* void rt_hw_context_switch_to(rt_ubase_t to, stuct rt_thread *to_thread);
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* #else
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* void rt_hw_context_switch_to(rt_ubase_t to);
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* #endif
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* a0 --> to
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* a1 --> to_thread
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*/
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.globl rt_hw_context_switch_to
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rt_hw_context_switch_to:
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LOAD sp, (a0)
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LOAD a0, 2 * REGBYTES(sp)
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csrw mstatus, a0
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j rt_hw_context_switch_exit
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/*
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* #ifdef RT_USING_SMP
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* void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to, struct rt_thread *to_thread);
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* #else
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* void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to);
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* #endif
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*
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* a0 --> from
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* a1 --> to
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* a2 --> to_thread
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*/
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.globl rt_hw_context_switch
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rt_hw_context_switch:
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/* saved from thread context
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* x1/ra -> sp(0)
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* x1/ra -> sp(1)
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* mstatus.mie -> sp(2)
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* x(i) -> sp(i-4)
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*/
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addi sp, sp, -32 * REGBYTES
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STORE sp, (a0)
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STORE x1, 0 * REGBYTES(sp)
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STORE x1, 1 * REGBYTES(sp)
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csrr a0, mstatus
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andi a0, a0, 8
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beqz a0, save_mpie
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li a0, 0x80
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save_mpie:
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STORE a0, 2 * REGBYTES(sp)
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STORE x4, 4 * REGBYTES(sp)
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STORE x5, 5 * REGBYTES(sp)
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STORE x6, 6 * REGBYTES(sp)
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STORE x7, 7 * REGBYTES(sp)
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STORE x8, 8 * REGBYTES(sp)
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STORE x9, 9 * REGBYTES(sp)
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STORE x10, 10 * REGBYTES(sp)
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STORE x11, 11 * REGBYTES(sp)
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STORE x12, 12 * REGBYTES(sp)
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STORE x13, 13 * REGBYTES(sp)
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STORE x14, 14 * REGBYTES(sp)
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STORE x15, 15 * REGBYTES(sp)
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STORE x16, 16 * REGBYTES(sp)
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STORE x17, 17 * REGBYTES(sp)
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STORE x18, 18 * REGBYTES(sp)
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STORE x19, 19 * REGBYTES(sp)
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STORE x20, 20 * REGBYTES(sp)
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STORE x21, 21 * REGBYTES(sp)
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STORE x22, 22 * REGBYTES(sp)
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STORE x23, 23 * REGBYTES(sp)
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STORE x24, 24 * REGBYTES(sp)
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STORE x25, 25 * REGBYTES(sp)
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STORE x26, 26 * REGBYTES(sp)
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STORE x27, 27 * REGBYTES(sp)
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STORE x28, 28 * REGBYTES(sp)
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STORE x29, 29 * REGBYTES(sp)
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STORE x30, 30 * REGBYTES(sp)
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STORE x31, 31 * REGBYTES(sp)
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/* restore to thread context
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* sp(0) -> epc;
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* sp(1) -> ra;
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* sp(i) -> x(i+2)
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*/
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LOAD sp, (a1)
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j rt_hw_context_switch_exit
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.global rt_hw_context_switch_exit
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rt_hw_context_switch_exit:
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#ifdef RT_USING_SMP
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#ifdef RT_USING_SIGNALS
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mv a0, sp
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csrr t0, mhartid
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/* switch interrupt stack of current cpu */
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la sp, __stack_start__
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addi t1, t0, 1
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li t2, __STACKSIZE__
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mul t1, t1, t2
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add sp, sp, t1 /* sp = (cpuid + 1) * __STACKSIZE__ + __stack_start__ */
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call rt_signal_check
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mv sp, a0
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#endif
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#endif
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/* resw ra to mepc */
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LOAD a0, 0 * REGBYTES(sp)
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csrw mepc, a0
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LOAD x1, 1 * REGBYTES(sp)
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li t0, 0x00001800
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csrs mstatus, t0
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LOAD a0, 2 * REGBYTES(sp)
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csrs mstatus, a0
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LOAD x4, 4 * REGBYTES(sp)
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LOAD x5, 5 * REGBYTES(sp)
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LOAD x6, 6 * REGBYTES(sp)
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LOAD x7, 7 * REGBYTES(sp)
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LOAD x8, 8 * REGBYTES(sp)
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LOAD x9, 9 * REGBYTES(sp)
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LOAD x10, 10 * REGBYTES(sp)
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LOAD x11, 11 * REGBYTES(sp)
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LOAD x12, 12 * REGBYTES(sp)
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LOAD x13, 13 * REGBYTES(sp)
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LOAD x14, 14 * REGBYTES(sp)
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LOAD x15, 15 * REGBYTES(sp)
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LOAD x16, 16 * REGBYTES(sp)
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LOAD x17, 17 * REGBYTES(sp)
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LOAD x18, 18 * REGBYTES(sp)
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LOAD x19, 19 * REGBYTES(sp)
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LOAD x20, 20 * REGBYTES(sp)
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LOAD x21, 21 * REGBYTES(sp)
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LOAD x22, 22 * REGBYTES(sp)
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LOAD x23, 23 * REGBYTES(sp)
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LOAD x24, 24 * REGBYTES(sp)
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LOAD x25, 25 * REGBYTES(sp)
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LOAD x26, 26 * REGBYTES(sp)
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LOAD x27, 27 * REGBYTES(sp)
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LOAD x28, 28 * REGBYTES(sp)
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LOAD x29, 29 * REGBYTES(sp)
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LOAD x30, 30 * REGBYTES(sp)
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LOAD x31, 31 * REGBYTES(sp)
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addi sp, sp, 32 * REGBYTES
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mret
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@ -1,130 +0,0 @@
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018/10/28 Bernard The unify RISC-V porting code.
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* 2022/12/08 WangShun Change the parameters of rt_hw_context_switch_interrupt
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include "cpuport.h"
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#ifndef RT_USING_SMP
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volatile rt_ubase_t rt_interrupt_from_thread = 0;
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volatile rt_ubase_t rt_interrupt_to_thread = 0;
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volatile rt_uint32_t rt_thread_switch_interrupt_flag = 0;
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#endif
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struct rt_hw_stack_frame
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{
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rt_ubase_t epc; /* epc - epc - program counter */
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rt_ubase_t ra; /* x1 - ra - return address for jumps */
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rt_ubase_t mstatus; /* - machine status register */
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rt_ubase_t gp; /* x3 - gp - global pointer */
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rt_ubase_t tp; /* x4 - tp - thread pointer */
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rt_ubase_t t0; /* x5 - t0 - temporary register 0 */
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rt_ubase_t t1; /* x6 - t1 - temporary register 1 */
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rt_ubase_t t2; /* x7 - t2 - temporary register 2 */
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rt_ubase_t s0_fp; /* x8 - s0/fp - saved register 0 or frame pointer */
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rt_ubase_t s1; /* x9 - s1 - saved register 1 */
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rt_ubase_t a0; /* x10 - a0 - return value or function argument 0 */
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rt_ubase_t a1; /* x11 - a1 - return value or function argument 1 */
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rt_ubase_t a2; /* x12 - a2 - function argument 2 */
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rt_ubase_t a3; /* x13 - a3 - function argument 3 */
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rt_ubase_t a4; /* x14 - a4 - function argument 4 */
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rt_ubase_t a5; /* x15 - a5 - function argument 5 */
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rt_ubase_t a6; /* x16 - a6 - function argument 6 */
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rt_ubase_t a7; /* x17 - s7 - function argument 7 */
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rt_ubase_t s2; /* x18 - s2 - saved register 2 */
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rt_ubase_t s3; /* x19 - s3 - saved register 3 */
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rt_ubase_t s4; /* x20 - s4 - saved register 4 */
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rt_ubase_t s5; /* x21 - s5 - saved register 5 */
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rt_ubase_t s6; /* x22 - s6 - saved register 6 */
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rt_ubase_t s7; /* x23 - s7 - saved register 7 */
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rt_ubase_t s8; /* x24 - s8 - saved register 8 */
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rt_ubase_t s9; /* x25 - s9 - saved register 9 */
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rt_ubase_t s10; /* x26 - s10 - saved register 10 */
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rt_ubase_t s11; /* x27 - s11 - saved register 11 */
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rt_ubase_t t3; /* x28 - t3 - temporary register 3 */
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rt_ubase_t t4; /* x29 - t4 - temporary register 4 */
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rt_ubase_t t5; /* x30 - t5 - temporary register 5 */
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rt_ubase_t t6; /* x31 - t6 - temporary register 6 */
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};
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/**
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* This function will initialize thread stack
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*
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* @param tentry the entry of thread
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* @param parameter the parameter of entry
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* @param stack_addr the beginning stack address
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* @param texit the function will be called when thread exit
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*
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* @return stack address
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*/
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rt_uint8_t *rt_hw_stack_init(void *tentry,
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void *parameter,
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rt_uint8_t *stack_addr,
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void *texit)
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{
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struct rt_hw_stack_frame *frame;
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rt_uint8_t *stk;
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int i;
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stk = stack_addr + sizeof(rt_ubase_t);
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stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_ubase_t)stk, REGBYTES);
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stk -= sizeof(struct rt_hw_stack_frame);
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frame = (struct rt_hw_stack_frame *)stk;
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for (i = 0; i < sizeof(struct rt_hw_stack_frame) / sizeof(rt_ubase_t); i++)
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{
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((rt_ubase_t *)frame)[i] = 0xdeadbeef;
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}
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frame->ra = (rt_ubase_t)texit;
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frame->a0 = (rt_ubase_t)parameter;
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frame->epc = (rt_ubase_t)tentry;
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/* force to machine mode(MPP=11) and set MPIE to 1 */
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frame->mstatus = 0x00007880;
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return stk;
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}
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/*
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* #ifdef RT_USING_SMP
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* void rt_hw_context_switch_interrupt(void *context, rt_ubase_t from, rt_ubase_t to, struct rt_thread *to_thread);
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* #else
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* void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to);
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* #endif
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*/
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#ifndef RT_USING_SMP
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void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to,rt_thread_t from_thread, rt_thread_t to_thread)
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{
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if (rt_thread_switch_interrupt_flag == 0)
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rt_interrupt_from_thread = from;
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rt_interrupt_to_thread = to;
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rt_thread_switch_interrupt_flag = 1;
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return ;
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}
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#endif /* end of RT_USING_SMP */
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/** shutdown CPU */
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void rt_hw_cpu_shutdown()
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{
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rt_uint32_t level;
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rt_kprintf("shutdown...\n");
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level = rt_hw_interrupt_disable();
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while (level)
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{
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RT_ASSERT(0);
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}
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}
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@ -1,25 +0,0 @@
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-10-03 Bernard The first version
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*/
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#ifndef CPUPORT_H__
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#define CPUPORT_H__
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/* bytes of register width */
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#ifdef ARCH_CPU_64BIT
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#define STORE sd
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#define LOAD ld
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#define REGBYTES 8
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#else
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#define STORE sw
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#define LOAD lw
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#define REGBYTES 4
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#endif
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#endif
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