From f2734c0a5438c57590217fbf7461c01a26eef9b2 Mon Sep 17 00:00:00 2001 From: iysheng Date: Thu, 10 Jun 2021 00:01:28 +0800 Subject: [PATCH] [bsp][gd32450z-eval] Formating files to pass the CI check --- .../CMSIS/GD/GD32F4xx/Include/gd32f4xx.h | 52 +++--- .../GD/GD32F4xx/Source/system_gd32f4xx.c | 156 +++++++++--------- bsp/gd32450z-eval/Libraries/CMSIS/core_cm4.h | 6 +- .../Libraries/CMSIS/core_cmFunc.h | 2 +- 4 files changed, 108 insertions(+), 108 deletions(-) diff --git a/bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Include/gd32f4xx.h b/bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Include/gd32f4xx.h index 6e704f8ed1..a901975bbd 100644 --- a/bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Include/gd32f4xx.h +++ b/bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Include/gd32f4xx.h @@ -1,7 +1,7 @@ /*! \file gd32f4xx.h \brief general definitions for GD32F4xx - + \version 2016-08-15, V1.0.0, firmware for GD32F4xx \version 2018-12-12, V2.0.0, firmware for GD32F4xx \version 2020-09-30, V2.1.0, firmware for GD32F4xx @@ -10,27 +10,27 @@ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -39,7 +39,7 @@ OF SUCH DAMAGE. #ifdef __cplusplus extern "C" { -#endif +#endif /* define GD32F4xx */ #if !defined (GD32F450) && !defined (GD32F405) && !defined (GD32F407) @@ -47,7 +47,7 @@ OF SUCH DAMAGE. /* #define GD32F405 */ /* #define GD32F407 */ #endif /* define GD32F4xx */ - + #if !defined (GD32F450) && !defined (GD32F405) && !defined (GD32F407) #error "Please select the target GD32F4xx device in gd32f4xx.h file" #endif /* undefine GD32F4xx tip */ @@ -63,7 +63,7 @@ OF SUCH DAMAGE. #endif /* high speed crystal oscillator startup timeout */ /* define value of internal 16MHz RC oscillator (IRC16M) in Hz */ -#if !defined (IRC16M_VALUE) +#if !defined (IRC16M_VALUE) #define IRC16M_VALUE ((uint32_t)16000000) #endif /* internal 16MHz RC oscillator value */ @@ -73,12 +73,12 @@ OF SUCH DAMAGE. #endif /* internal 16MHz RC oscillator startup timeout */ /* define value of internal 32KHz RC oscillator(IRC32K) in Hz */ -#if !defined (IRC32K_VALUE) +#if !defined (IRC32K_VALUE) #define IRC32K_VALUE ((uint32_t)32000) #endif /* internal 32KHz RC oscillator value */ /* define value of low speed crystal oscillator (LXTAL)in Hz */ -#if !defined (LXTAL_VALUE) +#if !defined (LXTAL_VALUE) #define LXTAL_VALUE ((uint32_t)32768) #endif /* low speed crystal oscillator value */ @@ -89,7 +89,7 @@ OF SUCH DAMAGE. #define __GD32F4xx_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:24] main version */ #define __GD32F4xx_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ #define __GD32F4xx_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ -#define __GD32F4xx_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __GD32F4xx_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __GD32F4xx_STDPERIPH_VERSION ((__GD32F4xx_STDPERIPH_VERSION_MAIN << 24)\ |(__GD32F4xx_STDPERIPH_VERSION_SUB1 << 16)\ |(__GD32F4xx_STDPERIPH_VERSION_SUB2 << 8)\ @@ -162,7 +162,7 @@ typedef enum IRQn TIMER7_TRG_CMT_TIMER13_IRQn = 45, /*!< TIMER7 trigger and commutation and TIMER13 interrupts */ TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupt */ DMA0_Channel7_IRQn = 47, /*!< DMA0 channel7 interrupt */ - + #if defined (GD32F450) EXMC_IRQn = 48, /*!< EXMC interrupt */ SDIO_IRQn = 49, /*!< SDIO interrupt */ @@ -294,7 +294,7 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; #define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr)) #define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr)) #define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) -#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) +#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) #define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) /* main flash and SRAM memory map */ @@ -355,7 +355,7 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; /* define marco USE_STDPERIPH_DRIVER */ #if !defined USE_STDPERIPH_DRIVER #define USE_STDPERIPH_DRIVER -#endif +#endif #ifdef USE_STDPERIPH_DRIVER #include "gd32f4xx_libopt.h" #endif /* USE_STDPERIPH_DRIVER */ @@ -363,4 +363,4 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; #ifdef cplusplus } #endif -#endif +#endif diff --git a/bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Source/system_gd32f4xx.c b/bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Source/system_gd32f4xx.c index 058dcadca2..2ea97ae3f8 100644 --- a/bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Source/system_gd32f4xx.c +++ b/bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Source/system_gd32f4xx.c @@ -59,7 +59,7 @@ #define RCU_MODIFY {volatile uint32_t i; \ RCU_CFG0 |= RCU_AHB_CKSYS_DIV2; \ for(i=0;i<50000;i++);} - + /* set the system clock frequency and declare the system clock configuration function */ #ifdef __SYSTEM_CLOCK_IRC16M uint32_t SystemCoreClock = __SYSTEM_CLOCK_IRC16M; @@ -117,7 +117,7 @@ void SystemInit (void) RCU_CTL |= RCU_CTL_IRC16MEN; RCU_MODIFY - + /* Reset CFG0 register */ RCU_CFG0 = 0x00000000U; @@ -132,8 +132,8 @@ void SystemInit (void) /* Disable all interrupts */ RCU_INT = 0x00000000U; - - /* Configure the System clock source, PLL Multiplier and Divider factors, + + /* Configure the System clock source, PLL Multiplier and Divider factors, AHB/APBx prescalers and Flash settings ----------------------------------*/ system_clock_config(); } @@ -167,7 +167,7 @@ static void system_clock_config(void) system_clock_200m_8m_hxtal(); #elif defined (__SYSTEM_CLOCK_200M_PLL_25M_HXTAL) system_clock_200m_25m_hxtal(); -#endif /* __SYSTEM_CLOCK_IRC16M */ +#endif /* __SYSTEM_CLOCK_IRC16M */ } #ifdef __SYSTEM_CLOCK_IRC16M @@ -181,33 +181,33 @@ static void system_clock_16m_irc16m(void) { uint32_t timeout = 0U; uint32_t stab_flag = 0U; - + /* enable IRC16M */ RCU_CTL |= RCU_CTL_IRC16MEN; - + /* wait until IRC16M is stable or the startup time is longer than IRC16M_STARTUP_TIMEOUT */ do{ timeout++; stab_flag = (RCU_CTL & RCU_CTL_IRC16MSTB); }while((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout)); - + /* if fail */ if(0U == (RCU_CTL & RCU_CTL_IRC16MSTB)){ while(1){ } } - + /* AHB = SYSCLK */ RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; /* APB2 = AHB */ RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; /* APB1 = AHB */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV1; - + /* select IRC16M as system clock */ RCU_CFG0 &= ~RCU_CFG0_SCS; RCU_CFG0 |= RCU_CKSYSSRC_IRC16M; - + /* wait until IRC16M is selected as system clock */ while(0 != (RCU_CFG0 & RCU_SCSS_IRC16M)){ } @@ -224,33 +224,33 @@ static void system_clock_hxtal(void) { uint32_t timeout = 0U; uint32_t stab_flag = 0U; - + /* enable HXTAL */ RCU_CTL |= RCU_CTL_HXTALEN; - + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ do{ timeout++; stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - + /* if fail */ if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ while(1){ } } - + /* AHB = SYSCLK */ RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; /* APB2 = AHB */ RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; /* APB1 = AHB */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV1; - + /* select HXTAL as system clock */ RCU_CFG0 &= ~RCU_CFG0_SCS; RCU_CFG0 |= RCU_CKSYSSRC_HXTAL; - + /* wait until HXTAL is selected as system clock */ while(0 == (RCU_CFG0 & RCU_SCSS_HXTAL)){ } @@ -267,7 +267,7 @@ static void system_clock_120m_irc16m(void) { uint32_t timeout = 0U; uint32_t stab_flag = 0U; - + /* enable IRC16M */ RCU_CTL |= RCU_CTL_IRC16MEN; @@ -282,7 +282,7 @@ static void system_clock_120m_irc16m(void) while(1){ } } - + RCU_APB1EN |= RCU_APB1EN_PMUEN; PMU_CTL |= PMU_CTL_LDOVS; @@ -294,7 +294,7 @@ static void system_clock_120m_irc16m(void) /* APB1 = AHB/4 */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; - /* Configure the main PLL, PSC = 16, PLL_N = 240, PLL_P = 2, PLL_Q = 5 */ + /* Configure the main PLL, PSC = 16, PLL_N = 240, PLL_P = 2, PLL_Q = 5 */ RCU_PLL = (16U | (240U << 6U) | (((2U >> 1U) - 1U) << 16U) | (RCU_PLLSRC_IRC16M) | (5U << 24U)); @@ -304,17 +304,17 @@ static void system_clock_120m_irc16m(void) /* wait until PLL is stable */ while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ } - + /* Enable the high-drive to extend the clock frequency to 120 Mhz */ PMU_CTL |= PMU_CTL_HDEN; while(0U == (PMU_CS & PMU_CS_HDRF)){ } - + /* select the high-drive mode */ PMU_CTL |= PMU_CTL_HDS; while(0U == (PMU_CS & PMU_CS_HDSRF)){ - } - + } + /* select PLL as system clock */ RCU_CFG0 &= ~RCU_CFG0_SCS; RCU_CFG0 |= RCU_CKSYSSRC_PLLP; @@ -335,7 +335,7 @@ static void system_clock_120m_8m_hxtal(void) { uint32_t timeout = 0U; uint32_t stab_flag = 0U; - + /* enable HXTAL */ RCU_CTL |= RCU_CTL_HXTALEN; @@ -350,7 +350,7 @@ static void system_clock_120m_8m_hxtal(void) while(1){ } } - + RCU_APB1EN |= RCU_APB1EN_PMUEN; PMU_CTL |= PMU_CTL_LDOVS; @@ -362,7 +362,7 @@ static void system_clock_120m_8m_hxtal(void) /* APB1 = AHB/4 */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; - /* Configure the main PLL, PSC = 8, PLL_N = 240, PLL_P = 2, PLL_Q = 5 */ + /* Configure the main PLL, PSC = 8, PLL_N = 240, PLL_P = 2, PLL_Q = 5 */ RCU_PLL = (8U | (240U << 6U) | (((2U >> 1U) - 1U) << 16U) | (RCU_PLLSRC_HXTAL) | (5U << 24U)); @@ -372,17 +372,17 @@ static void system_clock_120m_8m_hxtal(void) /* wait until PLL is stable */ while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ } - + /* Enable the high-drive to extend the clock frequency to 120 Mhz */ PMU_CTL |= PMU_CTL_HDEN; while(0U == (PMU_CS & PMU_CS_HDRF)){ } - + /* select the high-drive mode */ PMU_CTL |= PMU_CTL_HDS; while(0U == (PMU_CS & PMU_CS_HDSRF)){ - } - + } + /* select PLL as system clock */ RCU_CFG0 &= ~RCU_CFG0_SCS; RCU_CFG0 |= RCU_CKSYSSRC_PLLP; @@ -403,7 +403,7 @@ static void system_clock_120m_25m_hxtal(void) { uint32_t timeout = 0U; uint32_t stab_flag = 0U; - + /* enable HXTAL */ RCU_CTL |= RCU_CTL_HXTALEN; @@ -418,7 +418,7 @@ static void system_clock_120m_25m_hxtal(void) while(1){ } } - + RCU_APB1EN |= RCU_APB1EN_PMUEN; PMU_CTL |= PMU_CTL_LDOVS; @@ -430,7 +430,7 @@ static void system_clock_120m_25m_hxtal(void) /* APB1 = AHB/4 */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; - /* Configure the main PLL, PSC = 25, PLL_N = 240, PLL_P = 2, PLL_Q = 5 */ + /* Configure the main PLL, PSC = 25, PLL_N = 240, PLL_P = 2, PLL_Q = 5 */ RCU_PLL = (25U | (240U << 6U) | (((2U >> 1U) - 1U) << 16U) | (RCU_PLLSRC_HXTAL) | (5U << 24U)); @@ -440,17 +440,17 @@ static void system_clock_120m_25m_hxtal(void) /* wait until PLL is stable */ while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ } - + /* Enable the high-drive to extend the clock frequency to 120 Mhz */ PMU_CTL |= PMU_CTL_HDEN; while(0U == (PMU_CS & PMU_CS_HDRF)){ } - + /* select the high-drive mode */ PMU_CTL |= PMU_CTL_HDS; while(0U == (PMU_CS & PMU_CS_HDSRF)){ - } - + } + /* select PLL as system clock */ RCU_CFG0 &= ~RCU_CFG0_SCS; RCU_CFG0 |= RCU_CKSYSSRC_PLLP; @@ -471,7 +471,7 @@ static void system_clock_168m_irc16m(void) { uint32_t timeout = 0U; uint32_t stab_flag = 0U; - + /* enable IRC16M */ RCU_CTL |= RCU_CTL_IRC16MEN; @@ -486,7 +486,7 @@ static void system_clock_168m_irc16m(void) while(1){ } } - + RCU_APB1EN |= RCU_APB1EN_PMUEN; PMU_CTL |= PMU_CTL_LDOVS; @@ -498,7 +498,7 @@ static void system_clock_168m_irc16m(void) /* APB1 = AHB/4 */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; - /* Configure the main PLL, PSC = 16, PLL_N = 336, PLL_P = 2, PLL_Q = 7 */ + /* Configure the main PLL, PSC = 16, PLL_N = 336, PLL_P = 2, PLL_Q = 7 */ RCU_PLL = (16U | (336U << 6U) | (((2U >> 1U) - 1U) << 16U) | (RCU_PLLSRC_IRC16M) | (7U << 24U)); @@ -508,17 +508,17 @@ static void system_clock_168m_irc16m(void) /* wait until PLL is stable */ while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ } - + /* Enable the high-drive to extend the clock frequency to 168 Mhz */ PMU_CTL |= PMU_CTL_HDEN; while(0U == (PMU_CS & PMU_CS_HDRF)){ } - + /* select the high-drive mode */ PMU_CTL |= PMU_CTL_HDS; while(0U == (PMU_CS & PMU_CS_HDSRF)){ - } - + } + /* select PLL as system clock */ RCU_CFG0 &= ~RCU_CFG0_SCS; RCU_CFG0 |= RCU_CKSYSSRC_PLLP; @@ -538,7 +538,7 @@ static void system_clock_168m_irc16m(void) static void system_clock_168m_8m_hxtal(void) { uint32_t timeout = 0U; - + /* enable HXTAL */ RCU_CTL |= RCU_CTL_HXTALEN; @@ -562,7 +562,7 @@ static void system_clock_168m_8m_hxtal(void) /* APB1 = AHB/4 */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; - /* Configure the main PLL, PSC = 8, PLL_N = 336, PLL_P = 2, PLL_Q = 7 */ + /* Configure the main PLL, PSC = 8, PLL_N = 336, PLL_P = 2, PLL_Q = 7 */ RCU_PLL = (8U | (336 << 6U) | (((2 >> 1U) -1U) << 16U) | (RCU_PLLSRC_HXTAL) | (7 << 24U)); @@ -572,12 +572,12 @@ static void system_clock_168m_8m_hxtal(void) /* wait until PLL is stable */ while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ } - + /* Enable the high-drive to extend the clock frequency to 168 Mhz */ PMU_CTL |= PMU_CTL_HDEN; while(0U == (PMU_CS & PMU_CS_HDRF)){ } - + /* select the high-drive mode */ PMU_CTL |= PMU_CTL_HDS; while(0U == (PMU_CS & PMU_CS_HDSRF)){ @@ -603,7 +603,7 @@ static void system_clock_168m_25m_hxtal(void) { uint32_t timeout = 0U; uint32_t stab_flag = 0U; - + /* enable HXTAL */ RCU_CTL |= RCU_CTL_HXTALEN; @@ -618,7 +618,7 @@ static void system_clock_168m_25m_hxtal(void) while(1){ } } - + RCU_APB1EN |= RCU_APB1EN_PMUEN; PMU_CTL |= PMU_CTL_LDOVS; @@ -630,7 +630,7 @@ static void system_clock_168m_25m_hxtal(void) /* APB1 = AHB */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; - /* Configure the main PLL, PSC = 25, PLL_N = 336, PLL_P = 2, PLL_Q = 7 */ + /* Configure the main PLL, PSC = 25, PLL_N = 336, PLL_P = 2, PLL_Q = 7 */ RCU_PLL = (25U | (336U << 6U) | (((2U >> 1U) - 1U) << 16U) | (RCU_PLLSRC_HXTAL) | (7U << 24U)); @@ -640,17 +640,17 @@ static void system_clock_168m_25m_hxtal(void) /* wait until PLL is stable */ while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ } - + /* Enable the high-drive to extend the clock frequency to 168 Mhz */ PMU_CTL |= PMU_CTL_HDEN; while(0U == (PMU_CS & PMU_CS_HDRF)){ } - + /* select the high-drive mode */ PMU_CTL |= PMU_CTL_HDS; while(0U == (PMU_CS & PMU_CS_HDSRF)){ - } - + } + /* select PLL as system clock */ RCU_CFG0 &= ~RCU_CFG0_SCS; RCU_CFG0 |= RCU_CKSYSSRC_PLLP; @@ -671,7 +671,7 @@ static void system_clock_200m_irc16m(void) { uint32_t timeout = 0U; uint32_t stab_flag = 0U; - + /* enable IRC16M */ RCU_CTL |= RCU_CTL_IRC16MEN; @@ -686,7 +686,7 @@ static void system_clock_200m_irc16m(void) while(1){ } } - + RCU_APB1EN |= RCU_APB1EN_PMUEN; PMU_CTL |= PMU_CTL_LDOVS; @@ -698,7 +698,7 @@ static void system_clock_200m_irc16m(void) /* APB1 = AHB/4 */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; - /* Configure the main PLL, PSC = 16, PLL_N = 400, PLL_P = 2, PLL_Q = 9 */ + /* Configure the main PLL, PSC = 16, PLL_N = 400, PLL_P = 2, PLL_Q = 9 */ RCU_PLL = (16U | (400U << 6U) | (((2U >> 1U) - 1U) << 16U) | (RCU_PLLSRC_IRC16M) | (9U << 24U)); @@ -708,17 +708,17 @@ static void system_clock_200m_irc16m(void) /* wait until PLL is stable */ while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ } - + /* Enable the high-drive to extend the clock frequency to 200 Mhz */ PMU_CTL |= PMU_CTL_HDEN; while(0U == (PMU_CS & PMU_CS_HDRF)){ } - + /* select the high-drive mode */ PMU_CTL |= PMU_CTL_HDS; while(0U == (PMU_CS & PMU_CS_HDSRF)){ - } - + } + /* select PLL as system clock */ RCU_CFG0 &= ~RCU_CFG0_SCS; RCU_CFG0 |= RCU_CKSYSSRC_PLLP; @@ -739,7 +739,7 @@ static void system_clock_200m_8m_hxtal(void) { uint32_t timeout = 0U; uint32_t stab_flag = 0U; - + /* enable HXTAL */ RCU_CTL |= RCU_CTL_HXTALEN; @@ -754,7 +754,7 @@ static void system_clock_200m_8m_hxtal(void) while(1){ } } - + RCU_APB1EN |= RCU_APB1EN_PMUEN; PMU_CTL |= PMU_CTL_LDOVS; @@ -766,7 +766,7 @@ static void system_clock_200m_8m_hxtal(void) /* APB1 = AHB/4 */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; - /* Configure the main PLL, PSC = 8, PLL_N = 400, PLL_P = 2, PLL_Q = 9 */ + /* Configure the main PLL, PSC = 8, PLL_N = 400, PLL_P = 2, PLL_Q = 9 */ RCU_PLL = (8U | (400U << 6U) | (((2U >> 1U) - 1U) << 16U) | (RCU_PLLSRC_HXTAL) | (9U << 24U)); @@ -776,17 +776,17 @@ static void system_clock_200m_8m_hxtal(void) /* wait until PLL is stable */ while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ } - + /* Enable the high-drive to extend the clock frequency to 200 Mhz */ PMU_CTL |= PMU_CTL_HDEN; while(0U == (PMU_CS & PMU_CS_HDRF)){ } - + /* select the high-drive mode */ PMU_CTL |= PMU_CTL_HDS; while(0U == (PMU_CS & PMU_CS_HDSRF)){ - } - + } + /* select PLL as system clock */ RCU_CFG0 &= ~RCU_CFG0_SCS; RCU_CFG0 |= RCU_CKSYSSRC_PLLP; @@ -807,7 +807,7 @@ static void system_clock_200m_25m_hxtal(void) { uint32_t timeout = 0U; uint32_t stab_flag = 0U; - + /* enable HXTAL */ RCU_CTL |= RCU_CTL_HXTALEN; @@ -822,7 +822,7 @@ static void system_clock_200m_25m_hxtal(void) while(1){ } } - + RCU_APB1EN |= RCU_APB1EN_PMUEN; PMU_CTL |= PMU_CTL_LDOVS; @@ -834,7 +834,7 @@ static void system_clock_200m_25m_hxtal(void) /* APB1 = AHB/4 */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; - /* Configure the main PLL, PSC = 25, PLL_N = 400, PLL_P = 2, PLL_Q = 9 */ + /* Configure the main PLL, PSC = 25, PLL_N = 400, PLL_P = 2, PLL_Q = 9 */ RCU_PLL = (25U | (400U << 6U) | (((2U >> 1U) - 1U) << 16U) | (RCU_PLLSRC_HXTAL) | (9U << 24U)); @@ -844,17 +844,17 @@ static void system_clock_200m_25m_hxtal(void) /* wait until PLL is stable */ while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ } - + /* Enable the high-drive to extend the clock frequency to 200 Mhz */ PMU_CTL |= PMU_CTL_HDEN; while(0U == (PMU_CS & PMU_CS_HDRF)){ } - + /* select the high-drive mode */ PMU_CTL |= PMU_CTL_HDS; while(0U == (PMU_CS & PMU_CS_HDSRF)){ - } - + } + /* select PLL as system clock */ RCU_CFG0 &= ~RCU_CFG0_SCS; RCU_CFG0 |= RCU_CKSYSSRC_PLLP; @@ -875,7 +875,7 @@ void SystemCoreClockUpdate (void) { uint32_t sws; uint32_t pllpsc, plln, pllsel, pllp, ck_src, idx, clk_exp; - + /* exponent of AHB, APB1 and APB2 clock divider */ const uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; diff --git a/bsp/gd32450z-eval/Libraries/CMSIS/core_cm4.h b/bsp/gd32450z-eval/Libraries/CMSIS/core_cm4.h index d82841442c..e3cd89f728 100644 --- a/bsp/gd32450z-eval/Libraries/CMSIS/core_cm4.h +++ b/bsp/gd32450z-eval/Libraries/CMSIS/core_cm4.h @@ -100,7 +100,7 @@ #define __INLINE inline /*!< inline keyword for TASKING Compiler */ #define __STATIC_INLINE static inline -#elif defined ( __CSMC__ ) /* Cosmic */ +#elif defined ( __CSMC__ ) /* Cosmic */ #define __packed #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ @@ -170,8 +170,8 @@ #define __FPU_USED 0 #endif -#elif defined ( __CSMC__ ) /* Cosmic */ - #if ( __CSMC__ & 0x400) // FPU present for parser +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser #if (__FPU_PRESENT == 1) #define __FPU_USED 1 #else diff --git a/bsp/gd32450z-eval/Libraries/CMSIS/core_cmFunc.h b/bsp/gd32450z-eval/Libraries/CMSIS/core_cmFunc.h index b6ad0a4c5f..834bd17645 100644 --- a/bsp/gd32450z-eval/Libraries/CMSIS/core_cmFunc.h +++ b/bsp/gd32450z-eval/Libraries/CMSIS/core_cmFunc.h @@ -552,7 +552,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t v /** \brief Set Base Priority with condition This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. + or the new value increases the BASEPRI priority level. \param [in] basePri Base Priority value to set */