delete the useless files and update the file headers
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2186 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
dzzxzz@gmail.com
parent
aea59143b5
commit
f1e6f2f6ca
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/*
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* File : application.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006-2011, RT-Thread Develop Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2010-06-25 Bernard first version
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* 2011-08-08 lgnq modified for Loongson LS1B
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*/
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#include <rtthread.h>
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#include <ls1b.h>
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#ifdef RT_USING_RTGUI
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#include <rtgui/rtgui.h>
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extern void rt_hw_dc_init(void);
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#endif
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void rt_init_thread_entry(void* parameter)
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{
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#ifdef RT_USING_RTGUI
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{
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rt_device_t dc;
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/* init Display Controller */
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rt_hw_dc_init();
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/* re-init device driver */
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rt_device_init_all();
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/* find Display Controller device */
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dc = rt_device_find("dc");
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/* set Display Controller device as rtgui graphic driver */
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rtgui_graphic_set_device(dc);
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/* startup rtgui */
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rtgui_startup();
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}
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#endif
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}
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int rt_application_init()
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{
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rt_thread_t tid;
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/* create initialization thread */
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tid = rt_thread_create("init",
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rt_init_thread_entry, RT_NULL,
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4096, 8, 20);
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if (tid != RT_NULL)
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rt_thread_startup(tid);
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return 0;
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}
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@ -1,105 +0,0 @@
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/*
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* File : board.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006-2011, RT-Thread Develop Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2010-06-25 Bernard first version
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* 2011-08-08 lgnq modified for Loongson LS1B
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*/
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#include <rtthread.h>
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#include <rthw.h>
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#include "board.h"
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#include "uart.h"
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#include "ls1b.h"
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/**
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* @addtogroup Loongson LS1B
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*/
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/*@{*/
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/**
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* This is the timer interrupt service routine.
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*/
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void rt_hw_timer_handler(void)
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{
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unsigned int count;
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count = read_c0_compare();
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write_c0_compare(count);
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write_c0_count(0);
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/* increase a OS tick */
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rt_tick_increase();
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}
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/**
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* This function will initial OS timer
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*/
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void rt_hw_timer_init(void)
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{
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write_c0_compare(CPU_HZ/2/RT_TICK_PER_SECOND);
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write_c0_count(0);
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}
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/**
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* This function will initial sam7s64 board.
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*/
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void rt_hw_board_init(void)
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{
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#ifdef RT_USING_UART
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/* init hardware UART device */
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rt_hw_uart_init();
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#endif
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#ifdef RT_USING_CONSOLE
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/* set console device */
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rt_console_set_device("uart0");
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#endif
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/* init operating system timer */
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rt_hw_timer_init();
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rt_kprintf("current sr: 0x%08x\n", read_c0_status());
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}
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/* UART line status register value */
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#define UARTLSR_ERROR (1 << 7)
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#define UARTLSR_TE (1 << 6)
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#define UARTLSR_TFE (1 << 5)
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#define UARTLSR_BI (1 << 4)
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#define UARTLSR_FE (1 << 3)
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#define UARTLSR_PE (1 << 2)
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#define UARTLSR_OE (1 << 1)
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#define UARTLSR_DR (1 << 0)
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void rt_hw_console_output(const char* ptr)
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{
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/* stream mode */
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while (*ptr)
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{
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if (*ptr == '\n')
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{
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/* FIFO status, contain valid data */
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while (!(UART_LSR(UART0_BASE) & (UARTLSR_TE | UARTLSR_TFE)));
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/* write data */
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UART_DAT(UART0_BASE) = '\r';
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}
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/* FIFO status, contain valid data */
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while (!(UART_LSR(UART0_BASE) & (UARTLSR_TE | UARTLSR_TFE)));
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/* write data */
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UART_DAT(UART0_BASE) = *ptr;
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ptr ++;
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}
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}
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/*@}*/
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/*
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* File : board.h
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006-2011, RT-Thread Develop Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2010-06-25 Bernard first version
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* 2011-08-08 lgnq modified for Loongson LS1B
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*/
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#ifndef __BOARD_H__
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#define __BOARD_H__
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void rt_hw_board_init(void);
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/* 64M SDRAM */
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#define RT_HW_HEAP_END (0x80000000 + 64 * 1024 * 1024)
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#define CPU_HZ (125 * 1000000)
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#endif
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/*
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* File : display_controller.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006-2011, RT-Thread Develop Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2011-08-09 lgnq first version for LS1B DC
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*/
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#include <rtthread.h>
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#include "display_controller.h"
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struct vga_struct vga_mode[] =
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{
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{/*"640x480_70.00"*/ 28560, 640, 664, 728, 816, 480, 481, 484, 500, },
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{/*"640x640_60.00"*/ 33100, 640, 672, 736, 832, 640, 641, 644, 663, },
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{/*"640x768_60.00"*/ 39690, 640, 672, 736, 832, 768, 769, 772, 795, },
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{/*"640x800_60.00"*/ 42130, 640, 680, 744, 848, 800, 801, 804, 828, },
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{/*"800x480_70.00"*/ 35840, 800, 832, 912, 1024, 480, 481, 484, 500, },
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{/*"800x600_60.00"*/ 38220, 800, 832, 912, 1024, 600, 601, 604, 622, },
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{/*"800x640_60.00"*/ 40730, 800, 832, 912, 1024, 640, 641, 644, 663, },
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{/*"832x600_60.00"*/ 40010, 832, 864, 952, 1072, 600, 601, 604, 622, },
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{/*"832x608_60.00"*/ 40520, 832, 864, 952, 1072, 608, 609, 612, 630, },
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{/*"1024x480_60.00"*/ 38170, 1024, 1048, 1152, 1280, 480, 481, 484, 497, },
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{/*"1024x600_60.00"*/ 48960, 1024, 1064, 1168, 1312, 600, 601, 604, 622, },
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{/*"1024x640_60.00"*/ 52830, 1024, 1072, 1176, 1328, 640, 641, 644, 663, },
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{/*"1024x768_60.00"*/ 64110, 1024, 1080, 1184, 1344, 768, 769, 772, 795, },
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{/*"1152x764_60.00"*/ 71380, 1152, 1208, 1328, 1504, 764, 765, 768, 791, },
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{/*"1280x800_60.00"*/ 83460, 1280, 1344, 1480, 1680, 800, 801, 804, 828, },
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{/*"1280x1024_55.00"*/ 98600, 1280, 1352, 1488, 1696, 1024, 1025, 1028, 1057, },
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{/*"1440x800_60.00"*/ 93800, 1440, 1512, 1664, 1888, 800, 801, 804, 828, },
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{/*"1440x900_67.00"*/ 120280, 1440, 1528, 1680, 1920, 900, 901, 904, 935, },
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};
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ALIGN(16)
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volatile rt_uint16_t _rt_framebuffer[FB_YSIZE][FB_XSIZE];
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static struct rt_device_graphic_info _dc_info;
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#define abs(x) ((x<0)?(-x):x)
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#define min(a,b) ((a<b)?a:b)
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int caclulate_freq(long long XIN, long long PCLK)
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{
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int i;
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long long clk, clk1;
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int start, end;
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int mi;
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int pll,ctrl,div,div1,frac;
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pll = PLL_FREQ;
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ctrl = PLL_DIV_PARAM;
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rt_kprintf("pll=0x%x, ctrl=0x%x\n", pll, ctrl);
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// rt_kprintf("cpu freq is %d\n", tgt_pipefreq());
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start = -1;
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end = 1;
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for (i=start; i<=end; i++)
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{
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clk = (12+i+(pll&0x3f))*33333333/2;
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div = clk/(long)PCLK/1000;
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clk1 = (12+i+1+(pll&0x3f))*33333333/2;
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div1 = clk1/(long)PCLK/1000;
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if (div!=div1)
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break;
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}
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if (div!=div1)
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{
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frac = ((PCLK*1000*div1)*2*1024/33333333 - (12+i+(pll&0x3f))*1024)&0x3ff;
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pll = (pll & ~0x3ff3f)|(frac<<8)|((pll&0x3f)+i);
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ctrl = ctrl&~(0x1f<<26)|(div1<<26)|(1<<31);
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}
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else
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{
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clk = (12+start+(pll&0x3f))*33333333/2;
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clk1 = (12+end+(pll&0x3f))*33333333/2;
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if (abs((long)clk/div/1000-PCLK)<abs((long)clk1/(div+1)/1000-PCLK))
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{
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pll = (pll & ~0x3ff3f)|((pll&0x3f)+start);
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ctrl = ctrl&~(0x1f<<26)|(div<<26)|(1<<31);
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}
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else
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{
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pll = (pll & ~0x3ff3f)|((pll&0x3f)+end);
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ctrl = ctrl&~(0x1f<<26)|((div+1)<<26)|(1<<31);
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}
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}
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rt_kprintf("new pll=0x%x, ctrl=0x%x\n", pll, ctrl);
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ctrl |= 0x2a00;
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PLL_DIV_PARAM = ctrl;
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PLL_FREQ = pll;
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rt_thread_delay(10);
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// initserial(0);
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// _probe_frequencies();
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// rt_kprintf("cpu freq is %d\n",tgt_pipefreq());
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return 0;
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}
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static rt_err_t rt_dc_init(rt_device_t dev)
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{
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int i, out, mode=-1;
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int val;
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for (i=0; i<sizeof(vga_mode)/sizeof(struct vga_struct); i++)
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{
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if (vga_mode[i].hr == FB_XSIZE && vga_mode[i].vr == FB_YSIZE)
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{
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mode=i;
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#ifdef LS1FSOC
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// out = caclulatefreq(APB_CLK/1000,vga_mode[i].pclk);
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// rt_kprintf("out=%x\n",out);
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/*inner gpu dc logic fifo pll ctrl,must large then outclk*/
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// *(volatile int *)0xbfd00414 = out+1;
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/*output pix1 clock pll ctrl*/
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// *(volatile int *)0xbfd00410 = out;
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/*output pix2 clock pll ctrl */
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// *(volatile int *)0xbfd00424 = out;
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#else
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caclulate_freq(APB_CLK/1000, vga_mode[i].pclk);
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#endif
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break;
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}
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}
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if (mode<0)
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{
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rt_kprintf("\n\n\nunsupported framebuffer resolution\n\n\n");
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return;
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}
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DC_FB_CONFIG = 0x0;
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DC_FB_CONFIG = 0x3; // // framebuffer configuration RGB565
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DC_FB_BUFFER_ADDR0 = (rt_uint32_t)_rt_framebuffer - 0x80000000;
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DC_FB_BUFFER_ADDR1 = (rt_uint32_t)_rt_framebuffer - 0x80000000;
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DC_DITHER_CONFIG = 0x0;
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DC_DITHER_TABLE_LOW = 0x0;
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DC_DITHER_TABLE_HIGH = 0x0;
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DC_PANEL_CONFIG = 0x80001311;
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DC_PANEL_TIMING = 0x0;
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DC_HDISPLAY = (vga_mode[mode].hfl<<16) | vga_mode[mode].hr;
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DC_HSYNC = 0x40000000 | (vga_mode[mode].hse<<16) | vga_mode[mode].hss;
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DC_VDISPLAY = (vga_mode[mode].vfl<<16) | vga_mode[mode].vr;
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DC_VSYNC = 0x40000000 | (vga_mode[mode].vse<<16) | vga_mode[mode].vss;
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#if defined(CONFIG_VIDEO_32BPP)
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DC_FB_CONFIG = 0x00100104;
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DC_FB_BUFFER_STRIDE = FB_XSIZE*4;
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#elif defined(CONFIG_VIDEO_16BPP)
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DC_FB_CONFIG = 0x00100103;
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DC_FB_BUFFER_STRIDE = (FB_XSIZE*2+255)&(~255);
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#elif defined(CONFIG_VIDEO_15BPP)
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DC_FB_CONFIG = 0x00100102;
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DC_FB_BUFFER_STRIDE = FB_XSIZE*2;
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#elif defined(CONFIG_VIDEO_12BPP)
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DC_FB_CONFIG = 0x00100101;
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DC_FB_BUFFER_STRIDE = FB_XSIZE*2;
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#else //640x480-32Bits
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DC_FB_CONFIG = 0x00100104;
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DC_FB_BUFFER_STRIDE = FB_XSIZE*4;
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#endif //32Bits
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#ifdef LS1GSOC
|
|
||||||
/*fix ls1g dc
|
|
||||||
*first switch to tile mode
|
|
||||||
*change origin register to 0
|
|
||||||
*goback nomal mode
|
|
||||||
*/
|
|
||||||
{
|
|
||||||
val = DC_FB_CONFIG;
|
|
||||||
DC_FB_CONFIG = val | 0x10;
|
|
||||||
DC_FB_BUFFER_ORIGIN = 0;
|
|
||||||
DC_FB_BUFFER_ORIGIN;
|
|
||||||
rt_thread_delay(10);
|
|
||||||
DC_FB_CONFIG;
|
|
||||||
DC_FB_CONFIG = val;
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
return RT_EOK;
|
|
||||||
}
|
|
||||||
|
|
||||||
static rt_err_t rt_dc_control(rt_device_t dev, rt_uint8_t cmd, void *args)
|
|
||||||
{
|
|
||||||
switch (cmd)
|
|
||||||
{
|
|
||||||
case RTGRAPHIC_CTRL_RECT_UPDATE:
|
|
||||||
break;
|
|
||||||
case RTGRAPHIC_CTRL_POWERON:
|
|
||||||
break;
|
|
||||||
case RTGRAPHIC_CTRL_POWEROFF:
|
|
||||||
break;
|
|
||||||
case RTGRAPHIC_CTRL_GET_INFO:
|
|
||||||
rt_memcpy(args, &_dc_info, sizeof(_dc_info));
|
|
||||||
break;
|
|
||||||
case RTGRAPHIC_CTRL_SET_MODE:
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
return RT_EOK;
|
|
||||||
}
|
|
||||||
|
|
||||||
void rt_hw_dc_init(void)
|
|
||||||
{
|
|
||||||
rt_device_t dc = rt_malloc(sizeof(struct rt_device));
|
|
||||||
if (dc == RT_NULL)
|
|
||||||
{
|
|
||||||
rt_kprintf("dc == RT_NULL\n");
|
|
||||||
return; /* no memory yet */
|
|
||||||
}
|
|
||||||
|
|
||||||
_dc_info.bits_per_pixel = 16;
|
|
||||||
_dc_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P;
|
|
||||||
_dc_info.framebuffer = (rt_uint8_t*)HW_FB_ADDR;
|
|
||||||
_dc_info.width = FB_XSIZE;
|
|
||||||
_dc_info.height = FB_YSIZE;
|
|
||||||
|
|
||||||
/* init device structure */
|
|
||||||
dc->type = RT_Device_Class_Graphic;
|
|
||||||
dc->init = rt_dc_init;
|
|
||||||
dc->open = RT_NULL;
|
|
||||||
dc->close = RT_NULL;
|
|
||||||
dc->control = rt_dc_control;
|
|
||||||
dc->user_data = (void*)&_dc_info;
|
|
||||||
|
|
||||||
/* register Display Controller device to RT-Thread */
|
|
||||||
rt_device_register(dc, "dc", RT_DEVICE_FLAG_RDWR);
|
|
||||||
}
|
|
||||||
|
|
@ -1,58 +0,0 @@
|
||||||
/*
|
|
||||||
* File : display_controller.h
|
|
||||||
* This file is part of RT-Thread RTOS
|
|
||||||
* COPYRIGHT (C) 2006-2011, RT-Thread Develop Team
|
|
||||||
*
|
|
||||||
* The license and distribution terms for this file may be
|
|
||||||
* found in the file LICENSE in this distribution or at
|
|
||||||
* http://www.rt-thread.org/license/LICENSE
|
|
||||||
*
|
|
||||||
* Change Logs:
|
|
||||||
* Date Author Notes
|
|
||||||
* 2011-08-08 lgnq first version for LS1B
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __DISPLAY_CONTROLLER_H__
|
|
||||||
#define __DISPLAY_CONTROLLER_H__
|
|
||||||
|
|
||||||
#include <rtthread.h>
|
|
||||||
#include "ls1b.h"
|
|
||||||
|
|
||||||
#define DC_BASE 0xBC301240 //Display Controller
|
|
||||||
|
|
||||||
/* Frame Buffer registers */
|
|
||||||
#define DC_FB_CONFIG __REG32(DC_BASE + 0x000)
|
|
||||||
#define DC_FB_BUFFER_ADDR0 __REG32(DC_BASE + 0x020)
|
|
||||||
#define DC_FB_BUFFER_STRIDE __REG32(DC_BASE + 0x040)
|
|
||||||
#define DC_FB_BUFFER_ORIGIN __REG32(DC_BASE + 0x060)
|
|
||||||
#define DC_DITHER_CONFIG __REG32(DC_BASE + 0x120)
|
|
||||||
#define DC_DITHER_TABLE_LOW __REG32(DC_BASE + 0x140)
|
|
||||||
#define DC_DITHER_TABLE_HIGH __REG32(DC_BASE + 0x160)
|
|
||||||
#define DC_PANEL_CONFIG __REG32(DC_BASE + 0x180)
|
|
||||||
#define DC_PANEL_TIMING __REG32(DC_BASE + 0x1A0)
|
|
||||||
#define DC_HDISPLAY __REG32(DC_BASE + 0x1C0)
|
|
||||||
#define DC_HSYNC __REG32(DC_BASE + 0x1E0)
|
|
||||||
#define DC_VDISPLAY __REG32(DC_BASE + 0x240)
|
|
||||||
#define DC_VSYNC __REG32(DC_BASE + 0x260)
|
|
||||||
#define DC_FB_BUFFER_ADDR1 __REG32(DC_BASE + 0x340)
|
|
||||||
|
|
||||||
/* Display Controller driver for 1024x768 16bit */
|
|
||||||
#define FB_XSIZE 1024
|
|
||||||
#define FB_YSIZE 768
|
|
||||||
#define CONFIG_VIDEO_16BPP
|
|
||||||
|
|
||||||
#define APB_CLK 33333333
|
|
||||||
|
|
||||||
#define K1BASE 0xA0000000
|
|
||||||
#define KSEG1(addr) ((void *)(K1BASE | (rt_uint32_t)(addr)))
|
|
||||||
#define HW_FB_ADDR KSEG1(_rt_framebuffer)
|
|
||||||
#define HW_FB_PIXEL(x, y) *(volatile rt_uint16_t*)((rt_uint8_t*)HW_FB_ADDR + (y * FB_XSIZE * 2) + x * 2)
|
|
||||||
|
|
||||||
struct vga_struct
|
|
||||||
{
|
|
||||||
long pclk;
|
|
||||||
int hr,hss,hse,hfl;
|
|
||||||
int vr,vss,vse,vfl;
|
|
||||||
};
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
@ -1,7 +1,7 @@
|
||||||
/*
|
/*
|
||||||
* File : board.c
|
* File : board.c
|
||||||
* This file is part of RT-Thread RTOS
|
* This file is part of RT-Thread RTOS
|
||||||
* COPYRIGHT (C) 2006-2011, RT-Thread Develop Team
|
* COPYRIGHT (C) 2006-2012, RT-Thread Develop Team
|
||||||
*
|
*
|
||||||
* The license and distribution terms for this file may be
|
* The license and distribution terms for this file may be
|
||||||
* found in the file LICENSE in this distribution or at
|
* found in the file LICENSE in this distribution or at
|
||||||
|
|
@ -31,11 +31,11 @@
|
||||||
*/
|
*/
|
||||||
void rt_hw_timer_handler(void)
|
void rt_hw_timer_handler(void)
|
||||||
{
|
{
|
||||||
unsigned int count;
|
unsigned int count;
|
||||||
|
|
||||||
count = read_c0_compare();
|
count = read_c0_compare();
|
||||||
write_c0_compare(count);
|
write_c0_compare(count);
|
||||||
write_c0_count(0);
|
write_c0_count(0);
|
||||||
|
|
||||||
/* increase a OS tick */
|
/* increase a OS tick */
|
||||||
rt_tick_increase();
|
rt_tick_increase();
|
||||||
|
|
@ -46,8 +46,8 @@ void rt_hw_timer_handler(void)
|
||||||
*/
|
*/
|
||||||
void rt_hw_timer_init(void)
|
void rt_hw_timer_init(void)
|
||||||
{
|
{
|
||||||
write_c0_compare(CPU_HZ/2/RT_TICK_PER_SECOND);
|
write_c0_compare(CPU_HZ/2/RT_TICK_PER_SECOND);
|
||||||
write_c0_count(0);
|
write_c0_count(0);
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
@ -80,7 +80,7 @@ void rt_hw_board_init(void)
|
||||||
#define UARTLSR_PE (1 << 2)
|
#define UARTLSR_PE (1 << 2)
|
||||||
#define UARTLSR_OE (1 << 1)
|
#define UARTLSR_OE (1 << 1)
|
||||||
#define UARTLSR_DR (1 << 0)
|
#define UARTLSR_DR (1 << 0)
|
||||||
void rt_hw_console_output(const char* ptr)
|
void rt_hw_console_output(const char *ptr)
|
||||||
{
|
{
|
||||||
/* stream mode */
|
/* stream mode */
|
||||||
while (*ptr)
|
while (*ptr)
|
||||||
|
|
|
||||||
|
|
@ -1,7 +1,7 @@
|
||||||
/*
|
/*
|
||||||
* File : board.h
|
* File : board.h
|
||||||
* This file is part of RT-Thread RTOS
|
* This file is part of RT-Thread RTOS
|
||||||
* COPYRIGHT (C) 2006-2011, RT-Thread Develop Team
|
* COPYRIGHT (C) 2006-2012, RT-Thread Develop Team
|
||||||
*
|
*
|
||||||
* The license and distribution terms for this file may be
|
* The license and distribution terms for this file may be
|
||||||
* found in the file LICENSE in this distribution or at
|
* found in the file LICENSE in this distribution or at
|
||||||
|
|
|
||||||
|
|
@ -1,7 +1,7 @@
|
||||||
/*
|
/*
|
||||||
* File : display_controller.c
|
* File : display_controller.c
|
||||||
* This file is part of RT-Thread RTOS
|
* This file is part of RT-Thread RTOS
|
||||||
* COPYRIGHT (C) 2006-2011, RT-Thread Develop Team
|
* COPYRIGHT (C) 2006-2012, RT-Thread Develop Team
|
||||||
*
|
*
|
||||||
* The license and distribution terms for this file may be
|
* The license and distribution terms for this file may be
|
||||||
* found in the file LICENSE in this distribution or at
|
* found in the file LICENSE in this distribution or at
|
||||||
|
|
|
||||||
|
|
@ -1,7 +1,7 @@
|
||||||
/*
|
/*
|
||||||
* File : display_controller.h
|
* File : display_controller.h
|
||||||
* This file is part of RT-Thread RTOS
|
* This file is part of RT-Thread RTOS
|
||||||
* COPYRIGHT (C) 2006-2011, RT-Thread Develop Team
|
* COPYRIGHT (C) 2006-2012, RT-Thread Develop Team
|
||||||
*
|
*
|
||||||
* The license and distribution terms for this file may be
|
* The license and distribution terms for this file may be
|
||||||
* found in the file LICENSE in this distribution or at
|
* found in the file LICENSE in this distribution or at
|
||||||
|
|
|
||||||
|
|
@ -41,7 +41,7 @@ static void rt_uart_irqhandler(int irqno)
|
||||||
{
|
{
|
||||||
rt_ubase_t level;
|
rt_ubase_t level;
|
||||||
rt_uint8_t isr;
|
rt_uint8_t isr;
|
||||||
struct rt_uart_ls1b* uart = &uart_device;
|
struct rt_uart_ls1b *uart = &uart_device;
|
||||||
|
|
||||||
/* read interrupt status and clear it */
|
/* read interrupt status and clear it */
|
||||||
isr = UART_IIR(uart->hw_base);
|
isr = UART_IIR(uart->hw_base);
|
||||||
|
|
|
||||||
|
|
@ -1,7 +1,7 @@
|
||||||
/*
|
/*
|
||||||
* File : uart.h
|
* File : uart.h
|
||||||
* This file is part of RT-Thread RTOS
|
* This file is part of RT-Thread RTOS
|
||||||
* COPYRIGHT (C) 2006-2011, RT-Thread Develop Team
|
* COPYRIGHT (C) 2006-2012, RT-Thread Develop Team
|
||||||
*
|
*
|
||||||
* The license and distribution terms for this file may be
|
* The license and distribution terms for this file may be
|
||||||
* found in the file LICENSE in this distribution or at
|
* found in the file LICENSE in this distribution or at
|
||||||
|
|
@ -11,6 +11,7 @@
|
||||||
* Date Author Notes
|
* Date Author Notes
|
||||||
* 2011-08-08 lgnq first version for LS1B
|
* 2011-08-08 lgnq first version for LS1B
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef __UART_H__
|
#ifndef __UART_H__
|
||||||
#define __UART_H__
|
#define __UART_H__
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,94 +0,0 @@
|
||||||
/*
|
|
||||||
* File : startup.c
|
|
||||||
* This file is part of RT-Thread RTOS
|
|
||||||
* COPYRIGHT (C) 2006-2011, RT-Thread Develop Team
|
|
||||||
*
|
|
||||||
* The license and distribution terms for this file may be
|
|
||||||
* found in the file LICENSE in this distribution or at
|
|
||||||
* http://www.rt-thread.org/license/LICENSE
|
|
||||||
*
|
|
||||||
* Change Logs:
|
|
||||||
* Date Author Notes
|
|
||||||
* 2010-06-25 Bernard first version
|
|
||||||
* 2011-08-08 lgnq modified for Loongson LS1B
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <rthw.h>
|
|
||||||
#include <rtthread.h>
|
|
||||||
|
|
||||||
#include "board.h"
|
|
||||||
#define A_K0BASE 0x80000000
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @addtogroup Loongson LS1B
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*@{*/
|
|
||||||
extern unsigned char __bss_end;
|
|
||||||
|
|
||||||
extern int rt_application_init(void);
|
|
||||||
|
|
||||||
extern void tlb_refill_exception(void);
|
|
||||||
extern void general_exception(void);
|
|
||||||
extern void irq_exception(void);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* This function will startup RT-Thread RTOS.
|
|
||||||
*/
|
|
||||||
void rtthread_startup(void)
|
|
||||||
{
|
|
||||||
/* disable interrupt first */
|
|
||||||
rt_hw_interrupt_disable();
|
|
||||||
|
|
||||||
/* init cache */
|
|
||||||
rt_hw_cache_init();
|
|
||||||
/* init hardware interrupt */
|
|
||||||
rt_hw_interrupt_init();
|
|
||||||
|
|
||||||
/* copy vector */
|
|
||||||
memcpy((void *)A_K0BASE, tlb_refill_exception, 0x20);
|
|
||||||
memcpy((void *)(A_K0BASE + 0x180), general_exception, 0x20);
|
|
||||||
memcpy((void *)(A_K0BASE + 0x200), irq_exception, 0x20);
|
|
||||||
|
|
||||||
/* init board */
|
|
||||||
rt_hw_board_init();
|
|
||||||
rt_show_version();
|
|
||||||
|
|
||||||
/* init tick */
|
|
||||||
rt_system_tick_init();
|
|
||||||
|
|
||||||
/* init timer system */
|
|
||||||
rt_system_timer_init();
|
|
||||||
|
|
||||||
#ifdef RT_USING_HEAP
|
|
||||||
rt_system_heap_init((void*)&__bss_end, (void*)RT_HW_HEAP_END);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* init scheduler system */
|
|
||||||
rt_system_scheduler_init();
|
|
||||||
|
|
||||||
#ifdef RT_USING_DEVICE
|
|
||||||
/* init all device */
|
|
||||||
rt_device_init_all();
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* init application */
|
|
||||||
rt_application_init();
|
|
||||||
|
|
||||||
#ifdef RT_USING_FINSH
|
|
||||||
/* init finsh */
|
|
||||||
finsh_system_init();
|
|
||||||
finsh_set_device(FINSH_DEVICE_NAME);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* init idle thread */
|
|
||||||
rt_thread_idle_init();
|
|
||||||
|
|
||||||
/* start scheduler */
|
|
||||||
rt_system_scheduler_start();
|
|
||||||
|
|
||||||
/* never reach here */
|
|
||||||
return ;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*@}*/
|
|
||||||
|
|
@ -1,275 +0,0 @@
|
||||||
/*
|
|
||||||
* File : board.c
|
|
||||||
* This file is part of RT-Thread RTOS
|
|
||||||
* COPYRIGHT (C) 2006-2011, RT-Thread Develop Team
|
|
||||||
*
|
|
||||||
* The license and distribution terms for this file may be
|
|
||||||
* found in the file LICENSE in this distribution or at
|
|
||||||
* http://www.rt-thread.org/license/LICENSE
|
|
||||||
*
|
|
||||||
* Change Logs:
|
|
||||||
* Date Author Notes
|
|
||||||
* 2011-08-08 lgnq first version
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <rthw.h>
|
|
||||||
#include <rtthread.h>
|
|
||||||
|
|
||||||
#include "uart.h"
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @addtogroup Loongson LS1B
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*@{*/
|
|
||||||
#if defined(RT_USING_UART) && defined(RT_USING_DEVICE)
|
|
||||||
|
|
||||||
struct rt_uart_ls1b
|
|
||||||
{
|
|
||||||
struct rt_device parent;
|
|
||||||
|
|
||||||
rt_uint32_t hw_base;
|
|
||||||
rt_uint32_t irq;
|
|
||||||
|
|
||||||
/* buffer for reception */
|
|
||||||
rt_uint8_t read_index, save_index;
|
|
||||||
rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
|
|
||||||
}uart_device;
|
|
||||||
|
|
||||||
static void rt_uart_irqhandler(int irqno)
|
|
||||||
{
|
|
||||||
rt_ubase_t level;
|
|
||||||
rt_uint8_t isr;
|
|
||||||
struct rt_uart_ls1b* uart = &uart_device;
|
|
||||||
|
|
||||||
/* read interrupt status and clear it */
|
|
||||||
isr = UART_IIR(uart->hw_base);
|
|
||||||
isr = (isr >> 1) & 0x3;
|
|
||||||
|
|
||||||
if (isr & 0x02) /* receive data available */
|
|
||||||
{
|
|
||||||
/* Receive Data Available */
|
|
||||||
while (UART_LSR(uart->hw_base) & UARTLSR_DR)
|
|
||||||
{
|
|
||||||
uart->rx_buffer[uart->save_index] = UART_DAT(uart->hw_base);
|
|
||||||
|
|
||||||
level = rt_hw_interrupt_disable();
|
|
||||||
uart->save_index ++;
|
|
||||||
if (uart->save_index >= RT_UART_RX_BUFFER_SIZE)
|
|
||||||
uart->save_index = 0;
|
|
||||||
rt_hw_interrupt_enable(level);
|
|
||||||
}
|
|
||||||
|
|
||||||
/* invoke callback */
|
|
||||||
if(uart->parent.rx_indicate != RT_NULL)
|
|
||||||
{
|
|
||||||
rt_size_t length;
|
|
||||||
if (uart->read_index > uart->save_index)
|
|
||||||
length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index;
|
|
||||||
else
|
|
||||||
length = uart->save_index - uart->read_index;
|
|
||||||
|
|
||||||
uart->parent.rx_indicate(&uart->parent, length);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
static rt_err_t rt_uart_init (rt_device_t dev)
|
|
||||||
{
|
|
||||||
rt_uint32_t baud_div;
|
|
||||||
struct rt_uart_ls1b *uart = (struct rt_uart_ls1b*)dev;
|
|
||||||
|
|
||||||
RT_ASSERT(uart != RT_NULL);
|
|
||||||
|
|
||||||
#if 0
|
|
||||||
/* init UART Hardware */
|
|
||||||
UART_IER(uart->hw_base) = 0; /* clear interrupt */
|
|
||||||
UART_FCR(uart->hw_base) = 0x60; /* reset UART Rx/Tx */
|
|
||||||
|
|
||||||
/* enable UART clock */
|
|
||||||
/* set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */
|
|
||||||
UART_LCR(uart->hw_base) = 0x3;
|
|
||||||
|
|
||||||
/* set baudrate */
|
|
||||||
baud_div = DEV_CLK / 16 / UART_BAUDRATE;
|
|
||||||
UART_LCR(uart->hw_base) |= UARTLCR_DLAB;
|
|
||||||
|
|
||||||
UART_MSB(uart->hw_base) = (baud_div >> 8) & 0xff;
|
|
||||||
UART_LSB(uart->hw_base) = baud_div & 0xff;
|
|
||||||
|
|
||||||
UART_LCR(uart->hw_base) &= ~UARTLCR_DLAB;
|
|
||||||
|
|
||||||
/* Enable UART unit, enable and clear FIFO */
|
|
||||||
UART_FCR(uart->hw_base) = UARTFCR_UUE | UARTFCR_FE | UARTFCR_TFLS | UARTFCR_RFLS;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
return RT_EOK;
|
|
||||||
}
|
|
||||||
|
|
||||||
static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag)
|
|
||||||
{
|
|
||||||
struct rt_uart_ls1b *uart = (struct rt_uart_ls1b*)dev;
|
|
||||||
|
|
||||||
RT_ASSERT(uart != RT_NULL);
|
|
||||||
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
|
|
||||||
{
|
|
||||||
/* Enable the UART Interrupt */
|
|
||||||
UART_IER(uart->hw_base) |= UARTIER_IRXE;
|
|
||||||
|
|
||||||
/* install interrupt */
|
|
||||||
rt_hw_interrupt_install(uart->irq, rt_uart_irqhandler, RT_NULL);
|
|
||||||
rt_hw_interrupt_umask(uart->irq);
|
|
||||||
}
|
|
||||||
return RT_EOK;
|
|
||||||
}
|
|
||||||
|
|
||||||
static rt_err_t rt_uart_close(rt_device_t dev)
|
|
||||||
{
|
|
||||||
struct rt_uart_ls1b *uart = (struct rt_uart_ls1b*)dev;
|
|
||||||
|
|
||||||
RT_ASSERT(uart != RT_NULL);
|
|
||||||
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
|
|
||||||
{
|
|
||||||
/* Disable the UART Interrupt */
|
|
||||||
UART_IER(uart->hw_base) &= ~(UARTIER_IRXE);
|
|
||||||
}
|
|
||||||
|
|
||||||
return RT_EOK;
|
|
||||||
}
|
|
||||||
|
|
||||||
static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
|
|
||||||
{
|
|
||||||
rt_uint8_t* ptr;
|
|
||||||
struct rt_uart_ls1b *uart = (struct rt_uart_ls1b*)dev;
|
|
||||||
|
|
||||||
RT_ASSERT(uart != RT_NULL);
|
|
||||||
|
|
||||||
/* point to buffer */
|
|
||||||
ptr = (rt_uint8_t*) buffer;
|
|
||||||
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
|
|
||||||
{
|
|
||||||
while (size)
|
|
||||||
{
|
|
||||||
/* interrupt receive */
|
|
||||||
rt_base_t level;
|
|
||||||
|
|
||||||
/* disable interrupt */
|
|
||||||
level = rt_hw_interrupt_disable();
|
|
||||||
if (uart->read_index != uart->save_index)
|
|
||||||
{
|
|
||||||
*ptr = uart->rx_buffer[uart->read_index];
|
|
||||||
|
|
||||||
uart->read_index ++;
|
|
||||||
if (uart->read_index >= RT_UART_RX_BUFFER_SIZE)
|
|
||||||
uart->read_index = 0;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* no data in rx buffer */
|
|
||||||
|
|
||||||
/* enable interrupt */
|
|
||||||
rt_hw_interrupt_enable(level);
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* enable interrupt */
|
|
||||||
rt_hw_interrupt_enable(level);
|
|
||||||
|
|
||||||
ptr ++;
|
|
||||||
size --;
|
|
||||||
}
|
|
||||||
|
|
||||||
return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
|
|
||||||
}
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
|
|
||||||
{
|
|
||||||
char *ptr;
|
|
||||||
struct rt_uart_ls1b *uart = (struct rt_uart_ls1b*)dev;
|
|
||||||
|
|
||||||
RT_ASSERT(uart != RT_NULL);
|
|
||||||
|
|
||||||
ptr = (char*)buffer;
|
|
||||||
|
|
||||||
if (dev->flag & RT_DEVICE_FLAG_STREAM)
|
|
||||||
{
|
|
||||||
/* stream mode */
|
|
||||||
while (size)
|
|
||||||
{
|
|
||||||
if (*ptr == '\n')
|
|
||||||
{
|
|
||||||
/* FIFO status, contain valid data */
|
|
||||||
while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE)));
|
|
||||||
/* write data */
|
|
||||||
UART_DAT(uart->hw_base) = '\r';
|
|
||||||
}
|
|
||||||
|
|
||||||
/* FIFO status, contain valid data */
|
|
||||||
while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE)));
|
|
||||||
/* write data */
|
|
||||||
UART_DAT(uart->hw_base) = *ptr;
|
|
||||||
|
|
||||||
ptr ++;
|
|
||||||
size --;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
while ( size != 0 )
|
|
||||||
{
|
|
||||||
/* FIFO status, contain valid data */
|
|
||||||
while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE)));
|
|
||||||
|
|
||||||
/* write data */
|
|
||||||
UART_DAT(uart->hw_base) = *ptr;
|
|
||||||
|
|
||||||
ptr++;
|
|
||||||
size--;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
return (rt_size_t) ptr - (rt_size_t) buffer;
|
|
||||||
}
|
|
||||||
|
|
||||||
void rt_hw_uart_init(void)
|
|
||||||
{
|
|
||||||
struct rt_uart_ls1b* uart;
|
|
||||||
|
|
||||||
/* get uart device */
|
|
||||||
uart = &uart_device;
|
|
||||||
|
|
||||||
/* device initialization */
|
|
||||||
uart->parent.type = RT_Device_Class_Char;
|
|
||||||
rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
|
|
||||||
uart->read_index = uart->save_index = 0;
|
|
||||||
|
|
||||||
#if defined(RT_USING_UART0)
|
|
||||||
uart->hw_base = UART0_BASE;
|
|
||||||
uart->irq = LS1B_UART0_IRQ;
|
|
||||||
#elif defined(RT_USING_UART1)
|
|
||||||
uart->hw_base = UART1_BASE;
|
|
||||||
uart->irq = LS1B_UART1_IRQ;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* device interface */
|
|
||||||
uart->parent.init = rt_uart_init;
|
|
||||||
uart->parent.open = rt_uart_open;
|
|
||||||
uart->parent.close = rt_uart_close;
|
|
||||||
uart->parent.read = rt_uart_read;
|
|
||||||
uart->parent.write = rt_uart_write;
|
|
||||||
uart->parent.control = RT_NULL;
|
|
||||||
uart->parent.user_data = RT_NULL;
|
|
||||||
|
|
||||||
rt_device_register(&uart->parent, "uart0",
|
|
||||||
RT_DEVICE_FLAG_RDWR |
|
|
||||||
RT_DEVICE_FLAG_STREAM |
|
|
||||||
RT_DEVICE_FLAG_INT_RX);
|
|
||||||
}
|
|
||||||
#endif /* end of UART */
|
|
||||||
|
|
||||||
/*@}*/
|
|
||||||
|
|
@ -1,97 +0,0 @@
|
||||||
/*
|
|
||||||
* File : uart.h
|
|
||||||
* This file is part of RT-Thread RTOS
|
|
||||||
* COPYRIGHT (C) 2006-2011, RT-Thread Develop Team
|
|
||||||
*
|
|
||||||
* The license and distribution terms for this file may be
|
|
||||||
* found in the file LICENSE in this distribution or at
|
|
||||||
* http://www.rt-thread.org/license/LICENSE
|
|
||||||
*
|
|
||||||
* Change Logs:
|
|
||||||
* Date Author Notes
|
|
||||||
* 2011-08-08 lgnq first version for LS1B
|
|
||||||
*/
|
|
||||||
#ifndef __UART_H__
|
|
||||||
#define __UART_H__
|
|
||||||
|
|
||||||
#include "ls1b.h"
|
|
||||||
|
|
||||||
#define UART0_BASE 0xBFE40000
|
|
||||||
#define UART0_1_BASE 0xBFE41000
|
|
||||||
#define UART0_2_BASE 0xBFE42000
|
|
||||||
#define UART0_3_BASE 0xBFE43000
|
|
||||||
#define UART1_BASE 0xBFE44000
|
|
||||||
#define UART1_1_BASE 0xBFE45000
|
|
||||||
#define UART1_2_BASE 0xBFE46000
|
|
||||||
#define UART1_3_BASE 0xBFE47000
|
|
||||||
#define UART2_BASE 0xBFE48000
|
|
||||||
#define UART3_BASE 0xBFE4C000
|
|
||||||
#define UART4_BASE 0xBFE6C000
|
|
||||||
#define UART5_BASE 0xBFE7C000
|
|
||||||
|
|
||||||
/* UART registers */
|
|
||||||
#define UART_DAT(base) __REG8(base + 0x00)
|
|
||||||
#define UART_IER(base) __REG8(base + 0x01)
|
|
||||||
#define UART_IIR(base) __REG8(base + 0x02)
|
|
||||||
#define UART_FCR(base) __REG8(base + 0x02)
|
|
||||||
#define UART_LCR(base) __REG8(base + 0x03)
|
|
||||||
#define UART_MCR(base) __REG8(base + 0x04)
|
|
||||||
#define UART_LSR(base) __REG8(base + 0x05)
|
|
||||||
#define UART_MSR(base) __REG8(base + 0x06)
|
|
||||||
|
|
||||||
#define UART_LSB(base) __REG8(base + 0x00)
|
|
||||||
#define UART_MSB(base) __REG8(base + 0x01)
|
|
||||||
|
|
||||||
/* UART0 registers */
|
|
||||||
#define UART0_DAT __REG8(UART0_BASE + 0x00)
|
|
||||||
#define UART0_IER __REG8(UART0_BASE + 0x01)
|
|
||||||
#define UART0_IIR __REG8(UART0_BASE + 0x02)
|
|
||||||
#define UART0_FCR __REG8(UART0_BASE + 0x02)
|
|
||||||
#define UART0_LCR __REG8(UART0_BASE + 0x03)
|
|
||||||
#define UART0_MCR __REG8(UART0_BASE + 0x04)
|
|
||||||
#define UART0_LSR __REG8(UART0_BASE + 0x05)
|
|
||||||
#define UART0_MSR __REG8(UART0_BASE + 0x06)
|
|
||||||
|
|
||||||
#define UART0_LSB __REG8(UART0_BASE + 0x00)
|
|
||||||
#define UART0_MSB __REG8(UART0_BASE + 0x01)
|
|
||||||
|
|
||||||
/* UART1 registers */
|
|
||||||
#define UART1_DAT __REG8(UART1_BASE + 0x00)
|
|
||||||
#define UART1_IER __REG8(UART1_BASE + 0x01)
|
|
||||||
#define UART1_IIR __REG8(UART1_BASE + 0x02)
|
|
||||||
#define UART1_FCR __REG8(UART1_BASE + 0x02)
|
|
||||||
#define UART1_LCR __REG8(UART1_BASE + 0x03)
|
|
||||||
#define UART1_MCR __REG8(UART1_BASE + 0x04)
|
|
||||||
#define UART1_LSR __REG8(UART1_BASE + 0x05)
|
|
||||||
#define UART1_MSR __REG8(UART1_BASE + 0x06)
|
|
||||||
|
|
||||||
#define UART1_LSB __REG8(UART1_BASE + 0x00)
|
|
||||||
#define UART1_MSB __REG8(UART1_BASE + 0x01)
|
|
||||||
|
|
||||||
/* UART interrupt enable register value */
|
|
||||||
#define UARTIER_IME (1 << 3)
|
|
||||||
#define UARTIER_ILE (1 << 2)
|
|
||||||
#define UARTIER_ITXE (1 << 1)
|
|
||||||
#define UARTIER_IRXE (1 << 0)
|
|
||||||
|
|
||||||
/* UART line control register value */
|
|
||||||
#define UARTLCR_DLAB (1 << 7)
|
|
||||||
#define UARTLCR_BCB (1 << 6)
|
|
||||||
#define UARTLCR_SPB (1 << 5)
|
|
||||||
#define UARTLCR_EPS (1 << 4)
|
|
||||||
#define UARTLCR_PE (1 << 3)
|
|
||||||
#define UARTLCR_SB (1 << 2)
|
|
||||||
|
|
||||||
/* UART line status register value */
|
|
||||||
#define UARTLSR_ERROR (1 << 7)
|
|
||||||
#define UARTLSR_TE (1 << 6)
|
|
||||||
#define UARTLSR_TFE (1 << 5)
|
|
||||||
#define UARTLSR_BI (1 << 4)
|
|
||||||
#define UARTLSR_FE (1 << 3)
|
|
||||||
#define UARTLSR_PE (1 << 2)
|
|
||||||
#define UARTLSR_OE (1 << 1)
|
|
||||||
#define UARTLSR_DR (1 << 0)
|
|
||||||
|
|
||||||
void rt_hw_uart_init(void);
|
|
||||||
|
|
||||||
#endif
|
|
||||||
Loading…
Reference in New Issue