From f18a82d59b3ccf0b9eaf821d03c865bcbd45dc36 Mon Sep 17 00:00:00 2001 From: wuyangyong Date: Mon, 20 Dec 2010 13:41:56 +0000 Subject: [PATCH] fix pendsv priority set reverse bug git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1218 bbd45198-f89e-11dd-88c7-29a3b14d5316 --- libcpu/arm/lm3s/context_gcc.S | 4 +++- libcpu/arm/lm3s/context_rvds.S | 4 +++- libcpu/arm/lpc17xx/context_iar.S | 4 +++- libcpu/arm/lpc17xx/context_rvds.S | 4 +++- libcpu/arm/s3c24x0/start_rvds.S | 34 ++++++++++++++++++++++++++----- 5 files changed, 41 insertions(+), 9 deletions(-) diff --git a/libcpu/arm/lm3s/context_gcc.S b/libcpu/arm/lm3s/context_gcc.S index 04d45c1327..e4a0a3e68c 100644 --- a/libcpu/arm/lm3s/context_gcc.S +++ b/libcpu/arm/lm3s/context_gcc.S @@ -146,7 +146,9 @@ rt_hw_context_switch_to: /* set the PendSV exception priority */ LDR r0, =NVIC_SYSPRI2 LDR r1, =NVIC_PENDSV_PRI - STR r1, [r0] + LDR.W R2, [r0,#0x00] ; read + ORR r1,r1,r2 ; modify + STR r1, [r0] ; write-bak LDR r0, =NVIC_INT_CTRL /* trigger the PendSV exception (causes context switch) */ LDR r1, =NVIC_PENDSVSET diff --git a/libcpu/arm/lm3s/context_rvds.S b/libcpu/arm/lm3s/context_rvds.S index 5eab028ee4..6432965f57 100644 --- a/libcpu/arm/lm3s/context_rvds.S +++ b/libcpu/arm/lm3s/context_rvds.S @@ -155,7 +155,9 @@ rt_hw_context_switch_to PROC ; trigger the PendSV exception (causes context switch) LDR r0, =NVIC_INT_CTRL LDR r1, =NVIC_PENDSVSET - STR r1, [r0] + LDR.W R2, [r0,#0x00] ; read + ORR r1,r1,r2 ; modify + STR r1, [r0] ; write-bak ; enable interrupts at processor level CPSIE I diff --git a/libcpu/arm/lpc17xx/context_iar.S b/libcpu/arm/lpc17xx/context_iar.S index 70ab59d362..3c8f2d3599 100644 --- a/libcpu/arm/lpc17xx/context_iar.S +++ b/libcpu/arm/lpc17xx/context_iar.S @@ -148,7 +148,9 @@ rt_hw_context_switch_to: ; set the PendSV exception priority LDR r0, =NVIC_SYSPRI2 LDR r1, =NVIC_PENDSV_PRI - STR r1, [r0] + LDR.W R2, [r0,#0x00] ; read + ORR r1,r1,r2 ; modify + STR r1, [r0] ; write-bak ; trigger the PendSV exception (causes context switch) LDR r0, =NVIC_INT_CTRL diff --git a/libcpu/arm/lpc17xx/context_rvds.S b/libcpu/arm/lpc17xx/context_rvds.S index 0ffeb59c7e..b59c5da3da 100644 --- a/libcpu/arm/lpc17xx/context_rvds.S +++ b/libcpu/arm/lpc17xx/context_rvds.S @@ -150,7 +150,9 @@ rt_hw_context_switch_to PROC ; set the PendSV exception priority LDR r0, =NVIC_SYSPRI2 LDR r1, =NVIC_PENDSV_PRI - STR r1, [r0] + LDR.W R2, [r0,#0x00] ; read + ORR r1,r1,r2 ; modify + STR r1, [r0] ; write-bak ; trigger the PendSV exception (causes context switch) LDR r0, =NVIC_INT_CTRL diff --git a/libcpu/arm/s3c24x0/start_rvds.S b/libcpu/arm/s3c24x0/start_rvds.S index fe194148e9..5ca6f94022 100644 --- a/libcpu/arm/s3c24x0/start_rvds.S +++ b/libcpu/arm/s3c24x0/start_rvds.S @@ -498,7 +498,7 @@ GPDAT_OFS EQU 0x04 ; Data Register Offset GPUP_OFS EQU 0x08 ; Pull-up Disable Register Offset ;// I/O Setup -GP_SETUP EQU 0 +GP_SETUP EQU 1 ;// Port A Settings ;// Port A Control Register (GPACON) @@ -710,9 +710,9 @@ GPEUP_Val EQU 0x00000000 ;// GPF0 Pull-up Disable ;// ;// -GPF_SETUP EQU 0 -GPFCON_Val EQU 0x00000000 -GPFUP_Val EQU 0x00000000 +GPF_SETUP EQU 1 +GPFCON_Val EQU 0x000000AA +GPFUP_Val EQU 0x0000000F ;// Port G Settings ;// Port G Control Register (GPGCON) @@ -866,10 +866,34 @@ FIQ_Addr DCD FIQ_Handler Undef_Handler B Undef_Handler SWI_Handler B SWI_Handler PAbt_Handler B PAbt_Handler -DAbt_Handler B DAbt_Handler +;DAbt_Handler B DAbt_Handler FIQ_Handler B FIQ_Handler +;* +;************************************************************************* +;* +;* Interrupt handling +;* +;************************************************************************* +;* +; DAbt Handler +DAbt_Handler + IMPORT rt_hw_trap_dabt + sub sp, sp, #72 + stmia sp, {r0 - r12} ;/* Calling r0-r12 */ + add r8, sp, #60 + stmdb r8, {sp, lr} ;/* Calling SP, LR */ + str lr, [r8, #0] ;/* Save calling PC */ + mrs r6, spsr + str r6, [r8, #4] ;/* Save CPSR */ + str r0, [r8, #8] ;/* Save OLD_R0 */ + mov r0, sp + + bl rt_hw_trap_dabt + + +;########################################## ; Reset Handler EXPORT Reset_Handler