Merge pull request #1625 from uestczyh222/bypass
[Bsp][STM32F4xx-HAL]Fix Clock tree Support HSI| 修复时钟树,支持HSI
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commit
e751fc9934
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@ -287,7 +287,7 @@ config RT_USING_HSI
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bool "Using HSI as clock source"
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default n
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config BSP_HSE_BY_PASS
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bool "HES Bypass"
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bool "HSE Bypass"
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depends on !RT_USING_HSI
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default n
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config RT_HSE_VALUE
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@ -18,9 +18,6 @@
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* @addtogroup STM32
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*/
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/*@{*/
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#ifdef RT_USING_HSI
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#error Can not using HSI on this bsp
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#endif
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#if defined(RCC_PERIPHCLK_SDIO) || defined(RCC_PERIPHCLK_CEC) || defined(RCC_PERIPHCLK_LTDC)\
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|| defined(RCC_PERIPHCLK_SPDIFRX) || defined(RCC_PERIPHCLK_FMPI2C1) || defined(RCC_PERIPHCLK_LPTIM1)
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#warning Please give priority to the correctness of the clock tree when the peripherals are abnormal
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@ -28,11 +25,18 @@
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static void SystemClock_Config(void)
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{
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rt_uint32_t hse_clk, sys_clk;
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#if (RT_HSE_VALVE % 1000000 != 0)
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rt_uint32_t source_clk, sys_clk;
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#if !defined(RT_USING_HSI) && (RT_HSE_VALVE % 1000000 != 0)
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#error HSE must be integer of MHz
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#endif
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hse_clk = HSE_VALUE / 1000000UL;
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#ifdef RT_USING_HSI
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#define CLOCK_SOURE_VALUE HSI_VALUE
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#else
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#define CLOCK_SOURE_VALUE HSE_VALUE
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#endif
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source_clk = CLOCK_SOURE_VALUE / 1000000UL;
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sys_clk = HCLK_VALUE / 1000000UL;
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RCC_OscInitTypeDef RCC_OscInitStruct;
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RCC_ClkInitTypeDef RCC_ClkInitStruct;
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@ -45,27 +49,35 @@ static void SystemClock_Config(void)
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__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
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/**Initializes the CPU, AHB and APB busses clocks
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*/
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#ifdef RT_USING_HSI
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
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#else
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
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#endif
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#ifdef RT_USING_RTC
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RCC_OscInitStruct.OscillatorType |= RCC_OSCILLATORTYPE_LSI;
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RCC_OscInitStruct.LSIState = RCC_LSI_ON;
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#endif
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#ifdef RT_USING_HSI
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RCC_OscInitStruct.HSIState = RCC_HSI_ON;
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RCC_OscInitStruct.HSICalibrationValue = source_clk;
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#else
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#ifdef BSP_HSE_BY_PASS
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RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
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#elif !defined(RT_USING_HSI)
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#else
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RCC_OscInitStruct.HSEState = RCC_HSE_ON;
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#endif
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#endif
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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#ifdef RT_USING_HSI
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
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#else
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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if (hse_clk % 2 == 0)
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#endif
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if (source_clk % 2 == 0)
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{
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RCC_OscInitStruct.PLL.PLLM = hse_clk / 2; //Get 2M clock
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if ((sys_clk * 2) % 48 == 0)
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{
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RCC_OscInitStruct.PLL.PLLN = sys_clk;//Get 2*HCLK_VALUE
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;//Get HCLK_VALUE
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}
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else if ((sys_clk * 4) % 48 == 0)
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RCC_OscInitStruct.PLL.PLLM = source_clk / 2; //Get 2M clock
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if ((sys_clk * 4) % 48 == 0)
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{
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RCC_OscInitStruct.PLL.PLLN = sys_clk * 2;//Get 4*HCLK_VALUE
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;//Get HCLK_VALUE
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@ -80,16 +92,17 @@ static void SystemClock_Config(void)
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RCC_OscInitStruct.PLL.PLLN = sys_clk * 4;//Get 8*HCLK_VALUE
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV8;//Get HCLK_VALUE
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}
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else
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{
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//can not get 48M Clock USB is unuseable
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RCC_OscInitStruct.PLL.PLLN = sys_clk;//Get 2*HCLK_VALUE
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;//Get HCLK_VALUE
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}
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}
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else
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{
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RCC_OscInitStruct.PLL.PLLM = hse_clk;//Get 1M clock
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if ((sys_clk * 2) % 48 == 0)
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{
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RCC_OscInitStruct.PLL.PLLN = sys_clk * 2;//Get 2*HCLK_VALUE
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;//Get HCLK_VALUE
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}
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else if ((sys_clk * 4) % 48 == 0)
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RCC_OscInitStruct.PLL.PLLM = source_clk;//Get 1M clock
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if ((sys_clk * 4) % 48 == 0)
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{
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RCC_OscInitStruct.PLL.PLLN = sys_clk * 4;//Get 4*HCLK_VALUE
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;//Get HCLK_VALUE
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@ -104,8 +117,14 @@ static void SystemClock_Config(void)
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RCC_OscInitStruct.PLL.PLLN = sys_clk * 8;//Get 8*HCLK_VALUE
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV8;//Get HCLK_VALUE
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}
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else
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{
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//can not get 48M Clock USB is unuseable
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RCC_OscInitStruct.PLL.PLLN = sys_clk * 2;//Get 2*HCLK_VALUE
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;//Get HCLK_VALUE
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}
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}
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RCC_OscInitStruct.PLL.PLLQ = hse_clk / RCC_OscInitStruct.PLL.PLLM * RCC_OscInitStruct.PLL.PLLN / 48; //Get 48M Clock
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RCC_OscInitStruct.PLL.PLLQ = source_clk / RCC_OscInitStruct.PLL.PLLM * RCC_OscInitStruct.PLL.PLLN / 48; //Get 48M Clock
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
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{
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while (1)
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@ -133,6 +152,14 @@ static void SystemClock_Config(void)
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while (1)
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{}
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}
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#elif (RT_HSE_HCLK <= 100000000UL)
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
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{
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while (1)
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{}
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}
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#elif (RT_HSE_HCLK <= 168000000UL)
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
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