From 65ffe4e13ef52d007d83c93467871c529705b522 Mon Sep 17 00:00:00 2001 From: Shell Date: Mon, 15 Jul 2024 12:06:17 +0800 Subject: [PATCH 01/48] [libcpu/rv64] feat: unify tick.c The changes unify the tick.c implementations for all risc-v64 architectures, leveraging the CPUTIME feature. This refactoring was necessary to streamline the codebase, and ensure consistent timer handling across different platforms. Changes: - Updated `Kconfig` in `bsp/cvitek/cv18xx_risc-v` to fix formatting issues. - Updated .config for BSPs to update `CPUTIME_TIMER_FREQ` - Updated header of for API `riscv_cputime_init` - Initialized riscv timer on `rt_hw_tick_init` - Refactored `tick.c` and `tick.h` in `libcpu/risc-v/t-head/c906` and `libcpu/risc-v/virt64`: - Replaced direct use of `rdtime` with `clock_cpu_gettime`. - Removed redundant timer frequency definitions. - Added static assertions to check the value of `CPUTIME_TIMER_FREQ`. - Initialized `tick_cycles` based on `CPUTIME_TIMER_FREQ`. - Integrated `ktime` support for tick initialization. Signed-off-by: Shell Reviewed-on: https://github.com/RT-Thread/rt-thread/pull/9164 Reviewed-by: Chen Wang --- bsp/allwinner/d1s/.config | 330 +++++++++++++++--- bsp/allwinner/d1s/Kconfig | 1 + bsp/allwinner/d1s/rtconfig.h | 48 ++- bsp/cvitek/cv18xx_risc-v/.config | 123 ++++++- bsp/cvitek/cv18xx_risc-v/Kconfig | 7 +- bsp/cvitek/cv18xx_risc-v/rtconfig.h | 30 +- bsp/qemu-virt64-riscv/.config | 335 ++++++++++++++++--- bsp/qemu-virt64-riscv/Kconfig | 1 + bsp/qemu-virt64-riscv/rtconfig.h | 45 ++- components/drivers/include/drivers/cputime.h | 4 + libcpu/Kconfig | 9 + libcpu/risc-v/t-head/c906/tick.c | 44 +-- libcpu/risc-v/t-head/c906/tick.h | 6 +- libcpu/risc-v/virt64/tick.c | 49 ++- libcpu/risc-v/virt64/tick.h | 2 +- 15 files changed, 850 insertions(+), 184 deletions(-) diff --git a/bsp/allwinner/d1s/.config b/bsp/allwinner/d1s/.config index c2a2054637..00ba6314b4 100644 --- a/bsp/allwinner/d1s/.config +++ b/bsp/allwinner/d1s/.config @@ -101,6 +101,7 @@ CONFIG_ARCH_MM_MMU=y CONFIG_KERNEL_VADDR_START=0x40000000 CONFIG_ARCH_RISCV=y CONFIG_ARCH_RISCV64=y +CONFIG_ARCH_USING_RISCV_COMMON64=y # # RT-Thread Components @@ -202,7 +203,9 @@ CONFIG_RT_USING_SERIAL=y CONFIG_RT_USING_SERIAL_V2=y # CONFIG_RT_SERIAL_USING_DMA is not set # CONFIG_RT_USING_CAN is not set -# CONFIG_RT_USING_CPUTIME is not set +CONFIG_RT_USING_CPUTIME=y +CONFIG_RT_USING_CPUTIME_RISCV=y +CONFIG_CPUTIME_TIMER_FREQ=24000000 # CONFIG_RT_USING_I2C is not set # CONFIG_RT_USING_PHY is not set # CONFIG_RT_USING_ADC is not set @@ -379,9 +382,9 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64 # CONFIG_PKG_USING_KAWAII_MQTT is not set # CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set -# CONFIG_PKG_USING_LIBMODBUS is not set # CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set # # Wi-Fi @@ -400,6 +403,24 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64 # end of Wiced WiFi # CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set +# end of CYW43012 WiFi + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set +# end of BL808 WiFi + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# end of CYW43439 WiFi # end of Wi-Fi # CONFIG_PKG_USING_COAP is not set @@ -423,7 +444,6 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64 # CONFIG_PKG_USING_JIOT-C-SDK is not set # CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set # CONFIG_PKG_USING_JOYLINK is not set -# CONFIG_PKG_USING_EZ_IOT_OS is not set # CONFIG_PKG_USING_IOTSHARP_SDK is not set # end of IoT Cloud @@ -446,6 +466,8 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64 # CONFIG_PKG_USING_NMEALIB is not set # CONFIG_PKG_USING_PDULIB is not set # CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set # CONFIG_PKG_USING_LORAWAN_ED_STACK is not set # CONFIG_PKG_USING_WAYZ_IOTKIT is not set # CONFIG_PKG_USING_MAVLINK is not set @@ -454,6 +476,8 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64 # CONFIG_PKG_USING_AGILE_FTP is not set # CONFIG_PKG_USING_EMBEDDEDPROTO is not set # CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set # CONFIG_PKG_USING_LORA_PKT_FWD is not set # CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set # CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set @@ -461,6 +485,11 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64 # CONFIG_PKG_USING_SMALL_MODBUS is not set # CONFIG_PKG_USING_NET_SERVER is not set # CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set # end of IoT - internet of things # @@ -513,7 +542,6 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64 # LVGL: powerful and easy-to-use embedded GUI library # # CONFIG_PKG_USING_LVGL is not set -# CONFIG_PKG_USING_LITTLEVGL2RTT is not set # CONFIG_PKG_USING_LV_MUSIC_DEMO is not set # CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set # end of LVGL: powerful and easy-to-use embedded GUI library @@ -538,19 +566,12 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64 # CONFIG_PKG_USING_MP3PLAYER is not set # CONFIG_PKG_USING_TINYJPEG is not set # CONFIG_PKG_USING_UGUI is not set - -# -# PainterEngine: A cross-platform graphics application framework written in C language -# -# CONFIG_PKG_USING_PAINTERENGINE is not set -# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set -# end of PainterEngine: A cross-platform graphics application framework written in C language - # CONFIG_PKG_USING_MCURSES is not set # CONFIG_PKG_USING_TERMBOX is not set # CONFIG_PKG_USING_VT100 is not set # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set # end of multimedia packages # @@ -561,9 +582,9 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64 # CONFIG_PKG_USING_EASYLOGGER is not set # CONFIG_PKG_USING_SYSTEMVIEW is not set # CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set # CONFIG_PKG_USING_RDB is not set # CONFIG_PKG_USING_ULOG_EASYFLASH is not set -# CONFIG_PKG_USING_ULOG_FILE is not set # CONFIG_PKG_USING_LOGMGR is not set # CONFIG_PKG_USING_ADBD is not set # CONFIG_PKG_USING_COREMARK is not set @@ -597,9 +618,9 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64 # CONFIG_PKG_USING_CBOX is not set # CONFIG_PKG_USING_SNOWFLAKE is not set # CONFIG_PKG_USING_HASH_MATCH is not set -# CONFIG_PKG_USING_FIRE_PID_CURVE is not set # CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set # CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_ZDEBUG is not set # end of tools packages # @@ -614,6 +635,8 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64 # CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set # end of enhanced kernel services +# CONFIG_PKG_USING_AUNITY is not set + # # acceleration: Assembly language or algorithmic acceleration packages # @@ -626,6 +649,9 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64 # CMSIS: ARM Cortex-M Microcontroller Software Interface Standard # # CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_CORE is not set +# CONFIG_PKG_USING_CMSIS_DSP is not set +# CONFIG_PKG_USING_CMSIS_NN is not set # CONFIG_PKG_USING_CMSIS_RTOS1 is not set # CONFIG_PKG_USING_CMSIS_RTOS2 is not set # end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard @@ -642,10 +668,14 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64 # end of Micrium: Micrium software products porting for RT-Thread # CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set # CONFIG_PKG_USING_CAIRO is not set # CONFIG_PKG_USING_PIXMAN is not set # CONFIG_PKG_USING_PARTITION is not set # CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set # CONFIG_PKG_USING_FLASHDB is not set # CONFIG_PKG_USING_SQLITE is not set # CONFIG_PKG_USING_RTI is not set @@ -665,6 +695,7 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64 # CONFIG_PKG_USING_QBOOT is not set # CONFIG_PKG_USING_PPOOL is not set # CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set # CONFIG_PKG_USING_LPM is not set # CONFIG_PKG_USING_TLSF is not set # CONFIG_PKG_USING_EVENT_RECORDER is not set @@ -676,30 +707,52 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64 # CONFIG_PKG_USING_TFDB is not set # CONFIG_PKG_USING_QPC is not set # CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set # end of system packages # # peripheral libraries and drivers # -# CONFIG_PKG_USING_SENSORS_DRIVERS is not set -# CONFIG_PKG_USING_REALTEK_AMEBA is not set -# CONFIG_PKG_USING_SHT2X is not set -# CONFIG_PKG_USING_SHT3X is not set -# CONFIG_PKG_USING_ADT74XX is not set -# CONFIG_PKG_USING_AS7341 is not set + +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set # CONFIG_PKG_USING_STM32_SDIO is not set +# end of STM32 HAL & SDK Drivers + +# +# Infineon HAL Packages +# +# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set +# CONFIG_PKG_USING_INFINEON_CMSIS is not set +# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set +# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set +# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set +# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set +# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set +# CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set # CONFIG_PKG_USING_ESP_IDF is not set -# CONFIG_PKG_USING_ICM20608 is not set -# CONFIG_PKG_USING_BUTTON is not set -# CONFIG_PKG_USING_PCF8574 is not set -# CONFIG_PKG_USING_SX12XX is not set -# CONFIG_PKG_USING_SIGNAL_LED is not set -# CONFIG_PKG_USING_LEDBLINK is not set -# CONFIG_PKG_USING_LITTLED is not set -# CONFIG_PKG_USING_LKDGUI is not set -# CONFIG_PKG_USING_NRF5X_SDK is not set -# CONFIG_PKG_USING_NRFX is not set -# CONFIG_PKG_USING_WM_LIBRARIES is not set # # Kendryte SDK @@ -708,34 +761,128 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64 # CONFIG_PKG_USING_KENDRYTE_SDK is not set # end of Kendryte SDK +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_NUCLEI_SDK is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# end of HAL & SDK Drivers + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set +# end of sensors drivers + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# end of touch drivers + +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set # CONFIG_PKG_USING_INFRARED is not set # CONFIG_PKG_USING_MULTI_INFRARED is not set # CONFIG_PKG_USING_AGILE_BUTTON is not set # CONFIG_PKG_USING_AGILE_LED is not set # CONFIG_PKG_USING_AT24CXX is not set # CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set -# CONFIG_PKG_USING_AD7746 is not set # CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set # CONFIG_PKG_USING_I2C_TOOLS is not set # CONFIG_PKG_USING_NRF24L01 is not set -# CONFIG_PKG_USING_TOUCH_DRIVERS is not set -# CONFIG_PKG_USING_MAX17048 is not set # CONFIG_PKG_USING_RPLIDAR is not set # CONFIG_PKG_USING_AS608 is not set # CONFIG_PKG_USING_RC522 is not set # CONFIG_PKG_USING_WS2812B is not set -# CONFIG_PKG_USING_EMBARC_BSP is not set # CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set # CONFIG_PKG_USING_MULTI_RTIMER is not set # CONFIG_PKG_USING_MAX7219 is not set # CONFIG_PKG_USING_BEEP is not set # CONFIG_PKG_USING_EASYBLINK is not set # CONFIG_PKG_USING_PMS_SERIES is not set -# CONFIG_PKG_USING_NUCLEI_SDK is not set # CONFIG_PKG_USING_CAN_YMODEM is not set # CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set # CONFIG_PKG_USING_QLED is not set -# CONFIG_PKG_USING_PAJ7620 is not set # CONFIG_PKG_USING_AGILE_CONSOLE is not set # CONFIG_PKG_USING_LD3320 is not set # CONFIG_PKG_USING_WK2124 is not set @@ -749,7 +896,6 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64 # CONFIG_PKG_USING_VIRTUAL_SENSOR is not set # CONFIG_PKG_USING_VDEVICE is not set # CONFIG_PKG_USING_SGM706 is not set -# CONFIG_PKG_USING_STM32WB55_SDK is not set # CONFIG_PKG_USING_RDA58XX is not set # CONFIG_PKG_USING_LIBNFC is not set # CONFIG_PKG_USING_MFOC is not set @@ -759,17 +905,25 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64 # CONFIG_PKG_USING_ROSSERIAL is not set # CONFIG_PKG_USING_MICRO_ROS is not set # CONFIG_PKG_USING_MCP23008 is not set -# CONFIG_PKG_USING_BLUETRUM_SDK is not set # CONFIG_PKG_USING_MISAKA_AT24CXX is not set # CONFIG_PKG_USING_MISAKA_RGB_BLING is not set # CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set -# CONFIG_PKG_USING_BL_MCU_SDK is not set # CONFIG_PKG_USING_SOFT_SERIAL is not set # CONFIG_PKG_USING_MB85RS16 is not set -# CONFIG_PKG_USING_CW2015 is not set # CONFIG_PKG_USING_RFM300 is not set # CONFIG_PKG_USING_IO_INPUT_FILTER is not set -# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set # end of peripheral libraries and drivers # @@ -784,8 +938,20 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64 # CONFIG_PKG_USING_ULAPACK is not set # CONFIG_PKG_USING_QUEST is not set # CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set # end of AI packages +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_APID is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set +# end of Signal Processing and Control Algorithm Packages + # # miscellaneous packages # @@ -817,6 +983,7 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64 # CONFIG_PKG_USING_TETRIS is not set # CONFIG_PKG_USING_DONUT is not set # CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set # end of entertainment: terminal games and other interesting software packages # CONFIG_PKG_USING_LIBCSV is not set @@ -825,6 +992,7 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64 # CONFIG_PKG_USING_MINILZO is not set # CONFIG_PKG_USING_QUICKLZ is not set # CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set # CONFIG_PKG_USING_MULTIBUTTON is not set # CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set @@ -834,14 +1002,12 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64 # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set # CONFIG_PKG_USING_KENDRYTE_DEMO is not set -# CONFIG_PKG_USING_DIGITALCTRL is not set # CONFIG_PKG_USING_UPACKER is not set # CONFIG_PKG_USING_UPARAM is not set # CONFIG_PKG_USING_HELLO is not set # CONFIG_PKG_USING_VI is not set # CONFIG_PKG_USING_KI is not set # CONFIG_PKG_USING_ARMv7M_DWT is not set -# CONFIG_PKG_USING_UKAL is not set # CONFIG_PKG_USING_CRCLIB is not set # CONFIG_PKG_USING_LWGPS is not set # CONFIG_PKG_USING_STATE_MACHINE is not set @@ -852,6 +1018,7 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64 # CONFIG_PKG_USING_SLCAN2RTT is not set # CONFIG_PKG_USING_SOEM is not set # CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set # end of miscellaneous packages # @@ -860,26 +1027,30 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64 # CONFIG_PKG_USING_RTDUINO is not set # -# Projects +# Projects and Demos # +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set # CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set # CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set # CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set -# end of Projects +# end of Projects and Demos # # Sensors # -# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set -# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set -# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set @@ -921,7 +1092,7 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set -# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set @@ -971,18 +1142,61 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set # end of Sensors # # Display # +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set # CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set # end of Display # # Timing # +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set # CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set # end of Timing # @@ -990,6 +1204,8 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64 # # CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set # CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set +# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set # end of Data Processing # @@ -1008,11 +1224,19 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64 # # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set # end of Device Control # # Other # +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# end of Other # # Signal IO diff --git a/bsp/allwinner/d1s/Kconfig b/bsp/allwinner/d1s/Kconfig index 2815ee299b..0fa09d715c 100644 --- a/bsp/allwinner/d1s/Kconfig +++ b/bsp/allwinner/d1s/Kconfig @@ -12,6 +12,7 @@ osource "$PKGS_DIR/Kconfig" config BOARD_allwinnerd1s bool select ARCH_RISCV64 + select ARCH_USING_RISCV_COMMON64 select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN select RT_USING_CACHE diff --git a/bsp/allwinner/d1s/rtconfig.h b/bsp/allwinner/d1s/rtconfig.h index 8c0fd9b38e..fb57f87006 100644 --- a/bsp/allwinner/d1s/rtconfig.h +++ b/bsp/allwinner/d1s/rtconfig.h @@ -68,6 +68,7 @@ #define KERNEL_VADDR_START 0x40000000 #define ARCH_RISCV #define ARCH_RISCV64 +#define ARCH_USING_RISCV_COMMON64 /* RT-Thread Components */ @@ -143,6 +144,9 @@ #define RT_SYSTEM_WORKQUEUE_PRIORITY 23 #define RT_USING_SERIAL #define RT_USING_SERIAL_V2 +#define RT_USING_CPUTIME +#define RT_USING_CPUTIME_RISCV +#define CPUTIME_TIMER_FREQ 24000000 #define RT_USING_NULL #define RT_USING_ZERO #define RT_USING_RANDOM @@ -243,6 +247,18 @@ /* Wiced WiFi */ /* end of Wiced WiFi */ + +/* CYW43012 WiFi */ + +/* end of CYW43012 WiFi */ + +/* BL808 WiFi */ + +/* end of BL808 WiFi */ + +/* CYW43439 WiFi */ + +/* end of CYW43439 WiFi */ /* end of Wi-Fi */ /* IoT Cloud */ @@ -274,10 +290,6 @@ /* u8g2: a monochrome graphic library */ /* end of u8g2: a monochrome graphic library */ - -/* PainterEngine: A cross-platform graphics application framework written in C language */ - -/* end of PainterEngine: A cross-platform graphics application framework written in C language */ /* end of multimedia packages */ /* tools packages */ @@ -305,16 +317,38 @@ /* peripheral libraries and drivers */ +/* HAL & SDK Drivers */ + +/* STM32 HAL & SDK Drivers */ + +/* end of STM32 HAL & SDK Drivers */ + +/* Infineon HAL Packages */ + +/* end of Infineon HAL Packages */ /* Kendryte SDK */ /* end of Kendryte SDK */ +/* end of HAL & SDK Drivers */ + +/* sensors drivers */ + +/* end of sensors drivers */ + +/* touch drivers */ + +/* end of touch drivers */ /* end of peripheral libraries and drivers */ /* AI packages */ /* end of AI packages */ +/* Signal Processing and Control Algorithm Packages */ + +/* end of Signal Processing and Control Algorithm Packages */ + /* miscellaneous packages */ /* project laboratory */ @@ -333,9 +367,9 @@ /* Arduino libraries */ -/* Projects */ +/* Projects and Demos */ -/* end of Projects */ +/* end of Projects and Demos */ /* Sensors */ @@ -365,6 +399,8 @@ /* Other */ +/* end of Other */ + /* Signal IO */ /* end of Signal IO */ diff --git a/bsp/cvitek/cv18xx_risc-v/.config b/bsp/cvitek/cv18xx_risc-v/.config index a5bec1c11e..012e96eeaa 100644 --- a/bsp/cvitek/cv18xx_risc-v/.config +++ b/bsp/cvitek/cv18xx_risc-v/.config @@ -15,7 +15,6 @@ CONFIG_RT_THREAD_PRIORITY_32=y # CONFIG_RT_THREAD_PRIORITY_256 is not set CONFIG_RT_THREAD_PRIORITY_MAX=32 CONFIG_RT_TICK_PER_SECOND=1000 -CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y CONFIG_RT_HOOK_USING_FUNC_PTR=y # CONFIG_RT_USING_HOOKLIST is not set @@ -25,6 +24,8 @@ CONFIG_IDLE_THREAD_STACK_SIZE=8192 CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 CONFIG_RT_TIMER_THREAD_STACK_SIZE=8192 +# CONFIG_RT_USING_TIMER_ALL_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set # # kservice optimization @@ -46,6 +47,7 @@ CONFIG_RT_DEBUGING_COLOR=y CONFIG_RT_DEBUGING_CONTEXT=y # CONFIG_RT_DEBUGING_AUTO_INIT is not set # CONFIG_RT_DEBUGING_PAGE_LEAK is not set +CONFIG_RT_USING_OVERFLOW_CHECK=y # # Inter-Thread communication @@ -95,6 +97,7 @@ CONFIG_RT_USING_CACHE=y CONFIG_ARCH_MM_MMU=y CONFIG_ARCH_RISCV=y CONFIG_ARCH_RISCV64=y +CONFIG_ARCH_USING_RISCV_COMMON64=y # # RT-Thread Components @@ -170,6 +173,7 @@ CONFIG_RT_USING_DFS_ROMFS=y # Device Drivers # # CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_DEV_BUS is not set CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_UNAMED_PIPE_NUMBER=64 CONFIG_RT_USING_SYSTEM_WORKQUEUE=y @@ -181,7 +185,9 @@ CONFIG_RT_USING_SERIAL_V1=y CONFIG_RT_SERIAL_USING_DMA=y CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_CAN is not set -# CONFIG_RT_USING_CPUTIME is not set +CONFIG_RT_USING_CPUTIME=y +CONFIG_RT_USING_CPUTIME_RISCV=y +CONFIG_CPUTIME_TIMER_FREQ=25000000 # CONFIG_RT_USING_I2C is not set # CONFIG_RT_USING_PHY is not set # CONFIG_RT_USING_ADC is not set @@ -190,6 +196,8 @@ CONFIG_RT_USING_NULL=y CONFIG_RT_USING_ZERO=y CONFIG_RT_USING_RANDOM=y # CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set # CONFIG_RT_USING_PM is not set @@ -210,21 +218,12 @@ CONFIG_RT_MMCSD_MAX_PARTITION=16 # CONFIG_RT_USING_TOUCH is not set # CONFIG_RT_USING_LCD is not set # CONFIG_RT_USING_HWCRYPTO is not set -# CONFIG_RT_USING_PULSE_ENCODER is not set -# CONFIG_RT_USING_INPUT_CAPTURE is not set -# CONFIG_RT_USING_DEV_BUS is not set # CONFIG_RT_USING_WIFI is not set # CONFIG_RT_USING_VIRTIO is not set CONFIG_RT_USING_PIN=y CONFIG_RT_USING_KTIME=y # CONFIG_RT_USING_HWTIMER is not set - -# -# Using USB -# -# CONFIG_RT_USING_USB_HOST is not set -# CONFIG_RT_USING_USB_DEVICE is not set -# end of Using USB +# CONFIG_RT_USING_CHERRYUSB is not set # end of Device Drivers # @@ -393,6 +392,15 @@ CONFIG_RT_USING_ADT_REF=y # end of Utilities # CONFIG_RT_USING_VBUS is not set + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set # end of RT-Thread Components # @@ -420,6 +428,7 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set # # Wi-Fi @@ -524,6 +533,7 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_ZEPHYR_POLLING is not set # CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set # CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set # end of IoT - internet of things # @@ -669,6 +679,8 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set # end of enhanced kernel services +# CONFIG_PKG_USING_AUNITY is not set + # # acceleration: Assembly language or algorithmic acceleration packages # @@ -759,11 +771,29 @@ CONFIG_RT_USING_ADT_REF=y # # STM32 HAL & SDK Drivers # -# CONFIG_PKG_USING_STM32L4XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set # CONFIG_PKG_USING_STM32WB55_SDK is not set # CONFIG_PKG_USING_STM32_SDIO is not set # end of STM32 HAL & SDK Drivers +# +# Infineon HAL Packages +# +# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set +# CONFIG_PKG_USING_INFINEON_CMSIS is not set +# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set +# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set +# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set +# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set +# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set +# CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + # CONFIG_PKG_USING_BLUETRUM_SDK is not set # CONFIG_PKG_USING_EMBARC_BSP is not set # CONFIG_PKG_USING_ESP_IDF is not set @@ -958,6 +988,7 @@ CONFIG_RT_USING_ADT_REF=y # # Signal Processing and Control Algorithm Packages # +# CONFIG_PKG_USING_APID is not set # CONFIG_PKG_USING_FIRE_PID_CURVE is not set # CONFIG_PKG_USING_QPID is not set # CONFIG_PKG_USING_UKAL is not set @@ -1270,6 +1301,72 @@ CONFIG_RT_USING_ADT_REF=y # end of Arduino libraries # end of RT-Thread online packages +# +# Privated Packages of RealThread +# +# CONFIG_PKG_USING_CODEC is not set +# CONFIG_PKG_USING_PLAYER is not set +# CONFIG_PKG_USING_MPLAYER is not set +# CONFIG_PKG_USING_PERSIMMON_SRC is not set +# CONFIG_PKG_USING_JS_PERSIMMON is not set +# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set + +# +# Network Utilities +# +# CONFIG_PKG_USING_MDNS is not set +# CONFIG_PKG_USING_UPNP is not set +# end of Network Utilities + +# CONFIG_PKG_USING_WICED is not set +# CONFIG_PKG_USING_CLOUDSDK is not set +# CONFIG_PKG_USING_POWER_MANAGER is not set +# CONFIG_PKG_USING_RT_OTA is not set +# CONFIG_PKG_USING_RTINSIGHT is not set +# CONFIG_PKG_USING_SMARTCONFIG is not set +# CONFIG_PKG_USING_RTX is not set +# CONFIG_RT_USING_TESTCASE is not set +# CONFIG_PKG_USING_NGHTTP2 is not set +# CONFIG_PKG_USING_AVS is not set +# CONFIG_PKG_USING_ALI_LINKKIT is not set +# CONFIG_PKG_USING_STS is not set +# CONFIG_PKG_USING_DLMS is not set +# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set +# CONFIG_PKG_USING_ZBAR is not set +# CONFIG_PKG_USING_MCF is not set +# CONFIG_PKG_USING_URPC is not set +# CONFIG_PKG_USING_DCM is not set +# CONFIG_PKG_USING_EMQ is not set +# CONFIG_PKG_USING_CFGM is not set +# CONFIG_PKG_USING_RT_CMSIS_DAP is not set +# CONFIG_PKG_USING_SMODULE is not set +# CONFIG_PKG_USING_SNFD is not set +# CONFIG_PKG_USING_UDBD is not set +# CONFIG_PKG_USING_BENCHMARK is not set +# CONFIG_PKG_USING_UBJSON is not set +# CONFIG_PKG_USING_DATATYPE is not set +# CONFIG_PKG_USING_FASTFS is not set +# CONFIG_PKG_USING_RIL is not set +# CONFIG_PKG_USING_WATCH_DCM_SVC is not set +# CONFIG_PKG_USING_WATCH_APP_FWK is not set +# CONFIG_PKG_USING_GUI_TEST is not set +# CONFIG_PKG_USING_PMEM is not set +# CONFIG_PKG_USING_LWRDP is not set +# CONFIG_PKG_USING_MASAN is not set +# CONFIG_PKG_USING_BSDIFF_LIB is not set +# CONFIG_PKG_USING_PRC_DIFF is not set + +# +# RT-Thread Smart +# +# CONFIG_PKG_USING_UKERNEL is not set +# end of RT-Thread Smart + +# CONFIG_PKG_USING_TRACE_AGENT is not set +# CONFIG_PKG_USING_DLOG is not set +# CONFIG_PKG_USING_EXT4 is not set +# end of Privated Packages of RealThread + # # General Drivers Configuration # diff --git a/bsp/cvitek/cv18xx_risc-v/Kconfig b/bsp/cvitek/cv18xx_risc-v/Kconfig index 326734f67e..e21d6bfedc 100755 --- a/bsp/cvitek/cv18xx_risc-v/Kconfig +++ b/bsp/cvitek/cv18xx_risc-v/Kconfig @@ -13,6 +13,7 @@ rsource "board/Kconfig" config BSP_USING_CV18XX bool select ARCH_RISCV64 + select ARCH_USING_RISCV_COMMON64 select RT_USING_SYSTEM_WORKQUEUE select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN @@ -26,7 +27,7 @@ config C906_PLIC_PHY_ADDR default 0x70000000 config IRQ_MAX_NR - int + int default 64 config TIMER_CLK_FREQ @@ -40,7 +41,7 @@ config GPIO_IRQ_BASE config SYS_GPIO_IRQ_BASE int default 70 - + config __STACKSIZE__ int "stack size for interrupt" default 4096 @@ -72,5 +73,5 @@ choice config BOARD_TYPE_MILKV_DUO256M_SPINOR select SOC_TYPE_SG2002 bool "milkv-duo256m-spinor" - + endchoice diff --git a/bsp/cvitek/cv18xx_risc-v/rtconfig.h b/bsp/cvitek/cv18xx_risc-v/rtconfig.h index 0574fefe54..f3d181d929 100755 --- a/bsp/cvitek/cv18xx_risc-v/rtconfig.h +++ b/bsp/cvitek/cv18xx_risc-v/rtconfig.h @@ -9,7 +9,6 @@ #define RT_THREAD_PRIORITY_32 #define RT_THREAD_PRIORITY_MAX 32 #define RT_TICK_PER_SECOND 1000 -#define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK @@ -31,6 +30,7 @@ #define RT_DEBUGING_ASSERT #define RT_DEBUGING_COLOR #define RT_DEBUGING_CONTEXT +#define RT_USING_OVERFLOW_CHECK /* Inter-Thread communication */ @@ -63,6 +63,7 @@ #define ARCH_MM_MMU #define ARCH_RISCV #define ARCH_RISCV64 +#define ARCH_USING_RISCV_COMMON64 /* RT-Thread Components */ @@ -123,6 +124,9 @@ #define RT_USING_SERIAL_V1 #define RT_SERIAL_USING_DMA #define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_CPUTIME +#define RT_USING_CPUTIME_RISCV +#define CPUTIME_TIMER_FREQ 25000000 #define RT_USING_NULL #define RT_USING_ZERO #define RT_USING_RANDOM @@ -135,10 +139,6 @@ #define RT_MMCSD_MAX_PARTITION 16 #define RT_USING_PIN #define RT_USING_KTIME - -/* Using USB */ - -/* end of Using USB */ /* end of Device Drivers */ /* C/C++ and POSIX layer */ @@ -252,6 +252,10 @@ #define RT_USING_ADT_HASHMAP #define RT_USING_ADT_REF /* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ /* end of RT-Thread Components */ /* RT-Thread Utestcases */ @@ -348,6 +352,10 @@ /* end of STM32 HAL & SDK Drivers */ +/* Infineon HAL Packages */ + +/* end of Infineon HAL Packages */ + /* Kendryte SDK */ /* end of Kendryte SDK */ @@ -431,6 +439,18 @@ /* end of Arduino libraries */ /* end of RT-Thread online packages */ +/* Privated Packages of RealThread */ + + +/* Network Utilities */ + +/* end of Network Utilities */ + +/* RT-Thread Smart */ + +/* end of RT-Thread Smart */ +/* end of Privated Packages of RealThread */ + /* General Drivers Configuration */ #define BSP_USING_UART diff --git a/bsp/qemu-virt64-riscv/.config b/bsp/qemu-virt64-riscv/.config index e4432617e6..9d21fb62cf 100644 --- a/bsp/qemu-virt64-riscv/.config +++ b/bsp/qemu-virt64-riscv/.config @@ -24,6 +24,7 @@ CONFIG_IDLE_THREAD_STACK_SIZE=16384 CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 CONFIG_RT_TIMER_THREAD_STACK_SIZE=16384 +# CONFIG_RT_USING_TIMER_ALL_SOFT is not set CONFIG_RT_USING_CPU_USAGE_TRACER=y # @@ -100,6 +101,7 @@ CONFIG_RT_USING_HW_ATOMIC=y CONFIG_ARCH_MM_MMU=y CONFIG_ARCH_RISCV=y CONFIG_ARCH_RISCV64=y +CONFIG_ARCH_USING_RISCV_COMMON64=y CONFIG_ARCH_REMAP_KERNEL=y # @@ -176,6 +178,7 @@ CONFIG_RT_USING_DFS_ROMFS=y # Device Drivers # # CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_DEV_BUS is not set CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_UNAMED_PIPE_NUMBER=64 CONFIG_RT_USING_SYSTEM_WORKQUEUE=y @@ -198,6 +201,8 @@ CONFIG_RT_USING_NULL=y CONFIG_RT_USING_ZERO=y CONFIG_RT_USING_RANDOM=y # CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set # CONFIG_RT_USING_PM is not set @@ -212,9 +217,6 @@ CONFIG_RT_USING_SOFT_RTC=y # CONFIG_RT_USING_TOUCH is not set # CONFIG_RT_USING_LCD is not set # CONFIG_RT_USING_HWCRYPTO is not set -# CONFIG_RT_USING_PULSE_ENCODER is not set -# CONFIG_RT_USING_INPUT_CAPTURE is not set -# CONFIG_RT_USING_DEV_BUS is not set # CONFIG_RT_USING_WIFI is not set CONFIG_RT_USING_VIRTIO=y CONFIG_RT_USING_VIRTIO10=y @@ -407,6 +409,8 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_RT_USING_USB_HOST is not set # CONFIG_RT_USING_USB_DEVICE is not set # end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set # end of RT-Thread Components # @@ -432,9 +436,9 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_KAWAII_MQTT is not set # CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set -# CONFIG_PKG_USING_LIBMODBUS is not set # CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set # # Wi-Fi @@ -453,6 +457,24 @@ CONFIG_RT_USING_ADT_REF=y # end of Wiced WiFi # CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set +# end of CYW43012 WiFi + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set +# end of BL808 WiFi + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# end of CYW43439 WiFi # end of Wi-Fi # CONFIG_PKG_USING_COAP is not set @@ -476,7 +498,6 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_JIOT-C-SDK is not set # CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set # CONFIG_PKG_USING_JOYLINK is not set -# CONFIG_PKG_USING_EZ_IOT_OS is not set # CONFIG_PKG_USING_IOTSHARP_SDK is not set # end of IoT Cloud @@ -499,6 +520,8 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_NMEALIB is not set # CONFIG_PKG_USING_PDULIB is not set # CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set # CONFIG_PKG_USING_LORAWAN_ED_STACK is not set # CONFIG_PKG_USING_WAYZ_IOTKIT is not set # CONFIG_PKG_USING_MAVLINK is not set @@ -507,6 +530,8 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_AGILE_FTP is not set # CONFIG_PKG_USING_EMBEDDEDPROTO is not set # CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set # CONFIG_PKG_USING_LORA_PKT_FWD is not set # CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set # CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set @@ -514,6 +539,11 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_SMALL_MODBUS is not set # CONFIG_PKG_USING_NET_SERVER is not set # CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set # end of IoT - internet of things # @@ -566,7 +596,6 @@ CONFIG_RT_USING_ADT_REF=y # LVGL: powerful and easy-to-use embedded GUI library # # CONFIG_PKG_USING_LVGL is not set -# CONFIG_PKG_USING_LITTLEVGL2RTT is not set # CONFIG_PKG_USING_LV_MUSIC_DEMO is not set # CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set # end of LVGL: powerful and easy-to-use embedded GUI library @@ -591,19 +620,12 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_MP3PLAYER is not set # CONFIG_PKG_USING_TINYJPEG is not set # CONFIG_PKG_USING_UGUI is not set - -# -# PainterEngine: A cross-platform graphics application framework written in C language -# -# CONFIG_PKG_USING_PAINTERENGINE is not set -# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set -# end of PainterEngine: A cross-platform graphics application framework written in C language - # CONFIG_PKG_USING_MCURSES is not set # CONFIG_PKG_USING_TERMBOX is not set # CONFIG_PKG_USING_VT100 is not set # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set # end of multimedia packages # @@ -614,9 +636,9 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_EASYLOGGER is not set # CONFIG_PKG_USING_SYSTEMVIEW is not set # CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set # CONFIG_PKG_USING_RDB is not set # CONFIG_PKG_USING_ULOG_EASYFLASH is not set -# CONFIG_PKG_USING_ULOG_FILE is not set # CONFIG_PKG_USING_LOGMGR is not set # CONFIG_PKG_USING_ADBD is not set # CONFIG_PKG_USING_COREMARK is not set @@ -650,9 +672,9 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_CBOX is not set # CONFIG_PKG_USING_SNOWFLAKE is not set # CONFIG_PKG_USING_HASH_MATCH is not set -# CONFIG_PKG_USING_FIRE_PID_CURVE is not set # CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set # CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_ZDEBUG is not set # end of tools packages # @@ -667,6 +689,8 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set # end of enhanced kernel services +# CONFIG_PKG_USING_AUNITY is not set + # # acceleration: Assembly language or algorithmic acceleration packages # @@ -679,6 +703,9 @@ CONFIG_RT_USING_ADT_REF=y # CMSIS: ARM Cortex-M Microcontroller Software Interface Standard # # CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_CORE is not set +# CONFIG_PKG_USING_CMSIS_DSP is not set +# CONFIG_PKG_USING_CMSIS_NN is not set # CONFIG_PKG_USING_CMSIS_RTOS1 is not set # CONFIG_PKG_USING_CMSIS_RTOS2 is not set # end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard @@ -695,10 +722,14 @@ CONFIG_RT_USING_ADT_REF=y # end of Micrium: Micrium software products porting for RT-Thread # CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set # CONFIG_PKG_USING_CAIRO is not set # CONFIG_PKG_USING_PIXMAN is not set # CONFIG_PKG_USING_PARTITION is not set # CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set # CONFIG_PKG_USING_FLASHDB is not set # CONFIG_PKG_USING_SQLITE is not set # CONFIG_PKG_USING_RTI is not set @@ -718,6 +749,7 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_QBOOT is not set # CONFIG_PKG_USING_PPOOL is not set # CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set # CONFIG_PKG_USING_LPM is not set # CONFIG_PKG_USING_TLSF is not set # CONFIG_PKG_USING_EVENT_RECORDER is not set @@ -729,30 +761,52 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_TFDB is not set # CONFIG_PKG_USING_QPC is not set # CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set # end of system packages # # peripheral libraries and drivers # -# CONFIG_PKG_USING_SENSORS_DRIVERS is not set -# CONFIG_PKG_USING_REALTEK_AMEBA is not set -# CONFIG_PKG_USING_SHT2X is not set -# CONFIG_PKG_USING_SHT3X is not set -# CONFIG_PKG_USING_ADT74XX is not set -# CONFIG_PKG_USING_AS7341 is not set + +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set # CONFIG_PKG_USING_STM32_SDIO is not set +# end of STM32 HAL & SDK Drivers + +# +# Infineon HAL Packages +# +# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set +# CONFIG_PKG_USING_INFINEON_CMSIS is not set +# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set +# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set +# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set +# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set +# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set +# CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set # CONFIG_PKG_USING_ESP_IDF is not set -# CONFIG_PKG_USING_ICM20608 is not set -# CONFIG_PKG_USING_BUTTON is not set -# CONFIG_PKG_USING_PCF8574 is not set -# CONFIG_PKG_USING_SX12XX is not set -# CONFIG_PKG_USING_SIGNAL_LED is not set -# CONFIG_PKG_USING_LEDBLINK is not set -# CONFIG_PKG_USING_LITTLED is not set -# CONFIG_PKG_USING_LKDGUI is not set -# CONFIG_PKG_USING_NRF5X_SDK is not set -# CONFIG_PKG_USING_NRFX is not set -# CONFIG_PKG_USING_WM_LIBRARIES is not set # # Kendryte SDK @@ -761,34 +815,128 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_KENDRYTE_SDK is not set # end of Kendryte SDK +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_NUCLEI_SDK is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# end of HAL & SDK Drivers + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set +# end of sensors drivers + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# end of touch drivers + +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set # CONFIG_PKG_USING_INFRARED is not set # CONFIG_PKG_USING_MULTI_INFRARED is not set # CONFIG_PKG_USING_AGILE_BUTTON is not set # CONFIG_PKG_USING_AGILE_LED is not set # CONFIG_PKG_USING_AT24CXX is not set # CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set -# CONFIG_PKG_USING_AD7746 is not set # CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set # CONFIG_PKG_USING_I2C_TOOLS is not set # CONFIG_PKG_USING_NRF24L01 is not set -# CONFIG_PKG_USING_TOUCH_DRIVERS is not set -# CONFIG_PKG_USING_MAX17048 is not set # CONFIG_PKG_USING_RPLIDAR is not set # CONFIG_PKG_USING_AS608 is not set # CONFIG_PKG_USING_RC522 is not set # CONFIG_PKG_USING_WS2812B is not set -# CONFIG_PKG_USING_EMBARC_BSP is not set # CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set # CONFIG_PKG_USING_MULTI_RTIMER is not set # CONFIG_PKG_USING_MAX7219 is not set # CONFIG_PKG_USING_BEEP is not set # CONFIG_PKG_USING_EASYBLINK is not set # CONFIG_PKG_USING_PMS_SERIES is not set -# CONFIG_PKG_USING_NUCLEI_SDK is not set # CONFIG_PKG_USING_CAN_YMODEM is not set # CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set # CONFIG_PKG_USING_QLED is not set -# CONFIG_PKG_USING_PAJ7620 is not set # CONFIG_PKG_USING_AGILE_CONSOLE is not set # CONFIG_PKG_USING_LD3320 is not set # CONFIG_PKG_USING_WK2124 is not set @@ -802,7 +950,6 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_VIRTUAL_SENSOR is not set # CONFIG_PKG_USING_VDEVICE is not set # CONFIG_PKG_USING_SGM706 is not set -# CONFIG_PKG_USING_STM32WB55_SDK is not set # CONFIG_PKG_USING_RDA58XX is not set # CONFIG_PKG_USING_LIBNFC is not set # CONFIG_PKG_USING_MFOC is not set @@ -812,17 +959,25 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_ROSSERIAL is not set # CONFIG_PKG_USING_MICRO_ROS is not set # CONFIG_PKG_USING_MCP23008 is not set -# CONFIG_PKG_USING_BLUETRUM_SDK is not set # CONFIG_PKG_USING_MISAKA_AT24CXX is not set # CONFIG_PKG_USING_MISAKA_RGB_BLING is not set # CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set -# CONFIG_PKG_USING_BL_MCU_SDK is not set # CONFIG_PKG_USING_SOFT_SERIAL is not set # CONFIG_PKG_USING_MB85RS16 is not set -# CONFIG_PKG_USING_CW2015 is not set # CONFIG_PKG_USING_RFM300 is not set # CONFIG_PKG_USING_IO_INPUT_FILTER is not set -# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set # end of peripheral libraries and drivers # @@ -837,8 +992,20 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_ULAPACK is not set # CONFIG_PKG_USING_QUEST is not set # CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set # end of AI packages +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_APID is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set +# end of Signal Processing and Control Algorithm Packages + # # miscellaneous packages # @@ -870,6 +1037,7 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_TETRIS is not set # CONFIG_PKG_USING_DONUT is not set # CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set # end of entertainment: terminal games and other interesting software packages # CONFIG_PKG_USING_LIBCSV is not set @@ -878,6 +1046,7 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_MINILZO is not set # CONFIG_PKG_USING_QUICKLZ is not set # CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set # CONFIG_PKG_USING_MULTIBUTTON is not set # CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set @@ -887,14 +1056,12 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set # CONFIG_PKG_USING_KENDRYTE_DEMO is not set -# CONFIG_PKG_USING_DIGITALCTRL is not set # CONFIG_PKG_USING_UPACKER is not set # CONFIG_PKG_USING_UPARAM is not set # CONFIG_PKG_USING_HELLO is not set # CONFIG_PKG_USING_VI is not set # CONFIG_PKG_USING_KI is not set # CONFIG_PKG_USING_ARMv7M_DWT is not set -# CONFIG_PKG_USING_UKAL is not set # CONFIG_PKG_USING_CRCLIB is not set # CONFIG_PKG_USING_LWGPS is not set # CONFIG_PKG_USING_STATE_MACHINE is not set @@ -905,6 +1072,7 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_SLCAN2RTT is not set # CONFIG_PKG_USING_SOEM is not set # CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set # end of miscellaneous packages # @@ -913,26 +1081,30 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_RTDUINO is not set # -# Projects +# Projects and Demos # +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set # CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set # CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set # CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set -# end of Projects +# end of Projects and Demos # # Sensors # -# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set -# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set -# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set @@ -974,7 +1146,7 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set -# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set @@ -1024,18 +1196,61 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set # end of Sensors # # Display # +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set # CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set # end of Display # # Timing # +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set # CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set # end of Timing # @@ -1043,6 +1258,8 @@ CONFIG_RT_USING_ADT_REF=y # # CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set # CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set +# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set # end of Data Processing # @@ -1061,11 +1278,19 @@ CONFIG_RT_USING_ADT_REF=y # # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set # end of Device Control # # Other # +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# end of Other # # Signal IO diff --git a/bsp/qemu-virt64-riscv/Kconfig b/bsp/qemu-virt64-riscv/Kconfig index ff7d3bca3d..053cacc57c 100644 --- a/bsp/qemu-virt64-riscv/Kconfig +++ b/bsp/qemu-virt64-riscv/Kconfig @@ -14,6 +14,7 @@ config BOARD_QEMU_VIRT_RV64 bool select ARCH_RISCV64 select ARCH_CONTEXT_EXTEND + select ARCH_USING_RISCV_COMMON64 select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN select RT_USING_CACHE diff --git a/bsp/qemu-virt64-riscv/rtconfig.h b/bsp/qemu-virt64-riscv/rtconfig.h index 1c0b681c28..e8669d9692 100644 --- a/bsp/qemu-virt64-riscv/rtconfig.h +++ b/bsp/qemu-virt64-riscv/rtconfig.h @@ -71,6 +71,7 @@ #define ARCH_MM_MMU #define ARCH_RISCV #define ARCH_RISCV64 +#define ARCH_USING_RISCV_COMMON64 #define ARCH_REMAP_KERNEL /* RT-Thread Components */ @@ -290,6 +291,18 @@ /* Wiced WiFi */ /* end of Wiced WiFi */ + +/* CYW43012 WiFi */ + +/* end of CYW43012 WiFi */ + +/* BL808 WiFi */ + +/* end of BL808 WiFi */ + +/* CYW43439 WiFi */ + +/* end of CYW43439 WiFi */ /* end of Wi-Fi */ /* IoT Cloud */ @@ -321,10 +334,6 @@ /* u8g2: a monochrome graphic library */ /* end of u8g2: a monochrome graphic library */ - -/* PainterEngine: A cross-platform graphics application framework written in C language */ - -/* end of PainterEngine: A cross-platform graphics application framework written in C language */ /* end of multimedia packages */ /* tools packages */ @@ -352,16 +361,38 @@ /* peripheral libraries and drivers */ +/* HAL & SDK Drivers */ + +/* STM32 HAL & SDK Drivers */ + +/* end of STM32 HAL & SDK Drivers */ + +/* Infineon HAL Packages */ + +/* end of Infineon HAL Packages */ /* Kendryte SDK */ /* end of Kendryte SDK */ +/* end of HAL & SDK Drivers */ + +/* sensors drivers */ + +/* end of sensors drivers */ + +/* touch drivers */ + +/* end of touch drivers */ /* end of peripheral libraries and drivers */ /* AI packages */ /* end of AI packages */ +/* Signal Processing and Control Algorithm Packages */ + +/* end of Signal Processing and Control Algorithm Packages */ + /* miscellaneous packages */ /* project laboratory */ @@ -380,9 +411,9 @@ /* Arduino libraries */ -/* Projects */ +/* Projects and Demos */ -/* end of Projects */ +/* end of Projects and Demos */ /* Sensors */ @@ -412,6 +443,8 @@ /* Other */ +/* end of Other */ + /* Signal IO */ /* end of Signal IO */ diff --git a/components/drivers/include/drivers/cputime.h b/components/drivers/include/drivers/cputime.h index 3b1eb2aec0..478ccfd019 100644 --- a/components/drivers/include/drivers/cputime.h +++ b/components/drivers/include/drivers/cputime.h @@ -31,4 +31,8 @@ uint64_t clock_cpu_millisecond(uint64_t cpu_tick); int clock_cpu_setops(const struct rt_clock_cputime_ops *ops); +#ifdef RT_USING_CPUTIME_RISCV +int riscv_cputime_init(void); +#endif /* RT_USING_CPUTIME_RISCV */ + #endif diff --git a/libcpu/Kconfig b/libcpu/Kconfig index 2c07f463c5..ca5fdd9e34 100644 --- a/libcpu/Kconfig +++ b/libcpu/Kconfig @@ -262,6 +262,15 @@ config ARCH_RISCV64 select ARCH_CPU_64BIT bool +if ARCH_RISCV64 + config ARCH_USING_RISCV_COMMON64 + bool + depends on ARCH_RISCV64 + select RT_USING_CPUTIME + help + Using the common64 implementation under ./libcpu/risc-v +endif + config ARCH_REMAP_KERNEL bool depends on RT_USING_SMART diff --git a/libcpu/risc-v/t-head/c906/tick.c b/libcpu/risc-v/t-head/c906/tick.c index 79891adb0e..8e8ff86a74 100644 --- a/libcpu/risc-v/t-head/c906/tick.c +++ b/libcpu/risc-v/t-head/c906/tick.c @@ -6,44 +6,50 @@ * Change Logs: * Date Author Notes * 2018/10/28 Bernard The unify RISC-V porting code. + * 2024/07/08 Shell Using CPUTIME as tick */ #include #include +#include #include #include "sbi.h" -#include "tick.h" -static volatile uint64_t time_elapsed = 0; +#ifdef RT_USING_KTIME +#include +#endif + static volatile unsigned long tick_cycles = 0; -static unsigned long tick_delta = TIMER_CLK_FREQ / RT_TICK_PER_SECOND; - -static uint64_t get_ticks() -{ - __asm__ __volatile__( - "rdtime %0" - : "=r"(time_elapsed)); - return time_elapsed; -} - int tick_isr(void) { rt_tick_increase(); - sbi_set_timer(get_ticks() + tick_delta); + sbi_set_timer(clock_cpu_gettime() + tick_cycles); return 0; } +/* BSP should config clockbase frequency */ +RT_STATIC_ASSERT(defined_clockbase_freq, CPUTIME_TIMER_FREQ != 0); + /* Sets and enable the timer interrupt */ int rt_hw_tick_init(void) { + /* calculate the tick cycles */ + tick_cycles = CPUTIME_TIMER_FREQ / RT_TICK_PER_SECOND; + /* Clear the Supervisor-Timer bit in SIE */ clear_csr(sie, SIP_STIP); - /* Set timer */ - sbi_set_timer(get_ticks() + tick_delta); + /* Init riscv timer */ + riscv_cputime_init(); + /* Set timer */ + sbi_set_timer(clock_cpu_gettime() + tick_cycles); + +#ifdef RT_USING_KTIME + rt_ktime_cputimer_init(); +#endif /* Enable the Supervisor-Timer bit in SIE */ set_csr(sie, SIP_STIP); @@ -61,10 +67,10 @@ void rt_hw_us_delay(rt_uint32_t us) unsigned long end_time; unsigned long run_time; - start_time = get_ticks(); - end_time = start_time + us * (TIMER_CLK_FREQ / 1000000); + start_time = clock_cpu_gettime(); + end_time = start_time + us * (CPUTIME_TIMER_FREQ / 1000000); do { - run_time = get_ticks(); + run_time = clock_cpu_gettime(); } while(run_time < end_time); -} \ No newline at end of file +} diff --git a/libcpu/risc-v/t-head/c906/tick.h b/libcpu/risc-v/t-head/c906/tick.h index 00e4c120b7..6d0e8a90b6 100644 --- a/libcpu/risc-v/t-head/c906/tick.h +++ b/libcpu/risc-v/t-head/c906/tick.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2023, RT-Thread Development Team + * Copyright (c) 2006-2024, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -11,10 +11,6 @@ #ifndef TICK_H__ #define TICK_H__ -/* timer clock is 24 MHZ */ -#ifndef TIMER_CLK_FREQ -#define TIMER_CLK_FREQ (24000000) -#endif int tick_isr(void); int rt_hw_tick_init(void); diff --git a/libcpu/risc-v/virt64/tick.c b/libcpu/risc-v/virt64/tick.c index 3dd9af48a3..8e8ff86a74 100644 --- a/libcpu/risc-v/virt64/tick.c +++ b/libcpu/risc-v/virt64/tick.c @@ -6,11 +6,13 @@ * Change Logs: * Date Author Notes * 2018/10/28 Bernard The unify RISC-V porting code. + * 2024/07/08 Shell Using CPUTIME as tick */ #include #include +#include #include #include "sbi.h" @@ -18,40 +20,32 @@ #include #endif -static volatile uint64_t time_elapsed = 0; static volatile unsigned long tick_cycles = 0; -static uint64_t get_ticks() -{ - __asm__ __volatile__( - "rdtime %0" - : "=r"(time_elapsed)); - return time_elapsed; -} - int tick_isr(void) { - // uint64_t core_id = current_coreid(); - // clint->mtimecmp[core_id] += tick_cycles; rt_tick_increase(); - sbi_set_timer(get_ticks() + tick_cycles); - + sbi_set_timer(clock_cpu_gettime() + tick_cycles); return 0; } +/* BSP should config clockbase frequency */ +RT_STATIC_ASSERT(defined_clockbase_freq, CPUTIME_TIMER_FREQ != 0); + /* Sets and enable the timer interrupt */ int rt_hw_tick_init(void) { - /* Read core id */ - // unsigned long core_id = current_coreid(); + /* calculate the tick cycles */ + tick_cycles = CPUTIME_TIMER_FREQ / RT_TICK_PER_SECOND; /* Clear the Supervisor-Timer bit in SIE */ clear_csr(sie, SIP_STIP); - /* calculate the tick cycles */ - tick_cycles = CPUTIME_TIMER_FREQ / RT_TICK_PER_SECOND; + /* Init riscv timer */ + riscv_cputime_init(); + /* Set timer */ - sbi_set_timer(get_ticks() + tick_cycles); + sbi_set_timer(clock_cpu_gettime() + tick_cycles); #ifdef RT_USING_KTIME rt_ktime_cputimer_init(); @@ -61,3 +55,22 @@ int rt_hw_tick_init(void) return 0; } + +/** + * This function will delay for some us. + * + * @param us the delay time of us + */ +void rt_hw_us_delay(rt_uint32_t us) +{ + unsigned long start_time; + unsigned long end_time; + unsigned long run_time; + + start_time = clock_cpu_gettime(); + end_time = start_time + us * (CPUTIME_TIMER_FREQ / 1000000); + do + { + run_time = clock_cpu_gettime(); + } while(run_time < end_time); +} diff --git a/libcpu/risc-v/virt64/tick.h b/libcpu/risc-v/virt64/tick.h index 0bfd6f62e8..6d0e8a90b6 100644 --- a/libcpu/risc-v/virt64/tick.h +++ b/libcpu/risc-v/virt64/tick.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2024, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * From 80668e0ba20572d98300fdbaeb31a7aaf698b443 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Fri, 24 May 2024 08:58:09 +0800 Subject: [PATCH 02/48] bsp:cvitek: revert add i2c pinmux config for c906 The contents of the SOC type part in the Kconfig configuration are retained, and other parts related to I2C pin multiplexing selection have been rolled back. Signed-off-by: Chen Wang Reviewed-by: Yuanjie He <943313837@qq.com> Reviewed-by: Shell --- bsp/cvitek/c906_little/board/Kconfig | 115 --------- bsp/cvitek/cv18xx_risc-v/board/Kconfig | 115 --------- bsp/cvitek/drivers/drv_hw_i2c.c | 326 +------------------------ 3 files changed, 9 insertions(+), 547 deletions(-) diff --git a/bsp/cvitek/c906_little/board/Kconfig b/bsp/cvitek/c906_little/board/Kconfig index 52fdc2d2a9..06d8214321 100755 --- a/bsp/cvitek/c906_little/board/Kconfig +++ b/bsp/cvitek/c906_little/board/Kconfig @@ -29,127 +29,12 @@ menu "General Drivers Configuration" if BSP_USING_I2C config BSP_USING_I2C0 bool "Enable I2C0" - depends on BOARD_TYPE_MILKV_DUO || BOARD_TYPE_MILKV_DUO_SPINOR default n - if BSP_USING_I2C0 - choice - prompt "SCL" - - config BSP_USING_IIC0_SCL__IIC0_SCL - bool "IIC0_SCL/GP0" - endchoice - - choice - prompt "SDA" - - config BSP_USING_IIC0_SDA__IIC0_SDA - bool "IIC0_SDA/GP1" - endchoice - endif - config BSP_USING_I2C1 bool "Enable I2C1" default n - if BSP_USING_I2C1 - choice - prompt "SCL" - - if BOARD_TYPE_MILKV_DUO || BOARD_TYPE_MILKV_DUO_SPINOR - config BSP_USING_SD1_D2__IIC1_SCL - bool "SD1_D2/GP4" - config BSP_USING_SD1_D3__IIC1_SCL - bool "SD1_D3/GP9" - config BSP_USING_PAD_MIPIRX0N__IIC1_SCL - bool "PAD_MIPIRX0N/GP11" - endif - - if BOARD_TYPE_MILKV_DUO256M || BOARD_TYPE_MILKV_DUO256M_SPINOR - config BSP_USING_SD1_D2__IIC1_SCL - bool "SD1_D2/GP4" - config BSP_USING_SD1_D3__IIC1_SCL - bool "SD1_D3/GP9" - endif - - endchoice - - choice - prompt "SDA" - - if BOARD_TYPE_MILKV_DUO || BOARD_TYPE_MILKV_DUO_SPINOR - config BSP_USING_SD1_D1__IIC1_SDA - bool "SD1_D1/GP5" - config BSP_USING_SD1_D0__IIC1_SDA - bool "SD1_D0/GP8" - config BSP_USING_PAD_MIPIRX1P__IIC1_SDA - bool "PAD_MIPIRX1P/GP10" - endif - - if BOARD_TYPE_MILKV_DUO256M || BOARD_TYPE_MILKV_DUO256M_SPINOR - config BSP_USING_SD1_D1__IIC1_SDA - bool "SD1_D1/GP5" - config BSP_USING_SD1_D0__IIC1_SDA - bool "SD1_D0/GP8" - endif - endchoice - endif - - config BSP_USING_I2C2 - bool "Enable I2C2" - depends on BOARD_TYPE_MILKV_DUO256M || BOARD_TYPE_MILKV_DUO256M_SPINOR - default n - - if BSP_USING_I2C2 - choice - prompt "SCL" - - config BSP_USING_PAD_MIPI_TXP1__IIC2_SCL - bool "PAD_MIPI_TXP1/GP11" - endchoice - - choice - prompt "SDA" - - config BSP_USING_PAD_MIPI_TXM1__IIC2_SDA - bool "PAD_MIPI_TXM1/GP10" - endchoice - endif - - config BSP_USING_I2C3 - bool "Enable I2C3" - default n - - if BSP_USING_I2C3 - choice - prompt "SCL" - - if BOARD_TYPE_MILKV_DUO || BOARD_TYPE_MILKV_DUO_SPINOR - config BSP_USING_SD1_CMD__IIC3_SCL - bool "SD1_CMD/GP7" - endif - - if BOARD_TYPE_MILKV_DUO256M || BOARD_TYPE_MILKV_DUO256M_SPINOR - config BSP_USING_SD1_CMD__IIC3_SCL - bool "SD1_CMD/GP7" - endif - endchoice - - choice - prompt "SDA" - - if BOARD_TYPE_MILKV_DUO || BOARD_TYPE_MILKV_DUO_SPINOR - config BSP_USING_SD1_CLK__IIC3_SDA - bool "SD1_CLK/GP6" - endif - - if BOARD_TYPE_MILKV_DUO256M || BOARD_TYPE_MILKV_DUO256M_SPINOR - config BSP_USING_SD1_CLK__IIC3_SDA - bool "SD1_CLK/GP6" - endif - endchoice - endif - config I2C_IRQ_BASE int default 32 diff --git a/bsp/cvitek/cv18xx_risc-v/board/Kconfig b/bsp/cvitek/cv18xx_risc-v/board/Kconfig index 50efa0e0b0..bc213c777e 100755 --- a/bsp/cvitek/cv18xx_risc-v/board/Kconfig +++ b/bsp/cvitek/cv18xx_risc-v/board/Kconfig @@ -42,127 +42,12 @@ menu "General Drivers Configuration" if BSP_USING_I2C config BSP_USING_I2C0 bool "Enable I2C0" - depends on BOARD_TYPE_MILKV_DUO || BOARD_TYPE_MILKV_DUO_SPINOR default n - if BSP_USING_I2C0 - choice - prompt "SCL" - - config BSP_USING_IIC0_SCL__IIC0_SCL - bool "IIC0_SCL/GP0" - endchoice - - choice - prompt "SDA" - - config BSP_USING_IIC0_SDA__IIC0_SDA - bool "IIC0_SDA/GP1" - endchoice - endif - config BSP_USING_I2C1 bool "Enable I2C1" default n - if BSP_USING_I2C1 - choice - prompt "SCL" - - if BOARD_TYPE_MILKV_DUO || BOARD_TYPE_MILKV_DUO_SPINOR - config BSP_USING_SD1_D2__IIC1_SCL - bool "SD1_D2/GP4" - config BSP_USING_SD1_D3__IIC1_SCL - bool "SD1_D3/GP9" - config BSP_USING_PAD_MIPIRX0N__IIC1_SCL - bool "PAD_MIPIRX0N/GP11" - endif - - if BOARD_TYPE_MILKV_DUO256M || BOARD_TYPE_MILKV_DUO256M_SPINOR - config BSP_USING_SD1_D2__IIC1_SCL - bool "SD1_D2/GP4" - config BSP_USING_SD1_D3__IIC1_SCL - bool "SD1_D3/GP9" - endif - - endchoice - - choice - prompt "SDA" - - if BOARD_TYPE_MILKV_DUO || BOARD_TYPE_MILKV_DUO_SPINOR - config BSP_USING_SD1_D1__IIC1_SDA - bool "SD1_D1/GP5" - config BSP_USING_SD1_D0__IIC1_SDA - bool "SD1_D0/GP8" - config BSP_USING_PAD_MIPIRX1P__IIC1_SDA - bool "PAD_MIPIRX1P/GP10" - endif - - if BOARD_TYPE_MILKV_DUO256M || BOARD_TYPE_MILKV_DUO256M_SPINOR - config BSP_USING_SD1_D1__IIC1_SDA - bool "SD1_D1/GP5" - config BSP_USING_SD1_D0__IIC1_SDA - bool "SD1_D0/GP8" - endif - endchoice - endif - - config BSP_USING_I2C2 - bool "Enable I2C2" - depends on BOARD_TYPE_MILKV_DUO256M || BOARD_TYPE_MILKV_DUO256M_SPINOR - default n - - if BSP_USING_I2C2 - choice - prompt "SCL" - - config BSP_USING_PAD_MIPI_TXP1__IIC2_SCL - bool "PAD_MIPI_TXP1/GP11" - endchoice - - choice - prompt "SDA" - - config BSP_USING_PAD_MIPI_TXM1__IIC2_SDA - bool "PAD_MIPI_TXM1/GP10" - endchoice - endif - - config BSP_USING_I2C3 - bool "Enable I2C3" - default n - - if BSP_USING_I2C3 - choice - prompt "SCL" - - if BOARD_TYPE_MILKV_DUO || BOARD_TYPE_MILKV_DUO_SPINOR - config BSP_USING_SD1_CMD__IIC3_SCL - bool "SD1_CMD/GP7" - endif - - if BOARD_TYPE_MILKV_DUO256M || BOARD_TYPE_MILKV_DUO256M_SPINOR - config BSP_USING_SD1_CMD__IIC3_SCL - bool "SD1_CMD/GP7" - endif - endchoice - - choice - prompt "SDA" - - if BOARD_TYPE_MILKV_DUO || BOARD_TYPE_MILKV_DUO_SPINOR - config BSP_USING_SD1_CLK__IIC3_SDA - bool "SD1_CLK/GP6" - endif - - if BOARD_TYPE_MILKV_DUO256M || BOARD_TYPE_MILKV_DUO256M_SPINOR - config BSP_USING_SD1_CLK__IIC3_SDA - bool "SD1_CLK/GP6" - endif - endchoice - endif - config I2C_IRQ_BASE int default 49 diff --git a/bsp/cvitek/drivers/drv_hw_i2c.c b/bsp/cvitek/drivers/drv_hw_i2c.c index 3189de4579..022a050c74 100644 --- a/bsp/cvitek/drivers/drv_hw_i2c.c +++ b/bsp/cvitek/drivers/drv_hw_i2c.c @@ -467,327 +467,19 @@ static const struct rt_i2c_bus_device_ops i2c_ops = .i2c_bus_control = RT_NULL }; -static void rt_hw_i2c_pinmux_config_i2c0() -{ -#ifdef BSP_USING_I2C0 - - // SCL - #if defined(SOC_TYPE_CV180X) - #if defined(BSP_USING_IIC0_SCL__IIC0_SCL) - PINMUX_CONFIG(IIC0_SCL, IIC0_SCL); - #elif defined(BSP_USING_PWR_GPIO2__IIC0_SCL) - PINMUX_CONFIG(PWR_GPIO2, IIC0_SCL); - #elif defined(BSP_USING_PAD_MIPIRX4N__IIC0_SCL) - PINMUX_CONFIG(PAD_MIPIRX4N, IIC0_SCL); - #elif defined(BSP_USING_PAD_MIPI_TXP2__IIC0_SCL) - PINMUX_CONFIG(PAD_MIPI_TXP2, IIC0_SCL); - #endif - #endif // SOC_TYPE_CV180X - - #if defined(SOC_TYPE_SG2002) - #if defined(BSP_USING_IIC0_SCL__IIC0_SCL) - PINMUX_CONFIG(IIC0_SCL, IIC0_SCL); - #endif - #endif // SOC_TYPE_SG2002 - - // SDA - #if defined(SOC_TYPE_CV180X) - #if defined(BSP_USING_IIC0_SDA__IIC0_SDA) - PINMUX_CONFIG(IIC0_SDA, IIC0_SDA); - #elif defined(BSP_USING_PWR_GPIO1__IIC0_SDA) - PINMUX_CONFIG(PWR_GPIO1, IIC0_SDA); - #elif defined(BSP_USING_PAD_MIPIRX4P__IIC0_SDA) - PINMUX_CONFIG(PAD_MIPIRX4P, IIC0_SDA); - #elif defined(BSP_USING_PAD_MIPI_TXM2__IIC0_SDA) - PINMUX_CONFIG(PAD_MIPI_TXM2, IIC0_SDA); - #endif - #endif // SOC_TYPE_CV180X - - #if defined(SOC_TYPE_SG2002) - #if defined(BSP_USING_IIC0_SDA__IIC0_SDA) - PINMUX_CONFIG(IIC0_SDA, IIC0_SDA); - #endif - #endif // SOC_TYPE_SG2002 - -#endif /* BSP_USING_I2C0 */ -} - -static void rt_hw_i2c_pinmux_config_i2c1() -{ -#ifdef BSP_USING_I2C1 - - // SCL - #if defined(SOC_TYPE_CV180X) - #if defined(BSP_USING_SD0_CMD__IIC1_SCL) - PINMUX_CONFIG(SD0_CMD, IIC1_SCL); - #elif defined(BSP_USING_SD0_D2__IIC1_SCL) - PINMUX_CONFIG(SD0_D2, IIC1_SCL); - #elif defined(BSP_USING_SD1_D3__IIC1_SCL) - PINMUX_CONFIG(SD1_D3, IIC1_SCL); - #elif defined(BSP_USING_SD1_D2__IIC1_SCL) - PINMUX_CONFIG(SD1_D2, IIC1_SCL); - #elif defined(BSP_USING_MUX_SPI1_MOSI__IIC1_SCL) - PINMUX_CONFIG(MUX_SPI1_MOSI, IIC1_SCL); - #elif defined(BSP_USING_PAD_ETH_TXP__IIC1_SCL) - PINMUX_CONFIG(PAD_ETH_TXP, IIC1_SCL); - #elif defined(BSP_USING_PAD_MIPIRX4P__IIC1_SCL) - PINMUX_CONFIG(PAD_MIPIRX4P, IIC1_SCL); - #elif defined(BSP_USING_PAD_MIPIRX0N__IIC1_SCL) - PINMUX_CONFIG(PAD_MIPIRX0N, IIC1_SCL); - #elif defined(BSP_USING_PAD_MIPI_TXP2__IIC1_SCL) - PINMUX_CONFIG(PAD_MIPI_TXP2, IIC1_SCL); - #endif - #endif // SOC_TYPE_CV180X - - #if defined(SOC_TYPE_SG2002) - #if defined(BSP_USING_SD0_CMD__IIC1_SCL) - PINMUX_CONFIG(SD0_CMD, IIC1_SCL); - #elif defined(BSP_USING_SD0_D2__IIC1_SCL) - PINMUX_CONFIG(SD0_D2, IIC1_SCL); - #elif defined(BSP_USING_SD1_D3__IIC1_SCL) - PINMUX_CONFIG(SD1_D3, IIC1_SCL); - #elif defined(BSP_USING_SD1_D2__IIC1_SCL) - PINMUX_CONFIG(SD1_D2, IIC1_SCL); - #elif defined(BSP_USING_MUX_SPI1_MOSI__IIC1_SCL) - PINMUX_CONFIG(MUX_SPI1_MOSI, IIC1_SCL); - #elif defined(BSP_USING_PAD_ETH_TXP__IIC1_SCL) - PINMUX_CONFIG(PAD_ETH_TXP, IIC1_SCL); - #elif defined(BSP_USING_VIVO_D9__IIC1_SCL) - PINMUX_CONFIG(VIVO_D9, IIC1_SCL); - #elif defined(BSP_USING_VIVO_D3__IIC1_SCL) - PINMUX_CONFIG(VIVO_D3, IIC1_SCL); - #elif defined(BSP_USING_PAD_MIPIRX4P__IIC1_SCL) - PINMUX_CONFIG(PAD_MIPIRX4P, IIC1_SCL); - #elif defined(BSP_USING_PAD_MIPIRX0N__IIC1_SCL) - PINMUX_CONFIG(PAD_MIPIRX0N, IIC1_SCL); - #elif defined(BSP_USING_PAD_MIPI_TXP4__IIC1_SCL) - PINMUX_CONFIG(PAD_MIPI_TXP4, IIC1_SCL); - #elif defined(BSP_USING_PAD_MIPI_TXP3__IIC1_SCL) - PINMUX_CONFIG(PAD_MIPI_TXP3, IIC1_SCL); - #elif defined(BSP_USING_PAD_MIPI_TXP2__IIC1_SCL) - PINMUX_CONFIG(PAD_MIPI_TXP2, IIC1_SCL); - #endif - #endif // SOC_TYPE_SG2002 - - // SDA - #if defined(SOC_TYPE_CV180X) - #if defined(BSP_USING_SD0_CLK__IIC1_SDA) - PINMUX_CONFIG(SD0_CLK, IIC1_SDA); - #elif defined(BSP_USING_SD0_D1__IIC1_SDA) - PINMUX_CONFIG(SD0_D1, IIC1_SDA); - #elif defined(BSP_USING_SD1_D1__IIC1_SDA) - PINMUX_CONFIG(SD1_D1, IIC1_SDA); - #elif defined(BSP_USING_SD1_D0__IIC1_SDA) - PINMUX_CONFIG(SD1_D0, IIC1_SDA); - #elif defined(BSP_USING_MUX_SPI1_MISO__IIC1_SDA) - PINMUX_CONFIG(MUX_SPI1_MISO, IIC1_SDA); - #elif defined(BSP_USING_PAD_ETH_TXM__IIC1_SDA) - PINMUX_CONFIG(PAD_ETH_TXM, IIC1_SDA); - #elif defined(BSP_USING_PAD_MIPIRX4N__IIC1_SDA) - PINMUX_CONFIG(PAD_MIPIRX4N, IIC1_SDA); - #elif defined(BSP_USING_PAD_MIPIRX1P__IIC1_SDA) - PINMUX_CONFIG(PAD_MIPIRX1P, IIC1_SDA); - #elif defined(BSP_USING_PAD_MIPI_TXM2__IIC1_SDA) - PINMUX_CONFIG(PAD_MIPI_TXM2, IIC1_SDA); - #endif - #endif // SOC_TYPE_CV180X - - #if defined(SOC_TYPE_SG2002) - #if defined(BSP_USING_SD0_CLK__IIC1_SDA) - PINMUX_CONFIG(SD0_CLK, IIC1_SDA); - #elif defined(BSP_USING_SD0_D1__IIC1_SDA) - PINMUX_CONFIG(SD0_D1, IIC1_SDA); - #elif defined(BSP_USING_SD1_D1__IIC1_SDA) - PINMUX_CONFIG(SD1_D1, IIC1_SDA); - #elif defined(BSP_USING_SD1_D0__IIC1_SDA) - PINMUX_CONFIG(SD1_D0, IIC1_SDA); - #elif defined(BSP_USING_MUX_SPI1_MISO__IIC1_SDA) - PINMUX_CONFIG(MUX_SPI1_MISO, IIC1_SDA); - #elif defined(BSP_USING_PAD_ETH_TXM__IIC1_SDA) - PINMUX_CONFIG(PAD_ETH_TXM, IIC1_SDA); - #elif defined(BSP_USING_VIVO_D10__IIC1_SDA) - PINMUX_CONFIG(VIVO_D10, IIC1_SDA); - #elif defined(BSP_USING_VIVO_D4__IIC1_SDA) - PINMUX_CONFIG(VIVO_D4, IIC1_SDA); - #elif defined(BSP_USING_PAD_MIPIRX4N__IIC1_SDA) - PINMUX_CONFIG(PAD_MIPIRX4N, IIC1_SDA); - #elif defined(BSP_USING_PAD_MIPIRX1P__IIC1_SDA) - PINMUX_CONFIG(PAD_MIPIRX1P, IIC1_SDA); - #elif defined(BSP_USING_PAD_MIPI_TXM4__IIC1_SDA) - PINMUX_CONFIG(PAD_MIPI_TXM4, IIC1_SDA); - #elif defined(BSP_USING_PAD_MIPI_TXM3__IIC1_SDA) - PINMUX_CONFIG(PAD_MIPI_TXM3, IIC1_SDA); - #elif defined(BSP_USING_PAD_MIPI_TXM2__IIC1_SDA) - PINMUX_CONFIG(PAD_MIPI_TXM2, IIC1_SDA); - #endif - #endif // SOC_TYPE_SG2002 - -#endif /* BSP_USING_I2C1 */ -} - -static void rt_hw_i2c_pinmux_config_i2c2() -{ -#ifdef BSP_USING_I2C2 - - // SCL - #if defined(SOC_TYPE_CV180X) - #if defined(BSP_USING_PWR_GPIO1__IIC2_SCL) - PINMUX_CONFIG(PWR_GPIO1, IIC2_SCL); - #elif defined(BSP_USING_PAD_MIPI_TXP1__IIC2_SCL) - PINMUX_CONFIG(PAD_MIPI_TXP1, IIC2_SCL); - #endif - #endif // SOC_TYPE_CV180X - - #if defined(SOC_TYPE_SG2002) - #if defined(BSP_USING_PWR_GPIO1__IIC2_SCL) - PINMUX_CONFIG(PWR_GPIO1, IIC2_SCL); - #elif defined(BSP_USING_IIC2_SCL__IIC2_SCL) - PINMUX_CONFIG(IIC2_SCL, IIC2_SCL); - #elif defined(BSP_USING_VIVO_D8__IIC2_SCL) - PINMUX_CONFIG(VIVO_D8, IIC2_SCL); - #elif defined(BSP_USING_PAD_MIPI_TXP3__IIC2_SCL) - PINMUX_CONFIG(PAD_MIPI_TXP3, IIC2_SCL); - #elif defined(BSP_USING_PAD_MIPI_TXP1__IIC2_SCL) - PINMUX_CONFIG(PAD_MIPI_TXP1, IIC2_SCL); - #endif - #endif // SOC_TYPE_SG2002 - - // SDA - #if defined(SOC_TYPE_CV180X) - #if defined(BSP_USING_PWR_GPIO2__IIC2_SDA) - PINMUX_CONFIG(PWR_GPIO2, IIC2_SDA); - #elif defined(BSP_USING_PAD_MIPI_TXM1__IIC2_SDA) - PINMUX_CONFIG(PAD_MIPI_TXM1, IIC2_SDA); - #endif - #endif // SOC_TYPE_CV180X - - #if defined(SOC_TYPE_SG2002) - #if defined(BSP_USING_PWR_GPIO2__IIC2_SDA) - PINMUX_CONFIG(PWR_GPIO2, IIC2_SDA); - #elif defined(BSP_USING_IIC2_SDA__IIC2_SDA) - PINMUX_CONFIG(IIC2_SDA, IIC2_SDA); - #elif defined(BSP_USING_VIVO_D7__IIC2_SDA) - PINMUX_CONFIG(VIVO_D7, IIC2_SDA); - #elif defined(BSP_USING_PAD_MIPI_TXM3__IIC2_SDA) - PINMUX_CONFIG(PAD_MIPI_TXM3, IIC2_SDA); - #elif defined(BSP_USING_PAD_MIPI_TXM1__IIC2_SDA) - PINMUX_CONFIG(PAD_MIPI_TXM1, IIC2_SDA); - #endif - #endif // SOC_TYPE_SG2002 - -#endif /* BSP_USING_I2C2 */ -} - -static void rt_hw_i2c_pinmux_config_i2c3() -{ -#ifdef BSP_USING_I2C3 - - // SCL - #if defined(SOC_TYPE_CV180X) - #if defined(BSP_USING_SD1_CMD__IIC3_SCL) - PINMUX_CONFIG(SD1_CMD, IIC3_SCL); - #endif - #endif // SOC_TYPE_CV180X - - #if defined(SOC_TYPE_SG2002) - #if defined(BSP_USING_IIC3_SCL__IIC3_SCL) - PINMUX_CONFIG(IIC3_SCL, IIC3_SCL); - #elif defined(BSP_USING_SD1_CMD__IIC3_SCL) - PINMUX_CONFIG(SD1_CMD, IIC3_SCL); - #elif defined(BSP_USING_VIVO_D0__IIC3_SCL) - PINMUX_CONFIG(VIVO_D0, IIC3_SCL); - #endif - #endif // SOC_TYPE_SG2002 - - // SDA - #if defined(SOC_TYPE_CV180X) - #if defined(BSP_USING_SD1_CLK__IIC3_SDA) - PINMUX_CONFIG(SD1_CLK, IIC3_SDA); - #endif - #endif // SOC_TYPE_CV180X - - #if defined(SOC_TYPE_SG2002) - #if defined(BSP_USING_IIC3_SDA__IIC3_SDA) - PINMUX_CONFIG(IIC3_SDA, IIC3_SDA); - #elif defined(BSP_USING_SD1_CLK__IIC3_SDA) - PINMUX_CONFIG(SD1_CLK, IIC3_SDA); - #elif defined(BSP_USING_VIVO_D1__IIC3_SDA) - PINMUX_CONFIG(VIVO_D1, IIC3_SDA); - #endif - #endif // SOC_TYPE_SG2002 - -#endif /* BSP_USING_I2C3 */ -} - -static void rt_hw_i2c_pinmux_config_i2c4() -{ -#ifdef BSP_USING_I2C4 - - // SCL - #if defined(SOC_TYPE_CV180X) - #if defined(BSP_USING_PWR_WAKEUP0__IIC4_SCL) - PINMUX_CONFIG(PWR_WAKEUP0, IIC4_SCL); - #elif defined(BSP_USING_PAD_MIPIRX2N__IIC4_SCL) - PINMUX_CONFIG(PAD_MIPIRX2N, IIC4_SCL); - #endif - #endif // SOC_TYPE_CV180X - - #if defined(SOC_TYPE_SG2002) - #if defined(BSP_USING_CAM_RST0__IIC4_SCL) - PINMUX_CONFIG(CAM_RST0, IIC4_SCL); - #elif defined(BSP_USING_PWR_WAKEUP0__IIC4_SCL) - PINMUX_CONFIG(PWR_WAKEUP0, IIC4_SCL); - #elif defined(BSP_USING_PWR_WAKEUP1__IIC4_SCL) - PINMUX_CONFIG(PWR_WAKEUP1, IIC4_SCL); - #elif defined(BSP_USING_ADC3__IIC4_SCL) - PINMUX_CONFIG(ADC3, IIC4_SCL); - #elif defined(BSP_USING_VIVO_D1__IIC4_SCL) - PINMUX_CONFIG(VIVO_D1, IIC4_SCL); - #endif - #endif // SOC_TYPE_SG2002 - - // SDA - #if defined(SOC_TYPE_CV180X) - #if defined(BSP_USING_PWR_BUTTON1__IIC4_SDA) - PINMUX_CONFIG(PWR_BUTTON1, IIC4_SDA); - #elif defined(BSP_USING_PAD_MIPIRX2P__IIC4_SDA) - PINMUX_CONFIG(PAD_MIPIRX2P, IIC4_SDA); - #endif - #endif // SOC_TYPE_CV180X - - #if defined(SOC_TYPE_SG2002) - #if defined(BSP_USING_CAM_PD1__IIC4_SDA) - PINMUX_CONFIG(CAM_PD1, IIC4_SDA); - #elif defined(BSP_USING_PWR_BUTTON1__IIC4_SDA) - PINMUX_CONFIG(PWR_BUTTON1, IIC4_SDA); - #elif defined(BSP_USING_PWR_ON__IIC4_SDA) - PINMUX_CONFIG(PWR_ON, IIC4_SDA); - #elif defined(BSP_USING_ADC2__IIC4_SDA) - PINMUX_CONFIG(ADC2, IIC4_SDA); - #elif defined(BSP_USING_VIVO_D0__IIC4_SDA) - PINMUX_CONFIG(VIVO_D0, IIC4_SDA); - #elif defined(BSP_USING_PAD_MIPIRX2P__IIC4_SDA) - PINMUX_CONFIG(PAD_MIPIRX2P, IIC4_SDA); - #endif - #endif // SOC_TYPE_SG2002 - -#endif /* BSP_USING_I2C4 */ -} - -static void rt_hw_i2c_pinmux_config() -{ - rt_hw_i2c_pinmux_config_i2c0(); - rt_hw_i2c_pinmux_config_i2c1(); - rt_hw_i2c_pinmux_config_i2c2(); - rt_hw_i2c_pinmux_config_i2c3(); - rt_hw_i2c_pinmux_config_i2c4(); -} - int rt_hw_i2c_init(void) { int result = RT_EOK; - rt_hw_i2c_pinmux_config(); +#ifdef BSP_USING_I2C0 + PINMUX_CONFIG(IIC0_SCL, IIC0_SCL); + PINMUX_CONFIG(IIC0_SDA, IIC0_SDA); +#endif /* BSP_USING_I2C0 */ + +#ifdef BSP_USING_I2C1 + PINMUX_CONFIG(PAD_MIPIRX1P, IIC1_SDA); + PINMUX_CONFIG(PAD_MIPIRX0N, IIC1_SCL); +#endif /* BSP_USING_I2C1 */ for (rt_size_t i = 0; i < sizeof(_i2c_obj) / sizeof(struct _i2c_bus); i++) { From a63c07fd75ec9632e063646f043db3bfdad2aa49 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Tue, 28 May 2024 16:24:47 +0800 Subject: [PATCH 03/48] bsp: cvitek: new design for pinmux In the new design, we require the user to manually enter the PinName (as a string) in menuconfig instead of being given menu items to select. The original method will lead to too many menu item-related macros being defined in the code, causing ifdef and other codes scatter everywhere in the driver code, which is inconvenient to maintain. The new design adds a pinmux driver module to manage the multiplexing of pins. This patch provides this driver module. P.S., the reason why users are allowed to specify pinname in a string instead of the pin number is mainly because the technical manual provided by the SOC manufacturer does not have numbers for some pins, only names. Signed-off-by: Chen Wang Reviewed-by: Yuanjie He <943313837@qq.com> Reviewed-by: Shell --- bsp/cvitek/drivers/SConscript | 1 + bsp/cvitek/drivers/drv_pinmux.c | 544 ++++++++++++++++++++++++++++++++ bsp/cvitek/drivers/drv_pinmux.h | 448 ++++++++++++++++++++++++++ 3 files changed, 993 insertions(+) create mode 100644 bsp/cvitek/drivers/drv_pinmux.c create mode 100644 bsp/cvitek/drivers/drv_pinmux.h diff --git a/bsp/cvitek/drivers/SConscript b/bsp/cvitek/drivers/SConscript index 96be9b9aa9..d67ffc5e39 100755 --- a/bsp/cvitek/drivers/SConscript +++ b/bsp/cvitek/drivers/SConscript @@ -5,6 +5,7 @@ src = Split(''' drv_uart.c drv_por.c drv_gpio.c + drv_pinmux.c ''') CPPDEFINES = [] diff --git a/bsp/cvitek/drivers/drv_pinmux.c b/bsp/cvitek/drivers/drv_pinmux.c new file mode 100644 index 0000000000..17e7857944 --- /dev/null +++ b/bsp/cvitek/drivers/drv_pinmux.c @@ -0,0 +1,544 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024/05/24 unicornx first version + */ + +#include + +#include +#include "mmio.h" +#include "pinctrl.h" +#include "drv_pinmux.h" + +#define DBG_TAG "drv.pinmux" +#define DBG_LVL DBG_INFO +#include + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(ar) (sizeof(ar)/sizeof(ar[0])) +#endif + +/** + * @brief Function Selection for one Pin + * + * type: type of function + * select: value of selection + */ +struct fselect { + fs_type type; + uint8_t select; +}; + +/** + * @brief Function Mux for one Pin + * + * name: Pin Name + * addr: offset of pinmux registers against PINMUX_BASE + * offset: offset of function selection field in the pinmux register + * mask: mask of function selection field in the pinmux register + * selected: 1 if this pin has been selected, used for binding check. + */ +struct fmux { + char *name; + uint16_t addr; + uint8_t offset; + uint8_t mask; + uint8_t selected; +}; + +#define FS_NONE {fs_none, 0} + +#define FS_PINMUX(PIN_NAME) { \ + .name = #PIN_NAME, \ + .addr = FMUX_GPIO_FUNCSEL_##PIN_NAME, \ + .offset = PINMUX_OFFSET(PIN_NAME), \ + .mask = PINMUX_MASK(PIN_NAME), \ + .selected = 0, \ + } + + +/** + * @brief Define TWO tables for every SOC. + * + * Table-1: pinmux_array: every line maps to one pin register, store basic info. + * Table-2: pin_selects_array: function selection array, extend Table-1, store + * function selection info. + * NOTE: Index of pinmux_array matches the same as that in pin_selects_array. + */ +#if defined(SOC_TYPE_CV180X) + +struct fmux pinmux_array[] = { + FS_PINMUX(SD0_CLK), + FS_PINMUX(SD0_CMD), + FS_PINMUX(SD0_D0), + FS_PINMUX(SD0_D1), + FS_PINMUX(SD0_D2), + FS_PINMUX(SD0_D3), + FS_PINMUX(SD0_CD), + FS_PINMUX(SD0_PWR_EN), + FS_PINMUX(SPK_EN), + FS_PINMUX(UART0_TX), + FS_PINMUX(UART0_RX), + FS_PINMUX(SPINOR_HOLD_X), + FS_PINMUX(SPINOR_SCK), + FS_PINMUX(SPINOR_MOSI), + FS_PINMUX(SPINOR_WP_X), + FS_PINMUX(SPINOR_MISO), + FS_PINMUX(SPINOR_CS_X), + FS_PINMUX(JTAG_CPU_TMS), + FS_PINMUX(JTAG_CPU_TCK), + FS_PINMUX(IIC0_SCL), + FS_PINMUX(IIC0_SDA), + FS_PINMUX(AUX0), + FS_PINMUX(GPIO_ZQ), + FS_PINMUX(PWR_VBAT_DET), + FS_PINMUX(PWR_RSTN), + FS_PINMUX(PWR_SEQ1), + FS_PINMUX(PWR_SEQ2), + FS_PINMUX(PWR_WAKEUP0), + FS_PINMUX(PWR_BUTTON1), + FS_PINMUX(XTAL_XIN), + FS_PINMUX(PWR_GPIO0), + FS_PINMUX(PWR_GPIO1), + FS_PINMUX(PWR_GPIO2), + FS_PINMUX(SD1_GPIO1), + FS_PINMUX(SD1_GPIO0), + FS_PINMUX(SD1_D3), + FS_PINMUX(SD1_D2), + FS_PINMUX(SD1_D1), + FS_PINMUX(SD1_D0), + FS_PINMUX(SD1_CMD), + FS_PINMUX(SD1_CLK), + FS_PINMUX(PWM0_BUCK), + FS_PINMUX(ADC1), + FS_PINMUX(USB_VBUS_DET), + FS_PINMUX(MUX_SPI1_MISO), + FS_PINMUX(MUX_SPI1_MOSI), + FS_PINMUX(MUX_SPI1_CS), + FS_PINMUX(MUX_SPI1_SCK), + FS_PINMUX(PAD_ETH_TXP), + FS_PINMUX(PAD_ETH_TXM), + FS_PINMUX(PAD_ETH_RXP), + FS_PINMUX(PAD_ETH_RXM), + FS_PINMUX(GPIO_RTX), + FS_PINMUX(PAD_MIPIRX4N), + FS_PINMUX(PAD_MIPIRX4P), + FS_PINMUX(PAD_MIPIRX3N), + FS_PINMUX(PAD_MIPIRX3P), + FS_PINMUX(PAD_MIPIRX2N), + FS_PINMUX(PAD_MIPIRX2P), + FS_PINMUX(PAD_MIPIRX1N), + FS_PINMUX(PAD_MIPIRX1P), + FS_PINMUX(PAD_MIPIRX0N), + FS_PINMUX(PAD_MIPIRX0P), + FS_PINMUX(PAD_MIPI_TXM2), + FS_PINMUX(PAD_MIPI_TXP2), + FS_PINMUX(PAD_MIPI_TXM1), + FS_PINMUX(PAD_MIPI_TXP1), + FS_PINMUX(PAD_MIPI_TXM0), + FS_PINMUX(PAD_MIPI_TXP0), + FS_PINMUX(PKG_TYPE0), + FS_PINMUX(PKG_TYPE1), + FS_PINMUX(PKG_TYPE2), + FS_PINMUX(PAD_AUD_AINL_MIC), + FS_PINMUX(PAD_AUD_AINR_MIC), + FS_PINMUX(PAD_AUD_AOUTL), + FS_PINMUX(PAD_AUD_AOUTR), +}; + +const struct fselect pin_selects_array[][8] = { +/* SD0_CLK */ {{SDIO0_CLK, 0}, {IIC1_SDA, 1}, {SPI0_SCK, 2}, {XGPIOA_7, 3}, FS_NONE, {PWM_15, 5}, {EPHY_LNK_LED, 6}, {DBG_0, 7}}, +/* SD0_CMD */ {{SDIO0_CMD, 0}, {IIC1_SCL, 1}, {SPI0_SDO, 2}, {XGPIOA_8, 3}, FS_NONE, {PWM_14, 5}, {EPHY_SPD_LED, 6}, {DBG_1, 7}}, +/* SD0_D0 */ {{SDIO0_D_0, 0}, {CAM_MCLK1, 1}, {SPI0_SDI, 2}, {XGPIOA_9, 3}, {UART3_TX, 4}, {PWM_13, 5}, {WG0_D0, 6}, {DBG_2, 7}}, +/* SD0_D1 */ {{SDIO0_D_1, 0}, {IIC1_SDA, 1}, {AUX0, 2}, {XGPIOA_10, 3}, {UART1_TX, 4}, {PWM_12, 5}, {WG0_D1, 6}, {DBG_3, 7}}, +/* SD0_D2 */ {{SDIO0_D_2, 0}, {IIC1_SCL, 1}, {AUX1, 2}, {XGPIOA_11, 3}, {UART1_RX, 4}, {PWM_11, 5}, {WG1_D0, 6}, {DBG_4, 7}}, +/* SD0_D3 */ {{SDIO0_D_3, 0}, {CAM_MCLK0, 1}, {SPI0_CS_X, 2}, {XGPIOA_12, 3}, {UART3_RX, 4}, {PWM_10, 5}, {WG1_D1, 6}, {DBG_5, 7}}, +/* SD0_CD */ {{SDIO0_CD, 0}, FS_NONE, FS_NONE, {XGPIOA_13, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* SD0_PWR_EN */ {{SDIO0_PWR_EN, 0}, FS_NONE, FS_NONE, {XGPIOA_14, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* SPK_EN */ {FS_NONE, FS_NONE, FS_NONE, {XGPIOA_15, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* UART0_TX */ {{UART0_TX, 0}, {CAM_MCLK1, 1}, {PWM_4, 2}, {XGPIOA_16, 3}, {UART1_TX, 4}, {AUX1, 5}, {JTAG_TMS, 6}, {DBG_6, 7}}, +/* UART0_RX */ {{UART0_RX, 0}, {CAM_MCLK0, 1}, {PWM_5, 2}, {XGPIOA_17, 3}, {UART1_RX, 4}, {AUX0, 5}, {JTAG_TCK, 6}, {DBG_7, 7}}, +/* SPINOR_HOLD_X */ {FS_NONE, {SPINOR_HOLD_X, 1}, {SPINAND_HOLD, 2}, {XGPIOA_26, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* SPINOR_SCK */ {FS_NONE, {SPINOR_SCK, 1}, {SPINAND_CLK, 2}, {XGPIOA_22, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* SPINOR_MOSI */ {FS_NONE, {SPINOR_MOSI, 1}, {SPINAND_MOSI, 2}, {XGPIOA_25, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* SPINOR_WP_X */ {FS_NONE, {SPINOR_WP_X, 1}, {SPINAND_WP, 2}, {XGPIOA_27, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* SPINOR_MISO */ {FS_NONE, {SPINOR_MISO, 1}, {SPINAND_MISO, 2}, {XGPIOA_23, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* SPINOR_CS_X */ {FS_NONE, {SPINOR_CS_X, 1}, {SPINAND_CS, 2}, {XGPIOA_24, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* JTAG_CPU_TMS */ {{JTAG_TMS, 0}, {CAM_MCLK0, 1}, {PWM_7, 2}, {XGPIOA_19, 3}, {UART1_RTS, 4}, {AUX0, 5}, {UART1_TX, 6}, FS_NONE}, +/* JTAG_CPU_TCK */ {{JTAG_TCK, 0}, {CAM_MCLK1, 1}, {PWM_6, 2}, {XGPIOA_18, 3}, {UART1_CTS, 4}, {AUX1, 5}, {UART1_RX, 6}, FS_NONE}, +/* IIC0_SCL */ {{JTAG_TDI, 0}, {UART1_TX, 1}, {UART2_TX, 2}, {XGPIOA_28, 3}, {IIC0_SCL, 4}, {WG0_D0, 5}, FS_NONE, {DBG_10, 7}}, +/* IIC0_SDA */ {{JTAG_TDO, 0}, {UART1_RX, 1}, {UART2_RX, 2}, {XGPIOA_29, 3}, {IIC0_SDA, 4}, {WG0_D1, 5}, {WG1_D0, 6}, {DBG_11, 7}}, +/* AUX0 */ {{AUX0, 0}, FS_NONE, FS_NONE, {XGPIOA_30, 3}, {IIS1_MCLK, 4}, FS_NONE, {WG1_D1, 6}, {DBG_12, 7}}, +/* GPIO_ZQ */ {FS_NONE, FS_NONE, FS_NONE, {PWR_GPIO_24, 3}, {PWM_2, 4}, FS_NONE, FS_NONE, FS_NONE}, +/* PWR_VBAT_DET */ {{PWR_VBAT_DET, 0}, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* PWR_RSTN */ {{PWR_RSTN, 0}, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* PWR_SEQ1 */ {{PWR_SEQ1, 0}, FS_NONE, {PWR_GPIO_3, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* PWR_SEQ2 */ {{PWR_SEQ2, 0}, FS_NONE, {PWR_GPIO_4, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* PWR_WAKEUP0 */ {{PWR_WAKEUP0, 0}, {PWR_IR0, 1}, {PWR_UART0_TX, 2}, {PWR_GPIO_6, 3}, {UART1_TX, 4}, {IIC4_SCL, 5}, {EPHY_LNK_LED, 6}, {WG2_D0, 7}}, +/* PWR_BUTTON1 */ {{PWR_BUTTON1, 0}, FS_NONE, FS_NONE, {PWR_GPIO_8, 3}, {UART1_RX, 4}, {IIC4_SDA, 5}, {EPHY_SPD_LED, 6}, {WG2_D1, 7}}, +/* XTAL_XIN */ {{PWR_XTAL_CLKIN, 0}, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* PWR_GPIO0 */ {{PWR_GPIO_0, 0}, {UART2_TX, 1}, {PWR_UART0_RX, 2}, FS_NONE, {PWM_8, 4}, FS_NONE, FS_NONE, FS_NONE}, +/* PWR_GPIO1 */ {{PWR_GPIO_1, 0}, {UART2_RX, 1}, FS_NONE, {EPHY_LNK_LED, 3},{PWM_9, 4}, {PWR_IIC_SCL, 5}, {IIC2_SCL, 6}, {IIC0_SDA, 7}}, +/* PWR_GPIO2 */ {{PWR_GPIO_2, 0}, FS_NONE, {PWR_SECTICK, 2}, {EPHY_SPD_LED, 3},{PWM_10, 4}, {PWR_IIC_SDA, 5}, {IIC2_SDA, 6}, {IIC0_SCL, 7}}, +/* SD1_GPIO1 */ {FS_NONE, {UART4_TX, 1}, FS_NONE, {PWR_GPIO_26, 3}, FS_NONE, FS_NONE, FS_NONE, {PWM_10, 7}}, +/* SD1_GPIO0 */ {FS_NONE, {UART4_RX, 1}, FS_NONE, {PWR_GPIO_25, 3}, FS_NONE, FS_NONE, FS_NONE, {PWM_11, 7}}, +/* SD1_D3 */ {{PWR_SD1_D3, 0}, {SPI2_CS_X, 1}, {IIC1_SCL, 2}, {PWR_GPIO_18, 3}, {CAM_MCLK0, 4}, {UART3_CTS, 5}, {PWR_SPINOR1_CS_X, 6}, {PWM_4, 7}}, +/* SD1_D2 */ {{PWR_SD1_D2, 0}, {IIC1_SCL, 1}, {UART2_TX, 2}, {PWR_GPIO_19, 3}, {CAM_MCLK0, 4}, {UART3_TX, 5}, {PWR_SPINOR1_HOLD_X, 6},{PWM_5, 7}}, +/* SD1_D1 */ {{PWR_SD1_D1, 0}, {IIC1_SDA, 1}, {UART2_RX, 2}, {PWR_GPIO_20, 3}, {CAM_MCLK1, 4}, {UART3_RX, 5}, {PWR_SPINOR1_WP_X, 6}, {PWM_6, 7}}, +/* SD1_D0 */ {{PWR_SD1_D0, 0}, {SPI2_SDI, 1}, {IIC1_SDA, 2}, {PWR_GPIO_21, 3}, {CAM_MCLK1, 4}, {UART3_RTS, 5}, {PWR_SPINOR1_MISO, 6}, {PWM_7, 7}}, +/* SD1_CMD */ {{PWR_SD1_CMD, 0}, {SPI2_SDO, 1}, {IIC3_SCL, 2}, {PWR_GPIO_22, 3}, {CAM_VS0, 4}, {EPHY_LNK_LED, 5},{PWR_SPINOR1_MOSI, 6}, {PWM_8, 7}}, +/* SD1_CLK */ {{PWR_SD1_CLK, 0}, {SPI2_SCK, 1}, {IIC3_SDA, 2}, {PWR_GPIO_23, 3}, {CAM_HS0, 4}, {EPHY_SPD_LED, 5},{PWR_SPINOR1_SCK, 6}, {PWM_9, 7}}, +/* PWM0_BUCK */ {{PWM_0, 0}, FS_NONE, FS_NONE, {XGPIOB_0, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* ADC1 */ {FS_NONE, FS_NONE, FS_NONE, {XGPIOB_3, 3}, {KEY_COL2, 4}, FS_NONE, {PWM_3, 6}, FS_NONE}, +/* PKG_TYPE0 */ {{PKG_TYPE0, 0}, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* USB_VBUS_DET */ {{USB_VBUS_DET, 0}, FS_NONE, FS_NONE, {XGPIOB_6, 3}, {CAM_MCLK0, 4}, {CAM_MCLK1, 5}, {PWM_4, 6}, FS_NONE}, +/* PKG_TYPE1 */ {{PKG_TYPE1, 0}, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* PKG_TYPE2 */ {{PKG_TYPE2, 0}, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* MUX_SPI1_MISO */ {FS_NONE, {UART3_RTS, 1}, {IIC1_SDA, 2}, {XGPIOB_8, 3}, {PWM_9, 4}, {KEY_COL1, 5}, {SPI1_SDI, 6}, {DBG_14, 7}}, +/* MUX_SPI1_MOSI */ {FS_NONE, {UART3_RX, 1}, {IIC1_SCL, 2}, {XGPIOB_7, 3}, {PWM_8, 4}, {KEY_COL0, 5}, {SPI1_SDO, 6}, {DBG_13, 7}}, +/* MUX_SPI1_CS */ {FS_NONE, {UART3_CTS, 1}, {CAM_MCLK0, 2}, {XGPIOB_10, 3}, {PWM_11, 4}, {KEY_ROW3, 5}, {SPI1_CS_X, 6}, {DBG_16, 7}}, +/* MUX_SPI1_SCK */ {FS_NONE, {UART3_TX, 1}, {CAM_MCLK1, 2}, {XGPIOB_9, 3}, {PWM_10, 4}, {KEY_ROW2, 5}, {SPI1_SCK, 6}, {DBG_15, 7}}, +/* PAD_ETH_TXP */ {FS_NONE, {UART3_RX, 1}, {IIC1_SCL, 2}, {XGPIOB_25, 3}, {PWM_13, 4}, {CAM_MCLK0, 5}, {SPI1_SDO, 6}, {IIS2_LRCK, 7}}, +/* PAD_ETH_TXM */ {FS_NONE, {UART3_RTS, 1}, {IIC1_SDA, 2}, {XGPIOB_24, 3}, {PWM_12, 4}, {CAM_MCLK1, 5}, {SPI1_SDI, 6}, {IIS2_BCLK, 7}}, +/* PAD_ETH_RXP */ {FS_NONE, {UART3_TX, 1}, {CAM_MCLK1, 2}, {XGPIOB_27, 3}, {PWM_15, 4}, {CAM_HS0, 5}, {SPI1_SCK, 6}, {IIS2_DO, 7}}, +/* PAD_ETH_RXM */ {FS_NONE, {UART3_CTS, 1}, {CAM_MCLK0, 2}, {XGPIOB_26, 3}, {PWM_14, 4}, {CAM_VS0, 5}, {SPI1_CS_X, 6}, {IIS2_DI, 7}}, +/* GPIO_RTX */ {FS_NONE, {VI0_D_15, 1}, FS_NONE, {XGPIOB_23, 3}, {PWM_1, 4}, {CAM_MCLK0, 5}, FS_NONE, {IIS2_MCLK, 7}}, +/* PAD_MIPIRX4N */ {FS_NONE, {VI0_CLK, 1}, {IIC0_SCL, 2}, {XGPIOC_2, 3}, {IIC1_SDA, 4}, {CAM_MCLK0, 5}, {KEY_ROW0, 6}, {MUX_SPI1_SCK, 7}}, +/* PAD_MIPIRX4P */ {FS_NONE, {VI0_D_0, 1}, {IIC0_SDA, 2}, {XGPIOC_3, 3}, {IIC1_SCL, 4}, {CAM_MCLK1, 5}, {KEY_ROW1, 6}, {MUX_SPI1_CS, 7}}, +/* PAD_MIPIRX3N */ {FS_NONE, {VI0_D_1, 1}, FS_NONE, {XGPIOC_4, 3}, {CAM_MCLK0, 4}, FS_NONE, FS_NONE, {MUX_SPI1_MISO, 7}}, +/* PAD_MIPIRX3P */ {FS_NONE, {VI0_D_2, 1}, FS_NONE, {XGPIOC_5, 3}, FS_NONE, FS_NONE, FS_NONE, {MUX_SPI1_MOSI, 7}}, +/* PAD_MIPIRX2N */ {FS_NONE, {VI0_D_3, 1}, FS_NONE, {XGPIOC_6, 3}, FS_NONE, {IIC4_SCL, 5}, FS_NONE, {DBG_6, 7}}, +/* PAD_MIPIRX2P */ {FS_NONE, {VI0_D_4, 1}, FS_NONE, {XGPIOC_7, 3}, FS_NONE, {IIC4_SDA, 5}, FS_NONE, {DBG_7, 7}}, +/* PAD_MIPIRX1N */ {FS_NONE, {VI0_D_5, 1}, FS_NONE, {XGPIOC_8, 3}, FS_NONE, FS_NONE, {KEY_ROW3, 6}, {DBG_8, 7}}, +/* PAD_MIPIRX1P */ {FS_NONE, {VI0_D_6, 1}, FS_NONE, {XGPIOC_9, 3}, {IIC1_SDA, 4}, FS_NONE, {KEY_ROW2, 6}, {DBG_9, 7}}, +/* PAD_MIPIRX0N */ {FS_NONE, {VI0_D_7, 1}, FS_NONE, {XGPIOC_10, 3}, {IIC1_SCL, 4}, {CAM_MCLK1, 5}, FS_NONE, {DBG_10, 7}}, +/* PAD_MIPIRX0P */ {FS_NONE, {VI0_D_8, 1}, FS_NONE, {XGPIOC_11, 3}, {CAM_MCLK0, 4}, FS_NONE, FS_NONE, {DBG_11, 7}}, +/* PAD_MIPI_TXM2 */ {FS_NONE, {VI0_D_13, 1}, {IIC0_SDA, 2}, {XGPIOC_16, 3}, {IIC1_SDA, 4}, {PWM_8, 5}, {SPI0_SCK, 6}, FS_NONE}, +/* PAD_MIPI_TXP2 */ {FS_NONE, {VI0_D_14, 1}, {IIC0_SCL, 2}, {XGPIOC_17, 3}, {IIC1_SCL, 4}, {PWM_9, 5}, {SPI0_CS_X, 6}, {IIS1_MCLK, 7}}, +/* PAD_MIPI_TXM1 */ {{SPI3_SDO, 0}, {VI0_D_11, 1}, {IIS1_LRCK, 2}, {XGPIOC_14, 3}, {IIC2_SDA, 4}, {PWM_10, 5}, {SPI0_SDO, 6}, {DBG_14, 7}}, +/* PAD_MIPI_TXP1 */ {{SPI3_SDI, 0}, {VI0_D_12, 1}, {IIS1_DO, 2}, {XGPIOC_15, 3}, {IIC2_SCL, 4}, {PWM_11, 5}, {SPI0_SDI, 6}, {DBG_15, 7}}, +/* PAD_MIPI_TXM0 */ {{SPI3_SCK, 0}, {VI0_D_9, 1}, {IIS1_DI, 2}, {XGPIOC_12, 3}, {CAM_MCLK1, 4}, {PWM_14, 5}, {CAM_VS0, 6}, {DBG_12, 7}}, +/* PAD_MIPI_TXP0 */ {{SPI3_CS_X, 0}, {VI0_D_10, 1}, {IIS1_BCLK, 2}, {XGPIOC_13, 3}, {CAM_MCLK0, 4}, {PWM_15, 5}, {CAM_HS0, 6}, {DBG_13, 7}}, +/* PAD_AUD_AINL_MIC */ {FS_NONE, FS_NONE, FS_NONE, {XGPIOC_23, 3}, {IIS1_BCLK, 4}, {IIS2_BCLK, 5}, FS_NONE, FS_NONE}, +/* PAD_AUD_AINR_MIC */ {FS_NONE, FS_NONE, FS_NONE, {XGPIOC_22, 3}, {IIS1_DO, 4}, {IIS2_DI, 5}, {IIS1_DI, 6}, FS_NONE}, +/* PAD_AUD_AOUTL */ {FS_NONE, FS_NONE, FS_NONE, {XGPIOC_25, 3}, {IIS1_LRCK, 4}, {IIS2_LRCK, 5}, FS_NONE, FS_NONE}, +/* PAD_AUD_AOUTR */ {FS_NONE, FS_NONE, FS_NONE, {XGPIOC_24, 3}, {IIS1_DI, 4}, {IIS2_DO, 5}, {IIS1_DO, 6}, FS_NONE}, +}; + +#elif defined(SOC_TYPE_SG2002) + +struct fmux pinmux_array[] = { + FS_PINMUX(CAM_MCLK0), + FS_PINMUX(CAM_PD0), + FS_PINMUX(CAM_RST0), + FS_PINMUX(CAM_MCLK1), + FS_PINMUX(CAM_PD1), + FS_PINMUX(IIC3_SCL), + FS_PINMUX(IIC3_SDA), + FS_PINMUX(SD0_CLK), + FS_PINMUX(SD0_CMD), + FS_PINMUX(SD0_D0), + FS_PINMUX(SD0_D1), + FS_PINMUX(SD0_D2), + FS_PINMUX(SD0_D3), + FS_PINMUX(SD0_CD), + FS_PINMUX(SD0_PWR_EN), + FS_PINMUX(SPK_EN), + FS_PINMUX(UART0_TX), + FS_PINMUX(UART0_RX), + FS_PINMUX(EMMC_RSTN), + FS_PINMUX(EMMC_DAT2), + FS_PINMUX(EMMC_CLK), + FS_PINMUX(EMMC_DAT0), + FS_PINMUX(EMMC_DAT3), + FS_PINMUX(EMMC_CMD), + FS_PINMUX(EMMC_DAT1), + FS_PINMUX(JTAG_CPU_TMS), + FS_PINMUX(JTAG_CPU_TCK), + FS_PINMUX(JTAG_CPU_TRST), + FS_PINMUX(IIC0_SCL), + FS_PINMUX(IIC0_SDA), + FS_PINMUX(AUX0), + FS_PINMUX(PWR_VBAT_DET), + FS_PINMUX(PWR_RSTN), + FS_PINMUX(PWR_SEQ1), + FS_PINMUX(PWR_SEQ2), + FS_PINMUX(PWR_SEQ3), + FS_PINMUX(PWR_WAKEUP0), + FS_PINMUX(PWR_WAKEUP1), + FS_PINMUX(PWR_BUTTON1), + FS_PINMUX(PWR_ON), + FS_PINMUX(XTAL_XIN), + FS_PINMUX(PWR_GPIO0), + FS_PINMUX(PWR_GPIO1), + FS_PINMUX(PWR_GPIO2), + FS_PINMUX(CLK32K), + FS_PINMUX(CLK25M), + FS_PINMUX(IIC2_SCL), + FS_PINMUX(IIC2_SDA), + FS_PINMUX(UART2_TX), + FS_PINMUX(UART2_RTS), + FS_PINMUX(UART2_RX), + FS_PINMUX(UART2_CTS), + FS_PINMUX(SD1_D3), + FS_PINMUX(SD1_D2), + FS_PINMUX(SD1_D1), + FS_PINMUX(SD1_D0), + FS_PINMUX(SD1_CMD), + FS_PINMUX(SD1_CLK), + FS_PINMUX(RSTN), + FS_PINMUX(PWM0_BUCK), + FS_PINMUX(ADC3), + FS_PINMUX(ADC2), + FS_PINMUX(ADC1), + FS_PINMUX(USB_ID), + FS_PINMUX(USB_VBUS_EN), + FS_PINMUX(PKG_TYPE0), + FS_PINMUX(USB_VBUS_DET), + FS_PINMUX(PKG_TYPE1), + FS_PINMUX(PKG_TYPE2), + FS_PINMUX(MUX_SPI1_MISO), + FS_PINMUX(MUX_SPI1_MOSI), + FS_PINMUX(MUX_SPI1_CS), + FS_PINMUX(MUX_SPI1_SCK), + FS_PINMUX(PAD_ETH_TXM), + FS_PINMUX(PAD_ETH_TXP), + FS_PINMUX(PAD_ETH_RXM), + FS_PINMUX(PAD_ETH_RXP), + FS_PINMUX(VIVO_D10), + FS_PINMUX(VIVO_D9), + FS_PINMUX(VIVO_D8), + FS_PINMUX(VIVO_D7), + FS_PINMUX(VIVO_D6), + FS_PINMUX(VIVO_D5), + FS_PINMUX(VIVO_D4), + FS_PINMUX(VIVO_D3), + FS_PINMUX(VIVO_D2), + FS_PINMUX(VIVO_D1), + FS_PINMUX(VIVO_D0), + FS_PINMUX(VIVO_CLK), + FS_PINMUX(PAD_MIPIRX5N), + FS_PINMUX(PAD_MIPIRX5P), + FS_PINMUX(PAD_MIPIRX4N), + FS_PINMUX(PAD_MIPIRX4P), + FS_PINMUX(PAD_MIPIRX3N), + FS_PINMUX(PAD_MIPIRX3P), + FS_PINMUX(PAD_MIPIRX2N), + FS_PINMUX(PAD_MIPIRX2P), + FS_PINMUX(PAD_MIPIRX1N), + FS_PINMUX(PAD_MIPIRX1P), + FS_PINMUX(PAD_MIPIRX0N), + FS_PINMUX(PAD_MIPIRX0P), + FS_PINMUX(PAD_MIPI_TXM4), + FS_PINMUX(PAD_MIPI_TXP4), + FS_PINMUX(PAD_MIPI_TXM3), + FS_PINMUX(PAD_MIPI_TXP3), + FS_PINMUX(PAD_MIPI_TXM2), + FS_PINMUX(PAD_MIPI_TXP2), + FS_PINMUX(PAD_MIPI_TXM1), + FS_PINMUX(PAD_MIPI_TXP1), + FS_PINMUX(PAD_MIPI_TXM0), + FS_PINMUX(PAD_MIPI_TXP0), + FS_PINMUX(PAD_AUD_AINL_MIC), + FS_PINMUX(PAD_AUD_AINR_MIC), + FS_PINMUX(PAD_AUD_AOUTL), + FS_PINMUX(PAD_AUD_AOUTR), + FS_PINMUX(GPIO_RTX), + FS_PINMUX(GPIO_ZQ), +}; + +const struct fselect pin_selects_array[][8] = { +/* CAM_MCLK0 */ {{CAM_MCLK0, 0}, FS_NONE, {AUX1, 2}, {XGPIOA_0, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* CAM_PD0 */ {FS_NONE, {IIS1_MCLK, 1}, FS_NONE, {XGPIOA_1, 3}, {CAM_HS0, 4}, FS_NONE, FS_NONE, FS_NONE}, +/* CAM_RST0 */ {FS_NONE, FS_NONE, FS_NONE, {XGPIOA_2, 3}, {CAM_VS0, 4}, FS_NONE, {IIC4_SCL, 6}, FS_NONE}, +/* CAM_MCLK1 */ {{CAM_MCLK1, 0}, FS_NONE, {AUX2, 2}, {XGPIOA_3, 3}, {CAM_HS0, 4}, FS_NONE, FS_NONE, FS_NONE}, +/* CAM_PD1 */ {FS_NONE, {IIS1_MCLK, 1}, FS_NONE, {XGPIOA_4, 3}, {CAM_VS0, 4}, FS_NONE, {IIC4_SDA, 6}, FS_NONE}, +/* IIC3_SCL */ {{IIC3_SCL, 0}, FS_NONE, FS_NONE, {XGPIOA_5, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* IIC3_SDA */ {{IIC3_SDA, 0}, FS_NONE, FS_NONE, {XGPIOA_6, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* SD0_CLK */ {{SDIO0_CLK, 0}, {IIC1_SDA, 1}, {SPI0_SCK, 2}, {XGPIOA_7, 3}, FS_NONE, {PWM_15, 5}, {EPHY_LNK_LED, 6}, {DBG_0, 7}}, +/* SD0_CMD */ {{SDIO0_CMD, 0}, {IIC1_SCL, 1}, {SPI0_SDO, 2}, {XGPIOA_8, 3}, FS_NONE, {PWM_14, 5}, {EPHY_SPD_LED, 6}, {DBG_1, 7}}, +/* SD0_D0 */ {{SDIO0_D_0, 0}, {CAM_MCLK1, 1}, {SPI0_SDI, 2}, {XGPIOA_9, 3}, {UART3_TX, 4}, {PWM_13, 5}, {WG0_D0, 6}, {DBG_2, 7}}, +/* SD0_D1 */ {{SDIO0_D_1, 0}, {IIC1_SDA, 1}, {AUX0, 2}, {XGPIOA_10, 3}, {UART1_TX, 4}, {PWM_12, 5}, {WG0_D1, 6}, {DBG_3, 7}}, +/* SD0_D2 */ {{SDIO0_D_2, 0}, {IIC1_SCL, 1}, {AUX1, 2}, {XGPIOA_11, 3}, {UART1_RX, 4}, {PWM_11, 5}, {WG1_D0, 6}, {DBG_4, 7}}, +/* SD0_D3 */ {{SDIO0_D_3, 0}, {CAM_MCLK0, 1}, {SPI0_CS_X, 2}, {XGPIOA_12, 3}, {UART3_RX, 4}, {PWM_10, 5}, {WG1_D1, 6}, {DBG_5, 7}}, +/* SD0_CD */ {{SDIO0_CD, 0}, FS_NONE, FS_NONE, {XGPIOA_13, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* SD0_PWR_EN */ {{SDIO0_PWR_EN, 0}, FS_NONE, FS_NONE, {XGPIOA_14, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* SPK_EN */ {FS_NONE, FS_NONE, FS_NONE, {XGPIOA_15, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* UART0_TX */ {{UART0_TX, 0}, {CAM_MCLK1, 1}, {PWM_4, 2}, {XGPIOA_16, 3}, {UART1_TX, 4}, {AUX1, 5}, {JTAG_TMS, 6}, {DBG_6, 7}}, +/* UART0_RX */ {{UART0_RX, 0}, {CAM_MCLK0, 1}, {PWM_5, 2}, {XGPIOA_17, 3}, {UART1_RX, 4}, {AUX0, 5}, FS_NONE, {DBG_7, 7}}, +/* EMMC_RSTN */ {{EMMC_RSTN, 0}, FS_NONE, FS_NONE, {XGPIOA_21, 3}, {AUX2, 4}, FS_NONE, FS_NONE, FS_NONE}, +/* EMMC_DAT2 */ {{EMMC_DAT_2, 0}, {SPINOR_HOLD_X, 1}, {SPINAND_HOLD, 2}, {XGPIOA_26, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* EMMC_CLK */ {{EMMC_CLK, 0}, {SPINOR_SCK, 1}, {SPINAND_CLK, 2}, {XGPIOA_22, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* EMMC_DAT0 */ {{EMMC_DAT_0, 0}, {SPINOR_MOSI, 1}, {SPINAND_MOSI, 2}, {XGPIOA_25, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* EMMC_DAT3 */ {{EMMC_DAT_3, 0}, {SPINOR_WP_X, 1}, {SPINAND_WP, 2}, {XGPIOA_27, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* EMMC_CMD */ {{EMMC_CMD, 0}, {SPINOR_MISO, 1}, {SPINAND_MISO, 2}, {XGPIOA_23, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* EMMC_DAT1 */ {{EMMC_DAT_1, 0}, {SPINOR_CS_X, 1}, {SPINAND_CS, 2}, {XGPIOA_24, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* JTAG_CPU_TMS */ {{JTAG_CPU_TMS, 0}, {CAM_MCLK0, 1}, {PWM_7, 2}, {XGPIOA_19, 3}, {UART1_RTS, 4}, {AUX0, 5}, {UART1_TX, 6}, {VO_D_28, 7}}, +/* JTAG_CPU_TCK */ {{JTAG_CPU_TCK, 0}, {CAM_MCLK1, 1}, {PWM_6, 2}, {XGPIOA_18, 3}, {UART1_CTS, 4}, {AUX1, 5}, {UART1_RX, 6}, {VO_D_29, 7}}, +/* JTAG_CPU_TRST */ {{JTAG_CPU_TRST, 0}, FS_NONE, FS_NONE, {XGPIOA_20, 3}, FS_NONE, FS_NONE, {VO_D_30, 6}, FS_NONE}, +/* IIC0_SCL */ {{IIC0_SCL, 0}, {UART1_TX, 1}, {UART2_TX, 2}, {XGPIOA_28, 3}, FS_NONE, {WG0_D0, 5}, FS_NONE, {DBG_10, 7}}, +/* IIC0_SDA */ {{IIC0_SDA, 0}, {UART1_RX, 1}, {UART2_RX, 2}, {XGPIOA_29, 3}, FS_NONE, {WG0_D1, 5}, {WG1_D0, 6}, {DBG_11, 7}}, +/* AUX0 */ {{AUX0, 0}, FS_NONE, FS_NONE, {XGPIOA_30, 3}, {IIS1_MCLK, 4}, {VO_D_31, 5}, {WG1_D1, 6}, {DBG_12, 7}}, +/* PWR_VBAT_DET */ {{PWR_VBAT_DET, 0}, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* PWR_RSTN */ {{PWR_RSTN, 0}, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* PWR_SEQ1 */ {{PWR_SEQ1, 0}, FS_NONE, {PWR_GPIO_3, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* PWR_SEQ2 */ {{PWR_SEQ2, 0}, FS_NONE, {PWR_GPIO_4, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* PWR_SEQ3 */ {{PWR_SEQ3, 0}, FS_NONE, {PWR_GPIO_5, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* PWR_WAKEUP0 */ {{PWR_WAKEUP0, 0}, {PWR_IR0, 1}, {PWR_UART0_TX, 2}, {PWR_GPIO_6, 3}, {UART1_TX, 4}, {IIC4_SCL, 5}, {EPHY_LNK_LED, 6}, {WG2_D0, 7}}, +/* PWR_WAKEUP1 */ {{PWR_WAKEUP1, 0}, {PWR_IR1, 1}, FS_NONE, {PWR_GPIO_7, 3}, {UART1_TX, 4}, {IIC4_SCL, 5}, {EPHY_LNK_LED, 6}, {WG0_D0, 7}}, +/* PWR_BUTTON1 */ {{PWR_BUTTON1, 0}, FS_NONE, FS_NONE, {PWR_GPIO_8, 3}, {UART1_RX, 4}, {IIC4_SDA, 5}, {EPHY_SPD_LED, 6}, {WG2_D1, 7}}, +/* PWR_ON */ {{PWR_ON, 0}, FS_NONE, FS_NONE, {PWR_GPIO_9, 3}, {UART1_RX, 4}, {IIC4_SDA, 5}, {EPHY_SPD_LED, 6}, {WG0_D1, 7}}, +/* XTAL_XIN */ {{PWR_XTAL_CLKIN, 0}, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* PWR_GPIO0 */ {{PWR_GPIO_0, 0}, {UART2_TX, 1}, {PWR_UART0_RX, 2}, FS_NONE, {PWM_8, 4}, FS_NONE, FS_NONE, FS_NONE}, +/* PWR_GPIO1 */ {{PWR_GPIO_1, 0}, {UART2_RX, 1}, FS_NONE, {EPHY_LNK_LED, 3}, {PWM_9, 4}, {PWR_IIC_SCL, 5}, {IIC2_SCL, 6}, {PWR_MCU_JTAG_TMS, 7}}, +/* PWR_GPIO2 */ {{PWR_GPIO_2, 0}, FS_NONE, {PWR_SECTICK, 2}, {EPHY_SPD_LED, 3}, {PWM_10, 4}, {PWR_IIC_SDA, 5}, {IIC2_SDA, 6}, {PWR_MCU_JTAG_TCK, 7}}, +/* CLK32K */ {{CLK32K, 0}, {AUX0, 1}, {PWR_MCU_JTAG_TDI, 2}, {PWR_GPIO_10, 3}, {PWM_2, 4}, {KEY_COL0, 5}, {CAM_MCLK0, 6}, {DBG_0, 7}}, +/* CLK25M */ {{CLK25M, 0}, {AUX1, 1}, {PWR_MCU_JTAG_TDO, 2}, {PWR_GPIO_11, 3}, {PWM_3, 4}, {KEY_COL1, 5}, {CAM_MCLK1, 6}, {DBG_1, 7}}, +/* IIC2_SCL */ {{IIC2_SCL, 0}, {PWM_14, 1}, FS_NONE, {PWR_GPIO_12, 3}, {UART2_RX, 4}, FS_NONE, FS_NONE, {KEY_COL2, 7}}, +/* IIC2_SDA */ {{IIC2_SDA, 0}, {PWM_15, 1}, FS_NONE, {PWR_GPIO_13, 3}, {UART2_TX, 4}, {IIS1_MCLK, 5}, {IIS2_MCLK, 6}, {KEY_COL3, 7}}, +/* UART2_TX */ {{UART2_TX, 0}, {PWM_11, 1}, {PWR_UART1_TX, 2}, {PWR_GPIO_14, 3}, {KEY_ROW3, 4}, {UART4_TX, 5}, {IIS2_BCLK, 6}, {WG2_D0, 7}}, +/* UART2_RTS */ {{UART2_RTS, 0}, {PWM_8, 1}, FS_NONE, {PWR_GPIO_15, 3}, {KEY_ROW0, 4}, {UART4_RTS, 5}, {IIS2_DO, 6}, {WG1_D0, 7}}, +/* UART2_RX */ {{UART2_RX, 0}, {PWM_10, 1}, {PWR_UART1_RX, 2}, {PWR_GPIO_16, 3}, {KEY_COL3, 4}, {UART4_RX, 5}, {IIS2_DI, 6}, {WG2_D1, 7}}, +/* UART2_CTS */ {{UART2_CTS, 0}, {PWM_9, 1}, FS_NONE, {PWR_GPIO_17, 3}, {KEY_ROW1, 4}, {UART4_CTS, 5}, {IIS2_LRCK, 6}, {WG1_D1, 7}}, +/* SD1_D3 */ {{PWR_SD1_D3_VO32, 0}, {SPI2_CS_X, 1}, {IIC1_SCL, 2}, {PWR_GPIO_18, 3}, {CAM_MCLK0, 4}, {UART3_CTS, 5}, {PWR_SPINOR1_CS_X, 6}, {PWM_4, 7}}, +/* SD1_D2 */ {{PWR_SD1_D2_VO33, 0}, {IIC1_SCL, 1}, {UART2_TX, 2}, {PWR_GPIO_19, 3}, {CAM_MCLK0, 4}, {UART3_TX, 5}, {PWR_SPINOR1_HOLD_X, 6},{PWM_5, 7}}, +/* SD1_D1 */ {{PWR_SD1_D1_VO34, 0}, {IIC1_SDA, 1}, {UART2_RX, 2}, {PWR_GPIO_20, 3}, {CAM_MCLK1, 4}, {UART3_RX, 5}, {PWR_SPINOR1_WP_X, 6}, {PWM_6, 7}}, +/* SD1_D0 */ {{PWR_SD1_D0_VO35, 0}, {SPI2_SDI, 1}, {IIC1_SDA, 2}, {PWR_GPIO_21, 3}, {CAM_MCLK1, 4}, {UART3_RTS, 5}, {PWR_SPINOR1_MISO, 6}, {PWM_7, 7}}, +/* SD1_CMD */ {{PWR_SD1_CMD_VO36, 0}, {SPI2_SDO, 1}, {IIC3_SCL, 2}, {PWR_GPIO_22, 3}, {CAM_VS0, 4}, {EPHY_LNK_LED, 5}, {PWR_SPINOR1_MOSI, 6}, {PWM_8, 7}}, +/* SD1_CLK */ {{PWR_SD1_CLK_VO37, 0}, {SPI2_SCK, 1}, {IIC3_SDA, 2}, {PWR_GPIO_23, 3}, {CAM_HS0, 4}, {EPHY_SPD_LED, 5}, {PWR_SPINOR1_SCK, 6}, {PWM_9, 7}}, +/* RSTN */ {{RSTN, 0}, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* PWM0_BUCK */ {{PWM_0, 0}, FS_NONE, FS_NONE, {XGPIOB_0, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* ADC3 */ {FS_NONE, {CAM_MCLK0, 1}, {IIC4_SCL, 2}, {XGPIOB_1, 3}, {PWM_12, 4}, {EPHY_LNK_LED, 5}, {WG2_D0, 6}, {UART3_TX, 7}}, +/* ADC2 */ {FS_NONE, {CAM_MCLK1, 1}, {IIC4_SDA, 2}, {XGPIOB_2, 3}, {PWM_13, 4}, {EPHY_SPD_LED, 5}, {WG2_D1, 6}, {UART3_RX, 7}}, +/* ADC1 */ {FS_NONE, FS_NONE, FS_NONE, {XGPIOB_3, 3}, {KEY_COL2, 4}, FS_NONE, {PWM_3, 6}, FS_NONE}, +/* USB_ID */ {{USB_ID, 0}, FS_NONE, FS_NONE, {XGPIOB_4, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* USB_VBUS_EN */ {{USB_VBUS_EN, 0}, FS_NONE, FS_NONE, {XGPIOB_5, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* PKG_TYPE0 */ {{PKG_TYPE0, 0}, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* USB_VBUS_DET */ {{USB_VBUS_DET, 0}, FS_NONE, FS_NONE, {XGPIOB_6, 3}, {CAM_MCLK0, 4}, {CAM_MCLK1, 5}, FS_NONE, FS_NONE}, +/* PKG_TYPE1 */ {{PKG_TYPE1, 0}, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* PKG_TYPE2 */ {{PKG_TYPE2, 0}, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* MUX_SPI1_MISO */ {FS_NONE, {UART3_RTS, 1}, {IIC1_SDA, 2}, {XGPIOB_8, 3}, {PWM_9, 4}, {KEY_COL1, 5}, {SPI1_SDI, 6}, {DBG_14, 7}}, +/* MUX_SPI1_MOSI */ {FS_NONE, {UART3_RX, 1}, {IIC1_SCL, 2}, {XGPIOB_7, 3}, {PWM_8, 4}, {KEY_COL0, 5}, {SPI1_SDO, 6}, {DBG_13, 7}}, +/* MUX_SPI1_CS */ {FS_NONE, {UART3_CTS, 1}, {CAM_MCLK0, 2}, {XGPIOB_10, 3}, {PWM_11, 4}, {KEY_ROW3, 5}, {SPI1_CS_X, 6}, {DBG_16, 7}}, +/* MUX_SPI1_SCK */ {FS_NONE, {UART3_TX, 1}, {CAM_MCLK1, 2}, {XGPIOB_9, 3}, {PWM_10, 4}, {KEY_ROW2, 5}, {SPI1_SCK, 6}, {DBG_15, 7}}, +/* PAD_ETH_TXM */ {FS_NONE, {UART3_RTS, 1}, {IIC1_SDA, 2}, {XGPIOB_24, 3}, {PWM_12, 4}, {CAM_MCLK1, 5}, {SPI1_SDI, 6}, {IIS2_BCLK, 7}}, +/* PAD_ETH_TXP */ {FS_NONE, {UART3_RX, 1}, {IIC1_SCL, 2}, {XGPIOB_25, 3}, {PWM_13, 4}, {CAM_MCLK0, 5}, {SPI1_SDO, 6}, {IIS2_LRCK, 7}}, +/* PAD_ETH_RXM */ {FS_NONE, {UART3_CTS, 1}, {CAM_MCLK0, 2}, {XGPIOB_26, 3}, {PWM_14, 4}, {CAM_VS0, 5}, {SPI1_CS_X, 6}, {IIS2_DI, 7}}, +/* PAD_ETH_RXP */ {FS_NONE, {UART3_TX, 1}, {CAM_MCLK1, 2}, {XGPIOB_27, 3}, {PWM_15, 4}, {CAM_HS0, 5}, {SPI1_SCK, 6}, {IIS2_DO, 7}}, +/* VIVO_D10 */ {{PWM_1, 0}, {VI1_D_10, 1}, {VO_D_23, 2}, {XGPIOB_11, 3}, {RMII0_IRQ, 4}, {CAM_MCLK0, 5}, {IIC1_SDA, 6}, {UART2_TX, 7}}, +/* VIVO_D9 */ {{PWM_2, 0}, {VI1_D_9, 1}, {VO_D_22, 2}, {XGPIOB_12, 3}, FS_NONE, {CAM_MCLK1, 5}, {IIC1_SCL, 6}, {UART2_RX, 7}}, +/* VIVO_D8 */ {{PWM_3, 0}, {VI1_D_8, 1}, {VO_D_21, 2}, {XGPIOB_13, 3}, {RMII0_MDIO, 4}, {SPI3_SDO, 5}, {IIC2_SCL, 6}, {CAM_VS0, 7}}, +/* VIVO_D7 */ {{VI2_D_7, 0}, {VI1_D_7, 1}, {VO_D_20, 2}, {XGPIOB_14, 3}, {RMII0_RXD1, 4}, {SPI3_SDI, 5}, {IIC2_SDA, 6}, {CAM_HS0, 7}}, +/* VIVO_D6 */ {{VI2_D_6, 0}, {VI1_D_6, 1}, {VO_D_19, 2}, {XGPIOB_15, 3}, {RMII0_REFCLKI, 4},{SPI3_SCK, 5}, {UART2_TX, 6}, {CAM_VS0, 7}}, +/* VIVO_D5 */ {{VI2_D_5, 0}, {VI1_D_5, 1}, {VO_D_18, 2}, {XGPIOB_16, 3}, {RMII0_RXD0, 4}, {SPI3_CS_X, 5}, {UART2_RX, 6}, {CAM_HS0, 7}}, +/* VIVO_D4 */ {{VI2_D_4, 0}, {VI1_D_4, 1}, {VO_D_17, 2}, {XGPIOB_17, 3}, {RMII0_MDC, 4}, {IIC1_SDA, 5}, {UART2_CTS, 6}, {CAM_VS0, 7}}, +/* VIVO_D3 */ {{VI2_D_3, 0}, {VI1_D_3, 1}, {VO_D_16, 2}, {XGPIOB_18, 3}, {RMII0_TXD0, 4}, {IIC1_SCL, 5}, {UART2_RTS, 6}, {CAM_HS0, 7}}, +/* VIVO_D2 */ {{VI2_D_2, 0}, {VI1_D_2, 1}, {VO_D_15, 2}, {XGPIOB_19, 3}, {RMII0_TXD1, 4}, {CAM_MCLK1, 5}, {PWM_2, 6}, {UART2_TX, 7}}, +/* VIVO_D1 */ {{VI2_D_1, 0}, {VI1_D_1, 1}, {VO_D_14, 2}, {XGPIOB_20, 3}, {RMII0_RXDV, 4}, {IIC3_SDA, 5}, {PWM_3, 6}, {IIC4_SCL, 7}}, +/* VIVO_D0 */ {{VI2_D_0, 0}, {VI1_D_0, 1}, {VO_D_13, 2}, {XGPIOB_21, 3}, {RMII0_TXCLK, 4}, {IIC3_SCL, 5}, {WG1_D0, 6}, {IIC4_SDA, 7}}, +/* VIVO_CLK */ {{VI2_CLK, 0}, {VI1_CLK, 1}, {VO_CLK1, 2}, {XGPIOB_22, 3}, {RMII0_TXEN, 4}, {CAM_MCLK0, 5}, {WG1_D1, 6}, {UART2_RX, 7}}, +/* PAD_MIPIRX5N */ {FS_NONE, {VI1_D_11, 1}, {VO_D_12, 2}, {XGPIOC_0, 3}, FS_NONE, {CAM_MCLK0, 5}, {WG0_D0, 6}, {DBG_0, 7}}, +/* PAD_MIPIRX5P */ {FS_NONE, {VI1_D_12, 1}, {VO_D_11, 2}, {XGPIOC_1, 3}, {IIS1_MCLK, 4}, {CAM_MCLK1, 5}, {WG0_D1, 6}, {DBG_1, 7}}, +/* PAD_MIPIRX4N */ {FS_NONE, {VI0_CLK, 1}, {VI1_D_13, 2}, {XGPIOC_2, 3}, {IIC1_SDA, 4}, {CAM_MCLK0, 5}, {KEY_ROW0, 6}, {MUX_SPI1_SCK, 7}}, +/* PAD_MIPIRX4P */ {FS_NONE, {VI0_D_0, 1}, {VI1_D_14, 2}, {XGPIOC_3, 3}, {IIC1_SCL, 4}, {CAM_MCLK1, 5}, {KEY_ROW1, 6}, {MUX_SPI1_CS, 7}}, +/* PAD_MIPIRX3N */ {FS_NONE, {VI0_D_1, 1}, {VI1_D_15, 2}, {XGPIOC_4, 3}, {CAM_MCLK0, 4}, FS_NONE, FS_NONE, {MUX_SPI1_MISO, 7}}, +/* PAD_MIPIRX3P */ {FS_NONE, {VI0_D_2, 1}, {VI1_D_16, 2}, {XGPIOC_5, 3}, FS_NONE, FS_NONE, FS_NONE, {MUX_SPI1_MOSI, 7}}, +/* PAD_MIPIRX2N */ {FS_NONE, {VI0_D_3, 1}, {VO_D_10, 2}, {XGPIOC_6, 3}, {VI1_D_17, 4}, {IIC4_SCL, 5}, FS_NONE, {DBG_6, 7}}, +/* PAD_MIPIRX2P */ {FS_NONE, {VI0_D_4, 1}, {VO_D_9, 2}, {XGPIOC_7, 3}, {VI1_D_18, 4}, {IIC4_SDA, 5}, FS_NONE, {DBG_7, 7}}, +/* PAD_MIPIRX1N */ {FS_NONE, {VI0_D_5, 1}, {VO_D_8, 2}, {XGPIOC_8, 3}, FS_NONE, FS_NONE, {KEY_ROW3, 6}, {DBG_8, 7}}, +/* PAD_MIPIRX1P */ {FS_NONE, {VI0_D_6, 1}, {VO_D_7, 2}, {XGPIOC_9, 3}, {IIC1_SDA, 4}, FS_NONE, {KEY_ROW2, 6}, {DBG_9, 7}}, +/* PAD_MIPIRX0N */ {FS_NONE, {VI0_D_7, 1}, {VO_D_6, 2}, {XGPIOC_10, 3}, {IIC1_SCL, 4}, {CAM_MCLK1, 5}, FS_NONE, {DBG_10, 7}}, +/* PAD_MIPIRX0P */ {FS_NONE, {VI0_D_8, 1}, {VO_D_5, 2}, {XGPIOC_11, 3}, {CAM_MCLK0, 4}, FS_NONE, FS_NONE, {DBG_11, 7}}, +/* PAD_MIPI_TXM4 */ {FS_NONE, {SD1_CLK, 1}, {VO_D_24, 2}, {XGPIOC_18, 3}, {CAM_MCLK1, 4}, {PWM_12, 5}, {IIC1_SDA, 6}, {DBG_18, 7}}, +/* PAD_MIPI_TXP4 */ {FS_NONE, {SD1_CMD, 1}, {VO_D_25, 2}, {XGPIOC_19, 3}, {CAM_MCLK0, 4}, {PWM_13, 5}, {IIC1_SCL, 6}, {DBG_19, 7}}, +/* PAD_MIPI_TXM3 */ {FS_NONE, {SD1_D0, 1}, {VO_D_26, 2}, {XGPIOC_20, 3}, {IIC2_SDA, 4}, {PWM_14, 5}, {IIC1_SDA, 6}, {CAM_VS0, 7}}, +/* PAD_MIPI_TXP3 */ {FS_NONE, {SD1_D1, 1}, {VO_D_27, 2}, {XGPIOC_21, 3}, {IIC2_SCL, 4}, {PWM_15, 5}, {IIC1_SCL, 6}, {CAM_HS0, 7}}, +/* PAD_MIPI_TXM2 */ {FS_NONE, {VI0_D_13, 1}, {VO_D_0, 2}, {XGPIOC_16, 3}, {IIC1_SDA, 4}, {PWM_8, 5}, {SPI0_SCK, 6}, {SD1_D2, 7}}, +/* PAD_MIPI_TXP2 */ {FS_NONE, {VI0_D_14, 1}, {VO_CLK0, 2}, {XGPIOC_17, 3}, {IIC1_SCL, 4}, {PWM_9, 5}, {SPI0_CS_X, 6}, {SD1_D3, 7}}, +/* PAD_MIPI_TXM1 */ {FS_NONE, {VI0_D_11, 1}, {VO_D_2, 2}, {XGPIOC_14, 3}, {IIC2_SDA, 4}, {PWM_10, 5}, {SPI0_SDO, 6}, {DBG_14, 7}}, +/* PAD_MIPI_TXP1 */ {FS_NONE, {VI0_D_12, 1}, {VO_D_1, 2}, {XGPIOC_15, 3}, {IIC2_SCL, 4}, {PWM_11, 5}, {SPI0_SDI, 6}, {DBG_15, 7}}, +/* PAD_MIPI_TXM0 */ {FS_NONE, {VI0_D_9, 1}, {VO_D_4, 2}, {XGPIOC_12, 3}, {CAM_MCLK1, 4}, {PWM_14, 5}, {CAM_VS0, 6}, {DBG_12, 7}}, +/* PAD_MIPI_TXP0 */ {FS_NONE, {VI0_D_10, 1}, {VO_D_3, 2}, {XGPIOC_13, 3}, {CAM_MCLK0, 4}, {PWM_15, 5}, {CAM_HS0, 6}, {DBG_13, 7}}, +/* PAD_AUD_AINL_MIC */ {FS_NONE, FS_NONE, FS_NONE, {XGPIOC_23, 3}, {IIS1_BCLK, 4}, {IIS2_BCLK, 5}, FS_NONE, FS_NONE}, +/* PAD_AUD_AINR_MIC */ {FS_NONE, FS_NONE, FS_NONE, {XGPIOC_22, 3}, {IIS1_DO, 4}, {IIS2_DI, 5}, {IIS1_DI, 6}, FS_NONE}, +/* PAD_AUD_AOUTL */ {FS_NONE, FS_NONE, FS_NONE, {XGPIOC_25, 3}, {IIS1_LRCK, 4}, {IIS2_LRCK, 5}, FS_NONE, FS_NONE}, +/* PAD_AUD_AOUTR */ {FS_NONE, FS_NONE, FS_NONE, {XGPIOC_24, 3}, {IIS1_DI, 4}, {IIS2_DO, 5}, {IIS1_DO, 6}, FS_NONE}, +/* GPIO_RTX */ {FS_NONE, FS_NONE, FS_NONE, {XGPIOB_23, 3}, {PWM_1, 4}, {CAM_MCLK0, 5}, FS_NONE, FS_NONE}, +/* GPIO_ZQ */ {FS_NONE, FS_NONE, FS_NONE, {PWR_GPIO_24, 3}, {PWM_2, 4}, FS_NONE, FS_NONE, FS_NONE}, +}; + +#else + +#error "Unsupported SOC type!" + +#endif + +static int8_t pinmux_get_index(uint8_t pin_index, fs_type func_type) +{ + const struct fselect *p; + for (int i = 0; i < 8; i++) { + p = &(pin_selects_array[pin_index][i]); + LOG_D("[%d], type = %d, select = %d\n", i, p->type, p->select); + if (p->type == func_type) + return (int8_t)p->select; // it's safe bcos select should be [0, 7] + } + return -1; +} + +static int pinmux_check_whitelist(const char *pin_name, const char *whitelist[]) +{ + const char **name = &whitelist[0]; + while (*name) { + if (0 == strcmp(pin_name, *name)) + return 0; + name++; + } + return -1; +} + +int pinmux_config(const char *pin_name, fs_type func_type, const char *whitelist[]) +{ + const struct fmux *p_fmux; + int index; + int8_t select; + + if (whitelist) { + if (0 != pinmux_check_whitelist(pin_name, whitelist)) { + LOG_W("Pin Name \"%s\" is NOT Allowed by Whitelist!", pin_name); + return -RT_ERROR; + } + } + + for (index = 0; index < ARRAY_SIZE(pinmux_array); index++) { + p_fmux = &(pinmux_array[index]); + LOG_D("index[%d]: name: %s, addr: %d, offset: %d, mask: %d\n", + index, p_fmux->name, p_fmux->addr, p_fmux->offset, p_fmux->mask); + if (0 == strcmp(pin_name, p_fmux->name)) { + break; + } + } + if (index == ARRAY_SIZE(pinmux_array)) { + LOG_W("Pin Name \"%s\" is not found!", pin_name); + return -RT_ERROR;; + } + if (p_fmux->selected) { + LOG_W("Pin Name \"%s\" has been selected, duplicated?", pin_name); + return -RT_ERROR; + } + + select = pinmux_get_index(index, func_type); + if (-1 == select) { + LOG_W("Can not found Function selection for Pin \"%s\"", pin_name); + return -RT_ERROR; + } + + LOG_I("Pin Name = \"%s\", Func Type = %d, selected Func [%d]\n", pin_name, func_type, select); + pinmux_array[index].selected = 1; + mmio_clrsetbits_32(PINMUX_BASE + p_fmux->addr, p_fmux->mask << p_fmux->offset, select); + return RT_EOK; +} diff --git a/bsp/cvitek/drivers/drv_pinmux.h b/bsp/cvitek/drivers/drv_pinmux.h new file mode 100644 index 0000000000..56f228d265 --- /dev/null +++ b/bsp/cvitek/drivers/drv_pinmux.h @@ -0,0 +1,448 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024/05/24 unicornx first version + */ +#ifndef __DRV_PINMUX_H__ +#define __DRV_PINMUX_H__ + +/** + * @brief Function Selection Type + * + * FIXME: At present, we only define the ones we will use, + * not all of them. We will need to add them later. + */ +typedef enum _fs_type +{ + fs_none = 0, + AUX0, + AUX1, + AUX2, + CAM_HS0, + CAM_MCLK0, + CAM_MCLK1, + CAM_VS0, + CLK25M, + CLK32K, + DBG_0, + DBG_1, + DBG_2, + DBG_3, + DBG_4, + DBG_5, + DBG_6, + DBG_7, + DBG_8, + DBG_9, + DBG_10, + DBG_11, + DBG_12, + DBG_13, + DBG_14, + DBG_15, + DBG_16, + DBG_18, + DBG_19, + EMMC_CLK, + EMMC_CMD, + EMMC_DAT_0, + EMMC_DAT_1, + EMMC_DAT_2, + EMMC_DAT_3, + EMMC_RSTN, + EPHY_LNK_LED, + EPHY_SPD_LED, + IIC0_SCL, + IIC0_SDA, + IIC1_SCL, + IIC1_SDA, + IIC2_SCL, + IIC2_SDA, + IIC3_SCL, + IIC3_SDA, + IIC4_SCL, + IIC4_SDA, + IIS1_BCLK, + IIS1_DI, + IIS1_DO, + IIS1_LRCK, + IIS1_MCLK, + IIS2_BCLK, + IIS2_DI, + IIS2_DO, + IIS2_LRCK, + IIS2_MCLK, + JTAG_TCK, + JTAG_TDI, + JTAG_TDO, + JTAG_TMS, + JTAG_CPU_TCK, + JTAG_CPU_TMS, + JTAG_CPU_TRST, + KEY_COL0, + KEY_COL1, + KEY_COL2, + KEY_COL3, + KEY_ROW0, + KEY_ROW1, + KEY_ROW2, + KEY_ROW3, + MUX_SPI1_CS, + MUX_SPI1_MISO, + MUX_SPI1_MOSI, + MUX_SPI1_SCK, + PKG_TYPE0, + PKG_TYPE1, + PKG_TYPE2, + PWM_0, + PWM_1, + PWM_2, + PWM_3, + PWM_4, + PWM_5, + PWM_6, + PWM_7, + PWM_8, + PWM_9, + PWM_10, + PWM_11, + PWM_12, + PWM_13, + PWM_14, + PWM_15, + PWR_BUTTON1, + PWR_GPIO_0, + PWR_GPIO_1, + PWR_GPIO_2, + PWR_GPIO_3, + PWR_GPIO_4, + PWR_GPIO_5, + PWR_GPIO_6, + PWR_GPIO_7, + PWR_GPIO_8, + PWR_GPIO_9, + PWR_GPIO_10, + PWR_GPIO_11, + PWR_GPIO_12, + PWR_GPIO_13, + PWR_GPIO_14, + PWR_GPIO_15, + PWR_GPIO_16, + PWR_GPIO_17, + PWR_GPIO_18, + PWR_GPIO_19, + PWR_GPIO_20, + PWR_GPIO_21, + PWR_GPIO_22, + PWR_GPIO_23, + PWR_GPIO_24, + PWR_GPIO_25, + PWR_GPIO_26, + PWR_IIC_SCL, + PWR_IIC_SDA, + PWR_IR0, + PWR_IR1, + PWR_MCU_JTAG_TCK, + PWR_MCU_JTAG_TDI, + PWR_MCU_JTAG_TDO, + PWR_MCU_JTAG_TMS, + PWR_ON, + PWR_PTEST, + PWR_RSTN, + PWR_SD1_CLK_VO37, + PWR_SD1_CMD_VO36, + PWR_SD1_D0_VO35, + PWR_SD1_D1_VO34, + PWR_SD1_D2_VO33, + PWR_SD1_D3_VO32, + PWR_SD1_CLK, + PWR_SD1_CMD, + PWR_SD1_D0, + PWR_SD1_D1, + PWR_SD1_D2, + PWR_SD1_D3, + PWR_SECTICK, + PWR_SEQ1, + PWR_SEQ2, + PWR_SEQ3, + PWR_SPINOR1_CS_X, + PWR_SPINOR1_HOLD_X, + PWR_SPINOR1_MISO, + PWR_SPINOR1_MOSI, + PWR_SPINOR1_SCK, + PWR_SPINOR1_WP_X, + PWR_UART0_RX, + PWR_UART0_TX, + PWR_UART1_RX, + PWR_UART1_TX, + PWR_VBAT_DET, + PWR_WAKEUP0, + PWR_WAKEUP1, + PWR_XTAL_CLKIN, + RMII0_IRQ, + RMII0_MDC, + RMII0_MDIO, + RMII0_REFCLKI, + RMII0_RXD0, + RMII0_RXD1, + RMII0_RXDV, + RMII0_TXCLK, + RMII0_TXD0, + RMII0_TXD1, + RMII0_TXEN, + RSTN, + SD1_CLK, + SD1_CMD, + SD1_D0, + SD1_D1, + SD1_D2, + SD1_D3, + SDIO0_CD, + SDIO0_CLK, + SDIO0_CMD, + SDIO0_D_0, + SDIO0_D_1, + SDIO0_D_2, + SDIO0_D_3, + SDIO0_PWR_EN, + SPI0_CS_X, + SPI0_SCK, + SPI0_SDI, + SPI0_SDO, + SPI1_CS_X, + SPI1_SCK, + SPI1_SDI, + SPI1_SDO, + SPI2_CS_X, + SPI2_SCK, + SPI2_SDI, + SPI2_SDO, + SPI3_CS_X, + SPI3_SCK, + SPI3_SDI, + SPI3_SDO, + SPINAND_CLK, + SPINAND_CS, + SPINAND_HOLD, + SPINAND_MISO, + SPINAND_MOSI, + SPINAND_WP, + SPINOR_CS_X, + SPINOR_HOLD_X, + SPINOR_MISO, + SPINOR_MOSI, + SPINOR_SCK, + SPINOR_WP_X, + UART0_RX, + UART0_TX, + UART1_CTS, + UART1_RTS, + UART1_RX, + UART1_TX, + UART2_CTS, + UART2_RTS, + UART2_RX, + UART2_TX, + UART3_CTS, + UART3_RTS, + UART3_RX, + UART3_TX, + UART4_CTS, + UART4_RTS, + UART4_RX, + UART4_TX, + USB_ID, + USB_VBUS_DET, + USB_VBUS_EN, + VI0_CLK, + VI0_D_0, + VI0_D_1, + VI0_D_2, + VI0_D_3, + VI0_D_4, + VI0_D_5, + VI0_D_6, + VI0_D_7, + VI0_D_8, + VI0_D_9, + VI0_D_10, + VI0_D_11, + VI0_D_12, + VI0_D_13, + VI0_D_14, + VI0_D_15, + VI1_CLK, + VI1_D_0, + VI1_D_1, + VI1_D_2, + VI1_D_3, + VI1_D_4, + VI1_D_5, + VI1_D_6, + VI1_D_7, + VI1_D_8, + VI1_D_9, + VI1_D_10, + VI1_D_11, + VI1_D_12, + VI1_D_13, + VI1_D_14, + VI1_D_15, + VI1_D_16, + VI1_D_17, + VI1_D_18, + VI2_CLK, + VI2_D_0, + VI2_D_1, + VI2_D_2, + VI2_D_3, + VI2_D_4, + VI2_D_5, + VI2_D_6, + VI2_D_7, + VO_CLK0, + VO_CLK1, + VO_D_0, + VO_D_1, + VO_D_2, + VO_D_3, + VO_D_4, + VO_D_5, + VO_D_6, + VO_D_7, + VO_D_8, + VO_D_9, + VO_D_10, + VO_D_11, + VO_D_12, + VO_D_13, + VO_D_14, + VO_D_15, + VO_D_16, + VO_D_17, + VO_D_18, + VO_D_19, + VO_D_20, + VO_D_21, + VO_D_22, + VO_D_23, + VO_D_24, + VO_D_25, + VO_D_26, + VO_D_27, + VO_D_28, + VO_D_29, + VO_D_30, + VO_D_31, + WG0_D0, + WG0_D1, + WG1_D0, + WG1_D1, + WG2_D0, + WG2_D1, + XGPIOA_0, + XGPIOA_1, + XGPIOA_2, + XGPIOA_3, + XGPIOA_4, + XGPIOA_5, + XGPIOA_6, + XGPIOA_7, + XGPIOA_8, + XGPIOA_9, + XGPIOA_10, + XGPIOA_11, + XGPIOA_12, + XGPIOA_13, + XGPIOA_14, + XGPIOA_15, + XGPIOA_16, + XGPIOA_17, + XGPIOA_18, + XGPIOA_19, + XGPIOA_20, + XGPIOA_21, + XGPIOA_22, + XGPIOA_23, + XGPIOA_24, + XGPIOA_25, + XGPIOA_26, + XGPIOA_27, + XGPIOA_28, + XGPIOA_29, + XGPIOA_30, + XGPIOB_0, + XGPIOB_1, + XGPIOB_2, + XGPIOB_3, + XGPIOB_4, + XGPIOB_5, + XGPIOB_6, + XGPIOB_7, + XGPIOB_8, + XGPIOB_9, + XGPIOB_10, + XGPIOB_11, + XGPIOB_12, + XGPIOB_13, + XGPIOB_14, + XGPIOB_15, + XGPIOB_16, + XGPIOB_17, + XGPIOB_18, + XGPIOB_19, + XGPIOB_20, + XGPIOB_21, + XGPIOB_22, + XGPIOB_23, + XGPIOB_24, + XGPIOB_25, + XGPIOB_26, + XGPIOB_27, + XGPIOC_0, + XGPIOC_1, + XGPIOC_2, + XGPIOC_3, + XGPIOC_4, + XGPIOC_5, + XGPIOC_6, + XGPIOC_7, + XGPIOC_8, + XGPIOC_9, + XGPIOC_10, + XGPIOC_11, + XGPIOC_12, + XGPIOC_13, + XGPIOC_14, + XGPIOC_15, + XGPIOC_16, + XGPIOC_17, + XGPIOC_18, + XGPIOC_19, + XGPIOC_20, + XGPIOC_21, + XGPIOC_22, + XGPIOC_23, + XGPIOC_24, + XGPIOC_25, +} fs_type; + +/** + * @brief configure pin multiplex + * + * @param pin_name pin name string + * @param func_type function type enum + * @param whitelist pin name whilelist which is allowed to set. Ignore check + * if NULL. + * NOTE: whitelist should be a string list ended with NULL. + * + * @return RT_EOK if succeeded + * else: something wrong occurred and config is abandoned. + */ +extern int pinmux_config(const char *pin_name, fs_type func_type, const char *whitelist[]); + +#endif From d8d0af9143bc40c017aa7d9833b6a87e5d843968 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Mon, 13 May 2024 08:05:34 +0800 Subject: [PATCH 04/48] bsp:cvitek: add calibration for adc The ADC controller needs to be calibrated during the initialization phase, otherwise the measured voltage value will be inaccurate. Signed-off-by: Chen Wang --- bsp/cvitek/drivers/drv_adc.c | 8 +++++++- bsp/cvitek/drivers/drv_adc.h | 18 ++++++++++++++++++ 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/bsp/cvitek/drivers/drv_adc.c b/bsp/cvitek/drivers/drv_adc.c index 39440cd49a..242d2216eb 100644 --- a/bsp/cvitek/drivers/drv_adc.c +++ b/bsp/cvitek/drivers/drv_adc.c @@ -103,7 +103,13 @@ static const struct rt_adc_ops _adc_ops = int rt_hw_adc_init(void) { rt_uint8_t i; - for (i = 0; i < sizeof(adc_dev_config) / sizeof(adc_dev_config[0]); i ++) + + for (i = 0; i < sizeof(adc_dev_config) / sizeof(adc_dev_config[0]); i++) + { + cvi_do_calibration(adc_dev_config[i].base); + } + + for (i = 0; i < sizeof(adc_dev_config) / sizeof(adc_dev_config[0]); i++) { if (rt_hw_adc_register(&adc_dev_config[i].device, adc_dev_config[i].name, &_adc_ops, &adc_dev_config[i]) != RT_EOK) { diff --git a/bsp/cvitek/drivers/drv_adc.h b/bsp/cvitek/drivers/drv_adc.h index 7539ab5604..3ef86a2ecb 100644 --- a/bsp/cvitek/drivers/drv_adc.h +++ b/bsp/cvitek/drivers/drv_adc.h @@ -48,6 +48,11 @@ #define SARADC_RESULT_MASK 0x0FFF #define SARADC_RESULT_VALID (1 << 15) +#define SARADC_TEST_OFFSET 0x030 +#define SARADC_TEST_VREFSEL_BIT 2 + +#define SARADC_TRIM_OFFSET 0x034 + rt_inline void cvi_set_saradc_ctrl(unsigned long reg_base, rt_uint32_t value) { value |= mmio_read_32(reg_base + SARADC_CTRL_OFFSET); @@ -78,6 +83,19 @@ rt_inline void cvi_set_cyc(unsigned long reg_base) mmio_write_32(reg_base + SARADC_CYC_SET_OFFSET, value); } +rt_inline void cvi_do_calibration(unsigned long reg_base) +{ + rt_uint32_t val; + + val = mmio_read_32(reg_base + SARADC_TEST_OFFSET); + val |= 1 << SARADC_TEST_VREFSEL_BIT; + mmio_write_32(reg_base + SARADC_TEST_OFFSET, val); + + val = mmio_read_32(reg_base + SARADC_TRIM_OFFSET); + val |= 0x4; + mmio_write_32(reg_base + SARADC_TRIM_OFFSET, val); +} + int rt_hw_adc_init(void); #endif /* __DRV_ADC_H__ */ From 1b581d0755450788b161f05486ecd97ee4f88ff3 Mon Sep 17 00:00:00 2001 From: Shell Date: Tue, 16 Jul 2024 17:03:54 +0800 Subject: [PATCH 05/48] [dfs] Mark dirty on unmap on shared mapping only (#9195) [dfs] feat: Mark dirty on unmap for shared mapping This patch optimizes the pcache varea management by refining the conditions under which pages are marked dirty, specifically targeting the unmap operations in the dfs_pcache component. These changes were necessary to enhance the efficiency of page cache management. Changes: - Adjusted include statements in `dfs_pcache.c` for better organization. - Modified `dfs_aspace_unmap` function: - Added a check to ensure `varea` is not privately locked before marking a page as dirty. - Updated `dfs_aspace_page_unmap` function: - Added a similar check for `varea` lock status before marking a page as dirty. Signed-off-by: Shell --- components/dfs/dfs_v2/src/dfs_pcache.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/components/dfs/dfs_v2/src/dfs_pcache.c b/components/dfs/dfs_v2/src/dfs_pcache.c index 350ad1f061..6868170b9c 100644 --- a/components/dfs/dfs_v2/src/dfs_pcache.c +++ b/components/dfs/dfs_v2/src/dfs_pcache.c @@ -13,10 +13,11 @@ #define DBG_LVL DBG_WARNING #include -#include "dfs_pcache.h" -#include "dfs_dentry.h" -#include "dfs_mnt.h" -#include "mm_page.h" +#include +#include +#include +#include +#include #include #include @@ -1380,7 +1381,8 @@ int dfs_aspace_unmap(struct dfs_file *file, struct rt_varea *varea) rt_varea_unmap_page(map_varea, vaddr); - if (varea->attr == MMU_MAP_U_RWCB && page->fpos < page->aspace->vnode->size) + if (!rt_varea_is_private_locked(varea) && + page->fpos < page->aspace->vnode->size) { dfs_page_dirty(page); } @@ -1425,7 +1427,7 @@ int dfs_aspace_page_unmap(struct dfs_file *file, struct rt_varea *varea, void *v if (map && varea->aspace == map->aspace && vaddr == map->vaddr) { - if (varea->attr == MMU_MAP_U_RWCB) + if (!rt_varea_is_private_locked(varea)) { dfs_page_dirty(page); } From 23fc7bfa4d992a105d72f114f0a712b3f61cbd65 Mon Sep 17 00:00:00 2001 From: zms123456 <85141075+zmshahaha@users.noreply.github.com> Date: Tue, 16 Jul 2024 17:04:55 +0800 Subject: [PATCH 06/48] [libcpu][setup]fix fdt_ptr error (#9138) fix fdt_ptr error --- libcpu/aarch64/common/setup.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libcpu/aarch64/common/setup.c b/libcpu/aarch64/common/setup.c index b38398ed9d..dd30b1d673 100644 --- a/libcpu/aarch64/common/setup.c +++ b/libcpu/aarch64/common/setup.c @@ -235,7 +235,7 @@ void rt_hw_common_setup(void) rt_memblock_reserve_memory("fdt", fdt_start, fdt_end, MEMBLOCK_NONE); rt_memmove((void *)(fdt_start - PV_OFFSET), (void *)(fdt_ptr - PV_OFFSET), fdt_size); - fdt_ptr = (void *)fdt_start; + fdt_ptr = (void *)fdt_start - PV_OFFSET; rt_system_heap_init((void *)(heap_start - PV_OFFSET), (void *)(heap_end - PV_OFFSET)); From e1eb3d321712cee44de1a3698fb58ef75e5d8339 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Tue, 28 May 2024 16:33:30 +0800 Subject: [PATCH 07/48] bsp:cvitek: add pinmux for i2c Based on new pinmux framework, add configuration for uart. Board level pin available info is summarized and should be controlled by pin whitelist. Duo NAME I2C CV1800B/GPIO __ ---- --- ------------ --------------------- GP0 I2C0_SCL XGPIOA[28] IIC0_SCL__IIC0_SCL GP1 I2C0_SDA XGPIOA[29] IIC0_SDA__IIC0_SDA GP4 I2C1_SCL PWR_GPIO[19] SD1_D2__IIC1_SCL GP9 I2C1_SCL PWR_GPIO[18] SD1_D3__IIC1_SCL GP11 I2C1_SCL XGPIOC[10] PAD_MIPIRX0N__IIC1_SCL GP5 I2C1_SDA PWR_GPIO[20] SD1_D1__IIC1_SDA GP8 I2C1_SDA PWR_GPIO[21] SD1_D0__IIC1_SDA GP10 I2C1_SDA XGPIOC[9] PAD_MIPIRX1P__IIC1_SDA GP7 I2C3_SCL PWR_GPIO[22] SD1_CMD__IIC3_SCL GP6 I2C3_SDA PWR_GPIO[23] SD1_CLK__IIC3_SDA Duo256m NAME I2C CV1800B/GPIO __ ---- --- ------------ --------------------- GP4 I2C1_SCL PWR_GPIO[19] SD1_D2__IIC1_SCL GP9 I2C1_SCL PWR_GPIO[18] SD1_D3__IIC1_SCL GP5 I2C1_SDA PWR_GPIO[20] SD1_D1__IIC1_SDA GP8 I2C1_SDA PWR_GPIO[21] SD1_D0__IIC1_SDA GP11 I2C2_SCL XGPIOC[15] PAD_MIPI_TXP1__IIC2_SCL GP10 I2C2_SDA XGPIOC[14] PAD_MIPI_TXM1__IIC2_SDA GP7 I2C3_SCL PWR_GPIO[22] SD1_CMD__IIC3_SCL GP6 I2C3_SDA PWR_GPIO[23] SD1_CLK__IIC3_SDA Duo S(Note, we have not supported duo S, just list for memo) NAME I2C CV1800B/GPIO __ ---- --- ------------ --------------------- J3-B18 I2C1_SCL XGPIOB[18] VIVO_D3__IIC1_SCL J3-B12 I2C1_SCL XGPIOB[12] VIVO_D9__IIC1_SCL J3-B11 I2C1_SDA XGPIOB[11] VIVO_D10__IIC1_SDA J3-B13 I2C2_SCL XGPIOB[13] VIVO_D8__IIC2_SCL J4-E1 I2C2_SCL PWR_GPIO[1] PWR_GPIO1__IIC2_SCL J3-B14 I2C2_SDA XGPIOB[14] VIVO_D7__IIC2_SDA J4-E2 I2C2_SDA PWR_GPIO[2] PWR_GPIO2__IIC2_SDA J3-B20 I2C4_SCL XGPIOB[20] VIVO_D1__IIC4_SCL J4-B1 I2C4_SCL XGPIOB[1] ADC3__IIC4_SCL J3-B21 I2C4_SDA XGPIOB[21] VIVO_D0__IIC4_SDA J4-B2 I2C4_SDA XGPIOB[2] ADC2__IIC4_SDA Signed-off-by: Chen Wang --- bsp/cvitek/c906_little/board/Kconfig | 57 +++++++++ bsp/cvitek/cv18xx_risc-v/board/Kconfig | 57 +++++++++ bsp/cvitek/drivers/drv_hw_i2c.c | 160 +++++++++++++++++++++++-- 3 files changed, 265 insertions(+), 9 deletions(-) diff --git a/bsp/cvitek/c906_little/board/Kconfig b/bsp/cvitek/c906_little/board/Kconfig index 06d8214321..acb65707cc 100755 --- a/bsp/cvitek/c906_little/board/Kconfig +++ b/bsp/cvitek/c906_little/board/Kconfig @@ -31,10 +31,67 @@ menu "General Drivers Configuration" bool "Enable I2C0" default n + if BSP_USING_I2C0 + config BSP_I2C0_SCL_PINNAME + string "i2c0 scl pin name" + default "" + config BSP_I2C0_SDA_PINNAME + string "i2c0 sda pin name" + default "" + endif + config BSP_USING_I2C1 bool "Enable I2C1" default n + if BSP_USING_I2C1 + config BSP_I2C1_SCL_PINNAME + string "i2c1 scl pin name" + default "" + config BSP_I2C1_SDA_PINNAME + string "i2c1 sda pin name" + default "" + endif + + config BSP_USING_I2C2 + bool "Enable I2C2" + default n + + if BSP_USING_I2C2 + config BSP_I2C2_SCL_PINNAME + string "i2c2 scl pin name" + default "" + config BSP_I2C2_SDA_PINNAME + string "i2c2 sda pin name" + default "" + endif + + config BSP_USING_I2C3 + bool "Enable I2C3" + default n + + if BSP_USING_I2C3 + config BSP_I2C3_SCL_PINNAME + string "i2c3 scl pin name" + default "" + config BSP_I2C3_SDA_PINNAME + string "i2c3 sda pin name" + default "" + endif + + config BSP_USING_I2C4 + bool "Enable I2C4" + default n + + if BSP_USING_I2C4 + config BSP_I2C4_SCL_PINNAME + string "i2c4 scl pin name" + default "" + config BSP_I2C4_SDA_PINNAME + string "i2c4 sda pin name" + default "" + endif + config I2C_IRQ_BASE int default 32 diff --git a/bsp/cvitek/cv18xx_risc-v/board/Kconfig b/bsp/cvitek/cv18xx_risc-v/board/Kconfig index bc213c777e..3c3b7daacb 100755 --- a/bsp/cvitek/cv18xx_risc-v/board/Kconfig +++ b/bsp/cvitek/cv18xx_risc-v/board/Kconfig @@ -44,10 +44,67 @@ menu "General Drivers Configuration" bool "Enable I2C0" default n + if BSP_USING_I2C0 + config BSP_I2C0_SCL_PINNAME + string "i2c0 scl pin name" + default "" + config BSP_I2C0_SDA_PINNAME + string "i2c0 sda pin name" + default "" + endif + config BSP_USING_I2C1 bool "Enable I2C1" default n + if BSP_USING_I2C1 + config BSP_I2C1_SCL_PINNAME + string "i2c1 scl pin name" + default "" + config BSP_I2C1_SDA_PINNAME + string "i2c1 sda pin name" + default "" + endif + + config BSP_USING_I2C2 + bool "Enable I2C2" + default n + + if BSP_USING_I2C2 + config BSP_I2C2_SCL_PINNAME + string "i2c2 scl pin name" + default "" + config BSP_I2C2_SDA_PINNAME + string "i2c2 sda pin name" + default "" + endif + + config BSP_USING_I2C3 + bool "Enable I2C3" + default n + + if BSP_USING_I2C3 + config BSP_I2C3_SCL_PINNAME + string "i2c3 scl pin name" + default "" + config BSP_I2C3_SDA_PINNAME + string "i2c3 sda pin name" + default "" + endif + + config BSP_USING_I2C4 + bool "Enable I2C4" + default n + + if BSP_USING_I2C4 + config BSP_I2C4_SCL_PINNAME + string "i2c4 scl pin name" + default "" + config BSP_I2C4_SDA_PINNAME + string "i2c4 sda pin name" + default "" + endif + config I2C_IRQ_BASE int default 49 diff --git a/bsp/cvitek/drivers/drv_hw_i2c.c b/bsp/cvitek/drivers/drv_hw_i2c.c index 022a050c74..6f2fd06b40 100644 --- a/bsp/cvitek/drivers/drv_hw_i2c.c +++ b/bsp/cvitek/drivers/drv_hw_i2c.c @@ -10,6 +10,7 @@ #include "drv_hw_i2c.h" #include #include +#include "drv_pinmux.h" #define DBG_TAG "drv.i2c" #define DBG_LVL DBG_INFO @@ -467,19 +468,160 @@ static const struct rt_i2c_bus_device_ops i2c_ops = .i2c_bus_control = RT_NULL }; + +#if defined(BOARD_TYPE_MILKV_DUO) || defined(BOARD_TYPE_MILKV_DUO_SPINOR) + +#ifdef BSP_USING_I2C0 +static const char *pinname_whitelist_i2c0_scl[] = { + "IIC0_SCL", + NULL, +}; +static const char *pinname_whitelist_i2c0_sda[] = { + "IIC0_SDA", + NULL, +}; +#endif + +#ifdef BSP_USING_I2C1 +static const char *pinname_whitelist_i2c1_scl[] = { + "SD1_D2", + "SD1_D3", + "PAD_MIPIRX0N", + NULL, +}; +static const char *pinname_whitelist_i2c1_sda[] = { + "SD1_D1", + "SD1_D0", + "PAD_MIPIRX1P", + NULL, +}; +#endif + +#ifdef BSP_USING_I2C2 +// I2C2 is not ALLOWED for Duo +static const char *pinname_whitelist_i2c2_scl[] = { + NULL, +}; +static const char *pinname_whitelist_i2c2_sda[] = { + NULL, +}; +#endif + +#ifdef BSP_USING_I2C3 +static const char *pinname_whitelist_i2c3_scl[] = { + "SD1_CMD", + NULL, +}; +static const char *pinname_whitelist_i2c3_sda[] = { + "SD1_CLK", + NULL, +}; +#endif + +#ifdef BSP_USING_I2C4 +// I2C4 is not ALLOWED for Duo +static const char *pinname_whitelist_i2c4_scl[] = { + NULL, +}; +static const char *pinname_whitelist_i2c4_sda[] = { + NULL, +}; +#endif + +#elif defined(BOARD_TYPE_MILKV_DUO256M) || defined(BOARD_TYPE_MILKV_DUO256M_SPINOR) + +#ifdef BSP_USING_I2C0 +// I2C0 is not ALLOWED for Duo +static const char *pinname_whitelist_i2c0_scl[] = { + NULL, +}; +static const char *pinname_whitelist_i2c0_sda[] = { + NULL, +}; +#endif + +#ifdef BSP_USING_I2C1 +static const char *pinname_whitelist_i2c1_scl[] = { + "SD1_D2", + "SD1_D3", + NULL, +}; +static const char *pinname_whitelist_i2c1_sda[] = { + "SD1_D1", + "SD1_D0", + NULL, +}; +#endif + +#ifdef BSP_USING_I2C2 +static const char *pinname_whitelist_i2c2_scl[] = { + "PAD_MIPI_TXP1", + NULL, +}; +static const char *pinname_whitelist_i2c2_sda[] = { + "PAD_MIPI_TXM1", + NULL, +}; +#endif + +#ifdef BSP_USING_I2C3 +static const char *pinname_whitelist_i2c3_scl[] = { + "SD1_CMD", + NULL, +}; +static const char *pinname_whitelist_i2c3_sda[] = { + "SD1_CLK", + NULL, +}; +#endif + +#ifdef BSP_USING_I2C4 +// I2C4 is not ALLOWED for Duo +static const char *pinname_whitelist_i2c4_scl[] = { + NULL, +}; +static const char *pinname_whitelist_i2c4_sda[] = { + NULL, +}; +#endif + +#else + #error "Unsupported board type!" +#endif + +static void rt_hw_i2c_pinmux_config() +{ +#ifdef BSP_USING_I2C0 + pinmux_config(BSP_I2C0_SCL_PINNAME, IIC0_SCL, pinname_whitelist_i2c0_scl); + pinmux_config(BSP_I2C0_SDA_PINNAME, IIC0_SDA, pinname_whitelist_i2c0_sda); +#endif /* BSP_USING_I2C0 */ + +#ifdef BSP_USING_I2C1 + pinmux_config(BSP_I2C1_SCL_PINNAME, IIC1_SCL, pinname_whitelist_i2c1_scl); + pinmux_config(BSP_I2C1_SDA_PINNAME, IIC1_SDA, pinname_whitelist_i2c1_sda); +#endif /* BSP_USING_I2C1 */ + +#ifdef BSP_USING_I2C2 + pinmux_config(BSP_I2C2_SCL_PINNAME, IIC2_SCL, pinname_whitelist_i2c2_scl); + pinmux_config(BSP_I2C2_SDA_PINNAME, IIC2_SDA, pinname_whitelist_i2c2_sda); +#endif /* BSP_USING_I2C2 */ + +#ifdef BSP_USING_I2C3 + pinmux_config(BSP_I2C3_SCL_PINNAME, IIC3_SCL, pinname_whitelist_i2c3_scl); + pinmux_config(BSP_I2C3_SDA_PINNAME, IIC3_SDA, pinname_whitelist_i2c3_sda); +#endif /* BSP_USING_I2C3 */ + +#ifdef BSP_USING_I2C4 + pinmux_config(BSP_I2C4_SCL_PINNAME, IIC4_SCL, pinname_whitelist_i2c4_scl); + pinmux_config(BSP_I2C4_SDA_PINNAME, IIC4_SDA, pinname_whitelist_i2c4_sda); +#endif /* BSP_USING_I2C4 */ +} + int rt_hw_i2c_init(void) { int result = RT_EOK; -#ifdef BSP_USING_I2C0 - PINMUX_CONFIG(IIC0_SCL, IIC0_SCL); - PINMUX_CONFIG(IIC0_SDA, IIC0_SDA); -#endif /* BSP_USING_I2C0 */ - -#ifdef BSP_USING_I2C1 - PINMUX_CONFIG(PAD_MIPIRX1P, IIC1_SDA); - PINMUX_CONFIG(PAD_MIPIRX0N, IIC1_SCL); -#endif /* BSP_USING_I2C1 */ + rt_hw_i2c_pinmux_config(); for (rt_size_t i = 0; i < sizeof(_i2c_obj) / sizeof(struct _i2c_bus); i++) { From 114e143d56e5aabaee93880b06767ef8ebb832c3 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Tue, 28 May 2024 16:12:24 +0800 Subject: [PATCH 08/48] bsp:cvitek: add pinmux for uart Board level UART pinmux summary, following capability should be controlled by pinname whitelist. Duo: NAME UART CV1800B/GPIO __ ---- --- ------------ --------------------- GP13 UART0_RX XGPIOA[17] UART0_RX__UART0_RX GP12 UART0_TX XGPIOA[16] UART0_TX__UART0_TX GP1 UART1_RX XGPIOA[29] IIC0_SDA__UART1_RX GP13 UART1_RX XGPIOA[17] UART0_RX__UART1_RX GP0 UART1_TX XGPIOA[28] IIC0_SCL__UART1_TX GP12 UART1_TX XGPIOA[16] UART0_TX__UART1_TX GP1 UART2_RX XGPIOA[29] IIC0_SDA__UART2_RX GP5 UART2_RX PWR_GPIO[20] SD1_D1__UART2_RX GP0 UART2_TX XGPIOA[28] IIC0_SCL__UART2_TX GP4 UART2_TX PWR_GPIO[19] SD1_D2__UART2_TX GP5 UART3_RX PWR_GPIO[20] SD1_D1__UART3_RX GP4 UART3_TX PWR_GPIO[19] SD1_D2__UART3_TX GP3 UART4_RX PWR_GPIO[25] SD1_GPIO0__UART4_RX GP2 UART4_TX PWR_GPIO[26] SD1_GPIO1__UART4_TX Duo 256m: NAME UART CV1800B/GPIO __ ---- --- ------------ --------------------- GP13 UART0_RX XGPIOA[17] UART0_RX__UART0_RX GP12 UART0_TX XGPIOA[16] UART0_TX__UART0_TX GP1 UART1_RX XGPIOA[29] IIC0_SDA__UART1_RX GP3 UART1_RX XGPIOA[18] JTAG_CPU_TCK__UART1_RX GP13 UART1_RX XGPIOA[17] UART0_RX__UART1_RX GP0 UART1_TX XGPIOA[28] IIC0_SCL__UART1_TX GP2 UART1_TX XGPIOA[19] JTAG_CPU_TMS__UART1_TX GP12 UART1_TX XGPIOA[16] UART0_TX__UART1_TX GP1 UART2_RX XGPIOA[29] IIC0_SDA__UART2_RX GP5 UART2_RX PWR_GPIO[20] SD1_D1__UART2_RX GP0 UART2_TX XGPIOA[28] IIC0_SCL__UART2_TX GP4 UART2_TX PWR_GPIO[19] SD1_D2__UART2_TX GP5 UART3_RX PWR_GPIO[20] SD1_D1__UART3_RX GP4 UART3_TX PWR_GPIO[19] SD1_D2__UART3_TX Note: this patch also update the .config and rtconfig.h because this patch modify some configuration items's name, for example: RT_USIMG_UART0 -> BSP_USING_UART0. FIXME: only handle RISC-V related, no ARM. Signed-off-by: Chen Wang --- bsp/cvitek/c906_little/.config | 59 ++++++--- bsp/cvitek/c906_little/board/Kconfig | 73 +++++++++-- bsp/cvitek/c906_little/rtconfig.h | 18 ++- bsp/cvitek/cv18xx_risc-v/.config | 62 +++++++--- bsp/cvitek/cv18xx_risc-v/board/Kconfig | 88 +++++++++---- bsp/cvitek/cv18xx_risc-v/rtconfig.h | 18 ++- bsp/cvitek/drivers/drv_uart.c | 165 ++++++++++++++++++++++--- 7 files changed, 391 insertions(+), 92 deletions(-) diff --git a/bsp/cvitek/c906_little/.config b/bsp/cvitek/c906_little/.config index cb930cd937..5fe52bcac9 100644 --- a/bsp/cvitek/c906_little/.config +++ b/bsp/cvitek/c906_little/.config @@ -15,7 +15,6 @@ CONFIG_RT_THREAD_PRIORITY_32=y # CONFIG_RT_THREAD_PRIORITY_256 is not set CONFIG_RT_THREAD_PRIORITY_MAX=32 CONFIG_RT_TICK_PER_SECOND=1000 -CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y CONFIG_RT_HOOK_USING_FUNC_PTR=y # CONFIG_RT_USING_HOOKLIST is not set @@ -25,6 +24,8 @@ CONFIG_IDLE_THREAD_STACK_SIZE=1024 CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 CONFIG_RT_TIMER_THREAD_STACK_SIZE=2048 +# CONFIG_RT_USING_TIMER_ALL_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set # # kservice optimization @@ -45,6 +46,7 @@ CONFIG_RT_DEBUGING_ASSERT=y CONFIG_RT_DEBUGING_COLOR=y CONFIG_RT_DEBUGING_CONTEXT=y # CONFIG_RT_DEBUGING_AUTO_INIT is not set +CONFIG_RT_USING_OVERFLOW_CHECK=y # # Inter-Thread communication @@ -131,6 +133,7 @@ CONFIG_FINSH_USING_OPTION_COMPLETION=y # Device Drivers # # CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_DEV_BUS is not set CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_UNAMED_PIPE_NUMBER=64 # CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set @@ -149,6 +152,8 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_ZERO is not set # CONFIG_RT_USING_RANDOM is not set # CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set # CONFIG_RT_USING_PM is not set @@ -161,21 +166,12 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_TOUCH is not set # CONFIG_RT_USING_LCD is not set # CONFIG_RT_USING_HWCRYPTO is not set -# CONFIG_RT_USING_PULSE_ENCODER is not set -# CONFIG_RT_USING_INPUT_CAPTURE is not set -# CONFIG_RT_USING_DEV_BUS is not set # CONFIG_RT_USING_WIFI is not set # CONFIG_RT_USING_VIRTIO is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_KTIME is not set # CONFIG_RT_USING_HWTIMER is not set - -# -# Using USB -# -# CONFIG_RT_USING_USB_HOST is not set -# CONFIG_RT_USING_USB_DEVICE is not set -# end of Using USB +# CONFIG_RT_USING_CHERRYUSB is not set # end of Device Drivers # @@ -252,6 +248,15 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # end of Utilities # CONFIG_RT_USING_VBUS is not set + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set # end of RT-Thread Components # @@ -279,6 +284,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set # # Wi-Fi @@ -383,6 +389,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ZEPHYR_POLLING is not set # CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set # CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set # end of IoT - internet of things # @@ -528,6 +535,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set # end of enhanced kernel services +# CONFIG_PKG_USING_AUNITY is not set + # # acceleration: Assembly language or algorithmic acceleration packages # @@ -618,11 +627,27 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # STM32 HAL & SDK Drivers # -# CONFIG_PKG_USING_STM32L4XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set # CONFIG_PKG_USING_STM32WB55_SDK is not set # CONFIG_PKG_USING_STM32_SDIO is not set # end of STM32 HAL & SDK Drivers +# +# Infineon HAL Packages +# +# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set +# CONFIG_PKG_USING_INFINEON_CMSIS is not set +# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set +# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set +# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set +# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set +# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set +# CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + # CONFIG_PKG_USING_BLUETRUM_SDK is not set # CONFIG_PKG_USING_EMBARC_BSP is not set # CONFIG_PKG_USING_ESP_IDF is not set @@ -817,6 +842,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # Signal Processing and Control Algorithm Packages # +# CONFIG_PKG_USING_APID is not set # CONFIG_PKG_USING_FIRE_PID_CURVE is not set # CONFIG_PKG_USING_QPID is not set # CONFIG_PKG_USING_UKAL is not set @@ -1133,8 +1159,13 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # General Drivers Configuration # CONFIG_BSP_USING_UART=y -# CONFIG_RT_USING_UART0 is not set -CONFIG_RT_USING_UART1=y +# CONFIG_BSP_USING_UART0 is not set +CONFIG_BSP_USING_UART1=y +CONFIG_BSP_UART1_RX_PINNAME="IIC0_SDA" +CONFIG_BSP_UART1_TX_PINNAME="IIC0_SCL" +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_UART4 is not set CONFIG_UART_IRQ_BASE=30 # CONFIG_BSP_USING_I2C is not set # CONFIG_BSP_USING_ADC is not set diff --git a/bsp/cvitek/c906_little/board/Kconfig b/bsp/cvitek/c906_little/board/Kconfig index acb65707cc..6b7d6f91c5 100755 --- a/bsp/cvitek/c906_little/board/Kconfig +++ b/bsp/cvitek/c906_little/board/Kconfig @@ -6,17 +6,74 @@ menu "General Drivers Configuration" default y if BSP_USING_UART - config RT_USING_UART0 - bool "Enable UART 0" - default n + config BSP_USING_UART0 + bool "Enable UART 0" + default n - config RT_USING_UART1 - bool "Enable UART 1" - default y + if BSP_USING_UART0 + config BSP_UART0_RX_PINNAME + string "uart0 rx pin name" + default "" + config BSP_UART0_TX_PINNAME + string "uart0 tx pin name" + default "" + endif + + config BSP_USING_UART1 + bool "Enable UART 1" + default y + + if BSP_USING_UART1 + config BSP_UART1_RX_PINNAME + string "uart1 rx pin name" + default "IIC0_SDA" + config BSP_UART1_TX_PINNAME + string "uart1 tx pin name" + default "IIC0_SCL" + endif + + config BSP_USING_UART2 + bool "Enable UART 2" + default n + + if BSP_USING_UART2 + config BSP_UART2_RX_PINNAME + string "uart2 rx pin name" + default "" + config BSP_UART2_TX_PINNAME + string "uart2 tx pin name" + default "" + endif + + config BSP_USING_UART3 + bool "Enable UART 3" + default n + + if BSP_USING_UART3 + config BSP_UART3_RX_PINNAME + string "uart3 rx pin name" + default "" + config BSP_UART3_TX_PINNAME + string "uart3 tx pin name" + default "" + endif + + config BSP_USING_UART4 + bool "Enable UART 4" + default n + + if BSP_USING_UART4 + config BSP_UART4_RX_PINNAME + string "uart4 rx pin name" + default "" + config BSP_UART4_TX_PINNAME + string "uart4 tx pin name" + default "" + endif config UART_IRQ_BASE - int - default 30 + int + default 30 endif menuconfig BSP_USING_I2C diff --git a/bsp/cvitek/c906_little/rtconfig.h b/bsp/cvitek/c906_little/rtconfig.h index 70ef72f518..e86cf64339 100755 --- a/bsp/cvitek/c906_little/rtconfig.h +++ b/bsp/cvitek/c906_little/rtconfig.h @@ -9,7 +9,6 @@ #define RT_THREAD_PRIORITY_32 #define RT_THREAD_PRIORITY_MAX 32 #define RT_TICK_PER_SECOND 1000 -#define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK @@ -31,6 +30,7 @@ #define RT_DEBUGING_ASSERT #define RT_DEBUGING_COLOR #define RT_DEBUGING_CONTEXT +#define RT_USING_OVERFLOW_CHECK /* Inter-Thread communication */ @@ -95,10 +95,6 @@ #define RT_SERIAL_USING_DMA #define RT_SERIAL_RB_BUFSZ 64 #define RT_USING_PIN - -/* Using USB */ - -/* end of Using USB */ /* end of Device Drivers */ /* C/C++ and POSIX layer */ @@ -137,6 +133,10 @@ /* Utilities */ /* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ /* end of RT-Thread Components */ /* RT-Thread Utestcases */ @@ -233,6 +233,10 @@ /* end of STM32 HAL & SDK Drivers */ +/* Infineon HAL Packages */ + +/* end of Infineon HAL Packages */ + /* Kendryte SDK */ /* end of Kendryte SDK */ @@ -319,7 +323,9 @@ /* General Drivers Configuration */ #define BSP_USING_UART -#define RT_USING_UART1 +#define BSP_USING_UART1 +#define BSP_UART1_RX_PINNAME "IIC0_SDA" +#define BSP_UART1_TX_PINNAME "IIC0_SCL" #define UART_IRQ_BASE 30 /* end of General Drivers Configuration */ #define BSP_USING_C906_LITTLE diff --git a/bsp/cvitek/cv18xx_risc-v/.config b/bsp/cvitek/cv18xx_risc-v/.config index a5bec1c11e..7593b94de2 100644 --- a/bsp/cvitek/cv18xx_risc-v/.config +++ b/bsp/cvitek/cv18xx_risc-v/.config @@ -15,7 +15,6 @@ CONFIG_RT_THREAD_PRIORITY_32=y # CONFIG_RT_THREAD_PRIORITY_256 is not set CONFIG_RT_THREAD_PRIORITY_MAX=32 CONFIG_RT_TICK_PER_SECOND=1000 -CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y CONFIG_RT_HOOK_USING_FUNC_PTR=y # CONFIG_RT_USING_HOOKLIST is not set @@ -25,6 +24,8 @@ CONFIG_IDLE_THREAD_STACK_SIZE=8192 CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 CONFIG_RT_TIMER_THREAD_STACK_SIZE=8192 +# CONFIG_RT_USING_TIMER_ALL_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set # # kservice optimization @@ -46,6 +47,7 @@ CONFIG_RT_DEBUGING_COLOR=y CONFIG_RT_DEBUGING_CONTEXT=y # CONFIG_RT_DEBUGING_AUTO_INIT is not set # CONFIG_RT_DEBUGING_PAGE_LEAK is not set +CONFIG_RT_USING_OVERFLOW_CHECK=y # # Inter-Thread communication @@ -170,6 +172,7 @@ CONFIG_RT_USING_DFS_ROMFS=y # Device Drivers # # CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_DEV_BUS is not set CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_UNAMED_PIPE_NUMBER=64 CONFIG_RT_USING_SYSTEM_WORKQUEUE=y @@ -190,6 +193,8 @@ CONFIG_RT_USING_NULL=y CONFIG_RT_USING_ZERO=y CONFIG_RT_USING_RANDOM=y # CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set # CONFIG_RT_USING_PM is not set @@ -210,21 +215,12 @@ CONFIG_RT_MMCSD_MAX_PARTITION=16 # CONFIG_RT_USING_TOUCH is not set # CONFIG_RT_USING_LCD is not set # CONFIG_RT_USING_HWCRYPTO is not set -# CONFIG_RT_USING_PULSE_ENCODER is not set -# CONFIG_RT_USING_INPUT_CAPTURE is not set -# CONFIG_RT_USING_DEV_BUS is not set # CONFIG_RT_USING_WIFI is not set # CONFIG_RT_USING_VIRTIO is not set CONFIG_RT_USING_PIN=y CONFIG_RT_USING_KTIME=y # CONFIG_RT_USING_HWTIMER is not set - -# -# Using USB -# -# CONFIG_RT_USING_USB_HOST is not set -# CONFIG_RT_USING_USB_DEVICE is not set -# end of Using USB +# CONFIG_RT_USING_CHERRYUSB is not set # end of Device Drivers # @@ -393,6 +389,15 @@ CONFIG_RT_USING_ADT_REF=y # end of Utilities # CONFIG_RT_USING_VBUS is not set + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set # end of RT-Thread Components # @@ -420,6 +425,7 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set # # Wi-Fi @@ -524,6 +530,7 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_ZEPHYR_POLLING is not set # CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set # CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set # end of IoT - internet of things # @@ -669,6 +676,8 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set # end of enhanced kernel services +# CONFIG_PKG_USING_AUNITY is not set + # # acceleration: Assembly language or algorithmic acceleration packages # @@ -759,11 +768,27 @@ CONFIG_RT_USING_ADT_REF=y # # STM32 HAL & SDK Drivers # -# CONFIG_PKG_USING_STM32L4XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set # CONFIG_PKG_USING_STM32WB55_SDK is not set # CONFIG_PKG_USING_STM32_SDIO is not set # end of STM32 HAL & SDK Drivers +# +# Infineon HAL Packages +# +# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set +# CONFIG_PKG_USING_INFINEON_CMSIS is not set +# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set +# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set +# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set +# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set +# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set +# CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + # CONFIG_PKG_USING_BLUETRUM_SDK is not set # CONFIG_PKG_USING_EMBARC_BSP is not set # CONFIG_PKG_USING_ESP_IDF is not set @@ -958,6 +983,7 @@ CONFIG_RT_USING_ADT_REF=y # # Signal Processing and Control Algorithm Packages # +# CONFIG_PKG_USING_APID is not set # CONFIG_PKG_USING_FIRE_PID_CURVE is not set # CONFIG_PKG_USING_QPID is not set # CONFIG_PKG_USING_UKAL is not set @@ -1274,12 +1300,14 @@ CONFIG_RT_USING_ADT_REF=y # General Drivers Configuration # CONFIG_BSP_USING_UART=y -CONFIG_RT_USING_UART0=y +CONFIG_BSP_USING_UART0=y +CONFIG_BSP_UART0_RX_PINNAME="UART0_RX" +CONFIG_BSP_UART0_TX_PINNAME="UART0_TX" +# CONFIG_BSP_USING_UART1 is not set +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_UART4 is not set CONFIG_UART_IRQ_BASE=44 -# CONFIG_RT_USING_UART1 is not set -# CONFIG_RT_USING_UART2 is not set -# CONFIG_RT_USING_UART3 is not set -# CONFIG_RT_USING_UART4 is not set # CONFIG_BSP_USING_I2C is not set # CONFIG_BSP_USING_ADC is not set # CONFIG_BSP_USING_SPI is not set diff --git a/bsp/cvitek/cv18xx_risc-v/board/Kconfig b/bsp/cvitek/cv18xx_risc-v/board/Kconfig index 3c3b7daacb..6b3cf19fdd 100755 --- a/bsp/cvitek/cv18xx_risc-v/board/Kconfig +++ b/bsp/cvitek/cv18xx_risc-v/board/Kconfig @@ -6,30 +6,74 @@ menu "General Drivers Configuration" default y if BSP_USING_UART - config RT_USING_UART0 - bool "Enable UART 0" - default y + config BSP_USING_UART0 + bool "Enable UART 0" + default y + + if BSP_USING_UART0 + config BSP_UART0_RX_PINNAME + string "uart0 rx pin name" + default "UART0_RX" + config BSP_UART0_TX_PINNAME + string "uart0 tx pin name" + default "UART0_TX" + endif + + config BSP_USING_UART1 + bool "Enable UART 1" + default n + + if BSP_USING_UART1 + config BSP_UART1_RX_PINNAME + string "uart1 rx pin name" + default "" + config BSP_UART1_TX_PINNAME + string "uart1 tx pin name" + default "" + endif + + config BSP_USING_UART2 + bool "Enable UART 2" + default n + + if BSP_USING_UART2 + config BSP_UART2_RX_PINNAME + string "uart2 rx pin name" + default "" + config BSP_UART2_TX_PINNAME + string "uart2 tx pin name" + default "" + endif + + config BSP_USING_UART3 + bool "Enable UART 3" + default n + + if BSP_USING_UART3 + config BSP_UART3_RX_PINNAME + string "uart3 rx pin name" + default "" + config BSP_UART3_TX_PINNAME + string "uart3 tx pin name" + default "" + endif + + config BSP_USING_UART4 + bool "Enable UART 4" + default n + + if BSP_USING_UART4 + config BSP_UART4_RX_PINNAME + string "uart4 rx pin name" + default "" + config BSP_UART4_TX_PINNAME + string "uart4 tx pin name" + default "" + endif config UART_IRQ_BASE - int - default 44 - - config RT_USING_UART1 - bool "Enable UART 1" - default n - - config RT_USING_UART2 - bool "Enable UART 2" - default n - - config RT_USING_UART3 - bool "Enable UART 3" - default n - - config RT_USING_UART4 - bool "Enable UART 4" - default n - + int + default 44 endif menuconfig BSP_USING_I2C diff --git a/bsp/cvitek/cv18xx_risc-v/rtconfig.h b/bsp/cvitek/cv18xx_risc-v/rtconfig.h index 0574fefe54..d168377aa8 100755 --- a/bsp/cvitek/cv18xx_risc-v/rtconfig.h +++ b/bsp/cvitek/cv18xx_risc-v/rtconfig.h @@ -9,7 +9,6 @@ #define RT_THREAD_PRIORITY_32 #define RT_THREAD_PRIORITY_MAX 32 #define RT_TICK_PER_SECOND 1000 -#define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK @@ -31,6 +30,7 @@ #define RT_DEBUGING_ASSERT #define RT_DEBUGING_COLOR #define RT_DEBUGING_CONTEXT +#define RT_USING_OVERFLOW_CHECK /* Inter-Thread communication */ @@ -135,10 +135,6 @@ #define RT_MMCSD_MAX_PARTITION 16 #define RT_USING_PIN #define RT_USING_KTIME - -/* Using USB */ - -/* end of Using USB */ /* end of Device Drivers */ /* C/C++ and POSIX layer */ @@ -252,6 +248,10 @@ #define RT_USING_ADT_HASHMAP #define RT_USING_ADT_REF /* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ /* end of RT-Thread Components */ /* RT-Thread Utestcases */ @@ -348,6 +348,10 @@ /* end of STM32 HAL & SDK Drivers */ +/* Infineon HAL Packages */ + +/* end of Infineon HAL Packages */ + /* Kendryte SDK */ /* end of Kendryte SDK */ @@ -434,7 +438,9 @@ /* General Drivers Configuration */ #define BSP_USING_UART -#define RT_USING_UART0 +#define BSP_USING_UART0 +#define BSP_UART0_RX_PINNAME "UART0_RX" +#define BSP_UART0_TX_PINNAME "UART0_TX" #define UART_IRQ_BASE 44 /* end of General Drivers Configuration */ #define BSP_USING_CV18XX diff --git a/bsp/cvitek/drivers/drv_uart.c b/bsp/cvitek/drivers/drv_uart.c index ed482b2142..7da298452f 100644 --- a/bsp/cvitek/drivers/drv_uart.c +++ b/bsp/cvitek/drivers/drv_uart.c @@ -13,6 +13,7 @@ #include "board.h" #include "drv_uart.h" +#include "drv_pinmux.h" #define DBG_TAG "DRV.UART" #define DBG_LVL DBG_WARNING @@ -50,19 +51,19 @@ static struct hw_uart_device _uart##no##_device = \ }; \ static struct rt_serial_device _serial##no; -#ifdef RT_USING_UART0 +#ifdef BSP_USING_UART0 BSP_DEFINE_UART_DEVICE(0); #endif -#ifdef RT_USING_UART1 +#ifdef BSP_USING_UART1 BSP_DEFINE_UART_DEVICE(1); #endif -#ifdef RT_USING_UART2 +#ifdef BSP_USING_UART2 BSP_DEFINE_UART_DEVICE(2); #endif -#ifdef RT_USING_UART3 +#ifdef BSP_USING_UART3 BSP_DEFINE_UART_DEVICE(3); #endif @@ -234,6 +235,132 @@ static void rt_hw_uart_isr(int irqno, void *param) } } +#if defined(BOARD_TYPE_MILKV_DUO) || defined(BOARD_TYPE_MILKV_DUO_SPINOR) + +#ifdef BSP_USING_UART0 +static const char *pinname_whitelist_uart0_rx[] = { + "UART0_RX", + NULL, +}; +static const char *pinname_whitelist_uart0_tx[] = { + "UART0_TX", + NULL, +}; +#endif + +#ifdef BSP_USING_UART1 +static const char *pinname_whitelist_uart1_rx[] = { + "IIC0_SDA", + "UART0_RX", + NULL, +}; +static const char *pinname_whitelist_uart1_tx[] = { + "IIC0_SCL", + "UART0_TX", + NULL, +}; +#endif + +#ifdef BSP_USING_UART2 +static const char *pinname_whitelist_uart2_rx[] = { + "IIC0_SDA", + "SD1_D1", + NULL, +}; +static const char *pinname_whitelist_uart2_tx[] = { + "IIC0_SCL", + "SD1_D2", + NULL, +}; +#endif + +#ifdef BSP_USING_UART3 +static const char *pinname_whitelist_uart3_rx[] = { + "SD1_D1", + NULL, +}; +static const char *pinname_whitelist_uart3_tx[] = { + "SD1_D2", + NULL, +}; +#endif + +#ifdef BSP_USING_UART4 +static const char *pinname_whitelist_uart4_rx[] = { + "SD1_GPIO0", + NULL, +}; +static const char *pinname_whitelist_uart4_tx[] = { + "SD1_GPIO1", + NULL, +}; +#endif + +#elif defined(BOARD_TYPE_MILKV_DUO256M) || defined(BOARD_TYPE_MILKV_DUO256M_SPINOR) + +#ifdef BSP_USING_UART0 +static const char *pinname_whitelist_uart0_rx[] = { + "UART0_RX", + NULL, +}; +static const char *pinname_whitelist_uart0_tx[] = { + "UART0_TX", + NULL, +}; +#endif + +#ifdef BSP_USING_UART1 +static const char *pinname_whitelist_uart1_rx[] = { + "IIC0_SDA", + "JTAG_CPU_TCK", + "UART0_RX", + NULL, +}; +static const char *pinname_whitelist_uart1_tx[] = { + "IIC0_SCL", + "JTAG_CPU_TMS", + "UART0_TX", + NULL, +}; +#endif + +#ifdef BSP_USING_UART2 +static const char *pinname_whitelist_uart2_rx[] = { + "IIC0_SDA", + "SD1_D1", + NULL, +}; +static const char *pinname_whitelist_uart2_tx[] = { + "IIC0_SCL", + "SD1_D2", + NULL, +}; +#endif + +#ifdef BSP_USING_UART3 +static const char *pinname_whitelist_uart3_rx[] = { + "SD1_D1", + NULL, +}; +static const char *pinname_whitelist_uart3_tx[] = { + "SD1_D2", + NULL, +}; +#endif + +#ifdef BSP_USING_UART4 +static const char *pinname_whitelist_uart4_rx[] = { + NULL, +}; +static const char *pinname_whitelist_uart4_tx[] = { + NULL, +}; +#endif + +#else + #error "Unsupported board type!" +#endif + int rt_hw_uart_init(void) { struct hw_uart_device* uart; @@ -248,45 +375,45 @@ int rt_hw_uart_init(void) rt_hw_serial_register(&_serial##no, "uart" #no, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); \ rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, &_serial##no, "uart" #no); -#ifdef RT_USING_UART0 - PINMUX_CONFIG(UART0_RX, UART0_RX); - PINMUX_CONFIG(UART0_TX, UART0_TX); +#ifdef BSP_USING_UART0 + pinmux_config(BSP_UART0_RX_PINNAME, UART0_RX, pinname_whitelist_uart0_rx); + pinmux_config(BSP_UART0_TX_PINNAME, UART0_TX, pinname_whitelist_uart0_tx); BSP_INSTALL_UART_DEVICE(0); #if defined(ARCH_ARM) uart->hw_base = (rt_size_t)rt_ioremap((void*)uart->hw_base, 0x10000); #endif /* defined(ARCH_ARM) */ #endif -#ifdef RT_USING_UART1 - PINMUX_CONFIG(IIC0_SDA, UART1_RX); - PINMUX_CONFIG(IIC0_SCL, UART1_TX); +#ifdef BSP_USING_UART1 + pinmux_config(BSP_UART1_RX_PINNAME, UART1_RX, pinname_whitelist_uart1_rx); + pinmux_config(BSP_UART1_TX_PINNAME, UART1_TX, pinname_whitelist_uart1_tx); BSP_INSTALL_UART_DEVICE(1); #if defined(ARCH_ARM) uart->hw_base = (rt_size_t)rt_ioremap((void*)uart->hw_base, 0x10000); #endif /* defined(ARCH_ARM) */ #endif -#ifdef RT_USING_UART2 - PINMUX_CONFIG(SD1_D1, UART2_RX); - PINMUX_CONFIG(SD1_D2, UART2_TX); +#ifdef BSP_USING_UART2 + pinmux_config(BSP_UART2_RX_PINNAME, UART2_RX, pinname_whitelist_uart2_rx); + pinmux_config(BSP_UART2_TX_PINNAME, UART2_TX, pinname_whitelist_uart2_tx); BSP_INSTALL_UART_DEVICE(2); #if defined(ARCH_ARM) uart->hw_base = (rt_size_t)rt_ioremap((void*)uart->hw_base, 0x10000); #endif /* defined(ARCH_ARM) */ #endif -#ifdef RT_USING_UART3 - PINMUX_CONFIG(SD1_D1, UART3_RX); - PINMUX_CONFIG(SD1_D2, UART3_TX); +#ifdef BSP_USING_UART3 + pinmux_config(BSP_UART3_RX_PINNAME, UART3_RX, pinname_whitelist_uart3_rx); + pinmux_config(BSP_UART3_TX_PINNAME, UART3_TX, pinname_whitelist_uart3_tx); BSP_INSTALL_UART_DEVICE(3); #if defined(ARCH_ARM) uart->hw_base = (rt_size_t)rt_ioremap((void*)uart->hw_base, 0x10000); #endif /* defined(ARCH_ARM) */ #endif -#ifdef RT_USING_UART4 - PINMUX_CONFIG(SD1_GP0, UART4_RX); - PINMUX_CONFIG(SD1_GP1, UART4_TX); +#ifdef BSP_USING_UART4 + pinmux_config(BSP_UART4_RX_PINNAME, UART4_RX, pinname_whitelist_uart4_rx); + pinmux_config(BSP_UART4_TX_PINNAME, UART4_TX, pinname_whitelist_uart4_tx); BSP_INSTALL_UART_DEVICE(4); #if defined(ARCH_ARM) uart->hw_base = (rt_size_t)rt_ioremap((void*)uart->hw_base, 0x10000); From 51825a5b5cd32b445d0eba4beb421ae920d20c77 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Tue, 28 May 2024 17:47:48 +0800 Subject: [PATCH 09/48] bsp:cvitek: add pinmux for pwm Board level pin available info is summarized and list here for memo: Duo: NAME PWM CV1800B/GPIO __ ---- --- ------------ --------------------- PWM-1 GP9 PWM4 PWR_GPIO[18] SD1_D3__PWM_4 GP12 PWM4 XGPIOA[16] UART0_TX__PWM_4 GP4 PWM5 PWR_GPIO[19] SD1_D2__PWM_5 GP13 PWM5 XGPIOA[17] UART0_RX__PWM_5 GP5 PWM6 PWR_GPIO[20] SD1_D1__PWM_6 GP8 PMW7 PWR_GPIO[21] SD1_D0__PWM_7 PWM-2 GP7 PWM8 PWR_GPIO[22] SD1_CMD__PWM_8 GP6 PWM9 PWR_GPIO[23] SD1_CLK__PWM_9 GP2 PWM10 PWR_GPIO[26] SD1_GPIO1__PWM_10 GP3 PWM11 PWR_GPIO[25] SD1_GPIO0__PWM_11 Duo256: NAME PWM CV1800B/GPIO __ ---- --- ------------ --------------------- PWM-1 GP9 PWM4 PWR_GPIO[18] SD1_D3__PWM_4 GP12 PWM4 XGPIOA[16] UART0_TX__PWM_4 GP4 PWM5 PWR_GPIO[19] SD1_D2__PWM_5 GP13 PWM5 XGPIOA[17] UART0_RX__PWM_5 GP3 PWM6 XGPIOA[18] JTAG_CPU_TCK__PWM_6 GP5 PWM6 PWR_GPIO[20] SD1_D1__PWM_6 GP2 PWM7 XGPIOA[19] JTAG_CPU_TMS__PWM_7 GP8 PMW7 PWR_GPIO[21] SD1_D0__PWM_7 PWM-2 GP7 PWM8 PWR_GPIO[22] SD1_CMD__PWM_8 GP6 PWM9 PWR_GPIO[23] SD1_CLK__PWM_9 GP10 PWM10 XGPIOC[14] PAD_MIPI_TXM1__PWM_10 GP11 PWM11 XGPIOC[15] PAD_MIPI_TXP1__PWM_11 Signed-off-by: Chen Wang --- bsp/cvitek/c906_little/board/Kconfig | 76 ++++++++-- bsp/cvitek/cv18xx_risc-v/board/Kconfig | 76 ++++++++-- bsp/cvitek/drivers/drv_pwm.c | 185 +++++++++++++++++++++++++ 3 files changed, 321 insertions(+), 16 deletions(-) diff --git a/bsp/cvitek/c906_little/board/Kconfig b/bsp/cvitek/c906_little/board/Kconfig index 6b7d6f91c5..620f4039ff 100755 --- a/bsp/cvitek/c906_little/board/Kconfig +++ b/bsp/cvitek/c906_little/board/Kconfig @@ -190,20 +190,80 @@ menu "General Drivers Configuration" if BSP_USING_PWM config BSP_USING_PWM0 - bool "Enable PWM 0" - default n + bool "Enable PWM 0" + default n + + if BSP_USING_PWM0 + config BSP_PWM0_0_PINNAME + string "pwm[0] pin name" + default "" + config BSP_PWM0_1_PINNAME + string "pwm[1] pin name" + default "" + config BSP_PWM0_2_PINNAME + string "pwm[2] pin name" + default "" + config BSP_PWM0_3_PINNAME + string "pwm[3] pin name" + default "" + endif config BSP_USING_PWM1 - bool "Enable PWM 1" - default n + bool "Enable PWM 1" + default n + + if BSP_USING_PWM1 + config BSP_PWM1_4_PINNAME + string "pwm[4] pin name" + default "" + config BSP_PWM1_5_PINNAME + string "pwm[5] pin name" + default "" + config BSP_PWM1_6_PINNAME + string "pwm[6] pin name" + default "" + config BSP_PWM1_7_PINNAME + string "pwm[7] pin name" + default "" + endif config BSP_USING_PWM2 - bool "Enable PWM 2" - default n + bool "Enable PWM 2" + default n + + if BSP_USING_PWM2 + config BSP_PWM2_8_PINNAME + string "pwm[8] pin name" + default "" + config BSP_PWM2_9_PINNAME + string "pwm[9] pin name" + default "" + config BSP_PWM2_10_PINNAME + string "pwm[10] pin name" + default "" + config BSP_PWM2_11_PINNAME + string "pwm[11] pin name" + default "" + endif config BSP_USING_PWM3 - bool "Enable PWM 3" - default n + bool "Enable PWM 3" + default n + + if BSP_USING_PWM3 + config BSP_PWM3_12_PINNAME + string "pwm[12] pin name" + default "" + config BSP_PWM3_13_PINNAME + string "pwm[13] pin name" + default "" + config BSP_PWM3_14_PINNAME + string "pwm[14] pin name" + default "" + config BSP_PWM3_15_PINNAME + string "pwm[15] pin name" + default "" + endif endif config BSP_USING_RTC diff --git a/bsp/cvitek/cv18xx_risc-v/board/Kconfig b/bsp/cvitek/cv18xx_risc-v/board/Kconfig index 6b3cf19fdd..85426b7418 100755 --- a/bsp/cvitek/cv18xx_risc-v/board/Kconfig +++ b/bsp/cvitek/cv18xx_risc-v/board/Kconfig @@ -190,20 +190,80 @@ menu "General Drivers Configuration" if BSP_USING_PWM config BSP_USING_PWM0 - bool "Enable PWM 0" - default n + bool "Enable PWM 0" + default n + + if BSP_USING_PWM0 + config BSP_PWM0_0_PINNAME + string "pwm[0] pin name" + default "" + config BSP_PWM0_1_PINNAME + string "pwm[1] pin name" + default "" + config BSP_PWM0_2_PINNAME + string "pwm[2] pin name" + default "" + config BSP_PWM0_3_PINNAME + string "pwm[3] pin name" + default "" + endif config BSP_USING_PWM1 - bool "Enable PWM 1" - default n + bool "Enable PWM 1" + default n + + if BSP_USING_PWM1 + config BSP_PWM1_4_PINNAME + string "pwm[4] pin name" + default "" + config BSP_PWM1_5_PINNAME + string "pwm[5] pin name" + default "" + config BSP_PWM1_6_PINNAME + string "pwm[6] pin name" + default "" + config BSP_PWM1_7_PINNAME + string "pwm[7] pin name" + default "" + endif config BSP_USING_PWM2 - bool "Enable PWM 2" - default n + bool "Enable PWM 2" + default n + + if BSP_USING_PWM2 + config BSP_PWM2_8_PINNAME + string "pwm[8] pin name" + default "" + config BSP_PWM2_9_PINNAME + string "pwm[9] pin name" + default "" + config BSP_PWM2_10_PINNAME + string "pwm[10] pin name" + default "" + config BSP_PWM2_11_PINNAME + string "pwm[11] pin name" + default "" + endif config BSP_USING_PWM3 - bool "Enable PWM 3" - default n + bool "Enable PWM 3" + default n + + if BSP_USING_PWM3 + config BSP_PWM3_12_PINNAME + string "pwm[12] pin name" + default "" + config BSP_PWM3_13_PINNAME + string "pwm[13] pin name" + default "" + config BSP_PWM3_14_PINNAME + string "pwm[14] pin name" + default "" + config BSP_PWM3_15_PINNAME + string "pwm[15] pin name" + default "" + endif endif config BSP_USING_RTC diff --git a/bsp/cvitek/drivers/drv_pwm.c b/bsp/cvitek/drivers/drv_pwm.c index e79a152119..a52bc6af7a 100644 --- a/bsp/cvitek/drivers/drv_pwm.c +++ b/bsp/cvitek/drivers/drv_pwm.c @@ -10,6 +10,7 @@ #include #include #include "drv_pwm.h" +#include "drv_pinmux.h" #define DBG_LEVEL DBG_LOG #include @@ -134,11 +135,195 @@ static struct cvi_pwm_dev cvi_pwm[] = #endif }; + +#if defined(BOARD_TYPE_MILKV_DUO) || defined(BOARD_TYPE_MILKV_DUO_SPINOR) + +#ifdef BSP_USING_PWM0 +static const char *pinname_whitelist_pwm0[] = { + NULL, +}; +static const char *pinname_whitelist_pwm1[] = { + NULL, +}; +static const char *pinname_whitelist_pwm2[] = { + NULL, +}; +static const char *pinname_whitelist_pwm3[] = { + NULL, +}; +#endif + +#ifdef BSP_USING_PWM1 +static const char *pinname_whitelist_pwm4[] = { + "SD1_D3", + "UART0_TX", + NULL, +}; +static const char *pinname_whitelist_pwm5[] = { + "SD1_D2", + "UART0_RX", + NULL, +}; +static const char *pinname_whitelist_pwm6[] = { + "SD1_D1", + NULL, +}; +static const char *pinname_whitelist_pwm7[] = { + "SD1_D0", + NULL, +}; +#endif + +#ifdef BSP_USING_PWM2 +static const char *pinname_whitelist_pwm8[] = { + "SD1_CMD", + NULL, +}; +static const char *pinname_whitelist_pwm9[] = { + "SD1_CLK", + NULL, +}; +static const char *pinname_whitelist_pwm10[] = { + "SD1_GPIO1", + NULL, +}; +static const char *pinname_whitelist_pwm11[] = { + "SD1_GPIO0", + NULL, +}; +#endif + +#ifdef BSP_USING_PWM3 +static const char *pinname_whitelist_pwm12[] = { + NULL, +}; +static const char *pinname_whitelist_pwm13[] = { + NULL, +}; +static const char *pinname_whitelist_pwm14[] = { + NULL, +}; +static const char *pinname_whitelist_pwm15[] = { + NULL, +}; +#endif + +#elif defined(BOARD_TYPE_MILKV_DUO256M) || defined(BOARD_TYPE_MILKV_DUO256M_SPINOR) + +#ifdef BSP_USING_PWM0 +static const char *pinname_whitelist_pwm0[] = { + NULL, +}; +static const char *pinname_whitelist_pwm1[] = { + NULL, +}; +static const char *pinname_whitelist_pwm2[] = { + NULL, +}; +static const char *pinname_whitelist_pwm3[] = { + NULL, +}; +#endif + +#ifdef BSP_USING_PWM1 +static const char *pinname_whitelist_pwm4[] = { + "SD1_D3", + "UART0_TX", + NULL, +}; +static const char *pinname_whitelist_pwm5[] = { + "SD1_D2", + "UART0_RX", + NULL, +}; +static const char *pinname_whitelist_pwm6[] = { + "JTAG_CPU_TCK", + "SD1_D1", + NULL, +}; +static const char *pinname_whitelist_pwm7[] = { + "JTAG_CPU_TMS", + "SD1_D0", + NULL, +}; +#endif + +#ifdef BSP_USING_PWM2 +static const char *pinname_whitelist_pwm8[] = { + "SD1_CMD", + NULL, +}; +static const char *pinname_whitelist_pwm9[] = { + "SD1_CLK", + NULL, +}; +static const char *pinname_whitelist_pwm10[] = { + "PAD_MIPI_TXM1", + NULL, +}; +static const char *pinname_whitelist_pwm11[] = { + "PAD_MIPI_TXP1", + NULL, +}; +#endif + +#ifdef BSP_USING_PWM3 +static const char *pinname_whitelist_pwm12[] = { + NULL, +}; +static const char *pinname_whitelist_pwm13[] = { + NULL, +}; +static const char *pinname_whitelist_pwm14[] = { + NULL, +}; +static const char *pinname_whitelist_pwm15[] = { + NULL, +}; +#endif + +#else + #error "Unsupported board type!" +#endif + +static void rt_hw_pwm_pinmux_config() +{ +#ifdef BSP_USING_PWM0 + pinmux_config(BSP_PWM0_0_PINNAME, PWM_0, pinname_whitelist_pwm0); + pinmux_config(BSP_PWM0_1_PINNAME, PWM_1, pinname_whitelist_pwm1); + pinmux_config(BSP_PWM0_2_PINNAME, PWM_2, pinname_whitelist_pwm2); + pinmux_config(BSP_PWM0_3_PINNAME, PWM_3, pinname_whitelist_pwm3); +#endif /* BSP_USING_PWM0 */ + +#ifdef BSP_USING_PWM1 + pinmux_config(BSP_PWM1_4_PINNAME, PWM_4, pinname_whitelist_pwm4); + pinmux_config(BSP_PWM1_5_PINNAME, PWM_5, pinname_whitelist_pwm5); + pinmux_config(BSP_PWM1_6_PINNAME, PWM_6, pinname_whitelist_pwm6); + pinmux_config(BSP_PWM1_7_PINNAME, PWM_7, pinname_whitelist_pwm7); +#endif /* BSP_USING_PWM1 */ + +#ifdef BSP_USING_PWM2 + pinmux_config(BSP_PWM2_8_PINNAME, PWM_8, pinname_whitelist_pwm8); + pinmux_config(BSP_PWM2_9_PINNAME, PWM_9, pinname_whitelist_pwm9); + pinmux_config(BSP_PWM2_10_PINNAME, PWM_10, pinname_whitelist_pwm10); + pinmux_config(BSP_PWM2_11_PINNAME, PWM_11, pinname_whitelist_pwm11); +#endif /* BSP_USING_PWM2 */ + +#ifdef BSP_USING_PWM3 + pinmux_config(BSP_PWM3_12_PINNAME, PWM_12, pinname_whitelist_pwm12); + pinmux_config(BSP_PWM3_13_PINNAME, PWM_13, pinname_whitelist_pwm13); + pinmux_config(BSP_PWM3_14_PINNAME, PWM_14, pinname_whitelist_pwm14); + pinmux_config(BSP_PWM3_15_PINNAME, PWM_15, pinname_whitelist_pwm15); +#endif /* BSP_USING_PWM3 */ +} + int rt_hw_pwm_init(void) { int result = RT_EOK; uint8_t i; + rt_hw_pwm_pinmux_config(); + for (i = 0; i < sizeof(cvi_pwm) / sizeof(cvi_pwm[0]); i++) { result = rt_device_pwm_register(&cvi_pwm[i].device, cvi_pwm[i].name, &cvi_pwm_ops, &cvi_pwm[i]); From 2c85bcb463a37ae0a1ec60281e4a23945eb046d5 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Tue, 28 May 2024 18:45:53 +0800 Subject: [PATCH 10/48] bsp:cvitek: add pinmux for spi Board level pin available info: duo & duo256: NAME SPI CV1800B/GPIO __ ---- --- ------------ --------------------- GP6 SPI2_SCK PWR_GPIO[23] SD1_CLK__SPI2_SCK GP7 SPI2_SDO PWR_GPIO[22] SD1_CMD__SPI2_SDO GP8 SPI2_SDI PWR_GPIO[21] SD1_D0__SPI2_SDI GP9 SPI2_CS_X PWR_GPIO[18] SD1_D3__SPI2_CS_X Signed-off-by: Chen Wang --- bsp/cvitek/c906_little/board/Kconfig | 78 +++++++++++++++++++ bsp/cvitek/cv18xx_risc-v/board/Kconfig | 78 +++++++++++++++++++ bsp/cvitek/drivers/drv_spi.c | 104 +++++++++++++++++++++++++ 3 files changed, 260 insertions(+) diff --git a/bsp/cvitek/c906_little/board/Kconfig b/bsp/cvitek/c906_little/board/Kconfig index 620f4039ff..95c97e725b 100755 --- a/bsp/cvitek/c906_little/board/Kconfig +++ b/bsp/cvitek/c906_little/board/Kconfig @@ -164,6 +164,84 @@ menu "General Drivers Configuration" select RT_USING_SPI default n + if BSP_USING_SPI + config BSP_USING_SPI0 + bool "Enable SPI 0" + default n + + if BSP_USING_SPI0 + config BSP_SPI0_SCK_PINNAME + string "spi0 sck pin name" + default "" + config BSP_SPI0_SDO_PINNAME + string "spi0 sdo pin name" + default "" + config BSP_SPI0_SDI_PINNAME + string "spi0 sdi pin name" + default "" + config BSP_SPI0_CS_PINNAME + string "spi0 cs pin name" + default "" + endif + + config BSP_USING_SPI1 + bool "Enable SPI 1" + default n + + if BSP_USING_SPI1 + config BSP_SPI1_SCK_PINNAME + string "spi1 sck pin name" + default "" + config BSP_SPI1_SDO_PINNAME + string "spi1 sdo pin name" + default "" + config BSP_SPI1_SDI_PINNAME + string "spi1 sdi pin name" + default "" + config BSP_SPI1_CS_PINNAME + string "spi1 cs pin name" + default "" + endif + + config BSP_USING_SPI2 + bool "Enable SPI 2" + default n + + if BSP_USING_SPI2 + config BSP_SPI2_SCK_PINNAME + string "spi2 sck pin name" + default "" + config BSP_SPI2_SDO_PINNAME + string "spi2 sdo pin name" + default "" + config BSP_SPI2_SDI_PINNAME + string "spi2 sdi pin name" + default "" + config BSP_SPI2_CS_PINNAME + string "spi2 cs pin name" + default "" + endif + + config BSP_USING_SPI3 + bool "Enable SPI 3" + default n + + if BSP_USING_SPI3 + config BSP_SPI3_SCK_PINNAME + string "spi3 sck pin name" + default "" + config BSP_SPI3_SDO_PINNAME + string "spi3 sdo pin name" + default "" + config BSP_SPI3_SDI_PINNAME + string "spi3 sdi pin name" + default "" + config BSP_SPI3_CS_PINNAME + string "spi3 cs pin name" + default "" + endif + endif + menuconfig BSP_USING_WDT bool "Enable Watchdog Timer" select RT_USING_WDT diff --git a/bsp/cvitek/cv18xx_risc-v/board/Kconfig b/bsp/cvitek/cv18xx_risc-v/board/Kconfig index 85426b7418..6ed5c54e74 100755 --- a/bsp/cvitek/cv18xx_risc-v/board/Kconfig +++ b/bsp/cvitek/cv18xx_risc-v/board/Kconfig @@ -164,6 +164,84 @@ menu "General Drivers Configuration" select RT_USING_SPI default n + if BSP_USING_SPI + config BSP_USING_SPI0 + bool "Enable SPI 0" + default n + + if BSP_USING_SPI0 + config BSP_SPI0_SCK_PINNAME + string "spi0 sck pin name" + default "" + config BSP_SPI0_SDO_PINNAME + string "spi0 sdo pin name" + default "" + config BSP_SPI0_SDI_PINNAME + string "spi0 sdi pin name" + default "" + config BSP_SPI0_CS_PINNAME + string "spi0 cs pin name" + default "" + endif + + config BSP_USING_SPI1 + bool "Enable SPI 1" + default n + + if BSP_USING_SPI1 + config BSP_SPI1_SCK_PINNAME + string "spi1 sck pin name" + default "" + config BSP_SPI1_SDO_PINNAME + string "spi1 sdo pin name" + default "" + config BSP_SPI1_SDI_PINNAME + string "spi1 sdi pin name" + default "" + config BSP_SPI1_CS_PINNAME + string "spi1 cs pin name" + default "" + endif + + config BSP_USING_SPI2 + bool "Enable SPI 2" + default n + + if BSP_USING_SPI2 + config BSP_SPI2_SCK_PINNAME + string "spi2 sck pin name" + default "" + config BSP_SPI2_SDO_PINNAME + string "spi2 sdo pin name" + default "" + config BSP_SPI2_SDI_PINNAME + string "spi2 sdi pin name" + default "" + config BSP_SPI2_CS_PINNAME + string "spi2 cs pin name" + default "" + endif + + config BSP_USING_SPI3 + bool "Enable SPI 3" + default n + + if BSP_USING_SPI3 + config BSP_SPI3_SCK_PINNAME + string "spi3 sck pin name" + default "" + config BSP_SPI3_SDO_PINNAME + string "spi3 sdo pin name" + default "" + config BSP_SPI3_SDI_PINNAME + string "spi3 sdi pin name" + default "" + config BSP_SPI3_CS_PINNAME + string "spi3 cs pin name" + default "" + endif + endif + menuconfig BSP_USING_WDT bool "Enable Watchdog Timer" select RT_USING_WDT diff --git a/bsp/cvitek/drivers/drv_spi.c b/bsp/cvitek/drivers/drv_spi.c index 82a5b31b3d..3e88af06f6 100644 --- a/bsp/cvitek/drivers/drv_spi.c +++ b/bsp/cvitek/drivers/drv_spi.c @@ -9,6 +9,7 @@ */ #include "drv_spi.h" +#include "drv_pinmux.h" #define DBG_TAG "drv.spi" #define DBG_LVL DBG_INFO @@ -209,11 +210,114 @@ const static struct rt_spi_ops drv_spi_ops = spixfer, }; +#if defined(BOARD_TYPE_MILKV_DUO) || defined(BOARD_TYPE_MILKV_DUO_SPINOR) || defined(BOARD_TYPE_MILKV_DUO256M) || defined(BOARD_TYPE_MILKV_DUO256M_SPINOR) + +#ifdef BSP_USING_SPI0 +static const char *pinname_whitelist_spi0_sck[] = { + NULL, +}; +static const char *pinname_whitelist_spi0_sdo[] = { + NULL, +}; +static const char *pinname_whitelist_spi0_sdi[] = { + NULL, +}; +static const char *pinname_whitelist_spi0_cs[] = { + NULL, +}; +#endif + +#ifdef BSP_USING_SPI1 +static const char *pinname_whitelist_spi1_sck[] = { + NULL, +}; +static const char *pinname_whitelist_spi1_sdo[] = { + NULL, +}; +static const char *pinname_whitelist_spi1_sdi[] = { + NULL, +}; +static const char *pinname_whitelist_spi1_cs[] = { + NULL, +}; +#endif + +#ifdef BSP_USING_SPI2 +static const char *pinname_whitelist_spi2_sck[] = { + "SD1_CLK", + NULL, +}; +static const char *pinname_whitelist_spi2_sdo[] = { + "SD1_CMD", + NULL, +}; +static const char *pinname_whitelist_spi2_sdi[] = { + "SD1_D0", + NULL, +}; +static const char *pinname_whitelist_spi2_cs[] = { + "SD1_D3", + NULL, +}; +#endif + +#ifdef BSP_USING_SPI3 +static const char *pinname_whitelist_spi3_sck[] = { + NULL, +}; +static const char *pinname_whitelist_spi3_sdo[] = { + NULL, +}; +static const char *pinname_whitelist_spi3_sdi[] = { + NULL, +}; +static const char *pinname_whitelist_spi3_cs[] = { + NULL, +}; +#endif + +#else + #error "Unsupported board type!" +#endif + +static void rt_hw_spi_pinmux_config() +{ +#ifdef BSP_USING_SPI0 + pinmux_config(BSP_SPI0_SCK_PINNAME, SPI0_SCK, pinname_whitelist_spi0_sck); + pinmux_config(BSP_SPI0_SDO_PINNAME, SPI0_SDO, pinname_whitelist_spi0_sdo); + pinmux_config(BSP_SPI0_SDI_PINNAME, SPI0_SDI, pinname_whitelist_spi0_sdi); + pinmux_config(BSP_SPI0_CS_PINNAME, SPI0_CS_X, pinname_whitelist_spi0_cs); +#endif /* BSP_USING_SPI0 */ + +#ifdef BSP_USING_SPI1 + pinmux_config(BSP_SPI1_SCK_PINNAME, SPI1_SCK, pinname_whitelist_spi1_sck); + pinmux_config(BSP_SPI1_SDO_PINNAME, SPI1_SDO, pinname_whitelist_spi1_sdo); + pinmux_config(BSP_SPI1_SDI_PINNAME, SPI1_SDI, pinname_whitelist_spi1_sdi); + pinmux_config(BSP_SPI1_CS_PINNAME, SPI1_CS_X, pinname_whitelist_spi1_cs); +#endif /* BSP_USING_SPI1 */ + +#ifdef BSP_USING_SPI2 + pinmux_config(BSP_SPI2_SCK_PINNAME, SPI2_SCK, pinname_whitelist_spi2_sck); + pinmux_config(BSP_SPI2_SDO_PINNAME, SPI2_SDO, pinname_whitelist_spi2_sdo); + pinmux_config(BSP_SPI2_SDI_PINNAME, SPI2_SDI, pinname_whitelist_spi2_sdi); + pinmux_config(BSP_SPI2_CS_PINNAME, SPI2_CS_X, pinname_whitelist_spi2_cs); +#endif /* BSP_USING_SPI2 */ + +#ifdef BSP_USING_SPI3 + pinmux_config(BSP_SPI3_SCK_PINNAME, SPI3_SCK, pinname_whitelist_spi3_sck); + pinmux_config(BSP_SPI3_SDO_PINNAME, SPI3_SDO, pinname_whitelist_spi3_sdo); + pinmux_config(BSP_SPI3_SDI_PINNAME, SPI3_SDI, pinname_whitelist_spi3_sdi); + pinmux_config(BSP_SPI3_CS_PINNAME, SPI3_CS_X, pinname_whitelist_spi3_cs); +#endif /* BSP_USING_SPI3 */ +} + int rt_hw_spi_init(void) { rt_err_t ret = RT_EOK; struct spi_regs *reg = NULL; + rt_hw_spi_pinmux_config(); + for (rt_size_t i = 0; i < sizeof(cv1800_spi_obj) / sizeof(struct cv1800_spi); i++) { /* set reg base addr */ reg = get_spi_base(cv1800_spi_obj[i].spi_id); From d8294de64027696437bc4947c0eec28a3b4a17c4 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Tue, 4 Jun 2024 11:18:00 +0800 Subject: [PATCH 11/48] bsp:cvitek: add pinmux for adc Signed-off-by: Chen Wang --- bsp/cvitek/c906_little/board/Kconfig | 36 +++++++++- bsp/cvitek/cv18xx_risc-v/board/Kconfig | 36 +++++++++- bsp/cvitek/drivers/drv_adc.c | 92 ++++++++++++++++++++++++++ 3 files changed, 162 insertions(+), 2 deletions(-) diff --git a/bsp/cvitek/c906_little/board/Kconfig b/bsp/cvitek/c906_little/board/Kconfig index 95c97e725b..2a2422537e 100755 --- a/bsp/cvitek/c906_little/board/Kconfig +++ b/bsp/cvitek/c906_little/board/Kconfig @@ -154,11 +154,45 @@ menu "General Drivers Configuration" default 32 endif - config BSP_USING_ADC + menuconfig BSP_USING_ADC bool "Using ADC" select RT_USING_ADC default n + if BSP_USING_ADC + config BSP_USING_ADC_ACTIVE + bool "Enable ADC Controller in Active Domain" + default n + + if BSP_USING_ADC_ACTIVE + config BSP_ACTIVE_ADC1_PINNAME + string "Pin name for VIN1 in Active Domain" + default "" + config BSP_ACTIVE_ADC2_PINNAME + string "Pin name for VIN2 in Active Domain" + default "" + config BSP_ACTIVE_ADC3_PINNAME + string "Pin name for VIN3 in Active Domain" + default "" + endif + + config BSP_USING_ADC_NODIE + bool "Enable ADC Controller in No-die Domain" + default n + + if BSP_USING_ADC_NODIE + config BSP_NODIE_ADC1_PINNAME + string "Pin name for VIN1 in No-die Domain" + default "" + config BSP_NODIE_ADC2_PINNAME + string "Pin name for VIN2 in No-die Domain" + default "" + config BSP_NODIE_ADC3_PINNAME + string "Pin name for VIN3 in No-die Domain" + default "" + endif + endif + config BSP_USING_SPI bool "Using SPI" select RT_USING_SPI diff --git a/bsp/cvitek/cv18xx_risc-v/board/Kconfig b/bsp/cvitek/cv18xx_risc-v/board/Kconfig index 6ed5c54e74..93ce4221c5 100755 --- a/bsp/cvitek/cv18xx_risc-v/board/Kconfig +++ b/bsp/cvitek/cv18xx_risc-v/board/Kconfig @@ -154,11 +154,45 @@ menu "General Drivers Configuration" default 49 endif - config BSP_USING_ADC + menuconfig BSP_USING_ADC bool "Using ADC" select RT_USING_ADC default n + if BSP_USING_ADC + config BSP_USING_ADC_ACTIVE + bool "Enable ADC Controller in Active Domain" + default n + + if BSP_USING_ADC_ACTIVE + config BSP_ACTIVE_ADC1_PINNAME + string "Pin name for VIN1 in Active Domain" + default "" + config BSP_ACTIVE_ADC2_PINNAME + string "Pin name for VIN2 in Active Domain" + default "" + config BSP_ACTIVE_ADC3_PINNAME + string "Pin name for VIN3 in Active Domain" + default "" + endif + + config BSP_USING_ADC_NODIE + bool "Enable ADC Controller in No-die Domain" + default n + + if BSP_USING_ADC_NODIE + config BSP_NODIE_ADC1_PINNAME + string "Pin name for VIN1 in No-die Domain" + default "" + config BSP_NODIE_ADC2_PINNAME + string "Pin name for VIN2 in No-die Domain" + default "" + config BSP_NODIE_ADC3_PINNAME + string "Pin name for VIN3 in No-die Domain" + default "" + endif + endif + config BSP_USING_SPI bool "Using SPI" select RT_USING_SPI diff --git a/bsp/cvitek/drivers/drv_adc.c b/bsp/cvitek/drivers/drv_adc.c index 242d2216eb..f5f179fed1 100644 --- a/bsp/cvitek/drivers/drv_adc.c +++ b/bsp/cvitek/drivers/drv_adc.c @@ -10,6 +10,7 @@ #include #include #include "drv_adc.h" +#include "drv_pinmux.h" #define DBG_LEVEL DBG_LOG #include @@ -100,10 +101,101 @@ static const struct rt_adc_ops _adc_ops = .convert = _adc_convert, }; + +#if defined(BOARD_TYPE_MILKV_DUO) || defined(BOARD_TYPE_MILKV_DUO_SPINOR) + +/* + * cv180xb supports + * - adc1 & adc2 for active domain + * - adc3 for no-die domain + * + * FIXME: currnet adc driver only support adc1 in active domain + */ +#ifdef BSP_USING_ADC_ACTIVE +static const char *pinname_whitelist_adc1_active[] = { + "ADC1", + NULL, +}; +static const char *pinname_whitelist_adc2_active[] = { + NULL, +}; +static const char *pinname_whitelist_adc3_active[] = { + NULL, +}; +#endif + +#ifdef BSP_USING_ADC_NODIE +static const char *pinname_whitelist_adc1_nodie[] = { + NULL, +}; +static const char *pinname_whitelist_adc2_nodie[] = { + NULL, +}; +static const char *pinname_whitelist_adc3_nodie[] = { + NULL, +}; +#endif + +#elif defined(BOARD_TYPE_MILKV_DUO256M) || defined(BOARD_TYPE_MILKV_DUO256M_SPINOR) + +/* + * sg2002 supports + * - adc1 for active domain + * - adc1/adc2/adc3 for no-die domain + * + * FIXME: currnet adc driver only support adc1 in active domain + */ + +#ifdef BSP_USING_ADC_ACTIVE +static const char *pinname_whitelist_adc1_active[] = { + "ADC1", + NULL, +}; +static const char *pinname_whitelist_adc2_active[] = { + NULL, +}; +static const char *pinname_whitelist_adc3_active[] = { + NULL, +}; +#endif + +#ifdef BSP_USING_ADC_NODIE +static const char *pinname_whitelist_adc1_nodie[] = { + NULL, +}; +static const char *pinname_whitelist_adc2_nodie[] = { + NULL, +}; +static const char *pinname_whitelist_adc3_nodie[] = { + NULL, +}; +#endif + +#else + #error "Unsupported board type!" +#endif + +static void rt_hw_adc_pinmux_config() +{ +#ifdef BSP_USING_ADC_ACTIVE + pinmux_config(BSP_ACTIVE_ADC1_PINNAME, XGPIOB_3, pinname_whitelist_adc1_active); + pinmux_config(BSP_ACTIVE_ADC2_PINNAME, XGPIOB_6, pinname_whitelist_adc2_active); + /* cv1800b & sg2002 don't support ADC3 either in active domain */ +#endif + +#ifdef BSP_USING_ADC_NODIE + pinmux_config(BSP_NODIE_ADC1_PINNAME, PWR_GPIO_2, pinname_whitelist_adc1_nodie); + pinmux_config(BSP_NODIE_ADC2_PINNAME, PWR_GPIO_1, pinname_whitelist_adc2_nodie); + pinmux_config(BSP_NODIE_ADC3_PINNAME, PWR_VBAT_DET, pinname_whitelist_adc3_nodie); +#endif +} + int rt_hw_adc_init(void) { rt_uint8_t i; + rt_hw_adc_pinmux_config(); + for (i = 0; i < sizeof(adc_dev_config) / sizeof(adc_dev_config[0]); i++) { cvi_do_calibration(adc_dev_config[i].base); From 1d78d11567bc2187d10ca94e63c39cc95ff1195d Mon Sep 17 00:00:00 2001 From: Shell Date: Tue, 16 Jul 2024 20:38:55 +0800 Subject: [PATCH 12/48] [smart] feat: add unmap for null mapper (#9186) Do unmap before shrink so we don't see mapped entry on page table insertion, which is not acceptable for riscv implementation of architecture porting. Changes: - add un-mapping of pte on `_null_shrink()` Signed-off-by: Shell --- components/lwp/lwp_user_mm.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/components/lwp/lwp_user_mm.c b/components/lwp/lwp_user_mm.c index 01640d5a07..18f10e176f 100644 --- a/components/lwp/lwp_user_mm.c +++ b/components/lwp/lwp_user_mm.c @@ -70,11 +70,29 @@ static void _null_page_fault(struct rt_varea *varea, static rt_err_t _null_shrink(rt_varea_t varea, void *new_start, rt_size_t size) { + char *varea_start = varea->start; + void *rm_start; + void *rm_end; + + if (varea_start == (char *)new_start) + { + rm_start = varea_start + size; + rm_end = varea_start + varea->size; + } + else /* if (varea_start < (char *)new_start) */ + { + RT_ASSERT(varea_start < (char *)new_start); + rm_start = varea_start; + rm_end = new_start; + } + + rt_varea_unmap_range(varea, rm_start, rm_end - rm_start); return RT_EOK; } static rt_err_t _null_split(struct rt_varea *existed, void *unmap_start, rt_size_t unmap_len, struct rt_varea *subset) { + rt_varea_unmap_range(existed, unmap_start, unmap_len); return RT_EOK; } From dda79ad6bcde7e19ad88e89d5bda19e8b52dcc2c Mon Sep 17 00:00:00 2001 From: flyingcys Date: Tue, 4 Jun 2024 08:01:42 +0800 Subject: [PATCH 13/48] bsp: cvitek: re-wrote i2c driver Optimize the original i2c driver code. Signed-off-by: flyingcys Reviewed-by: Chen Wang --- bsp/cvitek/drivers/drv_hw_i2c.c | 690 ++++++++++++------------- bsp/cvitek/drivers/drv_hw_i2c.h | 865 +++++++++++++++++++++++++------- 2 files changed, 992 insertions(+), 563 deletions(-) diff --git a/bsp/cvitek/drivers/drv_hw_i2c.c b/bsp/cvitek/drivers/drv_hw_i2c.c index 6f2fd06b40..6044f935b6 100644 --- a/bsp/cvitek/drivers/drv_hw_i2c.c +++ b/bsp/cvitek/drivers/drv_hw_i2c.c @@ -1,11 +1,11 @@ /* - * Copyright (c) 2006-2023, RT-Thread Development Team + * Copyright (c) 2006-2024, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - *2024-02-14 ShichengChu first version + * 2024-02-14 ShichengChu first version */ #include "drv_hw_i2c.h" #include @@ -16,458 +16,416 @@ #define DBG_LVL DBG_INFO #include -#define false 0 -#define true 1 -struct _i2c_bus +struct dw_iic_bus { struct rt_i2c_bus_device parent; - uint8_t i2c_id; + dw_iic_regs_t *iic_base; + rt_uint32_t irq; char *device_name; }; -static struct _i2c_bus _i2c_obj[] = +static struct dw_iic_bus _i2c_obj[] = { #ifdef BSP_USING_I2C0 { - .i2c_id = I2C0, - .device_name = "i2c0", + .iic_base = (dw_iic_regs_t *)I2C0_BASE, + .device_name = "i2c0", + .irq = I2C0_IRQ, }, #endif /* BSP_USING_I2C0 */ #ifdef BSP_USING_I2C1 { - .i2c_id = I2C1, - .device_name = "i2c1", + .iic_base = (dw_iic_regs_t *)I2C1_BASE, + .device_name = "i2c1", + .irq = I2C1_IRQ, }, #endif /* BSP_USING_I2C1 */ +#ifdef BSP_USING_I2C2 + { + .iic_base = (dw_iic_regs_t *)I2C2_BASE, + .device_name = "i2c2", + .irq = I2C2_IRQ, + }, +#endif /* BSP_USING_I2C2 */ +#ifdef BSP_USING_I2C3 + { + .iic_base = (dw_iic_regs_t *)I2C3_BASE, + .device_name = "i2c3", + .irq = I2C3_IRQ, + }, +#endif /* BSP_USING_I2C3 */ +#ifdef BSP_USING_I2C4 + { + .iic_base = (dw_iic_regs_t *)I2C4_BASE, + .device_name = "i2c4", + .irq = I2C4_IRQ, + }, +#endif /* BSP_USING_I2C4 */ }; -static struct i2c_regs *get_i2c_base(uint8_t i2c_id) -{ - struct i2c_regs *i2c_base = NULL; - - switch (i2c_id) { - case I2C0: - i2c_base = (struct i2c_regs *)I2C0_BASE; - break; - case I2C1: - i2c_base = (struct i2c_regs *)I2C1_BASE; - break; - case I2C2: - i2c_base = (struct i2c_regs *)I2C2_BASE; - break; - case I2C3: - i2c_base = (struct i2c_regs *)I2C3_BASE; - break; - case I2C4: - i2c_base = (struct i2c_regs *)I2C4_BASE; - break; - } - - return i2c_base; -} - -static uint32_t get_i2c_intr(uint8_t i2c_id) -{ - uint32_t i2c_intr = 0; - - switch (i2c_id) { - case I2C0: - i2c_intr = I2C0_IRQ; - break; - case I2C1: - i2c_intr = I2C1_IRQ; - break; - case I2C2: - i2c_intr = I2C2_IRQ; - break; - case I2C3: - i2c_intr = I2C3_IRQ; - break; - case I2C4: - i2c_intr = I2C4_IRQ; - break; - } - - return i2c_intr; -} - -void i2c_write_cmd_data(struct i2c_regs *i2c, uint16_t value) -{ - mmio_write_32((uintptr_t)&i2c->ic_cmd_data, value); -} - -static void i2c_enable(struct i2c_regs *i2c, uint8_t enable) -{ - uint32_t ena = enable ? IC_ENABLE : 0; - int timeout = 100; - - do { - mmio_write_32((uintptr_t)&i2c->ic_enable, ena); - if ((mmio_read_32((uintptr_t)&i2c->ic_enable_status) & IC_ENABLE) == ena) - return; - - /* - * Wait 10 times the signaling period of the highest I2C - * transfer supported by the driver (for 400KHz this is - * 25us) as described in the DesignWare I2C databook. - */ - rt_hw_us_delay(25); - } while (timeout--); - - LOG_I("timeout in %sabling I2C adapter\n", enable ? "en" : "dis"); -} - -static void i2c_disable(struct i2c_regs *i2c) -{ - int timeout = 100; - - do { - mmio_write_32((uintptr_t)&i2c->ic_enable, 0x0); - if ((mmio_read_32((uintptr_t)&i2c->ic_enable_status) & IC_ENABLE) == 0x0) - return; - - /* - * Wait 10 times the signaling period of the highest I2C - * transfer supported by the driver (for 400KHz this is - * 25us) as described in the DesignWare I2C databook. - */ - rt_hw_us_delay(25); - } while (timeout--); - - LOG_I("timeout in disabling I2C adapter\n"); -} - -/* - * i2c_flush_rxfifo - Flushes the i2c RX FIFO - * - * Flushes the i2c RX FIFO - */ -static void i2c_flush_rxfifo(struct i2c_regs *i2c) -{ - while (mmio_read_32((uintptr_t)&i2c->ic_status) & IC_STATUS_RFNE) - mmio_read_32((uintptr_t)&i2c->ic_cmd_data); -} - -/* - * i2c_wait_for_bb - Waits for bus busy - * - * Waits for bus busy - */ -static int i2c_wait_for_bb(struct i2c_regs *i2c) +static rt_uint32_t dw_iic_wait_for_bb(dw_iic_regs_t *iic_base) { uint16_t timeout = 0; - - while ((mmio_read_32((uintptr_t)&i2c->ic_status) & IC_STATUS_MA) || - !(mmio_read_32((uintptr_t)&i2c->ic_status) & IC_STATUS_TFE)) { - + while ((iic_base->IC_STATUS & DW_IIC_MST_ACTIVITY_STATE) || !(iic_base->IC_STATUS & DW_IIC_TXFIFO_EMPTY_STATE)) + { /* Evaluate timeout */ rt_hw_us_delay(5); - timeout++; - if (timeout > 200) /* exceed 1 ms */ + timeout ++; + if (timeout > 200) + { + /* exceed 1 ms */ + LOG_E("Timed out waiting for bus busy"); return 1; + } } return 0; } -/* - * i2c_setaddress - Sets the target slave address - * @i2c_addr: target i2c address - * - * Sets the target slave address. - */ -static void i2c_setaddress(struct i2c_regs *i2c, uint16_t i2c_addr) +void dw_iic_set_reg_address(dw_iic_regs_t *iic_base, rt_uint32_t addr, uint8_t addr_len) { - /* Disable i2c */ - i2c_enable(i2c, false); - mmio_write_32((uintptr_t)&i2c->ic_tar, i2c_addr); - /* Enable i2c */ - i2c_enable(i2c, true); -} - - -static int i2c_xfer_init(struct i2c_regs *i2c, uint16_t chip, uint16_t addr, uint16_t alen) -{ - if (i2c_wait_for_bb(i2c)) - return 1; - - i2c_setaddress(i2c, chip); - - while (alen) { - alen--; + while (addr_len) + { + addr_len --; /* high byte address going out first */ - i2c_write_cmd_data(i2c, (addr >> (alen * 8)) & 0xff); // TODO - //mmio_write_32((uintptr_t)&i2c_base->ic_cmd_data, (addr >> (alen * 8)) & 0xff); + dw_iic_transmit_data(iic_base, (addr >> (addr_len * 8)) & 0xff); } - return 0; } -static int i2c_xfer_finish(struct i2c_regs *i2c) +static void dw_iic_set_target_address(dw_iic_regs_t *iic_base, rt_uint32_t address) { - uint16_t timeout = 0; - while (1) { - if ((mmio_read_32((uintptr_t)&i2c->ic_raw_intr_stat) & IC_STOP_DET)) { - mmio_read_32((uintptr_t)&i2c->ic_clr_stop_det); + rt_uint32_t i2c_status; + i2c_status = dw_iic_get_iic_status(iic_base); + dw_iic_disable(iic_base); + iic_base->IC_TAR = (iic_base->IC_TAR & ~0x3ff) | address; /* this register can be written only when the I2C is disabled*/ + + if (i2c_status == DW_IIC_EN) + { + dw_iic_enable(iic_base); + } +} + +static int dw_iic_xfer_init(dw_iic_regs_t *iic_base, rt_uint32_t dev_addr) +{ + if (dw_iic_wait_for_bb(iic_base)) + return -RT_ERROR; + + dw_iic_set_target_address(iic_base, dev_addr); + dw_iic_enable(iic_base); + + return RT_EOK; +} + +static int dw_iic_xfer_finish(dw_iic_regs_t *iic_base) +{ + rt_uint32_t timeout = 0; + + while (1) + { + if (iic_base->IC_RAW_INTR_STAT & DW_IIC_RAW_STOP_DET) + { + iic_base->IC_CLR_STOP_DET; break; - } else { - timeout++; + } + else + { + timeout ++; rt_hw_us_delay(5); - if (timeout > I2C_STOPDET_TO * 100) { - LOG_I("%s, tiemout\n", __func__); + if (timeout > 10000) + { + LOG_E("xfer finish tiemout"); break; } } } - if (i2c_wait_for_bb(i2c)) - return 1; + if (dw_iic_wait_for_bb(iic_base)) + { + return -RT_ERROR; + } - i2c_flush_rxfifo(i2c); + dw_iic_flush_rxfifo(iic_base); - return 0; + return RT_EOK; } -/* - * i2c_read - Read from i2c memory - * @chip: target i2c address - * @addr: address to read from - * @alen: - * @buffer: buffer for read data - * @len: no of bytes to be read - * - * Read from i2c memory. - */ -static int hal_i2c_read(uint8_t i2c_id, uint8_t dev, uint16_t addr, uint16_t alen, uint8_t *buffer, uint16_t len) +static void dw_iic_set_slave_mode(dw_iic_regs_t *iic_base) { - unsigned int active = 0; - unsigned int time_count = 0; - struct i2c_regs *i2c; - int ret = 0; + rt_uint32_t i2c_status; + i2c_status = dw_iic_get_iic_status(iic_base); + dw_iic_disable(iic_base); + rt_uint32_t val = DW_IIC_CON_MASTER_EN | DW_IIC_CON_SLAVE_EN; + iic_base->IC_CON &= ~val; ///< set 0 to disabled master mode; set 0 to enabled slave mode - i2c = get_i2c_base(i2c_id); + if (i2c_status == DW_IIC_EN) + { + dw_iic_enable(iic_base); + } +} - i2c_enable(i2c, true); +static void dw_iic_set_master_mode(dw_iic_regs_t *iic_base) +{ + rt_uint32_t i2c_status; + i2c_status = dw_iic_get_iic_status(iic_base); + dw_iic_disable(iic_base); + rt_uint32_t val = DW_IIC_CON_MASTER_EN | DW_IIC_CON_SLAVE_EN; ///< set 1 to enabled master mode; set 1 to disabled slave mode + iic_base->IC_CON |= val; - if (i2c_xfer_init(i2c, dev, addr, alen)) - return 1; + if (i2c_status == DW_IIC_EN) + { + dw_iic_enable(iic_base); + } +} - while (len) { - if (!active) { - /* - * Avoid writing to ic_cmd_data multiple times - * in case this loop spins too quickly and the - * ic_status RFNE bit isn't set after the first - * write. Subsequent writes to ic_cmd_data can - * trigger spurious i2c transfer. - */ - i2c_write_cmd_data(i2c, (dev <<1) | BIT_I2C_CMD_DATA_READ_BIT | BIT_I2C_CMD_DATA_STOP_BIT); - //mmio_write_32((uintptr_t)&i2c_base->ic_cmd_data, (dev <<1) | BIT_I2C_CMD_DATA_READ_BIT | BIT_I2C_CMD_DATA_STOP_BIT); - active = 1; +static rt_err_t dw_iic_recv(dw_iic_regs_t *iic_base, rt_uint32_t devaddr, rt_uint8_t *data, rt_uint32_t size, rt_uint32_t timeout) +{ + rt_err_t ret = RT_EOK; + rt_uint32_t timecount = 0; + + RT_ASSERT(data != RT_NULL); + + if (dw_iic_xfer_init(iic_base, devaddr)) + { + ret = -RT_EIO; + goto ERR_EXIT; + } + + timecount = timeout + rt_tick_get_millisecond(); + + for (int i = 0 ; i < size; i ++) + { + if(i != (size - 1)) + { + dw_iic_transmit_data(iic_base, DW_IIC_DATA_CMD); } - - if (mmio_read_32((uintptr_t)&i2c->ic_raw_intr_stat) & BIT_I2C_INT_RX_FULL) { - *buffer++ = (uint8_t)mmio_read_32((uintptr_t)&i2c->ic_cmd_data); - len--; - time_count = 0; - active = 0; - } - else { - rt_hw_us_delay(5); - time_count++; - if (time_count >= I2C_BYTE_TO * 100) - return 1; + else + { + dw_iic_transmit_data(iic_base, DW_IIC_DATA_CMD | DW_IIC_DATA_STOP); } } - ret = i2c_xfer_finish(i2c); - i2c_disable(i2c); + while (size > 0) + { + if (iic_base->IC_STATUS & DW_IIC_RXFIFO_NOT_EMPTY_STATE) + { + *data ++ = dw_iic_receive_data(iic_base); + -- size; + } + else if (rt_tick_get_millisecond() >= timecount) + { + LOG_E("Timed out read ic_cmd_data"); + ret = -RT_ETIMEOUT; + goto ERR_EXIT; + } + } + + if (dw_iic_xfer_finish(iic_base)) + { + ret = -RT_EIO; + goto ERR_EXIT; + } + +ERR_EXIT: + dw_iic_disable(iic_base); return ret; } -/* - * i2c_write - Write to i2c memory - * @chip: target i2c address - * @addr: address to read from - * @alen: - * @buffer: buffer for read data - * @len: no of bytes to be read - * - * Write to i2c memory. - */ - -static int hal_i2c_write(uint8_t i2c_id, uint8_t dev, uint16_t addr, uint16_t alen, uint8_t *buffer, uint16_t len) +static rt_err_t dw_iic_send(dw_iic_regs_t *iic_base, rt_uint32_t devaddr, const uint8_t *data, rt_uint32_t size, rt_uint32_t timeout) { - struct i2c_regs *i2c; - int ret = 0; - i2c = get_i2c_base(i2c_id); + rt_err_t ret = RT_EOK; + rt_uint32_t timecount; - i2c_enable(i2c, true); + RT_ASSERT(data != RT_NULL); - if (i2c_xfer_init(i2c, dev, addr, alen)) - return 1; + if (dw_iic_xfer_init(iic_base, devaddr)) + { + ret = -RT_EIO; + goto ERR_EXIT; + } - while (len) { - if (i2c->ic_status & IC_STATUS_TFNF) { - if (--len == 0) { - i2c_write_cmd_data(i2c, *buffer | IC_STOP); - //mmio_write_32((uintptr_t)&i2c_base->ic_cmd_data, *buffer | IC_STOP); - } else { - i2c_write_cmd_data(i2c, *buffer); - //mmio_write_32((uintptr_t)&i2c_base->ic_cmd_data, *buffer); + timecount = timeout + rt_tick_get_millisecond(); + + while (size > 0) + { + if (iic_base->IC_STATUS & DW_IIC_TXFIFO_NOT_FULL_STATE) + { + if (-- size == 0) + { + dw_iic_transmit_data(iic_base, *data ++ | DW_IIC_DATA_STOP); } - buffer++; - } else - LOG_I("len=%d, ic status is not TFNF\n", len); + else + { + dw_iic_transmit_data(iic_base, *data ++); + } + } + else if (rt_tick_get_millisecond() >= timecount) + { + LOG_D("ic status is not TFNF\n"); + ret = -RT_ETIMEOUT; + goto ERR_EXIT; + } } - ret = i2c_xfer_finish(i2c); - i2c_disable(i2c); + + LOG_D("dw_iic_xfer_finish"); + + if (dw_iic_xfer_finish(iic_base)) + { + ret = -RT_EIO; + goto ERR_EXIT; + } + +ERR_EXIT: + dw_iic_disable(iic_base); + return ret; } -/* - * hal_i2c_set_bus_speed - Set the i2c speed - * @speed: required i2c speed - * - * Set the i2c speed. - */ -static void i2c_set_bus_speed(struct i2c_regs *i2c, unsigned int speed) -{ - unsigned int cntl; - unsigned int hcnt, lcnt; - int i2c_spd; - - if (speed > I2C_FAST_SPEED) - i2c_spd = IC_SPEED_MODE_MAX; - else if ((speed <= I2C_FAST_SPEED) && (speed > I2C_STANDARD_SPEED)) - i2c_spd = IC_SPEED_MODE_FAST; - else - i2c_spd = IC_SPEED_MODE_STANDARD; - - /* to set speed cltr must be disabled */ - i2c_enable(i2c, false); - - cntl = (mmio_read_32((uintptr_t)&i2c->ic_con) & (~IC_CON_SPD_MSK)); - - switch (i2c_spd) { - case IC_SPEED_MODE_MAX: - cntl |= IC_CON_SPD_HS; - //hcnt = (u16)(((IC_CLK * MIN_HS100pF_SCL_HIGHTIME) / 1000) - 8); - /* 7 = 6+1 == MIN LEN +IC_FS_SPKLEN */ - //lcnt = (u16)(((IC_CLK * MIN_HS100pF_SCL_LOWTIME) / 1000) - 1); - hcnt = 6; - lcnt = 8; - - mmio_write_32((uintptr_t)&i2c->ic_hs_scl_hcnt, hcnt); - mmio_write_32((uintptr_t)&i2c->ic_hs_scl_lcnt, lcnt); - break; - - case IC_SPEED_MODE_STANDARD: - cntl |= IC_CON_SPD_SS; - - hcnt = (uint16_t)(((IC_CLK * MIN_SS_SCL_HIGHTIME) / 1000) - 7); - lcnt = (uint16_t)(((IC_CLK * MIN_SS_SCL_LOWTIME) / 1000) - 1); - - mmio_write_32((uintptr_t)&i2c->ic_ss_scl_hcnt, hcnt); - mmio_write_32((uintptr_t)&i2c->ic_ss_scl_lcnt, lcnt); - break; - - case IC_SPEED_MODE_FAST: - default: - cntl |= IC_CON_SPD_FS; - hcnt = (uint16_t)(((IC_CLK * MIN_FS_SCL_HIGHTIME) / 1000) - 7); - lcnt = (uint16_t)(((IC_CLK * MIN_FS_SCL_LOWTIME) / 1000) - 1); - - mmio_write_32((uintptr_t)&i2c->ic_fs_scl_hcnt, hcnt); - mmio_write_32((uintptr_t)&i2c->ic_fs_scl_lcnt, lcnt); - break; - } - - mmio_write_32((uintptr_t)&i2c->ic_con, cntl); - - /* Enable back i2c now speed set */ - i2c_enable(i2c, true); -} - -/* - * __hal_i2c_init - Init function - * @speed: required i2c speed - * @slaveaddr: slave address for the device - * - * Initialization function. - */ -static void hal_i2c_init(uint8_t i2c_id) -{ - struct i2c_regs *i2c; - uint32_t i2c_intr; - - LOG_I("%s, i2c-%d\n", __func__, i2c_id); - /* Disable i2c */ - //Need to acquire lock here - - i2c = get_i2c_base(i2c_id); - i2c_intr = get_i2c_intr(i2c_id); - - // request_irq(i2c_intr, i2c_dw_isr, 0, "IC2_INTR int", &dw_i2c[i2c_id]); - - i2c_enable(i2c, false); - mmio_write_32((uintptr_t)&i2c->ic_con, (IC_CON_SD | IC_CON_SPD_FS | IC_CON_MM | IC_CON_RE)); - mmio_write_32((uintptr_t)&i2c->ic_rx_tl, IC_RX_TL); - mmio_write_32((uintptr_t)&i2c->ic_tx_tl, IC_TX_TL); - mmio_write_32((uintptr_t)&i2c->ic_intr_mask, 0x0); - i2c_set_bus_speed(i2c, I2C_SPEED); - //mmio_write_32((uintptr_t)&i2c->ic_sar, slaveaddr); - /* Enable i2c */ - i2c_enable(i2c, false); - - //Need to release lock here -} - -static rt_ssize_t _master_xfer(struct rt_i2c_bus_device *bus, - struct rt_i2c_msg msgs[], - rt_uint32_t num) +static rt_ssize_t dw_iic_master_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], rt_uint32_t num) { struct rt_i2c_msg *msg; rt_uint32_t i; rt_ssize_t ret = -RT_ERROR; + rt_uint32_t timeout; - struct _i2c_bus *i2c = (struct _i2c_bus *)bus; + struct dw_iic_bus *i2c_bus = (struct dw_iic_bus *)bus; + dw_iic_regs_t *iic_base = i2c_bus->iic_base; for (i = 0; i < num; i++) { msg = &msgs[i]; - if (msg->flags & RT_I2C_RD) + if (msg->flags & RT_I2C_ADDR_10BIT) { - hal_i2c_read(i2c->i2c_id, msg->addr, RT_NULL, 1, msg->buf, msg->len); + dw_iic_set_master_10bit_addr_mode(iic_base); + dw_iic_set_slave_10bit_addr_mode(iic_base); } else { - hal_i2c_write(i2c->i2c_id, msg->addr, RT_NULL, 1, msg->buf, msg->len); + dw_iic_set_master_7bit_addr_mode(iic_base); + dw_iic_set_slave_7bit_addr_mode(iic_base); + } + + if (msg->flags & RT_I2C_RD) + { + timeout = 1000; + ret = dw_iic_recv(iic_base, msg->addr, msg->buf, msg->len, timeout); + if (ret != RT_EOK) + LOG_E("dw_iic_recv error: %d", ret); + } + else + { + timeout = 100; + ret = dw_iic_send(iic_base, msg->addr, msg->buf, msg->len, timeout); + if (ret != RT_EOK) + LOG_E("dw_iic_send error: %d", ret); } } - return ret; + return ret == RT_EOK ? num : ret; } -static void rt_hw_i2c_isr(int irqno, void *param) +static void dw_iic_set_transfer_speed_high(dw_iic_regs_t *iic_base) { - uint32_t stat, enabled; - struct i2c_regs *i2c = (struct i2c_regs *)param; + rt_uint32_t speed_config = iic_base->IC_CON; + speed_config &= ~(DW_IIC_CON_SPEEDL_EN | DW_IIC_CON_SPEEDH_EN); + speed_config |= DW_IIC_CON_SPEEDL_EN | DW_IIC_CON_SPEEDH_EN; + iic_base->IC_CON = speed_config; +} - enabled = mmio_read_32((uintptr_t)&i2c->ic_enable); - stat = mmio_read_32((uintptr_t)&i2c->ic_intr_stat); +static void dw_iic_set_transfer_speed_fast(dw_iic_regs_t *iic_base) +{ + rt_uint32_t speed_config = iic_base->IC_CON; + speed_config &= ~(DW_IIC_CON_SPEEDL_EN | DW_IIC_CON_SPEEDH_EN); + speed_config |= DW_IIC_CON_SPEEDH_EN; + iic_base->IC_CON = speed_config; +} - LOG_I("i2c interrupt stat: 0x%08x", stat); +static void dw_iic_set_transfer_speed_standard(dw_iic_regs_t *iic_base) +{ + rt_uint32_t speed_config = iic_base->IC_CON; + speed_config &= ~(DW_IIC_CON_SPEEDL_EN | DW_IIC_CON_SPEEDH_EN); + speed_config |= DW_IIC_CON_SPEEDL_EN; + iic_base->IC_CON = speed_config; +} + +static rt_err_t dw_iic_bus_control(struct rt_i2c_bus_device *bus, int cmd, void *args) +{ + struct dw_iic_bus *i2c_bus = (struct dw_iic_bus *)bus; + + RT_ASSERT(bus != RT_NULL); + + dw_iic_regs_t *iic_base = i2c_bus->iic_base; + + switch (cmd) + { + case RT_I2C_DEV_CTRL_CLK: + { + rt_uint32_t speed = *(rt_uint32_t *)args; + if (speed == 100 * 1000) + { + dw_iic_set_transfer_speed_standard(iic_base); + dw_iic_set_standard_scl_hcnt(iic_base, (((IC_CLK * 4000U) / 1000U) - 7U)); + dw_iic_set_standard_scl_lcnt(iic_base, (((IC_CLK * 4700) / 1000U) - 1U)); + } + else if (speed == 400 * 1000) + { + dw_iic_set_transfer_speed_fast(iic_base); + dw_iic_set_fast_scl_hcnt(iic_base, (((IC_CLK * 600U) / 1000U) - 7U)); + dw_iic_set_fast_scl_lcnt(iic_base, (((IC_CLK * 1300U) / 1000U) - 1U)); + } + else if (speed == 4 * 1000 * 1000) + { + dw_iic_set_transfer_speed_high(iic_base); + dw_iic_set_high_scl_hcnt(iic_base, 6U); + dw_iic_set_high_scl_lcnt(iic_base, 8U); + } + else + { + return -RT_EIO; + } + } + break; + + case RT_I2C_DEV_CTRL_10BIT: + dw_iic_set_master_10bit_addr_mode(iic_base); + dw_iic_set_slave_10bit_addr_mode(iic_base); + break; + + default: + return -RT_EIO; + break; + } + + return RT_EOK; } static const struct rt_i2c_bus_device_ops i2c_ops = { - .master_xfer = _master_xfer, + .master_xfer = dw_iic_master_xfer, .slave_xfer = RT_NULL, - .i2c_bus_control = RT_NULL + .i2c_bus_control = dw_iic_bus_control, }; +static void dw_iic_init(dw_iic_regs_t *iic_base) +{ + dw_iic_disable(iic_base); + dw_iic_clear_all_irq(iic_base); + dw_iic_disable_all_irq(iic_base); + + iic_base->IC_SAR = 0; + + dw_iic_set_receive_fifo_threshold(iic_base, 0x1); + dw_iic_set_transmit_fifo_threshold(iic_base, 0x0); + dw_iic_set_sda_hold_time(iic_base, 0x1e); + + dw_iic_set_master_mode(iic_base); + dw_iic_enable_restart(iic_base); + + dw_iic_set_transfer_speed_standard(iic_base); + dw_iic_set_standard_scl_hcnt(iic_base, (((IC_CLK * 4000U) / 1000U) - 7U)); + dw_iic_set_standard_scl_lcnt(iic_base, (((IC_CLK * 4700) / 1000U) - 1U)); +} #if defined(BOARD_TYPE_MILKV_DUO) || defined(BOARD_TYPE_MILKV_DUO_SPINOR) @@ -531,7 +489,7 @@ static const char *pinname_whitelist_i2c4_sda[] = { #elif defined(BOARD_TYPE_MILKV_DUO256M) || defined(BOARD_TYPE_MILKV_DUO256M_SPINOR) #ifdef BSP_USING_I2C0 -// I2C0 is not ALLOWED for Duo +// I2C0 is not ALLOWED for Duo256 static const char *pinname_whitelist_i2c0_scl[] = { NULL, }; @@ -576,7 +534,7 @@ static const char *pinname_whitelist_i2c3_sda[] = { #endif #ifdef BSP_USING_I2C4 -// I2C4 is not ALLOWED for Duo +// I2C4 is not ALLOWED for Duo256 static const char *pinname_whitelist_i2c4_scl[] = { NULL, }; @@ -623,9 +581,9 @@ int rt_hw_i2c_init(void) rt_hw_i2c_pinmux_config(); - for (rt_size_t i = 0; i < sizeof(_i2c_obj) / sizeof(struct _i2c_bus); i++) + for (rt_size_t i = 0; i < sizeof(_i2c_obj) / sizeof(struct dw_iic_bus); i++) { - hal_i2c_init(_i2c_obj->i2c_id); + dw_iic_init(_i2c_obj->iic_base); _i2c_obj[i].parent.ops = &i2c_ops; @@ -639,10 +597,6 @@ int rt_hw_i2c_init(void) LOG_E("%s register failed", _i2c_obj[i].device_name); result = -RT_ERROR; } - - uint32_t irqno = get_i2c_intr(_i2c_obj[i].i2c_id); - struct i2c_regs *_i2c = get_i2c_base(_i2c_obj[i].i2c_id); - rt_hw_interrupt_install(irqno, rt_hw_i2c_isr, _i2c, _i2c_obj[i].device_name); } return result; diff --git a/bsp/cvitek/drivers/drv_hw_i2c.h b/bsp/cvitek/drivers/drv_hw_i2c.h index 095550263b..05c9721ffb 100644 --- a/bsp/cvitek/drivers/drv_hw_i2c.h +++ b/bsp/cvitek/drivers/drv_hw_i2c.h @@ -1,11 +1,11 @@ /* - * Copyright (c) 2006-2023, RT-Thread Development Team + * Copyright (c) 2006-2024, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - *2024-02-14 ShichengChu first version + * 2024-02-14 ShichengChu first version */ #ifndef __DRV_HW_I2C_H__ #define __DRV_HW_I2C_H__ @@ -29,205 +29,680 @@ #define I2C3_BASE 0x4030000 #define I2C4_BASE 0x4040000 -#define BIT_I2C_CMD_DATA_READ_BIT (0x01 << 8) -#define BIT_I2C_CMD_DATA_STOP_BIT (0x01 << 9) - -/* bit definition */ -#define BIT_I2C_CON_MASTER_MODE (0x01 << 0) -#define BIT_I2C_CON_STANDARD_SPEED (0x01 << 1) -#define BIT_I2C_CON_FULL_SPEED (0x02 << 1) -#define BIT_I2C_CON_HIGH_SPEED (0x03 << 1) -#define BIT_I2C_CON_10B_ADDR_SLAVE (0x01 << 3) -#define BIT_I2C_CON_10B_ADDR_MASTER (0x01 << 4) -#define BIT_I2C_CON_RESTART_EN (0x01 << 5) -#define BIT_I2C_CON_SLAVE_DIS (0x01 << 6) - -#define BIT_I2C_TAR_10B_ADDR_MASTER (0x01 << 12) - -#define BIT_I2C_INT_RX_UNDER (0x01 << 0) -#define BIT_I2C_INT_RX_OVER (0x01 << 1) -#define BIT_I2C_INT_RX_FULL (0x01 << 2) -#define BIT_I2C_INT_TX_OVER (0x01 << 3) -#define BIT_I2C_INT_TX_EMPTY (0x01 << 4) -#define BIT_I2C_INT_RD_REQ (0x01 << 5) -#define BIT_I2C_INT_TX_ABRT (0x01 << 6) -#define BIT_I2C_INT_RX_DONE (0x01 << 7) -#define BIT_I2C_INT_ACTIVITY (0x01 << 8) -#define BIT_I2C_INT_STOP_DET (0x01 << 9) -#define BIT_I2C_INT_START_DET (0x01 << 10) -#define BIT_I2C_INT_GEN_ALL (0x01 << 11) -#define I2C_INTR_MASTER_MASK (BIT_I2C_INT_TX_ABRT | \ - BIT_I2C_INT_STOP_DET | \ - BIT_I2C_INT_RX_FULL | \ - BIT_I2C_INT_TX_EMPTY) - -#define BIT_I2C_INT_RX_UNDER_MASK (0x01 << 0) -#define BIT_I2C_INT_RX_OVER_MASK (0x01 << 1) -#define BIT_I2C_INT_RX_FULL_MASK (0x01 << 2) -#define BIT_I2C_INT_TX_OVER_MASK (0x01 << 3) -#define BIT_I2C_INT_TX_EMPTY_MASK (0x01 << 4) -#define BIT_I2C_INT_RD_REQ_MASK (0x01 << 5) -#define BIT_I2C_INT_TX_ABRT_MASK (0x01 << 6) -#define BIT_I2C_INT_RX_DONE_MASK (0x01 << 7) -#define BIT_I2C_INT_ACTIVITY_MASK (0x01 << 8) -#define BIT_I2C_INT_STOP_DET_MASK (0x01 << 9) -#define BIT_I2C_INT_START_DET_MASK (0x01 << 10) -#define BIT_I2C_INT_GEN_ALL_MASK (0x01 << 11) - -#define BIT_I2C_INT_RX_UNDER_RAW (0x01 << 0) -#define BIT_I2C_INT_RX_OVER_RAW (0x01 << 1) -#define BIT_I2C_INT_RX_FULL_RAW (0x01 << 2) -#define BIT_I2C_INT_TX_OVER_RAW (0x01 << 3) -#define BIT_I2C_INT_TX_EMPTY_RAW (0x01 << 4) -#define BIT_I2C_INT_RD_REQ_RAW (0x01 << 5) -#define BIT_I2C_INT_TX_ABRT_RAW (0x01 << 6) -#define BIT_I2C_INT_RX_DONE_RAW (0x01 << 7) -#define BIT_I2C_INT_ACTIVITY_RAW (0x01 << 8) -#define BIT_I2C_INT_STOP_DET_RAW (0x01 << 9) -#define BIT_I2C_INT_START_DET_RAW (0x01 << 10) -#define BIT_I2C_INT_GEN_ALL_RAW (0x01 << 11) - -#define BIT_I2C_DMA_CR_TDMAE (0x01 << 1) -#define BIT_I2C_DMA_CR_RDMAE (0x01 << 0) - -struct i2c_regs { - volatile uint32_t ic_con; /* 0x00 */ - volatile uint32_t ic_tar; /* 0x04 */ - volatile uint32_t ic_sar; /* 0x08 */ - volatile uint32_t ic_hs_maddr; /* 0x0c */ - volatile uint32_t ic_cmd_data; /* 0x10 */ - volatile uint32_t ic_ss_scl_hcnt; /* 0x14 */ - volatile uint32_t ic_ss_scl_lcnt; /* 0x18 */ - volatile uint32_t ic_fs_scl_hcnt; /* 0x1c */ - volatile uint32_t ic_fs_scl_lcnt; /* 0x20 */ - volatile uint32_t ic_hs_scl_hcnt; /* 0x24 */ - volatile uint32_t ic_hs_scl_lcnt; /* 0x28 */ - volatile uint32_t ic_intr_stat; /* 0x2c */ - volatile uint32_t ic_intr_mask; /* 0x30 */ - volatile uint32_t ic_raw_intr_stat; /* 0x34 */ - volatile uint32_t ic_rx_tl; /* 0x38 */ - volatile uint32_t ic_tx_tl; /* 0x3c */ - volatile uint32_t ic_clr_intr; /* 0x40 */ - volatile uint32_t ic_clr_rx_under; /* 0x44 */ - volatile uint32_t ic_clr_rx_over; /* 0x48 */ - volatile uint32_t ic_clr_tx_over; /* 0x4c */ - volatile uint32_t ic_clr_rd_req; /* 0x50 */ - volatile uint32_t ic_clr_tx_abrt; /* 0x54 */ - volatile uint32_t ic_clr_rx_done; /* 0x58 */ - volatile uint32_t ic_clr_activity; /* 0x5c */ - volatile uint32_t ic_clr_stop_det; /* 0x60 */ - volatile uint32_t ic_clr_start_det; /* 0x64 */ - volatile uint32_t ic_clr_gen_call; /* 0x68 */ - volatile uint32_t ic_enable; /* 0x6c */ - volatile uint32_t ic_status; /* 0x70 */ - volatile uint32_t ic_txflr; /* 0x74 */ - volatile uint32_t ic_rxflr; /* 0x78 */ - volatile uint32_t ic_sda_hold; /* 0x7c */ - volatile uint32_t ic_tx_abrt_source; /* 0x80 */ - volatile uint32_t ic_slv_dat_nack_only; /* 0x84 */ - volatile uint32_t ic_dma_cr; /* 0x88 */ - volatile uint32_t ic_dma_tdlr; /* 0x8c */ - volatile uint32_t ic_dma_rdlr; /* 0x90 */ - volatile uint32_t ic_sda_setup; /* 0x94 */ - volatile uint32_t ic_ack_general_call; /* 0x98 */ - volatile uint32_t ic_enable_status; /* 0x9c */ - volatile uint32_t ic_fs_spklen; /* 0xa0 */ - volatile uint32_t ic_hs_spklen; /* 0xa4 */ -}; - -#if !defined(IC_CLK) -#define IC_CLK 100 -#endif - -#define NANO_TO_MICRO 1000 - -/* High and low times in different speed modes (in ns) */ -#define MIN_SS_SCL_HIGHTIME 4000 -#define MIN_SS_SCL_LOWTIME 4700 -#define MIN_FS_SCL_HIGHTIME 600 -#define MIN_FS_SCL_LOWTIME 1300 -#define MIN_HS100pF_SCL_HIGHTIME 60 -#define MIN_HS100pF_SCL_LOWTIME 120 -#define MIN_HS400pF_SCL_HIGHTIME 160 -#define MIN_HS400pF_SCL_LOWTIME 320 - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ -/* Worst case timeout for 1 byte is kept as 2ms */ -#define I2C_BYTE_TO (CONFIG_SYS_HZ/500) - -#define I2C_STOPDET_TO (CONFIG_SYS_HZ/500) -#define I2C_BYTE_TO_BB (I2C_BYTE_TO * 16) - -/* i2c control register definitions */ -#define IC_CON_SD 0x0040 -#define IC_CON_RE 0x0020 -#define IC_CON_10BITADDRMASTER 0x0010 -#define IC_CON_10BITADDR_SLAVE 0x0008 -#define IC_CON_SPD_MSK 0x0006 -#define IC_CON_SPD_SS 0x0002 -#define IC_CON_SPD_FS 0x0004 -#define IC_CON_SPD_HS 0x0006 -#define IC_CON_MM 0x0001 - -/* i2c data buffer and command register definitions */ -#define IC_CMD 0x0100 -#define IC_STOP 0x0200 - -/* i2c interrupt status register definitions */ -#define IC_GEN_CALL 0x0800 -#define IC_START_DET 0x0400 -#define IC_STOP_DET 0x0200 -#define IC_ACTIVITY 0x0100 -#define IC_RX_DONE 0x0080 -#define IC_TX_ABRT 0x0040 -#define IC_RD_REQ 0x0020 -#define IC_TX_EMPTY 0x0010 -#define IC_TX_OVER 0x0008 -#define IC_RX_FULL 0x0004 -#define IC_RX_OVER 0x0002 -#define IC_RX_UNDER 0x0001 - -/* fifo threshold register definitions */ -#define IC_TL0 0x00 -#define IC_TL1 0x01 -#define IC_TL2 0x02 -#define IC_TL3 0x03 -#define IC_TL4 0x04 -#define IC_TL5 0x05 -#define IC_TL6 0x06 -#define IC_TL7 0x07 -#define IC_RX_TL IC_TL0 -#define IC_TX_TL IC_TL0 - -/* i2c enable register definitions */ -#define IC_ENABLE 0x0001 - -/* i2c status register definitions */ -#define IC_STATUS_SA 0x0040 -#define IC_STATUS_MA 0x0020 -#define IC_STATUS_RFF 0x0010 -#define IC_STATUS_RFNE 0x0008 -#define IC_STATUS_TFE 0x0004 -#define IC_STATUS_TFNF 0x0002 -#define IC_STATUS_ACT 0x0001 - -/* Speed Selection */ -#define IC_SPEED_MODE_STANDARD 1 -#define IC_SPEED_MODE_FAST 2 -#define IC_SPEED_MODE_MAX 3 - -#define I2C_MAX_SPEED 3400000 -#define I2C_FAST_SPEED 400000 -#define I2C_STANDARD_SPEED 100000 - -#define I2C_SPEED I2C_FAST_SPEED - #define I2C0_IRQ (I2C_IRQ_BASE + 0) #define I2C1_IRQ (I2C_IRQ_BASE + 1) #define I2C2_IRQ (I2C_IRQ_BASE + 2) #define I2C3_IRQ (I2C_IRQ_BASE + 3) #define I2C4_IRQ (I2C_IRQ_BASE + 4) + +#if !defined(IC_CLK) +#define IC_CLK 100 +#endif + +/* + * I2C register bit definitions + */ + +/* IC_CON, offset: 0x00 */ +#define DW_IIC_CON_DEFAUL (0x23U) +#define DW_IIC_CON_MASTER_Pos (0U) +#define DW_IIC_CON_MASTER_Msk (0x1U << DW_IIC_CON_MASTER_Pos) +#define DW_IIC_CON_MASTER_EN DW_IIC_CON_MASTER_Msk + +#define DW_IIC_CON_SPEEDL_Pos (1U) +#define DW_IIC_CON_SPEEDL_Msk (0x1U << DW_IIC_CON_SPEEDL_Pos) +#define DW_IIC_CON_SPEEDL_EN DW_IIC_CON_SPEEDL_Msk + +#define DW_IIC_CON_SPEEDH_Pos (2U) +#define DW_IIC_CON_SPEEDH_Msk (0x1U << DW_IIC_CON_SPEEDH_Pos) +#define DW_IIC_CON_SPEEDH_EN DW_IIC_CON_SPEEDH_Msk + +#define DW_IIC_CON_SLAVE_ADDR_MODE_Pos (3U) +#define DW_IIC_CON_SLAVE_ADDR_MODE_Msk (0x1U << DW_IIC_CON_SLAVE_ADDR_MODE_Pos) +#define DW_IIC_CON_SLAVE_ADDR_MODE DW_IIC_CON_SLAVE_ADDR_MODE_Msk + +#define DW_IIC_CON_MASTER_ADDR_MODE_Pos (4U) +#define DW_IIC_CON_MASTER_ADDR_MODE_Msk (0x1U << DW_IIC_CON_MASTER_ADDR_MODE_Pos) +#define DW_IIC_CON_MASTER_ADDR_MODE DW_IIC_CON_MASTER_ADDR_MODE_Msk + +#define DW_IIC_CON_RESTART_Pos (5U) +#define DW_IIC_CON_RESTART_Msk (0x1U << DW_IIC_CON_RESTART_Pos) +#define DW_IIC_CON_RESTART_EN DW_IIC_CON_RESTART_Msk + +#define DW_IIC_CON_SLAVE_Pos (6U) +#define DW_IIC_CON_SLAVE_Msk (0x1U << DW_IIC_CON_SLAVE_Pos) +#define DW_IIC_CON_SLAVE_EN DW_IIC_CON_SLAVE_Msk + +/* IC_TAR, offset: 0x04 */ +#define DW_IIC_TAR_GC_OR_START_Pos (10U) +#define DW_IIC_TAR_GC_OR_START_Msk (0x1U << DW_IIC_TAR_GC_OR_START_Pos) +#define DW_IIC_TAR_GC_OR_START DW_IIC_TAR_GC_OR_START_Msk + +#define DW_IIC_TAR_SPECIAL_Pos (11U) +#define DW_IIC_TAR_SPECIAL_Msk (0x1U << DW_IIC_TAR_SPECIAL_Pos) +#define DW_IIC_TAR_SPECIAL DW_IIC_TAR_SPECIAL_Msk + +#define DW_IIC_TAR_MASTER_ADDR_MODE_Pos (12U) +#define DW_IIC_TAR_MASTER_ADDR_MODE_Msk (0x1U << DW_IIC_TAR_MASTER_ADDR_MODE_Pos) +#define DW_IIC_TAR_MASTER_ADDR_MODE DW_IIC_TAR_MASTER_ADDR_MODE_Msk + +/* IC_DATA_CMD, offset: 0x10 */ +#define DW_IIC_DATA_CMD_Pos (8U) +#define DW_IIC_DATA_CMD_Msk (0x1U << DW_IIC_DATA_CMD_Pos) +#define DW_IIC_DATA_CMD DW_IIC_DATA_CMD_Msk + +#define DW_IIC_DATA_STOP_Pos (9U) +#define DW_IIC_DATA_STOP_Msk (0x1U << DW_IIC_DATA_STOP_Pos) +#define DW_IIC_DATA_STOP DW_IIC_DATA_STOP_Msk + +/* IC_INTR_STAT, offset: 0x2C */ +#define DW_IIC_INTR_RX_UNDER_Pos (0U) +#define DW_IIC_INTR_RX_UNDER_Msk (0x1U << DW_IIC_INTR_RX_UNDER_Pos) +#define DW_IIC_INTR_RX_UNDER DW_IIC_INTR_RX_UNDER_Msk + +#define DW_IIC_INTR_RX_OVER_Pos (1U) +#define DW_IIC_INTR_RX_OVER_Msk (0x1U << DW_IIC_INTR_RX_OVER_Pos) +#define DW_IIC_INTR_RX_OVER DW_IIC_INTR_RX_OVER_Msk + +#define DW_IIC_INTR_RX_FULL_Pos (2U) +#define DW_IIC_INTR_RX_FULL_Msk (0x1U << DW_IIC_INTR_RX_FULL_Pos) +#define DW_IIC_INTR_RX_FULL DW_IIC_INTR_RX_FULL_Msk + +#define DW_IIC_INTR_TX_OVER_Pos (3U) +#define DW_IIC_INTR_TX_OVER_Msk (0x1U << DW_IIC_INTR_TX_OVER_Pos) +#define DW_IIC_INTR_TX_OVER DW_IIC_INTR_TX_OVER_Msk + +#define DW_IIC_INTR_TX_EMPTY_Pos (4U) +#define DW_IIC_INTR_TX_EMPTY_Msk (0x1U << DW_IIC_INTR_TX_EMPTY_Pos) +#define DW_IIC_INTR_TX_EMPTY DW_IIC_INTR_TX_EMPTY_Msk + +#define DW_IIC_INTR_RD_REQ_Pos (5U) +#define DW_IIC_INTR_RD_REQ_Msk (0x1U << DW_IIC_INTR_RD_REQ_Pos) +#define DW_IIC_INTR_RD_REQ DW_IIC_INTR_RD_REQ_Msk + +#define DW_IIC_INTR_TX_ABRT_Pos (6U) +#define DW_IIC_INTR_TX_ABRT_Msk (0x1U << DW_IIC_INTR_TX_ABRT_Pos) +#define DW_IIC_INTR_TX_ABRT DW_IIC_INTR_TX_ABRT_Msk + +#define DW_IIC_INTR_RX_DONE_Pos (7U) +#define DW_IIC_INTR_RX_DONE_Msk (0x1U << DW_IIC_INTR_RX_DONE_Pos) +#define DW_IIC_INTR_RX_DONE DW_IIC_INTR_RX_DONE_Msk + +#define DW_IIC_INTR_ACTIVITY_Pos (8U) +#define DW_IIC_INTR_ACTIVITY_Msk (0x1U << DW_IIC_INTR_ACTIVITY_Pos) +#define DW_IIC_INTR_ACTIVITY DW_IIC_INTR_ACTIVITY_Msk + +#define DW_IIC_INTR_STOP_DET_Pos (9U) +#define DW_IIC_INTR_STOP_DET_Msk (0x1U << DW_IIC_INTR_STOP_DET_Pos) +#define DW_IIC_INTR_STOP_DET DW_IIC_INTR_STOP_DET_Msk + +#define DW_IIC_INTR_START_DET_Pos (10U) +#define DW_IIC_INTR_START_DET_Msk (0x1U << DW_IIC_INTR_START_DET_Pos) +#define DW_IIC_INTR_START_DET DW_IIC_INTR_START_DET_Msk + +#define DW_IIC_INTR_GEN_CALL_Pos (11U) +#define DW_IIC_INTR_GEN_CALL_Msk (0x1U << DW_IIC_INTR_GEN_CALL_Pos) +#define DW_IIC_INTR_GEN_CALL DW_IIC_INTR_GEN_CALL_Msk + +/* IC_INTR_MASK, offset: 0x30 */ +#define DW_IIC_M_RX_UNDER_Pos (0U) +#define DW_IIC_M_RX_UNDER_Msk (0x1U << DW_IIC_INTR_RX_UNDER_Pos) +#define DW_IIC_M_RX_UNDER DW_IIC_INTR_RX_UNDER_Msk + +#define DW_IIC_M_RX_OVER_Pos (1U) +#define DW_IIC_M_RX_OVER_Msk (0x1U << DW_IIC_INTR_RX_OVER_Pos) +#define DW_IIC_M_RX_OVER DW_IIC_INTR_RX_OVER_Msk + +#define DW_IIC_M_RX_FULL_Pos (2U) +#define DW_IIC_M_RX_FULL_Msk (0x1U << DW_IIC_INTR_RX_FULL_Pos) +#define DW_IIC_M_RX_FULL DW_IIC_INTR_RX_FULL_Msk + +#define DW_IIC_M_TX_OVER_Pos (3U) +#define DW_IIC_M_TX_OVER_Msk (0x1U << DW_IIC_INTR_TX_OVER_Pos) +#define DW_IIC_M_TX_OVER DW_IIC_INTR_TX_OVER_Msk + +#define DW_IIC_M_TX_EMPTY_Pos (4U) +#define DW_IIC_M_TX_EMPTY_Msk (0x1U << DW_IIC_INTR_TX_EMPTY_Pos) +#define DW_IIC_M_TX_EMPTY DW_IIC_INTR_TX_EMPTY_Msk + +#define DW_IIC_M_RD_REQ_Pos (5U) +#define DW_IIC_M_RD_REQ_Msk (0x1U << DW_IIC_INTR_RD_REQ_Pos) +#define DW_IIC_M_RD_REQ DW_IIC_INTR_RD_REQ_Msk + +#define DW_IIC_M_TX_ABRT_Pos (6U) +#define DW_IIC_M_TX_ABRT_Msk (0x1U << DW_IIC_INTR_TX_ABRT_Pos) +#define DW_IIC_M_TX_ABRT DW_IIC_INTR_TX_ABRT_Msk + +#define DW_IIC_M_RX_DONE_Pos (7U) +#define DW_IIC_M_RX_DONE_Msk (0x1U << DW_IIC_INTR_RX_DONE_Pos) +#define DW_IIC_M_RX_DONE DW_IIC_INTR_RX_DONE_Msk + +#define DW_IIC_M_ACTIVITY_Pos (8U) +#define DW_IIC_M_ACTIVITY_Msk (0x1U << DW_IIC_INTR_ACTIVITY_Pos) +#define DW_IIC_M_ACTIVITY DW_IIC_INTR_ACTIVITY_Msk + +#define DW_IIC_M_STOP_DET_Pos (9U) +#define DW_IIC_M_STOP_DET_Msk (0x1U << DW_IIC_INTR_STOP_DET_Pos) +#define DW_IIC_M_STOP_DET DW_IIC_INTR_STOP_DET_Msk + +#define DW_IIC_M_START_DET_Pos (10U) +#define DW_IIC_M_START_DET_Msk (0x1U << DW_IIC_INTR_START_DET_Pos) +#define DW_IIC_M_START_DET DW_IIC_INTR_START_DET_Msk + +#define DW_IIC_M_GEN_CALL_Pos (11U) +#define DW_IIC_M_GEN_CALL_Msk (0x1U << DW_IIC_INTR_GEN_CALL_Pos) +#define DW_IIC_M_GEN_CALL DW_IIC_INTR_GEN_CALL_Msk + +#define DW_IIC_INTR_DEFAULT_MASK ( DW_IIC_M_RX_FULL | DW_IIC_M_TX_EMPTY | DW_IIC_M_TX_ABRT | DW_IIC_M_STOP_DET) + +/* IC_RAW_INTR_STAT, offset: 0x34 */ +#define DW_IIC_RAW_RX_UNDER_Pos (0U) +#define DW_IIC_RAW_RX_UNDER_Msk (0x1U << DW_IIC_INTR_RX_UNDER_Pos) +#define DW_IIC_RAW_RX_UNDER DW_IIC_INTR_RX_UNDER_Msk + +#define DW_IIC_RAW_RX_OVER_Pos (1U) +#define DW_IIC_RAW_RX_OVER_Msk (0x1U << DW_IIC_INTR_RX_OVER_Pos) +#define DW_IIC_RAW_RX_OVER DW_IIC_INTR_RX_OVER_Msk + +#define DW_IIC_RAW_RX_FULL_Pos (2U) +#define DW_IIC_RAW_RX_FULL_Msk (0x1U << DW_IIC_INTR_RX_FULL_Pos) +#define DW_IIC_RAW_RX_FULL DW_IIC_INTR_RX_FULL_Msk + +#define DW_IIC_RAW_TX_OVER_Pos (3U) +#define DW_IIC_RAW_TX_OVER_Msk (0x1U << DW_IIC_INTR_TX_OVER_Pos) +#define DW_IIC_RAW_TX_OVER DW_IIC_INTR_TX_OVER_Msk + +#define DW_IIC_RAW_TX_EMPTY_Pos (4U) +#define DW_IIC_RAW_TX_EMPTY_Msk (0x1U << DW_IIC_INTR_TX_EMPTY_Pos) +#define DW_IIC_RAW_TX_EMPTY DW_IIC_INTR_TX_EMPTY_Msk + +#define DW_IIC_RAW_RD_REQ_Pos (5U) +#define DW_IIC_RAW_RD_REQ_Msk (0x1U << DW_IIC_INTR_RD_REQ_Pos) +#define DW_IIC_RAW_RD_REQ DW_IIC_INTR_RD_REQ_Msk + +#define DW_IIC_RAW_TX_ABRT_Pos (6U) +#define DW_IIC_RAW_TX_ABRT_Msk (0x1U << DW_IIC_INTR_TX_ABRT_Pos) +#define DW_IIC_RAW_TX_ABRT DW_IIC_INTR_TX_ABRT_Msk + +#define DW_IIC_RAW_RX_DONE_Pos (7U) +#define DW_IIC_RAW_RX_DONE_Msk (0x1U << DW_IIC_INTR_RX_DONE_Pos) +#define DW_IIC_RAW_RX_DONE DW_IIC_INTR_RX_DONE_Msk + +#define DW_IIC_RAW_ACTIVITY_Pos (8U) +#define DW_IIC_RAW_ACTIVITY_Msk (0x1U << DW_IIC_INTR_ACTIVITY_Pos) +#define DW_IIC_RAW_ACTIVITY DW_IIC_INTR_ACTIVITY_Msk + +#define DW_IIC_RAW_STOP_DET_Pos (9U) +#define DW_IIC_RAW_STOP_DET_Msk (0x1U << DW_IIC_INTR_STOP_DET_Pos) +#define DW_IIC_RAW_STOP_DET DW_IIC_INTR_STOP_DET_Msk + +#define DW_IIC_RAW_START_DET_Pos (10U) +#define DW_IIC_RAW_START_DET_Msk (0x1U << DW_IIC_INTR_START_DET_Pos) +#define DW_IIC_RAW_START_DET DW_IIC_INTR_START_DET_Msk + +#define DW_IIC_RAW_GEN_CALL_Pos (11U) +#define DW_IIC_RAW_GEN_CALL_Msk (0x1U << DW_IIC_INTR_GEN_CALL_Pos) +#define DW_IIC_RAW_GEN_CALL DW_IIC_INTR_GEN_CALL_Msk + + +/* IC_ENABLE, offset: 0x6C */ +#define DW_IIC_ENABLE_Pos (0U) +#define DW_IIC_ENABLE_Msk (0x1U << DW_IIC_ENABLE_Pos) +#define DW_IIC_EN DW_IIC_ENABLE_Msk + +/* IC_STATUS, offset: 0x70 */ +#define DW_IIC_STATUS_ACTIVITY_Pos (0U) +#define DW_IIC_STATUS_ACTIVITY_Msk (0x1U << DW_IIC_STATUS_ACTIVITY_Pos) +#define DW_IIC_STATUS_ACTIVITY_STATE DW_IIC_STATUS_ACTIVITY_Msk + +#define DW_IIC_STATUS_TFNE_Pos (1U) +#define DW_IIC_STATUS_TFNE_Msk (0x1U << DW_IIC_STATUS_TFNE_Pos) +#define DW_IIC_TXFIFO_NOT_FULL_STATE DW_IIC_STATUS_TFNE_Msk + +#define DW_IIC_STATUS_TFE_Pos (2U) +#define DW_IIC_STATUS_TFE_Msk (0x1U << DW_IIC_STATUS_TFE_Pos) +#define DW_IIC_TXFIFO_EMPTY_STATE DW_IIC_STATUS_TFE_Msk + +#define DW_IIC_STATUS_RFNE_Pos (3U) +#define DW_IIC_STATUS_RFNE_Msk (0x1U << DW_IIC_STATUS_RFNE_Pos) +#define DW_IIC_RXFIFO_NOT_EMPTY_STATE DW_IIC_STATUS_RFNE_Msk + +#define DW_IIC_STATUS_REF_Pos (4U) +#define DW_IIC_STATUS_REF_Msk (0x1U << DW_IIC_STATUS_REF_Pos) +#define DW_IIC_RXFIFO_FULL_STATE DW_IIC_STATUS_REF_Msk + +#define DW_IIC_STATUS_MST_ACTIVITY_Pos (5U) +#define DW_IIC_STATUS_MST_ACTIVITY_Msk (0x1U << DW_IIC_STATUS_MST_ACTIVITY_Pos) +#define DW_IIC_MST_ACTIVITY_STATE DW_IIC_STATUS_MST_ACTIVITY_Msk + +#define DW_IIC_STATUS_SLV_ACTIVITY_Pos (6U) +#define DW_IIC_STATUS_SLV_ACTIVITY_Msk (0x1U << DW_IIC_STATUS_SLV_ACTIVITY_Pos) +#define DW_IIC_SLV_ACTIVITY_STATE DW_IIC_STATUS_SLV_ACTIVITY_Msk + +/* IC_TX_ABRT_SOURCE, offset: 0x80 */ +#define DW_IIC_TX_ABRT_7B_ADDR_NOACK_Pos (0U) +#define DW_IIC_TX_ABRT_7B_ADDR_NOACK_Msk (0x1U << DW_IIC_TX_ABRT_7B_ADDR_NOACK_Pos) +#define DW_IIC_TX_ABRT_7B_ADDR_NOACK DW_IIC_TX_ABRT_7B_ADDR_NOACK_Msk + +#define DW_IIC_TX_ABRT_10ADDR1_NOACK_Pos (1U) +#define DW_IIC_TX_ABRT_10ADDR1_NOACK_Msk (0x1U << DW_IIC_TX_ABRT_10ADDR1_NOACK_Pos) +#define DW_IIC_TX_ABRT_10ADDR1_NOACK DW_IIC_TX_ABRT_10ADDR1_NOACK_Msk + +#define DW_IIC_TX_ABRT_10ADDR2_NOACK_Pos (2U) +#define DW_IIC_TX_ABRT_10ADDR2_NOACK_Msk (0x1U << DW_IIC_TX_ABRT_10ADDR2_NOACK_Pos) +#define DW_IIC_TX_ABRT_10ADDR2_NOACK DW_IIC_TX_ABRT_10ADDR2_NOACK_Msk + +#define DW_IIC_TX_ABRT_TXDATA_NOACK_Pos (3U) +#define DW_IIC_TX_ABRT_TXDATA_NOACK_Msk (0x1U << DW_IIC_TX_ABRT_TXDATA_NOACK_Pos) +#define DW_IIC_TX_ABRT_TXDATA_NOACK DW_IIC_TX_ABRT_TXDATA_NOACK_Msk + +#define DW_IIC_TX_ABRT_GCALL_NOACK_Pos (4U) +#define DW_IIC_TX_ABRT_GCALL_NOACK_Msk (0x1U << DW_IIC_TX_ABRT_GCALL_NOACK_Pos) +#define DW_IIC_TX_ABRT_GCALL_NOACK DW_IIC_TX_ABRT_GCALL_NOACK_Msk + +#define DW_IIC_TX_ABRT_GCALL_READ_Pos (5U) +#define DW_IIC_TX_ABRT_GCALL_READ_Msk (0x1U << DW_IIC_TX_ABRT_GCALL_READ_Pos) +#define DW_IIC_TX_ABRT_GCALL_READ DW_IIC_TX_ABRT_GCALL_READ_Msk + +#define DW_IIC_TX_ABRT_HS_ACKDET_Pos (6U) +#define DW_IIC_TX_ABRT_HS_ACKDET_Msk (0x1U << DW_IIC_TX_ABRT_HS_ACKDET_Pos) +#define DW_IIC_TX_ABRT_HS_ACKDET DW_IIC_TX_ABRT_HS_ACKDET_Msk + +#define DW_IIC_TX_ABRT_SBYTE_ACKDET_Pos (7U) +#define DW_IIC_TX_ABRT_SBYTE_ACKDET_Msk (0x1U << DW_IIC_TX_ABRT_SBYTE_ACKDET_Pos) +#define DW_IIC_TX_ABRT_SBYTE_ACKDET DW_IIC_TX_ABRT_SBYTE_ACKDET_Msk + +#define DW_IIC_TX_ABRT_HS_NORSTRT_Pos (8U) +#define DW_IIC_TX_ABRT_HS_NORSTRT_Msk (0x1U << DW_IIC_TX_ABRT_HS_NORSTRT_Pos) +#define DW_IIC_TX_ABRT_HS_NORSTRT DW_IIC_TX_ABRT_HS_NORSTRT_Msk + +#define DW_IIC_TX_ABRT_SBYTE_NORSTRT_Pos (9U) +#define DW_IIC_TX_ABRT_SBYTE_NORSTRT_Msk (0x1U << DW_IIC_TX_ABRT_SBYTE_NORSTRT_Pos) +#define DW_IIC_TX_ABRT_SBYTE_NORSTRT DW_IIC_TX_ABRT_SBYTE_NORSTRT_Msk + +#define DW_IIC_TX_ABRT_10B_RD_NORSTRT_Pos (10U) +#define DW_IIC_TX_ABRT_10B_RD_NORSTRT_Msk (0x1U << DW_IIC_TX_ABRT_10B_RD_NORSTRT_Pos) +#define DW_IIC_TX_ABRT_10B_RD_NORSTRT DW_IIC_TX_ABRT_10B_RD_NORSTRT_Msk + +#define DW_IIC_TX_ABRT_ARB_MASTER_DIS_Pos (11U) +#define DW_IIC_TX_ABRT_ARB_MASTER_DIS_Msk (0x1U << DW_IIC_TX_ABRT_ARB_MASTER_DIS_Pos) +#define DW_IIC_TX_ABRT_ARB_MASTER_DIS DW_IIC_TX_ABRT_ARB_MASTER_DIS_Msk + +#define DW_IIC_TX_ABRT_ARB_LOST_Pos (12U) +#define DW_IIC_TX_ABRT_ARB_LOST_Msk (0x1U << DW_IIC_TX_ABRT_ARB_LOST_Pos) +#define DW_IIC_TX_ABRT_ARB_LOST DW_IIC_TX_ABRT_ARB_LOST_Msk + +#define DW_IIC_TX_ABRT_SLVFLUSH_TXFIFO_Pos (13U) +#define DW_IIC_TX_ABRT_SLVFLUSH_TXFIFO_Msk (0x1U << DW_IIC_TX_ABRT_SLVFLUSH_TXFIFO_Pos) +#define DW_IIC_TX_ABRT_SLVFLUSH_TXFIFO DW_IIC_TX_ABRT_SLVFLUSH_TXFIFO_Msk + +#define DW_IIC_TX_ABRT_SLV_ARBLOST_Pos (14U) +#define DW_IIC_TX_ABRT_SLV_ARBLOST_Msk (0x1U << DW_IIC_TX_ABRT_SLV_ARBLOST_Pos) +#define DW_IIC_TX_ABRT_SLV_ARBLOST DW_IIC_TX_ABRT_SLV_ARBLOST_Msk + +#define DW_IIC_TX_ABRT_SLVRD_INTX_Pos (15U) +#define DW_IIC_TX_ABRT_SLVRD_INTX_Msk (0x1U << DW_IIC_TX_ABRT_SLVRD_INTX_Pos) +#define DW_IIC_TX_ABRT_SLVRD_INTX DW_IIC_TX_ABRT_SLVRD_INTX_Msk + +/* IC_DMA_CR, offset: 0x88 */ +#define DW_IIC_DMA_CR_RDMAE_Pos (0U) +#define DW_IIC_DMA_CR_RDMAE_Msk (0x1U << DW_IIC_DMA_CR_RDMAE_Pos) +#define DW_IIC_DMA_CR_RDMAE DW_IIC_DMA_CR_RDMAE_Msk + +#define DW_IIC_DMA_CR_TDMAE_Pos (1U) +#define DW_IIC_DMA_CR_TDMAE_Msk (0x1U << DW_IIC_DMA_CR_TDMAE_Pos) +#define DW_IIC_DMA_CR_TDMAE DW_IIC_DMA_CR_TDMAE_Msk + +/* IC_DMA_TDLR, offset: 0x8C */ +#define DW_IIC_DMA_TDLR_Msk (0x7U) +/* IC_DMA_RDLR, offset: 0x90 */ +#define DW_IIC_DMA_RDLR_Msk (0x7U) + +/* IC_GEN_CALL_EN, offset: 0xA0 */ +//no this register +#define DW_IIC_GEN_CALL_EN_Pos (0U) +#define DW_IIC_GEN_CALL_EN_Msk (0x1U << DW_IIC_GEN_CALL_EN_Pos) +#define DW_IIC_GEN_CALL_EN DW_IIC_GEN_CALL_EN_Msk + +/* IC_FIFO_RST_EN, offset: 0xA4 */ +//no this register +#define DW_IIC_FIFO_RST_EN_Pos (0U) +#define DW_IIC_FIFO_RST_EN_Msk (0x1U << DW_IIC_FIFO_RST_EN_Pos) +#define DW_IIC_FIFO_RST_EN DW_IIC_FIFO_RST_EN_Msk + +#define TXFIFO_IRQ_TH (0x4U) +#define RXFIFO_IRQ_TH (0x2U) +#define IIC_MAX_FIFO (0x8U) + +/* IIC default value definitions */ +#define DW_IIC_TIMEOUT_DEF_VAL 0x1000U + +#define DW_IIC_EEPROM_MAX_WRITE_LEN 0X1U + +typedef struct { + volatile uint32_t IC_CON; /* Offset: 0x000 (R/W) I2C Control */ + volatile uint32_t IC_TAR; /* Offset: 0x004 (R/W) I2C target address */ + volatile uint32_t IC_SAR; /* Offset: 0x008 (R/W) I2C slave address */ + volatile uint32_t IC_HS_MADDR; /* Offset: 0x00C (R/W) I2C HS Master Mode Code Address */ + volatile uint32_t IC_DATA_CMD; /* Offset: 0x010 (R/W) I2C RX/TX Data Buffer and Command */ + volatile uint32_t IC_SS_SCL_HCNT; /* Offset: 0x014 (R/W) Standard speed I2C Clock SCL High Count */ + volatile uint32_t IC_SS_SCL_LCNT; /* Offset: 0x018 (R/W) Standard speed I2C Clock SCL Low Count */ + volatile uint32_t IC_FS_SCL_HCNT; /* Offset: 0x01C (R/W) Fast speed I2C Clock SCL High Count */ + volatile uint32_t IC_FS_SCL_LCNT; /* Offset: 0x020 (R/W) Fast speed I2C Clock SCL Low Count */ + volatile uint32_t IC_HS_SCL_HCNT; /* Offset: 0x024 (R/W) High speed I2C Clock SCL High Count*/ + volatile uint32_t IC_HS_SCL_LCNT; /* Offset: 0x028 (R/W) High speed I2C Clock SCL Low Count */ + volatile const uint32_t IC_INTR_STAT; /* Offset: 0x02C (R) I2C Interrupt Status */ + volatile uint32_t IC_INTR_MASK; /* Offset: 0x030 (R/W) I2C Interrupt Mask */ + volatile const uint32_t IC_RAW_INTR_STAT; /* Offset: 0x034 (R) I2C Raw Interrupt Status */ + volatile uint32_t IC_RX_TL; /* Offset: 0x038 (R/W) I2C Receive FIFO Threshold */ + volatile uint32_t IC_TX_TL; /* Offset: 0x03C (R/W) I2C Transmit FIFO Threshold */ + volatile const uint32_t IC_CLR_INTR; /* Offset: 0x040 (R) Clear combined and individual interrupts*/ + volatile const uint32_t IC_CLR_RX_UNDER; /* Offset: 0x044 (R) I2C Clear RX_UNDER interrupt */ + volatile const uint32_t IC_CLR_RX_OVER; /* Offset: 0x048 (R) I2C Clear RX_OVER interrupt */ + volatile const uint32_t IC_CLR_TX_OVER; /* Offset: 0x04C (R) I2C Clear TX_OVER interrupt */ + volatile const uint32_t IC_CLR_RD_REQ; /* Offset: 0x050 (R) I2C Clear RD_REQ interrupt */ + volatile const uint32_t IC_CLR_TX_ABRT; /* Offset: 0x054 (R) I2C Clear TX_ABRT interrupt */ + volatile const uint32_t IC_CLR_RX_DONE; /* Offset: 0x058 (R) I2C Clear RX_DONE interrupt */ + volatile const uint32_t IC_CLR_ACTIVITY; /* Offset: 0x05C (R) I2C Clear ACTIVITY interrupt */ + volatile const uint32_t IC_CLR_STOP_DET; /* Offset: 0x060 (R) I2C Clear STOP_DET interrupt */ + volatile const uint32_t IC_CLR_START_DET; /* Offset: 0x064 (R) I2C Clear START_DET interrupt */ + volatile const uint32_t IC_CLR_GEN_CALL; /* Offset: 0x068 (R) I2C Clear GEN_CAL interrupt */ + volatile uint32_t IC_ENABLE; /* Offset: 0x06C (R/W) I2C enable */ + volatile const uint32_t IC_STATUS; /* Offset: 0x070 (R) I2C status register */ + volatile const uint32_t IC_TXFLR; /* Offset: 0x074 (R) Transmit FIFO Level register */ + volatile const uint32_t IC_RXFLR; /* Offset: 0x078 (R) Receive FIFO Level Register */ + volatile uint32_t IC_SDA_HOLD; /* Offset: 0x07C (R/W) SDA hold time register */ + volatile uint32_t IC_TX_ABRT_SOURCE; /* Offset: 0x080 (R/W) I2C Transmit Abort Status Register */ + volatile uint32_t IC_SLV_DAT_NACK_ONLY; /* Offset: 0x084 (R/W) I2C Slave Address1 */ + volatile uint32_t IC_DMA_CR; /* Offset: 0x088 (R/W) DMA Control Register for transmit and receive handshaking interface */ + volatile uint32_t IC_DMA_TDLR; /* Offset: 0x08C (R/W) DMA Transmit Data Level */ + volatile uint32_t IC_DMA_RDLR; /* Offset: 0x090 (R/W) DMA Receive Data Level */ + volatile uint32_t IC_SDA_SETUP; /* Offset: 0x094 (R/W) I2C Slave Address2 */ + volatile uint32_t IC_ACK_GENERAL_CALL; /* Offset: 0x098 (R/W) I2C Slave Address3 */ + volatile uint32_t IC_ENABLE_STATUS; /* Offset: 0x09C (R/W) I2C address number in slave mode */ + volatile uint32_t IC_FS_SPKLEN; /* Offset: 0x0A0 (R/W) I2C general call mask register when I2C is in the slave mode */ + volatile uint32_t IC_HS_SPKLEN; /* Offset: 0x0A4 (R/W) I2C FIFO flush register when I2C is in the slave transfer mode*/ +} dw_iic_regs_t; + +static inline void dw_iic_enable(dw_iic_regs_t *iic_base) +{ + iic_base->IC_ENABLE = DW_IIC_EN; +} + +static inline void dw_iic_disable(dw_iic_regs_t *iic_base) +{ + /* First clear ACTIVITY, then Disable IIC */ + iic_base->IC_CLR_ACTIVITY; + iic_base->IC_ENABLE = ~DW_IIC_EN; +} + +static inline uint32_t dw_iic_get_iic_status(dw_iic_regs_t *iic_base) +{ + return iic_base->IC_ENABLE; +} + +static inline void dw_iic_enable_restart(dw_iic_regs_t *iic_base) +{ + iic_base->IC_CON |= DW_IIC_CON_RESTART_EN; +} + +static inline void dw_iic_master_enable_transmit_irq(dw_iic_regs_t *iic_base) +{ + iic_base->IC_INTR_MASK = DW_IIC_INTR_TX_EMPTY | DW_IIC_INTR_TX_OVER | DW_IIC_INTR_STOP_DET; + iic_base->IC_CLR_INTR; +} + +static inline void dw_iic_slave_enable_transmit_irq(dw_iic_regs_t *iic_base) +{ + iic_base->IC_INTR_MASK = DW_IIC_INTR_RD_REQ | DW_IIC_INTR_STOP_DET; + iic_base->IC_CLR_INTR; +} + +static inline void dw_iic_master_enable_receive_irq(dw_iic_regs_t *iic_base) +{ + iic_base->IC_INTR_MASK = DW_IIC_INTR_STOP_DET | DW_IIC_INTR_RX_FULL | DW_IIC_INTR_RX_OVER; + iic_base->IC_CLR_INTR; +} + +static inline void dw_iic_slave_enable_receive_irq(dw_iic_regs_t *iic_base) +{ + iic_base->IC_INTR_MASK = DW_IIC_INTR_STOP_DET | DW_IIC_INTR_RX_FULL; + iic_base->IC_CLR_INTR; +} + +static inline void dw_iic_clear_all_irq(dw_iic_regs_t *iic_base) +{ + iic_base->IC_CLR_INTR; + iic_base->IC_CLR_RX_UNDER; + iic_base->IC_CLR_RX_OVER; + iic_base->IC_CLR_TX_OVER; + iic_base->IC_CLR_RD_REQ; + iic_base->IC_CLR_TX_ABRT; + iic_base->IC_CLR_RX_DONE; + iic_base->IC_CLR_ACTIVITY; + iic_base->IC_CLR_STOP_DET; + iic_base->IC_CLR_START_DET; + iic_base->IC_CLR_GEN_CALL; +} + +static inline void dw_iic_set_sda_hold_time(dw_iic_regs_t *iic_base, uint32_t val) +{ + iic_base->IC_SDA_HOLD = val; +} + +static inline void dw_iic_flush_rxfifo(dw_iic_regs_t *iic_base) +{ + while (iic_base->IC_STATUS & DW_IIC_RXFIFO_NOT_EMPTY_STATE) + iic_base->IC_DATA_CMD; +} + +static inline void dw_iic_set_slave_10bit_addr_mode(dw_iic_regs_t *iic_base) +{ + iic_base->IC_CON |= DW_IIC_CON_SLAVE_ADDR_MODE; +} + +static inline void dw_iic_set_slave_7bit_addr_mode(dw_iic_regs_t *iic_base) +{ + iic_base->IC_CON &= ~DW_IIC_CON_SLAVE_ADDR_MODE; +} + +static inline void dw_iic_set_master_10bit_addr_mode(dw_iic_regs_t *iic_base) +{ + iic_base->IC_TAR |= DW_IIC_TAR_MASTER_ADDR_MODE; +} + +static inline void dw_iic_set_master_7bit_addr_mode(dw_iic_regs_t *iic_base) +{ + iic_base->IC_TAR &= ~DW_IIC_TAR_MASTER_ADDR_MODE; + iic_base->IC_CON &= ~DW_IIC_CON_MASTER_ADDR_MODE; +} + +static inline void dw_iic_set_standard_scl_hcnt(dw_iic_regs_t *iic_base, uint32_t cnt) +{ + iic_base->IC_SS_SCL_HCNT = cnt; +} + +static inline void dw_iic_set_standard_scl_lcnt(dw_iic_regs_t *iic_base, uint32_t cnt) +{ + iic_base->IC_SS_SCL_LCNT = cnt; +} + +static inline void dw_iic_set_fast_scl_hcnt(dw_iic_regs_t *iic_base, uint32_t cnt) +{ + iic_base->IC_FS_SCL_HCNT = cnt; +} + +static inline void dw_iic_set_fast_scl_lcnt(dw_iic_regs_t *iic_base, uint32_t cnt) +{ + iic_base->IC_FS_SCL_LCNT = cnt; +} + +static inline void dw_iic_set_high_scl_hcnt(dw_iic_regs_t *iic_base, uint32_t cnt) +{ + iic_base->IC_HS_SCL_HCNT = cnt; +} + +static inline void dw_iic_set_high_scl_lcnt(dw_iic_regs_t *iic_base, uint32_t cnt) +{ + iic_base->IC_HS_SCL_LCNT = cnt; +} + +static inline void dw_iic_set_own_address(dw_iic_regs_t *iic_base, uint32_t address) +{ + iic_base->IC_SAR = address; +} + +static inline void dw_iic_set_transmit_fifo_threshold(dw_iic_regs_t *iic_base, uint32_t level) +{ + iic_base->IC_TX_TL = level; +} + +static inline void dw_iic_set_receive_fifo_threshold(dw_iic_regs_t *iic_base, uint32_t level) +{ + iic_base->IC_RX_TL = level - 1U; +} + +static inline uint32_t dw_iic_get_transmit_fifo_num(dw_iic_regs_t *iic_base) +{ + return iic_base->IC_TXFLR; +} + +static inline uint32_t dw_iic_get_receive_fifo_num(dw_iic_regs_t *iic_base) +{ + return iic_base->IC_RXFLR; +} + +static inline void dw_iic_transmit_data(dw_iic_regs_t *iic_base, uint16_t data) +{ + iic_base->IC_DATA_CMD = data; +} + +static inline uint8_t dw_iic_receive_data(dw_iic_regs_t *iic_base) +{ + return (uint8_t)iic_base->IC_DATA_CMD; +} + +static inline void dw_iic_data_cmd(dw_iic_regs_t *iic_base) +{ + iic_base->IC_DATA_CMD = DW_IIC_DATA_CMD; +} + +static inline void dw_iic_data_cmd_stop(dw_iic_regs_t *iic_base) +{ + iic_base->IC_DATA_CMD = DW_IIC_DATA_CMD | (1<<9); +} + +static inline void dw_iic_fifo_rst(dw_iic_regs_t *iic_base, uint32_t en) +{ + //no this register + //iic_base->IC_FIFO_RST_EN = (en & DW_IIC_FIFO_RST_EN_Msk); +} + +static inline void dw_iic_dma_transmit_enable(dw_iic_regs_t *iic_base) +{ + iic_base->IC_DMA_CR |= DW_IIC_DMA_CR_TDMAE; +} + +static inline void dw_iic_dma_transmit_disable(dw_iic_regs_t *iic_base) +{ + iic_base->IC_DMA_CR &= ~DW_IIC_DMA_CR_TDMAE; +} + +static inline void dw_iic_dma_receive_enable(dw_iic_regs_t *iic_base) +{ + iic_base->IC_DMA_CR |= DW_IIC_DMA_CR_RDMAE; +} + +static inline void dw_iic_dma_receive_disable(dw_iic_regs_t *iic_base) +{ + iic_base->IC_DMA_CR &= ~DW_IIC_DMA_CR_RDMAE; +} + +static inline void dw_iic_dma_transmit_level(dw_iic_regs_t *iic_base, uint8_t level) +{ + iic_base->IC_DMA_TDLR = ((uint32_t)level & DW_IIC_DMA_TDLR_Msk); +} + +static inline void dw_iic_dma_receive_level(dw_iic_regs_t *iic_base, uint8_t level) +{ + iic_base->IC_DMA_RDLR = ((uint32_t)level & DW_IIC_DMA_RDLR_Msk); +} + +static inline uint32_t dw_iic_get_raw_interrupt_state(dw_iic_regs_t *iic_base) +{ + return iic_base->IC_RAW_INTR_STAT; +} + +static inline void dw_iic_disable_all_irq(dw_iic_regs_t *iic_base) +{ + iic_base->IC_INTR_MASK = 0U; +} + +static inline uint32_t dw_iic_read_clear_intrbits(dw_iic_regs_t *iic_base) +{ + uint32_t stat = 0U; + + stat = iic_base->IC_INTR_STAT; + + if (stat & DW_IIC_INTR_RX_UNDER) + { + iic_base->IC_CLR_RX_UNDER; + } + + if (stat & DW_IIC_INTR_RX_OVER) + { + iic_base->IC_CLR_RX_OVER; + } + + if (stat & DW_IIC_INTR_TX_OVER) + { + iic_base->IC_CLR_TX_OVER; + } + + if (stat & DW_IIC_INTR_RD_REQ) + { + iic_base->IC_CLR_RD_REQ; + } + + if (stat & DW_IIC_INTR_TX_ABRT) + { + iic_base->IC_TX_ABRT_SOURCE; + } + + if (stat & DW_IIC_INTR_RX_DONE) + { + iic_base->IC_CLR_RX_DONE; + } + + if (stat & DW_IIC_INTR_ACTIVITY) + { + iic_base->IC_CLR_ACTIVITY; + } + + if (stat & DW_IIC_INTR_STOP_DET) + { + iic_base->IC_CLR_STOP_DET; + } + + if (stat & DW_IIC_INTR_START_DET) + { + iic_base->IC_CLR_START_DET; + } + + if (stat & DW_IIC_INTR_GEN_CALL) + { + iic_base->IC_CLR_GEN_CALL; + } + + return stat; +} + +static inline uint32_t dw_iic_get_intrrupt_state(dw_iic_regs_t *iic_base) +{ + return iic_base->IC_INTR_STAT; +} + int rt_hw_i2c_init(void); #endif /* __DRV_HW_I2C_H__ */ From 2d5eb2669f3fd9b4a1b52cf25d19a3915b767cae Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Thu, 13 Jun 2024 11:04:39 +0800 Subject: [PATCH 14/48] bsp: cvitek: remove warning when building wdt driver ``` ./bsp/cvitek/drivers/drv_wdt.c: In function '_wdt_control': warning: assignment to 'void *' from 'unsigned int' makes pointer from integer without a cast [-Wint-conversion] 119 | wdt_device->parent.user_data = (rt_uint32_t)(*(rt_uint32_t *)arg); | ^ warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] 122 | *(rt_uint32_t *)arg = (rt_uint32_t)wdt_device->parent.user_data; | ^ ``` Rootcasue: It's not portable to store integar in a pointer. Solution: use global _wdt_dev to store the timeout value. Signed-off-by: Chen Wang --- bsp/cvitek/drivers/drv_wdt.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/bsp/cvitek/drivers/drv_wdt.c b/bsp/cvitek/drivers/drv_wdt.c index ddde93a6dc..8cbc233b8d 100644 --- a/bsp/cvitek/drivers/drv_wdt.c +++ b/bsp/cvitek/drivers/drv_wdt.c @@ -23,6 +23,7 @@ struct _cvi_wdt_dev struct rt_watchdog_device device; const char *name; rt_uint32_t base; + rt_uint32_t timeout; }; static struct _cvi_wdt_dev _wdt_dev[] = @@ -113,11 +114,11 @@ static rt_err_t _wdt_control(rt_watchdog_t *wdt_device, int cmd, void *arg) cvi_wdt_feed_en(reg_base); break; case RT_DEVICE_CTRL_WDT_SET_TIMEOUT: - csi_wdt_set_timeout(reg_base, *(rt_uint32_t *)arg); - wdt_device->parent.user_data = (rt_uint32_t)(*(rt_uint32_t *)arg); + wdt->timeout = *(rt_uint32_t *)arg; + csi_wdt_set_timeout(reg_base, wdt->timeout); break; case RT_DEVICE_CTRL_WDT_GET_TIMEOUT: - *(rt_uint32_t *)arg = (rt_uint32_t)wdt_device->parent.user_data; + *(rt_uint32_t *)arg = wdt->timeout; break; case RT_DEVICE_CTRL_WDT_GET_TIMELEFT: *(rt_uint32_t *)arg = (cvi_wdt_get_counter_value(reg_base) / (WDT_FREQ_DEFAULT / 1000U)); From 4ad194bb47101345ce3b3fa631ab2215a0c190c0 Mon Sep 17 00:00:00 2001 From: zhuzhuzhu <945386260@qq.com> Date: Wed, 17 Jul 2024 09:08:10 +0800 Subject: [PATCH 15/48] [fix] fix cromfs read out of mem range (#9197) Update dfs_cromfs.c --- components/dfs/dfs_v2/filesystems/cromfs/dfs_cromfs.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/components/dfs/dfs_v2/filesystems/cromfs/dfs_cromfs.c b/components/dfs/dfs_v2/filesystems/cromfs/dfs_cromfs.c index 0d82914df4..ae67887a4d 100644 --- a/components/dfs/dfs_v2/filesystems/cromfs/dfs_cromfs.c +++ b/components/dfs/dfs_v2/filesystems/cromfs/dfs_cromfs.c @@ -786,18 +786,18 @@ static ssize_t dfs_cromfs_read(struct dfs_file *file, void *buf, size_t count, o rt_err_t result = RT_EOK; file_info *fi = NULL; cromfs_info *ci = NULL; - uint32_t length = 0; + ssize_t length = 0; ci = (cromfs_info *)file->dentry->mnt->data; fi = (file_info *)file->vnode->data; - if (count < file->vnode->size - *pos) + if ((off_t)count < (off_t)file->vnode->size - *pos) { length = count; } else { - length = file->vnode->size - *pos; + length = (off_t)file->vnode->size - *pos; } if (length > 0) From 1ef2afbc932d1ad4dd8f1841ae96522233bf53f9 Mon Sep 17 00:00:00 2001 From: flyingcys Date: Sun, 2 Jun 2024 22:09:11 +0800 Subject: [PATCH 16/48] bsp: cvitek: re-wrote spi driver Rewrote the spi driver. Reuse the driver code from https://github.com/sophgo/cvi_alios_open, which is Apache 2.0 licenced. Signed-off-by: flyingcys Reviewed-by: Chen Wang --- bsp/cvitek/drivers/SConscript | 2 + bsp/cvitek/drivers/drv_spi.c | 405 +++++++++++----------- bsp/cvitek/drivers/drv_spi.h | 151 +------- bsp/cvitek/drivers/libraries/spi/dw_spi.c | 375 ++++++++++++++++++++ bsp/cvitek/drivers/libraries/spi/dw_spi.h | 246 +++++++++++++ 5 files changed, 842 insertions(+), 337 deletions(-) create mode 100644 bsp/cvitek/drivers/libraries/spi/dw_spi.c create mode 100644 bsp/cvitek/drivers/libraries/spi/dw_spi.h diff --git a/bsp/cvitek/drivers/SConscript b/bsp/cvitek/drivers/SConscript index d67ffc5e39..91961af61a 100755 --- a/bsp/cvitek/drivers/SConscript +++ b/bsp/cvitek/drivers/SConscript @@ -31,6 +31,8 @@ if GetDepend('BSP_USING_WDT'): if GetDepend(['BSP_USING_SPI']): src += ['drv_spi.c'] + src += ['libraries/spi/dw_spi.c'] + CPPPATH += [cwd + r'/libraries/spi'] if GetDepend('BSP_USING_PWM'): src += ['drv_pwm.c'] diff --git a/bsp/cvitek/drivers/drv_spi.c b/bsp/cvitek/drivers/drv_spi.c index 3e88af06f6..e268fa89d0 100644 --- a/bsp/cvitek/drivers/drv_spi.c +++ b/bsp/cvitek/drivers/drv_spi.c @@ -1,217 +1,231 @@ /* - * Copyright (c) 2006-2023, RT-Thread Development Team + * Copyright (c) 2006-2024, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2024-03-28 qiujingbao first version + * 2024-03-28 qiujingbao first version + * 2024/06/08 flyingcys fix transmission failure */ +#include +#include +#include + +#include "board.h" #include "drv_spi.h" + #include "drv_pinmux.h" -#define DBG_TAG "drv.spi" -#define DBG_LVL DBG_INFO +#define DBG_LEVEL DBG_LOG #include +#define LOG_TAG "drv.spi" -static struct cv1800_spi cv1800_spi_obj[] = +struct _device_spi { -#ifdef BSP_USING_SPI - { - .spi_id = SPI2, - .device_name = "spi2", - .fifo_len = SPI_TXFTLR, - }, -#endif + struct rt_spi_bus spi_bus; + struct dw_spi dws; + char *device_name; }; -static struct spi_regs *get_spi_base(uint8_t spi_id) +static struct _device_spi _spi_obj[] = { - struct spi_regs *spi_base = NULL; - - switch (spi_id) +#ifdef BSP_USING_SPI0 { - case SPI0: - spi_base = (struct spi_regs *)SPI0_BASE; - break; - case SPI1: - spi_base = (struct spi_regs *)SPI1_BASE; - break; - case SPI2: - spi_base = (struct spi_regs *)SPI2_BASE; - break; - case SPI3: - spi_base = (struct spi_regs *)SPI3_BASE; - break; - } + .dws.regs = (void *)DW_SPI0_BASE, + .dws.irq = DW_SPI0_IRQn, + .dws.index = 0, + .device_name = "spi0", + }, +#endif /* BSP_USING_SPI0 */ +#ifdef BSP_USING_SPI1 + { + .dws.regs = (void *)DW_SPI1_BASE, + .dws.irq = DW_SPI1_IRQn, + .dws.index = 0, + .device_name = "spi1", + }, +#endif /* BSP_USING_SPI1 */ +#ifdef BSP_USING_SPI2 + { + .dws.regs = (void *)DW_SPI2_BASE, + .dws.irq = DW_SPI2_IRQn, + .dws.index = 0, + .device_name = "spi2", + }, +#endif /* BSP_USING_SPI2 */ +#ifdef BSP_USING_SPI3 + { + .dws.regs = (void *)DW_SPI3_BASE, + .dws.irq = DW_SPI3_IRQn, + .dws.index = 0, + .device_name = "spi3", + }, +#endif /* BSP_USING_SPI3 */ +}; - return spi_base; -} - -static rt_err_t drv_spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration) +static rt_err_t spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg) { - rt_err_t ret = RT_EOK; - struct cv1800_spi *spi_dev = RT_NULL; - uint32_t mode; - - spi_dev = (struct cv1800_spi *)(device->bus->parent.user_data); - - spi_dev->data_width = configuration->data_width; - - /* disable spi */ - spi_enable(spi_dev->reg, 0); - - /* clear irq */ - spi_clear_irq(spi_dev->reg, SPI_IRQ_MSAK); - - /* set clk */ - ret = spi_set_frequency(spi_dev->reg, configuration->max_hz); - if (ret) - return ret; - - /* set mode */ - ret = gen_spi_mode(configuration, &mode); - if (ret) - return ret; - - spi_set_mode(spi_dev->reg, mode); - - /* set cs */ - spi_enable_cs(spi_dev->reg, 0x1); - - spi_enable(spi_dev->reg, 0x1); - - mode = mmio_read_32((uintptr_t)&spi_dev->reg->spi_ctrl0); - LOG_D("mode: %x", mode); - mode = mmio_read_32((uintptr_t)&spi_dev->reg->spi_baudr); - LOG_D("spi_baudr: %x", mode); - - return ret; -} - -int hw_spi_recv(struct cv1800_spi *dev) { - uint32_t rever; - uint32_t tem; - int ret; - - rever = mmio_read_32((uintptr_t)&dev->reg->spi_rxflr); - ret = (int)rever; - - while (rever) - { - tem = mmio_read_32((uintptr_t)&dev->reg->spi_dr); - - if (dev->recv_buf < dev->recv_end) - { - if (dev->data_width == 8) - *(uint8_t *)(dev->recv_buf) = tem; - else - *(uint16_t *)(dev->recv_buf) = tem; - } - else - { - return 0; - } - - rever--; - dev->recv_buf += dev->data_width >> 3; - } - return ret; -} - -int hw_spi_send(struct cv1800_spi *dev) { - uint32_t txflr; - uint32_t max; - uint16_t value; - - txflr = mmio_read_32((uintptr_t)&dev->reg->spi_txflr); - max = dev->fifo_len - txflr; - - while (max) - { - if (dev->send_end - dev->send_buf) - { - if (dev->data_width == 8) - value = *(uint8_t *)(dev->send_buf); - else - value = *(uint16_t *)(dev->send_buf); - } - else - { - return 0; - } - - mmio_write_32((uintptr_t)&dev->reg->spi_dr, value); - dev->send_buf += dev->data_width >> 3; - max--; - } - - return 0; -} -static rt_ssize_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message) { - int ret = 0; - struct cv1800_spi *spi_dev; - RT_ASSERT(device != RT_NULL); RT_ASSERT(device->bus != RT_NULL); - RT_ASSERT(message != RT_NULL); + RT_ASSERT(device->bus->parent.user_data != RT_NULL); + RT_ASSERT(cfg != RT_NULL); - spi_dev = (struct cv1800_spi *)(device->bus->parent.user_data); + rt_err_t ret = RT_EOK; + struct _device_spi *spi = (struct _device_spi *)device->bus->parent.user_data; + struct dw_spi *dws = &spi->dws; - if (message->send_buf != RT_NULL) + rt_uint8_t mode; + + LOG_D("spi_configure input"); + + /* set cs low when spi idle */ + writel(0, (void *)0x030001d0); + + if (cfg->mode & RT_SPI_SLAVE) { - spi_dev->send_buf = message->send_buf; - spi_dev->send_end = (void *)((uint8_t *)spi_dev->send_buf + message->length); + LOG_E("invalid mode: %d", cfg->mode); + return -RT_EINVAL; } - if (message->recv_buf != RT_NULL) + spi_reset_chip(dws); + spi_hw_init(dws); + spi_enable_chip(dws, 0); + + LOG_D("cfg->max_hz: %d", cfg->max_hz); + dw_spi_set_clock(dws, SPI_REF_CLK, cfg->max_hz); + + LOG_D("cfg->data_width: %d", cfg->data_width); + if (dw_spi_set_data_frame_len(dws, (uint32_t)cfg->data_width) < 0) { - spi_dev->recv_buf = message->recv_buf; - spi_dev->recv_end = (void *)((uint8_t *)spi_dev->recv_buf + message->length); + LOG_E("dw_spi_set_data_frame_len failed...\n"); + return -RT_ERROR; } - /* if user use their cs */ - if (message->cs_take && device->cs_pin != PIN_NONE) - rt_pin_write(device->cs_pin, PIN_LOW); - - if (message->send_buf) + LOG_D("cfg->mode: %08x", cfg->mode); + switch (cfg->mode & RT_SPI_MODE_3) { - while (spi_dev->send_buf != spi_dev->send_end) - { - hw_spi_send(spi_dev); - } + case RT_SPI_MODE_0: + mode = SPI_FORMAT_CPOL0_CPHA0; + break; - /* wait for complete */ - while (mmio_read_32((uintptr_t)&spi_dev->reg->spi_txflr)) {} + case RT_SPI_MODE_1: + mode = SPI_FORMAT_CPOL0_CPHA1; + break; - ret = message->length; + case RT_SPI_MODE_2: + mode = SPI_FORMAT_CPOL1_CPHA0; + break; + + case RT_SPI_MODE_3: + mode = SPI_FORMAT_CPOL1_CPHA1; + break; + + default: + LOG_E("spi configure mode error %x\n", cfg->mode); + break; } - if (message->recv_buf) - { - while (spi_dev->recv_buf != spi_dev->recv_end) - { - hw_spi_recv(spi_dev); - } + dw_spi_set_polarity_and_phase(dws, mode); - ret = message->length; - } + dw_spi_set_cs(dws, 1, 0); - if (message->cs_release && device->cs_pin != PIN_NONE) - rt_pin_write(device->cs_pin, PIN_HIGH); + spi_enable_chip(dws, 1); - return ret; + return RT_EOK; } -const static struct rt_spi_ops drv_spi_ops = +static rt_err_t dw_spi_transfer_one(struct dw_spi *dws, const void *tx_buf, void *rx_buf, uint32_t len, enum transfer_type tran_type) { - drv_spi_configure, - spixfer, + uint8_t imask = 0; + uint16_t txlevel = 0; + + dws->tx = NULL; + dws->tx_end = NULL; + dws->rx = NULL; + dws->rx_end = NULL; + + if (tx_buf != NULL) { + dws->tx = tx_buf; + dws->tx_end = dws->tx + len; + } + + if (rx_buf != NULL) { + dws->rx = rx_buf; + dws->rx_end = dws->rx + len; + } + + dws->rx_len = len / dws->n_bytes; + dws->tx_len = len / dws->n_bytes; + + spi_enable_chip(dws, 0); + + /* For poll mode just disable all interrupts */ + spi_mask_intr(dws, 0xff); + + /* set tran mode */ + set_tran_mode(dws); + + /* cs0 */ + dw_spi_set_cs(dws, true, 0); + + /* enable spi */ + spi_enable_chip(dws, 1); + + rt_hw_us_delay(10); + + if (tran_type == POLL_TRAN) + { + if (poll_transfer(dws) < 0) + return -RT_ERROR; + } + else + { + return -RT_ENOSYS; + } + + return RT_EOK; +} + +static rt_ssize_t spi_xfer(struct rt_spi_device *device, struct rt_spi_message *message) +{ + RT_ASSERT(device != RT_NULL); + RT_ASSERT(device->bus != RT_NULL); + RT_ASSERT(device->bus->parent.user_data != RT_NULL); + RT_ASSERT(message != RT_NULL); + + struct _device_spi *spi = (struct _device_spi *)device->bus->parent.user_data; + struct dw_spi *dws = &spi->dws; + int32_t ret = 0; + + if (message->send_buf && message->recv_buf) + { + ret = dw_spi_transfer_one(dws, message->send_buf, message->recv_buf, message->length, POLL_TRAN); + + } + else if (message->send_buf) + { + ret = dw_spi_transfer_one(dws, message->send_buf, RT_NULL, message->length, POLL_TRAN); + + } + else if (message->recv_buf) + { + ret = dw_spi_transfer_one(dws, RT_NULL, message->recv_buf, message->length, POLL_TRAN); + + } + + return message->length; +} + +static const struct rt_spi_ops _spi_ops = +{ + .configure = spi_configure, + .xfer = spi_xfer, }; #if defined(BOARD_TYPE_MILKV_DUO) || defined(BOARD_TYPE_MILKV_DUO_SPINOR) || defined(BOARD_TYPE_MILKV_DUO256M) || defined(BOARD_TYPE_MILKV_DUO256M_SPINOR) - +// For Duo / Duo 256m, only SPI2 are exported on board. #ifdef BSP_USING_SPI0 static const char *pinname_whitelist_spi0_sck[] = { NULL, @@ -283,54 +297,49 @@ static const char *pinname_whitelist_spi3_cs[] = { static void rt_hw_spi_pinmux_config() { #ifdef BSP_USING_SPI0 - pinmux_config(BSP_SPI0_SCK_PINNAME, SPI0_SCK, pinname_whitelist_spi0_sck); - pinmux_config(BSP_SPI0_SDO_PINNAME, SPI0_SDO, pinname_whitelist_spi0_sdo); - pinmux_config(BSP_SPI0_SDI_PINNAME, SPI0_SDI, pinname_whitelist_spi0_sdi); - pinmux_config(BSP_SPI0_CS_PINNAME, SPI0_CS_X, pinname_whitelist_spi0_cs); + pinmux_config(BSP_SPI0_SCK_PINNAME, SPI0_SCK, pinname_whitelist_spi0_sck); + pinmux_config(BSP_SPI0_SDO_PINNAME, SPI0_SDO, pinname_whitelist_spi0_sdo); + pinmux_config(BSP_SPI0_SDI_PINNAME, SPI0_SDI, pinname_whitelist_spi0_sdi); + pinmux_config(BSP_SPI0_CS_PINNAME, SPI0_CS_X, pinname_whitelist_spi0_cs); #endif /* BSP_USING_SPI0 */ #ifdef BSP_USING_SPI1 - pinmux_config(BSP_SPI1_SCK_PINNAME, SPI1_SCK, pinname_whitelist_spi1_sck); - pinmux_config(BSP_SPI1_SDO_PINNAME, SPI1_SDO, pinname_whitelist_spi1_sdo); - pinmux_config(BSP_SPI1_SDI_PINNAME, SPI1_SDI, pinname_whitelist_spi1_sdi); - pinmux_config(BSP_SPI1_CS_PINNAME, SPI1_CS_X, pinname_whitelist_spi1_cs); + pinmux_config(BSP_SPI1_SCK_PINNAME, SPI1_SCK, pinname_whitelist_spi1_sck); + pinmux_config(BSP_SPI1_SDO_PINNAME, SPI1_SDO, pinname_whitelist_spi1_sdo); + pinmux_config(BSP_SPI1_SDI_PINNAME, SPI1_SDI, pinname_whitelist_spi1_sdi); + pinmux_config(BSP_SPI1_CS_PINNAME, SPI1_CS_X, pinname_whitelist_spi1_cs); #endif /* BSP_USING_SPI1 */ #ifdef BSP_USING_SPI2 - pinmux_config(BSP_SPI2_SCK_PINNAME, SPI2_SCK, pinname_whitelist_spi2_sck); - pinmux_config(BSP_SPI2_SDO_PINNAME, SPI2_SDO, pinname_whitelist_spi2_sdo); - pinmux_config(BSP_SPI2_SDI_PINNAME, SPI2_SDI, pinname_whitelist_spi2_sdi); - pinmux_config(BSP_SPI2_CS_PINNAME, SPI2_CS_X, pinname_whitelist_spi2_cs); + pinmux_config(BSP_SPI2_SCK_PINNAME, SPI2_SCK, pinname_whitelist_spi2_sck); + pinmux_config(BSP_SPI2_SDO_PINNAME, SPI2_SDO, pinname_whitelist_spi2_sdo); + pinmux_config(BSP_SPI2_SDI_PINNAME, SPI2_SDI, pinname_whitelist_spi2_sdi); + pinmux_config(BSP_SPI2_CS_PINNAME, SPI2_CS_X, pinname_whitelist_spi2_cs); #endif /* BSP_USING_SPI2 */ #ifdef BSP_USING_SPI3 - pinmux_config(BSP_SPI3_SCK_PINNAME, SPI3_SCK, pinname_whitelist_spi3_sck); - pinmux_config(BSP_SPI3_SDO_PINNAME, SPI3_SDO, pinname_whitelist_spi3_sdo); - pinmux_config(BSP_SPI3_SDI_PINNAME, SPI3_SDI, pinname_whitelist_spi3_sdi); - pinmux_config(BSP_SPI3_CS_PINNAME, SPI3_CS_X, pinname_whitelist_spi3_cs); + pinmux_config(BSP_SPI3_SCK_PINNAME, SPI3_SCK, pinname_whitelist_spi3_sck); + pinmux_config(BSP_SPI3_SDO_PINNAME, SPI3_SDO, pinname_whitelist_spi3_sdo); + pinmux_config(BSP_SPI3_SDI_PINNAME, SPI3_SDI, pinname_whitelist_spi3_sdi); + pinmux_config(BSP_SPI3_CS_PINNAME, SPI3_CS_X, pinname_whitelist_spi3_cs); #endif /* BSP_USING_SPI3 */ } int rt_hw_spi_init(void) { rt_err_t ret = RT_EOK; - struct spi_regs *reg = NULL; + struct dw_spi *dws; rt_hw_spi_pinmux_config(); - for (rt_size_t i = 0; i < sizeof(cv1800_spi_obj) / sizeof(struct cv1800_spi); i++) { - /* set reg base addr */ - reg = get_spi_base(cv1800_spi_obj[i].spi_id); - if (!reg) - return -RT_ERROR; - - cv1800_spi_obj[i].reg = reg; - cv1800_spi_obj[i].spi_bus.parent.user_data = &cv1800_spi_obj[i]; - - /* register spix bus */ - ret = rt_spi_bus_register(&cv1800_spi_obj[i].spi_bus, cv1800_spi_obj[i].device_name, &drv_spi_ops); + for (rt_size_t i = 0; i < sizeof(_spi_obj) / sizeof(struct _device_spi); i++) + { + _spi_obj[i].spi_bus.parent.user_data = (void *)&_spi_obj[i]; + ret = rt_spi_bus_register(&_spi_obj[i].spi_bus, _spi_obj[i].device_name, &_spi_ops); } + RT_ASSERT(ret == RT_EOK); + return ret; } INIT_BOARD_EXPORT(rt_hw_spi_init); diff --git a/bsp/cvitek/drivers/drv_spi.h b/bsp/cvitek/drivers/drv_spi.h index 2e20b15b2e..9ee398371d 100644 --- a/bsp/cvitek/drivers/drv_spi.h +++ b/bsp/cvitek/drivers/drv_spi.h @@ -5,151 +5,24 @@ * * Change Logs: * Date Author Notes - * 2024-03-28 qiujingbao first version + * 2024-03-28 qiujingbao first version + * 2024/06/08 flyingcys fix transmission failure */ #ifndef __DRV_SPI_H__ #define __DRV_SPI_H__ -#include "rtdevice.h" -#include -#include - #include "mmio.h" -#include "pinctrl.h" +#include "dw_spi.h" -#define SPI0 0x0 -#define SPI1 0x1 -#define SPI2 0x2 -#define SPI3 0x3 +#define DW_SPI_REG_SIZE (0x10000UL) +#define DW_SPI0_BASE (0x04180000UL) +#define DW_SPI1_BASE (DW_SPI0_BASE + 1 * DW_SPI_REG_SIZE) +#define DW_SPI2_BASE (DW_SPI0_BASE + 2 * DW_SPI_REG_SIZE) +#define DW_SPI3_BASE (DW_SPI0_BASE + 3 * DW_SPI_REG_SIZE) -#define SPI0_BASE 0x04180000 -#define SPI1_BASE 0x04190000 -#define SPI2_BASE 0x041A0000 -#define SPI3_BASE 0x041B0000 - -#define SPI_IRQ_MSAK 0x3e -#define SPI_FREQUENCY 187500000 - -/* Transmit FiFO Threshold Level */ -#define SPI_TXFTLR 0xf - -#define SPI_CTRL0_DATA_FREAM_SHIFT 0 -#define SPI_CTRL0_FREAM_FORMAT_SHIFT 4 -#define SPI_CTRL0_CPHA_SHIFT 6 -#define SPI_CTRL0_CPOL_SHIFT 7 -#define SPI_CTRL0_TRANS_MODE 8 -#define SPI_CTRL0_LOOP_SHIFT 11 -#define SPI_CTRL0_CTRL_FREAM_SHIFT 12 - -struct cv1800_spi { - uint8_t spi_id; - char *device_name; - - uint8_t fifo_len; - uint8_t data_width; - - const void *send_buf; - void *recv_buf; - - const void *send_end; - void *recv_end; - - struct rt_spi_bus spi_bus; - struct spi_regs *reg; -}; - -struct spi_regs { - uint32_t spi_ctrl0; // 0x00 - uint32_t spi_ctrl1; // 0x04 - uint32_t spi_ssienr; // 0x08 - uint32_t spi_mwcr; // 0x0c - uint32_t spi_ser; // 0x10 - uint32_t spi_baudr; // 0x14 - uint32_t spi_txftlr; // 0x18 - uint32_t spi_rxftlr; // 0x1c - uint32_t spi_txflr; // 0x20 - uint32_t spi_rxflr; // 0x24 - uint32_t spi_sr; // 0x28 - uint32_t spi_imr; // 0x2c - uint32_t spi_isr; // 0x30 - uint32_t spi_risr; // 0x34 - uint32_t spi_txoicr; // 0x38 - uint32_t spi_rxoicr; // 0x3c - uint32_t spi_rxuicr; // 0x40 - uint32_t spi_msticr; // 0x44 - uint32_t spi_icr; // 0x48 - uint32_t spi_dmacr; // 0x4c - uint32_t spi_dmatdlr; // 0x50 - uint32_t spi_dmardlr; // 0x54 - uint32_t spi_idr; // 0x58 - uint32_t spi_version; // 0x5c - uint32_t spi_dr; // 0x60 - uint32_t spi_rx_sample_dly; // 0xf0 - uint32_t spi_cs_override; // 0xf4 -}; - -uint32_t gen_spi_mode(struct rt_spi_configuration *cfg, uint32_t *mode) -{ - uint32_t value = 0; - - if (cfg->data_width != 8 && cfg->data_width != 16) - return -1; - - value |= (cfg->data_width - 1) >> SPI_CTRL0_DATA_FREAM_SHIFT; - value |= cfg->mode >> SPI_CTRL0_CPHA_SHIFT; - - *mode = value; - return 0; -} - -/* set spi mode */ -static inline void spi_set_mode(struct spi_regs *reg, uint32_t mode) -{ - mmio_write_32((uintptr_t)®->spi_ctrl0, mode); -} - -/* clear irq */ -static inline void spi_clear_irq(struct spi_regs *reg, uint32_t mode) -{ - mmio_write_32((uintptr_t)®->spi_imr, mode); -} - -static inline void spi_enable_cs(struct spi_regs *reg, uint32_t enable) -{ - if (enable) - enable = 0x1; - else - enable = 0x0; - - mmio_write_32((uintptr_t)®->spi_ser, enable); -} - -/* set spi frequency*/ -static inline rt_err_t spi_set_frequency(struct spi_regs *reg, uint32_t speed) -{ - uint16_t value; - - /* The value of the BAUDR register must be an even number between 2-65534 */ - value = SPI_FREQUENCY / speed; - if (value % 2 != 0) - value++; - - if (value < 4 || value > 65534) - value = 4; - - mmio_write_32((uintptr_t)®->spi_baudr, value); - - return RT_EOK; -} - -static inline void spi_enable(struct spi_regs *reg, uint32_t enable) -{ - if (enable) - enable = 0x1; - else - enable = 0x0; - - mmio_write_32((uintptr_t)®->spi_ssienr, enable); -} +#define DW_SPI0_IRQn 54 +#define DW_SPI1_IRQn 55 +#define DW_SPI2_IRQn 56 +#define DW_SPI3_IRQn 56 #endif /* __DRV_SPI_H__ */ diff --git a/bsp/cvitek/drivers/libraries/spi/dw_spi.c b/bsp/cvitek/drivers/libraries/spi/dw_spi.c new file mode 100644 index 0000000000..1c098e15ba --- /dev/null +++ b/bsp/cvitek/drivers/libraries/spi/dw_spi.c @@ -0,0 +1,375 @@ +/* + * Copyright (C) Cvitek Co., Ltd. 2019-2020. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include + +#include "mmio.h" +#include "dw_spi.h" + +#include + +#ifdef SPI_DEBUG +#define SP_DEBUG_LOG printf +#else +#define SP_DEBUG_LOG +#endif + +/* Restart the controller, disable all interrupts, clean rx fifo */ +void spi_hw_init(struct dw_spi *dws) +{ + /* + * Try to detect the FIFO depth if not set by interface driver, + * the depth could be from 2 to 256 from HW spec + */ + if (!dws->fifo_len) { + uint32_t fifo; + + for (fifo = 1; fifo < 256; fifo++) { + dw_writel(dws, CVI_DW_SPI_TXFTLR, fifo); + if (fifo != dw_readl(dws, CVI_DW_SPI_TXFTLR)) + break; + } + dw_writel(dws, CVI_DW_SPI_TXFTLR, 0); + + dws->fifo_len = (fifo == 1) ? 0 : fifo; + + SP_DEBUG_LOG("Detected FIFO size: %u bytes\n", dws->fifo_len); + } +} + +uint32_t min3(uint32_t a, uint32_t b, uint32_t c) +{ + uint32_t tmp; + + tmp = (a < b) ? a : b; + return (tmp < c) ? tmp : c; +} + +static inline void cpu_relax(void) +{ + //asm volatile("" ::: "memory"); +} + +static inline uint32_t tx_max(struct dw_spi *dws) +{ + uint32_t tx_left, tx_room, rxtx_gap, temp; + cpu_relax(); + tx_left = dws->tx_len; + tx_room = dws->fifo_len - dw_readl(dws, CVI_DW_SPI_TXFLR); + + /* + * Another concern is about the tx/rx mismatch, we + * though to use (dws->fifo_len - rxflr - txflr) as + * one maximum value for tx, but it doesn't cover the + * data which is out of tx/rx fifo and inside the + * shift registers. So a control from sw point of + * view is taken. + */ + + SP_DEBUG_LOG("tx left: %#x, tx room: %#x\n", tx_left, tx_room); + if (dws->rx != NULL && dws->tx != NULL) { + cpu_relax(); + rxtx_gap = dws->fifo_len - (dws->rx_len - dws->tx_len); + temp = min3(tx_left, tx_room, (uint32_t)(rxtx_gap)); + } else { + temp = tx_left < tx_room ? tx_left : tx_room; + } + + SP_DEBUG_LOG("temp: %#x\n", temp); + return temp; +} + +void dw_writer(struct dw_spi *dws) +{ + uint32_t max; + uint16_t txw = 0; + + max = tx_max(dws); + SP_DEBUG_LOG("max: %#x \n", max); + while (max--) { + if (dws->tx) { + if (dws->n_bytes == 1) + txw = *(uint8_t *)(dws->tx); + else + txw = *(uint16_t *)(dws->tx); + } + dw_writel(dws, CVI_DW_SPI_DR, txw); + dws->tx += dws->n_bytes; + --dws->tx_len; + } +} + +static inline uint32_t rx_max(struct dw_spi *dws) +{ + uint32_t temp; + uint32_t rx_left = dws->rx_len; + uint32_t data_in_fifo = dw_readl(dws, CVI_DW_SPI_RXFLR); + + temp = (rx_left < data_in_fifo ? rx_left : data_in_fifo); + SP_DEBUG_LOG("data_in_fifo:%u temp: %u\n", data_in_fifo, temp); + return temp; +} + +int dw_spi_check_status(struct dw_spi *dws, bool raw) +{ + uint32_t irq_status; + int ret = 0; + + if (raw) + irq_status = dw_readl(dws, CVI_DW_SPI_RISR); + else + irq_status = dw_readl(dws, CVI_DW_SPI_ISR); + + if (irq_status & CVI_SPI_INT_RXOI) { + SP_DEBUG_LOG("RX FIFO overflow detected\n"); + ret = -1; + } + + if (irq_status & CVI_SPI_INT_RXUI) { + SP_DEBUG_LOG("RX FIFO underflow detected\n"); + ret = -1; + } + + if (irq_status & CVI_SPI_INT_TXOI) { + SP_DEBUG_LOG("TX FIFO overflow detected\n"); + ret = -1; + } + + if (ret) + spi_reset_chip(dws); + + return ret; +} + +void dw_reader(struct dw_spi *dws) +{ + uint32_t max; + uint16_t rxw; + + max = rx_max(dws); + SP_DEBUG_LOG("max: %#x \n", max); + while (max--) { + rxw = dw_readl(dws, CVI_DW_SPI_DR); + if (dws->rx) { + if (dws->n_bytes == 1) + *(uint8_t *)(dws->rx) = rxw; + else + *(uint16_t *)(dws->rx) = rxw; + dws->rx += dws->n_bytes; + } + --dws->rx_len; + } +} + +int spi_delay_to_ns(struct spi_delay *_delay, struct dw_spi *dws) +{ + uint32_t delay = _delay->value; + uint32_t unit = _delay->unit; + uint32_t hz; + + if (!delay) + return 0; + + switch (unit) { + case SPI_DELAY_UNIT_USECS: + delay *= 1000; + break; + case SPI_DELAY_UNIT_NSECS: /* nothing to do here */ + break; + case SPI_DELAY_UNIT_SCK: + /* clock cycles need to be obtained from spi_transfer */ + if (!dws) + return -1; + /* if there is no effective speed know, then approximate + * by underestimating with half the requested hz + */ + hz = dws->speed_hz / 2; + if (!hz) + return -1; + delay *= DIV_ROUND_UP(1000000000, hz); + break; + default: + return -EINVAL; + } + + return delay; +} + +static void _spi_transfer_delay_ns(uint32_t ns) +{ + if (!ns) + return; + if (ns <= 1000) { + rt_hw_us_delay(1); + } else { + uint32_t us = DIV_ROUND_UP(ns, 1000); + rt_hw_us_delay(us); + } +} + +int spi_delay_exec(struct spi_delay *_delay, struct dw_spi *dws) +{ + int delay; + + if (!_delay) + return -1; + + delay = spi_delay_to_ns(_delay, dws); + if (delay < 0) + return delay; + + _spi_transfer_delay_ns(delay); + + return 0; +} + +int poll_transfer(struct dw_spi *dws) +{ + struct spi_delay delay; + uint16_t nbits; + delay.unit = SPI_DELAY_UNIT_SCK; + nbits = dws->n_bytes * BITS_PER_BYTE; + int ret = 0; + + do + { + dw_writer(dws); + cpu_relax(); + + delay.value = nbits * (dws->rx_len - dws->tx_len); + spi_delay_exec(&delay, dws); + dw_reader(dws); + cpu_relax(); + ret = dw_spi_check_status(dws, true); + if (ret) + return ret; + } while (dws->rx_len && dws->tx_len); + + return 0; +} + +void set_tran_mode(struct dw_spi *dws) +{ + uint32_t reg = dw_readl(dws, CVI_DW_SPI_CTRLR0); + uint8_t tmode; + + if (dws->rx && dws->tx) { + tmode = CVI_SPI_TMOD_TR; + } else if (dws->rx) { + tmode = CVI_SPI_TMOD_RO; + } else { + tmode = CVI_SPI_TMOD_TO; + } + reg &= ~CVI_SPI_TMOD_MASK; + reg |= (tmode << CVI_SPI_TMOD_OFFSET); + + dw_writel(dws, CVI_DW_SPI_CTRLR0, reg); +} + +void dw_spi_set_controller_mode(struct dw_spi *dws, uint8_t enable_master) +{ + /* do not support to switch controller mode, it is default master mode */ +} + +void dw_spi_set_cs(struct dw_spi *dws, bool enable, uint32_t index) +{ + uint32_t reg = dw_readl(dws, CVI_DW_SPI_SER); + + if (enable) + dw_writel(dws, CVI_DW_SPI_SER, reg | BIT(index)); + else + dw_writel(dws, CVI_DW_SPI_SER, reg & ~BIT(index)); +} + +void dw_spi_set_polarity_and_phase(struct dw_spi *dws, uint8_t format) +{ + uint32_t reg = dw_readl(dws, CVI_DW_SPI_CTRLR0); + reg &= ~(0x3 << 6); + + switch (format) { + case SPI_FORMAT_CPOL0_CPHA0: + reg |= (SPI_MODE_0 << 6); + break; + + case SPI_FORMAT_CPOL0_CPHA1: + reg |= (SPI_MODE_1 << 6); + break; + + case SPI_FORMAT_CPOL1_CPHA0: + reg |= (SPI_MODE_2 << 6); + break; + + case SPI_FORMAT_CPOL1_CPHA1: + reg |= (SPI_MODE_3 << 6); + break; + + default: + reg = dw_readl(dws, CVI_DW_SPI_CTRLR0); + break; + } + SP_DEBUG_LOG("set phase and polarity: %#x\n", reg); + dw_writel(dws, CVI_DW_SPI_CTRLR0, reg); +} + +uint32_t dw_spi_set_clock(struct dw_spi *dws, uint32_t clock_in, uint32_t clock_out) +{ + uint16_t div; + + div = (DIV_ROUND_UP(clock_in, clock_out) + 1) & 0xfffe; + dws->speed_hz = clock_in / div; + SP_DEBUG_LOG("clk div value is: %u, hz:%u\n", div, dws->speed_hz); + spi_set_clk(dws, div); + return dws->speed_hz; +} + +int dw_spi_set_data_frame_len(struct dw_spi *dws, uint32_t size) +{ + uint32_t temp = dw_readl(dws, CVI_DW_SPI_CTRLR0); + temp &= ~0xf; + + if (size == 8) { + dws->n_bytes = 1; + } else if (size == 16) { + dws->n_bytes = 2; + } else { + SP_DEBUG_LOG("do not support %u bit data!\n", size); + return -1; + } + temp |= (size - 1); + dw_writel(dws, CVI_DW_SPI_CTRLR0, temp); + SP_DEBUG_LOG("set data frame len: %#x\n", temp); + return 0; +} + +void dw_spi_show_regs(struct dw_spi *dws) +{ + SP_DEBUG_LOG("CTRLR0: \t0x%08x\n", dw_readl(dws, CVI_DW_SPI_CTRLR0)); + SP_DEBUG_LOG("CTRLR1: \t0x%08x\n", dw_readl(dws, CVI_DW_SPI_CTRLR1)); + SP_DEBUG_LOG("SSIENR: \t0x%08x\n", dw_readl(dws, CVI_DW_SPI_SSIENR)); + SP_DEBUG_LOG("SER: \t0x%08x\n", dw_readl(dws, CVI_DW_SPI_SER)); + SP_DEBUG_LOG("BAUDR: \t0x%08x\n", dw_readl(dws, CVI_DW_SPI_BAUDR)); + SP_DEBUG_LOG("TXFTLR: \t0x%08x\n", dw_readl(dws, CVI_DW_SPI_TXFTLR)); + SP_DEBUG_LOG("RXFTLR: \t0x%08x\n", dw_readl(dws, CVI_DW_SPI_RXFTLR)); + SP_DEBUG_LOG("TXFLR: \t0x%08x\n", dw_readl(dws, CVI_DW_SPI_TXFLR)); + SP_DEBUG_LOG("RXFLR: \t0x%08x\n", dw_readl(dws, CVI_DW_SPI_RXFLR)); + SP_DEBUG_LOG("SR: \t0x%08x\n", dw_readl(dws, CVI_DW_SPI_SR)); + SP_DEBUG_LOG("IMR: \t0x%08x\n", dw_readl(dws, CVI_DW_SPI_IMR)); + SP_DEBUG_LOG("ISR: \t0x%08x\n", dw_readl(dws, CVI_DW_SPI_ISR)); + SP_DEBUG_LOG("DMACR: \t0x%08x\n", dw_readl(dws, CVI_DW_SPI_DMACR)); + SP_DEBUG_LOG("DMATDLR: \t0x%08x\n", dw_readl(dws, CVI_DW_SPI_DMATDLR)); + SP_DEBUG_LOG("DMARDLR: \t0x%08x\n", dw_readl(dws, CVI_DW_SPI_DMARDLR)); +} diff --git a/bsp/cvitek/drivers/libraries/spi/dw_spi.h b/bsp/cvitek/drivers/libraries/spi/dw_spi.h new file mode 100644 index 0000000000..b5b6e6bc60 --- /dev/null +++ b/bsp/cvitek/drivers/libraries/spi/dw_spi.h @@ -0,0 +1,246 @@ +/* + * Copyright (C) Cvitek Co., Ltd. 2019-2020. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef __DW_SPI_HEADER_H__ +#define __DW_SPI_HEADER_H__ + +#include "stdint.h" +#include "stdbool.h" + +#define SPI_REGBASE 0x04180000 +#define SPI_REF_CLK 187500000 +#define MAX_SPI_NUM 4 + +#define CVI_DW_SPI_CTRLR0 0x00 +#define CVI_DW_SPI_CTRLR1 0x04 +#define CVI_DW_SPI_SSIENR 0x08 +#define CVI_DW_SPI_MWCR 0x0c +#define CVI_DW_SPI_SER 0x10 +#define CVI_DW_SPI_BAUDR 0x14 +#define CVI_DW_SPI_TXFTLR 0x18 +#define CVI_DW_SPI_RXFTLR 0x1c +#define CVI_DW_SPI_TXFLR 0x20 +#define CVI_DW_SPI_RXFLR 0x24 +#define CVI_DW_SPI_SR 0x28 +#define CVI_DW_SPI_IMR 0x2c +#define CVI_DW_SPI_ISR 0x30 +#define CVI_DW_SPI_RISR 0x34 +#define CVI_DW_SPI_TXOICR 0x38 +#define CVI_DW_SPI_RXOICR 0x3c +#define CVI_DW_SPI_RXUICR 0x40 +#define CVI_DW_SPI_MSTICR 0x44 +#define CVI_DW_SPI_ICR 0x48 +#define CVI_DW_SPI_DMACR 0x4c +#define CVI_DW_SPI_DMATDLR 0x50 +#define CVI_DW_SPI_DMARDLR 0x54 +#define CVI_DW_SPI_IDR 0x58 +#define CVI_DW_SPI_VERSION 0x5c +#define CVI_DW_SPI_DR 0x60 + +/* Bit fields in CTRLR0 */ +#define CVI_SPI_DFS_OFFSET 0 + +#define CVI_SPI_FRF_OFFSET 4 +#define CVI_SPI_FRF_SPI 0x0 +#define CVI_SPI_FRF_SSP 0x1 +#define CVI_SPI_FRF_MICROWIRE 0x2 +#define CVI_SPI_FRF_RESV 0x3 + +#define CVI_SPI_MODE_OFFSET 6 +#define CVI_SPI_SCPH_OFFSET 6 +#define CVI_SPI_SCOL_OFFSET 7 + +#define CVI_SPI_TMOD_OFFSET 8 +#define CVI_SPI_TMOD_MASK (0x3 << CVI_SPI_TMOD_OFFSET) +#define CVI_SPI_TMOD_TR 0x0 /* xmit & recv */ +#define CVI_SPI_TMOD_TO 0x1 /* xmit only */ +#define CVI_SPI_TMOD_RO 0x2 /* recv only */ +#define CVI_SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */ + +#define CVI_SPI_SLVOE_OFFSET 10 +#define CVI_SPI_SRL_OFFSET 11 +#define CVI_SPI_CFS_OFFSET 12 + +/* Bit fields in SR, 7 bits */ +#define CVI_SR_MASK 0x7f +#define CVI_SR_BUSY (1 << 0) +#define CVI_SR_TF_NOT_FULL (1 << 1) +#define CVI_SR_TF_EMPT (1 << 2) +#define CVI_SR_RF_NOT_EMPT (1 << 3) +#define CVI_SR_RF_FULL (1 << 4) +#define CVI_SR_TX_ERR (1 << 5) +#define SR_DCOL (1 << 6) + +/* Bit fields in ISR, IMR, RISR, 7 bits */ +#define CVI_SPI_INT_TXEI (1 << 0) +#define CVI_SPI_INT_TXOI (1 << 1) +#define CVI_SPI_INT_RXUI (1 << 2) +#define CVI_SPI_INT_RXOI (1 << 3) +#define CVI_SPI_INT_RXFI (1 << 4) +#define CVI_SPI_INT_MSTI (1 << 5) + +/* Bit fields in DMACR */ +#define CVI_SPI_DMA_RDMAE (1 << 0) +#define CVI_SPI_DMA_TDMAE (1 << 1) + +/* TX RX interrupt level threshold, max can be 256 */ +#define CVI_SPI_INT_THRESHOLD 32 +#define BITS_PER_BYTE 8 +#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) + +struct dw_spi { + void *regs; + int irq; + int index; + uint32_t fifo_len; /* depth of the FIFO buffer */ + uint16_t num_cs; /* supported slave numbers */ + uint32_t speed_hz; + /* Current message transfer state info */ + size_t len; + const void *tx; + const void *tx_end; + void *rx; + void *rx_end; + uint32_t rx_len; + uint32_t tx_len; + uint8_t n_bytes; /* current is a 1/2 bytes op */ + uint32_t dma_width; + int (*transfer_handler)(struct dw_spi *dws); + + /* Bus interface info */ + void *priv; +}; + +struct spi_delay { +#define SPI_DELAY_UNIT_USECS 0 +#define SPI_DELAY_UNIT_NSECS 1 +#define SPI_DELAY_UNIT_SCK 2 + uint16_t value; + uint8_t unit; +}; + +#define SPI_CPHA 0x01 +#define SPI_CPOL 0x02 + +#define SPI_MODE_0 (0|0) +#define SPI_MODE_1 (0|SPI_CPHA) +#define SPI_MODE_2 (SPI_CPOL|0) +#define SPI_MODE_3 (SPI_CPOL|SPI_CPHA) + +enum transfer_type { + POLL_TRAN = 0, + IRQ_TRAN, + DMA_TRAN, +}; + +enum dw_ssi_type { + SSI_MOTO_SPI = 0, + SSI_TI_SSP, + SSI_NS_MICROWIRE, +}; + +#define SPI_FORMAT_CPOL0_CPHA0 0 +#define SPI_FORMAT_CPOL0_CPHA1 1 +#define SPI_FORMAT_CPOL1_CPHA0 2 +#define SPI_FORMAT_CPOL1_CPHA1 3 + +#ifndef BIT +#define BIT(_n) ( 1 << (_n)) +#endif + +static void dw_writel(struct dw_spi *dws, uint32_t off, uint32_t val) +{ + writel(val, (dws->regs + off)); +} + +static uint32_t dw_readl(struct dw_spi *dws, uint32_t off) +{ + return readl(dws->regs + off); +} + +static inline void spi_enable_chip(struct dw_spi *dws, int enable) +{ + dw_writel(dws, CVI_DW_SPI_SSIENR, (enable ? 1 : 0)); +} + +static inline void spi_set_clk(struct dw_spi *dws, uint16_t div) +{ + dw_writel(dws, CVI_DW_SPI_BAUDR, div); +} + +/* Disable IRQ bits */ +static inline void spi_mask_intr(struct dw_spi *dws, uint32_t mask) +{ + uint32_t new_mask; + + new_mask = dw_readl(dws, CVI_DW_SPI_IMR) & ~mask; + dw_writel(dws, CVI_DW_SPI_IMR, new_mask); +} + +static inline uint32_t spi_get_status(struct dw_spi *dws) +{ + return dw_readl(dws, CVI_DW_SPI_SR); +} + +/* Enable IRQ bits */ +static inline void spi_umask_intr(struct dw_spi *dws, uint32_t mask) +{ + uint32_t new_mask; + + new_mask = dw_readl(dws, CVI_DW_SPI_IMR) | mask; + dw_writel(dws, CVI_DW_SPI_IMR, new_mask); +} + +static inline void spi_reset_chip(struct dw_spi *dws) +{ + spi_enable_chip(dws, 0); + spi_mask_intr(dws, 0xff); + dw_readl(dws, CVI_DW_SPI_ICR); + dw_writel(dws, CVI_DW_SPI_SER, 0); + spi_enable_chip(dws, 1); +} + +static inline void spi_enable_dma(struct dw_spi *dws, uint8_t is_tx, uint8_t op) +{ + /* 1: TDMAE, 0: RDMAE */ + uint32_t val = dw_readl(dws, CVI_DW_SPI_DMACR); + + if (op) + val |= 1 << (!!is_tx); + else + val &= ~(1 << (!!is_tx)); + + dw_writel(dws, CVI_DW_SPI_DMACR, val); +} + +static inline void spi_shutdown_chip(struct dw_spi *dws) +{ + spi_enable_chip(dws, 0); + spi_set_clk(dws, 0); +} + +void spi_hw_init(struct dw_spi *dws); +void dw_spi_set_controller_mode(struct dw_spi *dws, uint8_t enable_master); +void dw_spi_set_polarity_and_phase(struct dw_spi *dws, uint8_t format); +uint32_t dw_spi_set_clock(struct dw_spi *dws, uint32_t clock_in, uint32_t clock_out); +int dw_spi_set_data_frame_len(struct dw_spi *dws, uint32_t size); +void dw_spi_set_cs(struct dw_spi *dws, bool enable, uint32_t index); +void dw_reader(struct dw_spi *dws); +void dw_writer(struct dw_spi *dws); +void set_tran_mode(struct dw_spi *dws); +void dw_spi_show_regs(struct dw_spi *dws); +int poll_transfer(struct dw_spi *dws); +int dw_spi_check_status(struct dw_spi *dws, bool raw); +#endif From 2d1eba8bf3327fa5313544c6102bf6356d17a65a Mon Sep 17 00:00:00 2001 From: Shell Date: Wed, 17 Jul 2024 05:22:07 +0000 Subject: [PATCH 17/48] [libcpu] quality: call PV_OFFSET on entry for once This patch improves the efficiency and readability of the AArch64 common setup code by calculating the `PV_OFFSET` once at the start and reusing the value. This change reduces redundant calculations. Signed-off-by: Shell --- libcpu/aarch64/common/setup.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/libcpu/aarch64/common/setup.c b/libcpu/aarch64/common/setup.c index dd30b1d673..304e8565fb 100644 --- a/libcpu/aarch64/common/setup.c +++ b/libcpu/aarch64/common/setup.c @@ -208,11 +208,12 @@ void rt_hw_common_setup(void) rt_region_t init_page_region = { 0 }; rt_region_t platform_mem_region = { 0 }; static struct mem_desc platform_mem_desc; + const rt_ubase_t pv_off = PV_OFFSET; system_vectors_init(); #ifdef RT_USING_SMART - rt_hw_mmu_map_init(&rt_kernel_space, (void*)0xfffffffff0000000, 0x10000000, MMUTable, PV_OFFSET); + rt_hw_mmu_map_init(&rt_kernel_space, (void*)0xfffffffff0000000, 0x10000000, MMUTable, pv_off); #else rt_hw_mmu_map_init(&rt_kernel_space, (void*)0xffffd0000000, 0x10000000, MMUTable, 0); #endif @@ -234,13 +235,13 @@ void rt_hw_common_setup(void) rt_memblock_reserve_memory("init-page", init_page_start, init_page_end, MEMBLOCK_NONE); rt_memblock_reserve_memory("fdt", fdt_start, fdt_end, MEMBLOCK_NONE); - rt_memmove((void *)(fdt_start - PV_OFFSET), (void *)(fdt_ptr - PV_OFFSET), fdt_size); - fdt_ptr = (void *)fdt_start - PV_OFFSET; + rt_memmove((void *)(fdt_start - pv_off), (void *)(fdt_ptr - pv_off), fdt_size); + fdt_ptr = (void *)fdt_start - pv_off; - rt_system_heap_init((void *)(heap_start - PV_OFFSET), (void *)(heap_end - PV_OFFSET)); + rt_system_heap_init((void *)(heap_start - pv_off), (void *)(heap_end - pv_off)); - init_page_region.start = init_page_start - PV_OFFSET; - init_page_region.end = init_page_end - PV_OFFSET; + init_page_region.start = init_page_start - pv_off; + init_page_region.end = init_page_end - pv_off; rt_page_init(init_page_region); /* create MMU mapping of kernel memory */ @@ -248,8 +249,8 @@ void rt_hw_common_setup(void) platform_mem_region.end = RT_ALIGN(platform_mem_region.end, ARCH_PAGE_SIZE); platform_mem_desc.paddr_start = platform_mem_region.start; - platform_mem_desc.vaddr_start = platform_mem_region.start - PV_OFFSET; - platform_mem_desc.vaddr_end = platform_mem_region.end - PV_OFFSET - 1; + platform_mem_desc.vaddr_start = platform_mem_region.start - pv_off; + platform_mem_desc.vaddr_end = platform_mem_region.end - pv_off - 1; platform_mem_desc.attr = NORMAL_MEM; rt_hw_mmu_setup(&rt_kernel_space, &platform_mem_desc, 1); From 1bcf232d12d49303cd2eb0143c3aa1855dffd916 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Thu, 13 Jun 2024 14:24:52 +0800 Subject: [PATCH 18/48] bsp: cvitek: fix the wdt timeout unit problem See `components/drivers/include/drivers/watchdog.h` maco definition of RT_DEVICE_CTRL_WDT_GET_TIMEOUT RT_DEVICE_CTRL_WDT_SET_TIMEOUT RT_DEVICE_CTRL_WDT_GET_TIMELEFT The wdt timeout time unit is defined as seconds in the API, but the code incorrectly uses ms. Correct this and comply with the API definition. Signed-off-by: Chen Wang Reviewed-by: Yuanjie He <943313837@qq.com> Reviewed-by: Shell --- bsp/cvitek/drivers/drv_wdt.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/bsp/cvitek/drivers/drv_wdt.c b/bsp/cvitek/drivers/drv_wdt.c index 8cbc233b8d..c4792ccfff 100644 --- a/bsp/cvitek/drivers/drv_wdt.c +++ b/bsp/cvitek/drivers/drv_wdt.c @@ -66,6 +66,14 @@ rt_inline int wdt_top_in_ms(unsigned int top) return (1U << (16 + top)) / (WDT_FREQ_DEFAULT / 1000); } +/** + * @brief set timeout period + * + * @param reg_base base address of the watchdog controller + * @param ms timeout period (in millisecond) + * + * @return RT_EOK if successed. + */ static rt_err_t csi_wdt_set_timeout(unsigned long reg_base, uint32_t ms) { rt_err_t ret = RT_EOK; @@ -115,13 +123,13 @@ static rt_err_t _wdt_control(rt_watchdog_t *wdt_device, int cmd, void *arg) break; case RT_DEVICE_CTRL_WDT_SET_TIMEOUT: wdt->timeout = *(rt_uint32_t *)arg; - csi_wdt_set_timeout(reg_base, wdt->timeout); + csi_wdt_set_timeout(reg_base, wdt->timeout * 1000); break; case RT_DEVICE_CTRL_WDT_GET_TIMEOUT: *(rt_uint32_t *)arg = wdt->timeout; break; case RT_DEVICE_CTRL_WDT_GET_TIMELEFT: - *(rt_uint32_t *)arg = (cvi_wdt_get_counter_value(reg_base) / (WDT_FREQ_DEFAULT / 1000U)); + *(rt_uint32_t *)arg = (cvi_wdt_get_counter_value(reg_base) / WDT_FREQ_DEFAULT); break; case RT_DEVICE_CTRL_WDT_START: cvi_wdt_set_respond_system_reset(reg_base); From 393a61b048a06c00632c9ba507bf17fbd3d4239f Mon Sep 17 00:00:00 2001 From: zhao maosheng Date: Mon, 15 Jul 2024 17:29:11 +0800 Subject: [PATCH 19/48] Fix potential return value discrepancy when writing to urandom --- components/drivers/misc/rt_random.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/components/drivers/misc/rt_random.c b/components/drivers/misc/rt_random.c index da6b312e1e..9f4be20902 100644 --- a/components/drivers/misc/rt_random.c +++ b/components/drivers/misc/rt_random.c @@ -46,7 +46,7 @@ static rt_ssize_t random_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_si static rt_ssize_t random_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) { - ssize_t ret = sizeof(seed); + ssize_t ret = sizeof(seed) < size ? sizeof(seed) : size; rt_memcpy(&seed, buffer, ret); return ret; } @@ -137,7 +137,7 @@ static rt_ssize_t random_uread(rt_device_t dev, rt_off_t pos, void *buffer, rt_s static rt_ssize_t random_uwrite(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) { - ssize_t ret = sizeof(useed); + ssize_t ret = sizeof(useed) < size ? sizeof(useed) : size; rt_memcpy(&useed, buffer, ret); return ret; } From a6b2014214f5609473bc013fdf7453cc67235459 Mon Sep 17 00:00:00 2001 From: zhao maosheng Date: Thu, 18 Jul 2024 13:25:37 +0800 Subject: [PATCH 20/48] fix exec and mount error code --- components/dfs/dfs_v2/src/dfs_fs.c | 2 +- components/lwp/lwp_syscall.c | 10 ++++++++-- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/components/dfs/dfs_v2/src/dfs_fs.c b/components/dfs/dfs_v2/src/dfs_fs.c index e65ccee478..755b257191 100644 --- a/components/dfs/dfs_v2/src/dfs_fs.c +++ b/components/dfs/dfs_v2/src/dfs_fs.c @@ -127,7 +127,7 @@ int dfs_mount(const char *device_name, } else { - rt_set_errno(ENOENT); + rt_set_errno(ENODEV); ret = -1; } diff --git a/components/lwp/lwp_syscall.c b/components/lwp/lwp_syscall.c index e539e0452b..21a34bd28e 100644 --- a/components/lwp/lwp_syscall.c +++ b/components/lwp/lwp_syscall.c @@ -2172,7 +2172,7 @@ rt_weak sysret_t sys_vfork(void) sysret_t sys_execve(const char *path, char *const argv[], char *const envp[]) { - int error = -1; + rt_err_t error = -1; size_t len; struct rt_lwp *new_lwp = NULL; struct rt_lwp *lwp; @@ -2223,8 +2223,9 @@ sysret_t sys_execve(const char *path, char *const argv[], char *const envp[]) if (access(kpath, X_OK) != 0) { + error = rt_get_errno(); rt_free(kpath); - return -EACCES; + return (sysret_t)error; } /* setup args */ @@ -5784,6 +5785,11 @@ sysret_t sys_mount(char *source, char *target, copy_source = NULL; } ret = dfs_mount(copy_source, copy_target, copy_filesystemtype, 0, tmp); + + if (ret < 0) + { + ret = -rt_get_errno(); + } rt_free(copy_source); return ret; From 0efc408a00d087c346c222322374c75e6d33001a Mon Sep 17 00:00:00 2001 From: MuChenger <1516081466@qq.com> Date: Tue, 16 Jul 2024 16:11:02 +0800 Subject: [PATCH 21/48] adapt to rv64ilp32 toolchain --- bsp/qemu-virt64-riscv/Kconfig | 4 + bsp/qemu-virt64-riscv/README_ZH.md | 55 +++++++- .../qemu-rv64ilp32-nographic.sh | 1 + libcpu/risc-v/virt64/context_gcc.S | 8 +- libcpu/risc-v/virt64/cpuport.c | 17 +-- libcpu/risc-v/virt64/cpuport.h | 4 +- libcpu/risc-v/virt64/cpuport_gcc.S | 6 +- libcpu/risc-v/virt64/ext_context.h | 76 +++++----- libcpu/risc-v/virt64/interrupt.h | 5 +- libcpu/risc-v/virt64/regtypes.h | 19 +++ libcpu/risc-v/virt64/riscv.h | 8 +- libcpu/risc-v/virt64/stackframe.h | 130 +++++++++--------- libcpu/risc-v/virt64/trap.c | 10 +- 13 files changed, 214 insertions(+), 129 deletions(-) create mode 100755 bsp/qemu-virt64-riscv/qemu-rv64ilp32-nographic.sh create mode 100644 libcpu/risc-v/virt64/regtypes.h diff --git a/bsp/qemu-virt64-riscv/Kconfig b/bsp/qemu-virt64-riscv/Kconfig index 053cacc57c..e955063ec6 100644 --- a/bsp/qemu-virt64-riscv/Kconfig +++ b/bsp/qemu-virt64-riscv/Kconfig @@ -59,3 +59,7 @@ config ARCH_USING_NEW_CTX_SWITCH config __STACKSIZE__ int "stack size for interrupt" default 4096 + +config RT_USING_RV64ILP32 + bool "Use RV64ILP32 toolchain" + default n \ No newline at end of file diff --git a/bsp/qemu-virt64-riscv/README_ZH.md b/bsp/qemu-virt64-riscv/README_ZH.md index eafff95c2e..99f218003f 100644 --- a/bsp/qemu-virt64-riscv/README_ZH.md +++ b/bsp/qemu-virt64-riscv/README_ZH.md @@ -4,7 +4,7 @@ ## 1. 简介 -RISC-V是一种开放和免费的指令集体系结构(ISA)。本工程是在QEMU的RISCV64 VIRT版本上进行的一份移植。 +RISC-V是一种开放和免费的指令集体系结构(ISA)。本工程是在QEMU的RISCV64 VIRT版本上进行的一份移植。本工程支持玄铁团队联合中科院软件所共同推出的全球首款rv64ilp32产品级开源工具链。 ## 2. 编译说明 @@ -133,8 +133,59 @@ msh /> | PLIC | 支持 | - | | CLIC | 支持 | - | -## 5. 联系人信息 +## 5.如何使用rv64ilp32工具链 + +1. 工具链地址：https://github.com/ruyisdk/riscv-gnu-toolchain-rv64ilp32/tags + +2. 使用方法： + + - 配置工具链路径 + + - 修改ABI参数为：-mabi=ilp32d + + - 使用menuconfig使能下述选项: + + ```shell + RT_USING_RV64ILP32 + ``` + + - 使用menuconfig失能下述选项: + + ```shell + RT_USING_POSIX_PIPE + RT_USING_POSIX_FS + RT_USING_DFS + ``` + +3. 使用传统64位工具链与使用新32位工具链编译相同工程的固件大小对比： + + 传统64位工具链固件大小： + + ```bash + Memory region Used Size Region Size %age Used + SRAM: 225856 B 16 MB 1.35% + riscv64-unknown-elf-objcopy -O binary rtthread.elf rtthread.bin + riscv64-unknown-elf-size rtthread.elf + text data bss dec hex filename + 150907 3664 71268 225839 3722f rtthread.elf + ``` + + 新32位工具链固件大小： + + ```bash + Memory region Used Size Region Size %age Used + SRAM: 209376 B 16 MB 1.25% + riscv64-unknown-elf-objcopy -O binary rtthread.elf rtthread.bin + riscv64-unknown-elf-size rtthread.elf + text data bss dec hex filename + 138739 1356 69276 209371 331db rtthread.elf + ``` + +## 6. 联系人信息 维护人：[bernard][1] [1]: https://github.com/BernardXiong + + + diff --git a/bsp/qemu-virt64-riscv/qemu-rv64ilp32-nographic.sh b/bsp/qemu-virt64-riscv/qemu-rv64ilp32-nographic.sh new file mode 100755 index 0000000000..d1b95203d6 --- /dev/null +++ b/bsp/qemu-virt64-riscv/qemu-rv64ilp32-nographic.sh @@ -0,0 +1 @@ +/home/rv/opt-ilp32/bin/qemu-system-riscv64ilp32 -cpu rv64 -M virt -m 256M -nographic -kernel rtthread.elf diff --git a/libcpu/risc-v/virt64/context_gcc.S b/libcpu/risc-v/virt64/context_gcc.S index 486a787e61..d7be609efc 100644 --- a/libcpu/risc-v/virt64/context_gcc.S +++ b/libcpu/risc-v/virt64/context_gcc.S @@ -16,13 +16,13 @@ #include "stackframe.h" .macro PUSH_8 reg - addi sp, sp, -8 + addi sp, sp, -REGBYTES STORE \reg, (sp) .endm .macro POP_8 reg LOAD \reg, (sp) - addi sp, sp, 8 + addi sp, sp, REGBYTES .endm .macro RESERVE_CONTEXT @@ -44,11 +44,11 @@ li s10, (SSTATUS_SPP) or s11, s11, s10 PUSH_8 s11 - addi sp, sp, -8 + addi sp, sp, -REGBYTES .endm .macro RESTORE_CONTEXT - addi sp, sp, 8 + addi sp, sp, REGBYTES POP_8 s11 csrw sstatus, s11 POP_8 s11 diff --git a/libcpu/risc-v/virt64/cpuport.c b/libcpu/risc-v/virt64/cpuport.c index 92394bcc22..33795d1891 100644 --- a/libcpu/risc-v/virt64/cpuport.c +++ b/libcpu/risc-v/virt64/cpuport.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2024, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,6 +16,7 @@ #include "stack.h" #include #include +#include "regtypes.h" #define K_SSTATUS_DEFAULT (SSTATUS_SPP | SSTATUS_SPIE | SSTATUS_SUM | SSTATUS_FS) @@ -35,7 +36,7 @@ volatile rt_ubase_t rt_interrupt_to_thread = 0; */ volatile rt_ubase_t rt_thread_switch_interrupt_flag = 0; -void *_rt_hw_stack_init(rt_ubase_t *sp, rt_ubase_t ra, rt_ubase_t sstatus) +void *_rt_hw_stack_init(rt_uintreg_t *sp, rt_uintreg_t ra, rt_uintreg_t sstatus) { (*--sp) = 0; /* tp */ (*--sp) = ra; /* ra */ @@ -80,17 +81,17 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, rt_uint8_t *stack_addr, void *texit) { - rt_ubase_t *sp = (rt_ubase_t *)stack_addr; + rt_uintreg_t *sp = (rt_uintreg_t *)stack_addr; // we use a strict alignment requirement for Q extension - sp = (rt_ubase_t *)RT_ALIGN_DOWN((rt_ubase_t)sp, 16); + sp = (rt_uintreg_t *)RT_ALIGN_DOWN((rt_uintreg_t)sp, 16); - (*--sp) = (rt_ubase_t)tentry; - (*--sp) = (rt_ubase_t)parameter; - (*--sp) = (rt_ubase_t)texit; + (*--sp) = (rt_uintreg_t)tentry; + (*--sp) = (rt_uintreg_t)parameter; + (*--sp) = (rt_uintreg_t)texit; /* compatible to RESTORE_CONTEXT */ extern void _rt_thread_entry(void); - return (rt_uint8_t *)_rt_hw_stack_init(sp, (rt_ubase_t)_rt_thread_entry, K_SSTATUS_DEFAULT); + return (rt_uint8_t *)_rt_hw_stack_init(sp, (rt_uintreg_t)_rt_thread_entry, K_SSTATUS_DEFAULT); } /* diff --git a/libcpu/risc-v/virt64/cpuport.h b/libcpu/risc-v/virt64/cpuport.h index 8caccd100c..c12ff7ddf7 100644 --- a/libcpu/risc-v/virt64/cpuport.h +++ b/libcpu/risc-v/virt64/cpuport.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2024, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -17,6 +17,8 @@ #ifdef ARCH_CPU_64BIT #define STORE sd #define LOAD ld +#define FSTORE fsd +#define FLOAD fld #define REGBYTES 8 #else // error here, not portable diff --git a/libcpu/risc-v/virt64/cpuport_gcc.S b/libcpu/risc-v/virt64/cpuport_gcc.S index 8ea52d4796..89cf8701c6 100644 --- a/libcpu/risc-v/virt64/cpuport_gcc.S +++ b/libcpu/risc-v/virt64/cpuport_gcc.S @@ -14,11 +14,11 @@ START_POINT(_rt_thread_entry) LOAD ra, (sp) /* thread exit */ - addi sp, sp, 8 + addi sp, sp, REGBYTES LOAD a0, (sp) /* parameter */ - addi sp, sp, 8 + addi sp, sp, REGBYTES LOAD t0, (sp) /* tentry */ - addi sp, sp, 8 + addi sp, sp, REGBYTES mv s1, ra jalr t0 jalr s1 diff --git a/libcpu/risc-v/virt64/ext_context.h b/libcpu/risc-v/virt64/ext_context.h index ac757dddb6..70c2cfd12c 100644 --- a/libcpu/risc-v/virt64/ext_context.h +++ b/libcpu/risc-v/virt64/ext_context.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2024, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -28,38 +28,38 @@ */ #ifdef ENABLE_FPU -#define FPU_CTX_F0_OFF 0 /* offsetof(fpu_context_t, fpustatus.f[0]) - offsetof(fpu_context_t, fpustatus.f[0]) */ -#define FPU_CTX_F1_OFF 8 /* offsetof(fpu_context_t, fpustatus.f[1]) - offsetof(fpu_context_t, fpustatus.f[0]) */ -#define FPU_CTX_F2_OFF 16 /* offsetof(fpu_context_t, fpustatus.f[2]) - offsetof(fpu_context_t, fpustatus.f[0]) */ -#define FPU_CTX_F3_OFF 24 /* offsetof(fpu_context_t, fpustatus.f[3]) - offsetof(fpu_context_t, fpustatus.f[0]) */ -#define FPU_CTX_F4_OFF 32 /* offsetof(fpu_context_t, fpustatus.f[4]) - offsetof(fpu_context_t, fpustatus.f[0]) */ -#define FPU_CTX_F5_OFF 40 /* offsetof(fpu_context_t, fpustatus.f[5]) - offsetof(fpu_context_t, fpustatus.f[0]) */ -#define FPU_CTX_F6_OFF 48 /* offsetof(fpu_context_t, fpustatus.f[6]) - offsetof(fpu_context_t, fpustatus.f[0]) */ -#define FPU_CTX_F7_OFF 56 /* offsetof(fpu_context_t, fpustatus.f[7]) - offsetof(fpu_context_t, fpustatus.f[0]) */ -#define FPU_CTX_F8_OFF 64 /* offsetof(fpu_context_t, fpustatus.f[8]) - offsetof(fpu_context_t, fpustatus.f[0]) */ -#define FPU_CTX_F9_OFF 72 /* offsetof(fpu_context_t, fpustatus.f[9]) - offsetof(fpu_context_t, fpustatus.f[0]) */ -#define FPU_CTX_F10_OFF 80 /* offsetof(fpu_context_t, fpustatus.f[10]) - offsetof(fpu_context_t, fpustatus.f[0]) */ -#define FPU_CTX_F11_OFF 88 /* offsetof(fpu_context_t, fpustatus.f[11]) - offsetof(fpu_context_t, fpustatus.f[0]) */ -#define FPU_CTX_F12_OFF 96 /* offsetof(fpu_context_t, fpustatus.f[12]) - offsetof(fpu_context_t, fpustatus.f[0]) */ -#define FPU_CTX_F13_OFF 104 /* offsetof(fpu_context_t, fpustatus.f[13]) - offsetof(fpu_context_t, fpustatus.f[0]) */ -#define FPU_CTX_F14_OFF 112 /* offsetof(fpu_context_t, fpustatus.f[14]) - offsetof(fpu_context_t, fpustatus.f[0]) */ -#define FPU_CTX_F15_OFF 120 /* offsetof(fpu_context_t, fpustatus.f[15]) - offsetof(fpu_context_t, fpustatus.f[0]) */ -#define FPU_CTX_F16_OFF 128 /* offsetof(fpu_context_t, fpustatus.f[16]) - offsetof(fpu_context_t, fpustatus.f[0]) */ -#define FPU_CTX_F17_OFF 136 /* offsetof(fpu_context_t, fpustatus.f[17]) - offsetof(fpu_context_t, fpustatus.f[0]) */ -#define FPU_CTX_F18_OFF 144 /* offsetof(fpu_context_t, fpustatus.f[18]) - offsetof(fpu_context_t, fpustatus.f[0]) */ -#define FPU_CTX_F19_OFF 152 /* offsetof(fpu_context_t, fpustatus.f[19]) - offsetof(fpu_context_t, fpustatus.f[0]) */ -#define FPU_CTX_F20_OFF 160 /* offsetof(fpu_context_t, fpustatus.f[20]) - offsetof(fpu_context_t, fpustatus.f[0]) */ -#define FPU_CTX_F21_OFF 168 /* offsetof(fpu_context_t, fpustatus.f[21]) - offsetof(fpu_context_t, fpustatus.f[0]) */ -#define FPU_CTX_F22_OFF 176 /* offsetof(fpu_context_t, fpustatus.f[22]) - offsetof(fpu_context_t, fpustatus.f[0]) */ -#define FPU_CTX_F23_OFF 184 /* offsetof(fpu_context_t, fpustatus.f[23]) - offsetof(fpu_context_t, fpustatus.f[0]) */ -#define FPU_CTX_F24_OFF 192 /* offsetof(fpu_context_t, fpustatus.f[24]) - offsetof(fpu_context_t, fpustatus.f[0]) */ -#define FPU_CTX_F25_OFF 200 /* offsetof(fpu_context_t, fpustatus.f[25]) - offsetof(fpu_context_t, fpustatus.f[0]) */ -#define FPU_CTX_F26_OFF 208 /* offsetof(fpu_context_t, fpustatus.f[26]) - offsetof(fpu_context_t, fpustatus.f[0]) */ -#define FPU_CTX_F27_OFF 216 /* offsetof(fpu_context_t, fpustatus.f[27]) - offsetof(fpu_context_t, fpustatus.f[0]) */ -#define FPU_CTX_F28_OFF 224 /* offsetof(fpu_context_t, fpustatus.f[28]) - offsetof(fpu_context_t, fpustatus.f[0]) */ -#define FPU_CTX_F29_OFF 232 /* offsetof(fpu_context_t, fpustatus.f[29]) - offsetof(fpu_context_t, fpustatus.f[0]) */ -#define FPU_CTX_F30_OFF 240 /* offsetof(fpu_context_t, fpustatus.f[30]) - offsetof(fpu_context_t, fpustatus.f[0]) */ -#define FPU_CTX_F31_OFF 248 /* offsetof(fpu_context_t, fpustatus.f[31]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F0_OFF REGBYTES * 0 /* offsetof(fpu_context_t, fpustatus.f[0]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F1_OFF REGBYTES * 1 /* offsetof(fpu_context_t, fpustatus.f[1]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F2_OFF REGBYTES * 2 /* offsetof(fpu_context_t, fpustatus.f[2]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F3_OFF REGBYTES * 3 /* offsetof(fpu_context_t, fpustatus.f[3]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F4_OFF REGBYTES * 4 /* offsetof(fpu_context_t, fpustatus.f[4]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F5_OFF REGBYTES * 5 /* offsetof(fpu_context_t, fpustatus.f[5]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F6_OFF REGBYTES * 6 /* offsetof(fpu_context_t, fpustatus.f[6]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F7_OFF REGBYTES * 7 /* offsetof(fpu_context_t, fpustatus.f[7]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F8_OFF REGBYTES * 8 /* offsetof(fpu_context_t, fpustatus.f[8]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F9_OFF REGBYTES * 9 /* offsetof(fpu_context_t, fpustatus.f[9]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F10_OFF REGBYTES * 10 /* offsetof(fpu_context_t, fpustatus.f[10]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F11_OFF REGBYTES * 11 /* offsetof(fpu_context_t, fpustatus.f[11]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F12_OFF REGBYTES * 12 /* offsetof(fpu_context_t, fpustatus.f[12]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F13_OFF REGBYTES * 13 /* offsetof(fpu_context_t, fpustatus.f[13]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F14_OFF REGBYTES * 14 /* offsetof(fpu_context_t, fpustatus.f[14]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F15_OFF REGBYTES * 15 /* offsetof(fpu_context_t, fpustatus.f[15]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F16_OFF REGBYTES * 16 /* offsetof(fpu_context_t, fpustatus.f[16]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F17_OFF REGBYTES * 17 /* offsetof(fpu_context_t, fpustatus.f[17]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F18_OFF REGBYTES * 18 /* offsetof(fpu_context_t, fpustatus.f[18]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F19_OFF REGBYTES * 19 /* offsetof(fpu_context_t, fpustatus.f[19]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F20_OFF REGBYTES * 20 /* offsetof(fpu_context_t, fpustatus.f[20]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F21_OFF REGBYTES * 21 /* offsetof(fpu_context_t, fpustatus.f[21]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F22_OFF REGBYTES * 22 /* offsetof(fpu_context_t, fpustatus.f[22]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F23_OFF REGBYTES * 23 /* offsetof(fpu_context_t, fpustatus.f[23]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F24_OFF REGBYTES * 24 /* offsetof(fpu_context_t, fpustatus.f[24]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F25_OFF REGBYTES * 25 /* offsetof(fpu_context_t, fpustatus.f[25]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F26_OFF REGBYTES * 26 /* offsetof(fpu_context_t, fpustatus.f[26]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F27_OFF REGBYTES * 27 /* offsetof(fpu_context_t, fpustatus.f[27]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F28_OFF REGBYTES * 28 /* offsetof(fpu_context_t, fpustatus.f[28]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F29_OFF REGBYTES * 29 /* offsetof(fpu_context_t, fpustatus.f[29]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F30_OFF REGBYTES * 30 /* offsetof(fpu_context_t, fpustatus.f[30]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F31_OFF REGBYTES * 31 /* offsetof(fpu_context_t, fpustatus.f[31]) - offsetof(fpu_context_t, fpustatus.f[0]) */ #endif /* ENABLE_FPU */ /** @@ -84,9 +84,9 @@ /** * @brief save vector extension hardware state - * + * * @param dst register storing bottom of storage block - * + * */ .macro SAVE_VECTOR, dst mv t1, \dst @@ -117,9 +117,9 @@ /** * @brief restore vector extension hardware states - * + * * @param dst register storing bottom of storage block - * + * */ .macro RESTORE_VECTOR, dst // restore vector registers first since it will modify vector states @@ -152,4 +152,4 @@ #endif /* __ASSEMBLY__ */ -#endif /* __EXT_CONTEXT_H__ */ \ No newline at end of file +#endif /* __EXT_CONTEXT_H__ */ diff --git a/libcpu/risc-v/virt64/interrupt.h b/libcpu/risc-v/virt64/interrupt.h index aa01479076..6d6929121e 100644 --- a/libcpu/risc-v/virt64/interrupt.h +++ b/libcpu/risc-v/virt64/interrupt.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2024, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -15,6 +15,7 @@ #include #include "stack.h" +#include "regtypes.h" enum { @@ -41,6 +42,6 @@ int rt_hw_plic_irq_disable(int irq_number); void rt_hw_interrupt_init(void); void rt_hw_interrupt_mask(int vector); rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, void *param, const char *name); -void handle_trap(rt_size_t xcause, rt_size_t xtval, rt_size_t xepc, struct rt_hw_stack_frame *sp); +void handle_trap(rt_uintreg_t xcause, rt_uintreg_t xtval, rt_uintreg_t xepc, struct rt_hw_stack_frame *sp); #endif diff --git a/libcpu/risc-v/virt64/regtypes.h b/libcpu/risc-v/virt64/regtypes.h new file mode 100644 index 0000000000..14a7410676 --- /dev/null +++ b/libcpu/risc-v/virt64/regtypes.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-07-15 WangShun The first version + */ + +#ifndef REGTYPES_H__ +#define REGTYPES_H__ +#include +#if defined(RT_USING_RV64ILP32) +typedef unsigned long long rt_uintreg_t; +#else +typedef unsigned long rt_uintreg_t; +#endif +#endif /* REGTYPES_H__ */ diff --git a/libcpu/risc-v/virt64/riscv.h b/libcpu/risc-v/virt64/riscv.h index d0c0cc4b38..2b28703d64 100644 --- a/libcpu/risc-v/virt64/riscv.h +++ b/libcpu/risc-v/virt64/riscv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2024, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -12,9 +12,15 @@ #define __RISCV_H__ #include +#include +#if defined(RT_USING_RV64ILP32) +#define __SIZE(bit) (1ULL << (bit)) +#define __MASK(bit) (__SIZE(bit) - 1ULL) +#else #define __SIZE(bit) (1UL << (bit)) #define __MASK(bit) (__SIZE(bit) - 1UL) +#endif /* RT_USING_RV64ILP32 */ #define __UMASK(bit) (~(__MASK(bit))) #define __MASKVALUE(value,maskvalue) ((value) & (maskvalue)) #define __UMASKVALUE(value,maskvalue) ((value) & (~(maskvalue))) diff --git a/libcpu/risc-v/virt64/stackframe.h b/libcpu/risc-v/virt64/stackframe.h index 4caf3bc7ab..598bb905bf 100644 --- a/libcpu/risc-v/virt64/stackframe.h +++ b/libcpu/risc-v/virt64/stackframe.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2024, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -85,38 +85,38 @@ li t0, SSTATUS_FS csrs sstatus, t0 - fsd f0, FPU_CTX_F0_OFF(t1) - fsd f1, FPU_CTX_F1_OFF(t1) - fsd f2, FPU_CTX_F2_OFF(t1) - fsd f3, FPU_CTX_F3_OFF(t1) - fsd f4, FPU_CTX_F4_OFF(t1) - fsd f5, FPU_CTX_F5_OFF(t1) - fsd f6, FPU_CTX_F6_OFF(t1) - fsd f7, FPU_CTX_F7_OFF(t1) - fsd f8, FPU_CTX_F8_OFF(t1) - fsd f9, FPU_CTX_F9_OFF(t1) - fsd f10, FPU_CTX_F10_OFF(t1) - fsd f11, FPU_CTX_F11_OFF(t1) - fsd f12, FPU_CTX_F12_OFF(t1) - fsd f13, FPU_CTX_F13_OFF(t1) - fsd f14, FPU_CTX_F14_OFF(t1) - fsd f15, FPU_CTX_F15_OFF(t1) - fsd f16, FPU_CTX_F16_OFF(t1) - fsd f17, FPU_CTX_F17_OFF(t1) - fsd f18, FPU_CTX_F18_OFF(t1) - fsd f19, FPU_CTX_F19_OFF(t1) - fsd f20, FPU_CTX_F20_OFF(t1) - fsd f21, FPU_CTX_F21_OFF(t1) - fsd f22, FPU_CTX_F22_OFF(t1) - fsd f23, FPU_CTX_F23_OFF(t1) - fsd f24, FPU_CTX_F24_OFF(t1) - fsd f25, FPU_CTX_F25_OFF(t1) - fsd f26, FPU_CTX_F26_OFF(t1) - fsd f27, FPU_CTX_F27_OFF(t1) - fsd f28, FPU_CTX_F28_OFF(t1) - fsd f29, FPU_CTX_F29_OFF(t1) - fsd f30, FPU_CTX_F30_OFF(t1) - fsd f31, FPU_CTX_F31_OFF(t1) + FSTORE f0, FPU_CTX_F0_OFF(t1) + FSTORE f1, FPU_CTX_F1_OFF(t1) + FSTORE f2, FPU_CTX_F2_OFF(t1) + FSTORE f3, FPU_CTX_F3_OFF(t1) + FSTORE f4, FPU_CTX_F4_OFF(t1) + FSTORE f5, FPU_CTX_F5_OFF(t1) + FSTORE f6, FPU_CTX_F6_OFF(t1) + FSTORE f7, FPU_CTX_F7_OFF(t1) + FSTORE f8, FPU_CTX_F8_OFF(t1) + FSTORE f9, FPU_CTX_F9_OFF(t1) + FSTORE f10, FPU_CTX_F10_OFF(t1) + FSTORE f11, FPU_CTX_F11_OFF(t1) + FSTORE f12, FPU_CTX_F12_OFF(t1) + FSTORE f13, FPU_CTX_F13_OFF(t1) + FSTORE f14, FPU_CTX_F14_OFF(t1) + FSTORE f15, FPU_CTX_F15_OFF(t1) + FSTORE f16, FPU_CTX_F16_OFF(t1) + FSTORE f17, FPU_CTX_F17_OFF(t1) + FSTORE f18, FPU_CTX_F18_OFF(t1) + FSTORE f19, FPU_CTX_F19_OFF(t1) + FSTORE f20, FPU_CTX_F20_OFF(t1) + FSTORE f21, FPU_CTX_F21_OFF(t1) + FSTORE f22, FPU_CTX_F22_OFF(t1) + FSTORE f23, FPU_CTX_F23_OFF(t1) + FSTORE f24, FPU_CTX_F24_OFF(t1) + FSTORE f25, FPU_CTX_F25_OFF(t1) + FSTORE f26, FPU_CTX_F26_OFF(t1) + FSTORE f27, FPU_CTX_F27_OFF(t1) + FSTORE f28, FPU_CTX_F28_OFF(t1) + FSTORE f29, FPU_CTX_F29_OFF(t1) + FSTORE f30, FPU_CTX_F30_OFF(t1) + FSTORE f31, FPU_CTX_F31_OFF(t1) /* clr FS domain */ csrc sstatus, t0 @@ -166,38 +166,38 @@ li t0, SSTATUS_FS csrs sstatus, t0 - fld f0, FPU_CTX_F0_OFF(t2) - fld f1, FPU_CTX_F1_OFF(t2) - fld f2, FPU_CTX_F2_OFF(t2) - fld f3, FPU_CTX_F3_OFF(t2) - fld f4, FPU_CTX_F4_OFF(t2) - fld f5, FPU_CTX_F5_OFF(t2) - fld f6, FPU_CTX_F6_OFF(t2) - fld f7, FPU_CTX_F7_OFF(t2) - fld f8, FPU_CTX_F8_OFF(t2) - fld f9, FPU_CTX_F9_OFF(t2) - fld f10, FPU_CTX_F10_OFF(t2) - fld f11, FPU_CTX_F11_OFF(t2) - fld f12, FPU_CTX_F12_OFF(t2) - fld f13, FPU_CTX_F13_OFF(t2) - fld f14, FPU_CTX_F14_OFF(t2) - fld f15, FPU_CTX_F15_OFF(t2) - fld f16, FPU_CTX_F16_OFF(t2) - fld f17, FPU_CTX_F17_OFF(t2) - fld f18, FPU_CTX_F18_OFF(t2) - fld f19, FPU_CTX_F19_OFF(t2) - fld f20, FPU_CTX_F20_OFF(t2) - fld f21, FPU_CTX_F21_OFF(t2) - fld f22, FPU_CTX_F22_OFF(t2) - fld f23, FPU_CTX_F23_OFF(t2) - fld f24, FPU_CTX_F24_OFF(t2) - fld f25, FPU_CTX_F25_OFF(t2) - fld f26, FPU_CTX_F26_OFF(t2) - fld f27, FPU_CTX_F27_OFF(t2) - fld f28, FPU_CTX_F28_OFF(t2) - fld f29, FPU_CTX_F29_OFF(t2) - fld f30, FPU_CTX_F30_OFF(t2) - fld f31, FPU_CTX_F31_OFF(t2) + FLOAD f0, FPU_CTX_F0_OFF(t2) + FLOAD f1, FPU_CTX_F1_OFF(t2) + FLOAD f2, FPU_CTX_F2_OFF(t2) + FLOAD f3, FPU_CTX_F3_OFF(t2) + FLOAD f4, FPU_CTX_F4_OFF(t2) + FLOAD f5, FPU_CTX_F5_OFF(t2) + FLOAD f6, FPU_CTX_F6_OFF(t2) + FLOAD f7, FPU_CTX_F7_OFF(t2) + FLOAD f8, FPU_CTX_F8_OFF(t2) + FLOAD f9, FPU_CTX_F9_OFF(t2) + FLOAD f10, FPU_CTX_F10_OFF(t2) + FLOAD f11, FPU_CTX_F11_OFF(t2) + FLOAD f12, FPU_CTX_F12_OFF(t2) + FLOAD f13, FPU_CTX_F13_OFF(t2) + FLOAD f14, FPU_CTX_F14_OFF(t2) + FLOAD f15, FPU_CTX_F15_OFF(t2) + FLOAD f16, FPU_CTX_F16_OFF(t2) + FLOAD f17, FPU_CTX_F17_OFF(t2) + FLOAD f18, FPU_CTX_F18_OFF(t2) + FLOAD f19, FPU_CTX_F19_OFF(t2) + FLOAD f20, FPU_CTX_F20_OFF(t2) + FLOAD f21, FPU_CTX_F21_OFF(t2) + FLOAD f22, FPU_CTX_F22_OFF(t2) + FLOAD f23, FPU_CTX_F23_OFF(t2) + FLOAD f24, FPU_CTX_F24_OFF(t2) + FLOAD f25, FPU_CTX_F25_OFF(t2) + FLOAD f26, FPU_CTX_F26_OFF(t2) + FLOAD f27, FPU_CTX_F27_OFF(t2) + FLOAD f28, FPU_CTX_F28_OFF(t2) + FLOAD f29, FPU_CTX_F29_OFF(t2) + FLOAD f30, FPU_CTX_F30_OFF(t2) + FLOAD f31, FPU_CTX_F31_OFF(t2) /* clr FS domain */ csrc sstatus, t0 diff --git a/libcpu/risc-v/virt64/trap.c b/libcpu/risc-v/virt64/trap.c index 4366a5b2c0..b24be3baca 100644 --- a/libcpu/risc-v/virt64/trap.c +++ b/libcpu/risc-v/virt64/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2024, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -61,7 +61,7 @@ void dump_regs(struct rt_hw_stack_frame *regs) rt_kprintf("\t%s\n", (regs->sstatus & SSTATUS_SPP) ? "Last Privilege is Supervisor Mode" : "Last Privilege is User Mode"); rt_kprintf("\t%s\n", (regs->sstatus & SSTATUS_SUM) ? "Permit to Access User Page" : "Not Permit to Access User Page"); rt_kprintf("\t%s\n", (regs->sstatus & (1 << 19)) ? "Permit to Read Executable-only Page" : "Not Permit to Read Executable-only Page"); - rt_size_t satp_v = read_csr(satp); + rt_uintreg_t satp_v = read_csr(satp); rt_kprintf("satp = 0x%p\n", satp_v); rt_kprintf("\tCurrent Page Table(Physical) = 0x%p\n", __MASKVALUE(satp_v, __MASK(44)) << PAGE_OFFSET_BIT); rt_kprintf("\tCurrent ASID = 0x%p\n", __MASKVALUE(satp_v >> 44, __MASK(16)) << PAGE_OFFSET_BIT); @@ -291,10 +291,10 @@ static void handle_nested_trap_panic( #define PAGE_FAULT (id == EP_LOAD_PAGE_FAULT || id == EP_STORE_PAGE_FAULT) /* Trap entry */ -void handle_trap(rt_size_t scause, rt_size_t stval, rt_size_t sepc, struct rt_hw_stack_frame *sp) +void handle_trap(rt_uintreg_t scause, rt_uintreg_t stval, rt_uintreg_t sepc, struct rt_hw_stack_frame *sp) { ENTER_TRAP; - rt_size_t id = __MASKVALUE(scause, __MASK(63UL)); + rt_uintreg_t id = __MASKVALUE(scause, __MASK(63UL)); const char *msg; /* supervisor external interrupt */ @@ -316,7 +316,7 @@ void handle_trap(rt_size_t scause, rt_size_t stval, rt_size_t sepc, struct rt_hw { // trap cannot nested when handling another trap / interrupt CHECK_NESTED_PANIC(scause, stval, sepc, sp); - rt_size_t id = __MASKVALUE(scause, __MASK(63UL)); + rt_uintreg_t id = __MASKVALUE(scause, __MASK(63UL)); const char *msg; if (scause >> 63) From 7138f340b2c1cf002779a45d73c4d30295d44c58 Mon Sep 17 00:00:00 2001 From: Shell Date: Thu, 18 Apr 2024 17:12:10 +0800 Subject: [PATCH 22/48] [libcpu/arm64] feat: Trimming General Context This patch focuses on the ARM64 general context handling code. The modifications are aimed at enhancing performance by simplifying context save/restore operations. Changes include: - Adjusted stack alignment in `arch_set_thread_context` function. - Updated `lwp_gcc.S` to reset frame pointer and link register. - Refined `rt_hw_backtrace_frame_unwind` to handle user space address checks. - Added `GET_THREAD_SELF` macro in `asm-generic.h`. - Simplified context saving/restoring in `context_gcc.h` and related files. - Optimized `rt_hw_context_switch_interrupt` and related assembly routines. Signed-off-by: Shell --- .../lwp/arch/aarch64/cortex-a/lwp_arch.c | 10 +- .../lwp/arch/aarch64/cortex-a/lwp_gcc.S | 5 +- libcpu/aarch64/common/backtrace.c | 7 +- libcpu/aarch64/common/include/asm-generic.h | 11 +++ libcpu/aarch64/common/include/context_gcc.h | 94 +++++++++---------- libcpu/aarch64/common/mp/context_gcc.S | 80 ++++++++++------ libcpu/aarch64/common/mp/context_gcc.h | 6 -- libcpu/aarch64/common/mp/vector_gcc.S | 6 +- libcpu/aarch64/common/stack.c | 54 ++++------- libcpu/aarch64/common/stack_gcc.S | 1 + libcpu/aarch64/common/up/context_gcc.S | 34 +++++-- libcpu/aarch64/common/up/context_gcc.h | 6 +- libcpu/aarch64/common/up/vector_gcc.S | 16 +--- 13 files changed, 172 insertions(+), 158 deletions(-) diff --git a/components/lwp/arch/aarch64/cortex-a/lwp_arch.c b/components/lwp/arch/aarch64/cortex-a/lwp_arch.c index 3df6b2f4f7..7e6cd45960 100644 --- a/components/lwp/arch/aarch64/cortex-a/lwp_arch.c +++ b/components/lwp/arch/aarch64/cortex-a/lwp_arch.c @@ -106,18 +106,16 @@ int arch_set_thread_context(void (*exit)(void), void *new_thread_stack, struct rt_hw_exp_stack *ori_syscall = rt_thread_self()->user_ctx.ctx; RT_ASSERT(ori_syscall != RT_NULL); - thread_frame = (void *)((long)new_thread_stack - sizeof(struct rt_hw_exp_stack)); - syscall_frame = (void *)((long)new_thread_stack - 2 * sizeof(struct rt_hw_exp_stack)); + new_thread_stack = (rt_ubase_t*)RT_ALIGN_DOWN((rt_ubase_t)new_thread_stack, 16); + syscall_frame = (void *)((long)new_thread_stack - sizeof(struct rt_hw_exp_stack)); memcpy(syscall_frame, ori_syscall, sizeof(*syscall_frame)); syscall_frame->sp_el0 = (long)user_stack; syscall_frame->x0 = 0; - thread_frame->cpsr = ((3 << 6) | 0x4 | 0x1); - thread_frame->pc = (long)exit; - thread_frame->x0 = 0; + thread_frame = (void *)rt_hw_stack_init(exit, RT_NULL, (void *)syscall_frame, RT_NULL); - *thread_sp = syscall_frame; + *thread_sp = thread_frame; return 0; } diff --git a/components/lwp/arch/aarch64/cortex-a/lwp_gcc.S b/components/lwp/arch/aarch64/cortex-a/lwp_gcc.S index a71ee339cb..571f422a74 100644 --- a/components/lwp/arch/aarch64/cortex-a/lwp_gcc.S +++ b/components/lwp/arch/aarch64/cortex-a/lwp_gcc.S @@ -125,12 +125,15 @@ lwp_exec_user: * since this routine reset the SP, we take it as a start point */ START_POINT(SVC_Handler) + mov fp, xzr + mov lr, xzr + /* x0 is initial sp */ mov sp, x0 msr daifclr, #3 /* enable interrupt */ - bl rt_thread_self + GET_THREAD_SELF x0 bl lwp_user_setting_save ldp x8, x9, [sp, #(CONTEXT_OFFSET_X8)] diff --git a/libcpu/aarch64/common/backtrace.c b/libcpu/aarch64/common/backtrace.c index 0365ec71e4..66ab4c330f 100644 --- a/libcpu/aarch64/common/backtrace.c +++ b/libcpu/aarch64/common/backtrace.c @@ -85,11 +85,12 @@ rt_err_t rt_hw_backtrace_frame_unwind(rt_thread_t thread, struct rt_hw_backtrace if (fp && !((long)fp & 0x7)) { #ifdef RT_USING_SMART +#define IN_USER_SPACE(addr) ((rt_ubase_t)(addr) >= USER_VADDR_START && (rt_ubase_t)(addr) < USER_VADDR_TOP) if (thread && thread->lwp && rt_scheduler_is_available()) { rt_lwp_t lwp = thread->lwp; void *this_lwp = lwp_self(); - if (this_lwp == lwp && rt_kmem_v2p(fp) != ARCH_MAP_FAILED) + if ((!IN_USER_SPACE(fp) || this_lwp == lwp) && rt_kmem_v2p(fp) != ARCH_MAP_FAILED) { rc = _bt_kaddr(fp, frame); } @@ -129,8 +130,8 @@ rt_err_t rt_hw_backtrace_frame_get(rt_thread_t thread, struct rt_hw_backtrace_fr } else { - frame->pc = ARCH_CONTEXT_FETCH(thread->sp, 3); - frame->fp = ARCH_CONTEXT_FETCH(thread->sp, 7); + frame->pc = ARCH_CONTEXT_FETCH(thread->sp, 0); + frame->fp = ARCH_CONTEXT_FETCH(thread->sp, 4); rc = RT_EOK; } return rc; diff --git a/libcpu/aarch64/common/include/asm-generic.h b/libcpu/aarch64/common/include/asm-generic.h index b6b5d48dcb..362ef8f525 100644 --- a/libcpu/aarch64/common/include/asm-generic.h +++ b/libcpu/aarch64/common/include/asm-generic.h @@ -23,4 +23,15 @@ .cfi_endproc; \ .size name, .-name; +.macro GET_THREAD_SELF, dst:req +#ifdef ARCH_USING_HW_THREAD_SELF + mrs x0, tpidr_el1 +#else /* !ARCH_USING_HW_THREAD_SELF */ + bl rt_thread_self +#endif /* ARCH_USING_HW_THREAD_SELF */ + .if \dst != x0 + mov dst, x0 + .endif +.endm + #endif /* __ASM_GENERIC_H__ */ diff --git a/libcpu/aarch64/common/include/context_gcc.h b/libcpu/aarch64/common/include/context_gcc.h index cf9f53786b..843a890131 100644 --- a/libcpu/aarch64/common/include/context_gcc.h +++ b/libcpu/aarch64/common/include/context_gcc.h @@ -10,67 +10,61 @@ #ifndef __ARM64_INC_CONTEXT_H__ #define __ARM64_INC_CONTEXT_H__ -.macro SAVE_CONTEXT_SWITCH +#include "armv8.h" + +.macro SAVE_CONTEXT_SWITCH, tmpx, tmp2x /* Save the entire context. */ SAVE_FPU sp - stp x0, x1, [sp, #-0x10]! - stp x2, x3, [sp, #-0x10]! - stp x4, x5, [sp, #-0x10]! - stp x6, x7, [sp, #-0x10]! - stp x8, x9, [sp, #-0x10]! - stp x10, x11, [sp, #-0x10]! - stp x12, x13, [sp, #-0x10]! - stp x14, x15, [sp, #-0x10]! - stp x16, x17, [sp, #-0x10]! - stp x18, x19, [sp, #-0x10]! - stp x20, x21, [sp, #-0x10]! - stp x22, x23, [sp, #-0x10]! - stp x24, x25, [sp, #-0x10]! - stp x26, x27, [sp, #-0x10]! - stp x28, x29, [sp, #-0x10]! - mrs x28, fpcr - mrs x29, fpsr - stp x28, x29, [sp, #-0x10]! - mrs x29, sp_el0 - stp x29, x30, [sp, #-0x10]! + + stp x19, x20, [sp, #-0x10]! + stp x21, x22, [sp, #-0x10]! + stp x23, x24, [sp, #-0x10]! + stp x25, x26, [sp, #-0x10]! + stp x27, x28, [sp, #-0x10]! + + mrs \tmpx, sp_el0 + stp x29, \tmpx, [sp, #-0x10]! + + mrs \tmpx, fpcr + mrs \tmp2x, fpsr + stp \tmpx, \tmp2x, [sp, #-0x10]! + + mov \tmpx, #((3 << 6) | 0x5) /* el1h, disable interrupt */ + stp x30, \tmpx, [sp, #-0x10]! + +.endm + +.macro SAVE_CONTEXT_SWITCH_FAST + /* Save the entire context. */ + add sp, sp, #-1 * CONTEXT_FPU_SIZE + + add sp, sp, #-7 * 16 mov x19, #((3 << 6) | 0x4 | 0x1) /* el1h, disable interrupt */ - mov x18, x30 + stp lr, x19, [sp, #-0x10]! - stp x18, x19, [sp, #-0x10]! .endm .macro _RESTORE_CONTEXT_SWITCH - ldp x2, x3, [sp], #0x10 /* SPSR and ELR. */ + ldp x30, x19, [sp], #0x10 /* SPSR and ELR. */ + msr elr_el1, x30 + msr spsr_el1, x19 - tst x3, #0x1f - msr spsr_el1, x3 - msr elr_el1, x2 - ldp x29, x30, [sp], #0x10 - msr sp_el0, x29 - ldp x28, x29, [sp], #0x10 - msr fpcr, x28 - msr fpsr, x29 - ldp x28, x29, [sp], #0x10 - ldp x26, x27, [sp], #0x10 - ldp x24, x25, [sp], #0x10 - ldp x22, x23, [sp], #0x10 - ldp x20, x21, [sp], #0x10 - ldp x18, x19, [sp], #0x10 - ldp x16, x17, [sp], #0x10 - ldp x14, x15, [sp], #0x10 - ldp x12, x13, [sp], #0x10 - ldp x10, x11, [sp], #0x10 - ldp x8, x9, [sp], #0x10 - ldp x6, x7, [sp], #0x10 - ldp x4, x5, [sp], #0x10 - ldp x2, x3, [sp], #0x10 - ldp x0, x1, [sp], #0x10 + /* restore NEON */ + ldp x19, x20, [sp], #0x10 + msr fpcr, x19 + msr fpsr, x20 + + ldp x29, x19, [sp], #0x10 + msr sp_el0, x19 + ldp x27, x28, [sp], #0x10 + ldp x25, x26, [sp], #0x10 + ldp x23, x24, [sp], #0x10 + ldp x21, x22, [sp], #0x10 + ldp x19, x20, [sp], #0x10 + RESTORE_FPU sp -#ifdef RT_USING_SMART - beq arch_ret_to_user -#endif eret .endm diff --git a/libcpu/aarch64/common/mp/context_gcc.S b/libcpu/aarch64/common/mp/context_gcc.S index 9b91d1d3d0..355899e34d 100644 --- a/libcpu/aarch64/common/mp/context_gcc.S +++ b/libcpu/aarch64/common/mp/context_gcc.S @@ -35,13 +35,17 @@ rt_hw_context_switch_to: ldr x0, [x0] mov sp, x0 - mov x0, x1 + + /* reserved to_thread */ + mov x19, x1 + + mov x0, x19 bl rt_cpus_lock_status_restore #ifdef RT_USING_SMART - bl rt_thread_self + mov x0, x19 bl lwp_user_setting_restore #endif - b rt_hw_context_switch_exit + b _context_switch_exit .globl rt_hw_context_switch @@ -53,7 +57,7 @@ to, struct rt_thread *to_thread); * X2 --> to_thread */ rt_hw_context_switch: - SAVE_CONTEXT_SWITCH + SAVE_CONTEXT_SWITCH x19, x20 mov x3, sp str x3, [x0] // store sp in preempted tasks TCB ldr x0, [x1] // get new task stack pointer @@ -68,10 +72,15 @@ rt_hw_context_switch: mov x0, x19 bl lwp_user_setting_restore #endif - b rt_hw_context_switch_exit + b _context_switch_exit +.globl rt_hw_irq_exit .globl rt_hw_context_switch_interrupt +#define EXP_FRAME x19 +#define FROM_SPP x20 +#define TO_SPP x21 +#define TO_TCB x22 /* * void rt_hw_context_switch_interrupt(context, from sp, to sp, tp tcb) * X0 :interrupt context @@ -80,30 +89,45 @@ rt_hw_context_switch: * X3 :to_thread's tcb */ rt_hw_context_switch_interrupt: - stp x0, x1, [sp, #-0x10]! - stp x2, x3, [sp, #-0x10]! +#ifdef RT_USING_DEBUG + /* debug frame for backtrace */ stp x29, x30, [sp, #-0x10]! -#ifdef RT_USING_SMART - bl rt_thread_self - bl lwp_user_setting_save -#endif - ldp x29, x30, [sp], #0x10 - ldp x2, x3, [sp], #0x10 - ldp x0, x1, [sp], #0x10 - str x0, [x1] - ldr x0, [x2] - mov sp, x0 - mov x0, x3 - mov x19, x0 - bl rt_cpus_lock_status_restore - mov x0, x19 -#ifdef RT_USING_SMART - bl lwp_user_setting_restore -#endif - b rt_hw_context_switch_exit +#endif /* RT_USING_DEBUG */ -.global rt_hw_context_switch_exit -rt_hw_context_switch_exit: - clrex + /* we can discard all the previous ABI here */ + mov EXP_FRAME, x0 + mov FROM_SPP, x1 + mov TO_SPP, x2 + mov TO_TCB, x3 + +#ifdef RT_USING_SMART + GET_THREAD_SELF x0 + bl lwp_user_setting_save +#endif /* RT_USING_SMART */ + + /* reset SP of from-thread */ + mov sp, EXP_FRAME + + /* push context for swtich */ + adr lr, rt_hw_irq_exit + SAVE_CONTEXT_SWITCH_FAST + + /* save SP of from-thread */ mov x0, sp + str x0, [FROM_SPP] + + /* setup SP to to-thread's */ + ldr x0, [TO_SPP] + mov sp, x0 + + mov x0, TO_TCB + bl rt_cpus_lock_status_restore +#ifdef RT_USING_SMART + mov x0, TO_TCB + bl lwp_user_setting_restore +#endif /* RT_USING_SMART */ + b _context_switch_exit + +_context_switch_exit: + clrex RESTORE_CONTEXT_SWITCH diff --git a/libcpu/aarch64/common/mp/context_gcc.h b/libcpu/aarch64/common/mp/context_gcc.h index 2a1e7fe92b..fdb9dd217a 100644 --- a/libcpu/aarch64/common/mp/context_gcc.h +++ b/libcpu/aarch64/common/mp/context_gcc.h @@ -20,16 +20,10 @@ #include .macro RESTORE_CONTEXT_SWITCH - /* Set the SP to point to the stack of the task being restored. */ - mov sp, x0 - _RESTORE_CONTEXT_SWITCH .endm .macro RESTORE_IRQ_CONTEXT - /* Set the SP to point to the stack of the task being restored. */ - mov sp, x0 - ldp x2, x3, [sp], #0x10 /* SPSR and ELR. */ tst x3, #0x1f diff --git a/libcpu/aarch64/common/mp/vector_gcc.S b/libcpu/aarch64/common/mp/vector_gcc.S index 67b4bc5fe8..2b3ebd584e 100644 --- a/libcpu/aarch64/common/mp/vector_gcc.S +++ b/libcpu/aarch64/common/mp/vector_gcc.S @@ -15,10 +15,14 @@ #include "../include/vector_gcc.h" #include "context_gcc.h" +.section .text + .globl vector_fiq vector_fiq: b . +.globl rt_hw_irq_exit + START_POINT(vector_irq) SAVE_IRQ_CONTEXT stp x0, x1, [sp, #-0x10]! /* X0 is thread sp */ @@ -42,7 +46,7 @@ START_POINT(vector_irq) ldp x0, x1, [sp], #0x10 bl rt_scheduler_do_irq_switch - mov x0, sp +rt_hw_irq_exit: RESTORE_IRQ_CONTEXT START_POINT_END(vector_irq) diff --git a/libcpu/aarch64/common/stack.c b/libcpu/aarch64/common/stack.c index c554ab077d..e3e8ccbc9d 100644 --- a/libcpu/aarch64/common/stack.c +++ b/libcpu/aarch64/common/stack.c @@ -41,44 +41,22 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, *(rt_uint128_t *)stk = (rt_uint128_t) { 0 }; } - *(--stk) = (rt_ubase_t)0; /* X1 */ - *(--stk) = (rt_ubase_t)parameter; /* X0 */ - *(--stk) = (rt_ubase_t)3; /* X3 */ - *(--stk) = (rt_ubase_t)2; /* X2 */ - *(--stk) = (rt_ubase_t)5; /* X5 */ - *(--stk) = (rt_ubase_t)4; /* X4 */ - *(--stk) = (rt_ubase_t)7; /* X7 */ - *(--stk) = (rt_ubase_t)6; /* X6 */ - *(--stk) = (rt_ubase_t)9; /* X9 */ - *(--stk) = (rt_ubase_t)8; /* X8 */ - *(--stk) = (rt_ubase_t)11; /* X11 */ - *(--stk) = (rt_ubase_t)10; /* X10 */ - *(--stk) = (rt_ubase_t)13; /* X13 */ - *(--stk) = (rt_ubase_t)12; /* X12 */ - *(--stk) = (rt_ubase_t)15; /* X15 */ - *(--stk) = (rt_ubase_t)14; /* X14 */ - *(--stk) = (rt_ubase_t)17; /* X17 */ - *(--stk) = (rt_ubase_t)16; /* X16 */ - *(--stk) = (rt_ubase_t)tentry; /* X19, 1st param */ - *(--stk) = (rt_ubase_t)18; /* X18 */ - *(--stk) = (rt_ubase_t)21; /* X21 */ - *(--stk) = (rt_ubase_t)texit; /* X20, 2nd param */ - *(--stk) = (rt_ubase_t)23; /* X23 */ - *(--stk) = (rt_ubase_t)22; /* X22 */ - *(--stk) = (rt_ubase_t)25; /* X25 */ - *(--stk) = (rt_ubase_t)24; /* X24 */ - *(--stk) = (rt_ubase_t)27; /* X27 */ - *(--stk) = (rt_ubase_t)26; /* X26 */ - *(--stk) = (rt_ubase_t)0; /* X29 - addr 0 as AAPCS64 specified */ - *(--stk) = (rt_ubase_t)28; /* X28 */ - *(--stk) = (rt_ubase_t)0; /* FPSR */ - *(--stk) = (rt_ubase_t)0; /* FPCR */ - *(--stk) = (rt_ubase_t)0; /* X30 - procedure call link register. */ - *(--stk) = (rt_ubase_t)0; /* sp_el0 */ - - *(--stk) = INITIAL_SPSR_EL1; - - *(--stk) = (rt_ubase_t)_thread_start; /* Exception return address. */ + *(--stk) = (rt_ubase_t)texit; /* X20, 2nd param */ + *(--stk) = (rt_ubase_t)tentry; /* X19, 1st param */ + *(--stk) = (rt_ubase_t)22; /* X22 */ + *(--stk) = (rt_ubase_t)parameter; /* X21, 3rd param */ + *(--stk) = (rt_ubase_t)24; /* X24 */ + *(--stk) = (rt_ubase_t)23; /* X23 */ + *(--stk) = (rt_ubase_t)26; /* X26 */ + *(--stk) = (rt_ubase_t)25; /* X25 */ + *(--stk) = (rt_ubase_t)28; /* X28 */ + *(--stk) = (rt_ubase_t)27; /* X27 */ + *(--stk) = (rt_ubase_t)0; /* sp_el0 */ + *(--stk) = (rt_ubase_t)0; /* X29 - addr 0 as AAPCS64 specified */ + *(--stk) = (rt_ubase_t)0; /* FPSR */ + *(--stk) = (rt_ubase_t)0; /* FPCR */ + *(--stk) = INITIAL_SPSR_EL1; /* Save Processor States */ + *(--stk) = (rt_ubase_t)_thread_start; /* Exception return address. */ /* return task's current stack address */ return (rt_uint8_t *)stk; diff --git a/libcpu/aarch64/common/stack_gcc.S b/libcpu/aarch64/common/stack_gcc.S index 26016882b8..f970d23cb9 100644 --- a/libcpu/aarch64/common/stack_gcc.S +++ b/libcpu/aarch64/common/stack_gcc.S @@ -21,6 +21,7 @@ .section .text START_POINT(_thread_start) + mov x0, x21 blr x19 mov x29, #0 blr x20 diff --git a/libcpu/aarch64/common/up/context_gcc.S b/libcpu/aarch64/common/up/context_gcc.S index c22658af36..59e0dbd093 100644 --- a/libcpu/aarch64/common/up/context_gcc.S +++ b/libcpu/aarch64/common/up/context_gcc.S @@ -44,7 +44,7 @@ rt_thread_switch_interrupt_flag: rt_hw_context_switch_to: clrex ldr x0, [x0] - RESTORE_CONTEXT_SWITCH + RESTORE_CONTEXT_SWITCH x0 /* * void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to); @@ -55,23 +55,23 @@ rt_hw_context_switch_to: .globl rt_hw_context_switch rt_hw_context_switch: clrex - SAVE_CONTEXT_SWITCH + SAVE_CONTEXT_SWITCH x19, x20 mov x2, sp str x2, [x0] // store sp in preempted tasks TCB ldr x0, [x1] // get new task stack pointer - RESTORE_CONTEXT_SWITCH + RESTORE_CONTEXT_SWITCH x0 -/* - * void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to, rt_thread_t from_thread, rt_thread_t to_thread); - */ .globl rt_thread_switch_interrupt_flag .globl rt_interrupt_from_thread .globl rt_interrupt_to_thread .globl rt_hw_context_switch_interrupt + +/* + * void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to, rt_thread_t from_thread, rt_thread_t to_thread); + */ rt_hw_context_switch_interrupt: - clrex ldr x6, =rt_thread_switch_interrupt_flag ldr x7, [x6] cmp x7, #1 @@ -95,3 +95,23 @@ _reswitch: ldr x6, =rt_interrupt_to_thread // set rt_interrupt_to_thread str x1, [x6] ret + +.globl rt_hw_context_switch_interrupt_do + +/** + * rt_hw_context_switch_interrupt_do(void) + */ +rt_hw_context_switch_interrupt_do: + clrex + SAVE_CONTEXT_SWITCH_FAST + + ldr x3, =rt_interrupt_from_thread + ldr x4, [x3] + mov x0, sp + str x0, [x4] // store sp in preempted tasks's tcb + + ldr x3, =rt_interrupt_to_thread + ldr x4, [x3] + ldr x0, [x4] // get new task's stack pointer + + RESTORE_CONTEXT_SWITCH x0 diff --git a/libcpu/aarch64/common/up/context_gcc.h b/libcpu/aarch64/common/up/context_gcc.h index 266d3f6f31..cb48e5f244 100644 --- a/libcpu/aarch64/common/up/context_gcc.h +++ b/libcpu/aarch64/common/up/context_gcc.h @@ -19,9 +19,9 @@ #include #include -.macro RESTORE_CONTEXT_SWITCH +.macro RESTORE_CONTEXT_SWITCH using_sp /* Set the SP to point to the stack of the task being restored. */ - mov sp, x0 + mov sp, \using_sp #ifdef RT_USING_SMART bl rt_thread_self @@ -34,8 +34,6 @@ .endm .macro RESTORE_IRQ_CONTEXT - /* Set the SP to point to the stack of the task being restored. */ - MOV SP, X0 #ifdef RT_USING_SMART BL rt_thread_self MOV X19, X0 diff --git a/libcpu/aarch64/common/up/vector_gcc.S b/libcpu/aarch64/common/up/vector_gcc.S index 0bc509f9bc..0b2ddeb8d0 100644 --- a/libcpu/aarch64/common/up/vector_gcc.S +++ b/libcpu/aarch64/common/up/vector_gcc.S @@ -26,9 +26,7 @@ .globl vector_fiq vector_fiq: SAVE_IRQ_CONTEXT - stp x0, x1, [sp, #-0x10]! bl rt_hw_trap_fiq - ldp x0, x1, [sp], #0x10 RESTORE_IRQ_CONTEXT .globl rt_interrupt_enter @@ -36,19 +34,17 @@ vector_fiq: .globl rt_thread_switch_interrupt_flag .globl rt_interrupt_from_thread .globl rt_interrupt_to_thread +.globl rt_hw_context_switch_interrupt_do .align 8 .globl vector_irq vector_irq: SAVE_IRQ_CONTEXT - stp x0, x1, [sp, #-0x10]! /* X0 is thread sp */ bl rt_interrupt_enter bl rt_hw_trap_irq bl rt_interrupt_leave - ldp x0, x1, [sp], #0x10 - /** * if rt_thread_switch_interrupt_flag set, jump to * rt_hw_context_switch_interrupt_do and don't return @@ -61,15 +57,7 @@ vector_irq: mov x2, #0 // clear flag str x2, [x1] - ldr x3, =rt_interrupt_from_thread - ldr x4, [x3] - str x0, [x4] // store sp in preempted tasks's tcb - - ldr x3, =rt_interrupt_to_thread - ldr x4, [x3] - ldr x0, [x4] // get new task's stack pointer - - RESTORE_IRQ_CONTEXT + bl rt_hw_context_switch_interrupt_do vector_irq_exit: RESTORE_IRQ_CONTEXT_WITHOUT_MMU_SWITCH From 7c1d205a4e81365ce6846ce08bfb338372a52749 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Thu, 4 Jul 2024 10:07:14 +0800 Subject: [PATCH 23/48] bsp: cvitek: switch to device init function for some drivers Some drivers use INIT_BOARD_EXPORT, it is not necessary, it is enough to use INIT_DEVICE_EXPORT for genearl drivers. Signed-off-by: Chen Wang --- bsp/cvitek/drivers/drv_adc.c | 2 +- bsp/cvitek/drivers/drv_hw_i2c.c | 2 +- bsp/cvitek/drivers/drv_pwm.c | 2 +- bsp/cvitek/drivers/drv_spi.c | 2 +- bsp/cvitek/drivers/drv_wdt.c | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/bsp/cvitek/drivers/drv_adc.c b/bsp/cvitek/drivers/drv_adc.c index f5f179fed1..e3ca317b58 100644 --- a/bsp/cvitek/drivers/drv_adc.c +++ b/bsp/cvitek/drivers/drv_adc.c @@ -212,4 +212,4 @@ int rt_hw_adc_init(void) return RT_EOK; } -INIT_BOARD_EXPORT(rt_hw_adc_init); +INIT_DEVICE_EXPORT(rt_hw_adc_init); diff --git a/bsp/cvitek/drivers/drv_hw_i2c.c b/bsp/cvitek/drivers/drv_hw_i2c.c index 6044f935b6..7e116f9fea 100644 --- a/bsp/cvitek/drivers/drv_hw_i2c.c +++ b/bsp/cvitek/drivers/drv_hw_i2c.c @@ -601,4 +601,4 @@ int rt_hw_i2c_init(void) return result; } -INIT_BOARD_EXPORT(rt_hw_i2c_init); +INIT_DEVICE_EXPORT(rt_hw_i2c_init); diff --git a/bsp/cvitek/drivers/drv_pwm.c b/bsp/cvitek/drivers/drv_pwm.c index a52bc6af7a..28616218a9 100644 --- a/bsp/cvitek/drivers/drv_pwm.c +++ b/bsp/cvitek/drivers/drv_pwm.c @@ -335,4 +335,4 @@ int rt_hw_pwm_init(void) } return RT_EOK; } -INIT_BOARD_EXPORT(rt_hw_pwm_init); +INIT_DEVICE_EXPORT(rt_hw_pwm_init); diff --git a/bsp/cvitek/drivers/drv_spi.c b/bsp/cvitek/drivers/drv_spi.c index e268fa89d0..10d6c9011b 100644 --- a/bsp/cvitek/drivers/drv_spi.c +++ b/bsp/cvitek/drivers/drv_spi.c @@ -342,4 +342,4 @@ int rt_hw_spi_init(void) return ret; } -INIT_BOARD_EXPORT(rt_hw_spi_init); +INIT_DEVICE_EXPORT(rt_hw_spi_init); diff --git a/bsp/cvitek/drivers/drv_wdt.c b/bsp/cvitek/drivers/drv_wdt.c index c4792ccfff..1fb1ad8430 100644 --- a/bsp/cvitek/drivers/drv_wdt.c +++ b/bsp/cvitek/drivers/drv_wdt.c @@ -167,4 +167,4 @@ int rt_hw_wdt_init(void) return RT_EOK; } -INIT_BOARD_EXPORT(rt_hw_wdt_init); +INIT_DEVICE_EXPORT(rt_hw_wdt_init); From 8d3ad68caf91f12d11cc25bfb53f0cedb5eae380 Mon Sep 17 00:00:00 2001 From: wdfk-prog <1425075683@qq.com> Date: Thu, 11 Jul 2024 09:28:41 +0800 Subject: [PATCH 24/48] [src][tick]rt_tick setting arbitrary value function is added to support low-power wake-up tick compensation --- include/rtsched.h | 4 ++-- include/rtthread.h | 3 ++- src/clock.c | 56 +++++++++++++++++++++++++++++++++++--------- src/scheduler_comm.c | 14 ++++++++--- 4 files changed, 60 insertions(+), 17 deletions(-) diff --git a/include/rtsched.h b/include/rtsched.h index 786ca8b54e..d650e09e37 100644 --- a/include/rtsched.h +++ b/include/rtsched.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2023-2024, RT-Thread Development Team + * Copyright (c) 2023-2024 RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -157,7 +157,7 @@ void rt_sched_thread_startup(struct rt_thread *thread); /* scheduler related routine */ void rt_sched_post_ctx_switch(struct rt_thread *thread); -rt_err_t rt_sched_tick_increase(void); +rt_err_t rt_sched_tick_increase(rt_tick_t tick); /* thread status operation */ rt_uint8_t rt_sched_thread_get_stat(struct rt_thread *thread); diff --git a/include/rtthread.h b/include/rtthread.h index 517d3dac42..dc33a6c835 100644 --- a/include/rtthread.h +++ b/include/rtthread.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2024 RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -100,6 +100,7 @@ void rt_object_put_sethook(void (*hook)(struct rt_object *object)); rt_tick_t rt_tick_get(void); void rt_tick_set(rt_tick_t tick); void rt_tick_increase(void); +void rt_tick_increase_tick(rt_tick_t tick); rt_tick_t rt_tick_from_millisecond(rt_int32_t ms); rt_tick_t rt_tick_get_millisecond(void); #ifdef RT_USING_HOOK diff --git a/src/clock.c b/src/clock.c index 34684d2885..a29c0ad1cd 100644 --- a/src/clock.c +++ b/src/clock.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2024 RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -84,33 +84,33 @@ void rt_tick_set(rt_tick_t tick) } #ifdef RT_USING_CPU_USAGE_TRACER -static void _update_process_times(void) +static void _update_process_times(rt_tick_t tick) { struct rt_thread *thread = rt_thread_self(); struct rt_cpu *pcpu = rt_cpu_self(); if (!LWP_IS_USER_MODE(thread)) { - thread->user_time += 1; - pcpu->cpu_stat.user += 1; + thread->user_time += tick; + pcpu->cpu_stat.user += tick; } else { - thread->system_time += 1; + thread->system_time += tick; if (thread == pcpu->idle_thread) { - pcpu->cpu_stat.idle += 1; + pcpu->cpu_stat.idle += tick; } else { - pcpu->cpu_stat.system += 1; + pcpu->cpu_stat.system += tick; } } } #else -#define _update_process_times() +#define _update_process_times(tick) #endif /* RT_USING_CPU_USAGE_TRACER */ /** @@ -124,7 +124,7 @@ void rt_tick_increase(void) RT_OBJECT_HOOK_CALL(rt_tick_hook, ()); /* tracing cpu usage */ - _update_process_times(); + _update_process_times(1); /* increase the global tick */ #ifdef RT_USING_SMP @@ -135,7 +135,41 @@ void rt_tick_increase(void) #endif /* RT_USING_SMP */ /* check time slice */ - rt_sched_tick_increase(); + rt_sched_tick_increase(1); + + /* check timer */ +#ifdef RT_USING_SMP + if (rt_cpu_get_id() != 0) + { + return; + } +#endif + rt_timer_check(); +} + +/** + * @brief This function will notify kernel there is n tick passed. + * Normally, this function is invoked by clock ISR. + */ +void rt_tick_increase_tick(rt_tick_t tick) +{ + RT_ASSERT(rt_interrupt_get_nest() > 0); + + RT_OBJECT_HOOK_CALL(rt_tick_hook, ()); + + /* tracing cpu usage */ + _update_process_times(tick); + + /* increase the global tick */ +#ifdef RT_USING_SMP + /* get percpu and increase the tick */ + rt_atomic_add(&(rt_cpu_self()->tick), tick); +#else + rt_atomic_add(&(rt_tick), tick); +#endif /* RT_USING_SMP */ + + /* check time slice */ + rt_sched_tick_increase(tick); /* check timer */ #ifdef RT_USING_SMP @@ -191,7 +225,7 @@ RTM_EXPORT(rt_tick_from_millisecond); */ rt_weak rt_tick_t rt_tick_get_millisecond(void) { -#if RT_TICK_PER_SECOND == 0 // make cppcheck happy +#if RT_TICK_PER_SECOND == 0 /* make cppcheck happy*/ #error "RT_TICK_PER_SECOND must be greater than zero" #endif diff --git a/src/scheduler_comm.c b/src/scheduler_comm.c index 6cf8a0c94b..4e5495e727 100644 --- a/src/scheduler_comm.c +++ b/src/scheduler_comm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2024, RT-Thread Development Team + * Copyright (c) 2006-2024 RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -144,7 +144,7 @@ rt_err_t rt_sched_thread_ready(struct rt_thread *thread) return error; } -rt_err_t rt_sched_tick_increase(void) +rt_err_t rt_sched_tick_increase(rt_tick_t tick) { struct rt_thread *thread; rt_sched_lock_level_t slvl; @@ -153,7 +153,15 @@ rt_err_t rt_sched_tick_increase(void) rt_sched_lock(&slvl); - RT_SCHED_PRIV(thread).remaining_tick--; + if(RT_SCHED_PRIV(thread).remaining_tick > tick) + { + RT_SCHED_PRIV(thread).remaining_tick -= tick; + } + else + { + RT_SCHED_PRIV(thread).remaining_tick = 0; + } + if (RT_SCHED_PRIV(thread).remaining_tick) { rt_sched_unlock(slvl); From bceb6635b09451e9d8ec150cd57f82b6a8cedfc1 Mon Sep 17 00:00:00 2001 From: wdfk-prog <1425075683@qq.com> Date: Thu, 11 Jul 2024 15:57:51 +0800 Subject: [PATCH 25/48] [compoents][pm]The device is registered and uninstalled by linked list --- components/drivers/include/drivers/pm.h | 40 ++-- components/drivers/pm/pm.c | 287 +++++++++++++----------- 2 files changed, 178 insertions(+), 149 deletions(-) diff --git a/components/drivers/include/drivers/pm.h b/components/drivers/include/drivers/pm.h index 45b3ae09e6..f625782616 100644 --- a/components/drivers/include/drivers/pm.h +++ b/components/drivers/include/drivers/pm.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2023, RT-Thread Development Team + * Copyright (c) 2006-2024 RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -10,6 +10,7 @@ * 2019-04-28 Zero-Free improve PM mode and device ops interface * 2020-11-23 zhangsz update pm mode select * 2020-11-27 zhangsz update pm 2.0 + * 2024-07-04 wdfk-prog The device is registered and uninstalled by linked list */ #ifndef __PM_H__ @@ -134,15 +135,16 @@ struct rt_pm_ops struct rt_device_pm_ops { - int (*suspend)(const struct rt_device *device, rt_uint8_t mode); + rt_err_t (*suspend)(const struct rt_device *device, rt_uint8_t mode); void (*resume)(const struct rt_device *device, rt_uint8_t mode); - int (*frequency_change)(const struct rt_device *device, rt_uint8_t mode); + rt_err_t (*frequency_change)(const struct rt_device *device, rt_uint8_t mode); }; struct rt_device_pm { const struct rt_device *device; const struct rt_device_pm_ops *ops; + rt_slist_t list; }; struct rt_pm_module @@ -172,7 +174,7 @@ struct rt_pm rt_uint32_t sleep_status[PM_SLEEP_MODE_MAX - 1][(PM_MODULE_MAX_ID + 31) / 32]; /* the list of device, which has PM feature */ - rt_uint8_t device_pm_number; + rt_slist_t device_list; struct rt_device_pm *device_pm; /* if the mode has timer, the corresponding bit is 1*/ @@ -194,10 +196,10 @@ struct rt_pm_notify void *data; }; -void rt_pm_request(rt_uint8_t sleep_mode); -void rt_pm_release(rt_uint8_t sleep_mode); -void rt_pm_release_all(rt_uint8_t sleep_mode); -int rt_pm_run_enter(rt_uint8_t run_mode); +rt_err_t rt_pm_request(rt_uint8_t sleep_mode); +rt_err_t rt_pm_release(rt_uint8_t sleep_mode); +rt_err_t rt_pm_release_all(rt_uint8_t sleep_mode); +rt_err_t rt_pm_run_enter(rt_uint8_t run_mode); void rt_pm_device_register(struct rt_device *device, const struct rt_device_pm_ops *ops); void rt_pm_device_unregister(struct rt_device *device); @@ -208,22 +210,22 @@ void rt_pm_default_set(rt_uint8_t sleep_mode); void rt_system_pm_init(const struct rt_pm_ops *ops, rt_uint8_t timer_mask, void *user_data); -void rt_pm_module_request(uint8_t module_id, rt_uint8_t sleep_mode); -void rt_pm_module_release(uint8_t module_id, rt_uint8_t sleep_mode); -void rt_pm_module_release_all(uint8_t module_id, rt_uint8_t sleep_mode); +rt_err_t rt_pm_module_request(uint8_t module_id, rt_uint8_t sleep_mode); +rt_err_t rt_pm_module_release(uint8_t module_id, rt_uint8_t sleep_mode); +rt_err_t rt_pm_module_release_all(uint8_t module_id, rt_uint8_t sleep_mode); void rt_pm_module_delay_sleep(rt_uint8_t module_id, rt_tick_t timeout); rt_uint32_t rt_pm_module_get_status(void); rt_uint8_t rt_pm_get_sleep_mode(void); struct rt_pm *rt_pm_get_handle(void); /* sleep : request or release */ -void rt_pm_sleep_request(rt_uint16_t module_id, rt_uint8_t mode); -void rt_pm_sleep_release(rt_uint16_t module_id, rt_uint8_t mode); -void rt_pm_sleep_none_request(rt_uint16_t module_id); -void rt_pm_sleep_none_release(rt_uint16_t module_id); -void rt_pm_sleep_idle_request(rt_uint16_t module_id); -void rt_pm_sleep_idle_release(rt_uint16_t module_id); -void rt_pm_sleep_light_request(rt_uint16_t module_id); -void rt_pm_sleep_light_release(rt_uint16_t module_id); +rt_err_t rt_pm_sleep_request(rt_uint16_t module_id, rt_uint8_t mode); +rt_err_t rt_pm_sleep_release(rt_uint16_t module_id, rt_uint8_t mode); +rt_err_t rt_pm_sleep_none_request(rt_uint16_t module_id); +rt_err_t rt_pm_sleep_none_release(rt_uint16_t module_id); +rt_err_t rt_pm_sleep_idle_request(rt_uint16_t module_id); +rt_err_t rt_pm_sleep_idle_release(rt_uint16_t module_id); +rt_err_t rt_pm_sleep_light_request(rt_uint16_t module_id); +rt_err_t rt_pm_sleep_light_release(rt_uint16_t module_id); #endif /* __PM_H__ */ diff --git a/components/drivers/pm/pm.c b/components/drivers/pm/pm.c index 024e301792..b4ad3b2bbd 100644 --- a/components/drivers/pm/pm.c +++ b/components/drivers/pm/pm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2023, RT-Thread Development Team + * Copyright (c) 2006-2024 RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -10,6 +10,7 @@ * 2019-04-28 Zero-Free improve PM mode and device ops interface * 2020-11-23 zhangsz update pm mode select * 2020-11-27 zhangsz update pm 2.0 + * 2024-07-04 wdfk-prog The device is registered and uninstalled by linked list */ #include @@ -77,9 +78,6 @@ rt_weak void rt_pm_exit_critical(rt_uint32_t ctx, rt_uint8_t sleep_mode) /* lptimer start */ static void pm_lptimer_start(struct rt_pm *pm, uint32_t timeout) { - if (_pm.ops == RT_NULL) - return; - if (_pm.ops->timer_start != RT_NULL) _pm.ops->timer_start(pm, timeout); } @@ -87,9 +85,6 @@ static void pm_lptimer_start(struct rt_pm *pm, uint32_t timeout) /* lptimer stop */ static void pm_lptimer_stop(struct rt_pm *pm) { - if (_pm.ops == RT_NULL) - return; - if (_pm.ops->timer_stop != RT_NULL) _pm.ops->timer_stop(pm); } @@ -97,9 +92,6 @@ static void pm_lptimer_stop(struct rt_pm *pm) /* lptimer get timeout tick */ static rt_tick_t pm_lptimer_get_timeout(struct rt_pm *pm) { - if (_pm.ops == RT_NULL) - return RT_TICK_MAX; - if (_pm.ops->timer_get_tick != RT_NULL) return _pm.ops->timer_get_tick(pm); @@ -109,9 +101,6 @@ static rt_tick_t pm_lptimer_get_timeout(struct rt_pm *pm) /* enter sleep mode */ static void pm_sleep(struct rt_pm *pm, uint8_t sleep_mode) { - if (_pm.ops == RT_NULL) - return; - if (_pm.ops->sleep != RT_NULL) _pm.ops->sleep(pm, sleep_mode); } @@ -119,17 +108,22 @@ static void pm_sleep(struct rt_pm *pm, uint8_t sleep_mode) /** * This function will suspend all registered devices */ -static int _pm_device_suspend(rt_uint8_t mode) +static rt_err_t _pm_device_suspend(rt_uint8_t mode) { - int index, ret = RT_EOK; + rt_err_t ret = RT_EOK; + struct rt_device_pm *device_pm = RT_NULL; + rt_slist_t *node = RT_NULL; - for (index = 0; index < _pm.device_pm_number; index++) + for (node = rt_slist_first(&_pm.device_list); node; node = rt_slist_next(node)) { - if (_pm.device_pm[index].ops->suspend != RT_NULL) + device_pm = rt_slist_entry(node, struct rt_device_pm, list); + if (device_pm->ops != RT_NULL && device_pm->ops->suspend != RT_NULL) { - ret = _pm.device_pm[index].ops->suspend(_pm.device_pm[index].device, mode); + ret = device_pm->ops->suspend(device_pm->device, mode); if(ret != RT_EOK) + { break; + } } } @@ -141,13 +135,15 @@ static int _pm_device_suspend(rt_uint8_t mode) */ static void _pm_device_resume(rt_uint8_t mode) { - int index; + struct rt_device_pm *device_pm = RT_NULL; + rt_slist_t *node = RT_NULL; - for (index = 0; index < _pm.device_pm_number; index++) + for (node = rt_slist_first(&_pm.device_list); node; node = rt_slist_next(node)) { - if (_pm.device_pm[index].ops->resume != RT_NULL) + device_pm = rt_slist_entry(node, struct rt_device_pm, list); + if (device_pm->ops != RT_NULL && device_pm->ops->resume != RT_NULL) { - _pm.device_pm[index].ops->resume(_pm.device_pm[index].device, mode); + device_pm->ops->resume(device_pm->device, mode); } } } @@ -157,13 +153,16 @@ static void _pm_device_resume(rt_uint8_t mode) */ static void _pm_device_frequency_change(rt_uint8_t mode) { - rt_uint32_t index; + struct rt_device_pm *device_pm = RT_NULL; + rt_slist_t *node = RT_NULL; - /* make the frequency change */ - for (index = 0; index < _pm.device_pm_number; index ++) + for (node = rt_slist_first(&_pm.device_list); node; node = rt_slist_next(node)) { - if (_pm.device_pm[index].ops->frequency_change != RT_NULL) - _pm.device_pm[index].ops->frequency_change(_pm.device_pm[index].device, mode); + device_pm = rt_slist_entry(node, struct rt_device_pm, list); + if (device_pm->ops->frequency_change != RT_NULL) + { + device_pm->ops->frequency_change(device_pm->device, mode); + } } } @@ -172,13 +171,16 @@ static void _pm_device_frequency_change(rt_uint8_t mode) */ static void _pm_frequency_scaling(struct rt_pm *pm) { - rt_base_t level; + rt_base_t level = 0; if (pm->flags & RT_PM_FREQUENCY_PENDING) { level = rt_hw_interrupt_disable(); /* change system runing mode */ - pm->ops->run(pm, pm->run_mode); + if(pm->ops->run != RT_NULL) + { + pm->ops->run(pm, pm->run_mode); + } /* changer device frequency */ _pm_device_frequency_change(pm->run_mode); pm->flags &= ~RT_PM_FREQUENCY_PENDING; @@ -288,6 +290,12 @@ static rt_bool_t _pm_device_check_idle(void) return RT_TRUE; } +/** + * @brief Get the next system wake-up time + * @note When used by default, it goes into STANDBY mode and sleeps forever. tickless external rewriting is required + * @param mode: sleep mode + * @retval timeout_tick + */ rt_weak rt_tick_t pm_timer_next_timeout_tick(rt_uint8_t mode) { switch (mode) @@ -344,6 +352,7 @@ rt_weak rt_uint8_t pm_get_sleep_threshold_mode(rt_uint8_t cur_mode, rt_tick_t ti else if (timeout_tick < PM_STANDBY_THRESHOLD_TIME) sleep_mode = PM_SLEEP_MODE_DEEP; } + cur_mode = sleep_mode; #else if (timeout_tick < PM_TICKLESS_THRESHOLD_TIME) { @@ -359,8 +368,8 @@ rt_weak rt_uint8_t pm_get_sleep_threshold_mode(rt_uint8_t cur_mode, rt_tick_t ti */ static void _pm_change_sleep_mode(struct rt_pm *pm) { - rt_tick_t timeout_tick, delta_tick; - rt_base_t level; + rt_tick_t timeout_tick = 0, delta_tick = 0; + rt_base_t level = 0; uint8_t sleep_mode = PM_SLEEP_MODE_DEEP; level = rt_pm_enter_critical(pm->sleep_mode); @@ -380,23 +389,27 @@ static void _pm_change_sleep_mode(struct rt_pm *pm) if (_pm.sleep_mode == PM_SLEEP_MODE_NONE) { - pm->ops->sleep(pm, PM_SLEEP_MODE_NONE); + pm_sleep(pm, PM_SLEEP_MODE_NONE); rt_pm_exit_critical(level, pm->sleep_mode); } else { /* Notify app will enter sleep mode */ if (_pm_notify.notify) + { _pm_notify.notify(RT_PM_ENTER_SLEEP, pm->sleep_mode, _pm_notify.data); + } /* Suspend all peripheral device */ #ifdef PM_ENABLE_SUSPEND_SLEEP_MODE - int ret = _pm_device_suspend(pm->sleep_mode); + rt_err_t ret = _pm_device_suspend(pm->sleep_mode); if (ret != RT_EOK) { _pm_device_resume(pm->sleep_mode); if (_pm_notify.notify) + { _pm_notify.notify(RT_PM_EXIT_SLEEP, pm->sleep_mode, _pm_notify.data); + } if (pm->sleep_mode > PM_SUSPEND_SLEEP_MODE) { pm->sleep_mode = PM_SUSPEND_SLEEP_MODE; @@ -419,14 +432,7 @@ static void _pm_change_sleep_mode(struct rt_pm *pm) if (pm->timer_mask & (0x01 << pm->sleep_mode)) { - if (timeout_tick == RT_TICK_MAX) - { - pm_lptimer_start(pm, RT_TICK_MAX); - } - else - { - pm_lptimer_start(pm, timeout_tick); - } + pm_lptimer_start(pm, timeout_tick); } } @@ -440,7 +446,9 @@ static void _pm_change_sleep_mode(struct rt_pm *pm) pm_lptimer_stop(pm); if (delta_tick) { - rt_tick_set(rt_tick_get() + delta_tick); + rt_interrupt_enter(); + rt_tick_increase_tick(delta_tick); + rt_interrupt_leave(); } } @@ -451,14 +459,6 @@ static void _pm_change_sleep_mode(struct rt_pm *pm) _pm_notify.notify(RT_PM_EXIT_SLEEP, pm->sleep_mode, _pm_notify.data); rt_pm_exit_critical(level, pm->sleep_mode); - - if (pm->timer_mask & (0x01 << pm->sleep_mode)) - { - if (delta_tick) - { - rt_timer_check(); - } - } } } @@ -467,8 +467,10 @@ static void _pm_change_sleep_mode(struct rt_pm *pm) */ void rt_system_power_manager(void) { - if (_pm_init_flag == 0) + if (_pm_init_flag == 0 || _pm.ops == RT_NULL) + { return; + } /* CPU frequency scaling according to the runing mode settings */ _pm_frequency_scaling(&_pm); @@ -483,22 +485,28 @@ void rt_system_power_manager(void) * * @param parameter the parameter of run mode or sleep mode */ -void rt_pm_request(rt_uint8_t mode) +rt_err_t rt_pm_request(rt_uint8_t mode) { rt_base_t level; struct rt_pm *pm; if (_pm_init_flag == 0) - return; + { + return -RT_EPERM; + } if (mode > (PM_SLEEP_MODE_MAX - 1)) - return; + { + return -RT_EINVAL; + } level = rt_hw_interrupt_disable(); pm = &_pm; if (pm->modes[mode] < 255) pm->modes[mode] ++; rt_hw_interrupt_enable(level); + + return RT_EOK; } /** @@ -508,22 +516,28 @@ void rt_pm_request(rt_uint8_t mode) * @param parameter the parameter of run mode or sleep mode * */ -void rt_pm_release(rt_uint8_t mode) +rt_err_t rt_pm_release(rt_uint8_t mode) { rt_base_t level; struct rt_pm *pm; if (_pm_init_flag == 0) - return; + { + return -RT_EPERM; + } if (mode > (PM_SLEEP_MODE_MAX - 1)) - return; + { + return -RT_EINVAL; + } level = rt_hw_interrupt_disable(); pm = &_pm; if (pm->modes[mode] > 0) pm->modes[mode] --; rt_hw_interrupt_enable(level); + + return RT_EOK; } /** @@ -533,21 +547,27 @@ void rt_pm_release(rt_uint8_t mode) * @param parameter the parameter of run mode or sleep mode * */ -void rt_pm_release_all(rt_uint8_t mode) +rt_err_t rt_pm_release_all(rt_uint8_t mode) { rt_base_t level; struct rt_pm *pm; if (_pm_init_flag == 0) - return; + { + return -RT_EPERM; + } if (mode > (PM_SLEEP_MODE_MAX - 1)) - return; + { + return -RT_EINVAL; + } level = rt_hw_interrupt_disable(); pm = &_pm; pm->modes[mode] = 0; rt_hw_interrupt_enable(level); + + return RT_EOK; } /** @@ -557,19 +577,25 @@ void rt_pm_release_all(rt_uint8_t mode) * @param module_id the application or device module id * @param mode the system power sleep mode */ -void rt_pm_module_request(uint8_t module_id, rt_uint8_t mode) +rt_err_t rt_pm_module_request(uint8_t module_id, rt_uint8_t mode) { rt_base_t level; struct rt_pm *pm; if (_pm_init_flag == 0) - return; + { + return -RT_EPERM; + } if (mode > (PM_SLEEP_MODE_MAX - 1)) - return; + { + return -RT_EINVAL; + } if (module_id > (PM_MODULE_MAX_ID - 1)) - return; + { + return -RT_EINVAL; + } level = rt_hw_interrupt_disable(); pm = &_pm; @@ -577,6 +603,8 @@ void rt_pm_module_request(uint8_t module_id, rt_uint8_t mode) if (pm->modes[mode] < 255) pm->modes[mode] ++; rt_hw_interrupt_enable(level); + + return RT_EOK; } /** @@ -587,19 +615,25 @@ void rt_pm_module_request(uint8_t module_id, rt_uint8_t mode) * @param mode the system power sleep mode * */ -void rt_pm_module_release(uint8_t module_id, rt_uint8_t mode) +rt_err_t rt_pm_module_release(uint8_t module_id, rt_uint8_t mode) { rt_base_t level; struct rt_pm *pm; if (_pm_init_flag == 0) - return; + { + return -RT_EPERM; + } if (mode > (PM_SLEEP_MODE_MAX - 1)) - return; + { + return -RT_EINVAL; + } if (module_id > (PM_MODULE_MAX_ID - 1)) - return; + { + return -RT_EINVAL; + } level = rt_hw_interrupt_disable(); pm = &_pm; @@ -608,6 +642,8 @@ void rt_pm_module_release(uint8_t module_id, rt_uint8_t mode) if (pm->modes[mode] == 0) pm->module_status[module_id].req_status = 0x00; rt_hw_interrupt_enable(level); + + return RT_EOK; } /** @@ -618,22 +654,28 @@ void rt_pm_module_release(uint8_t module_id, rt_uint8_t mode) * @param mode the system power sleep mode * */ -void rt_pm_module_release_all(uint8_t module_id, rt_uint8_t mode) +rt_err_t rt_pm_module_release_all(uint8_t module_id, rt_uint8_t mode) { rt_base_t level; struct rt_pm *pm; if (_pm_init_flag == 0) - return; + { + return -RT_EPERM; + } if (mode > (PM_SLEEP_MODE_MAX - 1)) - return; + { + return -RT_EINVAL; + } level = rt_hw_interrupt_disable(); pm = &_pm; pm->modes[mode] = 0; pm->module_status[module_id].req_status = 0x00; rt_hw_interrupt_enable(level); + + return RT_EOK; } /** @@ -644,23 +686,24 @@ void rt_pm_module_release_all(uint8_t module_id, rt_uint8_t mode) * * @return none */ -void rt_pm_sleep_request(rt_uint16_t module_id, rt_uint8_t mode) +rt_err_t rt_pm_sleep_request(rt_uint16_t module_id, rt_uint8_t mode) { rt_base_t level; if (module_id >= PM_MODULE_MAX_ID) { - return; + return -RT_EINVAL; } if (mode >= (PM_SLEEP_MODE_MAX - 1)) { - return; + return -RT_EINVAL; } level = rt_hw_interrupt_disable(); _pm.sleep_status[mode][module_id / 32] |= 1 << (module_id % 32); rt_hw_interrupt_enable(level); + return RT_EOK; } /** @@ -670,9 +713,9 @@ void rt_pm_sleep_request(rt_uint16_t module_id, rt_uint8_t mode) * * @return NULL */ -void rt_pm_sleep_none_request(rt_uint16_t module_id) +rt_err_t rt_pm_sleep_none_request(rt_uint16_t module_id) { - rt_pm_sleep_request(module_id, PM_SLEEP_MODE_NONE); + return rt_pm_sleep_request(module_id, PM_SLEEP_MODE_NONE); } /** @@ -682,9 +725,9 @@ void rt_pm_sleep_none_request(rt_uint16_t module_id) * * @return NULL */ -void rt_pm_sleep_idle_request(rt_uint16_t module_id) +rt_err_t rt_pm_sleep_idle_request(rt_uint16_t module_id) { - rt_pm_sleep_request(module_id, PM_SLEEP_MODE_IDLE); + return rt_pm_sleep_request(module_id, PM_SLEEP_MODE_IDLE); } /** @@ -694,9 +737,9 @@ void rt_pm_sleep_idle_request(rt_uint16_t module_id) * * @return NULL */ -void rt_pm_sleep_light_request(rt_uint16_t module_id) +rt_err_t rt_pm_sleep_light_request(rt_uint16_t module_id) { - rt_pm_sleep_request(module_id, PM_SLEEP_MODE_LIGHT); + return rt_pm_sleep_request(module_id, PM_SLEEP_MODE_LIGHT); } /** @@ -707,23 +750,24 @@ void rt_pm_sleep_light_request(rt_uint16_t module_id) * * @return NULL */ -void rt_pm_sleep_release(rt_uint16_t module_id, rt_uint8_t mode) +rt_err_t rt_pm_sleep_release(rt_uint16_t module_id, rt_uint8_t mode) { rt_base_t level; if (module_id >= PM_MODULE_MAX_ID) { - return; + return -RT_EINVAL; } if (mode >= (PM_SLEEP_MODE_MAX - 1)) { - return; + return -RT_EINVAL; } level = rt_hw_interrupt_disable(); _pm.sleep_status[mode][module_id / 32] &= ~(1 << (module_id % 32)); rt_hw_interrupt_enable(level); + return RT_EOK; } /** @@ -733,9 +777,9 @@ void rt_pm_sleep_release(rt_uint16_t module_id, rt_uint8_t mode) * * @return none */ -void rt_pm_sleep_none_release(rt_uint16_t module_id) +rt_err_t rt_pm_sleep_none_release(rt_uint16_t module_id) { - rt_pm_sleep_release(module_id, PM_SLEEP_MODE_NONE); + return rt_pm_sleep_release(module_id, PM_SLEEP_MODE_NONE); } /** @@ -745,9 +789,9 @@ void rt_pm_sleep_none_release(rt_uint16_t module_id) * * @return none */ -void rt_pm_sleep_idle_release(rt_uint16_t module_id) +rt_err_t rt_pm_sleep_idle_release(rt_uint16_t module_id) { - rt_pm_sleep_release(module_id, PM_SLEEP_MODE_IDLE); + return rt_pm_sleep_release(module_id, PM_SLEEP_MODE_IDLE); } /** @@ -757,9 +801,9 @@ void rt_pm_sleep_idle_release(rt_uint16_t module_id) * * @return none */ -void rt_pm_sleep_light_release(rt_uint16_t module_id) +rt_err_t rt_pm_sleep_light_release(rt_uint16_t module_id) { - rt_pm_sleep_release(module_id, PM_SLEEP_MODE_LIGHT); + return rt_pm_sleep_release(module_id, PM_SLEEP_MODE_LIGHT); } /** @@ -770,24 +814,15 @@ void rt_pm_sleep_light_release(rt_uint16_t module_id) */ void rt_pm_device_register(struct rt_device *device, const struct rt_device_pm_ops *ops) { - rt_base_t level; struct rt_device_pm *device_pm; - RT_DEBUG_NOT_IN_INTERRUPT; - - level = rt_hw_interrupt_disable(); - - device_pm = (struct rt_device_pm *)RT_KERNEL_REALLOC(_pm.device_pm, - (_pm.device_pm_number + 1) * sizeof(struct rt_device_pm)); + device_pm = RT_KERNEL_MALLOC(sizeof(struct rt_device_pm)); if (device_pm != RT_NULL) { - _pm.device_pm = device_pm; - _pm.device_pm[_pm.device_pm_number].device = device; - _pm.device_pm[_pm.device_pm_number].ops = ops; - _pm.device_pm_number += 1; + rt_slist_append(&_pm.device_list, &device_pm->list); + device_pm->device = device; + device_pm->ops = ops; } - - rt_hw_interrupt_enable(level); } /** @@ -797,32 +832,18 @@ void rt_pm_device_register(struct rt_device *device, const struct rt_device_pm_o */ void rt_pm_device_unregister(struct rt_device *device) { - rt_base_t level; - rt_uint32_t index; - RT_DEBUG_NOT_IN_INTERRUPT; - - level = rt_hw_interrupt_disable(); - - for (index = 0; index < _pm.device_pm_number; index ++) + struct rt_device_pm *device_pm = RT_NULL; + rt_slist_t *node = RT_NULL; + for (node = rt_slist_first(&_pm.device_list); node; node = rt_slist_next(node)) { - if (_pm.device_pm[index].device == device) + device_pm = rt_slist_entry(node, struct rt_device_pm, list); + if (device_pm->device == device) { - /* remove current entry */ - for (; index < _pm.device_pm_number - 1; index ++) - { - _pm.device_pm[index] = _pm.device_pm[index + 1]; - } - - _pm.device_pm[_pm.device_pm_number - 1].device = RT_NULL; - _pm.device_pm[_pm.device_pm_number - 1].ops = RT_NULL; - - _pm.device_pm_number -= 1; - /* break out and not touch memory */ + rt_slist_remove(&_pm.device_list, &device_pm->list); + RT_KERNEL_FREE(device_pm); break; } } - - rt_hw_interrupt_enable(level); } /** @@ -914,10 +935,11 @@ static rt_err_t _rt_pm_device_control(rt_device_t dev, return RT_EOK; } -int rt_pm_run_enter(rt_uint8_t mode) +rt_err_t rt_pm_run_enter(rt_uint8_t mode) { - rt_base_t level; - struct rt_pm *pm; + rt_base_t level = 0; + struct rt_pm *pm = RT_NULL; + rt_err_t ret = RT_EOK; if (_pm_init_flag == 0) return -RT_EIO; @@ -925,12 +947,16 @@ int rt_pm_run_enter(rt_uint8_t mode) if (mode > PM_RUN_MODE_MAX) return -RT_EINVAL; - level = rt_hw_interrupt_disable(); pm = &_pm; + + level = rt_hw_interrupt_disable(); if (mode < pm->run_mode) { /* change system runing mode */ - pm->ops->run(pm, mode); + if(pm->ops != RT_NULL && pm->ops->run != RT_NULL) + { + pm->ops->run(pm, mode); + } /* changer device frequency */ _pm_device_frequency_change(mode); } @@ -941,7 +967,7 @@ int rt_pm_run_enter(rt_uint8_t mode) pm->run_mode = mode; rt_hw_interrupt_enable(level); - return RT_EOK; + return ret; } #ifdef RT_USING_DEVICE_OPS @@ -1004,7 +1030,8 @@ void rt_system_pm_init(const struct rt_pm_ops *ops, pm->ops = ops; pm->device_pm = RT_NULL; - pm->device_pm_number = 0; + + rt_slist_init(&pm->device_list); #if IDLE_THREAD_STACK_SIZE <= 256 #error "[pm.c ERR] IDLE Stack Size Too Small!" From a837f2b8e9b921b6318b63d28f7f77a98ca752b0 Mon Sep 17 00:00:00 2001 From: wdfk-prog <1425075683@qq.com> Date: Thu, 11 Jul 2024 13:44:42 +0800 Subject: [PATCH 26/48] [compoents][hwtimer]Add a user control interface --- components/drivers/hwtimer/hwtimer.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/components/drivers/hwtimer/hwtimer.c b/components/drivers/hwtimer/hwtimer.c index bcf9ea9a2a..1b2792558d 100644 --- a/components/drivers/hwtimer/hwtimer.c +++ b/components/drivers/hwtimer/hwtimer.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2023, RT-Thread Development Team + * Copyright (c) 2006-2024 RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -320,7 +320,14 @@ static rt_err_t rt_hwtimer_control(struct rt_device *dev, int cmd, void *args) break; default: { - result = -RT_ENOSYS; + if (timer->ops->control != RT_NULL) + { + result = timer->ops->control(timer, cmd, args); + } + else + { + result = -RT_ENOSYS; + } } break; } From fccd98747ea68c38e1dcb4017e127a668c2e00ca Mon Sep 17 00:00:00 2001 From: wdfk-prog <1425075683@qq.com> Date: Thu, 11 Jul 2024 13:45:21 +0800 Subject: [PATCH 27/48] [stm32][lptim]lptimer is register with hwtimer, only supports pm calls,the timer function is not supported --- .../libraries/HAL_Drivers/drivers/SConscript | 4 +- .../drivers/config/h7/lptim_config.h | 67 ++++ .../HAL_Drivers/drivers/drv_config.h | 3 +- .../libraries/HAL_Drivers/drivers/drv_lptim.c | 369 ++++++++++++++---- .../libraries/HAL_Drivers/drivers/drv_lptim.h | 17 +- bsp/stm32/stm32h750-artpi/board/Kconfig | 17 + 6 files changed, 382 insertions(+), 95 deletions(-) create mode 100644 bsp/stm32/libraries/HAL_Drivers/drivers/config/h7/lptim_config.h diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/SConscript b/bsp/stm32/libraries/HAL_Drivers/drivers/SConscript index a07e753955..3a836bd427 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/SConscript +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/SConscript @@ -52,8 +52,10 @@ if GetDepend(['RT_USING_DAC']): if GetDepend(['RT_USING_CAN']): src += ['drv_can.c'] -if GetDepend(['RT_USING_PM', 'SOC_SERIES_STM32L4']): +if GetDepend(['RT_USING_PM']): src += ['drv_pm.c'] + +if GetDepend(['BSP_USING_LPTIM']): src += ['drv_lptim.c'] if GetDepend('BSP_USING_SDRAM'): diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/h7/lptim_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/h7/lptim_config.h new file mode 100644 index 0000000000..794289d88a --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/h7/lptim_config.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2006-2024 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-07-11 wdfk-prog first version + */ + +#ifndef __LPTIM_CONFIG_H__ +#define __LPTIM_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef LPTIM_DEV_INFO_CONFIG +#define LPTIM_DEV_INFO_CONFIG \ + { \ + .maxfreq = 1000000, \ + .minfreq = 3000, \ + .maxcnt = 0xFFFF, \ + .cntmode = HWTIMER_CNTMODE_UP, \ + } +#endif /* TIM_DEV_INFO_CONFIG */ + +#ifdef BSP_USING_LPTIM1 +#ifndef LPTIM1_CONFIG +#define LPTIM1_CONFIG \ + { \ + .tim_handle.Instance = LPTIM1, \ + .tim_irqn = LPTIM1_IRQn, \ + .name = "lptim1", \ + } +#endif /* LPTIM1_CONFIG */ +#endif /* BSP_USING_LPTIM1 */ + +#ifdef BSP_USING_LPTIM2 +#ifndef LPTIM2_CONFIG +#define LPTIM2_CONFIG \ + { \ + .tim_handle.Instance = LPTIM2, \ + .tim_irqn = LPTIM2_IRQn, \ + .name = "lptim2", \ + } +#endif /* LPTIM1_CONFIG */ +#endif /* BSP_USING_LPTIM1 */ + +#ifdef BSP_USING_LPTIM3 +#ifndef LPTIM3_CONFIG +#define LPTIM3_CONFIG \ + { \ + .tim_handle.Instance = LPTIM3, \ + .tim_irqn = LPTIM3_IRQn, \ + .name = "lptim3", \ + } +#endif /* LPTIM3_CONFIG */ +#endif /* BSP_USING_LPTIM3 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LPTIM_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_config.h index fdb6eef253..e7eda99b85 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2023, RT-Thread Development Team + * Copyright (c) 2006-2024 RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -122,6 +122,7 @@ extern "C" { #include "h7/adc_config.h" #include "h7/dac_config.h" #include "h7/tim_config.h" +#include "h7/lptim_config.h" #include "h7/sdio_config.h" #include "h7/pwm_config.h" #include "h7/usbd_config.h" diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_lptim.c b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_lptim.c index 60b8b368ac..192343f5be 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_lptim.c +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_lptim.c @@ -1,123 +1,320 @@ /* - * Copyright (c) 2006-2023, RT-Thread Development Team + * Copyright (c) 2006-2024 RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2019-05-06 Zero-Free first version + * 2024-07-04 wdfk-prog lptimer is register with hwtimer, only supports pm calls,the timer function is not supported */ #include #include +#include +#include "drv_config.h" -static LPTIM_HandleTypeDef LptimHandle; +/*#define DRV_DEBUG*/ +#define LOG_TAG "drv.lptim" +#include +#ifdef BSP_USING_LPTIM + +#define LPTIM_REG_MAX_VALUE (0xFFFF) + +enum +{ +#ifdef BSP_USING_LPTIM1 + LPTIM1_INDEX, +#endif +#ifdef BSP_USING_LPTIM2 + LPTIM2_INDEX, +#endif +#ifdef BSP_USING_LPTIM3 + LPTIM3_INDEX, +#endif +}; + +struct stm32_hw_lptimer +{ + rt_hwtimer_t time_device; + LPTIM_HandleTypeDef tim_handle; + IRQn_Type tim_irqn; + char *name; +}; + +static struct stm32_hw_lptimer stm32_hw_lptimer_obj[] = +{ +#ifdef BSP_USING_LPTIM1 + LPTIM1_CONFIG, +#endif +#ifdef BSP_USING_LPTIM2 + LPTIM2_CONFIG, +#endif +#ifdef BSP_USING_LPTIM3 + LPTIM3_CONFIG, +#endif +}; + +static const struct rt_hwtimer_info _info = LPTIM_DEV_INFO_CONFIG; + +static void timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state) +{ + if(timer == RT_NULL) + { + LOG_E("init timer is NULL"); + return; + } + + if (state) + { + struct stm32_hw_lptimer *tim_device = rt_container_of(timer, struct stm32_hw_lptimer, time_device); + LPTIM_HandleTypeDef *tim = (LPTIM_HandleTypeDef *)timer->parent.user_data; + + if(tim_device == RT_NULL) + { + LOG_E("start tim_device is NULL"); + return; + } + if(tim == RT_NULL) + { + LOG_E("start %s LPTIM_Handle is NULL", tim_device->name); + return; + } + + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct = {0}; + + /* Enable LSI clock */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + HAL_RCC_OscConfig(&RCC_OscInitStruct); + + /* Select the LSI clock as LPTIM peripheral clock */ + RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPTIM1; + RCC_PeriphCLKInitStruct.Lptim1ClockSelection = RCC_LPTIM1CLKSOURCE_LSI; + HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInitStruct); + + tim->Init.Clock.Source = LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC; + tim->Init.Clock.Prescaler = LPTIM_PRESCALER_DIV32; + tim->Init.Trigger.Source = LPTIM_TRIGSOURCE_SOFTWARE; + tim->Init.OutputPolarity = LPTIM_OUTPUTPOLARITY_HIGH; + tim->Init.UpdateMode = LPTIM_UPDATE_IMMEDIATE; + tim->Init.CounterSource = LPTIM_COUNTERSOURCE_INTERNAL; + + HAL_StatusTypeDef ret = HAL_LPTIM_Init(tim); + if (ret != HAL_OK) + { + LOG_E("%s init failed %d", tim_device->name, ret); + } + else + { + NVIC_ClearPendingIRQ(LPTIM1_IRQn); + NVIC_SetPriority(LPTIM1_IRQn, 0); + NVIC_EnableIRQ(LPTIM1_IRQn); + LOG_D("%s init success", tim_device->name); + } + } +} + +static rt_err_t timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_t opmode) +{ + if(timer == RT_NULL) + { + LOG_E("start timer is NULL"); + return -RT_EINVAL; + } + + struct stm32_hw_lptimer *tim_device = rt_container_of(timer, struct stm32_hw_lptimer, time_device); + LPTIM_HandleTypeDef *tim = (LPTIM_HandleTypeDef *)timer->parent.user_data; + + if(tim_device == RT_NULL) + { + LOG_E("start tim_device is NULL"); + return -RT_EINVAL; + } + if(tim == RT_NULL) + { + LOG_E("start %s LPTIM_Handle is NULL", tim_device->name); + return -RT_EINVAL; + } + + HAL_StatusTypeDef ret = HAL_LPTIM_TimeOut_Start_IT(tim, LPTIM_REG_MAX_VALUE, t); + if(ret != HAL_OK) + { + LOG_E("start %s failed %d", tim_device->name, ret); + return -RT_ERROR; + } + else + { + LOG_D("start %s success", tim_device->name); + return RT_EOK; + } +} + +static void timer_stop(rt_hwtimer_t *timer) +{ + if(timer == RT_NULL) + { + LOG_E("stop timer is NULL"); + return; + } + + struct stm32_hw_lptimer *tim_device = rt_container_of(timer, struct stm32_hw_lptimer, time_device); + LPTIM_HandleTypeDef *tim = (LPTIM_HandleTypeDef *)timer->parent.user_data; + + if(tim_device == RT_NULL) + { + LOG_E("stop tim_device is NULL"); + return; + } + if(tim == RT_NULL) + { + LOG_E("stop %s LPTIM_Handle is NULL", tim_device->name); + return; + } + + HAL_StatusTypeDef ret = HAL_LPTIM_TimeOut_Stop_IT(tim); + if(ret != HAL_OK) + { + LOG_E("stop %s failed %d", tim_device->name, ret); + } + else + { + LOG_D("stop %s success", tim_device->name); + } +} + +static rt_uint32_t timer_get_freq(LPTIM_HandleTypeDef *tim) +{ + /*No calculation is performed. The default initial configuration is 1000hz*/ + return 1000; +} + + +static rt_uint32_t timer_counter_get(rt_hwtimer_t *timer) +{ + LPTIM_HandleTypeDef *tim = (LPTIM_HandleTypeDef *)timer->parent.user_data; + return HAL_LPTIM_ReadCounter(tim); +} + +static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) +{ + if(timer == RT_NULL) + { + LOG_E("start timer is NULL"); + return -RT_EINVAL; + } + + struct stm32_hw_lptimer *tim_device = rt_container_of(timer, struct stm32_hw_lptimer, time_device); + LPTIM_HandleTypeDef *tim = (LPTIM_HandleTypeDef *)timer->parent.user_data; + + if(tim_device == RT_NULL) + { + LOG_E("start tim_device is NULL"); + return -RT_EINVAL; + } + if(tim == RT_NULL) + { + LOG_E("start %s LPTIM_Handle is NULL", tim_device->name); + return -RT_EINVAL; + } + + rt_err_t result = RT_EOK; + switch (cmd) + { + case DRV_HW_LPTIMER_CTRL_GET_TICK_MAX: + { + *(rt_uint32_t *)arg = LPTIM_REG_MAX_VALUE; + break; + } + case DRV_HW_LPTIMER_CTRL_GET_FREQ: + { + *(rt_uint32_t *)arg = timer_get_freq(tim); + break; + } + case DRV_HW_LPTIMER_CTRL_START: + { + timer_start(timer, *(rt_uint32_t *)arg, HWTIMER_MODE_ONESHOT); + break; + } + case DRV_HW_LPTIMER_CTRL_GET_COUNT: + { + *(rt_uint32_t *)arg = timer_counter_get(timer); + break; + } + default: + { + result = -RT_ENOSYS; + } + break; + } + + return result; +} + +#ifdef BSP_USING_LPTIM1 void LPTIM1_IRQHandler(void) { - HAL_LPTIM_IRQHandler(&LptimHandle); -} - -void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim) -{ - /* enter interrupt */ rt_interrupt_enter(); - - /* leave interrupt */ + HAL_LPTIM_IRQHandler(&stm32_hw_lptimer_obj[LPTIM1_INDEX].tim_handle); rt_interrupt_leave(); } +#endif -/** - * This function get current count value of LPTIM - * - * @return the count vlaue - */ -rt_uint32_t stm32l4_lptim_get_current_tick(void) +#ifdef BSP_USING_LPTIM2 +void LPTIM2_IRQHandler(void) { - return HAL_LPTIM_ReadCounter(&LptimHandle); + rt_interrupt_enter(); + HAL_LPTIM_IRQHandler(&stm32_hw_lptimer_obj[LPTIM2_INDEX].tim_handle); + rt_interrupt_leave(); } +#endif -/** - * This function get the max value that LPTIM can count - * - * @return the max count - */ -rt_uint32_t stm32l4_lptim_get_tick_max(void) +#ifdef BSP_USING_LPTIM3 +void LPTIM3_IRQHandler(void) { - return (0xFFFF); + rt_interrupt_enter(); + HAL_LPTIM_IRQHandler(&stm32_hw_lptimer_obj[LPTIM3_INDEX].tim_handle); + rt_interrupt_leave(); } +#endif -/** - * This function start LPTIM with reload value - * - * @param reload The value that LPTIM count down from - * - * @return RT_EOK - */ -rt_err_t stm32l4_lptim_start(rt_uint32_t reload) +static const struct rt_hwtimer_ops _ops = { - HAL_LPTIM_TimeOut_Start_IT(&LptimHandle, 0xFFFF, reload); - - return (RT_EOK); -} - -/** - * This function stop LPTIM - */ -void stm32l4_lptim_stop(void) -{ - rt_uint32_t _ier; - - _ier = LptimHandle.Instance->IER; - LptimHandle.Instance->ICR = LptimHandle.Instance->ISR & _ier; -} - -/** - * This function get the count clock of LPTIM - * - * @return the count clock frequency in Hz - */ -rt_uint32_t stm32l4_lptim_get_countfreq(void) -{ - return 32000 / 32; -} + .init = timer_init, + .start = timer_start, + .stop = timer_stop, + .count_get = timer_counter_get, + .control = timer_ctrl, +}; /** * This function initialize the lptim */ -int stm32l4_hw_lptim_init(void) +static int stm32_hw_lptim_init(void) { - RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct = {0}; + int i = 0; + int result = RT_EOK; - /* Enable LSI clock */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI; - RCC_OscInitStruct.LSIState = RCC_LSI_ON; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; - HAL_RCC_OscConfig(&RCC_OscInitStruct); - - /* Select the LSI clock as LPTIM peripheral clock */ - RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPTIM1; - RCC_PeriphCLKInitStruct.Lptim1ClockSelection = RCC_LPTIM1CLKSOURCE_LSI; - HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInitStruct); - - LptimHandle.Instance = LPTIM1; - LptimHandle.Init.Clock.Source = LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC; - LptimHandle.Init.Clock.Prescaler = LPTIM_PRESCALER_DIV32; - LptimHandle.Init.Trigger.Source = LPTIM_TRIGSOURCE_SOFTWARE; - LptimHandle.Init.OutputPolarity = LPTIM_OUTPUTPOLARITY_HIGH; - LptimHandle.Init.UpdateMode = LPTIM_UPDATE_IMMEDIATE; - LptimHandle.Init.CounterSource = LPTIM_COUNTERSOURCE_INTERNAL; - if (HAL_LPTIM_Init(&LptimHandle) != HAL_OK) + for (i = 0; i < sizeof(stm32_hw_lptimer_obj) / sizeof(stm32_hw_lptimer_obj[0]); i++) { - return -1; + stm32_hw_lptimer_obj[i].time_device.info = &_info; + stm32_hw_lptimer_obj[i].time_device.ops = &_ops; + if (rt_device_hwtimer_register(&stm32_hw_lptimer_obj[i].time_device, stm32_hw_lptimer_obj[i].name, &stm32_hw_lptimer_obj[i].tim_handle) == RT_EOK) + { + LOG_D("%s register success", stm32_hw_lptimer_obj[i].name); + } + else + { + LOG_E("%s register failed", stm32_hw_lptimer_obj[i].name); + result = -RT_ERROR; + } } - NVIC_ClearPendingIRQ(LPTIM1_IRQn); - NVIC_SetPriority(LPTIM1_IRQn, 0); - NVIC_EnableIRQ(LPTIM1_IRQn); - - return 0; + return result; } -INIT_DEVICE_EXPORT(stm32l4_hw_lptim_init); +INIT_BOARD_EXPORT(stm32_hw_lptim_init); +#endif /* BSP_USING_LPTIM */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_lptim.h b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_lptim.h index 79f3e11753..124242abb5 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_lptim.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_lptim.h @@ -1,11 +1,12 @@ /* - * Copyright (c) 2006-2023, RT-Thread Development Team + * Copyright (c) 2006-2024 RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2019-05-06 Zero-Free first version + * 2024-07-04 wdfk-prog lptimer is register with hwtimer, only supports pm calls,the timer function is not supported */ #ifndef __DRV_PMTIMER_H__ @@ -13,11 +14,13 @@ #include -rt_uint32_t stm32l4_lptim_get_countfreq(void); -rt_uint32_t stm32l4_lptim_get_tick_max(void); -rt_uint32_t stm32l4_lptim_get_current_tick(void); - -rt_err_t stm32l4_lptim_start(rt_uint32_t load); -void stm32l4_lptim_stop(void); +/* 0x20 - 0x3F udevice control commands*/ +typedef enum +{ + DRV_HW_LPTIMER_CTRL_GET_TICK_MAX = 0x20, /* get the maximum tick value*/ + DRV_HW_LPTIMER_CTRL_GET_FREQ = 0X21, /* get the timer frequency*/ + DRV_HW_LPTIMER_CTRL_START = 0X22, /* set the timeout value*/ + DRV_HW_LPTIMER_CTRL_GET_COUNT = 0X23, /* get the current count value*/ +} drv_hw_lptimer_ctrl_t; #endif /* __DRV_PMTIMER_H__ */ diff --git a/bsp/stm32/stm32h750-artpi/board/Kconfig b/bsp/stm32/stm32h750-artpi/board/Kconfig index 63ca343eb7..122d147adb 100644 --- a/bsp/stm32/stm32h750-artpi/board/Kconfig +++ b/bsp/stm32/stm32h750-artpi/board/Kconfig @@ -224,6 +224,23 @@ menu "On-chip Peripheral Drivers" endif endif + menuconfig BSP_USING_LPTIM + bool "Enable lptimer" + default n + select RT_USING_LPTIMER + select RT_USING_HWTIMER + if BSP_USING_LPTIM + config BSP_USING_LPTIM1 + bool "Enable LPTIM1" + default n + config BSP_USING_LPTIM2 + bool "Enable LPTIM2" + default n + config BSP_USING_LPTIM3 + bool "Enable LPTIM3" + default n + endif + menuconfig BSP_USING_SPI bool "Enable SPI" default n From 568356cc48dcda8d802890290c5970aa7f8511ff Mon Sep 17 00:00:00 2001 From: wdfk-prog <1425075683@qq.com> Date: Thu, 11 Jul 2024 16:41:06 +0800 Subject: [PATCH 28/48] [stm32][pm]lptimer is supported --- .../libraries/HAL_Drivers/drivers/drv_pm.c | 209 ++++++++++-------- .../libraries/HAL_Drivers/drivers/drv_rtc.c | 8 +- 2 files changed, 123 insertions(+), 94 deletions(-) diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_pm.c b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_pm.c index 9d336a3429..3a5794dab2 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_pm.c +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_pm.c @@ -1,22 +1,51 @@ /* - * Copyright (c) 2006-2023, RT-Thread Development Team + * Copyright (c) 2006-2024 RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2019-05-06 Zero-Free first version + * 2024-07-04 wdfk-prog lptimer is supported */ #include #include #include +#include -static void uart_console_reconfig(void) +/*#define DRV_DEBUG*/ +#define LOG_TAG "drv.pm" +#include + +#ifdef RT_USING_PM + +#ifndef BSP_USING_PM_TIMER +/* +! Using LPTIM timer, the maximum sleep time is 65535, less than 1 min. Use RTC alarm timers for longer periods. +! For example: packages can be used :https://packages.rt-thread.org/detail.html?package=multi_rtimer +*/ +#ifdef BSP_USING_LPTIM1 +#define BSP_USING_PM_TIMER "lptim1" +#elif BSP_USING_LPTIM2 +#define BSP_USING_PM_TIMER "lptim2" +#elif BSP_USING_LPTIM3 +#define BSP_USING_PM_TIMER "lptim3" +#else +#error "Please define BSP_USING_PM_TIMER" +#endif + +static rt_device_t timer = RT_NULL; + +/* Re-configure the system clock */ +rt_weak void SystemClock_ReConfig(uint8_t run_mode) { - struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + /*todo add your code here*/ +} - rt_device_control(rt_console_get_device(), RT_DEVICE_CTRL_CONFIG, &config); +rt_weak void stm32_pm_device_run(struct rt_pm *pm, uint8_t mode) +{ + /*todo add your code here*/ } /** @@ -32,7 +61,6 @@ static void sleep(struct rt_pm *pm, uint8_t mode) break; case PM_SLEEP_MODE_IDLE: - // __WFI(); break; case PM_SLEEP_MODE_LIGHT: @@ -49,10 +77,12 @@ static void sleep(struct rt_pm *pm, uint8_t mode) break; case PM_SLEEP_MODE_DEEP: +#if defined(SOC_SERIES_STM32L4) /* Enter STOP 2 mode */ HAL_PWREx_EnterSTOP2Mode(PWR_STOPENTRY_WFI); /* Re-configure the system clock */ SystemClock_ReConfig(pm->run_mode); +#endif /* defined(SOC_SERIES_STM32L4) */ break; case PM_SLEEP_MODE_STANDBY: @@ -61,74 +91,17 @@ static void sleep(struct rt_pm *pm, uint8_t mode) break; case PM_SLEEP_MODE_SHUTDOWN: +#if defined(SOC_SERIES_STM32L4) /* Enter SHUTDOWNN mode */ HAL_PWREx_EnterSHUTDOWNMode(); +#endif /* defined(SOC_SERIES_STM32L4) */ break; default: - RT_ASSERT(0); break; } } -static uint8_t run_speed[PM_RUN_MODE_MAX][2] = -{ - {80, 0}, - {80, 1}, - {24, 2}, - {2, 3}, -}; - -static void run(struct rt_pm *pm, uint8_t mode) -{ - static uint8_t last_mode; - static char *run_str[] = PM_RUN_MODE_NAMES; - - if (mode == last_mode) - return; - last_mode = mode; - - /* 1. 设置 MSI 作为 SYSCLK 时钟源,以修改 PLL */ - SystemClock_MSI_ON(); - - /* 2. 根据RUN模式切换时钟频率(HSI) */ - switch (mode) - { - case PM_RUN_MODE_HIGH_SPEED: - case PM_RUN_MODE_NORMAL_SPEED: - HAL_PWREx_DisableLowPowerRunMode(); - SystemClock_80M(); - /* Configure the main internal regulator output voltage (Range1 by default)*/ - HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1); - break; - case PM_RUN_MODE_MEDIUM_SPEED: - HAL_PWREx_DisableLowPowerRunMode(); - SystemClock_24M(); - /* Configure the main internal regulator output voltage */ - HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE2); - break; - case PM_RUN_MODE_LOW_SPEED: - SystemClock_2M(); - /* Enter LP RUN mode */ - HAL_PWREx_EnableLowPowerRunMode(); - break; - default: - break; - } - - /* 3. 关闭 MSI 时钟 */ - // SystemClock_MSI_OFF(); - - /* 4. 更新外设时钟 */ - uart_console_reconfig(); - /* Re-Configure the Systick time */ - HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / RT_TICK_PER_SECOND); - /* Re-Configure the Systick */ - HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK); - - rt_kprintf("switch to %s mode, frequency = %d MHz\n", run_str[mode], run_speed[mode][0]); -} - /** * This function caculate the PM tick from OS tick * @@ -136,9 +109,19 @@ static void run(struct rt_pm *pm, uint8_t mode) * * @return the PM tick */ -static rt_tick_t stm32l4_pm_tick_from_os_tick(rt_tick_t tick) +static rt_tick_t stm32_pm_tick_from_os_tick(rt_tick_t tick) { - rt_uint32_t freq = stm32l4_lptim_get_countfreq(); + rt_uint32_t freq = 0; + rt_err_t ret = rt_device_control(timer, DRV_HW_LPTIMER_CTRL_GET_FREQ, &freq); + if(ret != RT_EOK) + { + LOG_E("Get PM timer %s frequency failed %d", timer->parent.name, ret); + return 0; + } + else + { + LOG_D("Get PM timer %s frequency %d", timer->parent.name, freq); + } return (freq * tick / RT_TICK_PER_SECOND); } @@ -150,18 +133,25 @@ static rt_tick_t stm32l4_pm_tick_from_os_tick(rt_tick_t tick) * * @return the OS tick */ -static rt_tick_t stm32l4_os_tick_from_pm_tick(rt_uint32_t tick) +static rt_tick_t stm32_os_tick_from_pm_tick(rt_uint32_t tick) { static rt_uint32_t os_tick_remain = 0; - rt_uint32_t ret, freq; + rt_tick_t os_tick = 0; + rt_uint32_t freq = 0; - freq = stm32l4_lptim_get_countfreq(); - ret = (tick * RT_TICK_PER_SECOND + os_tick_remain) / freq; + rt_err_t ret = rt_device_control(timer, DRV_HW_LPTIMER_CTRL_GET_FREQ, &freq); + if(ret != RT_EOK) + { + LOG_E("Get PM timer %s frequency failed %d", timer->parent.name, ret); + return 0; + } + + os_tick = (tick * RT_TICK_PER_SECOND + os_tick_remain) / freq; os_tick_remain += (tick * RT_TICK_PER_SECOND); os_tick_remain %= freq; - return ret; + return os_tick; } /** @@ -174,18 +164,33 @@ static void pm_timer_start(struct rt_pm *pm, rt_uint32_t timeout) { RT_ASSERT(pm != RT_NULL); RT_ASSERT(timeout > 0); + RT_ASSERT(timer != RT_NULL); if (timeout != RT_TICK_MAX) { - /* Convert OS Tick to pmtimer timeout value */ - timeout = stm32l4_pm_tick_from_os_tick(timeout); - if (timeout > stm32l4_lptim_get_tick_max()) + rt_uint32_t max_tick = 0; + rt_err_t ret = rt_device_control(timer, DRV_HW_LPTIMER_CTRL_GET_TICK_MAX, &max_tick); + if(ret != RT_EOK) { - timeout = stm32l4_lptim_get_tick_max(); + LOG_E("Get PM timer %s max tick failed %d", timer->parent.name, ret); + return; + } + + /* Convert OS Tick to pmtimer timeout value */ + timeout = stm32_pm_tick_from_os_tick(timeout); + + if (timeout > max_tick) + { + timeout = max_tick; } /* Enter PM_TIMER_MODE */ - stm32l4_lptim_start(timeout); + ret = rt_device_control(timer, DRV_HW_LPTIMER_CTRL_START, &timeout); + if(ret != RT_EOK) + { + LOG_E("Get PM timer %s max tick failed %d", timer->parent.name, ret); + return; + } } } @@ -199,7 +204,7 @@ static void pm_timer_stop(struct rt_pm *pm) RT_ASSERT(pm != RT_NULL); /* Reset pmtimer status */ - stm32l4_lptim_stop(); + rt_device_control(timer, HWTIMER_CTRL_STOP, RT_NULL); } /** @@ -215,29 +220,42 @@ static rt_tick_t pm_timer_get_tick(struct rt_pm *pm) RT_ASSERT(pm != RT_NULL); - timer_tick = stm32l4_lptim_get_current_tick(); + rt_err_t ret = rt_device_control(timer, DRV_HW_LPTIMER_CTRL_GET_COUNT, &timer_tick); - return stm32l4_os_tick_from_pm_tick(timer_tick); + if(ret != RT_EOK) + { + LOG_E("Get PM timer %s count failed %d", timer->parent.name, ret); + return 0; + } + else + { + return stm32_os_tick_from_pm_tick(timer_tick); + } } +static const struct rt_pm_ops _ops = +{ + sleep, + stm32_pm_device_run, + pm_timer_start, + pm_timer_stop, + pm_timer_get_tick +}; + /** * This function initialize the power manager */ int drv_pm_hw_init(void) { - static const struct rt_pm_ops _ops = - { - sleep, - run, - pm_timer_start, - pm_timer_stop, - pm_timer_get_tick - }; - rt_uint8_t timer_mask = 0; /* Enable Power Clock */ +#if !defined(SOC_SERIES_STM32H7) && !defined(SOC_SERIES_STM32WL) && !defined(SOC_SERIES_STM32WB) __HAL_RCC_PWR_CLK_ENABLE(); +#ifdef SOC_SERIES_STM32F1 + __HAL_RCC_BKP_CLK_ENABLE(); +#endif +#endif /* initialize timer mask */ timer_mask = 1UL << PM_SLEEP_MODE_DEEP; @@ -245,7 +263,18 @@ int drv_pm_hw_init(void) /* initialize system pm module */ rt_system_pm_init(&_ops, timer_mask, RT_NULL); - return 0; + timer = rt_device_find(BSP_USING_PM_TIMER); + + if(timer == RT_NULL) + { + LOG_E("Can't find PM timer device"); + return -RT_ERROR; + } + else + { + return rt_device_init(timer); + } } -INIT_BOARD_EXPORT(drv_pm_hw_init); +INIT_CORE_EXPORT(drv_pm_hw_init); +#endif /* RT_USING_PM */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_rtc.c b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_rtc.c index d5bc35057b..41097fe1fb 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_rtc.c +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_rtc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2023, RT-Thread Development Team + * Copyright (c) 2006-2024 RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -22,7 +22,7 @@ #define RTC_BKP_DR1 RT_NULL #endif -//#define DRV_DEBUG +/* #define DRV_DEBUG*/ #define LOG_TAG "drv.rtc" #include @@ -393,7 +393,7 @@ static rt_err_t rtc_alarm_time_set(struct rtc_device_object* p_dev) void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc) { - //LOG_D("rtc alarm isr.\n"); + /*LOG_D("rtc alarm isr.\n");*/ rt_alarm_update(&rtc_device.rtc_dev.parent, 1); } @@ -424,5 +424,5 @@ static int rt_hw_rtc_init(void) return RT_EOK; } -INIT_DEVICE_EXPORT(rt_hw_rtc_init); +INIT_BOARD_EXPORT(rt_hw_rtc_init); #endif /* BSP_USING_ONCHIP_RTC */ From 1a596607ed4b206aa9778d3d8202b047211435af Mon Sep 17 00:00:00 2001 From: Rbb666 Date: Fri, 12 Jul 2024 13:53:14 +0800 Subject: [PATCH 29/48] =?UTF-8?q?=E5=88=A0=E9=99=A4bsp:stm32l476=E7=9A=84p?= =?UTF-8?q?m=E7=BB=84=E4=BB=B6=E4=BE=9D=E8=B5=96?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- bsp/stm32/stm32l476-st-nucleo/.config | 177 ++++++++++++++++++----- bsp/stm32/stm32l476-st-nucleo/rtconfig.h | 96 ++++++++++-- 2 files changed, 228 insertions(+), 45 deletions(-) diff --git a/bsp/stm32/stm32l476-st-nucleo/.config b/bsp/stm32/stm32l476-st-nucleo/.config index edd160ed20..cea6a58d51 100644 --- a/bsp/stm32/stm32l476-st-nucleo/.config +++ b/bsp/stm32/stm32l476-st-nucleo/.config @@ -1,7 +1,3 @@ -# -# Automatically generated file; DO NOT EDIT. -# RT-Thread Configuration -# CONFIG_SOC_STM32L476RG=y CONFIG_BOARD_STM32L476_NUCLEO=y @@ -21,7 +17,6 @@ CONFIG_RT_THREAD_PRIORITY_32=y # CONFIG_RT_THREAD_PRIORITY_256 is not set CONFIG_RT_THREAD_PRIORITY_MAX=32 CONFIG_RT_TICK_PER_SECOND=1000 -CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y CONFIG_RT_HOOK_USING_FUNC_PTR=y # CONFIG_RT_USING_HOOKLIST is not set @@ -29,18 +24,28 @@ CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 CONFIG_IDLE_THREAD_STACK_SIZE=1024 # CONFIG_RT_USING_TIMER_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set # # kservice optimization # -# CONFIG_RT_KSERVICE_USING_STDLIB is not set -# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set # CONFIG_RT_USING_TINY_FFS is not set -# CONFIG_RT_KPRINTF_USING_LONGLONG is not set +# end of kservice optimization + +# +# klibc optimization +# +# CONFIG_RT_KLIBC_USING_STDLIB is not set +# CONFIG_RT_KLIBC_USING_TINY_SIZE is not set +# CONFIG_RT_KLIBC_USING_PRINTF_LONGLONG is not set +# end of klibc optimization + CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_ASSERT=y CONFIG_RT_DEBUGING_COLOR=y CONFIG_RT_DEBUGING_CONTEXT=y # CONFIG_RT_DEBUGING_AUTO_INIT is not set +CONFIG_RT_USING_OVERFLOW_CHECK=y # # Inter-Thread communication @@ -52,6 +57,7 @@ CONFIG_RT_USING_MAILBOX=y CONFIG_RT_USING_MESSAGEQUEUE=y # CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set # CONFIG_RT_USING_SIGNALS is not set +# end of Inter-Thread communication # # Memory Management @@ -68,6 +74,8 @@ CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y # CONFIG_RT_USING_MEMTRACE is not set # CONFIG_RT_USING_HEAP_ISR is not set CONFIG_RT_USING_HEAP=y +# end of Memory Management + CONFIG_RT_USING_DEVICE=y # CONFIG_RT_USING_DEVICE_OPS is not set # CONFIG_RT_USING_INTERRUPT_INFO is not set @@ -76,13 +84,12 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=256 CONFIG_RT_CONSOLE_DEVICE_NAME="uart2" -CONFIG_RT_VER_NUM=0x50100 +CONFIG_RT_VER_NUM=0x50200 # CONFIG_RT_USING_STDC_ATOMIC is not set CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 -# CONFIG_RT_USING_CACHE is not set +# end of RT-Thread Kernel + CONFIG_RT_USING_HW_ATOMIC=y -# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set -# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set CONFIG_RT_USING_CPU_FFS=y CONFIG_ARCH_ARM=y CONFIG_ARCH_ARM_CORTEX_M=y @@ -117,12 +124,15 @@ CONFIG_FINSH_USING_OPTION_COMPLETION=y # DFS: device virtual file system # # CONFIG_RT_USING_DFS is not set +# end of DFS: device virtual file system + # CONFIG_RT_USING_FAL is not set # # Device Drivers # # CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_DEV_BUS is not set CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_UNAMED_PIPE_NUMBER=64 # CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set @@ -141,17 +151,12 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_ZERO is not set # CONFIG_RT_USING_RANDOM is not set # CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set -CONFIG_RT_USING_PM=y -CONFIG_PM_TICKLESS_THRESHOLD_TIME=2 -# CONFIG_PM_USING_CUSTOM_CONFIG is not set -# CONFIG_PM_ENABLE_DEBUG is not set -# CONFIG_PM_ENABLE_SUSPEND_SLEEP_MODE is not set -# CONFIG_PM_ENABLE_THRESHOLD_SLEEP_MODE is not set -CONFIG_RT_USING_RTC=y -# CONFIG_RT_USING_ALARM is not set -# CONFIG_RT_USING_SOFT_RTC is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set # CONFIG_RT_USING_SPI is not set # CONFIG_RT_USING_WDT is not set @@ -160,21 +165,13 @@ CONFIG_RT_USING_RTC=y # CONFIG_RT_USING_TOUCH is not set # CONFIG_RT_USING_LCD is not set # CONFIG_RT_USING_HWCRYPTO is not set -# CONFIG_RT_USING_PULSE_ENCODER is not set -# CONFIG_RT_USING_INPUT_CAPTURE is not set -# CONFIG_RT_USING_DEV_BUS is not set # CONFIG_RT_USING_WIFI is not set # CONFIG_RT_USING_VIRTIO is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_KTIME is not set # CONFIG_RT_USING_HWTIMER is not set - -# -# Using USB -# -# CONFIG_RT_USING_USB is not set -# CONFIG_RT_USING_USB_HOST is not set -# CONFIG_RT_USING_USB_DEVICE is not set +# CONFIG_RT_USING_CHERRYUSB is not set +# end of Device Drivers # # C/C++ and POSIX layer @@ -192,6 +189,8 @@ CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 +# end of Timezone and Daylight Saving Time +# end of ISO-ANSI C layer # # POSIX (Portable Operating System Interface) layer @@ -213,7 +212,11 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # Socket is in the 'Network' category # +# end of Interprocess Communication (IPC) +# end of POSIX (Portable Operating System Interface) layer + # CONFIG_RT_USING_CPLUSPLUS is not set +# end of C/C++ and POSIX layer # # Network @@ -222,12 +225,14 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_RT_USING_NETDEV is not set # CONFIG_RT_USING_LWIP is not set # CONFIG_RT_USING_AT is not set +# end of Network # # Memory protection # # CONFIG_RT_USING_MEM_PROTECTION is not set # CONFIG_RT_USING_HW_STACK_GUARD is not set +# end of Memory protection # # Utilities @@ -239,12 +244,25 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_RT_USING_RESOURCE_ID is not set # CONFIG_RT_USING_ADT is not set # CONFIG_RT_USING_RT_LINK is not set +# end of Utilities + # CONFIG_RT_USING_VBUS is not set +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set +# end of RT-Thread Components + # # RT-Thread Utestcases # # CONFIG_RT_USING_UTESTCASES is not set +# end of RT-Thread Utestcases # # RT-Thread online packages @@ -253,7 +271,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # IoT - internet of things # -# CONFIG_PKG_USING_LWIP is not set # CONFIG_PKG_USING_LORAWAN_DRIVER is not set # CONFIG_PKG_USING_PAHOMQTT is not set # CONFIG_PKG_USING_UMQTT is not set @@ -266,6 +283,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set # # Wi-Fi @@ -275,27 +293,35 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # Marvell WiFi # # CONFIG_PKG_USING_WLANMARVELL is not set +# end of Marvell WiFi # # Wiced WiFi # # CONFIG_PKG_USING_WLAN_WICED is not set +# end of Wiced WiFi + # CONFIG_PKG_USING_RW007 is not set # # CYW43012 WiFi # # CONFIG_PKG_USING_WLAN_CYW43012 is not set +# end of CYW43012 WiFi # # BL808 WiFi # # CONFIG_PKG_USING_WLAN_BL808 is not set +# end of BL808 WiFi # # CYW43439 WiFi # # CONFIG_PKG_USING_WLAN_CYW43439 is not set +# end of CYW43439 WiFi +# end of Wi-Fi + # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set @@ -318,6 +344,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set # CONFIG_PKG_USING_JOYLINK is not set # CONFIG_PKG_USING_IOTSHARP_SDK is not set +# end of IoT Cloud + # CONFIG_PKG_USING_NIMBLE is not set # CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set # CONFIG_PKG_USING_OTA_DOWNLOADER is not set @@ -360,6 +388,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ZEPHYR_POLLING is not set # CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set # CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set +# end of IoT - internet of things # # security packages @@ -370,6 +400,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_TINYCRYPT is not set # CONFIG_PKG_USING_TFM is not set # CONFIG_PKG_USING_YD_CRYPTO is not set +# end of security packages # # language packages @@ -385,18 +416,22 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_JSMN is not set # CONFIG_PKG_USING_AGILE_JSMN is not set # CONFIG_PKG_USING_PARSON is not set +# end of JSON: JavaScript Object Notation, a lightweight data-interchange format # # XML: Extensible Markup Language # # CONFIG_PKG_USING_SIMPLE_XML is not set # CONFIG_PKG_USING_EZXML is not set +# end of XML: Extensible Markup Language + # CONFIG_PKG_USING_LUATOS_SOC is not set # CONFIG_PKG_USING_LUA is not set # CONFIG_PKG_USING_JERRYSCRIPT is not set # CONFIG_PKG_USING_MICROPYTHON is not set # CONFIG_PKG_USING_PIKASCRIPT is not set # CONFIG_PKG_USING_RTT_RUST is not set +# end of language packages # # multimedia packages @@ -408,12 +443,15 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_LVGL is not set # CONFIG_PKG_USING_LV_MUSIC_DEMO is not set # CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set +# end of LVGL: powerful and easy-to-use embedded GUI library # # u8g2: a monochrome graphic library # # CONFIG_PKG_USING_U8G2_OFFICIAL is not set # CONFIG_PKG_USING_U8G2 is not set +# end of u8g2: a monochrome graphic library + # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set # CONFIG_PKG_USING_STEMWIN is not set @@ -434,6 +472,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_GUIENGINE is not set # CONFIG_PKG_USING_PERSIMMON is not set # CONFIG_PKG_USING_3GPP_AMRNB is not set +# end of multimedia packages # # tools packages @@ -483,6 +522,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_VOFA_PLUS is not set # CONFIG_PKG_USING_RT_TRACE is not set # CONFIG_PKG_USING_ZDEBUG is not set +# end of tools packages # # system packages @@ -494,6 +534,9 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RT_MEMCPY_CM is not set # CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set # CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set +# end of enhanced kernel services + +# CONFIG_PKG_USING_AUNITY is not set # # acceleration: Assembly language or algorithmic acceleration packages @@ -501,16 +544,21 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_QFPLIB_M0_FULL is not set # CONFIG_PKG_USING_QFPLIB_M0_TINY is not set # CONFIG_PKG_USING_QFPLIB_M3 is not set +# end of acceleration: Assembly language or algorithmic acceleration packages # # CMSIS: ARM Cortex-M Microcontroller Software Interface Standard # # CONFIG_PKG_USING_CMSIS_5 is not set -# CONFIG_PKG_USING_CMSIS_CORE is not set +CONFIG_PKG_USING_CMSIS_CORE=y +CONFIG_PKG_CMSIS_CORE_PATH="/packages/system/CMSIS/CMSIS-Core" +CONFIG_PKG_USING_CMSIS_CORE_LATEST_VERSION=y +CONFIG_PKG_CMSIS_CORE_VER="latest" # CONFIG_PKG_USING_CMSIS_DSP is not set # CONFIG_PKG_USING_CMSIS_NN is not set # CONFIG_PKG_USING_CMSIS_RTOS1 is not set # CONFIG_PKG_USING_CMSIS_RTOS2 is not set +# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard # # Micrium: Micrium software products porting for RT-Thread @@ -521,6 +569,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_UC_CLK is not set # CONFIG_PKG_USING_UC_COMMON is not set # CONFIG_PKG_USING_UC_MODBUS is not set +# end of Micrium: Micrium software products porting for RT-Thread + # CONFIG_PKG_USING_FREERTOS_WRAPPER is not set # CONFIG_PKG_USING_LITEOS_SDK is not set # CONFIG_PKG_USING_TZ_DATABASE is not set @@ -568,6 +618,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RTP is not set # CONFIG_PKG_USING_REB is not set # CONFIG_PKG_USING_R_RHEALSTONE is not set +# end of system packages # # peripheral libraries and drivers @@ -580,9 +631,35 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # STM32 HAL & SDK Drivers # -# CONFIG_PKG_USING_STM32L4XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set +CONFIG_PKG_USING_STM32L4_HAL_DRIVER=y +CONFIG_PKG_STM32L4_HAL_DRIVER_PATH="/packages/peripherals/hal-sdk/stm32/stm32l4_hal_driver" +CONFIG_PKG_USING_STM32L4_HAL_DRIVER_LATEST_VERSION=y +CONFIG_PKG_STM32L4_HAL_DRIVER_VER="latest" +CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER=y +CONFIG_PKG_STM32L4_CMSIS_DRIVER_PATH="/packages/peripherals/hal-sdk/stm32/stm32l4_cmsis_driver" +CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER_LATEST_VERSION=y +CONFIG_PKG_STM32L4_CMSIS_DRIVER_VER="latest" # CONFIG_PKG_USING_STM32WB55_SDK is not set # CONFIG_PKG_USING_STM32_SDIO is not set +# end of STM32 HAL & SDK Drivers + +# +# Infineon HAL Packages +# +# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set +# CONFIG_PKG_USING_INFINEON_CMSIS is not set +# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set +# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set +# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set +# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set +# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set +# CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + # CONFIG_PKG_USING_BLUETRUM_SDK is not set # CONFIG_PKG_USING_EMBARC_BSP is not set # CONFIG_PKG_USING_ESP_IDF is not set @@ -592,9 +669,12 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # CONFIG_PKG_USING_K210_SDK is not set # CONFIG_PKG_USING_KENDRYTE_SDK is not set +# end of Kendryte SDK + # CONFIG_PKG_USING_NRF5X_SDK is not set # CONFIG_PKG_USING_NRFX is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# end of HAL & SDK Drivers # # sensors drivers @@ -664,6 +744,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ICM20608 is not set # CONFIG_PKG_USING_PAJ7620 is not set # CONFIG_PKG_USING_STHS34PF80 is not set +# end of sensors drivers # # touch drivers @@ -678,6 +759,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_XPT2046_TOUCH is not set # CONFIG_PKG_USING_CST816X is not set # CONFIG_PKG_USING_CST812T is not set +# end of touch drivers + # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_BUTTON is not set # CONFIG_PKG_USING_PCF8574 is not set @@ -750,6 +833,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_BT_MX01 is not set # CONFIG_PKG_USING_RGPOWER is not set # CONFIG_PKG_USING_SPI_TOOLS is not set +# end of peripheral libraries and drivers # # AI packages @@ -764,15 +848,18 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_QUEST is not set # CONFIG_PKG_USING_NAXOS is not set # CONFIG_PKG_USING_R_TINYMAIX is not set +# end of AI packages # # Signal Processing and Control Algorithm Packages # +# CONFIG_PKG_USING_APID is not set # CONFIG_PKG_USING_FIRE_PID_CURVE is not set # CONFIG_PKG_USING_QPID is not set # CONFIG_PKG_USING_UKAL is not set # CONFIG_PKG_USING_DIGITALCTRL is not set # CONFIG_PKG_USING_KISSFFT is not set +# end of Signal Processing and Control Algorithm Packages # # miscellaneous packages @@ -781,6 +868,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # project laboratory # +# end of project laboratory # # samples: kernel and components samples @@ -789,6 +877,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set # CONFIG_PKG_USING_NETWORK_SAMPLES is not set # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# end of samples: kernel and components samples # # entertainment: terminal games and other interesting software packages @@ -805,6 +894,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_COWSAY is not set # CONFIG_PKG_USING_MORSE is not set # CONFIG_PKG_USING_TINYSQUARE is not set +# end of entertainment: terminal games and other interesting software packages + # CONFIG_PKG_USING_LIBCSV is not set # CONFIG_PKG_USING_OPTPARSE is not set # CONFIG_PKG_USING_FASTLZ is not set @@ -839,6 +930,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_QPARAM is not set # CONFIG_PKG_USING_CorevMCU_CLI is not set # CONFIG_PKG_USING_GET_IRQ_PRIORITY is not set +# end of miscellaneous packages # # Arduino libraries @@ -854,6 +946,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set # CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set # CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set +# end of Projects and Demos # # Sensors @@ -993,6 +1086,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set # CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set # CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set +# end of Sensors # # Display @@ -1004,6 +1099,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set # CONFIG_PKG_USING_SEEED_TM1637 is not set +# end of Display # # Timing @@ -1012,6 +1108,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set # CONFIG_PKG_USING_ARDUINO_TICKER is not set # CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set +# end of Timing # # Data Processing @@ -1019,6 +1116,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set # CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set # CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set +# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set +# end of Data Processing # # Data Storage @@ -1029,6 +1128,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set +# end of Communication # # Device Control @@ -1040,12 +1140,14 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set # CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# end of Device Control # # Other # # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# end of Other # # Signal IO @@ -1058,10 +1160,14 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set +# end of Signal IO # # Uncategorized # +# end of Arduino libraries +# end of RT-Thread online packages + CONFIG_SOC_FAMILY_STM32=y CONFIG_SOC_SERIES_STM32L4=y CONFIG_BOARD_SERIES_STM32_NUCLEO_64=y @@ -1075,6 +1181,7 @@ CONFIG_BOARD_SERIES_STM32_NUCLEO_64=y # CONFIG_BSP_USING_STLINK_TO_USART=y # CONFIG_BSP_USING_ARDUINO is not set +# end of Onboard Peripheral Drivers # # On-chip Peripheral Drivers @@ -1092,7 +1199,9 @@ CONFIG_BSP_USING_UART2=y # CONFIG_BSP_USING_CRC is not set # CONFIG_BSP_USING_RNG is not set # CONFIG_BSP_USING_UDID is not set +# end of On-chip Peripheral Drivers # # Board extended module Drivers # +# end of Hardware Drivers Config diff --git a/bsp/stm32/stm32l476-st-nucleo/rtconfig.h b/bsp/stm32/stm32l476-st-nucleo/rtconfig.h index 8e11f3f4e5..557a686dd5 100644 --- a/bsp/stm32/stm32l476-st-nucleo/rtconfig.h +++ b/bsp/stm32/stm32l476-st-nucleo/rtconfig.h @@ -1,9 +1,6 @@ #ifndef RT_CONFIG_H__ #define RT_CONFIG_H__ -/* Automatically generated file; DO NOT EDIT. */ -/* RT-Thread Configuration */ - #define SOC_STM32L476RG #define BOARD_STM32L476_NUCLEO @@ -15,7 +12,6 @@ #define RT_THREAD_PRIORITY_32 #define RT_THREAD_PRIORITY_MAX 32 #define RT_TICK_PER_SECOND 1000 -#define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK @@ -24,9 +20,16 @@ /* kservice optimization */ +/* end of kservice optimization */ + +/* klibc optimization */ + +/* end of klibc optimization */ #define RT_USING_DEBUG +#define RT_DEBUGING_ASSERT #define RT_DEBUGING_COLOR #define RT_DEBUGING_CONTEXT +#define RT_USING_OVERFLOW_CHECK /* Inter-Thread communication */ @@ -35,6 +38,7 @@ #define RT_USING_EVENT #define RT_USING_MAILBOX #define RT_USING_MESSAGEQUEUE +/* end of Inter-Thread communication */ /* Memory Management */ @@ -42,12 +46,14 @@ #define RT_USING_SMALL_MEM #define RT_USING_SMALL_MEM_AS_HEAP #define RT_USING_HEAP +/* end of Memory Management */ #define RT_USING_DEVICE #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 256 #define RT_CONSOLE_DEVICE_NAME "uart2" -#define RT_VER_NUM 0x50100 +#define RT_VER_NUM 0x50200 #define RT_BACKTRACE_LEVEL_MAX_NR 32 +/* end of RT-Thread Kernel */ #define RT_USING_HW_ATOMIC #define RT_USING_CPU_FFS #define ARCH_ARM @@ -77,6 +83,7 @@ /* DFS: device virtual file system */ +/* end of DFS: device virtual file system */ /* Device Drivers */ @@ -86,13 +93,8 @@ #define RT_USING_SERIAL_V1 #define RT_SERIAL_USING_DMA #define RT_SERIAL_RB_BUFSZ 64 -#define RT_USING_PM -#define PM_TICKLESS_THRESHOLD_TIME 2 -#define RT_USING_RTC #define RT_USING_PIN - -/* Using USB */ - +/* end of Device Drivers */ /* C/C++ and POSIX layer */ @@ -104,6 +106,8 @@ #define RT_LIBC_TZ_DEFAULT_HOUR 8 #define RT_LIBC_TZ_DEFAULT_MIN 0 #define RT_LIBC_TZ_DEFAULT_SEC 0 +/* end of Timezone and Daylight Saving Time */ +/* end of ISO-ANSI C layer */ /* POSIX (Portable Operating System Interface) layer */ @@ -113,18 +117,30 @@ /* Socket is in the 'Network' category */ +/* end of Interprocess Communication (IPC) */ +/* end of POSIX (Portable Operating System Interface) layer */ +/* end of C/C++ and POSIX layer */ /* Network */ +/* end of Network */ /* Memory protection */ +/* end of Memory protection */ /* Utilities */ +/* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ +/* end of RT-Thread Components */ /* RT-Thread Utestcases */ +/* end of RT-Thread Utestcases */ /* RT-Thread online packages */ @@ -135,57 +151,80 @@ /* Marvell WiFi */ +/* end of Marvell WiFi */ /* Wiced WiFi */ +/* end of Wiced WiFi */ /* CYW43012 WiFi */ +/* end of CYW43012 WiFi */ /* BL808 WiFi */ +/* end of BL808 WiFi */ /* CYW43439 WiFi */ +/* end of CYW43439 WiFi */ +/* end of Wi-Fi */ /* IoT Cloud */ +/* end of IoT Cloud */ +/* end of IoT - internet of things */ /* security packages */ +/* end of security packages */ /* language packages */ /* JSON: JavaScript Object Notation, a lightweight data-interchange format */ +/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */ /* XML: Extensible Markup Language */ +/* end of XML: Extensible Markup Language */ +/* end of language packages */ /* multimedia packages */ /* LVGL: powerful and easy-to-use embedded GUI library */ +/* end of LVGL: powerful and easy-to-use embedded GUI library */ /* u8g2: a monochrome graphic library */ +/* end of u8g2: a monochrome graphic library */ +/* end of multimedia packages */ /* tools packages */ +/* end of tools packages */ /* system packages */ /* enhanced kernel services */ +/* end of enhanced kernel services */ /* acceleration: Assembly language or algorithmic acceleration packages */ +/* end of acceleration: Assembly language or algorithmic acceleration packages */ /* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ +#define PKG_USING_CMSIS_CORE +#define PKG_USING_CMSIS_CORE_LATEST_VERSION +/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ /* Micrium: Micrium software products porting for RT-Thread */ +/* end of Micrium: Micrium software products porting for RT-Thread */ +/* end of system packages */ /* peripheral libraries and drivers */ @@ -193,66 +232,98 @@ /* STM32 HAL & SDK Drivers */ +#define PKG_USING_STM32L4_HAL_DRIVER +#define PKG_USING_STM32L4_HAL_DRIVER_LATEST_VERSION +#define PKG_USING_STM32L4_CMSIS_DRIVER +#define PKG_USING_STM32L4_CMSIS_DRIVER_LATEST_VERSION +/* end of STM32 HAL & SDK Drivers */ + +/* Infineon HAL Packages */ + +/* end of Infineon HAL Packages */ /* Kendryte SDK */ +/* end of Kendryte SDK */ +/* end of HAL & SDK Drivers */ /* sensors drivers */ +/* end of sensors drivers */ /* touch drivers */ +/* end of touch drivers */ +/* end of peripheral libraries and drivers */ /* AI packages */ +/* end of AI packages */ /* Signal Processing and Control Algorithm Packages */ +/* end of Signal Processing and Control Algorithm Packages */ /* miscellaneous packages */ /* project laboratory */ +/* end of project laboratory */ + /* samples: kernel and components samples */ +/* end of samples: kernel and components samples */ /* entertainment: terminal games and other interesting software packages */ +/* end of entertainment: terminal games and other interesting software packages */ +/* end of miscellaneous packages */ /* Arduino libraries */ /* Projects and Demos */ +/* end of Projects and Demos */ /* Sensors */ +/* end of Sensors */ /* Display */ +/* end of Display */ /* Timing */ +/* end of Timing */ /* Data Processing */ +/* end of Data Processing */ /* Data Storage */ /* Communication */ +/* end of Communication */ /* Device Control */ +/* end of Device Control */ /* Other */ +/* end of Other */ /* Signal IO */ +/* end of Signal IO */ /* Uncategorized */ +/* end of Arduino libraries */ +/* end of RT-Thread online packages */ #define SOC_FAMILY_STM32 #define SOC_SERIES_STM32L4 #define BOARD_SERIES_STM32_NUCLEO_64 @@ -262,14 +333,17 @@ /* Onboard Peripheral Drivers */ #define BSP_USING_STLINK_TO_USART +/* end of Onboard Peripheral Drivers */ /* On-chip Peripheral Drivers */ #define BSP_USING_GPIO #define BSP_USING_UART #define BSP_USING_UART2 +/* end of On-chip Peripheral Drivers */ /* Board extended module Drivers */ +/* end of Hardware Drivers Config */ #endif From 6b3ef178304bbde511d84e7ab377d65e4af98e9b Mon Sep 17 00:00:00 2001 From: Rbb666 Date: Fri, 12 Jul 2024 15:14:52 +0800 Subject: [PATCH 30/48] =?UTF-8?q?=E5=88=A0=E9=99=A4stm32/drv=5Fpm.c?= =?UTF-8?q?=E4=B8=8D=E5=BF=85=E8=A6=81=E7=9A=84=E5=A4=B4=E6=96=87=E4=BB=B6?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- bsp/stm32/libraries/HAL_Drivers/drivers/drv_pm.c | 1 - 1 file changed, 1 deletion(-) diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_pm.c b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_pm.c index 3a5794dab2..2b93c30f94 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_pm.c +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_pm.c @@ -12,7 +12,6 @@ #include #include #include -#include /*#define DRV_DEBUG*/ #define LOG_TAG "drv.pm" From 30b605aa55d9572762ee4c208ccfd2248dee6317 Mon Sep 17 00:00:00 2001 From: Supper Thomas <78900636@qq.com> Date: Fri, 19 Jul 2024 13:09:00 +0800 Subject: [PATCH 31/48] [action][runner] add the keil ci check for runner Signed-off-by: Supper Thomas <78900636@qq.com> --- .github/workflows/action_runner.yml | 56 +++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 .github/workflows/action_runner.yml diff --git a/.github/workflows/action_runner.yml b/.github/workflows/action_runner.yml new file mode 100644 index 0000000000..599873eda8 --- /dev/null +++ b/.github/workflows/action_runner.yml @@ -0,0 +1,56 @@ +# +# Copyright (c) 2006-2024, RT-Thread Development Team +# +# SPDX-License-Identifier: Apache-2.0 +# +# Change Logs: +# Date Author Notes +# 2024-07-19 supperthomas the first version +# +name: action_runner + +on: + workflow_dispatch: + inputs: + bsp_options: + description: 'Which bsp path Would you want dist in bsp?like stm32/stm32f103-blue-pill' + required: false + type: string + default: 'stm32/stm32f103-blue-pill' + bsp_tool_chain: + description: 'Choice tool_chain' + required: false + default: 'KEIL' + type: choice + options: + - "KEIL" + - "IAR" + bsp_config: + description: 'Type a config you want mannual test in .config, like: CONFIG_RT_USING_DEBUG=y,CONFIG_RT_DEBUGING_COLOR=y,CONFIG_RT_DEBUGING_CONTEXT=y' + required: false + type: string + default: 'CONFIG_RT_USING_DEBUG=y,CONFIG_RT_DEBUGING_COLOR=y,CONFIG_RT_DEBUGING_CONTEXT=y' + +permissions: + contents: read + +jobs: + build: + runs-on: [self-hosted, windows, x64] + name: ${{ github.event.inputs.bsp_options }} + steps: + - uses: actions/checkout@v3 + - name: Bsp Scons Compile + if: ${{ success() }} + env: + RTT_BSP: ${{ github.event.inputs.bsp_options }} + RTT_TOOL_CHAIN: ${{ github.event.inputs.bsp_tool_chain}} + run: | + ls + echo $RTT_BSP + cd bsp/stm32/stm32f103-blue-pill + scons --target=mdk5 + UV4.exe -b project.uvprojx -q -j0 -t rt-thread -o action_runner.log + ls + sleep 10 + cat action_runner.log \ No newline at end of file From 2a3bb2bf951a9296dbb9064cdf31a0d425e9457f Mon Sep 17 00:00:00 2001 From: Z8MAN8 <1468559561@qq.com> Date: Fri, 19 Jul 2024 10:36:42 +0800 Subject: [PATCH 32/48] =?UTF-8?q?[bsp][cvitek]:=20=E5=B0=86adc=20wdt?= =?UTF-8?q?=E9=A9=B1=E5=8A=A8=E7=9A=84=E5=B1=80=E9=83=A8=E5=87=BD=E6=95=B0?= =?UTF-8?q?=E7=A7=BB=E8=87=B3=E6=BA=90=E6=96=87=E4=BB=B6?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- bsp/cvitek/drivers/drv_adc.c | 43 ++++++++++++++++++++++ bsp/cvitek/drivers/drv_adc.h | 43 ---------------------- bsp/cvitek/drivers/drv_wdt.c | 69 +++++++++++++++++++++++++++++++++++ bsp/cvitek/drivers/drv_wdt.h | 70 ------------------------------------ 4 files changed, 112 insertions(+), 113 deletions(-) diff --git a/bsp/cvitek/drivers/drv_adc.c b/bsp/cvitek/drivers/drv_adc.c index e3ca317b58..86cde2aabb 100644 --- a/bsp/cvitek/drivers/drv_adc.c +++ b/bsp/cvitek/drivers/drv_adc.c @@ -16,6 +16,49 @@ #include #define LOG_TAG "DRV.ADC" +rt_inline void cvi_set_saradc_ctrl(unsigned long reg_base, rt_uint32_t value) +{ + value |= mmio_read_32(reg_base + SARADC_CTRL_OFFSET); + mmio_write_32(reg_base + SARADC_CTRL_OFFSET, value); +} + +rt_inline void cvi_reset_saradc_ctrl(unsigned long reg_base, rt_uint32_t value) +{ + value = mmio_read_32(reg_base + SARADC_CTRL_OFFSET) & ~value; + mmio_write_32(reg_base + SARADC_CTRL_OFFSET, value); +} + +rt_inline rt_uint32_t cvi_get_saradc_status(unsigned long reg_base) +{ + return((rt_uint32_t)mmio_read_32(reg_base + SARADC_STATUS_OFFSET)); +} + +rt_inline void cvi_set_cyc(unsigned long reg_base) +{ + rt_uint32_t value; + + value = mmio_read_32(reg_base + SARADC_CYC_SET_OFFSET); + + value &= ~SARADC_CYC_CLKDIV_DIV_16; + mmio_write_32(reg_base + SARADC_CYC_SET_OFFSET, value); + + value |= SARADC_CYC_CLKDIV_DIV_16; //set saradc clock cycle=840ns + mmio_write_32(reg_base + SARADC_CYC_SET_OFFSET, value); +} + +rt_inline void cvi_do_calibration(unsigned long reg_base) +{ + rt_uint32_t val; + + val = mmio_read_32(reg_base + SARADC_TEST_OFFSET); + val |= 1 << SARADC_TEST_VREFSEL_BIT; + mmio_write_32(reg_base + SARADC_TEST_OFFSET, val); + + val = mmio_read_32(reg_base + SARADC_TRIM_OFFSET); + val |= 0x4; + mmio_write_32(reg_base + SARADC_TRIM_OFFSET, val); +} + struct cvi_adc_dev { struct rt_adc_device device; diff --git a/bsp/cvitek/drivers/drv_adc.h b/bsp/cvitek/drivers/drv_adc.h index 3ef86a2ecb..8cbec51b48 100644 --- a/bsp/cvitek/drivers/drv_adc.h +++ b/bsp/cvitek/drivers/drv_adc.h @@ -53,49 +53,6 @@ #define SARADC_TRIM_OFFSET 0x034 -rt_inline void cvi_set_saradc_ctrl(unsigned long reg_base, rt_uint32_t value) -{ - value |= mmio_read_32(reg_base + SARADC_CTRL_OFFSET); - mmio_write_32(reg_base + SARADC_CTRL_OFFSET, value); -} - -rt_inline void cvi_reset_saradc_ctrl(unsigned long reg_base, rt_uint32_t value) -{ - value = mmio_read_32(reg_base + SARADC_CTRL_OFFSET) & ~value; - mmio_write_32(reg_base + SARADC_CTRL_OFFSET, value); -} - -rt_inline rt_uint32_t cvi_get_saradc_status(unsigned long reg_base) -{ - return((rt_uint32_t)mmio_read_32(reg_base + SARADC_STATUS_OFFSET)); -} - -rt_inline void cvi_set_cyc(unsigned long reg_base) -{ - rt_uint32_t value; - - value = mmio_read_32(reg_base + SARADC_CYC_SET_OFFSET); - - value &= ~SARADC_CYC_CLKDIV_DIV_16; - mmio_write_32(reg_base + SARADC_CYC_SET_OFFSET, value); - - value |= SARADC_CYC_CLKDIV_DIV_16; //set saradc clock cycle=840ns - mmio_write_32(reg_base + SARADC_CYC_SET_OFFSET, value); -} - -rt_inline void cvi_do_calibration(unsigned long reg_base) -{ - rt_uint32_t val; - - val = mmio_read_32(reg_base + SARADC_TEST_OFFSET); - val |= 1 << SARADC_TEST_VREFSEL_BIT; - mmio_write_32(reg_base + SARADC_TEST_OFFSET, val); - - val = mmio_read_32(reg_base + SARADC_TRIM_OFFSET); - val |= 0x4; - mmio_write_32(reg_base + SARADC_TRIM_OFFSET, val); -} - int rt_hw_adc_init(void); #endif /* __DRV_ADC_H__ */ diff --git a/bsp/cvitek/drivers/drv_wdt.c b/bsp/cvitek/drivers/drv_wdt.c index 1fb1ad8430..80d5203440 100644 --- a/bsp/cvitek/drivers/drv_wdt.c +++ b/bsp/cvitek/drivers/drv_wdt.c @@ -18,6 +18,75 @@ #define WDT_FREQ_DEFAULT 25000000UL #define CVI_WDT_MAX_TOP 15 +rt_inline void cvi_wdt_top_setting() +{ + uint32_t val; + + mmio_write_32(CV_TOP + CV_TOP_WDT_OFFSET, CV_TOP_WDT_VAL); + + val = mmio_read_32(CV_RST_REG); + mmio_write_32(CV_RST_REG, val & ~CV_RST_WDT); + rt_hw_us_delay(10); + mmio_write_32(CV_RST_REG, val | CV_RST_WDT); +} + +rt_inline void cvi_wdt_start_en(unsigned long reg_base) +{ + WDT_CR(reg_base) |= CVI_WDT_CR_WDT_ENABLE_En; +} + +rt_inline void cvi_wdt_start_dis(unsigned long reg_base) +{ + WDT_CR(reg_base) &= ~CVI_WDT_CR_WDT_ENABLE_En; +} + +rt_inline uint32_t cvi_wdt_get_start(unsigned long reg_base) +{ + return (WDT_CR(reg_base) & CVI_WDT_CR_WDT_ENABLE_Msk); +} + +rt_inline void cvi_wdt_set_timeout(unsigned long reg_base, uint32_t value) +{ + WDT_TORR(reg_base) &= ~CVI_WDT_TORR_WDT_TORR_Pos; + WDT_TORR(reg_base) = ((value << CVI_WDT_TORR_WDT_ITORR_Pos) | (value << CVI_WDT_TORR_WDT_TORR_Pos)); +} + +rt_inline void cvi_wdt_set_respond_system_reset(unsigned long reg_base) +{ + WDT_CR(reg_base) &= ~CVI_WDT_CR_WDT_RESPOND_IRQ_THEN_RST; +} + +rt_inline void cvi_wdt_set_respond_irq_then_reset(unsigned long reg_base) +{ + WDT_CR(reg_base) |= CVI_WDT_CR_WDT_RESPOND_IRQ_THEN_RST; +} + +rt_inline void cvi_wdt_set_reset_pulse_width(unsigned long reg_base, uint32_t value) +{ + WDT_CR(reg_base) &= ~CVI_WDT_CR_WDT_RESET_PULSE_WIDTH_Msk; + WDT_CR(reg_base) |= (value << CVI_WDT_CR_WDT_RESET_PULSE_WIDTH_Pos); +} + +rt_inline void cvi_wdt_feed_en(unsigned long reg_base) +{ + WDT_CRR(reg_base) = CVI_WDT_CRR_FEED_En; +} + +rt_inline uint32_t cvi_wdt_get_counter_value(unsigned long reg_base) +{ + return (WDT_CCVR(reg_base) & CVI_WDT_CCVR_COUNTER_Msk); +} + +rt_inline uint32_t cvi_wdt_get_irq_stat(unsigned long reg_base) +{ + return (WDT_STAT(reg_base) & CVI_WDT_STAT_IRQ_STAT_Msk); +} + +rt_inline void cvi_wdt_clr_irq_en(unsigned long reg_base) +{ + WDT_EOI(reg_base); +} + struct _cvi_wdt_dev { struct rt_watchdog_device device; diff --git a/bsp/cvitek/drivers/drv_wdt.h b/bsp/cvitek/drivers/drv_wdt.h index 7fbab6f951..65073dec1d 100644 --- a/bsp/cvitek/drivers/drv_wdt.h +++ b/bsp/cvitek/drivers/drv_wdt.h @@ -89,76 +89,6 @@ static struct cvi_wdt_regs_t *cvi_wdt_reg = &cv182x_wdt_reg; #define CV_RST_REG (CV_TOP + 0x3004) #define CV_RST_WDT (1U << 16) -rt_inline void cvi_wdt_top_setting() -{ - uint32_t val; - - mmio_write_32(CV_TOP + CV_TOP_WDT_OFFSET, CV_TOP_WDT_VAL); - - val = mmio_read_32(CV_RST_REG); - mmio_write_32(CV_RST_REG, val & ~CV_RST_WDT); - rt_hw_us_delay(10); - mmio_write_32(CV_RST_REG, val | CV_RST_WDT); -} - -rt_inline void cvi_wdt_start_en(unsigned long reg_base) -{ - WDT_CR(reg_base) |= CVI_WDT_CR_WDT_ENABLE_En; -} - -rt_inline void cvi_wdt_start_dis(unsigned long reg_base) -{ - WDT_CR(reg_base) &= ~CVI_WDT_CR_WDT_ENABLE_En; -} - -rt_inline uint32_t cvi_wdt_get_start(unsigned long reg_base) -{ - return (WDT_CR(reg_base) & CVI_WDT_CR_WDT_ENABLE_Msk); -} - -rt_inline void cvi_wdt_set_timeout(unsigned long reg_base, uint32_t value) -{ - WDT_TORR(reg_base) &= ~CVI_WDT_TORR_WDT_TORR_Pos; - WDT_TORR(reg_base) = ((value << CVI_WDT_TORR_WDT_ITORR_Pos) | (value << CVI_WDT_TORR_WDT_TORR_Pos)); -} - -rt_inline void cvi_wdt_set_respond_system_reset(unsigned long reg_base) -{ - WDT_CR(reg_base) &= ~CVI_WDT_CR_WDT_RESPOND_IRQ_THEN_RST; -} - -rt_inline void cvi_wdt_set_respond_irq_then_reset(unsigned long reg_base) -{ - WDT_CR(reg_base) |= CVI_WDT_CR_WDT_RESPOND_IRQ_THEN_RST; -} - -rt_inline void cvi_wdt_set_reset_pulse_width(unsigned long reg_base, uint32_t value) -{ - WDT_CR(reg_base) &= ~CVI_WDT_CR_WDT_RESET_PULSE_WIDTH_Msk; - WDT_CR(reg_base) |= (value << CVI_WDT_CR_WDT_RESET_PULSE_WIDTH_Pos); -} - -rt_inline void cvi_wdt_feed_en(unsigned long reg_base) -{ - WDT_CRR(reg_base) = CVI_WDT_CRR_FEED_En; -} - -rt_inline uint32_t cvi_wdt_get_counter_value(unsigned long reg_base) -{ - return (WDT_CCVR(reg_base) & CVI_WDT_CCVR_COUNTER_Msk); -} - -rt_inline uint32_t cvi_wdt_get_irq_stat(unsigned long reg_base) -{ - return (WDT_STAT(reg_base) & CVI_WDT_STAT_IRQ_STAT_Msk); -} - -rt_inline void cvi_wdt_clr_irq_en(unsigned long reg_base) -{ - WDT_EOI(reg_base); -} - - int rt_hw_wdt_init(void); #endif /* __DRV_WDT_H__ */ From 78f3ebfb33c01c30cf0b98844d8a029ba3720c2f Mon Sep 17 00:00:00 2001 From: Z8MAN8 <1468559561@qq.com> Date: Sat, 20 Jul 2024 17:28:27 +0800 Subject: [PATCH 33/48] =?UTF-8?q?[bsp][cvitek]=20=E4=BF=AE=E5=A4=8D=20cv18?= =?UTF-8?q?xx=5Faarch64=20gpio=20=E9=A9=B1=E5=8A=A8=E7=9B=B8=E5=85=B3?= =?UTF-8?q?=E5=AE=8F=E9=85=8D=E7=BD=AE?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- bsp/cvitek/cv18xx_aarch64/Kconfig | 8 ++++++++ bsp/cvitek/cv18xx_aarch64/rtconfig.h | 2 ++ 2 files changed, 10 insertions(+) diff --git a/bsp/cvitek/cv18xx_aarch64/Kconfig b/bsp/cvitek/cv18xx_aarch64/Kconfig index 0c7c9a1422..4f7a160a25 100644 --- a/bsp/cvitek/cv18xx_aarch64/Kconfig +++ b/bsp/cvitek/cv18xx_aarch64/Kconfig @@ -22,6 +22,14 @@ config SOC_CV18XX_AARCH64 select ARCH_MM_MMU default y +config GPIO_IRQ_BASE + int + default 76 + +config SYS_GPIO_IRQ_BASE + int + default 86 + choice prompt "Board Type" default BOARD_TYPE_MILKV_DUO256M diff --git a/bsp/cvitek/cv18xx_aarch64/rtconfig.h b/bsp/cvitek/cv18xx_aarch64/rtconfig.h index a4b7c61003..a418f2da0c 100644 --- a/bsp/cvitek/cv18xx_aarch64/rtconfig.h +++ b/bsp/cvitek/cv18xx_aarch64/rtconfig.h @@ -329,6 +329,8 @@ /* Uncategorized */ #define SOC_CV18XX_AARCH64 +#define GPIO_IRQ_BASE 76 +#define SYS_GPIO_IRQ_BASE 86 #define BOARD_TYPE_MILKV_DUO256M /* General Drivers Configuration */ From 79d14461bdf8057220bd2187352dd9e4d9695b29 Mon Sep 17 00:00:00 2001 From: Rbb666 Date: Sun, 21 Jul 2024 17:52:20 +0800 Subject: [PATCH 34/48] [ci] add bsp/stm32+renesas examples files' review owner --- .github/CODEOWNERS | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/.github/CODEOWNERS b/.github/CODEOWNERS index 8d746a759c..e0a14036ea 100644 --- a/.github/CODEOWNERS +++ b/.github/CODEOWNERS @@ -7,9 +7,8 @@ /.hooks @supperthomas /.devcontainer @supperthomas /bsp/ESP32_C3 @supperthomas -/bsp/nr5x/ @supperthomas /bsp/stm32/stm32l496-st-nucleo @supperthomas -/bsp/stm32/stm32f407-rt-spark @supperthomas +/bsp/stm32/stm32f407-rt-spark @Rbb666 /bsp/stm32/stm32h743-openmv-h7plus @supperthomas /bsp/stm32/stm32l4r9-st-sensortile-box/ @supperthomas /bsp/stm32/stm32l475-atk-pandora/ @mysterywolf @@ -17,7 +16,10 @@ /bsp/stm32/stm32f411-st-nucleo/ @mysterywolf /bsp/stm32/stm32f412-st-nucleo/ @mysterywolf /bsp/stm32/stm32l476-st-nucleo/ @mysterywolf +/bsp/stm32/stm32h750-artpi/ @Rbb666 /bsp/maxim @supperthomas +/bsp/nxp @Rbb666 +/bsp/renesas @Rbb666 *arduino* @mysterywolf *.attach @mysterywolf @@ -30,5 +32,5 @@ /components/drivers/tty/ @BernardXiong /documentation @mysterywolf @Cathy-lulu -/examples @Guozhanxin +/examples @Rbb666 From 0e3c4bd26b34a54910db4da6b0a99bc470c65b08 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=BC=A0=E8=A1=8D?= Date: Mon, 22 Jul 2024 02:33:39 +0000 Subject: [PATCH 35/48] =?UTF-8?q?[BSP/Phytium]=E9=80=82=E9=85=8D=E6=9C=80?= =?UTF-8?q?=E6=96=B0=E8=A3=B8=E6=9C=BA=E9=A9=B1=E5=8A=A8?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- bsp/phytium/aarch32/.config | 64 +++++------ bsp/phytium/aarch32/Kconfig | 2 - bsp/phytium/aarch32/applications/main.c | 4 +- .../aarch32/configs/e2000d_demo_rtsmart | 43 ++++--- .../aarch32/configs/e2000d_demo_rtsmart.h | 22 ++-- .../aarch32/configs/e2000d_demo_rtthread | 37 +++--- .../aarch32/configs/e2000d_demo_rtthread.h | 18 ++- .../aarch32/configs/e2000q_demo_rtsmart | 45 ++++---- .../aarch32/configs/e2000q_demo_rtsmart.h | 23 ++-- .../aarch32/configs/e2000q_demo_rtthread | 43 ++++--- .../aarch32/configs/e2000q_demo_rtthread.h | 21 ++-- .../aarch32/configs/phytium_pi_rtsmart | 41 ++++--- .../aarch32/configs/phytium_pi_rtsmart.h | 21 ++-- .../aarch32/configs/phytium_pi_rtthread | 41 ++++--- .../aarch32/configs/phytium_pi_rtthread.h | 20 ++-- bsp/phytium/aarch32/makefile | 4 +- bsp/phytium/aarch32/rtconfig.h | 31 +++-- bsp/phytium/aarch64/.config | 66 +++++------ bsp/phytium/aarch64/Kconfig | 2 - bsp/phytium/aarch64/applications/main.c | 4 +- .../aarch64/configs/e2000d_demo_rtsmart | 43 +++---- .../aarch64/configs/e2000d_demo_rtsmart.h | 23 ++-- .../aarch64/configs/e2000d_demo_rtthread | 43 +++---- .../aarch64/configs/e2000d_demo_rtthread.h | 22 ++-- .../aarch64/configs/e2000q_demo_rtsmart | 43 +++---- .../aarch64/configs/e2000q_demo_rtsmart.h | 23 ++-- .../aarch64/configs/e2000q_demo_rtthread | 43 +++---- .../aarch64/configs/e2000q_demo_rtthread.h | 22 ++-- .../aarch64/configs/phytium_pi_rtsmart | 49 ++++---- .../aarch64/configs/phytium_pi_rtsmart.h | 26 ++--- .../aarch64/configs/phytium_pi_rtthread | 45 ++++---- .../aarch64/configs/phytium_pi_rtthread.h | 23 ++-- bsp/phytium/aarch64/makefile | 4 +- bsp/phytium/aarch64/rtconfig.h | 34 +++--- bsp/phytium/board/board.c | 43 +------ bsp/phytium/board/phytium_cpu.c | 4 +- bsp/phytium/board/phytium_cpu.h | 47 +++++++- bsp/phytium/board/phytium_cpu_id.S | 55 ++------- bsp/phytium/board/secondary_cpu.c | 28 ++--- bsp/phytium/board/smp_sgi_test.c | 106 ++++++++++++++++++ .../libraries/common/phytium_interrupt.c | 32 +----- bsp/phytium/libraries/drivers/drv_can.c | 12 +- bsp/phytium/libraries/drivers/drv_dc.c | 2 + bsp/phytium/libraries/drivers/drv_gpio.c | 22 ++-- bsp/phytium/libraries/drivers/drv_i2c.c | 3 +- bsp/phytium/libraries/drivers/drv_pwm.c | 15 +-- bsp/phytium/libraries/drivers/drv_qspi.c | 18 +-- bsp/phytium/libraries/drivers/drv_sdif.c | 4 +- .../phytium_standalone_sdk_install.py | 2 +- components/utilities/ymodem/ry_sy.c | 3 +- libcpu/aarch64/common/cpuport.c | 43 +++++++ libcpu/aarch64/common/include/cpuport.h | 30 ----- 52 files changed, 718 insertions(+), 746 deletions(-) create mode 100644 bsp/phytium/board/smp_sgi_test.c create mode 100644 libcpu/aarch64/common/cpuport.c diff --git a/bsp/phytium/aarch32/.config b/bsp/phytium/aarch32/.config index 34f0e9088f..4e7fc75c3f 100644 --- a/bsp/phytium/aarch32/.config +++ b/bsp/phytium/aarch32/.config @@ -8,14 +8,13 @@ CONFIG_RT_NAME_MAX=16 # CONFIG_RT_USING_NANO is not set # CONFIG_RT_USING_AMP is not set CONFIG_RT_USING_SMP=y -CONFIG_RT_CPUS_NR=2 +CONFIG_RT_CPUS_NR=4 CONFIG_RT_ALIGN_SIZE=4 # CONFIG_RT_THREAD_PRIORITY_8 is not set CONFIG_RT_THREAD_PRIORITY_32=y # CONFIG_RT_THREAD_PRIORITY_256 is not set CONFIG_RT_THREAD_PRIORITY_MAX=32 CONFIG_RT_TICK_PER_SECOND=1000 -CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y CONFIG_RT_HOOK_USING_FUNC_PTR=y # CONFIG_RT_USING_HOOKLIST is not set @@ -26,6 +25,8 @@ CONFIG_SYSTEM_THREAD_STACK_SIZE=4096 CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 CONFIG_RT_TIMER_THREAD_STACK_SIZE=4096 +# CONFIG_RT_USING_TIMER_ALL_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set # # kservice optimization @@ -49,6 +50,7 @@ CONFIG_RT_DEBUGING_CONTEXT=y # CONFIG_RT_DEBUGING_PAGE_LEAK is not set # CONFIG_RT_DEBUGING_SPINLOCK is not set # CONFIG_RT_DEBUGING_CRITICAL is not set +CONFIG_RT_USING_OVERFLOW_CHECK=y # # Inter-Thread communication @@ -184,6 +186,7 @@ CONFIG_RT_USING_DFS_MQUEUE=y # Device Drivers # # CONFIG_RT_USING_DM is not set +CONFIG_RT_USING_DEV_BUS=y CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_UNAMED_PIPE_NUMBER=64 CONFIG_RT_USING_SYSTEM_WORKQUEUE=y @@ -210,6 +213,8 @@ CONFIG_RT_USING_NULL=y CONFIG_RT_USING_ZERO=y CONFIG_RT_USING_RANDOM=y CONFIG_RT_USING_PWM=y +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set # CONFIG_RT_USING_PM is not set @@ -236,21 +241,12 @@ CONFIG_RT_USING_QSPI=y # CONFIG_RT_USING_TOUCH is not set # CONFIG_RT_USING_LCD is not set # CONFIG_RT_USING_HWCRYPTO is not set -# CONFIG_RT_USING_PULSE_ENCODER is not set -# CONFIG_RT_USING_INPUT_CAPTURE is not set -CONFIG_RT_USING_DEV_BUS=y # CONFIG_RT_USING_WIFI is not set # CONFIG_RT_USING_VIRTIO is not set CONFIG_RT_USING_PIN=y CONFIG_RT_USING_KTIME=y # CONFIG_RT_USING_HWTIMER is not set - -# -# Using USB -# -# CONFIG_RT_USING_USB_HOST is not set -# CONFIG_RT_USING_USB_DEVICE is not set -# end of Using USB +# CONFIG_RT_USING_CHERRYUSB is not set # end of Device Drivers # @@ -422,6 +418,15 @@ CONFIG_RT_USING_ADT_REF=y # end of Utilities # CONFIG_RT_USING_VBUS is not set + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set # end of RT-Thread Components # @@ -1317,9 +1322,9 @@ CONFIG_RT_USING_UART1=y # CONFIG_RT_USING_UART2 is not set # CONFIG_RT_USING_UART3 is not set CONFIG_BSP_USING_SPI=y -CONFIG_RT_USING_SPIM0=y +# CONFIG_RT_USING_SPIM0 is not set # CONFIG_RT_USING_SPIM1 is not set -# CONFIG_RT_USING_SPIM2 is not set +CONFIG_RT_USING_SPIM2=y # CONFIG_RT_USING_SPIM3 is not set CONFIG_BSP_USING_CAN=y CONFIG_RT_USING_CANFD=y @@ -1344,8 +1349,8 @@ CONFIG_RT_USING_PWM2=y # CONFIG_RT_USING_PWM7 is not set CONFIG_BSP_USING_I2C=y CONFIG_I2C_USE_MIO=y -CONFIG_RT_USING_MIO0=y -CONFIG_RT_USING_MIO1=y +# CONFIG_RT_USING_MIO0 is not set +# CONFIG_RT_USING_MIO1 is not set # CONFIG_RT_USING_MIO2 is not set # CONFIG_RT_USING_MIO3 is not set # CONFIG_RT_USING_MIO4 is not set @@ -1359,7 +1364,7 @@ CONFIG_RT_USING_MIO1=y # CONFIG_RT_USING_MIO12 is not set # CONFIG_RT_USING_MIO13 is not set # CONFIG_RT_USING_MIO14 is not set -# CONFIG_RT_USING_MIO15 is not set +CONFIG_RT_USING_MIO15=y # CONFIG_I2C_USE_CONTROLLER is not set CONFIG_BSP_USING_SDIF=y CONFIG_BSP_USING_SDCARD_FATFS=y @@ -1393,15 +1398,15 @@ CONFIG_USE_AARCH64_L1_TO_AARCH32=y # Soc configuration # # CONFIG_TARGET_PHYTIUMPI is not set -# CONFIG_TARGET_E2000Q is not set -CONFIG_TARGET_E2000D=y +CONFIG_TARGET_E2000Q=y +# CONFIG_TARGET_E2000D is not set # CONFIG_TARGET_E2000S is not set # CONFIG_TARGET_FT2004 is not set # CONFIG_TARGET_D2000 is not set # CONFIG_TARGET_PD2308 is not set CONFIG_SOC_NAME="e2000" -CONFIG_TARGET_TYPE_NAME="d" -CONFIG_SOC_CORE_NUM=2 +CONFIG_TARGET_TYPE_NAME="q" +CONFIG_SOC_CORE_NUM=4 CONFIG_F32BIT_MEMORY_ADDRESS=0x80000000 CONFIG_F32BIT_MEMORY_LENGTH=0x80000000 CONFIG_F64BIT_MEMORY_ADDRESS=0x2000000000 @@ -1415,22 +1420,21 @@ CONFIG_DEFAULT_DEBUG_PRINT_UART1=y # # Board Configuration # -CONFIG_E2000D_DEMO_BOARD=y CONFIG_BOARD_NAME="demo" - -# -# IO mux configuration when board start up -# # CONFIG_USE_SPI_IOPAD is not set # CONFIG_USE_GPIO_IOPAD is not set # CONFIG_USE_CAN_IOPAD is not set # CONFIG_USE_QSPI_IOPAD is not set # CONFIG_USE_PWM_IOPAD is not set -# CONFIG_USE_ADC_IOPAD is not set # CONFIG_USE_MIO_IOPAD is not set # CONFIG_USE_TACHO_IOPAD is not set # CONFIG_USE_UART_IOPAD is not set # CONFIG_USE_THIRD_PARTY_IOPAD is not set +CONFIG_E2000Q_DEMO_BOARD=y + +# +# IO mux configuration when board start up +# # end of IO mux configuration when board start up # CONFIG_CUS_DEMO_BOARD is not set @@ -1453,10 +1457,4 @@ CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y CONFIG_INTERRUPT_ROLE_MASTER=y # CONFIG_INTERRUPT_ROLE_SLAVE is not set # end of Sdk common configuration - -# -# Image information configuration -# -# CONFIG_IMAGE_INFO is not set -# end of Image information configuration # end of Standalone Setting diff --git a/bsp/phytium/aarch32/Kconfig b/bsp/phytium/aarch32/Kconfig index b80f6f07f9..5b99c615e8 100644 --- a/bsp/phytium/aarch32/Kconfig +++ b/bsp/phytium/aarch32/Kconfig @@ -2,8 +2,6 @@ mainmenu "RT-Thread Project Configuration" RTT_DIR := ../../.. -BSP_DIR := ../. - SDK_DIR := .././libraries/phytium_standalone_sdk PKGS_DIR := packages diff --git a/bsp/phytium/aarch32/applications/main.c b/bsp/phytium/aarch32/applications/main.c index 0b62318c5a..2ca409ba93 100644 --- a/bsp/phytium/aarch32/applications/main.c +++ b/bsp/phytium/aarch32/applications/main.c @@ -58,7 +58,7 @@ static void demo_core_thread(void *parameter) level = rt_cpus_lock(); rt_kprintf("Hi, core%d \r\n", rt_hw_cpu_id()); rt_cpus_unlock(level); - rt_thread_mdelay(200000); + rt_thread_mdelay(20000); } } @@ -80,6 +80,7 @@ void demo_core(void) rt_thread_control(&test_core[i], RT_THREAD_CTRL_BIND_CPU, (void *)cpu_id); rt_thread_startup(&test_core[i]); + rt_thread_mdelay(500); } } #endif @@ -91,4 +92,3 @@ int main(void) #endif return RT_EOK; } - diff --git a/bsp/phytium/aarch32/configs/e2000d_demo_rtsmart b/bsp/phytium/aarch32/configs/e2000d_demo_rtsmart index b481181c19..ad949ede1e 100644 --- a/bsp/phytium/aarch32/configs/e2000d_demo_rtsmart +++ b/bsp/phytium/aarch32/configs/e2000d_demo_rtsmart @@ -15,7 +15,6 @@ CONFIG_RT_THREAD_PRIORITY_32=y # CONFIG_RT_THREAD_PRIORITY_256 is not set CONFIG_RT_THREAD_PRIORITY_MAX=32 CONFIG_RT_TICK_PER_SECOND=1000 -CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y CONFIG_RT_HOOK_USING_FUNC_PTR=y # CONFIG_RT_USING_HOOKLIST is not set @@ -26,6 +25,8 @@ CONFIG_SYSTEM_THREAD_STACK_SIZE=4096 CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 CONFIG_RT_TIMER_THREAD_STACK_SIZE=4096 +# CONFIG_RT_USING_TIMER_ALL_SOFT is not set +CONFIG_RT_USING_CPU_USAGE_TRACER=y # # kservice optimization @@ -49,6 +50,7 @@ CONFIG_RT_DEBUGING_CONTEXT=y # CONFIG_RT_DEBUGING_PAGE_LEAK is not set # CONFIG_RT_DEBUGING_SPINLOCK is not set CONFIG_RT_DEBUGING_CRITICAL=y +CONFIG_RT_USING_OVERFLOW_CHECK=y # # Inter-Thread communication @@ -193,6 +195,7 @@ CONFIG_RT_PAGECACHE_GC_STOP_LEVEL=70 # Device Drivers # # CONFIG_RT_USING_DM is not set +CONFIG_RT_USING_DEV_BUS=y CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_UNAMED_PIPE_NUMBER=64 CONFIG_RT_USING_SYSTEM_WORKQUEUE=y @@ -219,6 +222,8 @@ CONFIG_RT_USING_NULL=y CONFIG_RT_USING_ZERO=y CONFIG_RT_USING_RANDOM=y CONFIG_RT_USING_PWM=y +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set # CONFIG_RT_USING_PM is not set @@ -245,21 +250,12 @@ CONFIG_RT_USING_QSPI=y # CONFIG_RT_USING_TOUCH is not set # CONFIG_RT_USING_LCD is not set # CONFIG_RT_USING_HWCRYPTO is not set -# CONFIG_RT_USING_PULSE_ENCODER is not set -# CONFIG_RT_USING_INPUT_CAPTURE is not set -CONFIG_RT_USING_DEV_BUS=y # CONFIG_RT_USING_WIFI is not set # CONFIG_RT_USING_VIRTIO is not set CONFIG_RT_USING_PIN=y CONFIG_RT_USING_KTIME=y # CONFIG_RT_USING_HWTIMER is not set - -# -# Using USB -# -# CONFIG_RT_USING_USB_HOST is not set -# CONFIG_RT_USING_USB_DEVICE is not set -# end of Using USB +# CONFIG_RT_USING_CHERRYUSB is not set # end of Device Drivers # @@ -454,6 +450,15 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64 # # CONFIG_RT_USING_MEMBLOCK is not set # end of Memory management + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set # end of RT-Thread Components # @@ -1349,9 +1354,9 @@ CONFIG_RT_USING_UART1=y # CONFIG_RT_USING_UART2 is not set # CONFIG_RT_USING_UART3 is not set CONFIG_BSP_USING_SPI=y -CONFIG_RT_USING_SPIM0=y +# CONFIG_RT_USING_SPIM0 is not set # CONFIG_RT_USING_SPIM1 is not set -# CONFIG_RT_USING_SPIM2 is not set +CONFIG_RT_USING_SPIM2=y # CONFIG_RT_USING_SPIM3 is not set CONFIG_BSP_USING_CAN=y CONFIG_RT_USING_CANFD=y @@ -1376,8 +1381,8 @@ CONFIG_RT_USING_PWM2=y # CONFIG_RT_USING_PWM7 is not set CONFIG_BSP_USING_I2C=y CONFIG_I2C_USE_MIO=y -CONFIG_RT_USING_MIO0=y -CONFIG_RT_USING_MIO1=y +# CONFIG_RT_USING_MIO0 is not set +# CONFIG_RT_USING_MIO1 is not set # CONFIG_RT_USING_MIO2 is not set # CONFIG_RT_USING_MIO3 is not set # CONFIG_RT_USING_MIO4 is not set @@ -1391,7 +1396,7 @@ CONFIG_RT_USING_MIO1=y # CONFIG_RT_USING_MIO12 is not set # CONFIG_RT_USING_MIO13 is not set # CONFIG_RT_USING_MIO14 is not set -# CONFIG_RT_USING_MIO15 is not set +CONFIG_RT_USING_MIO15=y # CONFIG_I2C_USE_CONTROLLER is not set CONFIG_BSP_USING_SDIF=y CONFIG_BSP_USING_SDCARD_FATFS=y @@ -1485,10 +1490,4 @@ CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y CONFIG_INTERRUPT_ROLE_MASTER=y # CONFIG_INTERRUPT_ROLE_SLAVE is not set # end of Sdk common configuration - -# -# Image information configuration -# -# CONFIG_IMAGE_INFO is not set -# end of Image information configuration # end of Standalone Setting diff --git a/bsp/phytium/aarch32/configs/e2000d_demo_rtsmart.h b/bsp/phytium/aarch32/configs/e2000d_demo_rtsmart.h index 8d2b0693d0..3015dfd6c7 100644 --- a/bsp/phytium/aarch32/configs/e2000d_demo_rtsmart.h +++ b/bsp/phytium/aarch32/configs/e2000d_demo_rtsmart.h @@ -11,7 +11,6 @@ #define RT_THREAD_PRIORITY_32 #define RT_THREAD_PRIORITY_MAX 32 #define RT_TICK_PER_SECOND 1000 -#define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK @@ -21,6 +20,7 @@ #define RT_USING_TIMER_SOFT #define RT_TIMER_THREAD_PRIO 4 #define RT_TIMER_THREAD_STACK_SIZE 4096 +#define RT_USING_CPU_USAGE_TRACER /* kservice optimization */ @@ -34,6 +34,7 @@ #define RT_DEBUGING_COLOR #define RT_DEBUGING_CONTEXT #define RT_DEBUGING_CRITICAL +#define RT_USING_OVERFLOW_CHECK /* Inter-Thread communication */ @@ -138,6 +139,7 @@ /* Device Drivers */ +#define RT_USING_DEV_BUS #define RT_USING_DEVICE_IPC #define RT_UNAMED_PIPE_NUMBER 64 #define RT_USING_SYSTEM_WORKQUEUE @@ -164,13 +166,8 @@ #define RT_MMCSD_MAX_PARTITION 16 #define RT_USING_SPI #define RT_USING_QSPI -#define RT_USING_DEV_BUS #define RT_USING_PIN #define RT_USING_KTIME - -/* Using USB */ - -/* end of Using USB */ /* end of Device Drivers */ /* C/C++ and POSIX layer */ @@ -309,6 +306,10 @@ /* Memory management */ /* end of Memory management */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ /* end of RT-Thread Components */ /* RT-Thread Utestcases */ @@ -498,7 +499,7 @@ #define RT_USING_UART0 #define RT_USING_UART1 #define BSP_USING_SPI -#define RT_USING_SPIM0 +#define RT_USING_SPIM2 #define BSP_USING_CAN #define RT_USING_CANFD #define RT_USING_CAN0 @@ -513,8 +514,7 @@ #define RT_USING_PWM2 #define BSP_USING_I2C #define I2C_USE_MIO -#define RT_USING_MIO0 -#define RT_USING_MIO1 +#define RT_USING_MIO15 #define BSP_USING_SDIF #define BSP_USING_SDCARD_FATFS #define USING_SDIF0 @@ -566,10 +566,6 @@ #define USE_DEFAULT_INTERRUPT_CONFIG #define INTERRUPT_ROLE_MASTER /* end of Sdk common configuration */ - -/* Image information configuration */ - -/* end of Image information configuration */ /* end of Standalone Setting */ #endif diff --git a/bsp/phytium/aarch32/configs/e2000d_demo_rtthread b/bsp/phytium/aarch32/configs/e2000d_demo_rtthread index 34f0e9088f..7970578ae9 100644 --- a/bsp/phytium/aarch32/configs/e2000d_demo_rtthread +++ b/bsp/phytium/aarch32/configs/e2000d_demo_rtthread @@ -15,7 +15,6 @@ CONFIG_RT_THREAD_PRIORITY_32=y # CONFIG_RT_THREAD_PRIORITY_256 is not set CONFIG_RT_THREAD_PRIORITY_MAX=32 CONFIG_RT_TICK_PER_SECOND=1000 -CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y CONFIG_RT_HOOK_USING_FUNC_PTR=y # CONFIG_RT_USING_HOOKLIST is not set @@ -26,6 +25,8 @@ CONFIG_SYSTEM_THREAD_STACK_SIZE=4096 CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 CONFIG_RT_TIMER_THREAD_STACK_SIZE=4096 +# CONFIG_RT_USING_TIMER_ALL_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set # # kservice optimization @@ -49,6 +50,7 @@ CONFIG_RT_DEBUGING_CONTEXT=y # CONFIG_RT_DEBUGING_PAGE_LEAK is not set # CONFIG_RT_DEBUGING_SPINLOCK is not set # CONFIG_RT_DEBUGING_CRITICAL is not set +CONFIG_RT_USING_OVERFLOW_CHECK=y # # Inter-Thread communication @@ -184,6 +186,7 @@ CONFIG_RT_USING_DFS_MQUEUE=y # Device Drivers # # CONFIG_RT_USING_DM is not set +CONFIG_RT_USING_DEV_BUS=y CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_UNAMED_PIPE_NUMBER=64 CONFIG_RT_USING_SYSTEM_WORKQUEUE=y @@ -210,6 +213,8 @@ CONFIG_RT_USING_NULL=y CONFIG_RT_USING_ZERO=y CONFIG_RT_USING_RANDOM=y CONFIG_RT_USING_PWM=y +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set # CONFIG_RT_USING_PM is not set @@ -236,21 +241,12 @@ CONFIG_RT_USING_QSPI=y # CONFIG_RT_USING_TOUCH is not set # CONFIG_RT_USING_LCD is not set # CONFIG_RT_USING_HWCRYPTO is not set -# CONFIG_RT_USING_PULSE_ENCODER is not set -# CONFIG_RT_USING_INPUT_CAPTURE is not set -CONFIG_RT_USING_DEV_BUS=y # CONFIG_RT_USING_WIFI is not set # CONFIG_RT_USING_VIRTIO is not set CONFIG_RT_USING_PIN=y CONFIG_RT_USING_KTIME=y # CONFIG_RT_USING_HWTIMER is not set - -# -# Using USB -# -# CONFIG_RT_USING_USB_HOST is not set -# CONFIG_RT_USING_USB_DEVICE is not set -# end of Using USB +# CONFIG_RT_USING_CHERRYUSB is not set # end of Device Drivers # @@ -422,6 +418,15 @@ CONFIG_RT_USING_ADT_REF=y # end of Utilities # CONFIG_RT_USING_VBUS is not set + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set # end of RT-Thread Components # @@ -1317,9 +1322,9 @@ CONFIG_RT_USING_UART1=y # CONFIG_RT_USING_UART2 is not set # CONFIG_RT_USING_UART3 is not set CONFIG_BSP_USING_SPI=y -CONFIG_RT_USING_SPIM0=y +# CONFIG_RT_USING_SPIM0 is not set # CONFIG_RT_USING_SPIM1 is not set -# CONFIG_RT_USING_SPIM2 is not set +CONFIG_RT_USING_SPIM2=y # CONFIG_RT_USING_SPIM3 is not set CONFIG_BSP_USING_CAN=y CONFIG_RT_USING_CANFD=y @@ -1453,10 +1458,4 @@ CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y CONFIG_INTERRUPT_ROLE_MASTER=y # CONFIG_INTERRUPT_ROLE_SLAVE is not set # end of Sdk common configuration - -# -# Image information configuration -# -# CONFIG_IMAGE_INFO is not set -# end of Image information configuration # end of Standalone Setting diff --git a/bsp/phytium/aarch32/configs/e2000d_demo_rtthread.h b/bsp/phytium/aarch32/configs/e2000d_demo_rtthread.h index 8f4dd6f43f..f140a43d53 100644 --- a/bsp/phytium/aarch32/configs/e2000d_demo_rtthread.h +++ b/bsp/phytium/aarch32/configs/e2000d_demo_rtthread.h @@ -10,7 +10,6 @@ #define RT_THREAD_PRIORITY_32 #define RT_THREAD_PRIORITY_MAX 32 #define RT_TICK_PER_SECOND 1000 -#define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK @@ -32,6 +31,7 @@ #define RT_DEBUGING_ASSERT #define RT_DEBUGING_COLOR #define RT_DEBUGING_CONTEXT +#define RT_USING_OVERFLOW_CHECK /* Inter-Thread communication */ @@ -124,6 +124,7 @@ /* Device Drivers */ +#define RT_USING_DEV_BUS #define RT_USING_DEVICE_IPC #define RT_UNAMED_PIPE_NUMBER 64 #define RT_USING_SYSTEM_WORKQUEUE @@ -150,13 +151,8 @@ #define RT_MMCSD_MAX_PARTITION 16 #define RT_USING_SPI #define RT_USING_QSPI -#define RT_USING_DEV_BUS #define RT_USING_PIN #define RT_USING_KTIME - -/* Using USB */ - -/* end of Using USB */ /* end of Device Drivers */ /* C/C++ and POSIX layer */ @@ -277,6 +273,10 @@ #define RT_USING_ADT_HASHMAP #define RT_USING_ADT_REF /* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ /* end of RT-Thread Components */ /* RT-Thread Utestcases */ @@ -466,7 +466,7 @@ #define RT_USING_UART0 #define RT_USING_UART1 #define BSP_USING_SPI -#define RT_USING_SPIM0 +#define RT_USING_SPIM2 #define BSP_USING_CAN #define RT_USING_CANFD #define RT_USING_CAN0 @@ -535,10 +535,6 @@ #define USE_DEFAULT_INTERRUPT_CONFIG #define INTERRUPT_ROLE_MASTER /* end of Sdk common configuration */ - -/* Image information configuration */ - -/* end of Image information configuration */ /* end of Standalone Setting */ #endif diff --git a/bsp/phytium/aarch32/configs/e2000q_demo_rtsmart b/bsp/phytium/aarch32/configs/e2000q_demo_rtsmart index 01d04de9eb..251c3dfea1 100644 --- a/bsp/phytium/aarch32/configs/e2000q_demo_rtsmart +++ b/bsp/phytium/aarch32/configs/e2000q_demo_rtsmart @@ -15,7 +15,6 @@ CONFIG_RT_THREAD_PRIORITY_32=y # CONFIG_RT_THREAD_PRIORITY_256 is not set CONFIG_RT_THREAD_PRIORITY_MAX=32 CONFIG_RT_TICK_PER_SECOND=1000 -CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y CONFIG_RT_HOOK_USING_FUNC_PTR=y # CONFIG_RT_USING_HOOKLIST is not set @@ -26,6 +25,8 @@ CONFIG_SYSTEM_THREAD_STACK_SIZE=4096 CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 CONFIG_RT_TIMER_THREAD_STACK_SIZE=4096 +# CONFIG_RT_USING_TIMER_ALL_SOFT is not set +CONFIG_RT_USING_CPU_USAGE_TRACER=y # # kservice optimization @@ -49,6 +50,7 @@ CONFIG_RT_DEBUGING_CONTEXT=y # CONFIG_RT_DEBUGING_PAGE_LEAK is not set # CONFIG_RT_DEBUGING_SPINLOCK is not set CONFIG_RT_DEBUGING_CRITICAL=y +CONFIG_RT_USING_OVERFLOW_CHECK=y # # Inter-Thread communication @@ -193,6 +195,7 @@ CONFIG_RT_PAGECACHE_GC_STOP_LEVEL=70 # Device Drivers # # CONFIG_RT_USING_DM is not set +CONFIG_RT_USING_DEV_BUS=y CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_UNAMED_PIPE_NUMBER=64 CONFIG_RT_USING_SYSTEM_WORKQUEUE=y @@ -219,6 +222,8 @@ CONFIG_RT_USING_NULL=y CONFIG_RT_USING_ZERO=y CONFIG_RT_USING_RANDOM=y CONFIG_RT_USING_PWM=y +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set # CONFIG_RT_USING_PM is not set @@ -245,21 +250,12 @@ CONFIG_RT_USING_QSPI=y # CONFIG_RT_USING_TOUCH is not set # CONFIG_RT_USING_LCD is not set # CONFIG_RT_USING_HWCRYPTO is not set -# CONFIG_RT_USING_PULSE_ENCODER is not set -# CONFIG_RT_USING_INPUT_CAPTURE is not set -CONFIG_RT_USING_DEV_BUS=y # CONFIG_RT_USING_WIFI is not set # CONFIG_RT_USING_VIRTIO is not set CONFIG_RT_USING_PIN=y CONFIG_RT_USING_KTIME=y # CONFIG_RT_USING_HWTIMER is not set - -# -# Using USB -# -# CONFIG_RT_USING_USB_HOST is not set -# CONFIG_RT_USING_USB_DEVICE is not set -# end of Using USB +# CONFIG_RT_USING_CHERRYUSB is not set # end of Device Drivers # @@ -454,6 +450,15 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64 # # CONFIG_RT_USING_MEMBLOCK is not set # end of Memory management + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set # end of RT-Thread Components # @@ -1349,9 +1354,9 @@ CONFIG_RT_USING_UART1=y # CONFIG_RT_USING_UART2 is not set # CONFIG_RT_USING_UART3 is not set CONFIG_BSP_USING_SPI=y -CONFIG_RT_USING_SPIM0=y +# CONFIG_RT_USING_SPIM0 is not set # CONFIG_RT_USING_SPIM1 is not set -# CONFIG_RT_USING_SPIM2 is not set +CONFIG_RT_USING_SPIM2=y # CONFIG_RT_USING_SPIM3 is not set CONFIG_BSP_USING_CAN=y CONFIG_RT_USING_CANFD=y @@ -1376,8 +1381,8 @@ CONFIG_RT_USING_PWM2=y # CONFIG_RT_USING_PWM7 is not set CONFIG_BSP_USING_I2C=y CONFIG_I2C_USE_MIO=y -CONFIG_RT_USING_MIO0=y -CONFIG_RT_USING_MIO1=y +# CONFIG_RT_USING_MIO0 is not set +# CONFIG_RT_USING_MIO1 is not set # CONFIG_RT_USING_MIO2 is not set # CONFIG_RT_USING_MIO3 is not set # CONFIG_RT_USING_MIO4 is not set @@ -1391,7 +1396,7 @@ CONFIG_RT_USING_MIO1=y # CONFIG_RT_USING_MIO12 is not set # CONFIG_RT_USING_MIO13 is not set # CONFIG_RT_USING_MIO14 is not set -# CONFIG_RT_USING_MIO15 is not set +CONFIG_RT_USING_MIO15=y # CONFIG_I2C_USE_CONTROLLER is not set CONFIG_BSP_USING_SDIF=y CONFIG_BSP_USING_SDCARD_FATFS=y @@ -1403,7 +1408,7 @@ CONFIG_USE_SDIF1_TF=y # CONFIG_USE_SDIF1_EMMC is not set CONFIG_BSP_USING_DC=y CONFIG_RT_USING_DC_CHANNEL0=y -# CONFIG_RT_USING_DC_CHANNEL1 is not set +CONFIG_RT_USING_DC_CHANNEL1=y # CONFIG_BSP_USING_XHCI is not set # CONFIG_BSP_USING_PUSB2 is not set # end of On-chip Peripheral Drivers @@ -1484,10 +1489,4 @@ CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y CONFIG_INTERRUPT_ROLE_MASTER=y # CONFIG_INTERRUPT_ROLE_SLAVE is not set # end of Sdk common configuration - -# -# Image information configuration -# -# CONFIG_IMAGE_INFO is not set -# end of Image information configuration # end of Standalone Setting diff --git a/bsp/phytium/aarch32/configs/e2000q_demo_rtsmart.h b/bsp/phytium/aarch32/configs/e2000q_demo_rtsmart.h index 9c1ea97896..cabdebdfa1 100644 --- a/bsp/phytium/aarch32/configs/e2000q_demo_rtsmart.h +++ b/bsp/phytium/aarch32/configs/e2000q_demo_rtsmart.h @@ -11,7 +11,6 @@ #define RT_THREAD_PRIORITY_32 #define RT_THREAD_PRIORITY_MAX 32 #define RT_TICK_PER_SECOND 1000 -#define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK @@ -21,6 +20,7 @@ #define RT_USING_TIMER_SOFT #define RT_TIMER_THREAD_PRIO 4 #define RT_TIMER_THREAD_STACK_SIZE 4096 +#define RT_USING_CPU_USAGE_TRACER /* kservice optimization */ @@ -34,6 +34,7 @@ #define RT_DEBUGING_COLOR #define RT_DEBUGING_CONTEXT #define RT_DEBUGING_CRITICAL +#define RT_USING_OVERFLOW_CHECK /* Inter-Thread communication */ @@ -138,6 +139,7 @@ /* Device Drivers */ +#define RT_USING_DEV_BUS #define RT_USING_DEVICE_IPC #define RT_UNAMED_PIPE_NUMBER 64 #define RT_USING_SYSTEM_WORKQUEUE @@ -164,13 +166,8 @@ #define RT_MMCSD_MAX_PARTITION 16 #define RT_USING_SPI #define RT_USING_QSPI -#define RT_USING_DEV_BUS #define RT_USING_PIN #define RT_USING_KTIME - -/* Using USB */ - -/* end of Using USB */ /* end of Device Drivers */ /* C/C++ and POSIX layer */ @@ -309,6 +306,10 @@ /* Memory management */ /* end of Memory management */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ /* end of RT-Thread Components */ /* RT-Thread Utestcases */ @@ -498,7 +499,7 @@ #define RT_USING_UART0 #define RT_USING_UART1 #define BSP_USING_SPI -#define RT_USING_SPIM0 +#define RT_USING_SPIM2 #define BSP_USING_CAN #define RT_USING_CANFD #define RT_USING_CAN0 @@ -513,8 +514,7 @@ #define RT_USING_PWM2 #define BSP_USING_I2C #define I2C_USE_MIO -#define RT_USING_MIO0 -#define RT_USING_MIO1 +#define RT_USING_MIO15 #define BSP_USING_SDIF #define BSP_USING_SDCARD_FATFS #define USING_SDIF0 @@ -523,6 +523,7 @@ #define USE_SDIF1_TF #define BSP_USING_DC #define RT_USING_DC_CHANNEL0 +#define RT_USING_DC_CHANNEL1 /* end of On-chip Peripheral Drivers */ /* Board extended module Drivers */ @@ -566,10 +567,6 @@ #define USE_DEFAULT_INTERRUPT_CONFIG #define INTERRUPT_ROLE_MASTER /* end of Sdk common configuration */ - -/* Image information configuration */ - -/* end of Image information configuration */ /* end of Standalone Setting */ #endif diff --git a/bsp/phytium/aarch32/configs/e2000q_demo_rtthread b/bsp/phytium/aarch32/configs/e2000q_demo_rtthread index 006545bb19..4e7fc75c3f 100644 --- a/bsp/phytium/aarch32/configs/e2000q_demo_rtthread +++ b/bsp/phytium/aarch32/configs/e2000q_demo_rtthread @@ -15,7 +15,6 @@ CONFIG_RT_THREAD_PRIORITY_32=y # CONFIG_RT_THREAD_PRIORITY_256 is not set CONFIG_RT_THREAD_PRIORITY_MAX=32 CONFIG_RT_TICK_PER_SECOND=1000 -CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y CONFIG_RT_HOOK_USING_FUNC_PTR=y # CONFIG_RT_USING_HOOKLIST is not set @@ -26,6 +25,8 @@ CONFIG_SYSTEM_THREAD_STACK_SIZE=4096 CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 CONFIG_RT_TIMER_THREAD_STACK_SIZE=4096 +# CONFIG_RT_USING_TIMER_ALL_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set # # kservice optimization @@ -49,6 +50,7 @@ CONFIG_RT_DEBUGING_CONTEXT=y # CONFIG_RT_DEBUGING_PAGE_LEAK is not set # CONFIG_RT_DEBUGING_SPINLOCK is not set # CONFIG_RT_DEBUGING_CRITICAL is not set +CONFIG_RT_USING_OVERFLOW_CHECK=y # # Inter-Thread communication @@ -184,6 +186,7 @@ CONFIG_RT_USING_DFS_MQUEUE=y # Device Drivers # # CONFIG_RT_USING_DM is not set +CONFIG_RT_USING_DEV_BUS=y CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_UNAMED_PIPE_NUMBER=64 CONFIG_RT_USING_SYSTEM_WORKQUEUE=y @@ -210,6 +213,8 @@ CONFIG_RT_USING_NULL=y CONFIG_RT_USING_ZERO=y CONFIG_RT_USING_RANDOM=y CONFIG_RT_USING_PWM=y +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set # CONFIG_RT_USING_PM is not set @@ -236,21 +241,12 @@ CONFIG_RT_USING_QSPI=y # CONFIG_RT_USING_TOUCH is not set # CONFIG_RT_USING_LCD is not set # CONFIG_RT_USING_HWCRYPTO is not set -# CONFIG_RT_USING_PULSE_ENCODER is not set -# CONFIG_RT_USING_INPUT_CAPTURE is not set -CONFIG_RT_USING_DEV_BUS=y # CONFIG_RT_USING_WIFI is not set # CONFIG_RT_USING_VIRTIO is not set CONFIG_RT_USING_PIN=y CONFIG_RT_USING_KTIME=y # CONFIG_RT_USING_HWTIMER is not set - -# -# Using USB -# -# CONFIG_RT_USING_USB_HOST is not set -# CONFIG_RT_USING_USB_DEVICE is not set -# end of Using USB +# CONFIG_RT_USING_CHERRYUSB is not set # end of Device Drivers # @@ -422,6 +418,15 @@ CONFIG_RT_USING_ADT_REF=y # end of Utilities # CONFIG_RT_USING_VBUS is not set + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set # end of RT-Thread Components # @@ -1317,9 +1322,9 @@ CONFIG_RT_USING_UART1=y # CONFIG_RT_USING_UART2 is not set # CONFIG_RT_USING_UART3 is not set CONFIG_BSP_USING_SPI=y -CONFIG_RT_USING_SPIM0=y +# CONFIG_RT_USING_SPIM0 is not set # CONFIG_RT_USING_SPIM1 is not set -# CONFIG_RT_USING_SPIM2 is not set +CONFIG_RT_USING_SPIM2=y # CONFIG_RT_USING_SPIM3 is not set CONFIG_BSP_USING_CAN=y CONFIG_RT_USING_CANFD=y @@ -1344,8 +1349,8 @@ CONFIG_RT_USING_PWM2=y # CONFIG_RT_USING_PWM7 is not set CONFIG_BSP_USING_I2C=y CONFIG_I2C_USE_MIO=y -CONFIG_RT_USING_MIO0=y -CONFIG_RT_USING_MIO1=y +# CONFIG_RT_USING_MIO0 is not set +# CONFIG_RT_USING_MIO1 is not set # CONFIG_RT_USING_MIO2 is not set # CONFIG_RT_USING_MIO3 is not set # CONFIG_RT_USING_MIO4 is not set @@ -1359,7 +1364,7 @@ CONFIG_RT_USING_MIO1=y # CONFIG_RT_USING_MIO12 is not set # CONFIG_RT_USING_MIO13 is not set # CONFIG_RT_USING_MIO14 is not set -# CONFIG_RT_USING_MIO15 is not set +CONFIG_RT_USING_MIO15=y # CONFIG_I2C_USE_CONTROLLER is not set CONFIG_BSP_USING_SDIF=y CONFIG_BSP_USING_SDCARD_FATFS=y @@ -1452,10 +1457,4 @@ CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y CONFIG_INTERRUPT_ROLE_MASTER=y # CONFIG_INTERRUPT_ROLE_SLAVE is not set # end of Sdk common configuration - -# -# Image information configuration -# -# CONFIG_IMAGE_INFO is not set -# end of Image information configuration # end of Standalone Setting diff --git a/bsp/phytium/aarch32/configs/e2000q_demo_rtthread.h b/bsp/phytium/aarch32/configs/e2000q_demo_rtthread.h index d5c52164aa..49d33c8d08 100644 --- a/bsp/phytium/aarch32/configs/e2000q_demo_rtthread.h +++ b/bsp/phytium/aarch32/configs/e2000q_demo_rtthread.h @@ -10,7 +10,6 @@ #define RT_THREAD_PRIORITY_32 #define RT_THREAD_PRIORITY_MAX 32 #define RT_TICK_PER_SECOND 1000 -#define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK @@ -32,6 +31,7 @@ #define RT_DEBUGING_ASSERT #define RT_DEBUGING_COLOR #define RT_DEBUGING_CONTEXT +#define RT_USING_OVERFLOW_CHECK /* Inter-Thread communication */ @@ -124,6 +124,7 @@ /* Device Drivers */ +#define RT_USING_DEV_BUS #define RT_USING_DEVICE_IPC #define RT_UNAMED_PIPE_NUMBER 64 #define RT_USING_SYSTEM_WORKQUEUE @@ -150,13 +151,8 @@ #define RT_MMCSD_MAX_PARTITION 16 #define RT_USING_SPI #define RT_USING_QSPI -#define RT_USING_DEV_BUS #define RT_USING_PIN #define RT_USING_KTIME - -/* Using USB */ - -/* end of Using USB */ /* end of Device Drivers */ /* C/C++ and POSIX layer */ @@ -277,6 +273,10 @@ #define RT_USING_ADT_HASHMAP #define RT_USING_ADT_REF /* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ /* end of RT-Thread Components */ /* RT-Thread Utestcases */ @@ -466,7 +466,7 @@ #define RT_USING_UART0 #define RT_USING_UART1 #define BSP_USING_SPI -#define RT_USING_SPIM0 +#define RT_USING_SPIM2 #define BSP_USING_CAN #define RT_USING_CANFD #define RT_USING_CAN0 @@ -481,8 +481,7 @@ #define RT_USING_PWM2 #define BSP_USING_I2C #define I2C_USE_MIO -#define RT_USING_MIO0 -#define RT_USING_MIO1 +#define RT_USING_MIO15 #define BSP_USING_SDIF #define BSP_USING_SDCARD_FATFS #define USING_SDIF0 @@ -535,10 +534,6 @@ #define USE_DEFAULT_INTERRUPT_CONFIG #define INTERRUPT_ROLE_MASTER /* end of Sdk common configuration */ - -/* Image information configuration */ - -/* end of Image information configuration */ /* end of Standalone Setting */ #endif diff --git a/bsp/phytium/aarch32/configs/phytium_pi_rtsmart b/bsp/phytium/aarch32/configs/phytium_pi_rtsmart index 67ab1c1f66..8c89d1c0a0 100644 --- a/bsp/phytium/aarch32/configs/phytium_pi_rtsmart +++ b/bsp/phytium/aarch32/configs/phytium_pi_rtsmart @@ -15,7 +15,6 @@ CONFIG_RT_THREAD_PRIORITY_32=y # CONFIG_RT_THREAD_PRIORITY_256 is not set CONFIG_RT_THREAD_PRIORITY_MAX=32 CONFIG_RT_TICK_PER_SECOND=1000 -CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y CONFIG_RT_HOOK_USING_FUNC_PTR=y # CONFIG_RT_USING_HOOKLIST is not set @@ -26,6 +25,8 @@ CONFIG_SYSTEM_THREAD_STACK_SIZE=4096 CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 CONFIG_RT_TIMER_THREAD_STACK_SIZE=4096 +# CONFIG_RT_USING_TIMER_ALL_SOFT is not set +CONFIG_RT_USING_CPU_USAGE_TRACER=y # # kservice optimization @@ -49,6 +50,7 @@ CONFIG_RT_DEBUGING_CONTEXT=y # CONFIG_RT_DEBUGING_PAGE_LEAK is not set # CONFIG_RT_DEBUGING_SPINLOCK is not set CONFIG_RT_DEBUGING_CRITICAL=y +CONFIG_RT_USING_OVERFLOW_CHECK=y # # Inter-Thread communication @@ -193,6 +195,7 @@ CONFIG_RT_PAGECACHE_GC_STOP_LEVEL=70 # Device Drivers # # CONFIG_RT_USING_DM is not set +CONFIG_RT_USING_DEV_BUS=y CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_UNAMED_PIPE_NUMBER=64 CONFIG_RT_USING_SYSTEM_WORKQUEUE=y @@ -219,6 +222,8 @@ CONFIG_RT_USING_NULL=y CONFIG_RT_USING_ZERO=y CONFIG_RT_USING_RANDOM=y CONFIG_RT_USING_PWM=y +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set # CONFIG_RT_USING_PM is not set @@ -245,21 +250,12 @@ CONFIG_RT_USING_QSPI=y # CONFIG_RT_USING_TOUCH is not set # CONFIG_RT_USING_LCD is not set # CONFIG_RT_USING_HWCRYPTO is not set -# CONFIG_RT_USING_PULSE_ENCODER is not set -# CONFIG_RT_USING_INPUT_CAPTURE is not set -CONFIG_RT_USING_DEV_BUS=y # CONFIG_RT_USING_WIFI is not set # CONFIG_RT_USING_VIRTIO is not set CONFIG_RT_USING_PIN=y CONFIG_RT_USING_KTIME=y # CONFIG_RT_USING_HWTIMER is not set - -# -# Using USB -# -# CONFIG_RT_USING_USB_HOST is not set -# CONFIG_RT_USING_USB_DEVICE is not set -# end of Using USB +# CONFIG_RT_USING_CHERRYUSB is not set # end of Device Drivers # @@ -454,6 +450,15 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64 # # CONFIG_RT_USING_MEMBLOCK is not set # end of Memory management + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set # end of RT-Thread Components # @@ -1391,10 +1396,10 @@ CONFIG_RT_USING_MIO1=y # CONFIG_I2C_USE_CONTROLLER is not set CONFIG_BSP_USING_SDIF=y CONFIG_BSP_USING_SDCARD_FATFS=y -# CONFIG_USING_SDIF0 is not set -CONFIG_USING_SDIF1=y -CONFIG_USE_SDIF1_TF=y -# CONFIG_USE_SDIF1_EMMC is not set +CONFIG_USING_SDIF0=y +CONFIG_USE_SDIF0_TF=y +# CONFIG_USE_SDIF0_EMMC is not set +# CONFIG_USING_SDIF1 is not set CONFIG_BSP_USING_DC=y CONFIG_RT_USING_DC_CHANNEL0=y # CONFIG_RT_USING_DC_CHANNEL1 is not set @@ -1477,10 +1482,4 @@ CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y CONFIG_INTERRUPT_ROLE_MASTER=y # CONFIG_INTERRUPT_ROLE_SLAVE is not set # end of Sdk common configuration - -# -# Image information configuration -# -# CONFIG_IMAGE_INFO is not set -# end of Image information configuration # end of Standalone Setting diff --git a/bsp/phytium/aarch32/configs/phytium_pi_rtsmart.h b/bsp/phytium/aarch32/configs/phytium_pi_rtsmart.h index 211a3c5218..66598d592d 100644 --- a/bsp/phytium/aarch32/configs/phytium_pi_rtsmart.h +++ b/bsp/phytium/aarch32/configs/phytium_pi_rtsmart.h @@ -11,7 +11,6 @@ #define RT_THREAD_PRIORITY_32 #define RT_THREAD_PRIORITY_MAX 32 #define RT_TICK_PER_SECOND 1000 -#define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK @@ -21,6 +20,7 @@ #define RT_USING_TIMER_SOFT #define RT_TIMER_THREAD_PRIO 4 #define RT_TIMER_THREAD_STACK_SIZE 4096 +#define RT_USING_CPU_USAGE_TRACER /* kservice optimization */ @@ -34,6 +34,7 @@ #define RT_DEBUGING_COLOR #define RT_DEBUGING_CONTEXT #define RT_DEBUGING_CRITICAL +#define RT_USING_OVERFLOW_CHECK /* Inter-Thread communication */ @@ -138,6 +139,7 @@ /* Device Drivers */ +#define RT_USING_DEV_BUS #define RT_USING_DEVICE_IPC #define RT_UNAMED_PIPE_NUMBER 64 #define RT_USING_SYSTEM_WORKQUEUE @@ -164,13 +166,8 @@ #define RT_MMCSD_MAX_PARTITION 16 #define RT_USING_SPI #define RT_USING_QSPI -#define RT_USING_DEV_BUS #define RT_USING_PIN #define RT_USING_KTIME - -/* Using USB */ - -/* end of Using USB */ /* end of Device Drivers */ /* C/C++ and POSIX layer */ @@ -309,6 +306,10 @@ /* Memory management */ /* end of Memory management */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ /* end of RT-Thread Components */ /* RT-Thread Utestcases */ @@ -513,8 +514,8 @@ #define RT_USING_MIO1 #define BSP_USING_SDIF #define BSP_USING_SDCARD_FATFS -#define USING_SDIF1 -#define USE_SDIF1_TF +#define USING_SDIF0 +#define USE_SDIF0_TF #define BSP_USING_DC #define RT_USING_DC_CHANNEL0 /* end of On-chip Peripheral Drivers */ @@ -559,10 +560,6 @@ #define USE_DEFAULT_INTERRUPT_CONFIG #define INTERRUPT_ROLE_MASTER /* end of Sdk common configuration */ - -/* Image information configuration */ - -/* end of Image information configuration */ /* end of Standalone Setting */ #endif diff --git a/bsp/phytium/aarch32/configs/phytium_pi_rtthread b/bsp/phytium/aarch32/configs/phytium_pi_rtthread index 1560737cf9..f2c54ccf8a 100644 --- a/bsp/phytium/aarch32/configs/phytium_pi_rtthread +++ b/bsp/phytium/aarch32/configs/phytium_pi_rtthread @@ -15,7 +15,6 @@ CONFIG_RT_THREAD_PRIORITY_32=y # CONFIG_RT_THREAD_PRIORITY_256 is not set CONFIG_RT_THREAD_PRIORITY_MAX=32 CONFIG_RT_TICK_PER_SECOND=1000 -CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y CONFIG_RT_HOOK_USING_FUNC_PTR=y # CONFIG_RT_USING_HOOKLIST is not set @@ -26,6 +25,8 @@ CONFIG_SYSTEM_THREAD_STACK_SIZE=4096 CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 CONFIG_RT_TIMER_THREAD_STACK_SIZE=4096 +# CONFIG_RT_USING_TIMER_ALL_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set # # kservice optimization @@ -49,6 +50,7 @@ CONFIG_RT_DEBUGING_CONTEXT=y # CONFIG_RT_DEBUGING_PAGE_LEAK is not set # CONFIG_RT_DEBUGING_SPINLOCK is not set # CONFIG_RT_DEBUGING_CRITICAL is not set +CONFIG_RT_USING_OVERFLOW_CHECK=y # # Inter-Thread communication @@ -184,6 +186,7 @@ CONFIG_RT_USING_DFS_MQUEUE=y # Device Drivers # # CONFIG_RT_USING_DM is not set +CONFIG_RT_USING_DEV_BUS=y CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_UNAMED_PIPE_NUMBER=64 CONFIG_RT_USING_SYSTEM_WORKQUEUE=y @@ -210,6 +213,8 @@ CONFIG_RT_USING_NULL=y CONFIG_RT_USING_ZERO=y CONFIG_RT_USING_RANDOM=y CONFIG_RT_USING_PWM=y +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set # CONFIG_RT_USING_PM is not set @@ -236,21 +241,12 @@ CONFIG_RT_USING_QSPI=y # CONFIG_RT_USING_TOUCH is not set # CONFIG_RT_USING_LCD is not set # CONFIG_RT_USING_HWCRYPTO is not set -# CONFIG_RT_USING_PULSE_ENCODER is not set -# CONFIG_RT_USING_INPUT_CAPTURE is not set -CONFIG_RT_USING_DEV_BUS=y # CONFIG_RT_USING_WIFI is not set # CONFIG_RT_USING_VIRTIO is not set CONFIG_RT_USING_PIN=y CONFIG_RT_USING_KTIME=y # CONFIG_RT_USING_HWTIMER is not set - -# -# Using USB -# -# CONFIG_RT_USING_USB_HOST is not set -# CONFIG_RT_USING_USB_DEVICE is not set -# end of Using USB +# CONFIG_RT_USING_CHERRYUSB is not set # end of Device Drivers # @@ -422,6 +418,15 @@ CONFIG_RT_USING_ADT_REF=y # end of Utilities # CONFIG_RT_USING_VBUS is not set + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set # end of RT-Thread Components # @@ -1359,10 +1364,10 @@ CONFIG_RT_USING_MIO1=y # CONFIG_I2C_USE_CONTROLLER is not set CONFIG_BSP_USING_SDIF=y CONFIG_BSP_USING_SDCARD_FATFS=y -# CONFIG_USING_SDIF0 is not set -CONFIG_USING_SDIF1=y -CONFIG_USE_SDIF1_TF=y -# CONFIG_USE_SDIF1_EMMC is not set +CONFIG_USING_SDIF0=y +CONFIG_USE_SDIF0_TF=y +# CONFIG_USE_SDIF0_EMMC is not set +# CONFIG_USING_SDIF1 is not set CONFIG_BSP_USING_DC=y CONFIG_RT_USING_DC_CHANNEL0=y CONFIG_RT_USING_DC_CHANNEL1=y @@ -1445,10 +1450,4 @@ CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y CONFIG_INTERRUPT_ROLE_MASTER=y # CONFIG_INTERRUPT_ROLE_SLAVE is not set # end of Sdk common configuration - -# -# Image information configuration -# -# CONFIG_IMAGE_INFO is not set -# end of Image information configuration # end of Standalone Setting diff --git a/bsp/phytium/aarch32/configs/phytium_pi_rtthread.h b/bsp/phytium/aarch32/configs/phytium_pi_rtthread.h index 365e3100fa..42733ae675 100644 --- a/bsp/phytium/aarch32/configs/phytium_pi_rtthread.h +++ b/bsp/phytium/aarch32/configs/phytium_pi_rtthread.h @@ -10,7 +10,6 @@ #define RT_THREAD_PRIORITY_32 #define RT_THREAD_PRIORITY_MAX 32 #define RT_TICK_PER_SECOND 1000 -#define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK @@ -32,6 +31,7 @@ #define RT_DEBUGING_ASSERT #define RT_DEBUGING_COLOR #define RT_DEBUGING_CONTEXT +#define RT_USING_OVERFLOW_CHECK /* Inter-Thread communication */ @@ -124,6 +124,7 @@ /* Device Drivers */ +#define RT_USING_DEV_BUS #define RT_USING_DEVICE_IPC #define RT_UNAMED_PIPE_NUMBER 64 #define RT_USING_SYSTEM_WORKQUEUE @@ -150,13 +151,8 @@ #define RT_MMCSD_MAX_PARTITION 16 #define RT_USING_SPI #define RT_USING_QSPI -#define RT_USING_DEV_BUS #define RT_USING_PIN #define RT_USING_KTIME - -/* Using USB */ - -/* end of Using USB */ /* end of Device Drivers */ /* C/C++ and POSIX layer */ @@ -277,6 +273,10 @@ #define RT_USING_ADT_HASHMAP #define RT_USING_ADT_REF /* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ /* end of RT-Thread Components */ /* RT-Thread Utestcases */ @@ -481,8 +481,8 @@ #define RT_USING_MIO1 #define BSP_USING_SDIF #define BSP_USING_SDCARD_FATFS -#define USING_SDIF1 -#define USE_SDIF1_TF +#define USING_SDIF0 +#define USE_SDIF0_TF #define BSP_USING_DC #define RT_USING_DC_CHANNEL0 #define RT_USING_DC_CHANNEL1 @@ -528,10 +528,6 @@ #define USE_DEFAULT_INTERRUPT_CONFIG #define INTERRUPT_ROLE_MASTER /* end of Sdk common configuration */ - -/* Image information configuration */ - -/* end of Image information configuration */ /* end of Standalone Setting */ #endif diff --git a/bsp/phytium/aarch32/makefile b/bsp/phytium/aarch32/makefile index 94322ca12c..f19f04e7ed 100644 --- a/bsp/phytium/aarch32/makefile +++ b/bsp/phytium/aarch32/makefile @@ -37,8 +37,8 @@ endif boot: make all - cp rtthread_a32.elf /mnt/d/tftboot - cp rtthread_a32.bin /mnt/d/tftboot + cp rtthread_a32.elf /mnt/d/tftpboot + cp rtthread_a32.bin /mnt/d/tftpboot debug: @$(OD) -D rtthread_a32.elf > rtthread_a32.asm diff --git a/bsp/phytium/aarch32/rtconfig.h b/bsp/phytium/aarch32/rtconfig.h index 8f4dd6f43f..49d33c8d08 100644 --- a/bsp/phytium/aarch32/rtconfig.h +++ b/bsp/phytium/aarch32/rtconfig.h @@ -5,12 +5,11 @@ #define RT_NAME_MAX 16 #define RT_USING_SMP -#define RT_CPUS_NR 2 +#define RT_CPUS_NR 4 #define RT_ALIGN_SIZE 4 #define RT_THREAD_PRIORITY_32 #define RT_THREAD_PRIORITY_MAX 32 #define RT_TICK_PER_SECOND 1000 -#define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK @@ -32,6 +31,7 @@ #define RT_DEBUGING_ASSERT #define RT_DEBUGING_COLOR #define RT_DEBUGING_CONTEXT +#define RT_USING_OVERFLOW_CHECK /* Inter-Thread communication */ @@ -124,6 +124,7 @@ /* Device Drivers */ +#define RT_USING_DEV_BUS #define RT_USING_DEVICE_IPC #define RT_UNAMED_PIPE_NUMBER 64 #define RT_USING_SYSTEM_WORKQUEUE @@ -150,13 +151,8 @@ #define RT_MMCSD_MAX_PARTITION 16 #define RT_USING_SPI #define RT_USING_QSPI -#define RT_USING_DEV_BUS #define RT_USING_PIN #define RT_USING_KTIME - -/* Using USB */ - -/* end of Using USB */ /* end of Device Drivers */ /* C/C++ and POSIX layer */ @@ -277,6 +273,10 @@ #define RT_USING_ADT_HASHMAP #define RT_USING_ADT_REF /* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ /* end of RT-Thread Components */ /* RT-Thread Utestcases */ @@ -466,7 +466,7 @@ #define RT_USING_UART0 #define RT_USING_UART1 #define BSP_USING_SPI -#define RT_USING_SPIM0 +#define RT_USING_SPIM2 #define BSP_USING_CAN #define RT_USING_CANFD #define RT_USING_CAN0 @@ -481,8 +481,7 @@ #define RT_USING_PWM2 #define BSP_USING_I2C #define I2C_USE_MIO -#define RT_USING_MIO0 -#define RT_USING_MIO1 +#define RT_USING_MIO15 #define BSP_USING_SDIF #define BSP_USING_SDCARD_FATFS #define USING_SDIF0 @@ -506,10 +505,10 @@ /* Soc configuration */ -#define TARGET_E2000D +#define TARGET_E2000Q #define SOC_NAME "e2000" -#define TARGET_TYPE_NAME "d" -#define SOC_CORE_NUM 2 +#define TARGET_TYPE_NAME "q" +#define SOC_CORE_NUM 4 #define F32BIT_MEMORY_ADDRESS 0x80000000 #define F32BIT_MEMORY_LENGTH 0x80000000 #define F64BIT_MEMORY_ADDRESS 0x2000000000 @@ -520,8 +519,8 @@ /* Board Configuration */ -#define E2000D_DEMO_BOARD #define BOARD_NAME "demo" +#define E2000Q_DEMO_BOARD /* IO mux configuration when board start up */ @@ -535,10 +534,6 @@ #define USE_DEFAULT_INTERRUPT_CONFIG #define INTERRUPT_ROLE_MASTER /* end of Sdk common configuration */ - -/* Image information configuration */ - -/* end of Image information configuration */ /* end of Standalone Setting */ #endif diff --git a/bsp/phytium/aarch64/.config b/bsp/phytium/aarch64/.config index 08c232fd9b..3dea5ae400 100644 --- a/bsp/phytium/aarch64/.config +++ b/bsp/phytium/aarch64/.config @@ -8,14 +8,13 @@ CONFIG_RT_NAME_MAX=16 # CONFIG_RT_USING_NANO is not set # CONFIG_RT_USING_AMP is not set CONFIG_RT_USING_SMP=y -CONFIG_RT_CPUS_NR=2 +CONFIG_RT_CPUS_NR=4 CONFIG_RT_ALIGN_SIZE=4 # CONFIG_RT_THREAD_PRIORITY_8 is not set CONFIG_RT_THREAD_PRIORITY_32=y # CONFIG_RT_THREAD_PRIORITY_256 is not set CONFIG_RT_THREAD_PRIORITY_MAX=32 CONFIG_RT_TICK_PER_SECOND=1000 -CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y CONFIG_RT_HOOK_USING_FUNC_PTR=y # CONFIG_RT_USING_HOOKLIST is not set @@ -26,6 +25,8 @@ CONFIG_SYSTEM_THREAD_STACK_SIZE=8192 CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 CONFIG_RT_TIMER_THREAD_STACK_SIZE=8192 +# CONFIG_RT_USING_TIMER_ALL_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set # # kservice optimization @@ -49,6 +50,7 @@ CONFIG_RT_DEBUGING_COLOR=y # CONFIG_RT_DEBUGING_PAGE_LEAK is not set # CONFIG_RT_DEBUGING_SPINLOCK is not set # CONFIG_RT_DEBUGING_CRITICAL is not set +CONFIG_RT_USING_OVERFLOW_CHECK=y # # Inter-Thread communication @@ -103,6 +105,8 @@ CONFIG_ARCH_RAM_OFFSET=0x80000000 CONFIG_ARCH_SECONDARY_CPU_STACK_SIZE=4096 CONFIG_ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS=y # CONFIG_ARCH_USING_GENERIC_CPUID is not set +CONFIG_ARCH_HEAP_SIZE=0x4000000 +CONFIG_ARCH_INIT_PAGE_SIZE=0x200000 # end of AArch64 Architecture Configuration CONFIG_ARCH_CPU_64BIT=y @@ -193,6 +197,7 @@ CONFIG_RT_USING_DFS_RAMFS=y # Device Drivers # # CONFIG_RT_USING_DM is not set +CONFIG_RT_USING_DEV_BUS=y CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_UNAMED_PIPE_NUMBER=64 CONFIG_RT_USING_SYSTEM_WORKQUEUE=y @@ -219,6 +224,8 @@ CONFIG_RT_USING_NULL=y CONFIG_RT_USING_ZERO=y CONFIG_RT_USING_RANDOM=y CONFIG_RT_USING_PWM=y +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set # CONFIG_RT_USING_PM is not set @@ -245,21 +252,12 @@ CONFIG_RT_USING_QSPI=y # CONFIG_RT_USING_TOUCH is not set # CONFIG_RT_USING_LCD is not set # CONFIG_RT_USING_HWCRYPTO is not set -# CONFIG_RT_USING_PULSE_ENCODER is not set -# CONFIG_RT_USING_INPUT_CAPTURE is not set -CONFIG_RT_USING_DEV_BUS=y # CONFIG_RT_USING_WIFI is not set # CONFIG_RT_USING_VIRTIO is not set CONFIG_RT_USING_PIN=y CONFIG_RT_USING_KTIME=y # CONFIG_RT_USING_HWTIMER is not set - -# -# Using USB -# -# CONFIG_RT_USING_USB_HOST is not set -# CONFIG_RT_USING_USB_DEVICE is not set -# end of Using USB +# CONFIG_RT_USING_CHERRYUSB is not set # end of Device Drivers # @@ -428,6 +426,15 @@ CONFIG_RT_USING_ADT_REF=y # end of Utilities # CONFIG_RT_USING_VBUS is not set + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set # end of RT-Thread Components # @@ -1347,10 +1354,10 @@ CONFIG_RT_USING_UART1=y # CONFIG_RT_USING_UART2 is not set # CONFIG_RT_USING_UART3 is not set CONFIG_BSP_USING_SPI=y -CONFIG_RT_USING_SPIM0=y -CONFIG_RT_USING_SPIM1=y +# CONFIG_RT_USING_SPIM0 is not set +# CONFIG_RT_USING_SPIM1 is not set CONFIG_RT_USING_SPIM2=y -CONFIG_RT_USING_SPIM3=y +# CONFIG_RT_USING_SPIM3 is not set CONFIG_BSP_USING_CAN=y CONFIG_RT_USING_CANFD=y # CONFIG_RT_USING_FILTER is not set @@ -1400,7 +1407,7 @@ CONFIG_USING_SDIF1=y CONFIG_USE_SDIF1_TF=y # CONFIG_USE_SDIF1_EMMC is not set CONFIG_BSP_USING_DC=y -# CONFIG_RT_USING_DC_CHANNEL0 is not set +CONFIG_RT_USING_DC_CHANNEL0=y CONFIG_RT_USING_DC_CHANNEL1=y # CONFIG_BSP_USING_XHCI is not set # CONFIG_BSP_USING_PUSB2 is not set @@ -1414,7 +1421,7 @@ CONFIG_RT_USING_DC_CHANNEL1=y CONFIG_BSP_USING_GIC=y CONFIG_BSP_USING_GICV3=y CONFIG_PHYTIUM_ARCH_AARCH64=y -CONFIG_ARM_SPI_BIND_CPU_ID=0 +CONFIG_ARM_SPI_BIND_CPU_ID=2 # # Standalone Setting @@ -1425,15 +1432,15 @@ CONFIG_TARGET_ARMV8_AARCH64=y # Soc configuration # # CONFIG_TARGET_PHYTIUMPI is not set -# CONFIG_TARGET_E2000Q is not set -CONFIG_TARGET_E2000D=y +CONFIG_TARGET_E2000Q=y +# CONFIG_TARGET_E2000D is not set # CONFIG_TARGET_E2000S is not set # CONFIG_TARGET_FT2004 is not set # CONFIG_TARGET_D2000 is not set # CONFIG_TARGET_PD2308 is not set CONFIG_SOC_NAME="e2000" -CONFIG_TARGET_TYPE_NAME="d" -CONFIG_SOC_CORE_NUM=2 +CONFIG_TARGET_TYPE_NAME="q" +CONFIG_SOC_CORE_NUM=4 CONFIG_F32BIT_MEMORY_ADDRESS=0x80000000 CONFIG_F32BIT_MEMORY_LENGTH=0x80000000 CONFIG_F64BIT_MEMORY_ADDRESS=0x2000000000 @@ -1447,22 +1454,21 @@ CONFIG_DEFAULT_DEBUG_PRINT_UART1=y # # Board Configuration # -CONFIG_E2000D_DEMO_BOARD=y CONFIG_BOARD_NAME="demo" - -# -# IO mux configuration when board start up -# # CONFIG_USE_SPI_IOPAD is not set # CONFIG_USE_GPIO_IOPAD is not set # CONFIG_USE_CAN_IOPAD is not set # CONFIG_USE_QSPI_IOPAD is not set # CONFIG_USE_PWM_IOPAD is not set -# CONFIG_USE_ADC_IOPAD is not set # CONFIG_USE_MIO_IOPAD is not set # CONFIG_USE_TACHO_IOPAD is not set # CONFIG_USE_UART_IOPAD is not set # CONFIG_USE_THIRD_PARTY_IOPAD is not set +CONFIG_E2000Q_DEMO_BOARD=y + +# +# IO mux configuration when board start up +# # end of IO mux configuration when board start up # CONFIG_CUS_DEMO_BOARD is not set @@ -1483,10 +1489,4 @@ CONFIG_LOG_DEBUG=y # CONFIG_BOOTUP_DEBUG_PRINTS is not set # CONFIG_USE_DEFAULT_INTERRUPT_CONFIG is not set # end of Sdk common configuration - -# -# Image information configuration -# -# CONFIG_IMAGE_INFO is not set -# end of Image information configuration # end of Standalone Setting diff --git a/bsp/phytium/aarch64/Kconfig b/bsp/phytium/aarch64/Kconfig index 4d38c63220..a3b99c57f2 100644 --- a/bsp/phytium/aarch64/Kconfig +++ b/bsp/phytium/aarch64/Kconfig @@ -2,8 +2,6 @@ mainmenu "RT-Thread Project Configuration" RTT_DIR := ../../.. -BSP_DIR := ../. - SDK_DIR:= .././libraries/phytium_standalone_sdk PKGS_DIR := packages diff --git a/bsp/phytium/aarch64/applications/main.c b/bsp/phytium/aarch64/applications/main.c index 9c05d8d070..f40e5d85e0 100644 --- a/bsp/phytium/aarch64/applications/main.c +++ b/bsp/phytium/aarch64/applications/main.c @@ -55,7 +55,7 @@ static void demo_core_thread(void *parameter) level = rt_cpus_lock(); rt_kprintf("Hi, core%d \r\n", rt_hw_cpu_id()); rt_cpus_unlock(level); - rt_thread_mdelay(200000); + rt_thread_mdelay(20000); } } @@ -71,7 +71,7 @@ void demo_core(void) demo_core_thread, RT_NULL, &core_stack[i], - 4096, + 2048, 20, 32); diff --git a/bsp/phytium/aarch64/configs/e2000d_demo_rtsmart b/bsp/phytium/aarch64/configs/e2000d_demo_rtsmart index 104f6bb118..0bd1c0648d 100644 --- a/bsp/phytium/aarch64/configs/e2000d_demo_rtsmart +++ b/bsp/phytium/aarch64/configs/e2000d_demo_rtsmart @@ -15,7 +15,6 @@ CONFIG_RT_THREAD_PRIORITY_32=y # CONFIG_RT_THREAD_PRIORITY_256 is not set CONFIG_RT_THREAD_PRIORITY_MAX=32 CONFIG_RT_TICK_PER_SECOND=1000 -CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y CONFIG_RT_HOOK_USING_FUNC_PTR=y # CONFIG_RT_USING_HOOKLIST is not set @@ -26,6 +25,8 @@ CONFIG_SYSTEM_THREAD_STACK_SIZE=8192 CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 CONFIG_RT_TIMER_THREAD_STACK_SIZE=8192 +# CONFIG_RT_USING_TIMER_ALL_SOFT is not set +CONFIG_RT_USING_CPU_USAGE_TRACER=y # # kservice optimization @@ -49,6 +50,7 @@ CONFIG_RT_DEBUGING_CONTEXT=y # CONFIG_RT_DEBUGING_PAGE_LEAK is not set # CONFIG_RT_DEBUGING_SPINLOCK is not set CONFIG_RT_DEBUGING_CRITICAL=y +CONFIG_RT_USING_OVERFLOW_CHECK=y # # Inter-Thread communication @@ -103,6 +105,8 @@ CONFIG_ARCH_RAM_OFFSET=0x80000000 CONFIG_ARCH_SECONDARY_CPU_STACK_SIZE=4096 CONFIG_ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS=y # CONFIG_ARCH_USING_GENERIC_CPUID is not set +CONFIG_ARCH_HEAP_SIZE=0x4000000 +CONFIG_ARCH_INIT_PAGE_SIZE=0x200000 # end of AArch64 Architecture Configuration CONFIG_ARCH_CPU_64BIT=y @@ -201,6 +205,7 @@ CONFIG_RT_PAGECACHE_GC_STOP_LEVEL=70 # Device Drivers # # CONFIG_RT_USING_DM is not set +CONFIG_RT_USING_DEV_BUS=y CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_UNAMED_PIPE_NUMBER=64 CONFIG_RT_USING_SYSTEM_WORKQUEUE=y @@ -227,6 +232,8 @@ CONFIG_RT_USING_NULL=y CONFIG_RT_USING_ZERO=y CONFIG_RT_USING_RANDOM=y CONFIG_RT_USING_PWM=y +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set # CONFIG_RT_USING_PM is not set @@ -253,21 +260,12 @@ CONFIG_RT_USING_QSPI=y # CONFIG_RT_USING_TOUCH is not set # CONFIG_RT_USING_LCD is not set # CONFIG_RT_USING_HWCRYPTO is not set -# CONFIG_RT_USING_PULSE_ENCODER is not set -# CONFIG_RT_USING_INPUT_CAPTURE is not set -CONFIG_RT_USING_DEV_BUS=y # CONFIG_RT_USING_WIFI is not set # CONFIG_RT_USING_VIRTIO is not set CONFIG_RT_USING_PIN=y CONFIG_RT_USING_KTIME=y # CONFIG_RT_USING_HWTIMER is not set - -# -# Using USB -# -# CONFIG_RT_USING_USB_HOST is not set -# CONFIG_RT_USING_USB_DEVICE is not set -# end of Using USB +# CONFIG_RT_USING_CHERRYUSB is not set # end of Device Drivers # @@ -486,6 +484,15 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64 # # CONFIG_RT_USING_MEMBLOCK is not set # end of Memory management + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set # end of RT-Thread Components # @@ -1405,10 +1412,10 @@ CONFIG_RT_USING_UART1=y # CONFIG_RT_USING_UART2 is not set # CONFIG_RT_USING_UART3 is not set CONFIG_BSP_USING_SPI=y -CONFIG_RT_USING_SPIM0=y -CONFIG_RT_USING_SPIM1=y +# CONFIG_RT_USING_SPIM0 is not set +# CONFIG_RT_USING_SPIM1 is not set CONFIG_RT_USING_SPIM2=y -CONFIG_RT_USING_SPIM3=y +# CONFIG_RT_USING_SPIM3 is not set CONFIG_BSP_USING_CAN=y CONFIG_RT_USING_CANFD=y # CONFIG_RT_USING_FILTER is not set @@ -1458,7 +1465,7 @@ CONFIG_USING_SDIF1=y CONFIG_USE_SDIF1_TF=y # CONFIG_USE_SDIF1_EMMC is not set CONFIG_BSP_USING_DC=y -# CONFIG_RT_USING_DC_CHANNEL0 is not set +CONFIG_RT_USING_DC_CHANNEL0=y CONFIG_RT_USING_DC_CHANNEL1=y # CONFIG_BSP_USING_XHCI is not set # CONFIG_BSP_USING_PUSB2 is not set @@ -1541,10 +1548,4 @@ CONFIG_LOG_DEBUG=y # CONFIG_BOOTUP_DEBUG_PRINTS is not set # CONFIG_USE_DEFAULT_INTERRUPT_CONFIG is not set # end of Sdk common configuration - -# -# Image information configuration -# -# CONFIG_IMAGE_INFO is not set -# end of Image information configuration # end of Standalone Setting diff --git a/bsp/phytium/aarch64/configs/e2000d_demo_rtsmart.h b/bsp/phytium/aarch64/configs/e2000d_demo_rtsmart.h index 381281719a..cabf108fe6 100644 --- a/bsp/phytium/aarch64/configs/e2000d_demo_rtsmart.h +++ b/bsp/phytium/aarch64/configs/e2000d_demo_rtsmart.h @@ -11,7 +11,6 @@ #define RT_THREAD_PRIORITY_32 #define RT_THREAD_PRIORITY_MAX 32 #define RT_TICK_PER_SECOND 1000 -#define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK @@ -21,6 +20,7 @@ #define RT_USING_TIMER_SOFT #define RT_TIMER_THREAD_PRIO 4 #define RT_TIMER_THREAD_STACK_SIZE 8192 +#define RT_USING_CPU_USAGE_TRACER /* kservice optimization */ @@ -35,6 +35,7 @@ #define RT_DEBUGING_COLOR #define RT_DEBUGING_CONTEXT #define RT_DEBUGING_CRITICAL +#define RT_USING_OVERFLOW_CHECK /* Inter-Thread communication */ @@ -73,6 +74,8 @@ #define ARCH_RAM_OFFSET 0x80000000 #define ARCH_SECONDARY_CPU_STACK_SIZE 4096 #define ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS +#define ARCH_HEAP_SIZE 0x4000000 +#define ARCH_INIT_PAGE_SIZE 0x200000 /* end of AArch64 Architecture Configuration */ #define ARCH_CPU_64BIT #define RT_USING_CACHE @@ -146,6 +149,7 @@ /* Device Drivers */ +#define RT_USING_DEV_BUS #define RT_USING_DEVICE_IPC #define RT_UNAMED_PIPE_NUMBER 64 #define RT_USING_SYSTEM_WORKQUEUE @@ -173,13 +177,8 @@ #define RT_MMCSD_MAX_PARTITION 16 #define RT_USING_SPI #define RT_USING_QSPI -#define RT_USING_DEV_BUS #define RT_USING_PIN #define RT_USING_KTIME - -/* Using USB */ - -/* end of Using USB */ /* end of Device Drivers */ /* C/C++ and POSIX layer */ @@ -310,6 +309,10 @@ /* Memory management */ /* end of Memory management */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ /* end of RT-Thread Components */ /* RT-Thread Utestcases */ @@ -502,10 +505,7 @@ #define RT_USING_UART0 #define RT_USING_UART1 #define BSP_USING_SPI -#define RT_USING_SPIM0 -#define RT_USING_SPIM1 #define RT_USING_SPIM2 -#define RT_USING_SPIM3 #define BSP_USING_CAN #define RT_USING_CANFD #define RT_USING_CAN0 @@ -528,6 +528,7 @@ #define USING_SDIF1 #define USE_SDIF1_TF #define BSP_USING_DC +#define RT_USING_DC_CHANNEL0 #define RT_USING_DC_CHANNEL1 /* end of On-chip Peripheral Drivers */ @@ -572,10 +573,6 @@ #define ELOG_LINE_BUF_SIZE 0x100 #define LOG_DEBUG /* end of Sdk common configuration */ - -/* Image information configuration */ - -/* end of Image information configuration */ /* end of Standalone Setting */ #endif diff --git a/bsp/phytium/aarch64/configs/e2000d_demo_rtthread b/bsp/phytium/aarch64/configs/e2000d_demo_rtthread index 08c232fd9b..d88f8fc29b 100644 --- a/bsp/phytium/aarch64/configs/e2000d_demo_rtthread +++ b/bsp/phytium/aarch64/configs/e2000d_demo_rtthread @@ -15,7 +15,6 @@ CONFIG_RT_THREAD_PRIORITY_32=y # CONFIG_RT_THREAD_PRIORITY_256 is not set CONFIG_RT_THREAD_PRIORITY_MAX=32 CONFIG_RT_TICK_PER_SECOND=1000 -CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y CONFIG_RT_HOOK_USING_FUNC_PTR=y # CONFIG_RT_USING_HOOKLIST is not set @@ -26,6 +25,8 @@ CONFIG_SYSTEM_THREAD_STACK_SIZE=8192 CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 CONFIG_RT_TIMER_THREAD_STACK_SIZE=8192 +# CONFIG_RT_USING_TIMER_ALL_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set # # kservice optimization @@ -49,6 +50,7 @@ CONFIG_RT_DEBUGING_COLOR=y # CONFIG_RT_DEBUGING_PAGE_LEAK is not set # CONFIG_RT_DEBUGING_SPINLOCK is not set # CONFIG_RT_DEBUGING_CRITICAL is not set +CONFIG_RT_USING_OVERFLOW_CHECK=y # # Inter-Thread communication @@ -103,6 +105,8 @@ CONFIG_ARCH_RAM_OFFSET=0x80000000 CONFIG_ARCH_SECONDARY_CPU_STACK_SIZE=4096 CONFIG_ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS=y # CONFIG_ARCH_USING_GENERIC_CPUID is not set +CONFIG_ARCH_HEAP_SIZE=0x4000000 +CONFIG_ARCH_INIT_PAGE_SIZE=0x200000 # end of AArch64 Architecture Configuration CONFIG_ARCH_CPU_64BIT=y @@ -193,6 +197,7 @@ CONFIG_RT_USING_DFS_RAMFS=y # Device Drivers # # CONFIG_RT_USING_DM is not set +CONFIG_RT_USING_DEV_BUS=y CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_UNAMED_PIPE_NUMBER=64 CONFIG_RT_USING_SYSTEM_WORKQUEUE=y @@ -219,6 +224,8 @@ CONFIG_RT_USING_NULL=y CONFIG_RT_USING_ZERO=y CONFIG_RT_USING_RANDOM=y CONFIG_RT_USING_PWM=y +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set # CONFIG_RT_USING_PM is not set @@ -245,21 +252,12 @@ CONFIG_RT_USING_QSPI=y # CONFIG_RT_USING_TOUCH is not set # CONFIG_RT_USING_LCD is not set # CONFIG_RT_USING_HWCRYPTO is not set -# CONFIG_RT_USING_PULSE_ENCODER is not set -# CONFIG_RT_USING_INPUT_CAPTURE is not set -CONFIG_RT_USING_DEV_BUS=y # CONFIG_RT_USING_WIFI is not set # CONFIG_RT_USING_VIRTIO is not set CONFIG_RT_USING_PIN=y CONFIG_RT_USING_KTIME=y # CONFIG_RT_USING_HWTIMER is not set - -# -# Using USB -# -# CONFIG_RT_USING_USB_HOST is not set -# CONFIG_RT_USING_USB_DEVICE is not set -# end of Using USB +# CONFIG_RT_USING_CHERRYUSB is not set # end of Device Drivers # @@ -428,6 +426,15 @@ CONFIG_RT_USING_ADT_REF=y # end of Utilities # CONFIG_RT_USING_VBUS is not set + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set # end of RT-Thread Components # @@ -1347,10 +1354,10 @@ CONFIG_RT_USING_UART1=y # CONFIG_RT_USING_UART2 is not set # CONFIG_RT_USING_UART3 is not set CONFIG_BSP_USING_SPI=y -CONFIG_RT_USING_SPIM0=y -CONFIG_RT_USING_SPIM1=y +# CONFIG_RT_USING_SPIM0 is not set +# CONFIG_RT_USING_SPIM1 is not set CONFIG_RT_USING_SPIM2=y -CONFIG_RT_USING_SPIM3=y +# CONFIG_RT_USING_SPIM3 is not set CONFIG_BSP_USING_CAN=y CONFIG_RT_USING_CANFD=y # CONFIG_RT_USING_FILTER is not set @@ -1400,7 +1407,7 @@ CONFIG_USING_SDIF1=y CONFIG_USE_SDIF1_TF=y # CONFIG_USE_SDIF1_EMMC is not set CONFIG_BSP_USING_DC=y -# CONFIG_RT_USING_DC_CHANNEL0 is not set +CONFIG_RT_USING_DC_CHANNEL0=y CONFIG_RT_USING_DC_CHANNEL1=y # CONFIG_BSP_USING_XHCI is not set # CONFIG_BSP_USING_PUSB2 is not set @@ -1483,10 +1490,4 @@ CONFIG_LOG_DEBUG=y # CONFIG_BOOTUP_DEBUG_PRINTS is not set # CONFIG_USE_DEFAULT_INTERRUPT_CONFIG is not set # end of Sdk common configuration - -# -# Image information configuration -# -# CONFIG_IMAGE_INFO is not set -# end of Image information configuration # end of Standalone Setting diff --git a/bsp/phytium/aarch64/configs/e2000d_demo_rtthread.h b/bsp/phytium/aarch64/configs/e2000d_demo_rtthread.h index 98e7776c04..449f76a2fe 100644 --- a/bsp/phytium/aarch64/configs/e2000d_demo_rtthread.h +++ b/bsp/phytium/aarch64/configs/e2000d_demo_rtthread.h @@ -10,7 +10,6 @@ #define RT_THREAD_PRIORITY_32 #define RT_THREAD_PRIORITY_MAX 32 #define RT_TICK_PER_SECOND 1000 -#define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK @@ -32,6 +31,7 @@ #define RT_USING_DEBUG #define RT_DEBUGING_ASSERT #define RT_DEBUGING_COLOR +#define RT_USING_OVERFLOW_CHECK /* Inter-Thread communication */ @@ -68,6 +68,8 @@ #define ARCH_RAM_OFFSET 0x80000000 #define ARCH_SECONDARY_CPU_STACK_SIZE 4096 #define ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS +#define ARCH_HEAP_SIZE 0x4000000 +#define ARCH_INIT_PAGE_SIZE 0x200000 /* end of AArch64 Architecture Configuration */ #define ARCH_CPU_64BIT #define RT_USING_CACHE @@ -131,6 +133,7 @@ /* Device Drivers */ +#define RT_USING_DEV_BUS #define RT_USING_DEVICE_IPC #define RT_UNAMED_PIPE_NUMBER 64 #define RT_USING_SYSTEM_WORKQUEUE @@ -158,13 +161,8 @@ #define RT_MMCSD_MAX_PARTITION 16 #define RT_USING_SPI #define RT_USING_QSPI -#define RT_USING_DEV_BUS #define RT_USING_PIN #define RT_USING_KTIME - -/* Using USB */ - -/* end of Using USB */ /* end of Device Drivers */ /* C/C++ and POSIX layer */ @@ -275,6 +273,10 @@ #define RT_USING_ADT_HASHMAP #define RT_USING_ADT_REF /* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ /* end of RT-Thread Components */ /* RT-Thread Utestcases */ @@ -467,10 +469,7 @@ #define RT_USING_UART0 #define RT_USING_UART1 #define BSP_USING_SPI -#define RT_USING_SPIM0 -#define RT_USING_SPIM1 #define RT_USING_SPIM2 -#define RT_USING_SPIM3 #define BSP_USING_CAN #define RT_USING_CANFD #define RT_USING_CAN0 @@ -493,6 +492,7 @@ #define USING_SDIF1 #define USE_SDIF1_TF #define BSP_USING_DC +#define RT_USING_DC_CHANNEL0 #define RT_USING_DC_CHANNEL1 /* end of On-chip Peripheral Drivers */ @@ -537,10 +537,6 @@ #define ELOG_LINE_BUF_SIZE 0x100 #define LOG_DEBUG /* end of Sdk common configuration */ - -/* Image information configuration */ - -/* end of Image information configuration */ /* end of Standalone Setting */ #endif diff --git a/bsp/phytium/aarch64/configs/e2000q_demo_rtsmart b/bsp/phytium/aarch64/configs/e2000q_demo_rtsmart index c1cd28a913..e03162e57e 100644 --- a/bsp/phytium/aarch64/configs/e2000q_demo_rtsmart +++ b/bsp/phytium/aarch64/configs/e2000q_demo_rtsmart @@ -15,7 +15,6 @@ CONFIG_RT_THREAD_PRIORITY_32=y # CONFIG_RT_THREAD_PRIORITY_256 is not set CONFIG_RT_THREAD_PRIORITY_MAX=32 CONFIG_RT_TICK_PER_SECOND=1000 -CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y CONFIG_RT_HOOK_USING_FUNC_PTR=y # CONFIG_RT_USING_HOOKLIST is not set @@ -26,6 +25,8 @@ CONFIG_SYSTEM_THREAD_STACK_SIZE=8192 CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 CONFIG_RT_TIMER_THREAD_STACK_SIZE=8192 +# CONFIG_RT_USING_TIMER_ALL_SOFT is not set +CONFIG_RT_USING_CPU_USAGE_TRACER=y # # kservice optimization @@ -49,6 +50,7 @@ CONFIG_RT_DEBUGING_CONTEXT=y # CONFIG_RT_DEBUGING_PAGE_LEAK is not set # CONFIG_RT_DEBUGING_SPINLOCK is not set CONFIG_RT_DEBUGING_CRITICAL=y +CONFIG_RT_USING_OVERFLOW_CHECK=y # # Inter-Thread communication @@ -103,6 +105,8 @@ CONFIG_ARCH_RAM_OFFSET=0x80000000 CONFIG_ARCH_SECONDARY_CPU_STACK_SIZE=4096 CONFIG_ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS=y # CONFIG_ARCH_USING_GENERIC_CPUID is not set +CONFIG_ARCH_HEAP_SIZE=0x4000000 +CONFIG_ARCH_INIT_PAGE_SIZE=0x200000 # end of AArch64 Architecture Configuration CONFIG_ARCH_CPU_64BIT=y @@ -201,6 +205,7 @@ CONFIG_RT_PAGECACHE_GC_STOP_LEVEL=70 # Device Drivers # # CONFIG_RT_USING_DM is not set +CONFIG_RT_USING_DEV_BUS=y CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_UNAMED_PIPE_NUMBER=64 CONFIG_RT_USING_SYSTEM_WORKQUEUE=y @@ -227,6 +232,8 @@ CONFIG_RT_USING_NULL=y CONFIG_RT_USING_ZERO=y CONFIG_RT_USING_RANDOM=y CONFIG_RT_USING_PWM=y +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set # CONFIG_RT_USING_PM is not set @@ -253,21 +260,12 @@ CONFIG_RT_USING_QSPI=y # CONFIG_RT_USING_TOUCH is not set # CONFIG_RT_USING_LCD is not set # CONFIG_RT_USING_HWCRYPTO is not set -# CONFIG_RT_USING_PULSE_ENCODER is not set -# CONFIG_RT_USING_INPUT_CAPTURE is not set -CONFIG_RT_USING_DEV_BUS=y # CONFIG_RT_USING_WIFI is not set # CONFIG_RT_USING_VIRTIO is not set CONFIG_RT_USING_PIN=y CONFIG_RT_USING_KTIME=y # CONFIG_RT_USING_HWTIMER is not set - -# -# Using USB -# -# CONFIG_RT_USING_USB_HOST is not set -# CONFIG_RT_USING_USB_DEVICE is not set -# end of Using USB +# CONFIG_RT_USING_CHERRYUSB is not set # end of Device Drivers # @@ -486,6 +484,15 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64 # # CONFIG_RT_USING_MEMBLOCK is not set # end of Memory management + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set # end of RT-Thread Components # @@ -1405,10 +1412,10 @@ CONFIG_RT_USING_UART1=y # CONFIG_RT_USING_UART2 is not set # CONFIG_RT_USING_UART3 is not set CONFIG_BSP_USING_SPI=y -CONFIG_RT_USING_SPIM0=y -CONFIG_RT_USING_SPIM1=y +# CONFIG_RT_USING_SPIM0 is not set +# CONFIG_RT_USING_SPIM1 is not set CONFIG_RT_USING_SPIM2=y -CONFIG_RT_USING_SPIM3=y +# CONFIG_RT_USING_SPIM3 is not set CONFIG_BSP_USING_CAN=y CONFIG_RT_USING_CANFD=y # CONFIG_RT_USING_FILTER is not set @@ -1458,7 +1465,7 @@ CONFIG_USING_SDIF1=y CONFIG_USE_SDIF1_TF=y # CONFIG_USE_SDIF1_EMMC is not set CONFIG_BSP_USING_DC=y -# CONFIG_RT_USING_DC_CHANNEL0 is not set +CONFIG_RT_USING_DC_CHANNEL0=y CONFIG_RT_USING_DC_CHANNEL1=y # CONFIG_BSP_USING_XHCI is not set # CONFIG_BSP_USING_PUSB2 is not set @@ -1540,10 +1547,4 @@ CONFIG_LOG_DEBUG=y # CONFIG_BOOTUP_DEBUG_PRINTS is not set # CONFIG_USE_DEFAULT_INTERRUPT_CONFIG is not set # end of Sdk common configuration - -# -# Image information configuration -# -# CONFIG_IMAGE_INFO is not set -# end of Image information configuration # end of Standalone Setting diff --git a/bsp/phytium/aarch64/configs/e2000q_demo_rtsmart.h b/bsp/phytium/aarch64/configs/e2000q_demo_rtsmart.h index 6d18b3fa0d..2fd3830b28 100644 --- a/bsp/phytium/aarch64/configs/e2000q_demo_rtsmart.h +++ b/bsp/phytium/aarch64/configs/e2000q_demo_rtsmart.h @@ -11,7 +11,6 @@ #define RT_THREAD_PRIORITY_32 #define RT_THREAD_PRIORITY_MAX 32 #define RT_TICK_PER_SECOND 1000 -#define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK @@ -21,6 +20,7 @@ #define RT_USING_TIMER_SOFT #define RT_TIMER_THREAD_PRIO 4 #define RT_TIMER_THREAD_STACK_SIZE 8192 +#define RT_USING_CPU_USAGE_TRACER /* kservice optimization */ @@ -35,6 +35,7 @@ #define RT_DEBUGING_COLOR #define RT_DEBUGING_CONTEXT #define RT_DEBUGING_CRITICAL +#define RT_USING_OVERFLOW_CHECK /* Inter-Thread communication */ @@ -73,6 +74,8 @@ #define ARCH_RAM_OFFSET 0x80000000 #define ARCH_SECONDARY_CPU_STACK_SIZE 4096 #define ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS +#define ARCH_HEAP_SIZE 0x4000000 +#define ARCH_INIT_PAGE_SIZE 0x200000 /* end of AArch64 Architecture Configuration */ #define ARCH_CPU_64BIT #define RT_USING_CACHE @@ -146,6 +149,7 @@ /* Device Drivers */ +#define RT_USING_DEV_BUS #define RT_USING_DEVICE_IPC #define RT_UNAMED_PIPE_NUMBER 64 #define RT_USING_SYSTEM_WORKQUEUE @@ -173,13 +177,8 @@ #define RT_MMCSD_MAX_PARTITION 16 #define RT_USING_SPI #define RT_USING_QSPI -#define RT_USING_DEV_BUS #define RT_USING_PIN #define RT_USING_KTIME - -/* Using USB */ - -/* end of Using USB */ /* end of Device Drivers */ /* C/C++ and POSIX layer */ @@ -310,6 +309,10 @@ /* Memory management */ /* end of Memory management */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ /* end of RT-Thread Components */ /* RT-Thread Utestcases */ @@ -502,10 +505,7 @@ #define RT_USING_UART0 #define RT_USING_UART1 #define BSP_USING_SPI -#define RT_USING_SPIM0 -#define RT_USING_SPIM1 #define RT_USING_SPIM2 -#define RT_USING_SPIM3 #define BSP_USING_CAN #define RT_USING_CANFD #define RT_USING_CAN0 @@ -528,6 +528,7 @@ #define USING_SDIF1 #define USE_SDIF1_TF #define BSP_USING_DC +#define RT_USING_DC_CHANNEL0 #define RT_USING_DC_CHANNEL1 /* end of On-chip Peripheral Drivers */ @@ -572,10 +573,6 @@ #define ELOG_LINE_BUF_SIZE 0x100 #define LOG_DEBUG /* end of Sdk common configuration */ - -/* Image information configuration */ - -/* end of Image information configuration */ /* end of Standalone Setting */ #endif diff --git a/bsp/phytium/aarch64/configs/e2000q_demo_rtthread b/bsp/phytium/aarch64/configs/e2000q_demo_rtthread index 4211fbc333..3dea5ae400 100644 --- a/bsp/phytium/aarch64/configs/e2000q_demo_rtthread +++ b/bsp/phytium/aarch64/configs/e2000q_demo_rtthread @@ -15,7 +15,6 @@ CONFIG_RT_THREAD_PRIORITY_32=y # CONFIG_RT_THREAD_PRIORITY_256 is not set CONFIG_RT_THREAD_PRIORITY_MAX=32 CONFIG_RT_TICK_PER_SECOND=1000 -CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y CONFIG_RT_HOOK_USING_FUNC_PTR=y # CONFIG_RT_USING_HOOKLIST is not set @@ -26,6 +25,8 @@ CONFIG_SYSTEM_THREAD_STACK_SIZE=8192 CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 CONFIG_RT_TIMER_THREAD_STACK_SIZE=8192 +# CONFIG_RT_USING_TIMER_ALL_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set # # kservice optimization @@ -49,6 +50,7 @@ CONFIG_RT_DEBUGING_COLOR=y # CONFIG_RT_DEBUGING_PAGE_LEAK is not set # CONFIG_RT_DEBUGING_SPINLOCK is not set # CONFIG_RT_DEBUGING_CRITICAL is not set +CONFIG_RT_USING_OVERFLOW_CHECK=y # # Inter-Thread communication @@ -103,6 +105,8 @@ CONFIG_ARCH_RAM_OFFSET=0x80000000 CONFIG_ARCH_SECONDARY_CPU_STACK_SIZE=4096 CONFIG_ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS=y # CONFIG_ARCH_USING_GENERIC_CPUID is not set +CONFIG_ARCH_HEAP_SIZE=0x4000000 +CONFIG_ARCH_INIT_PAGE_SIZE=0x200000 # end of AArch64 Architecture Configuration CONFIG_ARCH_CPU_64BIT=y @@ -193,6 +197,7 @@ CONFIG_RT_USING_DFS_RAMFS=y # Device Drivers # # CONFIG_RT_USING_DM is not set +CONFIG_RT_USING_DEV_BUS=y CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_UNAMED_PIPE_NUMBER=64 CONFIG_RT_USING_SYSTEM_WORKQUEUE=y @@ -219,6 +224,8 @@ CONFIG_RT_USING_NULL=y CONFIG_RT_USING_ZERO=y CONFIG_RT_USING_RANDOM=y CONFIG_RT_USING_PWM=y +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set # CONFIG_RT_USING_PM is not set @@ -245,21 +252,12 @@ CONFIG_RT_USING_QSPI=y # CONFIG_RT_USING_TOUCH is not set # CONFIG_RT_USING_LCD is not set # CONFIG_RT_USING_HWCRYPTO is not set -# CONFIG_RT_USING_PULSE_ENCODER is not set -# CONFIG_RT_USING_INPUT_CAPTURE is not set -CONFIG_RT_USING_DEV_BUS=y # CONFIG_RT_USING_WIFI is not set # CONFIG_RT_USING_VIRTIO is not set CONFIG_RT_USING_PIN=y CONFIG_RT_USING_KTIME=y # CONFIG_RT_USING_HWTIMER is not set - -# -# Using USB -# -# CONFIG_RT_USING_USB_HOST is not set -# CONFIG_RT_USING_USB_DEVICE is not set -# end of Using USB +# CONFIG_RT_USING_CHERRYUSB is not set # end of Device Drivers # @@ -428,6 +426,15 @@ CONFIG_RT_USING_ADT_REF=y # end of Utilities # CONFIG_RT_USING_VBUS is not set + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set # end of RT-Thread Components # @@ -1347,10 +1354,10 @@ CONFIG_RT_USING_UART1=y # CONFIG_RT_USING_UART2 is not set # CONFIG_RT_USING_UART3 is not set CONFIG_BSP_USING_SPI=y -CONFIG_RT_USING_SPIM0=y -CONFIG_RT_USING_SPIM1=y +# CONFIG_RT_USING_SPIM0 is not set +# CONFIG_RT_USING_SPIM1 is not set CONFIG_RT_USING_SPIM2=y -CONFIG_RT_USING_SPIM3=y +# CONFIG_RT_USING_SPIM3 is not set CONFIG_BSP_USING_CAN=y CONFIG_RT_USING_CANFD=y # CONFIG_RT_USING_FILTER is not set @@ -1400,7 +1407,7 @@ CONFIG_USING_SDIF1=y CONFIG_USE_SDIF1_TF=y # CONFIG_USE_SDIF1_EMMC is not set CONFIG_BSP_USING_DC=y -# CONFIG_RT_USING_DC_CHANNEL0 is not set +CONFIG_RT_USING_DC_CHANNEL0=y CONFIG_RT_USING_DC_CHANNEL1=y # CONFIG_BSP_USING_XHCI is not set # CONFIG_BSP_USING_PUSB2 is not set @@ -1482,10 +1489,4 @@ CONFIG_LOG_DEBUG=y # CONFIG_BOOTUP_DEBUG_PRINTS is not set # CONFIG_USE_DEFAULT_INTERRUPT_CONFIG is not set # end of Sdk common configuration - -# -# Image information configuration -# -# CONFIG_IMAGE_INFO is not set -# end of Image information configuration # end of Standalone Setting diff --git a/bsp/phytium/aarch64/configs/e2000q_demo_rtthread.h b/bsp/phytium/aarch64/configs/e2000q_demo_rtthread.h index 757e69ae63..92823621a2 100644 --- a/bsp/phytium/aarch64/configs/e2000q_demo_rtthread.h +++ b/bsp/phytium/aarch64/configs/e2000q_demo_rtthread.h @@ -10,7 +10,6 @@ #define RT_THREAD_PRIORITY_32 #define RT_THREAD_PRIORITY_MAX 32 #define RT_TICK_PER_SECOND 1000 -#define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK @@ -32,6 +31,7 @@ #define RT_USING_DEBUG #define RT_DEBUGING_ASSERT #define RT_DEBUGING_COLOR +#define RT_USING_OVERFLOW_CHECK /* Inter-Thread communication */ @@ -68,6 +68,8 @@ #define ARCH_RAM_OFFSET 0x80000000 #define ARCH_SECONDARY_CPU_STACK_SIZE 4096 #define ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS +#define ARCH_HEAP_SIZE 0x4000000 +#define ARCH_INIT_PAGE_SIZE 0x200000 /* end of AArch64 Architecture Configuration */ #define ARCH_CPU_64BIT #define RT_USING_CACHE @@ -131,6 +133,7 @@ /* Device Drivers */ +#define RT_USING_DEV_BUS #define RT_USING_DEVICE_IPC #define RT_UNAMED_PIPE_NUMBER 64 #define RT_USING_SYSTEM_WORKQUEUE @@ -158,13 +161,8 @@ #define RT_MMCSD_MAX_PARTITION 16 #define RT_USING_SPI #define RT_USING_QSPI -#define RT_USING_DEV_BUS #define RT_USING_PIN #define RT_USING_KTIME - -/* Using USB */ - -/* end of Using USB */ /* end of Device Drivers */ /* C/C++ and POSIX layer */ @@ -275,6 +273,10 @@ #define RT_USING_ADT_HASHMAP #define RT_USING_ADT_REF /* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ /* end of RT-Thread Components */ /* RT-Thread Utestcases */ @@ -467,10 +469,7 @@ #define RT_USING_UART0 #define RT_USING_UART1 #define BSP_USING_SPI -#define RT_USING_SPIM0 -#define RT_USING_SPIM1 #define RT_USING_SPIM2 -#define RT_USING_SPIM3 #define BSP_USING_CAN #define RT_USING_CANFD #define RT_USING_CAN0 @@ -493,6 +492,7 @@ #define USING_SDIF1 #define USE_SDIF1_TF #define BSP_USING_DC +#define RT_USING_DC_CHANNEL0 #define RT_USING_DC_CHANNEL1 /* end of On-chip Peripheral Drivers */ @@ -537,10 +537,6 @@ #define ELOG_LINE_BUF_SIZE 0x100 #define LOG_DEBUG /* end of Sdk common configuration */ - -/* Image information configuration */ - -/* end of Image information configuration */ /* end of Standalone Setting */ #endif diff --git a/bsp/phytium/aarch64/configs/phytium_pi_rtsmart b/bsp/phytium/aarch64/configs/phytium_pi_rtsmart index 2f91bd7866..46755594a2 100644 --- a/bsp/phytium/aarch64/configs/phytium_pi_rtsmart +++ b/bsp/phytium/aarch64/configs/phytium_pi_rtsmart @@ -15,7 +15,6 @@ CONFIG_RT_THREAD_PRIORITY_32=y # CONFIG_RT_THREAD_PRIORITY_256 is not set CONFIG_RT_THREAD_PRIORITY_MAX=32 CONFIG_RT_TICK_PER_SECOND=1000 -CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y CONFIG_RT_HOOK_USING_FUNC_PTR=y # CONFIG_RT_USING_HOOKLIST is not set @@ -26,6 +25,8 @@ CONFIG_SYSTEM_THREAD_STACK_SIZE=8192 CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 CONFIG_RT_TIMER_THREAD_STACK_SIZE=8192 +# CONFIG_RT_USING_TIMER_ALL_SOFT is not set +CONFIG_RT_USING_CPU_USAGE_TRACER=y # # kservice optimization @@ -49,6 +50,7 @@ CONFIG_RT_DEBUGING_CONTEXT=y # CONFIG_RT_DEBUGING_PAGE_LEAK is not set # CONFIG_RT_DEBUGING_SPINLOCK is not set CONFIG_RT_DEBUGING_CRITICAL=y +CONFIG_RT_USING_OVERFLOW_CHECK=y # # Inter-Thread communication @@ -103,6 +105,8 @@ CONFIG_ARCH_RAM_OFFSET=0x80000000 CONFIG_ARCH_SECONDARY_CPU_STACK_SIZE=4096 CONFIG_ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS=y # CONFIG_ARCH_USING_GENERIC_CPUID is not set +CONFIG_ARCH_HEAP_SIZE=0x4000000 +CONFIG_ARCH_INIT_PAGE_SIZE=0x200000 # end of AArch64 Architecture Configuration CONFIG_ARCH_CPU_64BIT=y @@ -201,6 +205,7 @@ CONFIG_RT_PAGECACHE_GC_STOP_LEVEL=70 # Device Drivers # # CONFIG_RT_USING_DM is not set +CONFIG_RT_USING_DEV_BUS=y CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_UNAMED_PIPE_NUMBER=64 CONFIG_RT_USING_SYSTEM_WORKQUEUE=y @@ -227,6 +232,8 @@ CONFIG_RT_USING_NULL=y CONFIG_RT_USING_ZERO=y CONFIG_RT_USING_RANDOM=y CONFIG_RT_USING_PWM=y +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set # CONFIG_RT_USING_PM is not set @@ -253,21 +260,12 @@ CONFIG_RT_USING_QSPI=y # CONFIG_RT_USING_TOUCH is not set # CONFIG_RT_USING_LCD is not set # CONFIG_RT_USING_HWCRYPTO is not set -# CONFIG_RT_USING_PULSE_ENCODER is not set -# CONFIG_RT_USING_INPUT_CAPTURE is not set -CONFIG_RT_USING_DEV_BUS=y # CONFIG_RT_USING_WIFI is not set # CONFIG_RT_USING_VIRTIO is not set CONFIG_RT_USING_PIN=y CONFIG_RT_USING_KTIME=y # CONFIG_RT_USING_HWTIMER is not set - -# -# Using USB -# -# CONFIG_RT_USING_USB_HOST is not set -# CONFIG_RT_USING_USB_DEVICE is not set -# end of Using USB +# CONFIG_RT_USING_CHERRYUSB is not set # end of Device Drivers # @@ -458,6 +456,15 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64 # # CONFIG_RT_USING_MEMBLOCK is not set # end of Memory management + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set # end of RT-Thread Components # @@ -1378,9 +1385,9 @@ CONFIG_RT_USING_UART1=y # CONFIG_RT_USING_UART3 is not set CONFIG_BSP_USING_SPI=y CONFIG_RT_USING_SPIM0=y -CONFIG_RT_USING_SPIM1=y -CONFIG_RT_USING_SPIM2=y -CONFIG_RT_USING_SPIM3=y +# CONFIG_RT_USING_SPIM1 is not set +# CONFIG_RT_USING_SPIM2 is not set +# CONFIG_RT_USING_SPIM3 is not set # CONFIG_BSP_USING_CAN is not set CONFIG_BSP_USING_GPIO=y CONFIG_BSP_USING_QSPI=y @@ -1419,10 +1426,10 @@ CONFIG_RT_USING_MIO10=y # CONFIG_I2C_USE_CONTROLLER is not set CONFIG_BSP_USING_SDIF=y CONFIG_BSP_USING_SDCARD_FATFS=y -# CONFIG_USING_SDIF0 is not set -CONFIG_USING_SDIF1=y -CONFIG_USE_SDIF1_TF=y -# CONFIG_USE_SDIF1_EMMC is not set +CONFIG_USING_SDIF0=y +CONFIG_USE_SDIF0_TF=y +# CONFIG_USE_SDIF0_EMMC is not set +# CONFIG_USING_SDIF1 is not set CONFIG_BSP_USING_DC=y CONFIG_RT_USING_DC_CHANNEL0=y CONFIG_RT_USING_DC_CHANNEL1=y @@ -1505,10 +1512,4 @@ CONFIG_LOG_DEBUG=y # CONFIG_BOOTUP_DEBUG_PRINTS is not set # CONFIG_USE_DEFAULT_INTERRUPT_CONFIG is not set # end of Sdk common configuration - -# -# Image information configuration -# -# CONFIG_IMAGE_INFO is not set -# end of Image information configuration # end of Standalone Setting diff --git a/bsp/phytium/aarch64/configs/phytium_pi_rtsmart.h b/bsp/phytium/aarch64/configs/phytium_pi_rtsmart.h index 9b97e65a5e..8dc8888d00 100644 --- a/bsp/phytium/aarch64/configs/phytium_pi_rtsmart.h +++ b/bsp/phytium/aarch64/configs/phytium_pi_rtsmart.h @@ -11,7 +11,6 @@ #define RT_THREAD_PRIORITY_32 #define RT_THREAD_PRIORITY_MAX 32 #define RT_TICK_PER_SECOND 1000 -#define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK @@ -21,6 +20,7 @@ #define RT_USING_TIMER_SOFT #define RT_TIMER_THREAD_PRIO 4 #define RT_TIMER_THREAD_STACK_SIZE 8192 +#define RT_USING_CPU_USAGE_TRACER /* kservice optimization */ @@ -35,6 +35,7 @@ #define RT_DEBUGING_COLOR #define RT_DEBUGING_CONTEXT #define RT_DEBUGING_CRITICAL +#define RT_USING_OVERFLOW_CHECK /* Inter-Thread communication */ @@ -73,6 +74,8 @@ #define ARCH_RAM_OFFSET 0x80000000 #define ARCH_SECONDARY_CPU_STACK_SIZE 4096 #define ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS +#define ARCH_HEAP_SIZE 0x4000000 +#define ARCH_INIT_PAGE_SIZE 0x200000 /* end of AArch64 Architecture Configuration */ #define ARCH_CPU_64BIT #define RT_USING_CACHE @@ -146,6 +149,7 @@ /* Device Drivers */ +#define RT_USING_DEV_BUS #define RT_USING_DEVICE_IPC #define RT_UNAMED_PIPE_NUMBER 64 #define RT_USING_SYSTEM_WORKQUEUE @@ -172,13 +176,8 @@ #define RT_MMCSD_MAX_PARTITION 16 #define RT_USING_SPI #define RT_USING_QSPI -#define RT_USING_DEV_BUS #define RT_USING_PIN #define RT_USING_KTIME - -/* Using USB */ - -/* end of Using USB */ /* end of Device Drivers */ /* C/C++ and POSIX layer */ @@ -307,6 +306,10 @@ /* Memory management */ /* end of Memory management */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ /* end of RT-Thread Components */ /* RT-Thread Utestcases */ @@ -500,9 +503,6 @@ #define RT_USING_UART1 #define BSP_USING_SPI #define RT_USING_SPIM0 -#define RT_USING_SPIM1 -#define RT_USING_SPIM2 -#define RT_USING_SPIM3 #define BSP_USING_GPIO #define BSP_USING_QSPI #define RT_USING_QSPI0 @@ -519,8 +519,8 @@ #define RT_USING_MIO10 #define BSP_USING_SDIF #define BSP_USING_SDCARD_FATFS -#define USING_SDIF1 -#define USE_SDIF1_TF +#define USING_SDIF0 +#define USE_SDIF0_TF #define BSP_USING_DC #define RT_USING_DC_CHANNEL0 #define RT_USING_DC_CHANNEL1 @@ -566,10 +566,6 @@ #define ELOG_LINE_BUF_SIZE 0x100 #define LOG_DEBUG /* end of Sdk common configuration */ - -/* Image information configuration */ - -/* end of Image information configuration */ /* end of Standalone Setting */ #endif diff --git a/bsp/phytium/aarch64/configs/phytium_pi_rtthread b/bsp/phytium/aarch64/configs/phytium_pi_rtthread index 38a74a7ea0..410d8ede0c 100644 --- a/bsp/phytium/aarch64/configs/phytium_pi_rtthread +++ b/bsp/phytium/aarch64/configs/phytium_pi_rtthread @@ -15,7 +15,6 @@ CONFIG_RT_THREAD_PRIORITY_32=y # CONFIG_RT_THREAD_PRIORITY_256 is not set CONFIG_RT_THREAD_PRIORITY_MAX=32 CONFIG_RT_TICK_PER_SECOND=1000 -CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y CONFIG_RT_HOOK_USING_FUNC_PTR=y # CONFIG_RT_USING_HOOKLIST is not set @@ -26,6 +25,8 @@ CONFIG_SYSTEM_THREAD_STACK_SIZE=8192 CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 CONFIG_RT_TIMER_THREAD_STACK_SIZE=8192 +# CONFIG_RT_USING_TIMER_ALL_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set # # kservice optimization @@ -49,6 +50,7 @@ CONFIG_RT_DEBUGING_CONTEXT=y # CONFIG_RT_DEBUGING_PAGE_LEAK is not set # CONFIG_RT_DEBUGING_SPINLOCK is not set # CONFIG_RT_DEBUGING_CRITICAL is not set +CONFIG_RT_USING_OVERFLOW_CHECK=y # # Inter-Thread communication @@ -103,6 +105,8 @@ CONFIG_ARCH_RAM_OFFSET=0x80000000 CONFIG_ARCH_SECONDARY_CPU_STACK_SIZE=4096 CONFIG_ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS=y # CONFIG_ARCH_USING_GENERIC_CPUID is not set +CONFIG_ARCH_HEAP_SIZE=0x4000000 +CONFIG_ARCH_INIT_PAGE_SIZE=0x200000 # end of AArch64 Architecture Configuration CONFIG_ARCH_CPU_64BIT=y @@ -193,6 +197,7 @@ CONFIG_RT_USING_DFS_RAMFS=y # Device Drivers # # CONFIG_RT_USING_DM is not set +CONFIG_RT_USING_DEV_BUS=y CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_UNAMED_PIPE_NUMBER=64 CONFIG_RT_USING_SYSTEM_WORKQUEUE=y @@ -219,6 +224,8 @@ CONFIG_RT_USING_NULL=y CONFIG_RT_USING_ZERO=y CONFIG_RT_USING_RANDOM=y CONFIG_RT_USING_PWM=y +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set # CONFIG_RT_USING_PM is not set @@ -245,21 +252,12 @@ CONFIG_RT_USING_QSPI=y # CONFIG_RT_USING_TOUCH is not set # CONFIG_RT_USING_LCD is not set # CONFIG_RT_USING_HWCRYPTO is not set -# CONFIG_RT_USING_PULSE_ENCODER is not set -# CONFIG_RT_USING_INPUT_CAPTURE is not set -CONFIG_RT_USING_DEV_BUS=y # CONFIG_RT_USING_WIFI is not set # CONFIG_RT_USING_VIRTIO is not set CONFIG_RT_USING_PIN=y CONFIG_RT_USING_KTIME=y # CONFIG_RT_USING_HWTIMER is not set - -# -# Using USB -# -# CONFIG_RT_USING_USB_HOST is not set -# CONFIG_RT_USING_USB_DEVICE is not set -# end of Using USB +# CONFIG_RT_USING_CHERRYUSB is not set # end of Device Drivers # @@ -428,6 +426,15 @@ CONFIG_RT_USING_ADT_REF=y # end of Utilities # CONFIG_RT_USING_VBUS is not set + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set # end of RT-Thread Components # @@ -1348,9 +1355,9 @@ CONFIG_RT_USING_UART1=y # CONFIG_RT_USING_UART3 is not set CONFIG_BSP_USING_SPI=y CONFIG_RT_USING_SPIM0=y -CONFIG_RT_USING_SPIM1=y -CONFIG_RT_USING_SPIM2=y -CONFIG_RT_USING_SPIM3=y +# CONFIG_RT_USING_SPIM1 is not set +# CONFIG_RT_USING_SPIM2 is not set +# CONFIG_RT_USING_SPIM3 is not set # CONFIG_BSP_USING_CAN is not set CONFIG_BSP_USING_GPIO=y CONFIG_BSP_USING_QSPI=y @@ -1394,8 +1401,8 @@ CONFIG_USING_SDIF1=y CONFIG_USE_SDIF1_TF=y # CONFIG_USE_SDIF1_EMMC is not set CONFIG_BSP_USING_DC=y -# CONFIG_RT_USING_DC_CHANNEL0 is not set -# CONFIG_RT_USING_DC_CHANNEL1 is not set +CONFIG_RT_USING_DC_CHANNEL0=y +CONFIG_RT_USING_DC_CHANNEL1=y # CONFIG_BSP_USING_XHCI is not set # CONFIG_BSP_USING_PUSB2 is not set # end of On-chip Peripheral Drivers @@ -1475,10 +1482,4 @@ CONFIG_LOG_DEBUG=y # CONFIG_BOOTUP_DEBUG_PRINTS is not set # CONFIG_USE_DEFAULT_INTERRUPT_CONFIG is not set # end of Sdk common configuration - -# -# Image information configuration -# -# CONFIG_IMAGE_INFO is not set -# end of Image information configuration # end of Standalone Setting diff --git a/bsp/phytium/aarch64/configs/phytium_pi_rtthread.h b/bsp/phytium/aarch64/configs/phytium_pi_rtthread.h index a1a53cb0c7..db477b8f43 100644 --- a/bsp/phytium/aarch64/configs/phytium_pi_rtthread.h +++ b/bsp/phytium/aarch64/configs/phytium_pi_rtthread.h @@ -10,7 +10,6 @@ #define RT_THREAD_PRIORITY_32 #define RT_THREAD_PRIORITY_MAX 32 #define RT_TICK_PER_SECOND 1000 -#define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK @@ -33,6 +32,7 @@ #define RT_DEBUGING_ASSERT #define RT_DEBUGING_COLOR #define RT_DEBUGING_CONTEXT +#define RT_USING_OVERFLOW_CHECK /* Inter-Thread communication */ @@ -69,6 +69,8 @@ #define ARCH_RAM_OFFSET 0x80000000 #define ARCH_SECONDARY_CPU_STACK_SIZE 4096 #define ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS +#define ARCH_HEAP_SIZE 0x4000000 +#define ARCH_INIT_PAGE_SIZE 0x200000 /* end of AArch64 Architecture Configuration */ #define ARCH_CPU_64BIT #define RT_USING_CACHE @@ -132,6 +134,7 @@ /* Device Drivers */ +#define RT_USING_DEV_BUS #define RT_USING_DEVICE_IPC #define RT_UNAMED_PIPE_NUMBER 64 #define RT_USING_SYSTEM_WORKQUEUE @@ -158,13 +161,8 @@ #define RT_MMCSD_MAX_PARTITION 16 #define RT_USING_SPI #define RT_USING_QSPI -#define RT_USING_DEV_BUS #define RT_USING_PIN #define RT_USING_KTIME - -/* Using USB */ - -/* end of Using USB */ /* end of Device Drivers */ /* C/C++ and POSIX layer */ @@ -275,6 +273,10 @@ #define RT_USING_ADT_HASHMAP #define RT_USING_ADT_REF /* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ /* end of RT-Thread Components */ /* RT-Thread Utestcases */ @@ -468,9 +470,6 @@ #define RT_USING_UART1 #define BSP_USING_SPI #define RT_USING_SPIM0 -#define RT_USING_SPIM1 -#define RT_USING_SPIM2 -#define RT_USING_SPIM3 #define BSP_USING_GPIO #define BSP_USING_QSPI #define RT_USING_QSPI0 @@ -490,6 +489,8 @@ #define USING_SDIF1 #define USE_SDIF1_TF #define BSP_USING_DC +#define RT_USING_DC_CHANNEL0 +#define RT_USING_DC_CHANNEL1 /* end of On-chip Peripheral Drivers */ /* Board extended module Drivers */ @@ -532,10 +533,6 @@ #define ELOG_LINE_BUF_SIZE 0x100 #define LOG_DEBUG /* end of Sdk common configuration */ - -/* Image information configuration */ - -/* end of Image information configuration */ /* end of Standalone Setting */ #endif diff --git a/bsp/phytium/aarch64/makefile b/bsp/phytium/aarch64/makefile index 79144a5994..fcae70077d 100644 --- a/bsp/phytium/aarch64/makefile +++ b/bsp/phytium/aarch64/makefile @@ -38,8 +38,8 @@ endif boot: make all - cp rtthread_a64.elf /mnt/d/tftboot - cp rtthread_a64.bin /mnt/d/tftboot + cp rtthread_a64.elf /mnt/d/tftpboot + cp rtthread_a64.bin /mnt/d/tftpboot debug: @$(OD) -D rtthread_a64.elf > rtthread_a64.asm diff --git a/bsp/phytium/aarch64/rtconfig.h b/bsp/phytium/aarch64/rtconfig.h index 98e7776c04..92823621a2 100644 --- a/bsp/phytium/aarch64/rtconfig.h +++ b/bsp/phytium/aarch64/rtconfig.h @@ -5,12 +5,11 @@ #define RT_NAME_MAX 16 #define RT_USING_SMP -#define RT_CPUS_NR 2 +#define RT_CPUS_NR 4 #define RT_ALIGN_SIZE 4 #define RT_THREAD_PRIORITY_32 #define RT_THREAD_PRIORITY_MAX 32 #define RT_TICK_PER_SECOND 1000 -#define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK @@ -32,6 +31,7 @@ #define RT_USING_DEBUG #define RT_DEBUGING_ASSERT #define RT_DEBUGING_COLOR +#define RT_USING_OVERFLOW_CHECK /* Inter-Thread communication */ @@ -68,6 +68,8 @@ #define ARCH_RAM_OFFSET 0x80000000 #define ARCH_SECONDARY_CPU_STACK_SIZE 4096 #define ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS +#define ARCH_HEAP_SIZE 0x4000000 +#define ARCH_INIT_PAGE_SIZE 0x200000 /* end of AArch64 Architecture Configuration */ #define ARCH_CPU_64BIT #define RT_USING_CACHE @@ -131,6 +133,7 @@ /* Device Drivers */ +#define RT_USING_DEV_BUS #define RT_USING_DEVICE_IPC #define RT_UNAMED_PIPE_NUMBER 64 #define RT_USING_SYSTEM_WORKQUEUE @@ -158,13 +161,8 @@ #define RT_MMCSD_MAX_PARTITION 16 #define RT_USING_SPI #define RT_USING_QSPI -#define RT_USING_DEV_BUS #define RT_USING_PIN #define RT_USING_KTIME - -/* Using USB */ - -/* end of Using USB */ /* end of Device Drivers */ /* C/C++ and POSIX layer */ @@ -275,6 +273,10 @@ #define RT_USING_ADT_HASHMAP #define RT_USING_ADT_REF /* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ /* end of RT-Thread Components */ /* RT-Thread Utestcases */ @@ -467,10 +469,7 @@ #define RT_USING_UART0 #define RT_USING_UART1 #define BSP_USING_SPI -#define RT_USING_SPIM0 -#define RT_USING_SPIM1 #define RT_USING_SPIM2 -#define RT_USING_SPIM3 #define BSP_USING_CAN #define RT_USING_CANFD #define RT_USING_CAN0 @@ -493,6 +492,7 @@ #define USING_SDIF1 #define USE_SDIF1_TF #define BSP_USING_DC +#define RT_USING_DC_CHANNEL0 #define RT_USING_DC_CHANNEL1 /* end of On-chip Peripheral Drivers */ @@ -502,7 +502,7 @@ #define BSP_USING_GIC #define BSP_USING_GICV3 #define PHYTIUM_ARCH_AARCH64 -#define ARM_SPI_BIND_CPU_ID 0 +#define ARM_SPI_BIND_CPU_ID 2 /* Standalone Setting */ @@ -510,10 +510,10 @@ /* Soc configuration */ -#define TARGET_E2000D +#define TARGET_E2000Q #define SOC_NAME "e2000" -#define TARGET_TYPE_NAME "d" -#define SOC_CORE_NUM 2 +#define TARGET_TYPE_NAME "q" +#define SOC_CORE_NUM 4 #define F32BIT_MEMORY_ADDRESS 0x80000000 #define F32BIT_MEMORY_LENGTH 0x80000000 #define F64BIT_MEMORY_ADDRESS 0x2000000000 @@ -524,8 +524,8 @@ /* Board Configuration */ -#define E2000D_DEMO_BOARD #define BOARD_NAME "demo" +#define E2000Q_DEMO_BOARD /* IO mux configuration when board start up */ @@ -537,10 +537,6 @@ #define ELOG_LINE_BUF_SIZE 0x100 #define LOG_DEBUG /* end of Sdk common configuration */ - -/* Image information configuration */ - -/* end of Image information configuration */ /* end of Standalone Setting */ #endif diff --git a/bsp/phytium/board/board.c b/bsp/phytium/board/board.c index 132c71d86b..ec58fdb0c7 100644 --- a/bsp/phytium/board/board.c +++ b/bsp/phytium/board/board.c @@ -17,6 +17,7 @@ #include "rtconfig.h" #include #include +#include #include #include /* TODO: why need application space when RT_SMART off */ @@ -203,7 +204,7 @@ void rt_hw_board_aarch32_init(void) rt_hw_mmu_map_init(&rt_kernel_space, (void *)0xf0000000, 0x10000000, MMUTable, PV_OFFSET); rt_hw_init_mmu_table(platform_mem_desc,platform_mem_desc_size) ; mmutable_p = (rt_uint32_t)MMUTable + (rt_uint32_t)PV_OFFSET ; - rt_hw_mmu_switch(mmutable_p) ; + rt_hw_mmu_switch((void*)mmutable_p) ; rt_page_init(init_page_region); /* rt_kernel_space 在start_gcc.S 中被初始化，此函数将iomap 空间放置在kernel space 上 */ rt_hw_mmu_ioremap_init(&rt_kernel_space, (void *)0xf0000000, 0x10000000); @@ -229,51 +230,13 @@ void rt_hw_board_aarch32_init(void) #if defined(FT_GIC_REDISTRUBUTIOR_OFFSET) cpu_offset = FT_GIC_REDISTRUBUTIOR_OFFSET ; #endif - rt_uint32_t redist_addr = 0; - FEarlyUartProbe(); FIOMuxInit(); -#if defined(RT_USING_SMART) - redist_addr = (uint32_t)rt_ioremap(GICV3_RD_BASE_ADDR, 4 * 128 * 1024); -#else - redist_addr = GICV3_RD_BASE_ADDR; -#endif - - arm_gic_redist_address_set(0, redist_addr + (cpu_id + cpu_offset) * GICV3_RD_OFFSET, rt_hw_cpu_id()); - -#if defined(TARGET_E2000Q) || defined(TARGET_PHYTIUMPI) - -#if RT_CPUS_NR == 2 - arm_gic_redist_address_set(0, redist_addr + 3 * GICV3_RD_OFFSET, 1); -#elif RT_CPUS_NR == 3 - arm_gic_redist_address_set(0, redist_addr + 3 * GICV3_RD_OFFSET, 1); - arm_gic_redist_address_set(0, redist_addr, 2); -#elif RT_CPUS_NR == 4 - arm_gic_redist_address_set(0, redist_addr + 3 * GICV3_RD_OFFSET, 1); - arm_gic_redist_address_set(0, redist_addr, 2); - arm_gic_redist_address_set(0, redist_addr + GICV3_RD_OFFSET, 3); -#endif - -#else - -#if RT_CPUS_NR == 2 - arm_gic_redist_address_set(0, redist_addr + (1 + cpu_offset) * GICV3_RD_OFFSET, 1); -#elif RT_CPUS_NR == 3 - arm_gic_redist_address_set(0, redist_addr + (1 + cpu_offset) * GICV3_RD_OFFSET, 1); - arm_gic_redist_address_set(0, redist_addr + (2 + cpu_offset) * GICV3_RD_OFFSET, 2); -#elif RT_CPUS_NR == 4 - arm_gic_redist_address_set(0, redist_addr + (1 + cpu_offset) * GICV3_RD_OFFSET, 1); - arm_gic_redist_address_set(0, redist_addr + (2 + cpu_offset) * GICV3_RD_OFFSET, 2); - arm_gic_redist_address_set(0, redist_addr + (3 + cpu_offset) * GICV3_RD_OFFSET, 3); -#endif - -#endif - + arm_gic_redist_address_set(0, platform_get_gic_redist_base(), rt_hw_cpu_id()); rt_hw_interrupt_init(); - /* compoent init */ #ifdef RT_USING_COMPONENTS_INIT rt_components_board_init(); diff --git a/bsp/phytium/board/phytium_cpu.c b/bsp/phytium/board/phytium_cpu.c index cd9fcbabfd..0edb88b55d 100644 --- a/bsp/phytium/board/phytium_cpu.c +++ b/bsp/phytium/board/phytium_cpu.c @@ -50,6 +50,8 @@ int phytium_cpu_id_mapping(int cpu_id) #endif } +#if defined(TARGET_ARMV8_AARCH32) + int rt_hw_cpu_id(void) { FError ret; @@ -63,8 +65,6 @@ int rt_hw_cpu_id(void) return phytium_cpu_id_mapping(cpu_id); } -#if defined(TARGET_ARMV8_AARCH32) - rt_uint64_t get_main_cpu_affval(void) { #if defined(TARGET_E2000Q) || defined(TARGET_PHYTIUMPI) diff --git a/bsp/phytium/board/phytium_cpu.h b/bsp/phytium/board/phytium_cpu.h index 15b9e40f51..fdcead287e 100644 --- a/bsp/phytium/board/phytium_cpu.h +++ b/bsp/phytium/board/phytium_cpu.h @@ -16,8 +16,11 @@ #include #include +#include #include "fparameters.h" #include "fio.h" +#include "faarch.h" + #ifdef RT_USING_SMART #include"ioremap.h" #endif @@ -43,14 +46,52 @@ rt_inline rt_uint32_t platform_get_gic_dist_base(void) return GICV3_DISTRIBUTOR_BASE_ADDR; } -#if defined(TARGET_ARMV8_AARCH64) - /* the basic constants and interfaces needed by gic */ -rt_inline rt_uint32_t platform_get_gic_redist_base(void) +rt_inline uintptr_t platform_get_gic_redist_base(void) { + uintptr_t redis_base, mpidr_aff, gicr_typer_aff; + mpidr_aff = (uintptr_t)(GetAffinity() & 0xfff); + + for (redis_base = GICV3_RD_BASE_ADDR; redis_base < GICV3_RD_BASE_ADDR + GICV3_RD_SIZE; redis_base += GICV3_RD_OFFSET) + { +#ifdef RT_USING_SMART + uintptr_t redis_base_virtual = (uintptr_t)rt_ioremap((void *)redis_base, GICV3_RD_OFFSET); + if (redis_base_virtual == 0) + { + continue; + } +#if defined(TARGET_ARMV8_AARCH64) + gicr_typer_aff = GIC_RDIST_TYPER(redis_base_virtual) >> 32; +#else + gicr_typer_aff = GIC_RDIST_TYPER(redis_base_virtual + 0x4); +#endif + if (mpidr_aff == gicr_typer_aff) + { + return redis_base_virtual; + } + else + { + rt_iounmap(redis_base_virtual); + } +#else +#if defined(TARGET_ARMV8_AARCH64) + gicr_typer_aff = GIC_RDIST_TYPER(redis_base) >> 32; +#else + gicr_typer_aff = GIC_RDIST_TYPER(redis_base + 0x4); +#endif + if (mpidr_aff == gicr_typer_aff) + { + return redis_base; + } +#endif + } + return 0; } + +#if defined(TARGET_ARMV8_AARCH64) + rt_inline rt_uint32_t platform_get_gic_cpu_base(void) { return 0; /* unused in gicv3 */ diff --git a/bsp/phytium/board/phytium_cpu_id.S b/bsp/phytium/board/phytium_cpu_id.S index 55c6f2599b..0a2d07f996 100644 --- a/bsp/phytium/board/phytium_cpu_id.S +++ b/bsp/phytium/board/phytium_cpu_id.S @@ -8,6 +8,7 @@ * Change Logs: * Date Author Notes * 2023-07-26 huanghe first commit + * 2024-07-02 zhangyan modify * */ @@ -93,29 +94,11 @@ core3: mov r0, #3 b return -core4: - mov r0, #4 - b return - -core5: - mov r0, #5 - b return - -core6: - mov r0, #6 - b return - -core8: - mov r0, #8 - b return - default: and r0, r0, #15 return: - bl cpu_id_mapping - mov pc, r9 #else @@ -152,14 +135,18 @@ map_cpu_id_3: mov x0, #1 RET - .globl rt_hw_cpu_id_set rt_hw_cpu_id_set: mov x9, lr mrs x0,MPIDR_EL1 and x1, x0, #15 msr tpidr_el1, x1 + mov lr, x9 + RET +.globl rt_hw_cpu_id +rt_hw_cpu_id: + mrs x0,MPIDR_EL1 ubfx x0, x0, #0, #12 ldr x1,= CORE0_AFF cmp x0, x1 @@ -183,8 +170,6 @@ rt_hw_cpu_id_set: beq core3 #endif - b default - core0: mov x0, #0 b return @@ -201,31 +186,9 @@ core3: mov x0, #3 b return -core4: - mov x0, #4 - b return - -core5: - mov x0, #5 - b return - -core6: - mov x0, #6 - b return - -core8: - mov x0, #8 - b return - -default: - and x0, x0, #15 - -return: - - //bl cpu_id_mapping - mov lr, x9 +return: + b cpu_id_mapping + RET - - #endif diff --git a/bsp/phytium/board/secondary_cpu.c b/bsp/phytium/board/secondary_cpu.c index 517c3434a4..af17a1e3f8 100644 --- a/bsp/phytium/board/secondary_cpu.c +++ b/bsp/phytium/board/secondary_cpu.c @@ -46,21 +46,10 @@ rt_uint64_t rt_cpu_mpidr_early[] = [0] = 0x80000200, [1] = 0x80000201, #elif defined(TARGET_E2000Q) || defined(TARGET_PHYTIUMPI) - [0] = 0x80000000, - [1] = 0x80000100, - [2] = 0x80000200, - [3] = 0x80000201, -#elif defined(TARGET_F2000_4) || defined(TARGET_D2000) - [0] = 0x80000000, - [1] = 0x80000001, - [2] = 0x80000100, - [3] = 0x80000101, -#if defined(TARGET_D2000) - [4] = 0x80000200, - [5] = 0x80000201, - [6] = 0x80000300, - [7] = 0x80000301, -#endif + [0] = 0x80000200, + [1] = 0x80000201, + [2] = 0x80000000, + [3] = 0x80000100, #endif }; @@ -117,23 +106,23 @@ void rt_hw_secondary_cpu_bsp_start(void) #else rt_uint32_t mmutable_p; mmutable_p = (rt_uint32_t)MMUTable + (rt_uint32_t)PV_OFFSET ; - rt_hw_mmu_switch(mmutable_p) ; + rt_hw_mmu_switch((void*)mmutable_p) ; #endif /* vector init */ rt_hw_vector_init(); + /* interrupt init */ #if defined(TARGET_ARMV8_AARCH64) arm_gic_cpu_init(0, 0); - + arm_gic_redist_address_set(0, platform_get_gic_redist_base(), rt_hw_cpu_id()); phytium_aarch64_arm_gic_redist_init(); - rt_kprintf("arm_gic_redist_init is over rt_hw_cpu_id() is %d \r\n", rt_hw_cpu_id()); #else arm_gic_cpu_init(0); + arm_gic_redist_address_set(0, platform_get_gic_redist_base(), rt_hw_cpu_id()); arm_gic_redist_init(0); #endif - /* gtimer init */ #if defined(TARGET_ARMV8_AARCH64) rt_hw_gtimer_init(); @@ -143,7 +132,6 @@ void rt_hw_secondary_cpu_bsp_start(void) rt_hw_interrupt_umask(RT_SCHEDULE_IPI); /* start scheduler */ - rt_kprintf("\rcall cpu %d on success\n", rt_hw_cpu_id()); rt_hw_secondary_cpu_idle_exec(); rt_system_scheduler_start(); diff --git a/bsp/phytium/board/smp_sgi_test.c b/bsp/phytium/board/smp_sgi_test.c new file mode 100644 index 0000000000..0ff7dc3e40 --- /dev/null +++ b/bsp/phytium/board/smp_sgi_test.c @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Email: opensource_embedded@phytium.com.cn + * + * Change Logs: + * Date Author Notes + * 2024/07/15 zhangyan first commit + */ +#include "rtconfig.h" +#ifdef RT_USING_SMP +#include +#include +#include +#include "fparameters.h" +#include "ftypes.h" +#include "board.h" +#include +#include "interrupt.h" +#include +#include "rtatomic.h" + +#define RT_TEST_IPI 3 + +struct rt_thread core_test_thread[RT_CPUS_NR]; + +static char *core_thread_name[4] = +{ + "core0_sgi_test", + "core1_sgi_test", + "core2_sgi_test", + "core3_sgi_test", +}; +static rt_uint8_t core_stack[RT_CPUS_NR][4096]; + +static rt_isr_handler_t smp_test_ipi_handle(int vector, void *param) +{ + rt_int32_t cpu_id = rt_hw_cpu_id(); + rt_kprintf("smp_test_ipi_handle, cpu_id = %d\n", cpu_id); +} + +static void core_thread(void *parameter) +{ + rt_base_t level; + rt_int32_t cpu_id = rt_hw_cpu_id(); + + /* code */ + level = rt_cpus_lock(); + rt_hw_ipi_handler_install(RT_TEST_IPI, smp_test_ipi_handle); + rt_hw_interrupt_umask(RT_TEST_IPI); + rt_kprintf("core%d, rt_hw_interrupt_umask(RT_TEST_IPI) successfully.\n", cpu_id); + rt_cpus_unlock(level); +} + +void demo_core_test(void) +{ + rt_ubase_t i; + rt_ubase_t cpu_id = 0; + rt_kprintf("demo_core%d \n", rt_hw_cpu_id()); + for (i = 0; i < RT_CPUS_NR; i++) + { + cpu_id = i; + rt_thread_init(&core_test_thread[i], + core_thread_name[i], + core_thread, + RT_NULL, + &core_stack[i], + 2048, + 20, + 32); + + rt_thread_control(&core_test_thread[i], RT_THREAD_CTRL_BIND_CPU, (void *)cpu_id); + rt_thread_startup(&core_test_thread[i]); + rt_thread_mdelay(100); + } +} + +/* this function will toggle output pin and test intr of input pin */ +static void smp_sgi_test_thread(void *parameter) +{ + rt_uint32_t cpu_mask = 0; + + for (int i = 0; i < RT_CPUS_NR; i++) + { + cpu_mask = (1 << i); + rt_hw_ipi_send(RT_TEST_IPI, cpu_mask); + rt_thread_mdelay(10); + } +} + +void smp_sgi_sample(int argc, char *argv[]) +{ + rt_thread_t thread; + rt_err_t res; + demo_core_test(); + rt_thread_mdelay(1000); + thread = rt_thread_create("smp_test_thread", smp_sgi_test_thread, RT_NULL, 4096, 25, 10); + res = rt_thread_startup(thread); + RT_ASSERT(res == RT_EOK); +} + +MSH_CMD_EXPORT(smp_sgi_sample, smp toggle sgi sample.); + +#endif \ No newline at end of file diff --git a/bsp/phytium/libraries/common/phytium_interrupt.c b/bsp/phytium/libraries/common/phytium_interrupt.c index 0714c563f4..37ceb55b24 100644 --- a/bsp/phytium/libraries/common/phytium_interrupt.c +++ b/bsp/phytium/libraries/common/phytium_interrupt.c @@ -94,7 +94,6 @@ void phytium_interrupt_init(void) rt_uint64_t gic_cpu_base; rt_uint64_t gic_dist_base; rt_uint64_t gic_irq_start; - rt_uint64_t redist_addr; phytium_gic_table = (struct arm_gic *)arm_gic_get_gic_table_addr(); /* initialize vector table */ @@ -106,44 +105,15 @@ void phytium_interrupt_init(void) #if defined(RT_USING_SMART) gic_dist_base = (rt_uint64_t)rt_ioremap((void *)platform_get_gic_dist_base(), 0x40000); gic_cpu_base = (rt_uint64_t)rt_ioremap((void*)platform_get_gic_cpu_base(), 0x1000); - redist_addr = (rt_uint64_t)rt_ioremap(GICV3_RD_BASE_ADDR, 4 * GICV3_RD_OFFSET); #else gic_dist_base = platform_get_gic_dist_base(); gic_cpu_base = platform_get_gic_cpu_base(); - redist_addr = GICV3_RD_BASE_ADDR; #endif gic_irq_start = 0; arm_gic_dist_init(0, gic_dist_base, gic_irq_start); arm_gic_cpu_init(0, gic_cpu_base); - arm_gic_redist_address_set(0, redist_addr + 2 * GICV3_RD_OFFSET, 0); - -#if defined(TARGET_E2000Q) || defined(TARGET_PHYTIUMPI) -#if RT_CPUS_NR == 2 - arm_gic_redist_address_set(0, redist_addr + 3 * GICV3_RD_OFFSET, 1); -#elif RT_CPUS_NR == 3 - arm_gic_redist_address_set(0, redist_addr + 3 * GICV3_RD_OFFSET, 1); - arm_gic_redist_address_set(0, redist_addr, 2); -#elif RT_CPUS_NR == 4 - arm_gic_redist_address_set(0, redist_addr + 3 * GICV3_RD_OFFSET, 1); - arm_gic_redist_address_set(0, redist_addr, 2); - arm_gic_redist_address_set(0, redist_addr + GICV3_RD_OFFSET, 3); -#endif -#else -#if defined(TARGET_E2000D) - rt_uint32_t cpu_offset = 2; -#endif -#if RT_CPUS_NR == 2 - arm_gic_redist_address_set(0, redist_addr + (1 + cpu_offset) * GICV3_RD_OFFSET, 1); -#elif RT_CPUS_NR == 3 - arm_gic_redist_address_set(0, redist_addr + (1 + cpu_offset) * GICV3_RD_OFFSET, 1); - arm_gic_redist_address_set(0, redist_addr + (2 + cpu_offset) * GICV3_RD_OFFSET, 2); -#elif RT_CPUS_NR == 4 - arm_gic_redist_address_set(0, redist_addr + (1 + cpu_offset) * GICV3_RD_OFFSET, 1); - arm_gic_redist_address_set(0, redist_addr + (2 + cpu_offset) * GICV3_RD_OFFSET, 2); - arm_gic_redist_address_set(0, redist_addr + (3 + cpu_offset) * GICV3_RD_OFFSET, 3); -#endif -#endif + arm_gic_redist_address_set(0, platform_get_gic_redist_base(), 0); phytium_aarch64_arm_gic_redist_init(); } diff --git a/bsp/phytium/libraries/drivers/drv_can.c b/bsp/phytium/libraries/drivers/drv_can.c index f531bcc0fd..49e57dd71d 100644 --- a/bsp/phytium/libraries/drivers/drv_can.c +++ b/bsp/phytium/libraries/drivers/drv_can.c @@ -93,8 +93,8 @@ static rt_err_t _can_config(struct rt_can_device *can, struct can_configure *cfg /*Set the baudrate*/ FCanBaudrateConfig arb_segment_config; FCanBaudrateConfig data_segment_config; - memset(&arb_segment_config, 0, sizeof(arb_segment_config)); - memset(&data_segment_config, 0, sizeof(data_segment_config)); + rt_memset(&arb_segment_config, 0, sizeof(arb_segment_config)); + rt_memset(&data_segment_config, 0, sizeof(data_segment_config)); #if defined(RT_CAN_USING_CANFD) FCanFdEnable(&(drv_can->can_handle), TRUE); arb_segment_config.auto_calc = TRUE; @@ -243,8 +243,8 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg) { FCanBaudrateConfig arb_segment_config; FCanBaudrateConfig data_segment_config; - memset(&arb_segment_config, 0, sizeof(arb_segment_config)); - memset(&data_segment_config, 0, sizeof(data_segment_config)); + rt_memset(&arb_segment_config, 0, sizeof(arb_segment_config)); + rt_memset(&data_segment_config, 0, sizeof(data_segment_config)); drv_can->device.config.baud_rate = argval; FCanEnable(&(drv_can->can_handle), RT_FALSE); arb_segment_config.auto_calc = TRUE; @@ -276,8 +276,8 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg) { FCanBaudrateConfig arb_segment_config; FCanBaudrateConfig data_segment_config; - memset(&arb_segment_config, 0, sizeof(arb_segment_config)); - memset(&data_segment_config, 0, sizeof(data_segment_config)); + rt_memset(&arb_segment_config, 0, sizeof(arb_segment_config)); + rt_memset(&data_segment_config, 0, sizeof(data_segment_config)); drv_can->device.config.baud_rate = argval; FCanEnable(&(drv_can->can_handle), RT_FALSE); arb_segment_config.auto_calc = TRUE; diff --git a/bsp/phytium/libraries/drivers/drv_dc.c b/bsp/phytium/libraries/drivers/drv_dc.c index e4f788c4cb..cc40731a25 100644 --- a/bsp/phytium/libraries/drivers/drv_dc.c +++ b/bsp/phytium/libraries/drivers/drv_dc.c @@ -31,6 +31,8 @@ static rt_uint16_t _rt_framebuffer[1024 * 768 * 4] __aligned(128); static struct rt_device_graphic_info _dc_info; +void rt_hw_dc_register(struct phytium_dc_bus *dc_control_bus, const char *name, rt_uint32_t flag, void *data); + static rt_err_t dc_config(struct phytium_dc_bus *dc_control_bus) { RT_ASSERT(dc_control_bus); diff --git a/bsp/phytium/libraries/drivers/drv_gpio.c b/bsp/phytium/libraries/drivers/drv_gpio.c index 2bab210c1d..f975c5fe78 100644 --- a/bsp/phytium/libraries/drivers/drv_gpio.c +++ b/bsp/phytium/libraries/drivers/drv_gpio.c @@ -22,8 +22,6 @@ #include "ioremap.h" #endif -#include - #if defined(TARGET_E2000) #include "fparameters.h" #endif @@ -37,12 +35,6 @@ #include "fgpio.h" #include "drv_gpio.h" /**************************** Type Definitions *******************************/ -typedef void (*FGpioOpsIrqHandler)(s32 vector, void *param); -typedef struct -{ - FGpioOpsIrqHandler irq_handler; - void *irq_args; -} FGpioOpsPinConfig; /***************** Macros (Inline Functions) Definitions *********************/ @@ -78,7 +70,7 @@ static void drv_pin_mode(struct rt_device *device, rt_base_t pin, rt_uint8_t mod } FGpioConfig input_cfg = *FGpioLookupConfig(index); - memset(&instance[index], 0, sizeof(FGpio)); + rt_memset(&instance[index], 0, sizeof(FGpio)); #ifdef RT_USING_SMART input_cfg.base_addr = (uintptr)rt_ioremap((void *)input_cfg.base_addr, 0x1000); #endif @@ -108,7 +100,6 @@ static void drv_pin_mode(struct rt_device *device, rt_base_t pin, rt_uint8_t mod void drv_pin_write(struct rt_device *device, rt_base_t pin, rt_uint8_t value) { FGpio *instance = (FGpio *)device->user_data; - FError err = FGPIO_SUCCESS; u32 index = (u32)pin; FGpioSetOutputValue(&instance[index], (value == PIN_HIGH) ? FGPIO_PIN_HIGH : FGPIO_PIN_LOW); @@ -117,7 +108,6 @@ void drv_pin_write(struct rt_device *device, rt_base_t pin, rt_uint8_t value) rt_ssize_t drv_pin_read(struct rt_device *device, rt_base_t pin) { FGpio *instance = (FGpio *)device->user_data; - FError err = FGPIO_SUCCESS; u32 index = (u32)pin; return FGpioGetInputValue(&instance[index]) == FGPIO_PIN_HIGH ? PIN_HIGH : PIN_LOW; @@ -127,10 +117,14 @@ rt_err_t drv_pin_attach_irq(struct rt_device *device, rt_base_t pin, rt_uint8_t mode, void (*hdr)(void *args), void *args) { FGpio *instance = (FGpio *)device->user_data; - FError err = FGPIO_SUCCESS; u32 index = (u32)pin; rt_base_t level; +#ifdef RT_USING_SMART + FGpioIntrMap *map = &fgpio_intr_map[instance[index].config.ctrl]; + map->base_addr = (uintptr)rt_ioremap((void *)map->base_addr, 0x1000); +#endif + level = rt_hw_interrupt_disable(); FGpioOpsSetupIRQ(&instance[index]); @@ -154,7 +148,7 @@ rt_err_t drv_pin_attach_irq(struct rt_device *device, rt_base_t pin, break; } - FGpioRegisterInterruptCB(&instance[index], hdr, args); /* register intr callback */ + FGpioRegisterInterruptCB(&instance[index], (FGpioInterruptCallback)hdr, args); /* register intr callback */ rt_hw_interrupt_enable(level); return RT_EOK; @@ -163,7 +157,6 @@ rt_err_t drv_pin_attach_irq(struct rt_device *device, rt_base_t pin, rt_err_t drv_pin_detach_irq(struct rt_device *device, rt_base_t pin) { FGpio *instance = (FGpio *)device->user_data; - FError err = FGPIO_SUCCESS; u32 index = (u32)pin; FGpioIntrMap *map = &fgpio_intr_map[instance[index].config.ctrl]; rt_base_t level; @@ -182,7 +175,6 @@ rt_err_t drv_pin_detach_irq(struct rt_device *device, rt_base_t pin) rt_err_t drv_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled) { FGpio *instance = (FGpio *)device->user_data; - FError err = FGPIO_SUCCESS; u32 index = (u32)pin; FGpioSetInterruptMask(&instance[index], enabled); diff --git a/bsp/phytium/libraries/drivers/drv_i2c.c b/bsp/phytium/libraries/drivers/drv_i2c.c index 21ac4d0eac..4f195ee982 100644 --- a/bsp/phytium/libraries/drivers/drv_i2c.c +++ b/bsp/phytium/libraries/drivers/drv_i2c.c @@ -12,6 +12,7 @@ */ #include "rtconfig.h" #include +#include #define LOG_TAG "i2c_drv" #include "drv_log.h" #include "drv_i2c.h" @@ -118,7 +119,7 @@ static rt_err_t i2c_mio_config(struct phytium_i2c_bus *i2c_bus) return -RT_ERROR; } mio_handle.is_ready = 0; - memset(&mio_handle, 0, sizeof(mio_handle)); + rt_memset(&mio_handle, 0, sizeof(mio_handle)); return RT_EOK; } diff --git a/bsp/phytium/libraries/drivers/drv_pwm.c b/bsp/phytium/libraries/drivers/drv_pwm.c index 6703e3af3e..ee2225718a 100644 --- a/bsp/phytium/libraries/drivers/drv_pwm.c +++ b/bsp/phytium/libraries/drivers/drv_pwm.c @@ -78,7 +78,7 @@ static rt_err_t drv_pwm_set(struct phytium_pwm *pwm_dev, int cmd, struct rt_pwm_ FPwmVariableConfig pwm_cfg; u32 channel = configuration->channel; - memset(&pwm_cfg, 0, sizeof(pwm_cfg)); + rt_memset(&pwm_cfg, 0, sizeof(pwm_cfg)); pwm_cfg.tim_ctrl_mode = FPWM_MODULO; pwm_cfg.tim_ctrl_div = 50 - 1; /* Precision set to microseconds */ @@ -119,18 +119,11 @@ static rt_err_t drv_pwm_get(struct phytium_pwm *pwm_dev, struct rt_pwm_configura { RT_ASSERT(pwm_dev); RT_ASSERT(configuration); - u32 ret; FPwmVariableConfig pwm_cfg; u32 channel = configuration->channel; - memset(&pwm_cfg, 0, sizeof(pwm_cfg)); - ret = FPwmVariableGet(&pwm_dev->pwm_handle, channel, &pwm_cfg); - if (ret != FPWM_SUCCESS) - { - LOG_E("Pwm variable get failed.\n"); - - return -RT_ERROR; - } + rt_memset(&pwm_cfg, 0, sizeof(pwm_cfg)); + FPwmVariableGet(&pwm_dev->pwm_handle, channel, &pwm_cfg); configuration->period = pwm_cfg.pwm_period * 1000; configuration->pulse = pwm_cfg.pwm_pulse * 1000; @@ -148,7 +141,7 @@ static rt_err_t drv_pwm_set_dead_time(struct phytium_pwm *pwm_dev, struct rt_pwm FPwmDbVariableConfig db_cfg; u32 channel = configuration->channel; - memset(&db_cfg, 0, sizeof(db_cfg)); + rt_memset(&db_cfg, 0, sizeof(db_cfg)); db_cfg.db_rise_cycle = configuration->dead_time / 1000; db_cfg.db_fall_cycle = configuration->dead_time / 1000; db_cfg.db_polarity_sel = FPWM_DB_AH; diff --git a/bsp/phytium/libraries/drivers/drv_qspi.c b/bsp/phytium/libraries/drivers/drv_qspi.c index d2c1517c93..3cb1a3af39 100644 --- a/bsp/phytium/libraries/drivers/drv_qspi.c +++ b/bsp/phytium/libraries/drivers/drv_qspi.c @@ -61,7 +61,7 @@ rt_err_t FQspiInit(phytium_qspi_bus *phytium_qspi_bus) } else { - rt_kprintf("Qspi init successfully.\n"); + LOG_D("Qspi init successfully.\n"); } /* Detect connected flash infomation */ @@ -73,7 +73,7 @@ rt_err_t FQspiInit(phytium_qspi_bus *phytium_qspi_bus) } else { - rt_kprintf("Qspi flash detect successfully.\n"); + LOG_D("Qspi flash detect successfully.\n"); } #ifdef USING_QSPI_CHANNEL0 @@ -131,7 +131,7 @@ static rt_err_t phytium_qspi_configure(struct rt_spi_device *device, struct rt_s if (RT_EOK != ret) { qspi_bus->init = RT_FALSE; - rt_kprintf("Qspi init failed!!!\n"); + LOG_E("Qspi init failed!!!\n"); return -RT_ERROR; } qspi_bus->init = RT_EOK; @@ -175,7 +175,7 @@ static rt_ssize_t phytium_qspi_xfer(struct rt_spi_device *device, struct rt_spi_ } else { - rt_kprintf("Write successfully!!!\r\n"); + LOG_D("Write successfully!!!\r\n"); } return RT_EOK; @@ -188,19 +188,19 @@ static rt_ssize_t phytium_qspi_xfer(struct rt_spi_device *device, struct rt_spi_ ret |= FQspiFlashReadDataConfig(&(qspi_bus->fqspi), cmd); if (FT_SUCCESS != ret) { - rt_kprintf("Failed to config read, test result 0x%x.\r\n", ret); + LOG_D("Failed to config read, test result 0x%x.\r\n", ret); return -RT_ERROR; } /* read norflash data */ size_t read_len = FQspiFlashReadData(&(qspi_bus->fqspi), flash_addr, (u8 *)message->recv_buf, len); if (read_len != len) { - rt_kprintf("Failed to read mem, read len = %d.\r\n", read_len); + LOG_E("Failed to read mem, read len = %d.\r\n", read_len); return -RT_ERROR; } else { - rt_kprintf("Read successfully!!!, read_len = %d\r\n", read_len); + LOG_D("Read successfully!!!, read_len = %d\r\n", read_len); } FtDumpHexByte(message->recv_buf, read_len); @@ -241,7 +241,7 @@ static rt_ssize_t phytium_qspi_xfer(struct rt_spi_device *device, struct rt_spi_ return 1; } - rt_kprintf("cmd not found!!!\r\n"); + LOG_E("cmd not found!!!\r\n"); return ret; } @@ -286,7 +286,7 @@ static int rt_qspi_init(phytium_qspi_bus *phytium_qspi) if (rt_qspi_bus_register(&phytium_qspi->qspi_bus, phytium_qspi->name, &phytium_qspi_ops) == RT_EOK) { - rt_kprintf("Qspi bus register successfully!!!\n"); + LOG_D("Qspi bus register successfully!!!\n"); } else { diff --git a/bsp/phytium/libraries/drivers/drv_sdif.c b/bsp/phytium/libraries/drivers/drv_sdif.c index aef5119458..75c622f3ba 100644 --- a/bsp/phytium/libraries/drivers/drv_sdif.c +++ b/bsp/phytium/libraries/drivers/drv_sdif.c @@ -398,11 +398,11 @@ static void sdif_send_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *r return; } - memset(req_cmd, 0, sizeof(*req_cmd)); + rt_memset(req_cmd, 0, sizeof(FSdifCmdData)); if (req->data) { - memset(req_data, 0, sizeof(*req_data)); + rt_memset(req_data, 0, sizeof(FSdifData)); req_cmd->data_p = req_data; } else diff --git a/bsp/phytium/libraries/phytium_standalone_sdk_install.py b/bsp/phytium/libraries/phytium_standalone_sdk_install.py index a09cf9971d..a99519fc10 100644 --- a/bsp/phytium/libraries/phytium_standalone_sdk_install.py +++ b/bsp/phytium/libraries/phytium_standalone_sdk_install.py @@ -19,6 +19,6 @@ def clone_repository(branch, commit_hash): if __name__ == "__main__": branch_to_clone = "master" - commit_to_clone = "57e28e517e45d9d36b832cbdf038970e2ece600e" + commit_to_clone = "3a353d48ee1db27acf77241a62fb7e35c779e110" clone_repository(branch_to_clone, commit_to_clone) \ No newline at end of file diff --git a/components/utilities/ymodem/ry_sy.c b/components/utilities/ymodem/ry_sy.c index 89664f1ad9..4bbf816eb8 100644 --- a/components/utilities/ymodem/ry_sy.c +++ b/components/utilities/ymodem/ry_sy.c @@ -46,7 +46,6 @@ static enum rym_code _rym_recv_begin( rt_size_t len) { struct custom_ctx *cctx = (struct custom_ctx *)ctx; - struct stat file_buf; char insert_0 = '\0'; char *ret; rt_err_t err; @@ -64,7 +63,7 @@ static enum rym_code _rym_recv_begin( cctx->fd = open(cctx->fpath, O_CREAT | O_WRONLY | O_TRUNC, 0); if (cctx->fd < 0) { - rt_err_t err = rt_get_errno(); + err = rt_get_errno(); rt_kprintf("error creating file: %d\n", err); return RYM_CODE_CAN; } diff --git a/libcpu/aarch64/common/cpuport.c b/libcpu/aarch64/common/cpuport.c new file mode 100644 index 0000000000..4c1bf01cf3 --- /dev/null +++ b/libcpu/aarch64/common/cpuport.c @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-06-21 Zhangyan first version + */ + +#include +#include +#include + +#ifdef RT_USING_CPU_FFS +/** + * This function finds the first bit set (beginning with the least significant bit) + * in value and return the index of that bit. + * + * Bits are numbered starting at 1 (the least significant bit). A return value of + * zero from any of these functions means that the argument was zero. + * + * @return return the index of the first bit set. If value is 0, then this function + * shall return 0. + */ +int __rt_ffs(int value) +{ +#ifdef __GNUC__ + return __builtin_ffs(value); +#else + __asm__ volatile ( + "rbit w1, %w0\n" + "cmp %w0, 0\n" + "clz w1, w1\n" + "csinc %w0, wzr, w1, eq\n" + : "=r"(value) + : "0"(value) + ); + return value; +#endif +} + +#endif /* RT_USING_CPU_FFS */ \ No newline at end of file diff --git a/libcpu/aarch64/common/include/cpuport.h b/libcpu/aarch64/common/include/cpuport.h index 217f477aaf..cbd04500a0 100644 --- a/libcpu/aarch64/common/include/cpuport.h +++ b/libcpu/aarch64/common/include/cpuport.h @@ -53,36 +53,6 @@ typedef struct void _thread_start(void); -#ifdef RT_USING_CPU_FFS -/** - * This function finds the first bit set (beginning with the least significant bit) - * in value and return the index of that bit. - * - * Bits are numbered starting at 1 (the least significant bit). A return value of - * zero from any of these functions means that the argument was zero. - * - * @return return the index of the first bit set. If value is 0, then this function - * shall return 0. - */ -rt_inline int __rt_ffs(int value) -{ -#ifdef __GNUC__ - return __builtin_ffs(value); -#else - __asm__ volatile ( - "rbit w1, %w0\n" - "cmp %w0, 0\n" - "clz w1, w1\n" - "csinc %w0, wzr, w1, eq\n" - : "=r"(value) - : "0"(value) - ); - return value; -#endif -} - -#endif /* RT_USING_CPU_FFS */ - #ifdef ARCH_USING_HW_THREAD_SELF rt_inline struct rt_thread *rt_hw_thread_self(void) { From 1202d51bd64c4a1d442e708eba42d88c1c086016 Mon Sep 17 00:00:00 2001 From: zhangyan <1422953826@qq.com> Date: Mon, 22 Jul 2024 10:42:30 +0800 Subject: [PATCH 36/48] format check --- bsp/phytium/board/phytium_cpu.h | 2 +- bsp/phytium/board/smp_sgi_test.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/bsp/phytium/board/phytium_cpu.h b/bsp/phytium/board/phytium_cpu.h index fdcead287e..bbc9236535 100644 --- a/bsp/phytium/board/phytium_cpu.h +++ b/bsp/phytium/board/phytium_cpu.h @@ -58,7 +58,7 @@ rt_inline uintptr_t platform_get_gic_redist_base(void) uintptr_t redis_base_virtual = (uintptr_t)rt_ioremap((void *)redis_base, GICV3_RD_OFFSET); if (redis_base_virtual == 0) { - continue; + continue; } #if defined(TARGET_ARMV8_AARCH64) gicr_typer_aff = GIC_RDIST_TYPER(redis_base_virtual) >> 32; diff --git a/bsp/phytium/board/smp_sgi_test.c b/bsp/phytium/board/smp_sgi_test.c index 0ff7dc3e40..6567ad89e7 100644 --- a/bsp/phytium/board/smp_sgi_test.c +++ b/bsp/phytium/board/smp_sgi_test.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 * * Email: opensource_embedded@phytium.com.cn - * + * * Change Logs: * Date Author Notes * 2024/07/15 zhangyan first commit From e726b93016165bac2bf47c12b80c9f154e2b998e Mon Sep 17 00:00:00 2001 From: Shell Date: Thu, 18 Jul 2024 09:57:46 +0000 Subject: [PATCH 37/48] [utest] feat: print progress on testing This is required so the user will not be confused on waiting for test to complete. Changes: - notify user that the test is not corrupted - expand waiting tick on timed mtx test, for compatibility on different hw. Signed-off-by: Shell --- .../testcases/kernel/sched_timed_mtx_tc.c | 2 +- examples/utest/testcases/kernel/timer_tc.c | 25 +++++++++++++++++-- 2 files changed, 24 insertions(+), 3 deletions(-) diff --git a/examples/utest/testcases/kernel/sched_timed_mtx_tc.c b/examples/utest/testcases/kernel/sched_timed_mtx_tc.c index f03202a2dc..3729e4a22e 100644 --- a/examples/utest/testcases/kernel/sched_timed_mtx_tc.c +++ b/examples/utest/testcases/kernel/sched_timed_mtx_tc.c @@ -197,7 +197,7 @@ static void timed_mtx_tc(void) for (size_t i = 0; i < 2; i++) { uassert_int_equal( - rt_sem_take(&_thr_exit_sem, 2 * TEST_LOOP_TICKS), + rt_sem_take(&_thr_exit_sem, 4 * TEST_LOOP_TICKS), RT_EOK); } diff --git a/examples/utest/testcases/kernel/timer_tc.c b/examples/utest/testcases/kernel/timer_tc.c index b914d5d06b..50546982eb 100644 --- a/examples/utest/testcases/kernel/timer_tc.c +++ b/examples/utest/testcases/kernel/timer_tc.c @@ -22,6 +22,9 @@ } \ } while (0) +/* notify user that the test is not corrupted */ +#define PRINT_PROGRESS(id) LOG_I("Testing on %d", id) + static rt_uint8_t timer_flag_oneshot[] = { RT_TIMER_FLAG_ONE_SHOT, RT_TIMER_FLAG_ONE_SHOT | RT_TIMER_FLAG_HARD_TIMER, @@ -649,6 +652,8 @@ static void test_timer_stress(void) { rt_tick_t start; rt_ubase_t iters = 0; + rt_ubase_t cur_tick; + rt_ubase_t next_print_time; LOG_I("timer stress test begin, it will take %d seconds", 3*TEST_TIME_S); @@ -665,8 +670,9 @@ static void test_timer_stress(void) } start = rt_tick_get(); - - while (rt_tick_get() - start <= TEST_TIME_S * RT_TICK_PER_SECOND) + cur_tick = rt_tick_get(); + next_print_time = cur_tick + RT_TICK_PER_SECOND; + while (cur_tick - start <= TEST_TIME_S * RT_TICK_PER_SECOND) { for (int j = 0; j < STRESS_TIMERS; j++) { @@ -680,6 +686,12 @@ static void test_timer_stress(void) } } iters ++; + cur_tick = rt_tick_get(); + if (cur_tick > next_print_time) + { + PRINT_PROGRESS(next_print_time); + next_print_time = cur_tick + RT_TICK_PER_SECOND; + } } for (int j = 0; j < STRESS_TIMERS; j++) @@ -710,16 +722,25 @@ static rt_err_t utest_tc_cleanup(void) static void testcase(void) { UTEST_UNIT_RUN(test_static_timer); + PRINT_PROGRESS(__LINE__); UTEST_UNIT_RUN(test_static_timer_control); + PRINT_PROGRESS(__LINE__); UTEST_UNIT_RUN(test_static_timer_start_twice); + PRINT_PROGRESS(__LINE__); UTEST_UNIT_RUN(test_static_timer_op_in_callback); + PRINT_PROGRESS(__LINE__); #ifdef RT_USING_HEAP UTEST_UNIT_RUN(test_dynamic_timer); + PRINT_PROGRESS(__LINE__); UTEST_UNIT_RUN(test_dynamic_timer_control); + PRINT_PROGRESS(__LINE__); UTEST_UNIT_RUN(test_dynamic_timer_start_twice); + PRINT_PROGRESS(__LINE__); UTEST_UNIT_RUN(test_dynamic_timer_op_in_callback); + PRINT_PROGRESS(__LINE__); #endif /* RT_USING_HEAP */ UTEST_UNIT_RUN(test_timer_stress); + PRINT_PROGRESS(__LINE__); } UTEST_TC_EXPORT(testcase, "testcases.kernel.timer_tc", utest_tc_init, utest_tc_cleanup, 1000); From 04cad7f9c67d3cd94da798903b9cac133c10fbcc Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Mon, 22 Jul 2024 16:30:06 +0800 Subject: [PATCH 38/48] bsp: cvitek: improve documentation Currently, the documents under bsp/cvitek are a bit messy. There are currently four readme files: - bsp/cvitek/README.md (Chinese) - bsp/cvitek/c906_little/README.md (Chinese/English) - bsp/cvitek/cv18xx_aarch64/README.md (Chinese) - bsp/cvitek/cv18xx_risc-v/README.md (Chinese/English) Regarding the working mode of the big + small cores, it is meaningless to describe the small core alone, or the large core alone. This can also be seen in the existing files. The readme of the small core will also introduce the programming of the large core, and vice versa. Considering that the official default mode is C906B + C906L. ARM large core can be treataed as a special case. So the document structure is modified as follows: - Remove `bsp/cvitek/c906_little/README.md` and `bsp/cvitek/cv18xx_risc-v/README.md`, merge them all into `bsp/cvitek/README.md` - Add a link to `bsp/cvitek/cv18xx_aarch64/README.md` in `bsp/cvitek/README.md` FIXME: The modified document does not provide English version. Is it really necessary? Signed-off-by: Chen Wang --- bsp/cvitek/README.md | 138 +++++++++++++++++------- bsp/cvitek/c906_little/README.md | 73 ------------- bsp/cvitek/c906_little/README_en.md | 72 ------------- bsp/cvitek/cv18xx_risc-v/README.md | 148 -------------------------- bsp/cvitek/cv18xx_risc-v/README_en.md | 147 ------------------------- 5 files changed, 99 insertions(+), 479 deletions(-) delete mode 100755 bsp/cvitek/c906_little/README.md delete mode 100755 bsp/cvitek/c906_little/README_en.md delete mode 100755 bsp/cvitek/cv18xx_risc-v/README.md delete mode 100755 bsp/cvitek/cv18xx_risc-v/README_en.md diff --git a/bsp/cvitek/README.md b/bsp/cvitek/README.md index db1c27ae17..40253a2226 100755 --- a/bsp/cvitek/README.md +++ b/bsp/cvitek/README.md @@ -1,25 +1,99 @@ -# cvitek bsp + + +- [参考文档](#参考文档) +- [概述](#概述) +- [BSP 支持情况](#bsp-支持情况) + - [驱动支持列表](#驱动支持列表) +- [编译](#编译) + - [Toolchain 下载](#toolchain-下载) + - [依赖安装](#依赖安装) + - [构建](#构建) +- [运行](#运行) +- [FAQ](#faq) +- [联系人信息](#联系人信息) + + + +# 参考文档 + +- 【参考 1】CV1800B/CV1801B Datasheet（中文版）： +- 【参考 2】SG2002/SG2000 技术参考手册（中文版）：。官方定期发布 pdf 形式。可以下载下载最新版本的中文版本技术参考手册：`sg2002_trm_cn.pdf` 或者 `sg2000_trm_cn.pdf`。 + +# 概述 + +支持开发板以及集成 SoC 芯片信息如下 + +- milk-v duo: [https://milkv.io/duo](https://milkv.io/duo)，SoC 采用 CV1800B。 +- milk-v duo256m: [https://milkv.io/duo256m](https://milkv.io/docs/duo/getting-started/duo256m)，SoC 采用 SG2002。 + +Duo 家族开发板采用 CV18xx 系列芯片。芯片的工作模式总结如下： + +- CV1800B，支持一种工作模式： + - 大核（RISC-V C906@1GHz）+ 小核（RISC-V C906@700MHz）。 +- SG2002（原 CV181xC），支持两种工作模式，通过管脚 GPIO_RTX 的外围电路控制进行切换： + - 大核（RISC-V C906@1GHz）+ 小核（RISC-V C906@700MHz）。 + - 大核（ARM Cortex-A53@1GHz）+ 小核（RISC-V C906@700MHz）。 +- SG2000（原 CV181xH），支持两种工作模式，通过管脚 GPIO_RTX 的外围电路控制进行切换： + - 大核（RISC-V C906@1GHz）+ 小核（RISC-V C906@700MHz）。 + - 大核（ARM Cortex-A53@1GHz）+ 小核（RISC-V C906@700MHz）。 + +# BSP 支持情况 + +由于大小核的存在，以及不同 SoC 下不同工作模式的存在，bsp/cvitek 提供了三种不同 BSP/OS，需要单独编译。 + +| BSP 名称 | 大小核 | 芯片架构 | 默认串口控制台 | 备注 | +| ------------- | ------- |---------------- | -------------- | -------- | +| cv18xx_risc-v | 大核 | RISC-V C906 | uart0 | 支持 MMU，支持 RT-Thread 标准版 和 RT-SMART 模式，默认运行 RT-Thread 标准版本 | +| c906-little | 小核 | RISC-V C906 | uart1 | 无 MMU，运行 RT-Thread 标准版 | +| cv18xx_aarch64| 大核 | ARM Cortex A53 | uart0 | 支持 MMU， 支持 RT-Thread 标准版 和 RT-SMART 版，默认运行 RT-Thread 标准版本 | + +由于开发板默认运行的大核为 "cv18xx_risc-v", 所以本文将主要介绍 "cv18xx_risc-v" 和 "c906-little" 的构建和使用。有关 "cv18xx_aarch64" 的介绍请参考 [这里](./cv18xx_aarch64/README.md)。 + +## 驱动支持列表 + +| 驱动 | 支持情况 | 备注 | +| :---- | :------- | :---------------- | +| uart | 支持 | 默认波特率115200 | +| gpio | 支持 | | +| i2c | 支持 | | +| adc | 支持 | | +| spi | 支持 | 默认CS引脚，每个数据之间CS会拉高，请根据时序选择GPIO作为CS。若读取数据，tx需持续dummy数据。| +| pwm | 支持 | | +| timer | 支持 | | +| wdt | 支持 | | +| sdio | 支持 | | +| eth | 支持 | | + +# 编译 + +## Toolchain 下载 + +> 注：当前 bsp 只支持 Linux 编译，推荐 ubuntu 22.04 + +1. RT-Thread 标准版工具链：`riscv64-unknown-elf-gcc` 下载地址 [https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1705395512373/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.1-20240115.tar.gz](https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1705395512373/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.1-20240115.tar.gz) + +2. RT-Smart 版工具链： `riscv64-unknown-linux-musl-gcc` 下载地址 [https://github.com/RT-Thread/toolchains-ci/releases/download/v1.7/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu_latest.tar.bz2](https://github.com/RT-Thread/toolchains-ci/releases/download/v1.7/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu_latest.tar.bz2) -## 支持芯片 -针对算能系列 RISC-V 芯片的 bsp，包括： +正确解压后，在`rtconfig.py`中将 `riscv64-unknown-elf-gcc` 或 `riscv64-unknown-linux-musl-gcc` 工具链的本地路径加入 `EXEC_PATH` 或通过 `RTT_EXEC_PATH` 环境变量指定路径。 -- 大核 +```shell +# RT-Thread 标准版按照以下配置： +$ export RTT_CC_PREFIX=riscv64-unknown-elf- +$ export RTT_EXEC_PATH=/opt/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.1/bin -| 芯片名称 | 芯片架构 | 内存大小 | 默认日志串口 | 备注 | -| ------- | ------- |------- | -------- | -------- | -| cv180x | RISC-V C906 | 64MByte | uart0 | 支持 MMU， 支持 RT-Thread 标准版 和 RT-SMART 模式，默认运行 RT-Thread 标准版本 | -| cv181x | RISC-V C906 或 Cortex A53 通过硬件 IO 二选一 | 64MByte | uart0 | 支持 MMU， 支持 RT-Thread 标准版 和 RT-SMART 版，默认运行 RT-Thread 标准版本 | +# RT-Samrt 版按照以下配置： +$ export RTT_CC_PREFIX=riscv64-unknown-linux-musl- +$ export RTT_EXEC_PATH=/opt/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu/bin +``` -- 小核 +## 依赖安装 +```shell +$ sudo apt install -y scons libncurses5-dev device-tree-compiler +``` -| 目录 | 内存大小 | 默认日志串口 | 备注 | -| ---- | ------- | -------- | --- | -| c906-little | 与大核共享 | uart1 | 无 MMU，运行 RT-Thread 标准版 | +## 构建 -> 注：异构芯片需单独编译每个核的 OS - -## 编译 异构芯片需单独编译每个核的 OS，在大/小核对应的目录下，依次执行: 1. 开发板选择 @@ -42,35 +116,21 @@ Board Type (milkv-duo) ---> $ scons ``` -## 运行 - 编译成功后，会在 `bsp/cvitek/output` 对应开发板型号目录下自动生成 `fip.bin` 和 `boot.sd` 文件，其中大核运行文件在 `boot.sd` 中，小核的运行文件在 `fip.bin` 中。 +- fip.bin：fsbl、opensbi、uboot、小核运行文件打包后的 bin 文件 +- boot.sd：大核打包后的 bin 文件 + +# 运行 + 1. 将 SD 卡分为 2 个分区，第 1 个分区用于存放 bin 文件，第 2 个分区用于作为数据存储分区，分区格式为 `FAT32`。 -2. 将根目录下的 `fip.bin` 和 `boot.sd` 复制 SD 卡第一个分区中。 - - fip.bin：fsbl、 opensbi、uboot、小核运行文件打包后的 bin 文件 - - boot.sd：大核打包后的 bin 文件 -## 驱动支持列表 +2. 将根目录下的 `fip.bin` 和 `boot.sd` 复制到 SD 卡第一个分区中。两个固件文件可以独立修改更新，譬如后续只需要更新大核，只需要重新编译 "cv18xx_risc-v" 并复制 `boot.sd` 文件即可。 -| 驱动 | 支持情况 | 备注 | -| :--- | :------- | :---------------- | -| uart | 支持 | 默认波特率115200 | -| gpio | 支持 | | -| i2c | 支持 | | -| adc | 支持 | | -| spi | 支持 | 默认CS引脚，每个数据之间CS会拉高，请根据时序选择GPIO作为CS。若读取数据，tx需持续dummy数据。| -| pwm | 支持 | | -| timer | 支持 | | -| wdt | 支持 | | -| sdio | 支持 | | -| eth | 支持 | | +3. 更新完固件文件后， 重新上电可以看到串口的输出信息。 -## 支持开发板 -- milk-v duo: [https://milkv.io/duo](https://milkv.io/duo) -- milk-v duo256m: [https://milkv.io/duo256m](https://milkv.io/docs/duo/getting-started/duo256m) +# FAQ -## FAQ 1. 如遇到不能正常编译，请先使用 `scons --menuconfig` 重新生成配置。 2. 错误：./mkimage: error while loading shared libraries: libssl.so.1.1: cannot open shared object file: No such file or directory @@ -84,8 +144,8 @@ $ sudo dpkg -i libssl1.1_1.1.1f-1ubuntu2_amd64.deb 3. 如发现切换开发板编译正常，但无法正常打包，请切换至自动下载的 `cvi_bootloader` 目录，并手工运行 `git pull` 更新，或删除该目录后重新自动下载。 -## 联系人信息 +# 联系人信息 维护人：[flyingcys](https://github.com/flyingcys) -更多信息请参考 [https://riscv-rtthread-programming-manual.readthedocs.io](https://riscv-rtthread-programming-manual.readthedocs.io) \ No newline at end of file +更多信息请参考 [https://riscv-rtthread-programming-manual.readthedocs.io](https://riscv-rtthread-programming-manual.readthedocs.io) diff --git a/bsp/cvitek/c906_little/README.md b/bsp/cvitek/c906_little/README.md deleted file mode 100755 index 14bd1a7e49..0000000000 --- a/bsp/cvitek/c906_little/README.md +++ /dev/null @@ -1,73 +0,0 @@ -# c906_little bsp -该 bsp 为 cv18xx 系列处理器中的协处理器，采用 RISCV C906 @ 700Mhz。 -特性： -- 无 MMU -- 集成浮点运算单元 (FPU) - -## Toolchain 下载 -下载 `riscv64-unknown-elf-gcc` 的工具链: [https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1705395512373/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.1-20240115.tar.gz](https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1705395512373/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.1-20240115.tar.gz) - -> 注： -当前 bsp 只支持 Linux 编译 - -正确解压后，在`rtconfig.py`中将 `riscv64-unknown-elf-gcc` 工具链的本地路径加入 `EXEC_PATH` 或通过 `RTT_EXEC_PATH` 环境变量指定路径。 - -```shell -$ export RTT_EXEC_PATH=/opt/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.1/bin -``` - -## 编译 -1. 依赖安装 - -```shell -$ sudo apt install -y scons libncurses5-dev wget flex bison -``` - - -2. Linux平台下，先执行： -```shell -$ scons --menuconfig -``` - -选择当前需要编译的目标开发板类型： -```shell -Board Type (milkv-duo) ---> - ( ) milkv-duo - ( ) milkv-duo-spinor - (X) milkv-duo256m - ( ) milkv-duo256m-spinor -``` - -它会自动下载 env 相关脚本到 ~/.env 目录，然后执行 -```shell -$ source ~/.env/env.sh -$ pkgs --update -``` -更新完软件包后，执行 `scons -j10` 或 `scons -j10 --verbose` 来编译这个板级支持包。或者通过 `scons --exec-path="GCC工具链路径"` 命令，在指定工具链位置的同时直接编译。编译正确无误，会产生rtthread.elf 文件。 - -编译完成后脚本自动调用 `combine-fip.sh` 脚本进行打包，并生成 `fip.sd`, 该文件即为 SD 卡启动的 c906_little 文件。 - -第一次调用 `combine-fip.sh` 脚本时会自动下载打包需要的 `opsbsbi`、`fsbl`、`uboot` 等相关文件至 `bsp/cvitek/cvitek_bootloader` 目录，请耐心等待。 - -下载完成后会自动解压、编译，后续再次编译同一类型开发板只会调用相关文件打包合成 `fip.bin`。如需手工编译相关 `cvitek_bootloader` 文件，可在 `bsp/cvitek/cvitek_bootloader` 目录下执行 `bash build.sh lunch` 选择对应的开发板编译。 - -## 运行 -1. 将 SD 卡分为 2 个分区，第 1 个分区用于存放 bin 文件，第 2 个分区用于作为数据存储分区，分区格式为 `FAT32`。 -2. 将根目录下的 `fip.bin` 和 `boot.sd` 复制 SD 卡第一个分区中。后续更新固件只需要复制 `fip.sd` 文件即可。 -其中： -- fip.bin：fsbl、 opensbi、 uboot、c906_little 打包后的 bin 文件 -- boot.sd：大核打包后的 bin 文件 - -更新完 `fip.sd` 后， 重新上电可以看到串口的输出信息： -```shell -HW_HEAP_BEGIN:83f74dc0 RT_HW_HEAP_END:84000000 size: 569920 - - \ | / -- RT - Thread Operating System - / | \ 5.1.0 build Jan 27 2024 22:45:49 - 2006 - 2022 Copyright by RT-Thread team -Hello, RISC-V! -msh /> -``` - -> 注：c906 小核默认日志串口为 uart1 \ No newline at end of file diff --git a/bsp/cvitek/c906_little/README_en.md b/bsp/cvitek/c906_little/README_en.md deleted file mode 100755 index df6d28fa9c..0000000000 --- a/bsp/cvitek/c906_little/README_en.md +++ /dev/null @@ -1,72 +0,0 @@ -# c906_little bsp -This BSP is a coprocessor in the cv18xx series processor, using RISCV C906 @ 700Mhz. -Features: -- No MMU -- Integrated Floating-point Unit (FPU) - -## Toolchain Download -Download the toolchain for `riscv64-unknown-elf-gcc`: [https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1705395512373/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.1-20240115.tar.gz](https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1705395512373/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.1-20240115.tar.gz) - -> Note: -Current BSP only supports Linux compilation. - -After correct decompression, add the local path of the `riscv64-unknown-elf-gcc` toolchain to `EXEC_PATH` in `rtconfig.py`, or specify the path through the `RTT_EXEC_PATH` environment variable. - -```shell -$ export RTT_EXEC_PATH=/opt/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.1/bin -``` - -## Compilation -1. Dependency Installation - -```shell -$ sudo apt install -y scons libncurses5-dev wget flex bison -``` - -2. On Linux platform, execute: -```shell -$ scons --menuconfig -``` - -Choose the target development board type that needs to be compiled: -```shell -Board Type (milkv-duo) ---> - ( ) milkv-duo - ( ) milkv-duo-spinor - (X) milkv-duo256m - ( ) milkv-duo256m-spinor -``` - -It will automatically download env related scripts to the ~/.env directory, then execute -```shell -$ source ~/.env/env.sh -$ pkgs --update -``` -After updating the software packages, execute `scons -j10` or `scons -j10 --verbose` to compile this BSP. Or use the `scons --exec-path="GCC toolchain path"` command to compile directly while specifying the toolchain location. If the compilation is correct, the rtthread.elf file will be generated. - -After the compilation is completed, the script automatically calls the `combine-fip.sh` script for packaging, and generates `fip.sd`, which is the c906_little file for SD card startup. - -The first time the `combine-fip.sh` script is called, it will automatically download the required `opsbsbi`, `fsbl`, `uboot`, and other related files to the `bsp/cvitek/cvitek_bootloader` directory, please be patient. - -After downloading, it will automatically decompress and compile. Subsequently, when compiling the same type of development board again, only the relevant files will be called to package and synthesize `fip.bin`. If you need to manually compile the related `cvitek_bootloader` files, you can execute `bash build.sh lunch` in the `bsp/cvitek/cvitek_bootloader` directory to choose the corresponding development board for compilation. - -## Running -1. Divide the SD card into 2 partitions, the 1st partition is used to store bin files, and the 2nd partition is used as a data storage partition, with the partition format being `FAT32`. -2. Copy the `fip.bin` and `boot.sd` from the root directory into the 1st partition of the SD card. Subsequent firmware updates only require copying the `fip.sd` file. -Where: -- fip.bin: fsbl, opensbi, uboot, c906_little packaged bin file -- boot.sd: bin file packaged by the main kernel - -After updating `fip.sd`, restarting will show the output information on the serial port: -```shell -HW_HEAP_BEGIN:83f74dc0 RT_HW_HEAP_END:84000000 size: 569920 - - \ | / -- RT - Thread Operating System - / | \ 5.1.0 build Jan 27 2024 22:45:49 - 2006 - 2022 Copyright by RT-Thread team -Hello, RISC-V! -msh /> -``` - -> Note: The default log serial port for the c906 little core is uart1 \ No newline at end of file diff --git a/bsp/cvitek/cv18xx_risc-v/README.md b/bsp/cvitek/cv18xx_risc-v/README.md deleted file mode 100755 index d931c171d7..0000000000 --- a/bsp/cvitek/cv18xx_risc-v/README.md +++ /dev/null @@ -1,148 +0,0 @@ - **中文** | [English](README_en.md) - -## 概述 -CV18xx 系列芯片面向民用消费监控 IP 摄像机、居家智能等多项产品领域而推出的高性能、低功耗芯片，集成了 H.264/H.265 视频压缩编码器和 ISP；支持数字寛动态、 3D 降噪、除雾、镜头畸变校正等多种图像增强和矫正算法，为客户提供专业级的视频图像质量。 - -1. 处理器内核 - -- 主处理器 RISCV C906 @ 1.0Ghz - - 32KB I-cache, 64KB D-Cache - - 集成矢量(Vector)及浮点运算单元 (FPU) . -- 协处理器 RISCV C906 @ 700Mhz - - 集成浮点运算单元 (FPU) - -2. 存储器接口 -- 内建 DRAM : DDR2 16bitx1, 最高速率达 1333Mbps , 容量512Mbit (64MB) -- 支持SPI NOR flash 接口 (1.8V / 3.0V) - - 支持 1, 2, 4 线模式 - - 最大支持 256MByte -- 支持 SPI Nand flash 接口 (1.8V / 3.0V) - - 支持 1KB/2KB/4KB page (对应的最大容量 16GB/32GB/64GB) - - 使用器件本身内建的 ECC 模块 - -3. 外设 -- Up to 26 GPIO pins on the MilkV-Duo 40-pin header provide access to internal peripherals such as SDIO, I2C, PWM, SPI, J-TAG, and UART -- Up to 3x I2C -- Up to 5x UART -- Up to 1x SDIO1 -- Up to 1x SPI -- Up to 2x ADC -- Up to 7x PWM -- Up to 1x RUN -- Up to 1x JTAG -- 集成 MAC PHY 支持 10/100Mbps 全双工或半双工模式 -- 一个 USB Host / device 接口 - -4. [GPIO 引脚分布](https://milkv.io/zh/docs/duo/getting-started/duo256m#gpio-%E5%BC%95%E8%84%9A%E5%88%86%E5%B8%83) - -## Toolchain 下载 -1. RT-Thread 标准版工具链：`riscv64-unknown-elf-gcc` 下载地址 [https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1705395512373/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.1-20240115.tar.gz](https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1705395512373/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.1-20240115.tar.gz) - -2. RT-Smart 版工具链： `riscv64-unknown-linux-musl-gcc` 下载地址 [https://github.com/RT-Thread/toolchains-ci/releases/download/v1.7/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu_latest.tar.bz2](https://github.com/RT-Thread/toolchains-ci/releases/download/v1.7/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu_latest.tar.bz2) - -> 注： -当前 bsp 只支持 Linux 编译，推荐 ubuntu 22.04 - -正确解压后，在`rtconfig.py`中将 `riscv64-unknown-elf-gcc` 或 `riscv64-unknown-linux-musl-gcc` 工具链的本地路径加入 `EXEC_PATH` 或通过 `RTT_EXEC_PATH` 环境变量指定路径。 - -```shell -# RT-Thread 标准版按照以下配置： -$ export RTT_CC_PREFIX=riscv64-unknown-elf- -$ export RTT_EXEC_PATH=/opt/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.1/bin - -# RT-Samrt 版按照以下配置： -$ export RTT_CC_PREFIX=riscv64-unknown-linux-musl- -$ export RTT_EXEC_PATH=/opt/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu/bin -``` - -## 编译 - -### 依赖安装 -```shell -$ sudo apt install -y scons libncurses5-dev device-tree-compiler -``` - -## 修改当前工程配置 - -Linux平台下，执行： -```shell -$ scons --menuconfig -``` - -1. 默认编译为 RT-Thread 标准版，如果需要编译为 RT-Smart 版，请按照如下方式修改： -```shell -RT-Thread Kernel ---> - [*] Enable RT-Thread Smart (microkernel on kernel/userland) - - (0x80000000) The virtural address of kernel start -``` - -2. 选择当前需要编译的目标开发板类型： -```shell -Board Type (milkv-duo) ---> - ( ) milkv-duo - ( ) milkv-duo-spinor - (X) milkv-duo256m - ( ) milkv-duo256m-spinor -``` - -它会自动下载env相关脚本到~/.env目录，然后执行 -```shell -$ source ~/.env/env.sh -$ pkgs --update -``` -更新完软件包后，执行 `scons -j10` 或 `scons -j10 --verbose` 来编译这个板级支持包，编译正确无误，会产生 rtthread.elf 文件。 - -编译完成后脚本自动调用 `./mksdimg.sh` 脚本进行打包，并生成 `boot.sd`, 该文件即为 SD 卡启动的 kernel 文件。 - - -## 运行 -1. 将 SD 卡分为 2 个分区，第 1 个分区用于存放 bin 文件，第 2 个分区用于作为数据存储分区，分区格式为 `FAT32`。 -2. 将根目录下的 `fip.bin` 和 `boot.sd` 复制 SD 卡第一个分区中。后续更新固件只需要复制 `boot.sd` 文件即可。 -其中： -- fip.bin：fsbl、 opensbi 和 uboot 打包后的 bin 文件 -- boot.sd：kernel 打包后的 bin 文件 - -更新完 `boot.sd` 后， 重新上电可以看到串口的输出信息： -```shell -U-Boot 2021.10 (Jun 26 2023 - 14:09:06 +0800)cvitek_cv180x - -DRAM: 63.3 MiB -gd->relocaddr=0x82435000. offset=0x2235000 -MMC: cv-sd@4310000: 0 -Loading Environment from ... OK -In: serial -Out: serial -Err: serial -Net: -Warning: ethernet@4070000 (eth0) using random MAC address - 62:80:19:6c:d4:64 -eth0: ethernet@4070000 -Hit any key to stop autoboot: 0 -Boot from SD ... -switch to partitions #0, OK -mmc0 is current device -132692 bytes read in 12 ms (10.5 MiB/s) -## Loading kernel from FIT Image at 81400000 ... - Using 'config-cv1800b_milkv_duo_sd' configuration - Trying 'kernel-1' kernel subimage - Verifying Hash Integrity ... crc32+ OK -## Loading fdt from FIT Image at 81400000 ... - Using 'config-cv1800b_milkv_duo_sd' configuration - Trying 'fdt-cv1800b_milkv_duo_sd' fdt subimage - Verifying Hash Integrity ... sha256+ OK - Booting using the fdt blob at 0x8141b590 - Uncompressing Kernel Image - Decompressing 296768 bytes used 42ms - Loading Device Tree to 0000000081be5000, end 0000000081becb60 ... OK - -Starting kernel ... - -heap: [0x802766b0 - 0x812766b0] - - \ | / -- RT - Thread Operating System - / | \ 5.1.0 build Apr 7 2024 23:33:20 - 2006 - 2024 Copyright by RT-Thread team -Hello RISC-V! -msh /> -``` diff --git a/bsp/cvitek/cv18xx_risc-v/README_en.md b/bsp/cvitek/cv18xx_risc-v/README_en.md deleted file mode 100755 index 8a9842e354..0000000000 --- a/bsp/cvitek/cv18xx_risc-v/README_en.md +++ /dev/null @@ -1,147 +0,0 @@ -[中文](README.md) | **English** - -## Overview -The CV18xx series of chips are high-performance, low-power chips launched for various products in the field of civilian consumer surveillance IP cameras, smart homes, and more. These chips integrate H.264/H.265 video compression encoders, as well as ISP; they support various image enhancement and correction algorithms such as digital wide dynamic range, 3D noise reduction, defogging, and lens distortion correction, providing customers with professional-level video image quality. - -1. Processor Core -- Main Processor: RISC-V C906 @ 1.0Ghz - - 32KB I-cache, 64KB D-Cache - - Integrated Vector and Floating-Point Unit (FPU). -- Co-processor: RISC-V C906 @ 700Mhz - - Integrated Floating-Point Unit (FPU) - -2. Storage Interface -- Built-in DRAM: DDR2 16bitx1, with a maximum speed of 1333Mbps, and a capacity of 512Mbit (64MB) -- Support for SPI NOR flash interface (1.8V / 3.0V) - - Supports 1, 2, 4 line modes - - Maximum support of 256MByte -- Support for SPI Nand flash interface (1.8V / 3.0V) - - Supports 1KB/2KB/4KB page (corresponding to maximum capacity of 16GB/32GB/64GB) - - Utilizes the device's built-in ECC module - -3. Peripherals -- Up to 26 GPIO pins on the MilkV-Duo 40-pin header provide access to internal peripherals such as SDIO, I2C, PWM, SPI, J-TAG, and UART -- Up to 3x I2C -- Up to 5x UART -- Up to 1x SDIO1 -- Up to 1x SPI -- Up to 2x ADC -- Up to 7x PWM -- Up to 1x RUN -- Up to 1x JTAG -- Integrated MAC PHY supports 10/100Mbps full or half duplex mode -- One USB host/device interface - -4. [GPIO pinout](https://milkv.io/docs/duo/getting-started/duo256m#gpio-pinout) - -## Toolchain Download -1. RT-Thread Standard Edition Toolchain: `riscv64-unknown-elf-gcc` Download Link [https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1705395512373/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.1-20240115.tar.gz](https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1705395512373/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.1-20240115.tar.gz) - -2. RT-Smart Edition Toolchain: `riscv64-unknown-linux-musl-gcc` Download Link [https://github.com/RT-Thread/toolchains-ci/releases/download/v1.7/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu_latest.tar.bz2](https://github.com/RT-Thread/toolchains-ci/releases/download/v1.7/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu_latest.tar.bz2) - -> Note: -The current bsp only supports Linux compilation, and it is recommended to use Ubuntu 22.04 - -After correctly extracting, add the local path of the `riscv64-unknown-elf-gcc` or `riscv64-unknown-linux-musl-gcc` toolchain to `EXEC_PATH` in `rtconfig.py` or specify the path through the `RTT_EXEC_PATH` environment variable. - -```shell -# For RT-Thread Standard Edition, use the following configuration: -$ export RTT_CC_PREFIX=riscv64-unknown-elf- -$ export RTT_EXEC_PATH=/opt/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.1/bin - -# For RT-Smart Edition, use the following configuration: -$ export RTT_CC_PREFIX=riscv64-unknown-linux-musl- -$ export RTT_EXEC_PATH=/opt/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu/bin -``` - -## Compilation - -### Dependency Installation -```shell -$ sudo apt install -y scons libncurses5-dev device-tree-compiler -``` - -## Modify Current Project Configuration - -For the Linux platform, execute: -```shell -$ scons --menuconfig -``` - -1. By default, compile as RT-Thread Standard Edition. If you need to compile as RT-Smart Edition, modify as follows: -```shell -RT-Thread Kernel ---> - [*] Enable RT-Thread Smart (microkernel on kernel/userland) - - (0x80000000) The virtual address of kernel start -``` - -2. Select the current target development board type: -```shell -Board Type (milkv-duo) ---> - ( ) milkv-duo - ( ) milkv-duo-spinor - (X) milkv-duo256m - ( ) milkv-duo256m-spinor -``` - -It will automatically download relevant scripts to the ~/.env directory, then execute: -```shell -$ source ~/.env/env.sh -$ pkgs --update -``` -After updating the software package, execute `scons -j10` or `scons -j10 --verbose` to compile this board support package. If the compilation is successful, an rtthread.elf file will be generated. - -After the compilation is complete, the script automatically calls the `./mksdimg.sh` script to package and generate `boot.sd`, which is the kernel file for SD card startup. - -## Running -1. Divide the SD card into 2 partitions, with the first partition used to store bin files, and the second partition used as a data storage partition, with `FAT32` format. -2. Copy the `fip.bin` and `boot.sd` files from the root directory to the first partition of the SD card. Subsequent firmware updates only require copying the `boot.sd` file. -Where: -- fip.bin: fsbl, opensbi, and uboot packaged bin file -- boot.sd: kernel packaged bin file - -After updating `boot.sd`, restart to see the serial port output: - -```shell -U-Boot 2021.10 (Jun 26 2023 - 14:09:06 +0800)cvitek_cv180x - -DRAM: 63.3 MiB -gd->relocaddr=0x82435000. offset=0x2235000 -MMC: cv-sd@4310000: 0 -Loading Environment from ... OK -In: serial -Out: serial -Err: serial -Net: -Warning: ethernet@4070000 (eth0) using random MAC address - 62:80:19:6c:d4:64 -eth0: ethernet@4070000 -Hit any key to stop autoboot: 0 -Boot from SD ... -switch to partitions #0, OK -mmc0 is current device -132692 bytes read in 12 ms (10.5 MiB/s) -## Loading kernel from FIT Image at 81400000 ... - Using 'config-cv1800b_milkv_duo_sd' configuration - Trying 'kernel-1' kernel subimage - Verifying Hash Integrity ... crc32+ OK -## Loading fdt from FIT Image at 81400000 ... - Using 'config-cv1800b_milkv_duo_sd' configuration - Trying 'fdt-cv1800b_milkv_duo_sd' fdt subimage - Verifying Hash Integrity ... sha256+ OK - Booting using the fdt blob at 0x8141b590 - Uncompressing Kernel Image - Decompressing 296768 bytes used 42ms - Loading Device Tree to 0000000081be5000, end 0000000081becb60 ... OK - -Starting kernel ... - -heap: [0x802766b0 - 0x812766b0] - - \ | / -- RT - Thread Operating System - / | \ 5.1.0 build Apr 7 2024 23:33:20 - 2006 - 2024 Copyright by RT-Thread team -Hello RISC-V! -msh /> -``` \ No newline at end of file From 79457efc49dd514c45912f6ebeb1e9b672062ffc Mon Sep 17 00:00:00 2001 From: Jiading Xu Date: Sun, 21 Jul 2024 20:30:10 +0800 Subject: [PATCH 39/48] components: net: lwip: port: add netdev callback on link status change setting - set netdev callback on link status change in netdev_add() Signed-off-by: Jiading Xu --- components/net/lwip/port/ethernetif.c | 5 +++++ components/net/netdev/Kconfig | 6 +++++- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/components/net/lwip/port/ethernetif.c b/components/net/lwip/port/ethernetif.c index c88337cdc6..48961704b4 100644 --- a/components/net/lwip/port/ethernetif.c +++ b/components/net/lwip/port/ethernetif.c @@ -421,6 +421,11 @@ static int netdev_add(struct netif *lwip_netif) netdev->gw = lwip_netif->gw; netdev->netmask = lwip_netif->netmask; +#ifdef NETDEV_USING_LINK_STATUS_CALLBACK + extern void netdev_status_change(struct netdev *netdev, enum netdev_cb_type type); + netdev_set_status_callback(netdev, netdev_status_change); +#endif + return result; } diff --git a/components/net/netdev/Kconfig b/components/net/netdev/Kconfig index 5f1697d7ba..b45c279513 100644 --- a/components/net/netdev/Kconfig +++ b/components/net/netdev/Kconfig @@ -19,7 +19,11 @@ if RT_USING_NETDEV config NETDEV_USING_AUTO_DEFAULT bool "Enable default netdev automatic change features" default y - + + config NETDEV_USING_LINK_STATUS_CALLBACK + bool "Enable netdev callback on link status change" + default n + config NETDEV_USING_IPV6 bool "Enable IPV6 protocol support" default n From 08b8dfb225f86d578803d54a2ce92d9c7a139b5b Mon Sep 17 00:00:00 2001 From: Shell Date: Tue, 23 Jul 2024 02:18:50 +0000 Subject: [PATCH 40/48] quality: include the essential only to avoid recursion The rtdef.h is a big header with multiple dependency inside, which makes it easier to introduce recursion dependency. Signed-off-by: Shell --- libcpu/aarch64/common/include/armv8.h | 2 +- libcpu/aarch64/common/include/cpuport.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/libcpu/aarch64/common/include/armv8.h b/libcpu/aarch64/common/include/armv8.h index 5f64f03090..9063a8337d 100644 --- a/libcpu/aarch64/common/include/armv8.h +++ b/libcpu/aarch64/common/include/armv8.h @@ -92,7 +92,7 @@ #else /* !__ASSEMBLY__ */ -#include +#include typedef struct { rt_uint64_t value[2]; } rt_uint128_t; diff --git a/libcpu/aarch64/common/include/cpuport.h b/libcpu/aarch64/common/include/cpuport.h index 217f477aaf..58fe3b145f 100644 --- a/libcpu/aarch64/common/include/cpuport.h +++ b/libcpu/aarch64/common/include/cpuport.h @@ -15,7 +15,7 @@ #include #include -#include +#include #ifdef RT_USING_SMP From 5b828417482ee7329c3f9f551ef234684c51e933 Mon Sep 17 00:00:00 2001 From: heyuanjie87 <943313837@qq.com> Date: Wed, 24 Jul 2024 12:28:50 +0800 Subject: [PATCH 41/48] =?UTF-8?q?[feat]=E6=B7=BB=E5=8A=A0ioremap=E5=85=BC?= =?UTF-8?q?=E5=AE=B9=E5=AE=9A=E4=B9=89=E4=BB=A5=E9=80=82=E5=BA=94smart?= =?UTF-8?q?=E8=BF=90=E8=A1=8C?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- bsp/cvitek/drivers/drv_ioremap.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 bsp/cvitek/drivers/drv_ioremap.h diff --git a/bsp/cvitek/drivers/drv_ioremap.h b/bsp/cvitek/drivers/drv_ioremap.h new file mode 100644 index 0000000000..b616a7697e --- /dev/null +++ b/bsp/cvitek/drivers/drv_ioremap.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024/07/24 heyuanjie87 first version + */ + +#ifndef __DRV_IOREMAP_H__ +#define __DRV_IOREMAP_H__ + +#include + +#ifdef RT_USING_SMART +#include + +#define DRV_IOREMAP(addr, size) rt_ioremap(addr, size) +#define DRV_IOUNMAP(addr) rt_iounmap(addr) +#else +#define DRV_IOREMAP(addr, size) (addr) +#define DRV_IOUNMAP(addr) +#endif + +#endif From 4c2fe22cbe31c287e61e0831cbeeca37e5675f53 Mon Sep 17 00:00:00 2001 From: Z8MAN8 <1468559561@qq.com> Date: Wed, 24 Jul 2024 19:29:46 +0800 Subject: [PATCH 42/48] bsp: cvitek: add missing soc type for aarch64 When compiling CV18xx_arch64, there are the following errors: 1. missing soc type for aarch64 2. uart device objects defined but not used Analysis: a63c07f ("bsp: cvitek: new design for pinmux") and 114e143("bsp:cvitek: add pinmux for uart"), CV18xx_arch64 is not considered. Solution: Refer to the cv18xx_riscv format to add the corresponding chip type SOC_Type_SG2002, as well as the corresponding macro for the serial port pins and interrupts Signed-off-by: Shicheng Chu <1468559561@qq.com> Reviewed-by: Chen Wang --- bsp/cvitek/cv18xx_aarch64/.config | 208 +++++++++++++++++++----- bsp/cvitek/cv18xx_aarch64/Kconfig | 6 + bsp/cvitek/cv18xx_aarch64/board/Kconfig | 88 +++++++--- bsp/cvitek/cv18xx_aarch64/rtconfig.h | 104 ++++++++++-- 4 files changed, 335 insertions(+), 71 deletions(-) diff --git a/bsp/cvitek/cv18xx_aarch64/.config b/bsp/cvitek/cv18xx_aarch64/.config index 1ee98cb4a3..d74cb4e81f 100644 --- a/bsp/cvitek/cv18xx_aarch64/.config +++ b/bsp/cvitek/cv18xx_aarch64/.config @@ -1,7 +1,3 @@ -# -# Automatically generated file; DO NOT EDIT. -# RT-Thread Project Configuration -# # # RT-Thread Kernel @@ -19,7 +15,6 @@ CONFIG_RT_THREAD_PRIORITY_32=y # CONFIG_RT_THREAD_PRIORITY_256 is not set CONFIG_RT_THREAD_PRIORITY_MAX=32 CONFIG_RT_TICK_PER_SECOND=100 -CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y CONFIG_RT_HOOK_USING_FUNC_PTR=y # CONFIG_RT_USING_HOOKLIST is not set @@ -29,11 +24,14 @@ CONFIG_IDLE_THREAD_STACK_SIZE=8192 CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 CONFIG_RT_TIMER_THREAD_STACK_SIZE=8192 +# CONFIG_RT_USING_TIMER_ALL_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set # # kservice optimization # # CONFIG_RT_USING_TINY_FFS is not set +# end of kservice optimization # # klibc optimization @@ -41,11 +39,15 @@ CONFIG_RT_TIMER_THREAD_STACK_SIZE=8192 # CONFIG_RT_KLIBC_USING_STDLIB is not set # CONFIG_RT_KLIBC_USING_TINY_SIZE is not set CONFIG_RT_KLIBC_USING_PRINTF_LONGLONG=y +# end of klibc optimization + CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_ASSERT=y CONFIG_RT_DEBUGING_COLOR=y CONFIG_RT_DEBUGING_CONTEXT=y # CONFIG_RT_DEBUGING_AUTO_INIT is not set # CONFIG_RT_DEBUGING_PAGE_LEAK is not set +CONFIG_RT_USING_OVERFLOW_CHECK=y # # Inter-Thread communication @@ -57,6 +59,7 @@ CONFIG_RT_USING_MAILBOX=y CONFIG_RT_USING_MESSAGEQUEUE=y # CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set # CONFIG_RT_USING_SIGNALS is not set +# end of Inter-Thread communication # # Memory Management @@ -77,6 +80,8 @@ CONFIG_RT_USING_MEMHEAP_AUTO_BINDING=y CONFIG_RT_USING_MEMTRACE=y # CONFIG_RT_USING_HEAP_ISR is not set CONFIG_RT_USING_HEAP=y +# end of Memory Management + CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_DEVICE_OPS=y CONFIG_RT_USING_INTERRUPT_INFO=y @@ -88,6 +93,7 @@ CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" CONFIG_RT_VER_NUM=0x50200 CONFIG_RT_USING_STDC_ATOMIC=y CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# end of RT-Thread Kernel # # AArch64 Architecture Configuration @@ -96,16 +102,19 @@ CONFIG_ARCH_TEXT_OFFSET=0x200000 CONFIG_ARCH_RAM_OFFSET=0x80000000 CONFIG_ARCH_SECONDARY_CPU_STACK_SIZE=4096 CONFIG_ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_ARCH_USING_GENERIC_CPUID=y +CONFIG_ARCH_HEAP_SIZE=0x4000000 +CONFIG_ARCH_INIT_PAGE_SIZE=0x200000 +# end of AArch64 Architecture Configuration + CONFIG_ARCH_CPU_64BIT=y CONFIG_RT_USING_CACHE=y -# CONFIG_RT_USING_HW_ATOMIC is not set -# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set -# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set CONFIG_RT_USING_CPU_FFS=y CONFIG_ARCH_MM_MMU=y CONFIG_ARCH_ARM=y CONFIG_ARCH_ARM_MMU=y CONFIG_ARCH_ARMV8=y +CONFIG_ARCH_USING_HW_THREAD_SELF=y # # RT-Thread Components @@ -165,18 +174,23 @@ CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512 CONFIG_RT_DFS_ELM_REENTRANT=y CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 # CONFIG_RT_DFS_ELM_USE_EXFAT is not set +# end of elm-chan's FatFs, Generic FAT Filesystem Module + CONFIG_RT_USING_DFS_DEVFS=y CONFIG_RT_USING_DFS_ROMFS=y # CONFIG_RT_USING_DFS_ROMFS_USER_ROOT is not set # CONFIG_RT_USING_DFS_CROMFS is not set # CONFIG_RT_USING_DFS_TMPFS is not set # CONFIG_RT_USING_DFS_MQUEUE is not set +# end of DFS: device virtual file system + # CONFIG_RT_USING_FAL is not set # # Device Drivers # CONFIG_RT_USING_DM=y +CONFIG_RT_USING_DEV_BUS=y CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_UNAMED_PIPE_NUMBER=64 CONFIG_RT_USING_SYSTEM_WORKQUEUE=y @@ -197,6 +211,8 @@ CONFIG_RT_USING_NULL=y CONFIG_RT_USING_ZERO=y CONFIG_RT_USING_RANDOM=y # CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set CONFIG_RT_USING_PM=y @@ -214,9 +230,6 @@ CONFIG_PM_TICKLESS_THRESHOLD_TIME=2 # CONFIG_RT_USING_TOUCH is not set # CONFIG_RT_USING_LCD is not set # CONFIG_RT_USING_HWCRYPTO is not set -# CONFIG_RT_USING_PULSE_ENCODER is not set -# CONFIG_RT_USING_INPUT_CAPTURE is not set -CONFIG_RT_USING_DEV_BUS=y # CONFIG_RT_USING_WIFI is not set CONFIG_RT_USING_VIRTIO=y CONFIG_RT_USING_VIRTIO10=y @@ -230,19 +243,15 @@ CONFIG_RT_USING_VIRTIO_INPUT=y CONFIG_RT_USING_OFW=y # CONFIG_RT_USING_BUILTIN_FDT is not set CONFIG_RT_FDT_EARLYCON_MSG_SIZE=128 +CONFIG_RT_USING_OFW_BUS_RANGES_NUMBER=8 # CONFIG_RT_USING_PIC is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_PINCTRL is not set CONFIG_RT_USING_KTIME=y CONFIG_RT_USING_CLK=y # CONFIG_RT_USING_HWTIMER is not set - -# -# Using USB -# -# CONFIG_RT_USING_USB is not set -# CONFIG_RT_USING_USB_HOST is not set -# CONFIG_RT_USING_USB_DEVICE is not set +# CONFIG_RT_USING_CHERRYUSB is not set +# end of Device Drivers # # C/C++ and POSIX layer @@ -260,6 +269,8 @@ CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 +# end of Timezone and Daylight Saving Time +# end of ISO-ANSI C layer # # POSIX (Portable Operating System Interface) layer @@ -292,7 +303,11 @@ CONFIG_RT_USING_POSIX_PIPE_SIZE=512 # # Socket is in the 'Network' category # +# end of Interprocess Communication (IPC) +# end of POSIX (Portable Operating System Interface) layer + # CONFIG_RT_USING_CPLUSPLUS is not set +# end of C/C++ and POSIX layer # # Network @@ -301,12 +316,14 @@ CONFIG_RT_USING_POSIX_PIPE_SIZE=512 # CONFIG_RT_USING_NETDEV is not set # CONFIG_RT_USING_LWIP is not set # CONFIG_RT_USING_AT is not set +# end of Network # # Memory protection # # CONFIG_RT_USING_MEM_PROTECTION is not set # CONFIG_RT_USING_HW_STACK_GUARD is not set +# end of Memory protection # # Utilities @@ -322,12 +339,26 @@ CONFIG_RT_USING_ADT_BITMAP=y CONFIG_RT_USING_ADT_HASHMAP=y CONFIG_RT_USING_ADT_REF=y # CONFIG_RT_USING_RT_LINK is not set +# end of Utilities + # CONFIG_RT_USING_VBUS is not set +CONFIG_RT_USING_MEMBLOCK=y + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set +# end of RT-Thread Components # # RT-Thread Utestcases # # CONFIG_RT_USING_UTESTCASES is not set +# end of RT-Thread Utestcases # # RT-Thread online packages @@ -336,7 +367,6 @@ CONFIG_RT_USING_ADT_REF=y # # IoT - internet of things # -# CONFIG_PKG_USING_LWIP is not set # CONFIG_PKG_USING_LORAWAN_DRIVER is not set # CONFIG_PKG_USING_PAHOMQTT is not set # CONFIG_PKG_USING_UMQTT is not set @@ -349,6 +379,7 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set # # Wi-Fi @@ -358,27 +389,35 @@ CONFIG_RT_USING_ADT_REF=y # Marvell WiFi # # CONFIG_PKG_USING_WLANMARVELL is not set +# end of Marvell WiFi # # Wiced WiFi # # CONFIG_PKG_USING_WLAN_WICED is not set +# end of Wiced WiFi + # CONFIG_PKG_USING_RW007 is not set # # CYW43012 WiFi # # CONFIG_PKG_USING_WLAN_CYW43012 is not set +# end of CYW43012 WiFi # # BL808 WiFi # # CONFIG_PKG_USING_WLAN_BL808 is not set +# end of BL808 WiFi # # CYW43439 WiFi # # CONFIG_PKG_USING_WLAN_CYW43439 is not set +# end of CYW43439 WiFi +# end of Wi-Fi + # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set @@ -401,6 +440,8 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set # CONFIG_PKG_USING_JOYLINK is not set # CONFIG_PKG_USING_IOTSHARP_SDK is not set +# end of IoT Cloud + # CONFIG_PKG_USING_NIMBLE is not set # CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set # CONFIG_PKG_USING_OTA_DOWNLOADER is not set @@ -443,6 +484,8 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_ZEPHYR_POLLING is not set # CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set # CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set +# end of IoT - internet of things # # security packages @@ -453,6 +496,7 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_TINYCRYPT is not set # CONFIG_PKG_USING_TFM is not set # CONFIG_PKG_USING_YD_CRYPTO is not set +# end of security packages # # language packages @@ -468,18 +512,23 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_JSMN is not set # CONFIG_PKG_USING_AGILE_JSMN is not set # CONFIG_PKG_USING_PARSON is not set +# CONFIG_PKG_USING_RYAN_JSON is not set +# end of JSON: JavaScript Object Notation, a lightweight data-interchange format # # XML: Extensible Markup Language # # CONFIG_PKG_USING_SIMPLE_XML is not set # CONFIG_PKG_USING_EZXML is not set +# end of XML: Extensible Markup Language + # CONFIG_PKG_USING_LUATOS_SOC is not set # CONFIG_PKG_USING_LUA is not set # CONFIG_PKG_USING_JERRYSCRIPT is not set # CONFIG_PKG_USING_MICROPYTHON is not set # CONFIG_PKG_USING_PIKASCRIPT is not set # CONFIG_PKG_USING_RTT_RUST is not set +# end of language packages # # multimedia packages @@ -491,12 +540,15 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_LVGL is not set # CONFIG_PKG_USING_LV_MUSIC_DEMO is not set # CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set +# end of LVGL: powerful and easy-to-use embedded GUI library # # u8g2: a monochrome graphic library # # CONFIG_PKG_USING_U8G2_OFFICIAL is not set # CONFIG_PKG_USING_U8G2 is not set +# end of u8g2: a monochrome graphic library + # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set # CONFIG_PKG_USING_STEMWIN is not set @@ -516,6 +568,7 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_GUIENGINE is not set # CONFIG_PKG_USING_3GPP_AMRNB is not set +# end of multimedia packages # # tools packages @@ -564,6 +617,7 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set # CONFIG_PKG_USING_VOFA_PLUS is not set # CONFIG_PKG_USING_ZDEBUG is not set +# end of tools packages # # system packages @@ -575,6 +629,9 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_RT_MEMCPY_CM is not set # CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set # CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set +# end of enhanced kernel services + +# CONFIG_PKG_USING_AUNITY is not set # # acceleration: Assembly language or algorithmic acceleration packages @@ -582,13 +639,18 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_QFPLIB_M0_FULL is not set # CONFIG_PKG_USING_QFPLIB_M0_TINY is not set # CONFIG_PKG_USING_QFPLIB_M3 is not set +# end of acceleration: Assembly language or algorithmic acceleration packages # # CMSIS: ARM Cortex-M Microcontroller Software Interface Standard # # CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_CORE is not set +# CONFIG_PKG_USING_CMSIS_DSP is not set +# CONFIG_PKG_USING_CMSIS_NN is not set # CONFIG_PKG_USING_CMSIS_RTOS1 is not set # CONFIG_PKG_USING_CMSIS_RTOS2 is not set +# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard # # Micrium: Micrium software products porting for RT-Thread @@ -599,6 +661,8 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_UC_CLK is not set # CONFIG_PKG_USING_UC_COMMON is not set # CONFIG_PKG_USING_UC_MODBUS is not set +# end of Micrium: Micrium software products porting for RT-Thread + # CONFIG_PKG_USING_FREERTOS_WRAPPER is not set # CONFIG_PKG_USING_LITEOS_SDK is not set # CONFIG_PKG_USING_TZ_DATABASE is not set @@ -646,11 +710,58 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_RTP is not set # CONFIG_PKG_USING_REB is not set # CONFIG_PKG_USING_R_RHEALSTONE is not set +# end of system packages # # peripheral libraries and drivers # +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# end of STM32 HAL & SDK Drivers + +# +# Infineon HAL Packages +# +# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set +# CONFIG_PKG_USING_INFINEON_CMSIS is not set +# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set +# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set +# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set +# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set +# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set +# CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_ESP_IDF is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# end of Kendryte SDK + +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# end of HAL & SDK Drivers + # # sensors drivers # @@ -719,6 +830,7 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_ICM20608 is not set # CONFIG_PKG_USING_PAJ7620 is not set # CONFIG_PKG_USING_STHS34PF80 is not set +# end of sensors drivers # # touch drivers @@ -732,9 +844,10 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_FT6236 is not set # CONFIG_PKG_USING_XPT2046_TOUCH is not set # CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# end of touch drivers + # CONFIG_PKG_USING_REALTEK_AMEBA is not set -# CONFIG_PKG_USING_STM32_SDIO is not set -# CONFIG_PKG_USING_ESP_IDF is not set # CONFIG_PKG_USING_BUTTON is not set # CONFIG_PKG_USING_PCF8574 is not set # CONFIG_PKG_USING_SX12XX is not set @@ -742,14 +855,6 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_LEDBLINK is not set # CONFIG_PKG_USING_LITTLED is not set # CONFIG_PKG_USING_LKDGUI is not set -# CONFIG_PKG_USING_NRF5X_SDK is not set -# CONFIG_PKG_USING_NRFX is not set - -# -# Kendryte SDK -# -# CONFIG_PKG_USING_K210_SDK is not set -# CONFIG_PKG_USING_KENDRYTE_SDK is not set # CONFIG_PKG_USING_INFRARED is not set # CONFIG_PKG_USING_MULTI_INFRARED is not set # CONFIG_PKG_USING_AGILE_BUTTON is not set @@ -764,7 +869,6 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_AS608 is not set # CONFIG_PKG_USING_RC522 is not set # CONFIG_PKG_USING_WS2812B is not set -# CONFIG_PKG_USING_EMBARC_BSP is not set # CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set # CONFIG_PKG_USING_MULTI_RTIMER is not set # CONFIG_PKG_USING_MAX7219 is not set @@ -787,7 +891,6 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_VIRTUAL_SENSOR is not set # CONFIG_PKG_USING_VDEVICE is not set # CONFIG_PKG_USING_SGM706 is not set -# CONFIG_PKG_USING_STM32WB55_SDK is not set # CONFIG_PKG_USING_RDA58XX is not set # CONFIG_PKG_USING_LIBNFC is not set # CONFIG_PKG_USING_MFOC is not set @@ -797,7 +900,6 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_ROSSERIAL is not set # CONFIG_PKG_USING_MICRO_ROS is not set # CONFIG_PKG_USING_MCP23008 is not set -# CONFIG_PKG_USING_BLUETRUM_SDK is not set # CONFIG_PKG_USING_MISAKA_AT24CXX is not set # CONFIG_PKG_USING_MISAKA_RGB_BLING is not set # CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set @@ -805,7 +907,6 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_MB85RS16 is not set # CONFIG_PKG_USING_RFM300 is not set # CONFIG_PKG_USING_IO_INPUT_FILTER is not set -# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set # CONFIG_PKG_USING_LRF_NV7LIDAR is not set # CONFIG_PKG_USING_AIP650 is not set # CONFIG_PKG_USING_FINGERPRINT is not set @@ -816,7 +917,10 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_X9555 is not set # CONFIG_PKG_USING_SYSTEM_RUN_LED is not set # CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_BT_MX02 is not set # CONFIG_PKG_USING_SPI_TOOLS is not set +# end of peripheral libraries and drivers # # AI packages @@ -832,15 +936,18 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_NAXOS is not set # CONFIG_PKG_USING_NCNN is not set # CONFIG_PKG_USING_R_TINYMAIX is not set +# end of AI packages # # Signal Processing and Control Algorithm Packages # +# CONFIG_PKG_USING_APID is not set # CONFIG_PKG_USING_FIRE_PID_CURVE is not set # CONFIG_PKG_USING_QPID is not set # CONFIG_PKG_USING_UKAL is not set # CONFIG_PKG_USING_DIGITALCTRL is not set # CONFIG_PKG_USING_KISSFFT is not set +# end of Signal Processing and Control Algorithm Packages # # miscellaneous packages @@ -849,6 +956,7 @@ CONFIG_RT_USING_ADT_REF=y # # project laboratory # +# end of project laboratory # # samples: kernel and components samples @@ -857,6 +965,7 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set # CONFIG_PKG_USING_NETWORK_SAMPLES is not set # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# end of samples: kernel and components samples # # entertainment: terminal games and other interesting software packages @@ -872,6 +981,8 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_DONUT is not set # CONFIG_PKG_USING_COWSAY is not set # CONFIG_PKG_USING_MORSE is not set +# end of entertainment: terminal games and other interesting software packages + # CONFIG_PKG_USING_LIBCSV is not set # CONFIG_PKG_USING_OPTPARSE is not set # CONFIG_PKG_USING_FASTLZ is not set @@ -905,6 +1016,7 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_SOEM is not set # CONFIG_PKG_USING_QPARAM is not set # CONFIG_PKG_USING_CorevMCU_CLI is not set +# end of miscellaneous packages # # Arduino libraries @@ -920,6 +1032,7 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set # CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set # CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set +# end of Projects and Demos # # Sensors @@ -1059,6 +1172,8 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set # CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set # CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set +# end of Sensors # # Display @@ -1070,6 +1185,7 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set # CONFIG_PKG_USING_SEEED_TM1637 is not set +# end of Display # # Timing @@ -1078,6 +1194,7 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set # CONFIG_PKG_USING_ARDUINO_TICKER is not set # CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set +# end of Timing # # Data Processing @@ -1085,6 +1202,8 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set # CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set # CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set +# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set +# end of Data Processing # # Data Storage @@ -1095,6 +1214,7 @@ CONFIG_RT_USING_ADT_REF=y # # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set +# end of Communication # # Device Control @@ -1106,12 +1226,14 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set # CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# end of Device Control # # Other # # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# end of Other # # Signal IO @@ -1124,11 +1246,18 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set +# end of Signal IO # # Uncategorized # +# end of Arduino libraries +# end of RT-Thread online packages + CONFIG_SOC_CV18XX_AARCH64=y +CONFIG_GPIO_IRQ_BASE=76 +CONFIG_SYS_GPIO_IRQ_BASE=86 +CONFIG_SOC_TYPE_SG2002=y CONFIG_BOARD_TYPE_MILKV_DUO256M=y # CONFIG_BOARD_TYPE_MILKV_DUO256M_SPINOR is not set @@ -1140,12 +1269,15 @@ CONFIG_BSP_USING_GIC=y CONFIG_BSP_USING_GICV2=y # CONFIG_BSP_USING_GICV3 is not set CONFIG_BSP_USING_UART=y -CONFIG_RT_USING_UART0=y +CONFIG_BSP_USING_UART0=y +CONFIG_BSP_UART0_RX_PINNAME="UART0_RX" +CONFIG_BSP_UART0_TX_PINNAME="UART0_TX" +# CONFIG_BSP_USING_UART1 is not set +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_UART4 is not set CONFIG_UART_IRQ_BASE=60 -# CONFIG_RT_USING_UART1 is not set -# CONFIG_RT_USING_UART2 is not set -# CONFIG_RT_USING_UART3 is not set -# CONFIG_RT_USING_UART4 is not set # CONFIG_BSP_USING_ADC is not set # CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_PWM is not set +# end of General Drivers Configuration diff --git a/bsp/cvitek/cv18xx_aarch64/Kconfig b/bsp/cvitek/cv18xx_aarch64/Kconfig index 4f7a160a25..daa0de51ab 100644 --- a/bsp/cvitek/cv18xx_aarch64/Kconfig +++ b/bsp/cvitek/cv18xx_aarch64/Kconfig @@ -30,14 +30,20 @@ config SYS_GPIO_IRQ_BASE int default 86 +config SOC_TYPE_SG2002 + bool + default n + choice prompt "Board Type" default BOARD_TYPE_MILKV_DUO256M config BOARD_TYPE_MILKV_DUO256M + select SOC_TYPE_SG2002 bool "milkv-duo256m" config BOARD_TYPE_MILKV_DUO256M_SPINOR + select SOC_TYPE_SG2002 bool "milkv-duo256m-spinor" endchoice diff --git a/bsp/cvitek/cv18xx_aarch64/board/Kconfig b/bsp/cvitek/cv18xx_aarch64/board/Kconfig index a7e559a1a4..cd8e62193c 100755 --- a/bsp/cvitek/cv18xx_aarch64/board/Kconfig +++ b/bsp/cvitek/cv18xx_aarch64/board/Kconfig @@ -24,30 +24,74 @@ menu "General Drivers Configuration" default y if BSP_USING_UART - config RT_USING_UART0 - bool "Enable UART 0" - default y + config BSP_USING_UART0 + bool "Enable UART 0" + default y + + if BSP_USING_UART0 + config BSP_UART0_RX_PINNAME + string "uart0 rx pin name" + default "UART0_RX" + config BSP_UART0_TX_PINNAME + string "uart0 tx pin name" + default "UART0_TX" + endif + + config BSP_USING_UART1 + bool "Enable UART 1" + default n + + if BSP_USING_UART1 + config BSP_UART1_RX_PINNAME + string "uart1 rx pin name" + default "" + config BSP_UART1_TX_PINNAME + string "uart1 tx pin name" + default "" + endif + + config BSP_USING_UART2 + bool "Enable UART 2" + default n + + if BSP_USING_UART2 + config BSP_UART2_RX_PINNAME + string "uart2 rx pin name" + default "" + config BSP_UART2_TX_PINNAME + string "uart2 tx pin name" + default "" + endif + + config BSP_USING_UART3 + bool "Enable UART 3" + default n + + if BSP_USING_UART3 + config BSP_UART3_RX_PINNAME + string "uart3 rx pin name" + default "" + config BSP_UART3_TX_PINNAME + string "uart3 tx pin name" + default "" + endif + + config BSP_USING_UART4 + bool "Enable UART 4" + default n + + if BSP_USING_UART4 + config BSP_UART4_RX_PINNAME + string "uart4 rx pin name" + default "" + config BSP_UART4_TX_PINNAME + string "uart4 tx pin name" + default "" + endif config UART_IRQ_BASE - int - default 60 - - config RT_USING_UART1 - bool "Enable UART 1" - default n - - config RT_USING_UART2 - bool "Enable UART 2" - default n - - config RT_USING_UART3 - bool "Enable UART 3" - default n - - config RT_USING_UART4 - bool "Enable UART 4" - default n - + int + default 60 endif config BSP_USING_ADC diff --git a/bsp/cvitek/cv18xx_aarch64/rtconfig.h b/bsp/cvitek/cv18xx_aarch64/rtconfig.h index a418f2da0c..18e4a7c732 100644 --- a/bsp/cvitek/cv18xx_aarch64/rtconfig.h +++ b/bsp/cvitek/cv18xx_aarch64/rtconfig.h @@ -1,9 +1,6 @@ #ifndef RT_CONFIG_H__ #define RT_CONFIG_H__ -/* Automatically generated file; DO NOT EDIT. */ -/* RT-Thread Project Configuration */ - /* RT-Thread Kernel */ #define RT_NAME_MAX 16 @@ -12,7 +9,6 @@ #define RT_THREAD_PRIORITY_32 #define RT_THREAD_PRIORITY_MAX 32 #define RT_TICK_PER_SECOND 100 -#define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK @@ -24,13 +20,17 @@ /* kservice optimization */ +/* end of kservice optimization */ /* klibc optimization */ #define RT_KLIBC_USING_PRINTF_LONGLONG +/* end of klibc optimization */ #define RT_USING_DEBUG +#define RT_DEBUGING_ASSERT #define RT_DEBUGING_COLOR #define RT_DEBUGING_CONTEXT +#define RT_USING_OVERFLOW_CHECK /* Inter-Thread communication */ @@ -39,6 +39,7 @@ #define RT_USING_EVENT #define RT_USING_MAILBOX #define RT_USING_MESSAGEQUEUE +/* end of Inter-Thread communication */ /* Memory Management */ @@ -51,6 +52,7 @@ #define RT_USING_MEMHEAP_AUTO_BINDING #define RT_USING_MEMTRACE #define RT_USING_HEAP +/* end of Memory Management */ #define RT_USING_DEVICE #define RT_USING_DEVICE_OPS #define RT_USING_INTERRUPT_INFO @@ -61,6 +63,7 @@ #define RT_VER_NUM 0x50200 #define RT_USING_STDC_ATOMIC #define RT_BACKTRACE_LEVEL_MAX_NR 32 +/* end of RT-Thread Kernel */ /* AArch64 Architecture Configuration */ @@ -68,6 +71,10 @@ #define ARCH_RAM_OFFSET 0x80000000 #define ARCH_SECONDARY_CPU_STACK_SIZE 4096 #define ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS +#define ARCH_USING_GENERIC_CPUID +#define ARCH_HEAP_SIZE 0x4000000 +#define ARCH_INIT_PAGE_SIZE 0x200000 +/* end of AArch64 Architecture Configuration */ #define ARCH_CPU_64BIT #define RT_USING_CACHE #define RT_USING_CPU_FFS @@ -75,6 +82,7 @@ #define ARCH_ARM #define ARCH_ARM_MMU #define ARCH_ARMV8 +#define ARCH_USING_HW_THREAD_SELF /* RT-Thread Components */ @@ -119,12 +127,15 @@ #define RT_DFS_ELM_MAX_SECTOR_SIZE 512 #define RT_DFS_ELM_REENTRANT #define RT_DFS_ELM_MUTEX_TIMEOUT 3000 +/* end of elm-chan's FatFs, Generic FAT Filesystem Module */ #define RT_USING_DFS_DEVFS #define RT_USING_DFS_ROMFS +/* end of DFS: device virtual file system */ /* Device Drivers */ #define RT_USING_DM +#define RT_USING_DEV_BUS #define RT_USING_DEVICE_IPC #define RT_UNAMED_PIPE_NUMBER 64 #define RT_USING_SYSTEM_WORKQUEUE @@ -139,7 +150,6 @@ #define RT_USING_RANDOM #define RT_USING_PM #define PM_TICKLESS_THRESHOLD_TIME 2 -#define RT_USING_DEV_BUS #define RT_USING_VIRTIO #define RT_USING_VIRTIO10 #define RT_USING_VIRTIO_MMIO_ALIGN @@ -150,12 +160,11 @@ #define RT_USING_VIRTIO_INPUT #define RT_USING_OFW #define RT_FDT_EARLYCON_MSG_SIZE 128 +#define RT_USING_OFW_BUS_RANGES_NUMBER 8 #define RT_USING_PIN #define RT_USING_KTIME #define RT_USING_CLK - -/* Using USB */ - +/* end of Device Drivers */ /* C/C++ and POSIX layer */ @@ -167,6 +176,8 @@ #define RT_LIBC_TZ_DEFAULT_HOUR 8 #define RT_LIBC_TZ_DEFAULT_MIN 0 #define RT_LIBC_TZ_DEFAULT_SEC 0 +/* end of Timezone and Daylight Saving Time */ +/* end of ISO-ANSI C layer */ /* POSIX (Portable Operating System Interface) layer */ @@ -187,12 +198,17 @@ /* Socket is in the 'Network' category */ +/* end of Interprocess Communication (IPC) */ +/* end of POSIX (Portable Operating System Interface) layer */ +/* end of C/C++ and POSIX layer */ /* Network */ +/* end of Network */ /* Memory protection */ +/* end of Memory protection */ /* Utilities */ @@ -202,9 +218,17 @@ #define RT_USING_ADT_BITMAP #define RT_USING_ADT_HASHMAP #define RT_USING_ADT_REF +/* end of Utilities */ +#define RT_USING_MEMBLOCK + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ +/* end of RT-Thread Components */ /* RT-Thread Utestcases */ +/* end of RT-Thread Utestcases */ /* RT-Thread online packages */ @@ -215,122 +239,177 @@ /* Marvell WiFi */ +/* end of Marvell WiFi */ /* Wiced WiFi */ +/* end of Wiced WiFi */ /* CYW43012 WiFi */ +/* end of CYW43012 WiFi */ /* BL808 WiFi */ +/* end of BL808 WiFi */ /* CYW43439 WiFi */ +/* end of CYW43439 WiFi */ +/* end of Wi-Fi */ /* IoT Cloud */ +/* end of IoT Cloud */ +/* end of IoT - internet of things */ /* security packages */ +/* end of security packages */ /* language packages */ /* JSON: JavaScript Object Notation, a lightweight data-interchange format */ +/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */ /* XML: Extensible Markup Language */ +/* end of XML: Extensible Markup Language */ +/* end of language packages */ /* multimedia packages */ /* LVGL: powerful and easy-to-use embedded GUI library */ +/* end of LVGL: powerful and easy-to-use embedded GUI library */ /* u8g2: a monochrome graphic library */ +/* end of u8g2: a monochrome graphic library */ +/* end of multimedia packages */ /* tools packages */ +/* end of tools packages */ /* system packages */ /* enhanced kernel services */ +/* end of enhanced kernel services */ /* acceleration: Assembly language or algorithmic acceleration packages */ +/* end of acceleration: Assembly language or algorithmic acceleration packages */ /* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ +/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ /* Micrium: Micrium software products porting for RT-Thread */ +/* end of Micrium: Micrium software products porting for RT-Thread */ +/* end of system packages */ /* peripheral libraries and drivers */ -/* sensors drivers */ +/* HAL & SDK Drivers */ +/* STM32 HAL & SDK Drivers */ -/* touch drivers */ +/* end of STM32 HAL & SDK Drivers */ +/* Infineon HAL Packages */ + +/* end of Infineon HAL Packages */ /* Kendryte SDK */ +/* end of Kendryte SDK */ +/* end of HAL & SDK Drivers */ + +/* sensors drivers */ + +/* end of sensors drivers */ + +/* touch drivers */ + +/* end of touch drivers */ +/* end of peripheral libraries and drivers */ /* AI packages */ +/* end of AI packages */ /* Signal Processing and Control Algorithm Packages */ +/* end of Signal Processing and Control Algorithm Packages */ /* miscellaneous packages */ /* project laboratory */ +/* end of project laboratory */ + /* samples: kernel and components samples */ +/* end of samples: kernel and components samples */ /* entertainment: terminal games and other interesting software packages */ +/* end of entertainment: terminal games and other interesting software packages */ +/* end of miscellaneous packages */ /* Arduino libraries */ /* Projects and Demos */ +/* end of Projects and Demos */ /* Sensors */ +/* end of Sensors */ /* Display */ +/* end of Display */ /* Timing */ +/* end of Timing */ /* Data Processing */ +/* end of Data Processing */ /* Data Storage */ /* Communication */ +/* end of Communication */ /* Device Control */ +/* end of Device Control */ /* Other */ +/* end of Other */ /* Signal IO */ +/* end of Signal IO */ /* Uncategorized */ +/* end of Arduino libraries */ +/* end of RT-Thread online packages */ #define SOC_CV18XX_AARCH64 #define GPIO_IRQ_BASE 76 #define SYS_GPIO_IRQ_BASE 86 +#define SOC_TYPE_SG2002 #define BOARD_TYPE_MILKV_DUO256M /* General Drivers Configuration */ @@ -339,7 +418,10 @@ #define BSP_USING_GIC #define BSP_USING_GICV2 #define BSP_USING_UART -#define RT_USING_UART0 +#define BSP_USING_UART0 +#define BSP_UART0_RX_PINNAME "UART0_RX" +#define BSP_UART0_TX_PINNAME "UART0_TX" #define UART_IRQ_BASE 60 +/* end of General Drivers Configuration */ #endif From 84eea6c654f9941089e100244b3488771a6f1d1e Mon Sep 17 00:00:00 2001 From: Z8MAN8 <1468559561@qq.com> Date: Wed, 24 Jul 2024 19:44:52 +0800 Subject: [PATCH 43/48] bsp: cviteK: update board init for aarch64 When compiling CV18xx_arch64, have a error: can not find "rt_fdt_commit_memregion_early" Analysis: b785ef9 ("[libcpu][aarch64]memory setup using memblock ") no longer support "rt_fdt_commit_memregion_early", become use "rt_memblock_reserve_memory" Solution: Refer to the bsp/qemu-virt64-aarch64/drivers/board.c delete "rt_fdt_commit_memregion_early" Signed-off-by: Shicheng Chu <1468559561@qq.com> Reviewed-by: Chen Wang --- bsp/cvitek/cv18xx_aarch64/board/board.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/bsp/cvitek/cv18xx_aarch64/board/board.c b/bsp/cvitek/cv18xx_aarch64/board/board.c index f2edb9b5cb..de7778704f 100644 --- a/bsp/cvitek/cv18xx_aarch64/board/board.c +++ b/bsp/cvitek/cv18xx_aarch64/board/board.c @@ -79,13 +79,6 @@ void rt_hw_board_init(void) #else void rt_hw_board_init(void) { - rt_fdt_commit_memregion_early(&(rt_region_t) - { - .name = "memheap", - .start = (rt_size_t)rt_kmem_v2p((void *)HEAP_BEGIN), - .end = (rt_size_t)rt_kmem_v2p((void *)HEAP_END), - }, RT_TRUE); - rt_hw_common_setup(); } #endif /* RT_USING_OFW */ From 57bca1a07274cef3c9a72aedeabb7cf7ffa27550 Mon Sep 17 00:00:00 2001 From: kurisaw <2053731441@qq.com> Date: Wed, 24 Jul 2024 09:30:38 +0800 Subject: [PATCH 44/48] [sensor_v2] Repair an error occurs when sensor v2 probes a sensor device for the first time --- components/drivers/sensor/v2/sensor_cmd.c | 26 ++++++++++++----------- 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/components/drivers/sensor/v2/sensor_cmd.c b/components/drivers/sensor/v2/sensor_cmd.c index e278f349de..1b65c0058d 100644 --- a/components/drivers/sensor/v2/sensor_cmd.c +++ b/components/drivers/sensor/v2/sensor_cmd.c @@ -550,7 +550,7 @@ static void sensor_cmd_warning_probe(void) LOG_W("Please probe sensor device first!"); } -static void sensor(int argc, char **argv) +static int sensor(int argc, char **argv) { static rt_device_t dev = RT_NULL; struct rt_sensor_data data; @@ -562,14 +562,14 @@ static void sensor(int argc, char **argv) if (argc < 2) { sensor_cmd_warning_unknown(); - return; + return -RT_ERROR; } else if (!rt_strcmp(argv[1], "info")) { if (dev == RT_NULL) { sensor_cmd_warning_probe(); - return ; + return -RT_ERROR; } sensor = (rt_sensor_t)dev; rt_kprintf("name :%s\n", sensor->info.name); @@ -595,7 +595,7 @@ static void sensor(int argc, char **argv) if (dev == RT_NULL) { sensor_cmd_warning_probe(); - return; + return -RT_ERROR; } if (argc == 3) { @@ -628,7 +628,7 @@ static void sensor(int argc, char **argv) information = rt_object_get_information(RT_Object_Class_Device); if(information == RT_NULL) - return; + return -RT_ERROR; rt_kprintf("device name sensor name sensor type mode resolution range\n"); rt_kprintf("----------- ------------- ------------------ ---- ---------- ----------\n"); @@ -655,7 +655,7 @@ static void sensor(int argc, char **argv) if (dev == RT_NULL) { sensor_cmd_warning_probe(); - return; + return -RT_ERROR; } if (rt_device_control(dev, RT_SENSOR_CTRL_SOFT_RESET, RT_NULL) != RT_EOK) @@ -671,19 +671,19 @@ static void sensor(int argc, char **argv) if (argc < 3) { sensor_cmd_warning_unknown(); - return; + return -RT_ERROR; } new_dev = rt_device_find(argv[2]); if (new_dev == RT_NULL) { LOG_E("Can't find device:%s", argv[2]); - return; + return -RT_ERROR; } if (rt_device_open(new_dev, RT_DEVICE_FLAG_RDWR) != RT_EOK) { LOG_E("open device failed!"); - return; + return -RT_ERROR; } if (rt_device_control(new_dev, RT_SENSOR_CTRL_GET_ID, ®) == RT_EOK) { @@ -702,7 +702,7 @@ static void sensor(int argc, char **argv) if (dev == RT_NULL) { sensor_cmd_warning_probe(); - return; + return -RT_ERROR; } sensor = (rt_sensor_t)dev; @@ -734,7 +734,7 @@ static void sensor(int argc, char **argv) if (dev == RT_NULL) { sensor_cmd_warning_probe(); - return; + return -RT_ERROR; } sensor = (rt_sensor_t)dev; @@ -766,7 +766,7 @@ static void sensor(int argc, char **argv) if (dev == RT_NULL) { sensor_cmd_warning_probe(); - return; + return -RT_ERROR; } sensor = (rt_sensor_t)dev; @@ -795,5 +795,7 @@ static void sensor(int argc, char **argv) { sensor_cmd_warning_unknown(); } + + return RT_EOK; } MSH_CMD_EXPORT(sensor, sensor test function); From ab11bd04bfdb8b190f7e96a8a6a1f5be43979975 Mon Sep 17 00:00:00 2001 From: kurisaw <2053731441@qq.com> Date: Wed, 24 Jul 2024 09:43:33 +0800 Subject: [PATCH 45/48] Synchronizing sensor_v1 changes --- components/drivers/sensor/v1/sensor_cmd.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/components/drivers/sensor/v1/sensor_cmd.c b/components/drivers/sensor/v1/sensor_cmd.c index 0410af4853..cb98385b79 100644 --- a/components/drivers/sensor/v1/sensor_cmd.c +++ b/components/drivers/sensor/v1/sensor_cmd.c @@ -281,7 +281,7 @@ static void sensor_polling(int argc, char **argv) MSH_CMD_EXPORT(sensor_polling, Sensor polling mode test function); #endif -static void sensor(int argc, char **argv) +static int sensor(int argc, char **argv) { static rt_device_t dev = RT_NULL; struct rt_sensor_data data; @@ -310,7 +310,7 @@ static void sensor(int argc, char **argv) if (dev == RT_NULL) { LOG_W("Please probe sensor device first!"); - return ; + return -RT_ERROR; } rt_device_control(dev, RT_SENSOR_CTRL_GET_INFO, &info); switch (info.vendor) @@ -431,7 +431,7 @@ static void sensor(int argc, char **argv) if (dev == RT_NULL) { LOG_W("Please probe sensor device first!"); - return ; + return -RT_ERROR; } if (argc == 3) { @@ -469,12 +469,12 @@ static void sensor(int argc, char **argv) if (dev == RT_NULL) { LOG_E("Can't find device:%s", argv[2]); - return; + return -RT_ERROR; } if (rt_device_open(dev, RT_DEVICE_FLAG_RDWR) != RT_EOK) { LOG_E("open device failed!"); - return; + return -RT_ERROR; } rt_device_control(dev, RT_SENSOR_CTRL_GET_ID, ®); LOG_I("device id: 0x%x!", reg); @@ -483,7 +483,7 @@ static void sensor(int argc, char **argv) else if (dev == RT_NULL) { LOG_W("Please probe sensor first!"); - return ; + return -RT_ERROR; } else if (!strcmp(argv[1], "sr")) { @@ -510,6 +510,8 @@ static void sensor(int argc, char **argv) { LOG_W("Unknown command, please enter 'sensor' get help information!"); } + + return RT_EOK; } #ifdef RT_USING_FINSH MSH_CMD_EXPORT(sensor, sensor test function); From c8914c7f2bd4109bdb7f01f388bbc09e5e15c9a9 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Tue, 23 Jul 2024 13:58:24 +0800 Subject: [PATCH 46/48] bsp: cvitek: fixed stacksize issue In the original Sconstruct script, `GetDepend('__STACKSIZE__')` is placed before the call to `PrepareBuilding()`, which causes the value of `GetDepend('__STACKSIZE__')` to always be False, and the value of `__STACKSIZE__` in `link_stacksize.lds` will not be updated. Solution: move the call if `PrepareBuilding()` ahead. Also sync and update the .config and rtconfig.h, plus the link_stacksize.lds. Signed-off-by: Chen Wang --- bsp/cvitek/cv18xx_risc-v/.config | 66 --------------------- bsp/cvitek/cv18xx_risc-v/SConstruct | 15 ++--- bsp/cvitek/cv18xx_risc-v/link_stacksize.lds | 2 +- bsp/cvitek/cv18xx_risc-v/rtconfig.h | 12 ---- 4 files changed, 9 insertions(+), 86 deletions(-) diff --git a/bsp/cvitek/cv18xx_risc-v/.config b/bsp/cvitek/cv18xx_risc-v/.config index ff74894dde..60365a528c 100644 --- a/bsp/cvitek/cv18xx_risc-v/.config +++ b/bsp/cvitek/cv18xx_risc-v/.config @@ -1299,72 +1299,6 @@ CONFIG_RT_USING_ADT_REF=y # end of Arduino libraries # end of RT-Thread online packages -# -# Privated Packages of RealThread -# -# CONFIG_PKG_USING_CODEC is not set -# CONFIG_PKG_USING_PLAYER is not set -# CONFIG_PKG_USING_MPLAYER is not set -# CONFIG_PKG_USING_PERSIMMON_SRC is not set -# CONFIG_PKG_USING_JS_PERSIMMON is not set -# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set - -# -# Network Utilities -# -# CONFIG_PKG_USING_MDNS is not set -# CONFIG_PKG_USING_UPNP is not set -# end of Network Utilities - -# CONFIG_PKG_USING_WICED is not set -# CONFIG_PKG_USING_CLOUDSDK is not set -# CONFIG_PKG_USING_POWER_MANAGER is not set -# CONFIG_PKG_USING_RT_OTA is not set -# CONFIG_PKG_USING_RTINSIGHT is not set -# CONFIG_PKG_USING_SMARTCONFIG is not set -# CONFIG_PKG_USING_RTX is not set -# CONFIG_RT_USING_TESTCASE is not set -# CONFIG_PKG_USING_NGHTTP2 is not set -# CONFIG_PKG_USING_AVS is not set -# CONFIG_PKG_USING_ALI_LINKKIT is not set -# CONFIG_PKG_USING_STS is not set -# CONFIG_PKG_USING_DLMS is not set -# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set -# CONFIG_PKG_USING_ZBAR is not set -# CONFIG_PKG_USING_MCF is not set -# CONFIG_PKG_USING_URPC is not set -# CONFIG_PKG_USING_DCM is not set -# CONFIG_PKG_USING_EMQ is not set -# CONFIG_PKG_USING_CFGM is not set -# CONFIG_PKG_USING_RT_CMSIS_DAP is not set -# CONFIG_PKG_USING_SMODULE is not set -# CONFIG_PKG_USING_SNFD is not set -# CONFIG_PKG_USING_UDBD is not set -# CONFIG_PKG_USING_BENCHMARK is not set -# CONFIG_PKG_USING_UBJSON is not set -# CONFIG_PKG_USING_DATATYPE is not set -# CONFIG_PKG_USING_FASTFS is not set -# CONFIG_PKG_USING_RIL is not set -# CONFIG_PKG_USING_WATCH_DCM_SVC is not set -# CONFIG_PKG_USING_WATCH_APP_FWK is not set -# CONFIG_PKG_USING_GUI_TEST is not set -# CONFIG_PKG_USING_PMEM is not set -# CONFIG_PKG_USING_LWRDP is not set -# CONFIG_PKG_USING_MASAN is not set -# CONFIG_PKG_USING_BSDIFF_LIB is not set -# CONFIG_PKG_USING_PRC_DIFF is not set - -# -# RT-Thread Smart -# -# CONFIG_PKG_USING_UKERNEL is not set -# end of RT-Thread Smart - -# CONFIG_PKG_USING_TRACE_AGENT is not set -# CONFIG_PKG_USING_DLOG is not set -# CONFIG_PKG_USING_EXT4 is not set -# end of Privated Packages of RealThread - # # General Drivers Configuration # diff --git a/bsp/cvitek/cv18xx_risc-v/SConstruct b/bsp/cvitek/cv18xx_risc-v/SConstruct index 6ffc4cd71a..967a4e2910 100755 --- a/bsp/cvitek/cv18xx_risc-v/SConstruct +++ b/bsp/cvitek/cv18xx_risc-v/SConstruct @@ -24,13 +24,6 @@ Export('rtconfig') rtconfig.CPU='virt64' rtconfig.ARCH='risc-v' -stack_size = 4096 - -stack_lds = open('link_stacksize.lds', 'w') -if GetDepend('__STACKSIZE__'): stack_size = GetDepend('__STACKSIZE__') -stack_lds.write('__STACKSIZE__ = %d;\n' % stack_size) -stack_lds.close() - SDK_ROOT = os.path.abspath('./') if os.path.exists(SDK_ROOT + '/drivers'): @@ -44,5 +37,13 @@ objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False) # include libraries objs.extend(SConscript(drivers_path_prefix + '/SConscript', variant_dir='build/drivers', duplicate=0)) +stack_size = 4096 + +stack_lds = open('link_stacksize.lds', 'w') +if GetDepend('__STACKSIZE__'): + stack_size = GetDepend('__STACKSIZE__') +stack_lds.write('__STACKSIZE__ = %d;\n' % stack_size) +stack_lds.close() + # make a building DoBuilding(TARGET, objs) diff --git a/bsp/cvitek/cv18xx_risc-v/link_stacksize.lds b/bsp/cvitek/cv18xx_risc-v/link_stacksize.lds index 28438c7da1..38d573dcad 100755 --- a/bsp/cvitek/cv18xx_risc-v/link_stacksize.lds +++ b/bsp/cvitek/cv18xx_risc-v/link_stacksize.lds @@ -1 +1 @@ -__STACKSIZE__ = 4096; +__STACKSIZE__ = 8192; diff --git a/bsp/cvitek/cv18xx_risc-v/rtconfig.h b/bsp/cvitek/cv18xx_risc-v/rtconfig.h index 8932c30602..8f5a1391b4 100755 --- a/bsp/cvitek/cv18xx_risc-v/rtconfig.h +++ b/bsp/cvitek/cv18xx_risc-v/rtconfig.h @@ -439,18 +439,6 @@ /* end of Arduino libraries */ /* end of RT-Thread online packages */ -/* Privated Packages of RealThread */ - - -/* Network Utilities */ - -/* end of Network Utilities */ - -/* RT-Thread Smart */ - -/* end of RT-Thread Smart */ -/* end of Privated Packages of RealThread */ - /* General Drivers Configuration */ #define BSP_USING_UART From d1c7712bfb68ab6de9b6e88d8ad511320682507c Mon Sep 17 00:00:00 2001 From: sheltonyu <59359365+sheltonyu@users.noreply.github.com> Date: Wed, 24 Jul 2024 23:22:50 +0800 Subject: [PATCH 47/48] [bsp/at32] 1.add support hwi2c driver, 2.update all firmware libraries. (#9241) * 1.add support hwi2c driver, 2.update all firmware libraries * update some files and fixed errors * add support a423 at hwi2c driver * add .ignore_format.yml --- bsp/at32/at32a403a-start/README.md | 1 + bsp/at32/at32a403a-start/board/Kconfig | 51 + bsp/at32/at32a403a-start/board/src/at32_msp.c | 54 + bsp/at32/at32a423-start/README.md | 1 + bsp/at32/at32a423-start/board/Kconfig | 51 + bsp/at32/at32a423-start/board/inc/at32_msp.h | 1 + bsp/at32/at32a423-start/board/src/at32_msp.c | 62 + bsp/at32/at32f402-start/README.md | 1 + bsp/at32/at32f402-start/board/Kconfig | 51 + bsp/at32/at32f402-start/board/src/at32_msp.c | 63 + bsp/at32/at32f403a-start/README.md | 1 + bsp/at32/at32f403a-start/board/Kconfig | 51 + bsp/at32/at32f403a-start/board/src/at32_msp.c | 54 + bsp/at32/at32f405-start/README.md | 1 + bsp/at32/at32f405-start/board/Kconfig | 51 + bsp/at32/at32f405-start/board/src/at32_msp.c | 63 + bsp/at32/at32f407-start/README.md | 1 + bsp/at32/at32f407-start/board/Kconfig | 51 + bsp/at32/at32f407-start/board/src/at32_msp.c | 54 + bsp/at32/at32f413-start/README.md | 1 + bsp/at32/at32f413-start/board/Kconfig | 36 + bsp/at32/at32f413-start/board/src/at32_msp.c | 38 + bsp/at32/at32f415-start/README.md | 1 + bsp/at32/at32f415-start/board/Kconfig | 36 + bsp/at32/at32f415-start/board/src/at32_msp.c | 38 + bsp/at32/at32f421-start/README.md | 1 + bsp/at32/at32f421-start/board/Kconfig | 36 + bsp/at32/at32f421-start/board/inc/at32_msp.h | 1 + bsp/at32/at32f421-start/board/src/at32_msp.c | 44 + bsp/at32/at32f423-start/README.md | 1 + bsp/at32/at32f423-start/board/Kconfig | 51 + bsp/at32/at32f423-start/board/inc/at32_msp.h | 1 + bsp/at32/at32f423-start/board/src/at32_msp.c | 63 + bsp/at32/at32f425-start/README.md | 1 + bsp/at32/at32f425-start/board/Kconfig | 36 + bsp/at32/at32f425-start/board/inc/at32_msp.h | 1 + bsp/at32/at32f425-start/board/src/at32_msp.c | 44 + bsp/at32/at32f435-start/README.md | 1 + bsp/at32/at32f435-start/board/Kconfig | 51 + bsp/at32/at32f435-start/board/src/at32_msp.c | 63 + bsp/at32/at32f437-start/README.md | 1 + bsp/at32/at32f437-start/board/Kconfig | 51 + bsp/at32/at32f437-start/board/src/at32_msp.c | 63 + bsp/at32/libraries/.ignore_format.yml | 15 + .../cm4/device_support/system_at32f402_405.c | 44 + .../cm4/device_support/system_at32f402_405.h | 1 + .../drivers/inc/at32f402_405_acc.h | 1 + .../drivers/inc/at32f402_405_adc.h | 7 +- .../drivers/inc/at32f402_405_can.h | 1 + .../drivers/inc/at32f402_405_crm.h | 4 +- .../drivers/inc/at32f402_405_debug.h | 24 +- .../drivers/inc/at32f402_405_dma.h | 3 + .../drivers/inc/at32f402_405_ertc.h | 1 + .../drivers/inc/at32f402_405_exint.h | 1 + .../drivers/inc/at32f402_405_i2c.h | 13 +- .../drivers/inc/at32f402_405_pwc.h | 3 +- .../drivers/inc/at32f402_405_qspi.h | 33 +- .../drivers/inc/at32f402_405_scfg.h | 4 +- .../drivers/inc/at32f402_405_spi.h | 1 + .../drivers/inc/at32f402_405_tmr.h | 3 +- .../drivers/inc/at32f402_405_usart.h | 12 +- .../drivers/inc/at32f402_405_wwdt.h | 1 + .../drivers/src/at32f402_405_acc.c | 16 + .../drivers/src/at32f402_405_adc.c | 49 +- .../drivers/src/at32f402_405_can.c | 96 + .../drivers/src/at32f402_405_crm.c | 63 +- .../drivers/src/at32f402_405_dma.c | 182 ++ .../drivers/src/at32f402_405_ertc.c | 49 + .../drivers/src/at32f402_405_exint.c | 30 + .../drivers/src/at32f402_405_flash.c | 8 +- .../drivers/src/at32f402_405_i2c.c | 83 +- .../drivers/src/at32f402_405_pwc.c | 11 +- .../drivers/src/at32f402_405_qspi.c | 52 +- .../drivers/src/at32f402_405_scfg.c | 15 +- .../drivers/src/at32f402_405_spi.c | 70 + .../drivers/src/at32f402_405_tmr.c | 49 +- .../drivers/src/at32f402_405_usart.c | 92 +- .../drivers/src/at32f402_405_usb.c | 1 - .../drivers/src/at32f402_405_wwdt.c | 10 + .../cm4/device_support/system_at32f403a_407.c | 8 +- .../cm4/device_support/system_at32f403a_407.h | 7 +- .../drivers/inc/at32f403a_407_acc.h | 3 +- .../drivers/inc/at32f403a_407_adc.h | 3 +- .../drivers/inc/at32f403a_407_bpr.h | 3 +- .../drivers/inc/at32f403a_407_can.h | 5 +- .../drivers/inc/at32f403a_407_crc.h | 34 +- .../drivers/inc/at32f403a_407_crm.h | 3 +- .../drivers/inc/at32f403a_407_dac.h | 2 - .../drivers/inc/at32f403a_407_debug.h | 2 - .../drivers/inc/at32f403a_407_def.h | 4 +- .../drivers/inc/at32f403a_407_dma.h | 3 +- .../drivers/inc/at32f403a_407_emac.h | 39 +- .../drivers/inc/at32f403a_407_exint.h | 3 +- .../drivers/inc/at32f403a_407_flash.h | 8 +- .../drivers/inc/at32f403a_407_gpio.h | 8 +- .../drivers/inc/at32f403a_407_i2c.h | 3 +- .../drivers/inc/at32f403a_407_misc.h | 6 +- .../drivers/inc/at32f403a_407_pwc.h | 4 +- .../drivers/inc/at32f403a_407_rtc.h | 3 +- .../drivers/inc/at32f403a_407_sdio.h | 8 +- .../drivers/inc/at32f403a_407_spi.h | 3 +- .../drivers/inc/at32f403a_407_tmr.h | 7 +- .../drivers/inc/at32f403a_407_usart.h | 6 +- .../drivers/inc/at32f403a_407_usb.h | 4 +- .../drivers/inc/at32f403a_407_wdt.h | 2 - .../drivers/inc/at32f403a_407_wwdt.h | 3 +- .../drivers/inc/at32f403a_407_xmc.h | 5 +- .../drivers/src/at32f403a_407_acc.c | 18 +- .../drivers/src/at32f403a_407_adc.c | 269 +-- .../drivers/src/at32f403a_407_bpr.c | 22 +- .../drivers/src/at32f403a_407_can.c | 98 +- .../drivers/src/at32f403a_407_crc.c | 50 +- .../drivers/src/at32f403a_407_crm.c | 71 +- .../drivers/src/at32f403a_407_dac.c | 2 - .../drivers/src/at32f403a_407_debug.c | 2 - .../drivers/src/at32f403a_407_dma.c | 48 +- .../drivers/src/at32f403a_407_emac.c | 215 ++- .../drivers/src/at32f403a_407_exint.c | 41 +- .../drivers/src/at32f403a_407_flash.c | 577 +++--- .../drivers/src/at32f403a_407_gpio.c | 4 +- .../drivers/src/at32f403a_407_i2c.c | 95 +- .../drivers/src/at32f403a_407_misc.c | 2 - .../drivers/src/at32f403a_407_pwc.c | 7 +- .../drivers/src/at32f403a_407_rtc.c | 31 +- .../drivers/src/at32f403a_407_sdio.c | 63 +- .../drivers/src/at32f403a_407_spi.c | 93 +- .../drivers/src/at32f403a_407_tmr.c | 114 +- .../drivers/src/at32f403a_407_usart.c | 103 +- .../drivers/src/at32f403a_407_usb.c | 40 +- .../drivers/src/at32f403a_407_wdt.c | 2 - .../drivers/src/at32f403a_407_wwdt.c | 12 +- .../drivers/src/at32f403a_407_xmc.c | 47 +- .../cm4/device_support/system_at32f413.c | 2 - .../cm4/device_support/system_at32f413.h | 7 +- .../drivers/inc/at32f413_acc.h | 3 +- .../drivers/inc/at32f413_adc.h | 3 +- .../drivers/inc/at32f413_bpr.h | 7 +- .../drivers/inc/at32f413_can.h | 8 +- .../drivers/inc/at32f413_crc.h | 34 +- .../drivers/inc/at32f413_crm.h | 7 +- .../drivers/inc/at32f413_debug.h | 2 - .../drivers/inc/at32f413_def.h | 4 +- .../drivers/inc/at32f413_dma.h | 3 +- .../drivers/inc/at32f413_exint.h | 3 +- .../drivers/inc/at32f413_flash.h | 8 +- .../drivers/inc/at32f413_gpio.h | 4 +- .../drivers/inc/at32f413_i2c.h | 3 +- .../drivers/inc/at32f413_misc.h | 6 +- .../drivers/inc/at32f413_pwc.h | 18 +- .../drivers/inc/at32f413_rtc.h | 3 +- .../drivers/inc/at32f413_sdio.h | 8 +- .../drivers/inc/at32f413_spi.h | 3 +- .../drivers/inc/at32f413_tmr.h | 12 +- .../drivers/inc/at32f413_usart.h | 7 +- .../drivers/inc/at32f413_usb.h | 4 +- .../drivers/inc/at32f413_wdt.h | 2 - .../drivers/inc/at32f413_wwdt.h | 3 +- .../drivers/src/at32f413_acc.c | 18 +- .../drivers/src/at32f413_adc.c | 269 +-- .../drivers/src/at32f413_bpr.c | 24 +- .../drivers/src/at32f413_can.c | 101 +- .../drivers/src/at32f413_crc.c | 50 +- .../drivers/src/at32f413_crm.c | 64 +- .../drivers/src/at32f413_debug.c | 2 - .../drivers/src/at32f413_dma.c | 48 +- .../drivers/src/at32f413_exint.c | 31 +- .../drivers/src/at32f413_flash.c | 469 ++--- .../drivers/src/at32f413_gpio.c | 4 +- .../drivers/src/at32f413_i2c.c | 97 +- .../drivers/src/at32f413_misc.c | 2 - .../drivers/src/at32f413_pwc.c | 20 +- .../drivers/src/at32f413_rtc.c | 31 +- .../drivers/src/at32f413_sdio.c | 63 +- .../drivers/src/at32f413_spi.c | 77 +- .../drivers/src/at32f413_tmr.c | 121 +- .../drivers/src/at32f413_usart.c | 97 +- .../drivers/src/at32f413_usb.c | 40 +- .../drivers/src/at32f413_wdt.c | 2 - .../drivers/src/at32f413_wwdt.c | 12 +- .../cm4/device_support/system_at32f415.c | 2 - .../cm4/device_support/system_at32f415.h | 7 +- .../drivers/inc/at32f415_adc.h | 3 +- .../drivers/inc/at32f415_can.h | 5 +- .../drivers/inc/at32f415_cmp.h | 20 +- .../drivers/inc/at32f415_crc.h | 34 +- .../drivers/inc/at32f415_crm.h | 11 +- .../drivers/inc/at32f415_debug.h | 2 - .../drivers/inc/at32f415_def.h | 4 +- .../drivers/inc/at32f415_dma.h | 3 +- .../drivers/inc/at32f415_ertc.h | 13 +- .../drivers/inc/at32f415_exint.h | 3 +- .../drivers/inc/at32f415_flash.h | 4 +- .../drivers/inc/at32f415_gpio.h | 4 +- .../drivers/inc/at32f415_i2c.h | 3 +- .../drivers/inc/at32f415_misc.h | 6 +- .../drivers/inc/at32f415_pwc.h | 4 +- .../drivers/inc/at32f415_sdio.h | 5 +- .../drivers/inc/at32f415_spi.h | 3 +- .../drivers/inc/at32f415_tmr.h | 19 +- .../drivers/inc/at32f415_usart.h | 7 +- .../drivers/inc/at32f415_usb.h | 3 +- .../drivers/inc/at32f415_wdt.h | 2 - .../drivers/inc/at32f415_wwdt.h | 3 +- .../drivers/src/at32f415_adc.c | 267 +-- .../drivers/src/at32f415_can.c | 98 +- .../drivers/src/at32f415_cmp.c | 14 +- .../drivers/src/at32f415_crc.c | 50 +- .../drivers/src/at32f415_crm.c | 72 +- .../drivers/src/at32f415_debug.c | 2 - .../drivers/src/at32f415_dma.c | 48 +- .../drivers/src/at32f415_ertc.c | 72 +- .../drivers/src/at32f415_exint.c | 31 +- .../drivers/src/at32f415_flash.c | 439 ++--- .../drivers/src/at32f415_gpio.c | 4 +- .../drivers/src/at32f415_i2c.c | 97 +- .../drivers/src/at32f415_misc.c | 2 - .../drivers/src/at32f415_pwc.c | 7 +- .../drivers/src/at32f415_sdio.c | 63 +- .../drivers/src/at32f415_spi.c | 77 +- .../drivers/src/at32f415_tmr.c | 125 +- .../drivers/src/at32f415_usart.c | 97 +- .../drivers/src/at32f415_usb.c | 11 +- .../drivers/src/at32f415_wdt.c | 2 - .../drivers/src/at32f415_wwdt.c | 12 +- .../cm4/device_support/system_at32f421.h | 4 + .../drivers/inc/at32f421_adc.h | 9 +- .../drivers/inc/at32f421_cmp.h | 4 +- .../drivers/inc/at32f421_crc.h | 30 +- .../drivers/inc/at32f421_crm.h | 7 +- .../drivers/inc/at32f421_dma.h | 1 + .../drivers/inc/at32f421_ertc.h | 1 + .../drivers/inc/at32f421_exint.h | 1 + .../drivers/inc/at32f421_gpio.h | 60 +- .../drivers/inc/at32f421_i2c.h | 1 + .../drivers/inc/at32f421_pwc.h | 8 +- .../drivers/inc/at32f421_scfg.h | 4 +- .../drivers/inc/at32f421_spi.h | 1 + .../drivers/inc/at32f421_tmr.h | 3 +- .../drivers/inc/at32f421_usart.h | 1 + .../drivers/inc/at32f421_wwdt.h | 1 + .../drivers/src/at32f421_adc.c | 279 +-- .../drivers/src/at32f421_cmp.c | 2 +- .../drivers/src/at32f421_crc.c | 46 + .../drivers/src/at32f421_crm.c | 59 + .../drivers/src/at32f421_dma.c | 30 + .../drivers/src/at32f421_ertc.c | 47 +- .../drivers/src/at32f421_exint.c | 28 + .../drivers/src/at32f421_flash.c | 2 +- .../drivers/src/at32f421_i2c.c | 79 + .../drivers/src/at32f421_pwc.c | 18 +- .../drivers/src/at32f421_scfg.c | 2 - .../drivers/src/at32f421_spi.c | 63 + .../drivers/src/at32f421_tmr.c | 43 +- .../drivers/src/at32f421_usart.c | 76 + .../drivers/src/at32f421_wwdt.c | 10 + .../cm4/device_support/system_at32f423.c | 24 +- .../cm4/device_support/system_at32f423.h | 1 + .../drivers/inc/at32f423_acc.h | 1 + .../drivers/inc/at32f423_adc.h | 9 +- .../drivers/inc/at32f423_can.h | 1 + .../drivers/inc/at32f423_crc.h | 30 +- .../drivers/inc/at32f423_crm.h | 3 +- .../drivers/inc/at32f423_dac.h | 1 + .../drivers/inc/at32f423_debug.h | 24 +- .../drivers/inc/at32f423_dma.h | 3 + .../drivers/inc/at32f423_ertc.h | 1 + .../drivers/inc/at32f423_exint.h | 1 + .../drivers/inc/at32f423_i2c.h | 13 +- .../drivers/inc/at32f423_pwc.h | 11 +- .../drivers/inc/at32f423_scfg.h | 6 +- .../drivers/inc/at32f423_spi.h | 1 + .../drivers/inc/at32f423_tmr.h | 5 +- .../drivers/inc/at32f423_usart.h | 4 +- .../drivers/inc/at32f423_wwdt.h | 1 + .../drivers/inc/at32f423_xmc.h | 2 +- .../drivers/src/at32f423_acc.c | 16 + .../drivers/src/at32f423_adc.c | 48 + .../drivers/src/at32f423_can.c | 96 + .../drivers/src/at32f423_crc.c | 46 + .../drivers/src/at32f423_crm.c | 91 +- .../drivers/src/at32f423_dac.c | 28 + .../drivers/src/at32f423_dma.c | 178 ++ .../drivers/src/at32f423_ertc.c | 49 + .../drivers/src/at32f423_exint.c | 34 + .../drivers/src/at32f423_gpio.c | 28 +- .../drivers/src/at32f423_i2c.c | 83 +- .../drivers/src/at32f423_scfg.c | 10 +- .../drivers/src/at32f423_spi.c | 70 + .../drivers/src/at32f423_tmr.c | 57 +- .../drivers/src/at32f423_usart.c | 125 +- .../drivers/src/at32f423_wwdt.c | 10 + .../drivers/src/at32f423_xmc.c | 2 +- .../drivers/inc/at32f425_acc.h | 1 + .../drivers/inc/at32f425_adc.h | 1 + .../drivers/inc/at32f425_can.h | 1 + .../drivers/inc/at32f425_crc.h | 30 +- .../drivers/inc/at32f425_crm.h | 7 +- .../drivers/inc/at32f425_debug.h | 20 + .../drivers/inc/at32f425_dma.h | 1 + .../drivers/inc/at32f425_ertc.h | 5 +- .../drivers/inc/at32f425_exint.h | 1 + .../drivers/inc/at32f425_flash.h | 4 +- .../drivers/inc/at32f425_i2c.h | 13 +- .../drivers/inc/at32f425_pwc.h | 12 +- .../drivers/inc/at32f425_scfg.h | 6 +- .../drivers/inc/at32f425_spi.h | 1 + .../drivers/inc/at32f425_tmr.h | 7 +- .../drivers/inc/at32f425_usart.h | 1 + .../drivers/inc/at32f425_usb.h | 1 + .../drivers/inc/at32f425_wwdt.h | 1 + .../drivers/src/at32f425_acc.c | 16 + .../drivers/src/at32f425_adc.c | 267 +-- .../drivers/src/at32f425_can.c | 96 + .../drivers/src/at32f425_crc.c | 46 + .../drivers/src/at32f425_crm.c | 58 + .../drivers/src/at32f425_dma.c | 32 + .../drivers/src/at32f425_ertc.c | 53 +- .../drivers/src/at32f425_exint.c | 28 + .../drivers/src/at32f425_flash.c | 2 +- .../drivers/src/at32f425_i2c.c | 83 +- .../drivers/src/at32f425_pwc.c | 18 +- .../drivers/src/at32f425_scfg.c | 10 +- .../drivers/src/at32f425_spi.c | 71 + .../drivers/src/at32f425_tmr.c | 67 +- .../drivers/src/at32f425_usart.c | 76 + .../drivers/src/at32f425_usb.c | 3 +- .../drivers/src/at32f425_wwdt.c | 10 + .../cm4/device_support/system_at32f435_437.c | 10 +- .../cm4/device_support/system_at32f435_437.h | 8 +- .../drivers/inc/at32f435_437_acc.h | 3 +- .../drivers/inc/at32f435_437_adc.h | 3 +- .../drivers/inc/at32f435_437_can.h | 5 +- .../drivers/inc/at32f435_437_crc.h | 34 +- .../drivers/inc/at32f435_437_crm.h | 29 +- .../drivers/inc/at32f435_437_dac.h | 3 +- .../drivers/inc/at32f435_437_debug.h | 26 +- .../drivers/inc/at32f435_437_def.h | 4 +- .../drivers/inc/at32f435_437_dma.h | 5 +- .../drivers/inc/at32f435_437_dvp.h | 67 +- .../drivers/inc/at32f435_437_edma.h | 13 +- .../drivers/inc/at32f435_437_emac.h | 37 +- .../drivers/inc/at32f435_437_ertc.h | 13 +- .../drivers/inc/at32f435_437_exint.h | 3 +- .../drivers/inc/at32f435_437_flash.h | 2 - .../drivers/inc/at32f435_437_gpio.h | 4 +- .../drivers/inc/at32f435_437_i2c.h | 21 +- .../drivers/inc/at32f435_437_misc.h | 6 +- .../drivers/inc/at32f435_437_pwc.h | 18 +- .../drivers/inc/at32f435_437_qspi.h | 56 +- .../drivers/inc/at32f435_437_scfg.h | 12 +- .../drivers/inc/at32f435_437_sdio.h | 5 +- .../drivers/inc/at32f435_437_spi.h | 3 +- .../drivers/inc/at32f435_437_tmr.h | 22 +- .../drivers/inc/at32f435_437_usart.h | 6 +- .../drivers/inc/at32f435_437_usb.h | 3 +- .../drivers/inc/at32f435_437_wdt.h | 2 - .../drivers/inc/at32f435_437_wwdt.h | 3 +- .../drivers/inc/at32f435_437_xmc.h | 7 +- .../drivers/src/at32f435_437_acc.c | 19 +- .../drivers/src/at32f435_437_adc.c | 275 +-- .../drivers/src/at32f435_437_can.c | 98 +- .../drivers/src/at32f435_437_crc.c | 50 +- .../drivers/src/at32f435_437_crm.c | 94 +- .../drivers/src/at32f435_437_dac.c | 30 +- .../drivers/src/at32f435_437_debug.c | 2 - .../drivers/src/at32f435_437_dma.c | 192 +- .../drivers/src/at32f435_437_dvp.c | 142 +- .../drivers/src/at32f435_437_edma.c | 137 +- .../drivers/src/at32f435_437_emac.c | 216 ++- .../drivers/src/at32f435_437_ertc.c | 74 +- .../drivers/src/at32f435_437_exint.c | 31 +- .../drivers/src/at32f435_437_flash.c | 579 +++--- .../drivers/src/at32f435_437_gpio.c | 4 +- .../drivers/src/at32f435_437_i2c.c | 97 +- .../drivers/src/at32f435_437_misc.c | 2 - .../drivers/src/at32f435_437_pwc.c | 9 +- .../drivers/src/at32f435_437_qspi.c | 83 +- .../drivers/src/at32f435_437_scfg.c | 4 - .../drivers/src/at32f435_437_sdio.c | 63 +- .../drivers/src/at32f435_437_spi.c | 86 +- .../drivers/src/at32f435_437_tmr.c | 132 +- .../drivers/src/at32f435_437_usart.c | 96 +- .../drivers/src/at32f435_437_usb.c | 9 +- .../drivers/src/at32f435_437_wdt.c | 2 - .../drivers/src/at32f435_437_wwdt.c | 12 +- .../drivers/src/at32f435_437_xmc.c | 97 +- bsp/at32/libraries/rt_drivers/SConscript | 3 + .../rt_drivers/config/a403a/dma_config.h | 31 +- .../rt_drivers/config/a403a/i2c_config.h | 122 ++ .../rt_drivers/config/a423/dma_config.h | 44 +- .../rt_drivers/config/a423/i2c_config.h | 134 ++ .../rt_drivers/config/f402_405/dma_config.h | 44 +- .../rt_drivers/config/f402_405/i2c_config.h | 134 ++ .../rt_drivers/config/f403a_407/dma_config.h | 31 +- .../rt_drivers/config/f403a_407/i2c_config.h | 122 ++ .../rt_drivers/config/f413/dma_config.h | 21 +- .../rt_drivers/config/f413/i2c_config.h | 91 + .../rt_drivers/config/f415/dma_config.h | 20 + .../rt_drivers/config/f415/i2c_config.h | 91 + .../rt_drivers/config/f421/dma_config.h | 20 + .../rt_drivers/config/f421/i2c_config.h | 91 + .../rt_drivers/config/f423/dma_config.h | 44 +- .../rt_drivers/config/f423/i2c_config.h | 134 ++ .../rt_drivers/config/f425/dma_config.h | 28 + .../rt_drivers/config/f425/i2c_config.h | 99 + .../rt_drivers/config/f435_437/dma_config.h | 42 + .../rt_drivers/config/f435_437/i2c_config.h | 134 ++ bsp/at32/libraries/rt_drivers/drv_config.h | 11 + bsp/at32/libraries/rt_drivers/drv_hard_i2c.c | 1695 +++++++++++++++++ bsp/at32/libraries/rt_drivers/drv_hard_i2c.h | 95 + 410 files changed, 13985 insertions(+), 3598 deletions(-) create mode 100644 bsp/at32/libraries/.ignore_format.yml create mode 100644 bsp/at32/libraries/rt_drivers/config/a403a/i2c_config.h create mode 100644 bsp/at32/libraries/rt_drivers/config/a423/i2c_config.h create mode 100644 bsp/at32/libraries/rt_drivers/config/f402_405/i2c_config.h create mode 100644 bsp/at32/libraries/rt_drivers/config/f403a_407/i2c_config.h create mode 100644 bsp/at32/libraries/rt_drivers/config/f413/i2c_config.h create mode 100644 bsp/at32/libraries/rt_drivers/config/f415/i2c_config.h create mode 100644 bsp/at32/libraries/rt_drivers/config/f421/i2c_config.h create mode 100644 bsp/at32/libraries/rt_drivers/config/f423/i2c_config.h create mode 100644 bsp/at32/libraries/rt_drivers/config/f425/i2c_config.h create mode 100644 bsp/at32/libraries/rt_drivers/config/f435_437/i2c_config.h create mode 100644 bsp/at32/libraries/rt_drivers/drv_hard_i2c.c create mode 100644 bsp/at32/libraries/rt_drivers/drv_hard_i2c.h diff --git a/bsp/at32/at32a403a-start/README.md b/bsp/at32/at32a403a-start/README.md index dfe372c1f1..5345b000e1 100644 --- a/bsp/at32/at32a403a-start/README.md +++ b/bsp/at32/at32a403a-start/README.md @@ -41,6 +41,7 @@ AT32A403A-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以 | UART | 支持 | USART1/2/3 | | GPIO | 支持 | PA0...PF7 | | IIC | 支持 | GPIO模拟I2C | +| HWIIC | 支持 | I2C1/2/3 | | SPI | 支持 | SPI1/2 | | ADC | 支持 | ADC1/2 | | DAC | 支持 | DAC1 | diff --git a/bsp/at32/at32a403a-start/board/Kconfig b/bsp/at32/at32a403a-start/board/Kconfig index 6663e58a41..018b0815bc 100644 --- a/bsp/at32/at32a403a-start/board/Kconfig +++ b/bsp/at32/at32a403a-start/board/Kconfig @@ -265,6 +265,57 @@ menu "On-chip Peripheral Drivers" endif endif + menuconfig BSP_USING_HARD_I2C + bool "Enable I2C BUS (hardware driver)" + default n + select RT_USING_I2C + if BSP_USING_HARD_I2C + config BSP_USING_HARD_I2C1 + bool "Enable I2C1 BUS" + default n + + config BSP_I2C1_TX_USING_DMA + bool "Enable I2C1 TX DMA" + depends on BSP_USING_HARD_I2C1 + default n + + config BSP_I2C1_RX_USING_DMA + bool "Enable I2C1 RX DMA" + depends on BSP_USING_HARD_I2C1 + select BSP_I2C1_TX_USING_DMA + default n + + config BSP_USING_HARD_I2C2 + bool "Enable I2C2 BUS" + default n + + config BSP_I2C2_TX_USING_DMA + bool "Enable I2C2 TX DMA" + depends on BSP_USING_HARD_I2C2 + default n + + config BSP_I2C2_RX_USING_DMA + bool "Enable I2C2 RX DMA" + depends on BSP_USING_HARD_I2C2 + select BSP_I2C2_TX_USING_DMA + default n + + config BSP_USING_HARD_I2C3 + bool "Enable I2C3 BUS" + default n + + config BSP_I2C3_TX_USING_DMA + bool "Enable I2C3 TX DMA" + depends on BSP_USING_HARD_I2C3 + default n + + config BSP_I2C3_RX_USING_DMA + bool "Enable I2C3 RX DMA" + depends on BSP_USING_HARD_I2C3 + select BSP_I2C3_TX_USING_DMA + default n + endif + menuconfig BSP_USING_ADC bool "Enable ADC" default n diff --git a/bsp/at32/at32a403a-start/board/src/at32_msp.c b/bsp/at32/at32a403a-start/board/src/at32_msp.c index eedc7cc834..7011c578d2 100644 --- a/bsp/at32/at32a403a-start/board/src/at32_msp.c +++ b/bsp/at32/at32a403a-start/board/src/at32_msp.c @@ -129,6 +129,60 @@ void at32_msp_spi_init(void *instance) } #endif /* BSP_USING_SPI */ +#ifdef BSP_USING_HARD_I2C +void at32_msp_i2c_init(void *instance) +{ + gpio_init_type gpio_init_struct; + i2c_type *i2c_x = (i2c_type *)instance; + + gpio_default_para_init(&gpio_init_struct); + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; +#ifdef BSP_USING_HARD_I2C1 + if(I2C1 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7; + gpio_init(GPIOB, &gpio_init_struct); + } +#endif +#ifdef BSP_USING_HARD_I2C2 + if(I2C2 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C2_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_10 | GPIO_PINS_11; + gpio_init(GPIOB, &gpio_init_struct); + } +#endif +#ifdef BSP_USING_HARD_I2C3 + if(I2C3 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C3_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_8; + gpio_init(GPIOA, &gpio_init_struct); + gpio_init_struct.gpio_pins = GPIO_PINS_9; + gpio_init(GPIOC, &gpio_init_struct); + } +#endif + /* add others */ +} +#endif /* BSP_USING_HARD_I2C */ + #ifdef BSP_USING_SDIO void at32_msp_sdio_init(void *instance) { diff --git a/bsp/at32/at32a423-start/README.md b/bsp/at32/at32a423-start/README.md index dff31e6b10..069560c7dc 100644 --- a/bsp/at32/at32a423-start/README.md +++ b/bsp/at32/at32a423-start/README.md @@ -41,6 +41,7 @@ AT32A423-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以 | UART | 支持 | USART1/2/3 | | GPIO | 支持 | PA0...PF10 | | IIC | 支持 | GPIO模拟I2C | +| HWIIC | 支持 | I2C1/2/3 | | SPI | 支持 | SPI1/2 | | ADC | 支持 | ADC1 | | DAC | 支持 | DAC1 | diff --git a/bsp/at32/at32a423-start/board/Kconfig b/bsp/at32/at32a423-start/board/Kconfig index 4fec6bd8a7..ea24f1513f 100644 --- a/bsp/at32/at32a423-start/board/Kconfig +++ b/bsp/at32/at32a423-start/board/Kconfig @@ -277,6 +277,57 @@ menu "On-chip Peripheral Drivers" endif endif + menuconfig BSP_USING_HARD_I2C + bool "Enable I2C BUS (hardware driver)" + default n + select RT_USING_I2C + if BSP_USING_HARD_I2C + config BSP_USING_HARD_I2C1 + bool "Enable I2C1 BUS" + default n + + config BSP_I2C1_TX_USING_DMA + bool "Enable I2C1 TX DMA" + depends on BSP_USING_HARD_I2C1 + default n + + config BSP_I2C1_RX_USING_DMA + bool "Enable I2C1 RX DMA" + depends on BSP_USING_HARD_I2C1 + select BSP_I2C1_TX_USING_DMA + default n + + config BSP_USING_HARD_I2C2 + bool "Enable I2C2 BUS" + default n + + config BSP_I2C2_TX_USING_DMA + bool "Enable I2C2 TX DMA" + depends on BSP_USING_HARD_I2C2 + default n + + config BSP_I2C2_RX_USING_DMA + bool "Enable I2C2 RX DMA" + depends on BSP_USING_HARD_I2C2 + select BSP_I2C2_TX_USING_DMA + default n + + config BSP_USING_HARD_I2C3 + bool "Enable I2C3 BUS" + default n + + config BSP_I2C3_TX_USING_DMA + bool "Enable I2C3 TX DMA" + depends on BSP_USING_HARD_I2C3 + default n + + config BSP_I2C3_RX_USING_DMA + bool "Enable I2C3 RX DMA" + depends on BSP_USING_HARD_I2C3 + select BSP_I2C3_TX_USING_DMA + default n + endif + menuconfig BSP_USING_ADC bool "Enable ADC" default n diff --git a/bsp/at32/at32a423-start/board/inc/at32_msp.h b/bsp/at32/at32a423-start/board/inc/at32_msp.h index d53871331d..af1060a15d 100644 --- a/bsp/at32/at32a423-start/board/inc/at32_msp.h +++ b/bsp/at32/at32a423-start/board/inc/at32_msp.h @@ -19,5 +19,6 @@ void at32_msp_hwtmr_init(void *instance); void at32_msp_can_init(void *instance); void at32_msp_usb_init(void *instance); void at32_msp_dac_init(void *instance); +void at32_msp_i2c_init(void *instance); #endif /* __AT32_MSP_H__ */ diff --git a/bsp/at32/at32a423-start/board/src/at32_msp.c b/bsp/at32/at32a423-start/board/src/at32_msp.c index e5898985dc..3a81f5585c 100644 --- a/bsp/at32/at32a423-start/board/src/at32_msp.c +++ b/bsp/at32/at32a423-start/board/src/at32_msp.c @@ -134,6 +134,68 @@ void at32_msp_spi_init(void *instance) /* add others */ } #endif /* BSP_USING_SPI */ +#ifdef BSP_USING_HARD_I2C +void at32_msp_i2c_init(void *instance) +{ + gpio_init_type gpio_init_struct; + i2c_type *i2c_x = (i2c_type *)instance; + + gpio_default_para_init(&gpio_init_struct); + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; +#ifdef BSP_USING_HARD_I2C1 + if(I2C1 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7; + gpio_init(GPIOB, &gpio_init_struct); + + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE6, GPIO_MUX_4); + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE7, GPIO_MUX_4); + } +#endif +#ifdef BSP_USING_HARD_I2C2 + if(I2C2 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C2_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_10 | GPIO_PINS_11; + gpio_init(GPIOB, &gpio_init_struct); + + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE10, GPIO_MUX_4); + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE11, GPIO_MUX_4); + } +#endif +#ifdef BSP_USING_HARD_I2C3 + if(I2C3 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C3_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_8; + gpio_init(GPIOA, &gpio_init_struct); + gpio_init_struct.gpio_pins = GPIO_PINS_9; + gpio_init(GPIOC, &gpio_init_struct); + + gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE8, GPIO_MUX_4); + gpio_pin_mux_config(GPIOC, GPIO_PINS_SOURCE9, GPIO_MUX_4); + } +#endif + /* add others */ +} +#endif /* BSP_USING_HARD_I2C */ #ifdef BSP_USING_PWM void at32_msp_tmr_init(void *instance) diff --git a/bsp/at32/at32f402-start/README.md b/bsp/at32/at32f402-start/README.md index 0d45c5a80a..9f052ed24a 100644 --- a/bsp/at32/at32f402-start/README.md +++ b/bsp/at32/at32f402-start/README.md @@ -41,6 +41,7 @@ AT32F402-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以 | UART | 支持 | USART1/2/3 | | GPIO | 支持 | PA0...PF7 | | IIC | 支持 | GPIO模拟I2C | +| HWIIC | 支持 | I2C1/2/3 | | SPI | 支持 | SPI1/2 | | ADC | 支持 | ADC1 | | PWM | 支持 | TMR1/2 | diff --git a/bsp/at32/at32f402-start/board/Kconfig b/bsp/at32/at32f402-start/board/Kconfig index 30446e35a0..b83b21f261 100644 --- a/bsp/at32/at32f402-start/board/Kconfig +++ b/bsp/at32/at32f402-start/board/Kconfig @@ -288,6 +288,57 @@ menu "On-chip Peripheral Drivers" endif endif + menuconfig BSP_USING_HARD_I2C + bool "Enable I2C BUS (hardware driver)" + default n + select RT_USING_I2C + if BSP_USING_HARD_I2C + config BSP_USING_HARD_I2C1 + bool "Enable I2C1 BUS" + default n + + config BSP_I2C1_TX_USING_DMA + bool "Enable I2C1 TX DMA" + depends on BSP_USING_HARD_I2C1 + default n + + config BSP_I2C1_RX_USING_DMA + bool "Enable I2C1 RX DMA" + depends on BSP_USING_HARD_I2C1 + select BSP_I2C1_TX_USING_DMA + default n + + config BSP_USING_HARD_I2C2 + bool "Enable I2C2 BUS" + default n + + config BSP_I2C2_TX_USING_DMA + bool "Enable I2C2 TX DMA" + depends on BSP_USING_HARD_I2C2 + default n + + config BSP_I2C2_RX_USING_DMA + bool "Enable I2C2 RX DMA" + depends on BSP_USING_HARD_I2C2 + select BSP_I2C2_TX_USING_DMA + default n + + config BSP_USING_HARD_I2C3 + bool "Enable I2C3 BUS" + default n + + config BSP_I2C3_TX_USING_DMA + bool "Enable I2C3 TX DMA" + depends on BSP_USING_HARD_I2C3 + default n + + config BSP_I2C3_RX_USING_DMA + bool "Enable I2C3 RX DMA" + depends on BSP_USING_HARD_I2C3 + select BSP_I2C3_TX_USING_DMA + default n + endif + menuconfig BSP_USING_ADC bool "Enable ADC" default n diff --git a/bsp/at32/at32f402-start/board/src/at32_msp.c b/bsp/at32/at32f402-start/board/src/at32_msp.c index 711a9e8bab..9afbb74cfc 100644 --- a/bsp/at32/at32f402-start/board/src/at32_msp.c +++ b/bsp/at32/at32f402-start/board/src/at32_msp.c @@ -127,6 +127,69 @@ void at32_msp_spi_init(void *instance) } #endif /* BSP_USING_SPI */ +#ifdef BSP_USING_HARD_I2C +void at32_msp_i2c_init(void *instance) +{ + gpio_init_type gpio_init_struct; + i2c_type *i2c_x = (i2c_type *)instance; + + gpio_default_para_init(&gpio_init_struct); + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; +#ifdef BSP_USING_HARD_I2C1 + if(I2C1 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7; + gpio_init(GPIOB, &gpio_init_struct); + + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE6, GPIO_MUX_4); + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE7, GPIO_MUX_4); + } +#endif +#ifdef BSP_USING_HARD_I2C2 + if(I2C2 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C2_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_3 | GPIO_PINS_10; + gpio_init(GPIOB, &gpio_init_struct); + + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE3, GPIO_MUX_4); + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE10, GPIO_MUX_4); + } +#endif +#ifdef BSP_USING_HARD_I2C3 + if(I2C3 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C3_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_8; + gpio_init(GPIOA, &gpio_init_struct); + gpio_init_struct.gpio_pins = GPIO_PINS_9; + gpio_init(GPIOC, &gpio_init_struct); + + gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE8, GPIO_MUX_4); + gpio_pin_mux_config(GPIOC, GPIO_PINS_SOURCE9, GPIO_MUX_4); + } +#endif + /* add others */ +} +#endif /* BSP_USING_HARD_I2C */ + #ifdef BSP_USING_PWM void at32_msp_tmr_init(void *instance) { diff --git a/bsp/at32/at32f403a-start/README.md b/bsp/at32/at32f403a-start/README.md index f46ec9ab29..3b469c3394 100644 --- a/bsp/at32/at32f403a-start/README.md +++ b/bsp/at32/at32f403a-start/README.md @@ -41,6 +41,7 @@ AT32F403A-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以 | UART | 支持 | USART1/2/3 | | GPIO | 支持 | PA0...PF7 | | IIC | 支持 | GPIO模拟I2C | +| HWIIC | 支持 | I2C1/2/3 | | SPI | 支持 | SPI1/2 | | ADC | 支持 | ADC1/2 | | DAC | 支持 | DAC1 | diff --git a/bsp/at32/at32f403a-start/board/Kconfig b/bsp/at32/at32f403a-start/board/Kconfig index f3c913d3dc..b0dade514b 100644 --- a/bsp/at32/at32f403a-start/board/Kconfig +++ b/bsp/at32/at32f403a-start/board/Kconfig @@ -265,6 +265,57 @@ menu "On-chip Peripheral Drivers" endif endif + menuconfig BSP_USING_HARD_I2C + bool "Enable I2C BUS (hardware driver)" + default n + select RT_USING_I2C + if BSP_USING_HARD_I2C + config BSP_USING_HARD_I2C1 + bool "Enable I2C1 BUS" + default n + + config BSP_I2C1_TX_USING_DMA + bool "Enable I2C1 TX DMA" + depends on BSP_USING_HARD_I2C1 + default n + + config BSP_I2C1_RX_USING_DMA + bool "Enable I2C1 RX DMA" + depends on BSP_USING_HARD_I2C1 + select BSP_I2C1_TX_USING_DMA + default n + + config BSP_USING_HARD_I2C2 + bool "Enable I2C2 BUS" + default n + + config BSP_I2C2_TX_USING_DMA + bool "Enable I2C2 TX DMA" + depends on BSP_USING_HARD_I2C2 + default n + + config BSP_I2C2_RX_USING_DMA + bool "Enable I2C2 RX DMA" + depends on BSP_USING_HARD_I2C2 + select BSP_I2C2_TX_USING_DMA + default n + + config BSP_USING_HARD_I2C3 + bool "Enable I2C3 BUS" + default n + + config BSP_I2C3_TX_USING_DMA + bool "Enable I2C3 TX DMA" + depends on BSP_USING_HARD_I2C3 + default n + + config BSP_I2C3_RX_USING_DMA + bool "Enable I2C3 RX DMA" + depends on BSP_USING_HARD_I2C3 + select BSP_I2C3_TX_USING_DMA + default n + endif + menuconfig BSP_USING_ADC bool "Enable ADC" default n diff --git a/bsp/at32/at32f403a-start/board/src/at32_msp.c b/bsp/at32/at32f403a-start/board/src/at32_msp.c index 979afdfe66..848ff32cdd 100644 --- a/bsp/at32/at32f403a-start/board/src/at32_msp.c +++ b/bsp/at32/at32f403a-start/board/src/at32_msp.c @@ -129,6 +129,60 @@ void at32_msp_spi_init(void *instance) } #endif /* BSP_USING_SPI */ +#ifdef BSP_USING_HARD_I2C +void at32_msp_i2c_init(void *instance) +{ + gpio_init_type gpio_init_struct; + i2c_type *i2c_x = (i2c_type *)instance; + + gpio_default_para_init(&gpio_init_struct); + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; +#ifdef BSP_USING_HARD_I2C1 + if(I2C1 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7; + gpio_init(GPIOB, &gpio_init_struct); + } +#endif +#ifdef BSP_USING_HARD_I2C2 + if(I2C2 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C2_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_10 | GPIO_PINS_11; + gpio_init(GPIOB, &gpio_init_struct); + } +#endif +#ifdef BSP_USING_HARD_I2C3 + if(I2C3 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C3_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_8; + gpio_init(GPIOA, &gpio_init_struct); + gpio_init_struct.gpio_pins = GPIO_PINS_9; + gpio_init(GPIOC, &gpio_init_struct); + } +#endif + /* add others */ +} +#endif /* BSP_USING_HARD_I2C */ + #ifdef BSP_USING_SDIO void at32_msp_sdio_init(void *instance) { diff --git a/bsp/at32/at32f405-start/README.md b/bsp/at32/at32f405-start/README.md index 888952cca5..957f63b6ab 100644 --- a/bsp/at32/at32f405-start/README.md +++ b/bsp/at32/at32f405-start/README.md @@ -41,6 +41,7 @@ AT32F405-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以 | UART | 支持 | USART1/2/3 | | GPIO | 支持 | PA0...PF7 | | IIC | 支持 | GPIO模拟I2C | +| HWIIC | 支持 | I2C1/2/3 | | SPI | 支持 | SPI1/2 | | ADC | 支持 | ADC1 | | PWM | 支持 | TMR1/2 | diff --git a/bsp/at32/at32f405-start/board/Kconfig b/bsp/at32/at32f405-start/board/Kconfig index f6a196f4e0..5de191fc0f 100644 --- a/bsp/at32/at32f405-start/board/Kconfig +++ b/bsp/at32/at32f405-start/board/Kconfig @@ -307,6 +307,57 @@ menu "On-chip Peripheral Drivers" endif endif + menuconfig BSP_USING_HARD_I2C + bool "Enable I2C BUS (hardware driver)" + default n + select RT_USING_I2C + if BSP_USING_HARD_I2C + config BSP_USING_HARD_I2C1 + bool "Enable I2C1 BUS" + default n + + config BSP_I2C1_TX_USING_DMA + bool "Enable I2C1 TX DMA" + depends on BSP_USING_HARD_I2C1 + default n + + config BSP_I2C1_RX_USING_DMA + bool "Enable I2C1 RX DMA" + depends on BSP_USING_HARD_I2C1 + select BSP_I2C1_TX_USING_DMA + default n + + config BSP_USING_HARD_I2C2 + bool "Enable I2C2 BUS" + default n + + config BSP_I2C2_TX_USING_DMA + bool "Enable I2C2 TX DMA" + depends on BSP_USING_HARD_I2C2 + default n + + config BSP_I2C2_RX_USING_DMA + bool "Enable I2C2 RX DMA" + depends on BSP_USING_HARD_I2C2 + select BSP_I2C2_TX_USING_DMA + default n + + config BSP_USING_HARD_I2C3 + bool "Enable I2C3 BUS" + default n + + config BSP_I2C3_TX_USING_DMA + bool "Enable I2C3 TX DMA" + depends on BSP_USING_HARD_I2C3 + default n + + config BSP_I2C3_RX_USING_DMA + bool "Enable I2C3 RX DMA" + depends on BSP_USING_HARD_I2C3 + select BSP_I2C3_TX_USING_DMA + default n + endif + menuconfig BSP_USING_ADC bool "Enable ADC" default n diff --git a/bsp/at32/at32f405-start/board/src/at32_msp.c b/bsp/at32/at32f405-start/board/src/at32_msp.c index 4ece05a5a5..da12e07a50 100644 --- a/bsp/at32/at32f405-start/board/src/at32_msp.c +++ b/bsp/at32/at32f405-start/board/src/at32_msp.c @@ -127,6 +127,69 @@ void at32_msp_spi_init(void *instance) } #endif /* BSP_USING_SPI */ +#ifdef BSP_USING_HARD_I2C +void at32_msp_i2c_init(void *instance) +{ + gpio_init_type gpio_init_struct; + i2c_type *i2c_x = (i2c_type *)instance; + + gpio_default_para_init(&gpio_init_struct); + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; +#ifdef BSP_USING_HARD_I2C1 + if(I2C1 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7; + gpio_init(GPIOB, &gpio_init_struct); + + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE6, GPIO_MUX_4); + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE7, GPIO_MUX_4); + } +#endif +#ifdef BSP_USING_HARD_I2C2 + if(I2C2 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C2_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_3 | GPIO_PINS_10; + gpio_init(GPIOB, &gpio_init_struct); + + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE3, GPIO_MUX_4); + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE10, GPIO_MUX_4); + } +#endif +#ifdef BSP_USING_HARD_I2C3 + if(I2C3 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C3_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_8; + gpio_init(GPIOA, &gpio_init_struct); + gpio_init_struct.gpio_pins = GPIO_PINS_9; + gpio_init(GPIOC, &gpio_init_struct); + + gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE8, GPIO_MUX_4); + gpio_pin_mux_config(GPIOC, GPIO_PINS_SOURCE9, GPIO_MUX_4); + } +#endif + /* add others */ +} +#endif /* BSP_USING_HARD_I2C */ + #ifdef BSP_USING_PWM void at32_msp_tmr_init(void *instance) { diff --git a/bsp/at32/at32f407-start/README.md b/bsp/at32/at32f407-start/README.md index 56d9206892..f255f93f44 100644 --- a/bsp/at32/at32f407-start/README.md +++ b/bsp/at32/at32f407-start/README.md @@ -41,6 +41,7 @@ AT32F407-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以 | UART | 支持 | USART1/2/3 | | GPIO | 支持 | PA0...PF7 | | IIC | 支持 | GPIO模拟I2C | +| HWIIC | 支持 | I2C1/2/3 | | SPI | 支持 | SPI1/2 | | ADC | 支持 | ADC1/2 | | DAC | 支持 | DAC1 | diff --git a/bsp/at32/at32f407-start/board/Kconfig b/bsp/at32/at32f407-start/board/Kconfig index 78d5ae066a..1032819de2 100644 --- a/bsp/at32/at32f407-start/board/Kconfig +++ b/bsp/at32/at32f407-start/board/Kconfig @@ -282,6 +282,57 @@ menu "On-chip Peripheral Drivers" endif endif + menuconfig BSP_USING_HARD_I2C + bool "Enable I2C BUS (hardware driver)" + default n + select RT_USING_I2C + if BSP_USING_HARD_I2C + config BSP_USING_HARD_I2C1 + bool "Enable I2C1 BUS" + default n + + config BSP_I2C1_TX_USING_DMA + bool "Enable I2C1 TX DMA" + depends on BSP_USING_HARD_I2C1 + default n + + config BSP_I2C1_RX_USING_DMA + bool "Enable I2C1 RX DMA" + depends on BSP_USING_HARD_I2C1 + select BSP_I2C1_TX_USING_DMA + default n + + config BSP_USING_HARD_I2C2 + bool "Enable I2C2 BUS" + default n + + config BSP_I2C2_TX_USING_DMA + bool "Enable I2C2 TX DMA" + depends on BSP_USING_HARD_I2C2 + default n + + config BSP_I2C2_RX_USING_DMA + bool "Enable I2C2 RX DMA" + depends on BSP_USING_HARD_I2C2 + select BSP_I2C2_TX_USING_DMA + default n + + config BSP_USING_HARD_I2C3 + bool "Enable I2C3 BUS" + default n + + config BSP_I2C3_TX_USING_DMA + bool "Enable I2C3 TX DMA" + depends on BSP_USING_HARD_I2C3 + default n + + config BSP_I2C3_RX_USING_DMA + bool "Enable I2C3 RX DMA" + depends on BSP_USING_HARD_I2C3 + select BSP_I2C3_TX_USING_DMA + default n + endif + menuconfig BSP_USING_ADC bool "Enable ADC" default n diff --git a/bsp/at32/at32f407-start/board/src/at32_msp.c b/bsp/at32/at32f407-start/board/src/at32_msp.c index 23ea2a937b..63ef0c2dee 100644 --- a/bsp/at32/at32f407-start/board/src/at32_msp.c +++ b/bsp/at32/at32f407-start/board/src/at32_msp.c @@ -131,6 +131,60 @@ void at32_msp_spi_init(void *instance) } #endif /* BSP_USING_SPI */ +#ifdef BSP_USING_HARD_I2C +void at32_msp_i2c_init(void *instance) +{ + gpio_init_type gpio_init_struct; + i2c_type *i2c_x = (i2c_type *)instance; + + gpio_default_para_init(&gpio_init_struct); + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; +#ifdef BSP_USING_HARD_I2C1 + if(I2C1 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7; + gpio_init(GPIOB, &gpio_init_struct); + } +#endif +#ifdef BSP_USING_HARD_I2C2 + if(I2C2 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C2_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_10 | GPIO_PINS_11; + gpio_init(GPIOB, &gpio_init_struct); + } +#endif +#ifdef BSP_USING_HARD_I2C3 + if(I2C3 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C3_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_8; + gpio_init(GPIOA, &gpio_init_struct); + gpio_init_struct.gpio_pins = GPIO_PINS_9; + gpio_init(GPIOC, &gpio_init_struct); + } +#endif + /* add others */ +} +#endif /* BSP_USING_HARD_I2C */ + #ifdef BSP_USING_SDIO void at32_msp_sdio_init(void *instance) { diff --git a/bsp/at32/at32f413-start/README.md b/bsp/at32/at32f413-start/README.md index d8bfd68310..5042036452 100644 --- a/bsp/at32/at32f413-start/README.md +++ b/bsp/at32/at32f413-start/README.md @@ -41,6 +41,7 @@ AT32F413-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以 | UART | 支持 | USART1/2/3 | | GPIO | 支持 | PA0...PF5 | | IIC | 支持 | GPIO模拟I2C | +| HWIIC | 支持 | I2C1/2 | | SPI | 支持 | SPI1/2 | | ADC | 支持 | ADC1/2 | | PWM | 支持 | TMR1/2 | diff --git a/bsp/at32/at32f413-start/board/Kconfig b/bsp/at32/at32f413-start/board/Kconfig index b184fd5e38..19b148f6f8 100644 --- a/bsp/at32/at32f413-start/board/Kconfig +++ b/bsp/at32/at32f413-start/board/Kconfig @@ -253,6 +253,42 @@ menu "On-chip Peripheral Drivers" endif endif + menuconfig BSP_USING_HARD_I2C + bool "Enable I2C BUS (hardware driver)" + default n + select RT_USING_I2C + if BSP_USING_HARD_I2C + config BSP_USING_HARD_I2C1 + bool "Enable I2C1 BUS" + default n + + config BSP_I2C1_TX_USING_DMA + bool "Enable I2C1 TX DMA" + depends on BSP_USING_HARD_I2C1 + default n + + config BSP_I2C1_RX_USING_DMA + bool "Enable I2C1 RX DMA" + depends on BSP_USING_HARD_I2C1 + select BSP_I2C1_TX_USING_DMA + default n + + config BSP_USING_HARD_I2C2 + bool "Enable I2C2 BUS" + default n + + config BSP_I2C2_TX_USING_DMA + bool "Enable I2C2 TX DMA" + depends on BSP_USING_HARD_I2C2 + default n + + config BSP_I2C2_RX_USING_DMA + bool "Enable I2C2 RX DMA" + depends on BSP_USING_HARD_I2C2 + select BSP_I2C2_TX_USING_DMA + default n + endif + menuconfig BSP_USING_ADC bool "Enable ADC" default n diff --git a/bsp/at32/at32f413-start/board/src/at32_msp.c b/bsp/at32/at32f413-start/board/src/at32_msp.c index a2e137a632..fc0498c408 100644 --- a/bsp/at32/at32f413-start/board/src/at32_msp.c +++ b/bsp/at32/at32f413-start/board/src/at32_msp.c @@ -129,6 +129,44 @@ void at32_msp_spi_init(void *instance) } #endif /* BSP_USING_SPI */ +#ifdef BSP_USING_HARD_I2C +void at32_msp_i2c_init(void *instance) +{ + gpio_init_type gpio_init_struct; + i2c_type *i2c_x = (i2c_type *)instance; + + gpio_default_para_init(&gpio_init_struct); + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; +#ifdef BSP_USING_HARD_I2C1 + if(I2C1 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7; + gpio_init(GPIOB, &gpio_init_struct); + } +#endif +#ifdef BSP_USING_HARD_I2C2 + if(I2C2 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C2_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_10 | GPIO_PINS_11; + gpio_init(GPIOB, &gpio_init_struct); + } +#endif + /* add others */ +} +#endif /* BSP_USING_HARD_I2C */ + #ifdef BSP_USING_SDIO void at32_msp_sdio_init(void *instance) { diff --git a/bsp/at32/at32f415-start/README.md b/bsp/at32/at32f415-start/README.md index 2727ce40b4..3201f54c59 100644 --- a/bsp/at32/at32f415-start/README.md +++ b/bsp/at32/at32f415-start/README.md @@ -41,6 +41,7 @@ AT32F415-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以 | UART | 支持 | USART1/2/3 | | GPIO | 支持 | PA0...PF5 | | IIC | 支持 | GPIO模拟I2C | +| HWIIC | 支持 | I2C1/2 | | SPI | 支持 | SPI1/2 | | ADC | 支持 | ADC1 | | PWM | 支持 | TMR1/2 | diff --git a/bsp/at32/at32f415-start/board/Kconfig b/bsp/at32/at32f415-start/board/Kconfig index 57d365d634..e7861dc72d 100644 --- a/bsp/at32/at32f415-start/board/Kconfig +++ b/bsp/at32/at32f415-start/board/Kconfig @@ -268,6 +268,42 @@ menu "On-chip Peripheral Drivers" endif endif + menuconfig BSP_USING_HARD_I2C + bool "Enable I2C BUS (hardware driver)" + default n + select RT_USING_I2C + if BSP_USING_HARD_I2C + config BSP_USING_HARD_I2C1 + bool "Enable I2C1 BUS" + default n + + config BSP_I2C1_TX_USING_DMA + bool "Enable I2C1 TX DMA" + depends on BSP_USING_HARD_I2C1 + default n + + config BSP_I2C1_RX_USING_DMA + bool "Enable I2C1 RX DMA" + depends on BSP_USING_HARD_I2C1 + select BSP_I2C1_TX_USING_DMA + default n + + config BSP_USING_HARD_I2C2 + bool "Enable I2C2 BUS" + default n + + config BSP_I2C2_TX_USING_DMA + bool "Enable I2C2 TX DMA" + depends on BSP_USING_HARD_I2C2 + default n + + config BSP_I2C2_RX_USING_DMA + bool "Enable I2C2 RX DMA" + depends on BSP_USING_HARD_I2C2 + select BSP_I2C2_TX_USING_DMA + default n + endif + menuconfig BSP_USING_ADC bool "Enable ADC" default n diff --git a/bsp/at32/at32f415-start/board/src/at32_msp.c b/bsp/at32/at32f415-start/board/src/at32_msp.c index 5fc183eaa7..64db65da7a 100644 --- a/bsp/at32/at32f415-start/board/src/at32_msp.c +++ b/bsp/at32/at32f415-start/board/src/at32_msp.c @@ -129,6 +129,44 @@ void at32_msp_spi_init(void *instance) } #endif /* BSP_USING_SPI */ +#ifdef BSP_USING_HARD_I2C +void at32_msp_i2c_init(void *instance) +{ + gpio_init_type gpio_init_struct; + i2c_type *i2c_x = (i2c_type *)instance; + + gpio_default_para_init(&gpio_init_struct); + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; +#ifdef BSP_USING_HARD_I2C1 + if(I2C1 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7; + gpio_init(GPIOB, &gpio_init_struct); + } +#endif +#ifdef BSP_USING_HARD_I2C2 + if(I2C2 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C2_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_10 | GPIO_PINS_11; + gpio_init(GPIOB, &gpio_init_struct); + } +#endif + /* add others */ +} +#endif /* BSP_USING_HARD_I2C */ + #ifdef BSP_USING_SDIO void at32_msp_sdio_init(void *instance) { diff --git a/bsp/at32/at32f421-start/README.md b/bsp/at32/at32f421-start/README.md index 80ceadbfa2..d8b987553c 100644 --- a/bsp/at32/at32f421-start/README.md +++ b/bsp/at32/at32f421-start/README.md @@ -41,6 +41,7 @@ AT32F421-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以 | UART | 支持 | USART1/2 | | GPIO | 支持 | PA0...PF7 | | IIC | 支持 | GPIO模拟I2C | +| HWIIC | 支持 | I2C1/2 | | SPI | 支持 | SPI1/2 | | ADC | 支持 | ADC1 | | PWM | 支持 | TMR1 | diff --git a/bsp/at32/at32f421-start/board/Kconfig b/bsp/at32/at32f421-start/board/Kconfig index 85b3a545e6..16abb90011 100644 --- a/bsp/at32/at32f421-start/board/Kconfig +++ b/bsp/at32/at32f421-start/board/Kconfig @@ -203,6 +203,42 @@ menu "On-chip Peripheral Drivers" endif endif + menuconfig BSP_USING_HARD_I2C + bool "Enable I2C BUS (hardware driver)" + default n + select RT_USING_I2C + if BSP_USING_HARD_I2C + config BSP_USING_HARD_I2C1 + bool "Enable I2C1 BUS" + default n + + config BSP_I2C1_TX_USING_DMA + bool "Enable I2C1 TX DMA" + depends on BSP_USING_HARD_I2C1 + default n + + config BSP_I2C1_RX_USING_DMA + bool "Enable I2C1 RX DMA" + depends on BSP_USING_HARD_I2C1 + select BSP_I2C1_TX_USING_DMA + default n + + config BSP_USING_HARD_I2C2 + bool "Enable I2C2 BUS" + default n + + config BSP_I2C2_TX_USING_DMA + bool "Enable I2C2 TX DMA" + depends on BSP_USING_HARD_I2C2 + default n + + config BSP_I2C2_RX_USING_DMA + bool "Enable I2C2 RX DMA" + depends on BSP_USING_HARD_I2C2 + select BSP_I2C2_TX_USING_DMA + default n + endif + menuconfig BSP_USING_ADC bool "Enable ADC" default n diff --git a/bsp/at32/at32f421-start/board/inc/at32_msp.h b/bsp/at32/at32f421-start/board/inc/at32_msp.h index a5bb12535b..69de853e72 100644 --- a/bsp/at32/at32f421-start/board/inc/at32_msp.h +++ b/bsp/at32/at32f421-start/board/inc/at32_msp.h @@ -16,5 +16,6 @@ void at32_msp_spi_init(void *instance); void at32_msp_tmr_init(void *instance); void at32_msp_adc_init(void *instance); void at32_msp_hwtmr_init(void *instance); +void at32_msp_i2c_init(void *instance); #endif /* __AT32_MSP_H__ */ diff --git a/bsp/at32/at32f421-start/board/src/at32_msp.c b/bsp/at32/at32f421-start/board/src/at32_msp.c index e321e050b8..a5221a799d 100644 --- a/bsp/at32/at32f421-start/board/src/at32_msp.c +++ b/bsp/at32/at32f421-start/board/src/at32_msp.c @@ -116,6 +116,50 @@ void at32_msp_spi_init(void *instance) } #endif /* BSP_USING_SPI */ +#ifdef BSP_USING_HARD_I2C +void at32_msp_i2c_init(void *instance) +{ + gpio_init_type gpio_init_struct; + i2c_type *i2c_x = (i2c_type *)instance; + + gpio_default_para_init(&gpio_init_struct); + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; +#ifdef BSP_USING_HARD_I2C1 + if(I2C1 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7; + gpio_init(GPIOB, &gpio_init_struct); + + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE6, GPIO_MUX_1); + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE7, GPIO_MUX_1); + } +#endif +#ifdef BSP_USING_HARD_I2C2 + if(I2C2 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C2_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_10 | GPIO_PINS_11; + gpio_init(GPIOB, &gpio_init_struct); + + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE10, GPIO_MUX_1); + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE11, GPIO_MUX_1); + } +#endif + /* add others */ +} +#endif /* BSP_USING_HARD_I2C */ + #ifdef BSP_USING_PWM void at32_msp_tmr_init(void *instance) { diff --git a/bsp/at32/at32f423-start/README.md b/bsp/at32/at32f423-start/README.md index cf029f9a09..c574adbca5 100644 --- a/bsp/at32/at32f423-start/README.md +++ b/bsp/at32/at32f423-start/README.md @@ -41,6 +41,7 @@ AT32F423-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以 | UART | 支持 | USART1/2/3 | | GPIO | 支持 | PA0...PF10 | | IIC | 支持 | GPIO模拟I2C | +| HWIIC | 支持 | I2C1/2/3 | | SPI | 支持 | SPI1/2 | | ADC | 支持 | ADC1 | | DAC | 支持 | DAC1 | diff --git a/bsp/at32/at32f423-start/board/Kconfig b/bsp/at32/at32f423-start/board/Kconfig index 2f3caa16f6..13d3a8b173 100644 --- a/bsp/at32/at32f423-start/board/Kconfig +++ b/bsp/at32/at32f423-start/board/Kconfig @@ -277,6 +277,57 @@ menu "On-chip Peripheral Drivers" endif endif + menuconfig BSP_USING_HARD_I2C + bool "Enable I2C BUS (hardware driver)" + default n + select RT_USING_I2C + if BSP_USING_HARD_I2C + config BSP_USING_HARD_I2C1 + bool "Enable I2C1 BUS" + default n + + config BSP_I2C1_TX_USING_DMA + bool "Enable I2C1 TX DMA" + depends on BSP_USING_HARD_I2C1 + default n + + config BSP_I2C1_RX_USING_DMA + bool "Enable I2C1 RX DMA" + depends on BSP_USING_HARD_I2C1 + select BSP_I2C1_TX_USING_DMA + default n + + config BSP_USING_HARD_I2C2 + bool "Enable I2C2 BUS" + default n + + config BSP_I2C2_TX_USING_DMA + bool "Enable I2C2 TX DMA" + depends on BSP_USING_HARD_I2C2 + default n + + config BSP_I2C2_RX_USING_DMA + bool "Enable I2C2 RX DMA" + depends on BSP_USING_HARD_I2C2 + select BSP_I2C2_TX_USING_DMA + default n + + config BSP_USING_HARD_I2C3 + bool "Enable I2C3 BUS" + default n + + config BSP_I2C3_TX_USING_DMA + bool "Enable I2C3 TX DMA" + depends on BSP_USING_HARD_I2C3 + default n + + config BSP_I2C3_RX_USING_DMA + bool "Enable I2C3 RX DMA" + depends on BSP_USING_HARD_I2C3 + select BSP_I2C3_TX_USING_DMA + default n + endif + menuconfig BSP_USING_ADC bool "Enable ADC" default n diff --git a/bsp/at32/at32f423-start/board/inc/at32_msp.h b/bsp/at32/at32f423-start/board/inc/at32_msp.h index fad72d455c..e072121a29 100644 --- a/bsp/at32/at32f423-start/board/inc/at32_msp.h +++ b/bsp/at32/at32f423-start/board/inc/at32_msp.h @@ -19,5 +19,6 @@ void at32_msp_hwtmr_init(void *instance); void at32_msp_can_init(void *instance); void at32_msp_usb_init(void *instance); void at32_msp_dac_init(void *instance); +void at32_msp_i2c_init(void *instance); #endif /* __AT32_MSP_H__ */ diff --git a/bsp/at32/at32f423-start/board/src/at32_msp.c b/bsp/at32/at32f423-start/board/src/at32_msp.c index e109cede2b..396e8622e8 100644 --- a/bsp/at32/at32f423-start/board/src/at32_msp.c +++ b/bsp/at32/at32f423-start/board/src/at32_msp.c @@ -135,6 +135,69 @@ void at32_msp_spi_init(void *instance) } #endif /* BSP_USING_SPI */ +#ifdef BSP_USING_HARD_I2C +void at32_msp_i2c_init(void *instance) +{ + gpio_init_type gpio_init_struct; + i2c_type *i2c_x = (i2c_type *)instance; + + gpio_default_para_init(&gpio_init_struct); + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; +#ifdef BSP_USING_HARD_I2C1 + if(I2C1 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7; + gpio_init(GPIOB, &gpio_init_struct); + + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE6, GPIO_MUX_4); + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE7, GPIO_MUX_4); + } +#endif +#ifdef BSP_USING_HARD_I2C2 + if(I2C2 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C2_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_10 | GPIO_PINS_11; + gpio_init(GPIOB, &gpio_init_struct); + + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE10, GPIO_MUX_4); + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE11, GPIO_MUX_4); + } +#endif +#ifdef BSP_USING_HARD_I2C3 + if(I2C3 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C3_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_8; + gpio_init(GPIOA, &gpio_init_struct); + gpio_init_struct.gpio_pins = GPIO_PINS_9; + gpio_init(GPIOC, &gpio_init_struct); + + gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE8, GPIO_MUX_4); + gpio_pin_mux_config(GPIOC, GPIO_PINS_SOURCE9, GPIO_MUX_4); + } +#endif + /* add others */ +} +#endif /* BSP_USING_HARD_I2C */ + #ifdef BSP_USING_PWM void at32_msp_tmr_init(void *instance) { diff --git a/bsp/at32/at32f425-start/README.md b/bsp/at32/at32f425-start/README.md index d03cd087fe..46cdceda87 100644 --- a/bsp/at32/at32f425-start/README.md +++ b/bsp/at32/at32f425-start/README.md @@ -41,6 +41,7 @@ AT32F425-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以 | UART | 支持 | USART1/2/3 | | GPIO | 支持 | PA0...PF7 | | IIC | 支持 | GPIO模拟I2C | +| HWIIC | 支持 | I2C1/2 | | SPI | 支持 | SPI1/2 | | ADC | 支持 | ADC1 | | PWM | 支持 | TMR1/2 | diff --git a/bsp/at32/at32f425-start/board/Kconfig b/bsp/at32/at32f425-start/board/Kconfig index 7937f438d2..4a517ac6f5 100644 --- a/bsp/at32/at32f425-start/board/Kconfig +++ b/bsp/at32/at32f425-start/board/Kconfig @@ -277,6 +277,42 @@ menu "On-chip Peripheral Drivers" endif endif + menuconfig BSP_USING_HARD_I2C + bool "Enable I2C BUS (hardware driver)" + default n + select RT_USING_I2C + if BSP_USING_HARD_I2C + config BSP_USING_HARD_I2C1 + bool "Enable I2C1 BUS" + default n + + config BSP_I2C1_TX_USING_DMA + bool "Enable I2C1 TX DMA" + depends on BSP_USING_HARD_I2C1 + default n + + config BSP_I2C1_RX_USING_DMA + bool "Enable I2C1 RX DMA" + depends on BSP_USING_HARD_I2C1 + select BSP_I2C1_TX_USING_DMA + default n + + config BSP_USING_HARD_I2C2 + bool "Enable I2C2 BUS" + default n + + config BSP_I2C2_TX_USING_DMA + bool "Enable I2C2 TX DMA" + depends on BSP_USING_HARD_I2C2 + default n + + config BSP_I2C2_RX_USING_DMA + bool "Enable I2C2 RX DMA" + depends on BSP_USING_HARD_I2C2 + select BSP_I2C2_TX_USING_DMA + default n + endif + menuconfig BSP_USING_ADC bool "Enable ADC" default n diff --git a/bsp/at32/at32f425-start/board/inc/at32_msp.h b/bsp/at32/at32f425-start/board/inc/at32_msp.h index c2eb468175..c002259b47 100644 --- a/bsp/at32/at32f425-start/board/inc/at32_msp.h +++ b/bsp/at32/at32f425-start/board/inc/at32_msp.h @@ -18,5 +18,6 @@ void at32_msp_adc_init(void *instance); void at32_msp_hwtmr_init(void *instance); void at32_msp_can_init(void *instance); void at32_msp_usb_init(void *instance); +void at32_msp_i2c_init(void *instance); #endif /* __AT32_MSP_H__ */ diff --git a/bsp/at32/at32f425-start/board/src/at32_msp.c b/bsp/at32/at32f425-start/board/src/at32_msp.c index 1c781af19f..4f0ba76955 100644 --- a/bsp/at32/at32f425-start/board/src/at32_msp.c +++ b/bsp/at32/at32f425-start/board/src/at32_msp.c @@ -135,6 +135,50 @@ void at32_msp_spi_init(void *instance) } #endif /* BSP_USING_SPI */ +#ifdef BSP_USING_HARD_I2C +void at32_msp_i2c_init(void *instance) +{ + gpio_init_type gpio_init_struct; + i2c_type *i2c_x = (i2c_type *)instance; + + gpio_default_para_init(&gpio_init_struct); + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; +#ifdef BSP_USING_HARD_I2C1 + if(I2C1 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7; + gpio_init(GPIOB, &gpio_init_struct); + + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE6, GPIO_MUX_1); + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE7, GPIO_MUX_1); + } +#endif +#ifdef BSP_USING_HARD_I2C2 + if(I2C2 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C2_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_10 | GPIO_PINS_11; + gpio_init(GPIOB, &gpio_init_struct); + + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE10, GPIO_MUX_1); + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE11, GPIO_MUX_1); + } +#endif + /* add others */ +} +#endif /* BSP_USING_HARD_I2C */ + #ifdef BSP_USING_PWM void at32_msp_tmr_init(void *instance) { diff --git a/bsp/at32/at32f435-start/README.md b/bsp/at32/at32f435-start/README.md index 4217a3ba91..3dae129767 100644 --- a/bsp/at32/at32f435-start/README.md +++ b/bsp/at32/at32f435-start/README.md @@ -41,6 +41,7 @@ AT32F437-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以 | UART | 支持 | USART1/2/3 | | GPIO | 支持 | PA0...PH7 | | IIC | 支持 | GPIO模拟I2C | +| HWIIC | 支持 | I2C1/2/3 | | SPI | 支持 | SPI1/2 | | ADC | 支持 | ADC1/2 | | DAC | 支持 | DAC1 | diff --git a/bsp/at32/at32f435-start/board/Kconfig b/bsp/at32/at32f435-start/board/Kconfig index 4c245df038..828d66eba4 100644 --- a/bsp/at32/at32f435-start/board/Kconfig +++ b/bsp/at32/at32f435-start/board/Kconfig @@ -314,6 +314,57 @@ menu "On-chip Peripheral Drivers" endif endif + menuconfig BSP_USING_HARD_I2C + bool "Enable I2C BUS (hardware driver)" + default n + select RT_USING_I2C + if BSP_USING_HARD_I2C + config BSP_USING_HARD_I2C1 + bool "Enable I2C1 BUS" + default n + + config BSP_I2C1_TX_USING_DMA + bool "Enable I2C1 TX DMA" + depends on BSP_USING_HARD_I2C1 + default n + + config BSP_I2C1_RX_USING_DMA + bool "Enable I2C1 RX DMA" + depends on BSP_USING_HARD_I2C1 + select BSP_I2C1_TX_USING_DMA + default n + + config BSP_USING_HARD_I2C2 + bool "Enable I2C2 BUS" + default n + + config BSP_I2C2_TX_USING_DMA + bool "Enable I2C2 TX DMA" + depends on BSP_USING_HARD_I2C2 + default n + + config BSP_I2C2_RX_USING_DMA + bool "Enable I2C2 RX DMA" + depends on BSP_USING_HARD_I2C2 + select BSP_I2C2_TX_USING_DMA + default n + + config BSP_USING_HARD_I2C3 + bool "Enable I2C3 BUS" + default n + + config BSP_I2C3_TX_USING_DMA + bool "Enable I2C3 TX DMA" + depends on BSP_USING_HARD_I2C3 + default n + + config BSP_I2C3_RX_USING_DMA + bool "Enable I2C3 RX DMA" + depends on BSP_USING_HARD_I2C3 + select BSP_I2C3_TX_USING_DMA + default n + endif + menuconfig BSP_USING_ADC bool "Enable ADC" default n diff --git a/bsp/at32/at32f435-start/board/src/at32_msp.c b/bsp/at32/at32f435-start/board/src/at32_msp.c index 056ae2266e..dcd558ae8c 100644 --- a/bsp/at32/at32f435-start/board/src/at32_msp.c +++ b/bsp/at32/at32f435-start/board/src/at32_msp.c @@ -126,6 +126,69 @@ void at32_msp_spi_init(void *instance) } #endif /* BSP_USING_SPI */ +#ifdef BSP_USING_HARD_I2C +void at32_msp_i2c_init(void *instance) +{ + gpio_init_type gpio_init_struct; + i2c_type *i2c_x = (i2c_type *)instance; + + gpio_default_para_init(&gpio_init_struct); + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; +#ifdef BSP_USING_HARD_I2C1 + if(I2C1 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7; + gpio_init(GPIOB, &gpio_init_struct); + + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE6, GPIO_MUX_4); + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE7, GPIO_MUX_4); + } +#endif +#ifdef BSP_USING_HARD_I2C2 + if(I2C2 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C2_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_10 | GPIO_PINS_11; + gpio_init(GPIOB, &gpio_init_struct); + + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE10, GPIO_MUX_4); + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE11, GPIO_MUX_4); + } +#endif +#ifdef BSP_USING_HARD_I2C3 + if(I2C3 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C3_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_8; + gpio_init(GPIOA, &gpio_init_struct); + gpio_init_struct.gpio_pins = GPIO_PINS_9; + gpio_init(GPIOC, &gpio_init_struct); + + gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE8, GPIO_MUX_4); + gpio_pin_mux_config(GPIOC, GPIO_PINS_SOURCE9, GPIO_MUX_4); + } +#endif + /* add others */ +} +#endif /* BSP_USING_HARD_I2C */ + #ifdef BSP_USING_SDIO void at32_msp_sdio_init(void *instance) { diff --git a/bsp/at32/at32f437-start/README.md b/bsp/at32/at32f437-start/README.md index 8e43ada974..6ce3bfa7ab 100644 --- a/bsp/at32/at32f437-start/README.md +++ b/bsp/at32/at32f437-start/README.md @@ -41,6 +41,7 @@ AT32F437-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以 | UART | 支持 | USART1/2/3 | | GPIO | 支持 | PA0...PH7 | | IIC | 支持 | GPIO模拟I2C | +| HWIIC | 支持 | I2C1/2/3 | | SPI | 支持 | SPI1/2 | | ADC | 支持 | ADC1/2 | | DAC | 支持 | DAC1 | diff --git a/bsp/at32/at32f437-start/board/Kconfig b/bsp/at32/at32f437-start/board/Kconfig index 9a9e889270..8dc22159dd 100644 --- a/bsp/at32/at32f437-start/board/Kconfig +++ b/bsp/at32/at32f437-start/board/Kconfig @@ -331,6 +331,57 @@ menu "On-chip Peripheral Drivers" endif endif + menuconfig BSP_USING_HARD_I2C + bool "Enable I2C BUS (hardware driver)" + default n + select RT_USING_I2C + if BSP_USING_HARD_I2C + config BSP_USING_HARD_I2C1 + bool "Enable I2C1 BUS" + default n + + config BSP_I2C1_TX_USING_DMA + bool "Enable I2C1 TX DMA" + depends on BSP_USING_HARD_I2C1 + default n + + config BSP_I2C1_RX_USING_DMA + bool "Enable I2C1 RX DMA" + depends on BSP_USING_HARD_I2C1 + select BSP_I2C1_TX_USING_DMA + default n + + config BSP_USING_HARD_I2C2 + bool "Enable I2C2 BUS" + default n + + config BSP_I2C2_TX_USING_DMA + bool "Enable I2C2 TX DMA" + depends on BSP_USING_HARD_I2C2 + default n + + config BSP_I2C2_RX_USING_DMA + bool "Enable I2C2 RX DMA" + depends on BSP_USING_HARD_I2C2 + select BSP_I2C2_TX_USING_DMA + default n + + config BSP_USING_HARD_I2C3 + bool "Enable I2C3 BUS" + default n + + config BSP_I2C3_TX_USING_DMA + bool "Enable I2C3 TX DMA" + depends on BSP_USING_HARD_I2C3 + default n + + config BSP_I2C3_RX_USING_DMA + bool "Enable I2C3 RX DMA" + depends on BSP_USING_HARD_I2C3 + select BSP_I2C3_TX_USING_DMA + default n + endif + menuconfig BSP_USING_ADC bool "Enable ADC" default n diff --git a/bsp/at32/at32f437-start/board/src/at32_msp.c b/bsp/at32/at32f437-start/board/src/at32_msp.c index 45f8049b16..1a22f367f1 100644 --- a/bsp/at32/at32f437-start/board/src/at32_msp.c +++ b/bsp/at32/at32f437-start/board/src/at32_msp.c @@ -127,6 +127,69 @@ void at32_msp_spi_init(void *instance) } #endif /* BSP_USING_SPI */ +#ifdef BSP_USING_HARD_I2C +void at32_msp_i2c_init(void *instance) +{ + gpio_init_type gpio_init_struct; + i2c_type *i2c_x = (i2c_type *)instance; + + gpio_default_para_init(&gpio_init_struct); + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; +#ifdef BSP_USING_HARD_I2C1 + if(I2C1 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7; + gpio_init(GPIOB, &gpio_init_struct); + + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE6, GPIO_MUX_4); + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE7, GPIO_MUX_4); + } +#endif +#ifdef BSP_USING_HARD_I2C2 + if(I2C2 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C2_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_10 | GPIO_PINS_11; + gpio_init(GPIOB, &gpio_init_struct); + + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE10, GPIO_MUX_4); + gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE11, GPIO_MUX_4); + } +#endif +#ifdef BSP_USING_HARD_I2C3 + if(I2C3 == i2c_x) + { + crm_periph_clock_enable(CRM_I2C3_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE); + crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE); + + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init_struct.gpio_pins = GPIO_PINS_8; + gpio_init(GPIOA, &gpio_init_struct); + gpio_init_struct.gpio_pins = GPIO_PINS_9; + gpio_init(GPIOC, &gpio_init_struct); + + gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE8, GPIO_MUX_4); + gpio_pin_mux_config(GPIOC, GPIO_PINS_SOURCE9, GPIO_MUX_4); + } +#endif + /* add others */ +} +#endif /* BSP_USING_HARD_I2C */ + #ifdef BSP_USING_SDIO void at32_msp_sdio_init(void *instance) { diff --git a/bsp/at32/libraries/.ignore_format.yml b/bsp/at32/libraries/.ignore_format.yml new file mode 100644 index 0000000000..43e3e13167 --- /dev/null +++ b/bsp/at32/libraries/.ignore_format.yml @@ -0,0 +1,15 @@ +# files format check exclude path, please follow the instructions below to modify; +# If you need to exclude an entire folder, add the folder path in dir_path; +# If you need to exclude a file, add the path to the file in file_path. + +dir_path: +- AT32A403A_Firmware_Library +- AT32A423_Firmware_Library +- AT32F402_405_Firmware_Library +- AT32F403A_407_Firmware_Library +- AT32F413_Firmware_Library +- AT32F415_Firmware_Library +- AT32F421_Firmware_Library +- AT32F423_Firmware_Library +- AT32F425_Firmware_Library +- AT32F435_437_Firmware_Library \ No newline at end of file diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/cmsis/cm4/device_support/system_at32f402_405.c b/bsp/at32/libraries/AT32F402_405_Firmware_Library/cmsis/cm4/device_support/system_at32f402_405.c index 3ae8ffef98..c5c1fb82e5 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/cmsis/cm4/device_support/system_at32f402_405.c +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/cmsis/cm4/device_support/system_at32f402_405.c @@ -179,6 +179,50 @@ void system_core_clock_update(void) system_core_clock = system_core_clock >> div_value; } +/** + * @brief reduce power consumption initialize + * If OTGHS is not used, call this function to reduce power consumption. + * PLL or HEXT should be enabled when calling this function. + * + * If OTGHS is required, initialize OTGHS to reduce power consumption, + * without the need to call this function. + * @param none + * @retval none + */ +void reduce_power_consumption(void) +{ + volatile uint32_t delay = 0x34BC0; + if(CRM->ctrl_bit.hextstbl) + { + *(__IO uint32_t *)0x40023878 = 0x00; + } + else if(CRM->ctrl_bit.pllstbl == SET) + { + CRM->pllcfg_bit.plluen = TRUE; + while(CRM->ctrl_bit.pllstbl != SET || CRM->ctrl_bit.pllustbl != SET); + *(__IO uint32_t *)0x40023878 = 0x10; + } + else + { + /* the pll or hext need to be enable */ + return; + } + CRM->ahben1 |= 1 << 29; + *(__IO uint32_t *)0x40040038 = 0x210000; + *(__IO uint32_t *)0x4004000C |= 0x40000000; + *(__IO uint32_t *)0x40040804 &= ~0x2; + while(delay --) + { + if(*(__IO uint32_t *)0x40040808 & 0x1) + break; + } + *(__IO uint32_t *)0x40040038 |= 0x400000; + *(__IO uint32_t *)0x40040E00 |= 0x1; + *(__IO uint32_t *)0x40040038 &= ~0x10000; + *(__IO uint32_t *)0x40023878 = 0x0; + return; +} + /** * @} */ diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/cmsis/cm4/device_support/system_at32f402_405.h b/bsp/at32/libraries/AT32F402_405_Firmware_Library/cmsis/cm4/device_support/system_at32f402_405.h index 505accc409..f215decd4f 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/cmsis/cm4/device_support/system_at32f402_405.h +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/cmsis/cm4/device_support/system_at32f402_405.h @@ -52,6 +52,7 @@ extern unsigned int system_core_clock; /*!< system clock frequency (core clock) extern void SystemInit(void); extern void system_core_clock_update(void); +extern void reduce_power_consumption(void); /** * @} diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_acc.h b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_acc.h index fca7522003..7dbca2ca4e 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_acc.h +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_acc.h @@ -178,6 +178,7 @@ uint16_t acc_read_c1(void); uint16_t acc_read_c2(void); uint16_t acc_read_c3(void); flag_status acc_flag_get(uint16_t acc_flag); +flag_status acc_interrupt_flag_get(uint16_t acc_flag); void acc_flag_clear(uint16_t acc_flag); /** diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_adc.h b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_adc.h index 40464531d8..bcf387e511 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_adc.h +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_adc.h @@ -1,7 +1,7 @@ /** ************************************************************************** - * @file at32f425_adc.h - * @brief at32f425 adc header file + * @file at32f402_405_adc.h + * @brief at32f402_405 adc header file ************************************************************************** * Copyright notice & Disclaimer * @@ -34,7 +34,7 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "at32f402_405.h" -/** @addtogroup AT32F425_periph_driver +/** @addtogroup AT32F402_405_periph_driver * @{ */ @@ -688,6 +688,7 @@ flag_status adc_preempt_software_trigger_status_get(adc_type *adc_x); uint16_t adc_ordinary_conversion_data_get(adc_type *adc_x); uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel); flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag); +flag_status adc_interrupt_flag_get(adc_type *adc_x, uint8_t adc_flag); void adc_flag_clear(adc_type *adc_x, uint32_t adc_flag); void adc_ordinary_oversample_enable(adc_type *adc_x, confirm_state new_state); void adc_preempt_oversample_enable(adc_type *adc_x, confirm_state new_state); diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_can.h b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_can.h index 395d84c89e..9bd92caae5 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_can.h +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_can.h @@ -1018,6 +1018,7 @@ can_error_record_type can_error_type_record_get(can_type* can_x); uint8_t can_receive_error_counter_get(can_type* can_x); uint8_t can_transmit_error_counter_get(can_type* can_x); void can_interrupt_enable(can_type* can_x, uint32_t can_int, confirm_state new_state); +flag_status can_interrupt_flag_get(can_type* can_x, uint32_t can_flag); flag_status can_flag_get(can_type* can_x, uint32_t can_flag); void can_flag_clear(can_type* can_x, uint32_t can_flag); diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_crm.h b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_crm.h index dc3faacc58..8eee924b5d 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_crm.h +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_crm.h @@ -461,8 +461,7 @@ typedef enum CRM_CLKOUT_ADC = 0x11, /*!< output adcclk to clkout pin */ CRM_CLKOUT_HICK = 0x12, /*!< output high speed internal clock to clkout pin */ CRM_CLKOUT_LICK = 0x13, /*!< output low speed internal clock to clkout pin */ - CRM_CLKOUT_LEXT = 0x14, /*!< output low speed external crystal to clkout pin */ - CRM_CLKOUT_USBHS = 0x15 /*!< output usbhsclk to clkout pin */ + CRM_CLKOUT_LEXT = 0x14 /*!< output low speed external crystal to clkout pin */ } crm_clkout_select_type; /** @@ -1179,6 +1178,7 @@ void crm_reset(void); void crm_lext_bypass(confirm_state new_state); void crm_hext_bypass(confirm_state new_state); flag_status crm_flag_get(uint32_t flag); +flag_status crm_interrupt_flag_get(uint32_t flag); error_status crm_hext_stable_wait(void); void crm_hick_clock_trimming_set(uint8_t trim_value); void crm_hick_clock_calibration_set(uint8_t cali_value); diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_debug.h b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_debug.h index 85d2b984c6..954ef3d3aa 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_debug.h +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_debug.h @@ -113,6 +113,7 @@ typedef struct __IO uint32_t reserved1 : 29;/* [31:3] */ } ctrl_bit; }; + /** * @brief debug apb1 frz register, offset:0x08 */ @@ -145,8 +146,9 @@ typedef struct __IO uint32_t reserved6 : 3;/* [31:29] */ } apb1_frz_bit; }; + /** - * @brief debug apb2 frz register, offset:0x0c + * @brief debug apb2 frz register, offset:0x0C */ union { @@ -163,6 +165,26 @@ typedef struct } apb2_frz_bit; }; + /** + * @brief debug reserved1 register, offset:0x10~0x1C + */ + __IO uint32_t reserved1[4]; + + /** + * @brief debug ser id register, offset:0x20 + */ + union + { + __IO uint32_t ser_id; + struct + { + __IO uint32_t rev_id : 3;/* [2:0] */ + __IO uint32_t reserved1 : 5;/* [7:3] */ + __IO uint32_t ser_id : 8;/* [15:8] */ + __IO uint32_t reserved2 : 16;/* [31:16] */ + } ser_id_bit; + }; + } debug_type; /** diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_dma.h b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_dma.h index 71c95cd74b..59cf7e41d7 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_dma.h +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_dma.h @@ -727,6 +727,7 @@ uint16_t dma_data_number_get(dma_channel_type *dmax_channely); void dma_interrupt_enable(dma_channel_type *dmax_channely, uint32_t dma_int, confirm_state new_state); void dma_channel_enable(dma_channel_type *dmax_channely, confirm_state new_state); flag_status dma_flag_get(uint32_t dmax_flag); +flag_status dma_interrupt_flag_get(uint32_t dmax_flag); void dma_flag_clear(uint32_t dmax_flag); void dma_default_para_init(dma_init_type *dma_init_struct); void dma_init(dma_channel_type *dmax_channely, dma_init_type *dma_init_struct); @@ -742,8 +743,10 @@ void dmamux_generator_config(dmamux_generator_type *dmamux_gen_x, dmamux_gen_ini void dmamux_sync_interrupt_enable(dmamux_channel_type *dmamux_channelx, confirm_state new_state); void dmamux_generator_interrupt_enable(dmamux_generator_type *dmamux_gen_x, confirm_state new_state); flag_status dmamux_sync_flag_get(dma_type *dma_x, uint32_t flag); +flag_status dmamux_sync_interrupt_flag_get(dma_type *dma_x, uint32_t flag); void dmamux_sync_flag_clear(dma_type *dma_x, uint32_t flag); flag_status dmamux_generator_flag_get(dma_type *dma_x, uint32_t flag); +flag_status dmamux_generator_interrupt_flag_get(dma_type *dma_x, uint32_t flag); void dmamux_generator_flag_clear(dma_type *dma_x, uint32_t flag); /** diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_ertc.h b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_ertc.h index 0d17d6f7a9..a2e1a4a6da 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_ertc.h +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_ertc.h @@ -1174,6 +1174,7 @@ void ertc_tamper_enable(ertc_tamper_select_type tamper_x, confirm_state new_stat void ertc_interrupt_enable(uint32_t source, confirm_state new_state); flag_status ertc_interrupt_get(uint32_t source); flag_status ertc_flag_get(uint32_t flag); +flag_status ertc_interrupt_flag_get(uint32_t flag); void ertc_flag_clear(uint32_t flag); void ertc_bpr_data_write(ertc_dt_type dt, uint32_t data); uint32_t ertc_bpr_data_read(ertc_dt_type dt); diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_exint.h b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_exint.h index 9a428982da..3171859d7c 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_exint.h +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_exint.h @@ -209,6 +209,7 @@ void exint_default_para_init(exint_init_type *exint_struct); void exint_init(exint_init_type *exint_struct); void exint_flag_clear(uint32_t exint_line); flag_status exint_flag_get(uint32_t exint_line); +flag_status exint_interrupt_flag_get(uint32_t exint_line); void exint_software_interrupt_event_generate(uint32_t exint_line); void exint_interrupt_enable(uint32_t exint_line, confirm_state new_state); void exint_event_enable(uint32_t exint_line, confirm_state new_state); diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_i2c.h b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_i2c.h index 36263c2c3e..bed3ed62d8 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_i2c.h +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_i2c.h @@ -155,12 +155,12 @@ typedef enum { I2C_ADDR2_NOMASK = 0x00, /*!< compare bit [7:1] */ I2C_ADDR2_MASK01 = 0x01, /*!< only compare bit [7:2] */ - I2C_ADDR2_MASK02 = 0x02, /*!< only compare bit [7:2] */ - I2C_ADDR2_MASK03 = 0x03, /*!< only compare bit [7:3] */ - I2C_ADDR2_MASK04 = 0x04, /*!< only compare bit [7:4] */ - I2C_ADDR2_MASK05 = 0x05, /*!< only compare bit [7:5] */ - I2C_ADDR2_MASK06 = 0x06, /*!< only compare bit [7:6] */ - I2C_ADDR2_MASK07 = 0x07 /*!< only compare bit [7] */ + I2C_ADDR2_MASK02 = 0x02, /*!< only compare bit [7:3] */ + I2C_ADDR2_MASK03 = 0x03, /*!< only compare bit [7:4] */ + I2C_ADDR2_MASK04 = 0x04, /*!< only compare bit [7:5] */ + I2C_ADDR2_MASK05 = 0x05, /*!< only compare bit [7:6] */ + I2C_ADDR2_MASK06 = 0x06, /*!< only compare bit [7] */ + I2C_ADDR2_MASK07 = 0x07 /*!< response all addresses other than those reserved for i2c */ } i2c_addr2_mask_type; /** @@ -456,6 +456,7 @@ void i2c_stop_generate(i2c_type *i2c_x); void i2c_data_send(i2c_type *i2c_x, uint8_t data); uint8_t i2c_data_receive(i2c_type *i2c_x); flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag); +flag_status i2c_interrupt_flag_get(i2c_type *i2c_x, uint32_t flag); void i2c_flag_clear(i2c_type *i2c_x, uint32_t flag); /** diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_pwc.h b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_pwc.h index f42000a802..10887dfecb 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_pwc.h +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_pwc.h @@ -126,8 +126,7 @@ typedef enum typedef enum { PWC_REGULATOR_ON = 0x00, /*!< voltage regulator state on when deepsleep mode */ - PWC_REGULATOR_LOW_POWER = 0x01, /*!< voltage regulator state low power when deepsleep mode */ - PWC_REGULATOR_EXTRA_LOW_POWER = 0x02 /*!< voltage regulator state extra low power when deepsleep mode */ + PWC_REGULATOR_EXTRA_LOW_POWER = 0x01 /*!< voltage regulator state extra low power when deepsleep mode */ } pwc_regulator_type ; /** diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_qspi.h b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_qspi.h index 9f87cfbe53..5350ff2e30 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_qspi.h +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_qspi.h @@ -121,11 +121,11 @@ typedef enum typedef enum { QSPI_CLK_DIV_2 = 0x00, /*!< qspi clk divide by 2 */ + QSPI_CLK_DIV_3 = 0x04, /*!< qspi clk divide by 3 */ QSPI_CLK_DIV_4 = 0x01, /*!< qspi clk divide by 4 */ + QSPI_CLK_DIV_5 = 0x05, /*!< qspi clk divide by 5 */ QSPI_CLK_DIV_6 = 0x02, /*!< qspi clk divide by 6 */ QSPI_CLK_DIV_8 = 0x03, /*!< qspi clk divide by 8 */ - QSPI_CLK_DIV_3 = 0x04, /*!< qspi clk divide by 3 */ - QSPI_CLK_DIV_5 = 0x05, /*!< qspi clk divide by 5 */ QSPI_CLK_DIV_10 = 0x06, /*!< qspi clk divide by 10 */ QSPI_CLK_DIV_12 = 0x07 /*!< qspi clk divide by 12 */ } qspi_clk_div_type; @@ -177,7 +177,7 @@ typedef enum { QSPI_DMA_FIFO_THOD_WORD08 = 0x00, /*!< qspi dma fifo threshold 8 words */ QSPI_DMA_FIFO_THOD_WORD16 = 0x01, /*!< qspi dma fifo threshold 16 words */ - QSPI_DMA_FIFO_THOD_WORD32 = 0x02 /*!< qspi dma fifo threshold 32 words */ + QSPI_DMA_FIFO_THOD_WORD24 = 0x02 /*!< qspi dma fifo threshold 24 words */ } qspi_dma_fifo_thod_type; /** @@ -185,7 +185,7 @@ typedef enum */ typedef struct { - confirm_state pe_mode_enable; /*!< perfornance enhance mode enable */ + confirm_state pe_mode_enable; /*!< performance enhance mode enable */ uint8_t pe_mode_operate_code; /*!< performance enhance mode operate code */ uint8_t instruction_code; /*!< instruction code */ qspi_cmd_inslen_type instruction_length; /*!< instruction code length */ @@ -458,9 +458,23 @@ typedef struct }; /** - * @brief qspi reserved register, offset:0x40~4C + * @brief qspi ctrl3 register, offset:0x40 */ - __IO uint32_t reserved2[4]; + union + { + __IO uint32_t ctrl3; + struct + { + __IO uint32_t reserved1 : 8; /* [7:0] */ + __IO uint32_t ispc : 1; /* [8] */ + __IO uint32_t reserved2 : 23;/* [31:9] */ + } ctrl3_bit; + }; + + /** + * @brief qspi reserved register, offset:0x44~4C + */ + __IO uint32_t reserved2[3]; /** * @brief qspi rev register, offset:0x50 @@ -505,13 +519,15 @@ typedef struct * @{ */ +void qspi_reset(qspi_type* qspi_x); void qspi_encryption_enable(qspi_type* qspi_x, confirm_state new_state); -void qspi_sck_mode_set( qspi_type* qspi_x, qspi_clk_mode_type new_mode); +void qspi_sck_mode_set(qspi_type* qspi_x, qspi_clk_mode_type new_mode); void qspi_clk_division_set(qspi_type* qspi_x, qspi_clk_div_type new_clkdiv); void qspi_xip_cache_bypass_set(qspi_type* qspi_x, confirm_state new_state); void qspi_interrupt_enable(qspi_type* qspi_x, confirm_state new_state); flag_status qspi_flag_get(qspi_type* qspi_x, uint32_t flag); -void qspi_flag_clear( qspi_type* qspi_x, uint32_t flag); +flag_status qspi_interrupt_flag_get(qspi_type* qspi_x, uint32_t flag); +void qspi_flag_clear(qspi_type* qspi_x, uint32_t flag); void qspi_dma_rx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_threshold); void qspi_dma_tx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_threshold); void qspi_dma_enable(qspi_type* qspi_x, confirm_state new_state); @@ -525,6 +541,7 @@ uint32_t qspi_word_read(qspi_type* qspi_x); void qspi_word_write(qspi_type* qspi_x, uint32_t value); void qspi_half_word_write(qspi_type* qspi_x, uint16_t value); void qspi_byte_write(qspi_type* qspi_x, uint8_t value); +void qspi_auto_ispc_enable(qspi_type* qspi_x); /** * @} */ diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_scfg.h b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_scfg.h index a4e5241088..a76d70ef41 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_scfg.h +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_scfg.h @@ -55,8 +55,6 @@ extern "C" { typedef enum { SCFG_IR_SOURCE_TMR10 = 0x00, /* infrared signal source select tmr10 */ - SCFG_IR_SOURCE_USART1 = 0x01, /* infrared signal source select usart1 */ - SCFG_IR_SOURCE_USART2 = 0x02 /* infrared signal source select usart2 */ } scfg_ir_source_type; /** @@ -277,7 +275,7 @@ void scfg_infrared_config(scfg_ir_source_type source, scfg_ir_polarity_type pola scfg_mem_map_type scfg_mem_map_get(void); void scfg_i2s_full_duplex_config(scfg_i2s_type i2s_full_duplex); void scfg_pvm_lock_enable(confirm_state new_state); -error_status scfg_sram_operr_status_get(void); +flag_status scfg_sram_operr_status_get(void); void scfg_sram_operr_lock_enable(confirm_state new_state); void scfg_lockup_enable(confirm_state new_state); void scfg_exint_line_config(scfg_port_source_type port_source, scfg_pins_source_type pin_source); diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_spi.h b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_spi.h index 20a5e636fc..18bc75bd0d 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_spi.h +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_spi.h @@ -508,6 +508,7 @@ void spi_i2s_dma_receiver_enable(spi_type* spi_x, confirm_state new_state); void spi_i2s_data_transmit(spi_type* spi_x, uint16_t tx_data); uint16_t spi_i2s_data_receive(spi_type* spi_x); flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag); +flag_status spi_i2s_interrupt_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag); void spi_i2s_flag_clear(spi_type* spi_x, uint32_t spi_i2s_flag); void i2sf_full_duplex_mode_enable(spi_type* spi_x, confirm_state new_state); void i2sf_pcm_sample_clock_set(spi_type* spi_x, i2s_pcm_sample_clock_type pcm_sample_clock); diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_tmr.h b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_tmr.h index 24f03f9ee2..4f12194237 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_tmr.h +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_tmr.h @@ -444,7 +444,6 @@ typedef struct */ typedef struct { - uint8_t brk_filter_value; /*!< tmr brake filter value */ uint8_t deadtime; /*!< dead-time generator setup */ tmr_brk_polarity_type brk_polarity; /*!< tmr brake polarity */ tmr_wp_level_type wp_level; /*!< write protect configuration */ @@ -972,6 +971,7 @@ void tmr_trigger_input_select(tmr_type *tmr_x, sub_tmr_input_sel_type trigger_se void tmr_sub_sync_mode_set(tmr_type *tmr_x, confirm_state new_state); void tmr_dma_request_enable(tmr_type *tmr_x, tmr_dma_request_type dma_request, confirm_state new_state); void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state new_state); +flag_status tmr_interrupt_flag_get(tmr_type *tmr_x, uint32_t tmr_flag); flag_status tmr_flag_get(tmr_type *tmr_x, uint32_t tmr_flag); void tmr_flag_clear(tmr_type *tmr_x, uint32_t tmr_flag); void tmr_event_sw_trigger(tmr_type *tmr_x, tmr_event_trigger_type tmr_event); @@ -993,6 +993,7 @@ void tmr_force_output_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, void tmr_dma_control_config(tmr_type *tmr_x, tmr_dma_transfer_length_type dma_length, \ tmr_dma_address_type dma_base_address); void tmr_brkdt_config(tmr_type *tmr_x, tmr_brkdt_config_type *brkdt_struct); +void tmr_brk_filter_value_set(tmr_type *tmr_x, uint8_t filter_value); void tmr_iremap_config(tmr_type *tmr_x, tmr_input_remap_type input_remap); /** diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_usart.h b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_usart.h index b5a738f8b4..df2612e9bf 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_usart.h +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_usart.h @@ -184,6 +184,15 @@ typedef enum USART_ID_RELATED_DATA_BIT = 0x01 /*!< usart id bit num related data bits */ } usart_identification_bit_num_type; +/** + * @brief usart de polarity type + */ +typedef enum +{ + USART_DE_POLARITY_HIGH = 0x00, /*!< usart de polarity high */ + USART_DE_POLARITY_LOW = 0x01 /*!< usart de polarity low */ +} usart_de_polarity_type; + /** * @brief type define usart register all */ @@ -418,11 +427,12 @@ void usart_irda_mode_enable(usart_type* usart_x, confirm_state new_state); void usart_irda_low_power_enable(usart_type* usart_x, confirm_state new_state); void usart_hardware_flow_control_set(usart_type* usart_x,usart_hardware_flow_control_type flow_state); flag_status usart_flag_get(usart_type* usart_x, uint32_t flag); +flag_status usart_interrupt_flag_get(usart_type* usart_x, uint32_t flag); void usart_flag_clear(usart_type* usart_x, uint32_t flag); void usart_rs485_delay_time_config(usart_type* usart_x, uint8_t start_delay_time, uint8_t complete_delay_time); void usart_transmit_receive_pin_swap(usart_type* usart_x, confirm_state new_state); void usart_id_bit_num_set(usart_type* usart_x, usart_identification_bit_num_type id_bit_num); -void usart_de_polarity_reverse(usart_type* usart_x, confirm_state new_state); +void usart_de_polarity_set(usart_type* usart_x, usart_de_polarity_type de_polarity); void usart_rs485_mode_enable(usart_type* usart_x, confirm_state new_state); void usart_msb_transmit_first_enable(usart_type* usart_x, confirm_state new_state); void usart_dt_polarity_reverse(usart_type* usart_x, confirm_state new_state); diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_wwdt.h b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_wwdt.h index 1cecfd0a31..475ac0d8f0 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_wwdt.h +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_wwdt.h @@ -134,6 +134,7 @@ void wwdt_flag_clear(void); void wwdt_enable(uint8_t wwdt_cnt); void wwdt_interrupt_enable(void); flag_status wwdt_flag_get(void); +flag_status wwdt_interrupt_flag_get(void); void wwdt_counter_set(uint8_t wwdt_cnt); void wwdt_window_counter_set(uint8_t window_cnt); diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_acc.c b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_acc.c index b5a5e20d13..33fa7fb78a 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_acc.c +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_acc.c @@ -188,6 +188,22 @@ flag_status acc_flag_get(uint16_t acc_flag) return (flag_status)(ACC->sts_bit.rslost); } +/** + * @brief check whether the specified acc interrupt flag is set or not. + * @param acc_flag: specifies the flag to check. + * this parameter can be one of the following values: + * - ACC_RSLOST_FLAG + * - ACC_CALRDY_FLAG + * @retval flag_status (SET or RESET) + */ +flag_status acc_interrupt_flag_get(uint16_t acc_flag) +{ + if(acc_flag == ACC_CALRDY_FLAG) + return (flag_status)(ACC->sts_bit.calrdy && ACC->ctrl1_bit.calrdyien); + else + return (flag_status)(ACC->sts_bit.rslost && ACC->ctrl1_bit.eien); +} + /** * @brief clear the specified acc flag is set or not. * @param acc_flag: specifies the flag to check. diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_adc.c b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_adc.c index 1a3a9f1a72..be97d94305 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_adc.c +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_adc.c @@ -799,10 +799,10 @@ uint16_t adc_ordinary_conversion_data_get(adc_type *adc_x) * ADC1. * @param adc_preempt_channel: select the preempt channel. * this parameter can be one of the following values: - * - ADC_PREEMPTED_CHANNEL_1 - * - ADC_PREEMPTED_CHANNEL_2 - * - ADC_PREEMPTED_CHANNEL_3 - * - ADC_PREEMPTED_CHANNEL_4 + * - ADC_PREEMPT_CHANNEL_1 + * - ADC_PREEMPT_CHANNEL_2 + * - ADC_PREEMPT_CHANNEL_3 + * - ADC_PREEMPT_CHANNEL_4 * @retval the conversion data for selection preempt channel. */ uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel) @@ -857,6 +857,47 @@ flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag) return status; } +/** + * @brief get interrupt flag of the specified adc peripheral. + * @param adc_x: select the adc peripheral. + * this parameter can be one of the following values: + * ADC1. + * @param adc_flag: select the adc flag. + * this parameter can be one of the following values: + * - ADC_VMOR_FLAG + * - ADC_CCE_FLAG + * - ADC_PCCE_FLAG + * @retval the new state of adc flag status(SET or RESET). + */ +flag_status adc_interrupt_flag_get(adc_type *adc_x, uint8_t adc_flag) +{ + flag_status status = RESET; + switch(adc_flag) + { + case ADC_VMOR_FLAG: + if(adc_x->sts_bit.vmor && adc_x->ctrl1_bit.vmorien) + { + status = SET; + } + break; + case ADC_CCE_FLAG: + if(adc_x->sts_bit.cce && adc_x->ctrl1_bit.cceien) + { + status = SET; + } + break; + case ADC_PCCE_FLAG: + if(adc_x->sts_bit.pcce && adc_x->ctrl1_bit.pcceien) + { + status = SET; + } + break; + default: + break; + } + return status; +} + /** * @brief clear flag of the specified adc peripheral. * @param adc_x: select the adc peripheral. diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_can.c b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_can.c index ec3a3544b0..3de82fa09a 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_can.c +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_can.c @@ -928,6 +928,102 @@ void can_interrupt_enable(can_type* can_x, uint32_t can_int, confirm_state new_s } } +/** + * @brief get interrupt flag of the specified can peripheral. + * @param can_x: select the can peripheral. + * this parameter can be one of the following values: + * CAN1,CAN2. + * @param can_flag: select the flag. + * this parameter can be one of the following flags: + * - CAN_EAF_FLAG + * - CAN_EPF_FLAG + * - CAN_BOF_FLAG + * - CAN_ETR_FLAG + * - CAN_EOIF_FLAG + * - CAN_TM0TCF_FLAG + * - CAN_TM1TCF_FLAG + * - CAN_TM2TCF_FLAG + * - CAN_RF0MN_FLAG + * - CAN_RF0FF_FLAG + * - CAN_RF0OF_FLAG + * - CAN_RF1MN_FLAG + * - CAN_RF1FF_FLAG + * - CAN_RF1OF_FLAG + * - CAN_QDZIF_FLAG + * - CAN_EDZC_FLAG + * - CAN_TMEF_FLAG + * note:the state of CAN_EDZC_FLAG need to check dzc and edzif bit + * note:the state of CAN_TMEF_FLAG need to check rqc0,rqc1 and rqc2 bit + * @retval status of can_flag, the returned value can be:SET or RESET. + */ +flag_status can_interrupt_flag_get(can_type* can_x, uint32_t can_flag) +{ + flag_status bit_status = RESET; + flag_status int_status = RESET; + + switch(can_flag) + { + case CAN_EAF_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.eaien); + break; + case CAN_EPF_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.epien); + break; + case CAN_BOF_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.boien); + break; + case CAN_ETR_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.etrien); + break; + case CAN_EOIF_FLAG: + int_status = (flag_status)can_x->inten_bit.eoien; + break; + case CAN_TM0TCF_FLAG: + case CAN_TM1TCF_FLAG: + case CAN_TM2TCF_FLAG: + int_status = (flag_status)can_x->inten_bit.tcien; + break; + case CAN_RF0MN_FLAG: + int_status = (flag_status)can_x->inten_bit.rf0mien; + break; + case CAN_RF0FF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf0fien; + break; + case CAN_RF0OF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf0oien; + break; + case CAN_RF1MN_FLAG: + int_status = (flag_status)can_x->inten_bit.rf1mien; + break; + case CAN_RF1FF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf1fien; + break; + case CAN_RF1OF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf1oien; + break; + case CAN_QDZIF_FLAG: + int_status = (flag_status)can_x->inten_bit.qdzien; + break; + case CAN_EDZC_FLAG: + int_status = (flag_status)can_x->inten_bit.edzien; + break; + case CAN_TMEF_FLAG: + int_status = (flag_status)can_x->inten_bit.tcien; + break; + default: + int_status = RESET; + break; + } + + if(int_status != SET) + { + return RESET; + } + bit_status = can_flag_get(can_x, can_flag); + + return bit_status; +} + /** * @brief get flag of the specified can peripheral. * @param can_x: select the can peripheral. diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_crm.c b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_crm.c index 1119b212d8..e2527a4a77 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_crm.c +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_crm.c @@ -141,6 +141,64 @@ flag_status crm_flag_get(uint32_t flag) return status; } +/** + * @brief get crm interrupt flag status + * @param flag + * this parameter can be one of the following values: + * - CRM_LICK_READY_INT_FLAG + * - CRM_LEXT_READY_INT_FLAG + * - CRM_HICK_READY_INT_FLAG + * - CRM_HEXT_READY_INT_FLAG + * - CRM_PLL_READY_INT_FLAG + * - CRM_CLOCK_FAILURE_INT_FLAG + * @retval flag_status (SET or RESET) + */ +flag_status crm_interrupt_flag_get(uint32_t flag) +{ + flag_status status = RESET; + switch(flag) + { + case CRM_LICK_READY_INT_FLAG: + if(CRM->clkint_bit.lickstblf && CRM->clkint_bit.lickstblien) + { + status = SET; + } + break; + case CRM_LEXT_READY_INT_FLAG: + if(CRM->clkint_bit.lextstblf && CRM->clkint_bit.lextstblien) + { + status = SET; + } + break; + case CRM_HICK_READY_INT_FLAG: + if(CRM->clkint_bit.hickstblf && CRM->clkint_bit.hickstblien) + { + status = SET; + } + break; + case CRM_HEXT_READY_INT_FLAG: + if(CRM->clkint_bit.hextstblf && CRM->clkint_bit.hextstblien) + { + status = SET; + } + break; + case CRM_PLL_READY_INT_FLAG: + if(CRM->clkint_bit.pllstblf && CRM->clkint_bit.pllstblien) + { + status = SET; + } + break; + case CRM_CLOCK_FAILURE_INT_FLAG: + if(CRM->clkint_bit.cfdf && CRM->ctrl_bit.cfden) + { + status = SET; + } + break; + } + + return status; +} + /** * @brief wait for hext stable * @param none @@ -871,7 +929,7 @@ void crm_clocks_freq_get(crm_clocks_freq_type *clocks_struct) } /** - * @brief set crm clkout2 + * @brief set crm clkout * @param clkout * this parameter can be one of the following values: * - CRM_CLKOUT_SCLK @@ -882,7 +940,6 @@ void crm_clocks_freq_get(crm_clocks_freq_type *clocks_struct) * - CRM_CLKOUT_HICK * - CRM_CLKOUT_LICK * - CRM_CLKOUT_LEXT - * - CRM_CLKOUT_USBHS * @retval none */ void crm_clock_out_set(crm_clkout_select_type clkout) @@ -899,7 +956,7 @@ void crm_clock_out_set(crm_clkout_select_type clkout) } /** - * @brief set crm clkout1 division1 + * @brief set crm clkout division1 * @param div1 * this parameter can be one of the following values: * - CRM_CLKOUT_DIV1_1 diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_dma.c b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_dma.c index 05fb5afbce..792bd30ac2 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_dma.c +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_dma.c @@ -197,6 +197,52 @@ void dma_channel_enable(dma_channel_type *dmax_channely, confirm_state new_state dmax_channely->ctrl_bit.chen = new_state; } +/** + * @brief get dma interrupt flag + * @param dmax_flag + * this parameter can be one of the following values: + * - DMA1_FDT1_FLAG - DMA1_HDT1_FLAG - DMA1_DTERR1_FLAG + * - DMA1_FDT2_FLAG - DMA1_HDT2_FLAG - DMA1_DTERR2_FLAG + * - DMA1_FDT3_FLAG - DMA1_HDT3_FLAG - DMA1_DTERR3_FLAG + * - DMA1_FDT4_FLAG - DMA1_HDT4_FLAG - DMA1_DTERR4_FLAG + * - DMA1_FDT5_FLAG - DMA1_HDT5_FLAG - DMA1_DTERR5_FLAG + * - DMA1_FDT6_FLAG - DMA1_HDT6_FLAG - DMA1_DTERR6_FLAG + * - DMA1_FDT7_FLAG - DMA1_HDT7_FLAG - DMA1_DTERR7_FLAG + * - DMA2_FDT1_FLAG - DMA2_HDT1_FLAG - DMA2_DTERR1_FLAG + * - DMA2_FDT2_FLAG - DMA2_HDT2_FLAG - DMA2_DTERR2_FLAG + * - DMA2_FDT3_FLAG - DMA2_HDT3_FLAG - DMA2_DTERR3_FLAG + * - DMA2_FDT4_FLAG - DMA2_HDT4_FLAG - DMA2_DTERR4_FLAG + * - DMA2_FDT5_FLAG - DMA2_HDT5_FLAG - DMA2_DTERR5_FLAG + * - DMA2_FDT6_FLAG - DMA2_HDT6_FLAG - DMA2_DTERR6_FLAG + * - DMA2_FDT7_FLAG - DMA2_HDT7_FLAG - DMA2_DTERR7_FLAG + * @retval state of dma flag + */ +flag_status dma_interrupt_flag_get(uint32_t dmax_flag) +{ + flag_status status = RESET; + uint32_t temp = 0; + + if(dmax_flag > 0x10000000) + { + temp = DMA2->sts; + } + else + { + temp = DMA1->sts; + } + + if ((temp & dmax_flag) != (uint16_t)RESET) + { + status = SET; + } + else + { + status = RESET; + } + + return status; +} + /** * @brief dma flag get. * @param dma_flag @@ -599,6 +645,78 @@ flag_status dmamux_sync_flag_get(dma_type *dma_x, uint32_t flag) } } +/** + * @brief dmamux sync interrupt flag get. + * @param dma_x : pointer to a dma_type structure, can be DMA1 or DMA2. + * @param flag + * this parameter can be any combination of the following values: + * - DMAMUX_SYNC_OV1_FLAG + * - DMAMUX_SYNC_OV2_FLAG + * - DMAMUX_SYNC_OV3_FLAG + * - DMAMUX_SYNC_OV4_FLAG + * - DMAMUX_SYNC_OV5_FLAG + * - DMAMUX_SYNC_OV6_FLAG + * - DMAMUX_SYNC_OV7_FLAG + * @retval state of dmamux sync flag. + */ +flag_status dmamux_sync_interrupt_flag_get(dma_type *dma_x, uint32_t flag) +{ + + flag_status bitstatus = RESET; + uint32_t sync_int_temp = flag; + uint32_t index = 0; + uint32_t tmpreg = 0, enablestatus = 0; + uint32_t regoffset = 0x4; + + while((sync_int_temp & 0x00000001) == RESET) + { + sync_int_temp = sync_int_temp >> 1; + index++; + } + + if(dma_x == DMA1) + { + tmpreg = *(uint32_t*)(DMA1MUX_BASE + (index * regoffset)); + } + else + { + tmpreg = *(uint32_t*)(DMA2MUX_BASE + (index * regoffset)); + } + + if((tmpreg & (uint32_t)0x00000100) != (uint32_t)RESET) + { + enablestatus = SET; + } + else + { + enablestatus = RESET; + } + + if(dma_x == DMA1) + { + if(((DMA1->muxsyncsts & flag) != (uint32_t)RESET) && (enablestatus != RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if(((DMA2->muxsyncsts & flag) != (uint32_t)RESET) && (enablestatus != RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + return bitstatus; +} + /** * @brief dmamux sync flag clear. * @param dma_x : pointer to a dma_type structure, can be DMA1 or DMA2. @@ -641,6 +759,70 @@ flag_status dmamux_generator_flag_get(dma_type *dma_x, uint32_t flag) } } +/** + * @brief dmamux request generator interrupt flag get. + * @param dma_x : pointer to a dma_type structure, can be DMA1 or DMA2. + * @param flag + * this parameter can be any combination of the following values: + * - DMAMUX_GEN_TRIG_OV1_FLAG + * - DMAMUX_GEN_TRIG_OV2_FLAG + * - DMAMUX_GEN_TRIG_OV3_FLAG + * - DMAMUX_GEN_TRIG_OV4_FLAG + * @retval state of dmamux sync flag. + */ +flag_status dmamux_generator_interrupt_flag_get(dma_type *dma_x, uint32_t flag) +{ + flag_status bitstatus = RESET; + uint32_t sync_int_temp = flag; + uint32_t index = 0; + uint32_t tmpreg = 0, enablestatus = 0; + uint32_t regoffset = 0x4; + + while((sync_int_temp & 0x00000001) == RESET) + { + sync_int_temp = sync_int_temp >> 1; + index++; + } + + if(dma_x == DMA1) + tmpreg = *(uint32_t*)(DMA1MUX_GENERATOR1_BASE + (index * regoffset)); + else + tmpreg = *(uint32_t*)(DMA2MUX_GENERATOR1_BASE + (index * regoffset)); + + if((tmpreg & (uint32_t)0x00000100) != (uint32_t)RESET) + { + enablestatus = SET; + } + else + { + enablestatus = RESET; + } + if(dma_x == DMA1) + { + if(((DMA1->muxgsts & flag) != (uint32_t)RESET) && (enablestatus != RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if(((DMA2->muxgsts & flag) != (uint32_t)RESET) && (enablestatus != RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + + return bitstatus; +} + /** * @brief dmamux request generator flag clear. * @param dma_x : pointer to a dma_type structure, can be DMA1 or DMA2. diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_ertc.c b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_ertc.c index 819469cc00..2c28a48091 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_ertc.c +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_ertc.c @@ -1482,6 +1482,55 @@ flag_status ertc_flag_get(uint32_t flag) } } +/** + * @brief get interrupt flag status. + * @param flag: specifies the flag to check. + * this parameter can be one of the following values: + * - ERTC_ALAF_FLAG: alarm clock a flag. + * - ERTC_ALBF_FLAG: alarm clock b flag. + * - ERTC_WATF_FLAG: wakeup timer flag. + * - ERTC_TSF_FLAG: timestamp flag. + * - ERTC_TP1F_FLAG: tamper detection 1 flag. + * - ERTC_TP2F_FLAG: tamper detection 2 flag. + * @retval the new state of flag (SET or RESET). + */ +flag_status ertc_interrupt_flag_get(uint32_t flag) +{ + __IO uint32_t iten = 0; + + switch(flag) + { + case ERTC_ALAF_FLAG: + iten = ERTC->ctrl_bit.alaien; + break; + case ERTC_ALBF_FLAG: + iten = ERTC->ctrl_bit.albien; + break; + case ERTC_WATF_FLAG: + iten = ERTC->ctrl_bit.watien; + break; + case ERTC_TSF_FLAG: + iten = ERTC->ctrl_bit.tsien; + break; + case ERTC_TP1F_FLAG: + case ERTC_TP2F_FLAG: + iten = ERTC->tamp_bit.tpien; + break; + + default: + break; + } + + if(((ERTC->sts & flag) != (uint32_t)RESET) && (iten)) + { + return SET; + } + else + { + return RESET; + } +} + /** * @brief clear flag status * @param flag: specifies the flag to clear. diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_exint.c b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_exint.c index 35ebe36125..4f520d0e8c 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_exint.c +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_exint.c @@ -153,6 +153,36 @@ flag_status exint_flag_get(uint32_t exint_line) return status; } +/** + * @brief get exint interrupt flag + * @param exint_line + * this parameter can be one of the following values: + * - EXINT_LINE_0 + * - EXINT_LINE_1 + * ... + * - EXINT_LINE_21 + * - EXINT_LINE_22 + * @retval the new state of exint flag(SET or RESET). + */ +flag_status exint_interrupt_flag_get(uint32_t exint_line) +{ + flag_status status = RESET; + uint32_t exint_flag = 0; + exint_flag = EXINT->intsts & exint_line; + exint_flag = exint_flag & EXINT->inten; + + if((exint_flag != (uint16_t)RESET)) + { + status = SET; + } + else + { + status = RESET; + } + return status; +} + + /** * @brief generate exint software interrupt event * @param exint_line diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_flash.c b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_flash.c index bf8bc31884..b6d4262ff6 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_flash.c +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_flash.c @@ -536,7 +536,7 @@ flag_status flash_fap_high_level_status_get(void) } /** - * @brief program the flash system setting byte in usd: wdt_ato_en / depslp_rst / stdby_rst / boot1 / depslp_wdt / stdby_wdt. + * @brief program the flash system setting byte in usd: wdt_ato_en / depslp_rst / stdby_rst / boot1 / depslp_wdt / stdby_wdt / ram_prt_chk. * @param usd_ssb: the system setting byte * @note this parameter usd_ssb must contain a combination of all the following 6 types of data * type 1: wdt_ato_en, select the wdt auto start @@ -563,6 +563,10 @@ flag_status flash_fap_high_level_status_get(void) * this data can be one of the following values: * - USD_STDBY_WDT_CONTINUE: wdt continue count when entering in standby * - USD_STDBY_WDT_STOP: wdt stop count when entering in standby + * type 7: ram_prt_chk, ram parity check disable or enable. + * this data can be one of the following values: + * - USD_RAM_PRT_CHK_DISABLE: ram parity check disabled + * - USD_RAM_PRT_CHK_ENABLE: ram parity check enabled * @retval status: the returned value can be: FLASH_PROGRAM_ERROR, * FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT. */ @@ -593,7 +597,7 @@ flash_status_type flash_ssb_set(uint8_t usd_ssb) * @brief return the flash system setting byte status. * @param none * @retval values from flash_usd register: wdt_ato_en(bit0), depslp_rst(bit1), - * stdby_rst(bit2), boot1(bit4), depslp_wdt(bit5) and stdby_wdt(bit6). + * stdby_rst(bit2), boot1(bit4), depslp_wdt(bit5), stdby_wdt(bit6) and ram_prt_chk(bit7). */ uint8_t flash_ssb_status_get(void) { diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_i2c.c b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_i2c.c index 38cb5eb7d1..a446678985 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_i2c.c +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_i2c.c @@ -120,12 +120,12 @@ void i2c_own_address1_set(i2c_type *i2c_x, i2c_address_mode_type mode, uint16_t * this parameter can be one of the following values: * - I2C_ADDR2_NOMASK: compare bit [7:1]. * - I2C_ADDR2_MASK01: only compare bit [7:2]. - * - I2C_ADDR2_MASK02: only compare bit [7:2]. - * - I2C_ADDR2_MASK03: only compare bit [7:3]. - * - I2C_ADDR2_MASK04: only compare bit [7:4]. - * - I2C_ADDR2_MASK05: only compare bit [7:5]. - * - I2C_ADDR2_MASK06: only compare bit [7:6]. - * - I2C_ADDR2_MASK07: only compare bit [7]. + * - I2C_ADDR2_MASK02: only compare bit [7:3]. + * - I2C_ADDR2_MASK03: only compare bit [7:4]. + * - I2C_ADDR2_MASK04: only compare bit [7:5]. + * - I2C_ADDR2_MASK05: only compare bit [7:6]. + * - I2C_ADDR2_MASK06: only compare bit [7]. + * - I2C_ADDR2_MASK07: response all addresses other than those reserved for i2c. * @retval none */ void i2c_own_address2_set(i2c_type *i2c_x, uint8_t address, i2c_addr2_mask_type mask) @@ -706,6 +706,77 @@ flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag) } } +/** + * @brief get interrupt flag status. + * @param i2c_x: to select the i2c peripheral. + * this parameter can be one of the following values: + * I2C1, I2C2, I2C3. + * @param flag: specifies the flag to check. + * this parameter can be one of the following values: + * - I2C_TDBE_FLAG: transmit data buffer empty flag. + * - I2C_TDIS_FLAG: send interrupt status. + * - I2C_RDBF_FLAG: receive data buffer full flag. + * - I2C_ADDRF_FLAG: 0~7 bit address match flag. + * - I2C_ACKFAIL_FLAG: acknowledge failure flag. + * - I2C_STOPF_FLAG: stop condition generation complete flag. + * - I2C_TDC_FLAG: transmit data complete flag. + * - I2C_TCRLD_FLAG: transmission is complete, waiting to load data. + * - I2C_BUSERR_FLAG: bus error flag. + * - I2C_ARLOST_FLAG: arbitration lost flag. + * - I2C_OUF_FLAG: overflow or underflow flag. + * - I2C_PECERR_FLAG: pec receive error flag. + * - I2C_TMOUT_FLAG: smbus timeout flag. + * - I2C_ALERTF_FLAG: smbus alert flag. + * @retval the new state of flag (SET or RESET). + */ +flag_status i2c_interrupt_flag_get(i2c_type *i2c_x, uint32_t flag) +{ + __IO uint32_t iten = 0; + + switch(flag) + { + case I2C_TDIS_FLAG: + iten = i2c_x->ctrl1_bit.tdien; + break; + case I2C_RDBF_FLAG: + iten = i2c_x->ctrl1_bit.rdien; + break; + case I2C_ADDRF_FLAG: + iten = i2c_x->ctrl1_bit.addrien; + break; + case I2C_ACKFAIL_FLAG: + iten = i2c_x->ctrl1_bit.ackfailien; + break; + case I2C_STOPF_FLAG: + iten = i2c_x->ctrl1_bit.stopien; + break; + case I2C_TDC_FLAG: + case I2C_TCRLD_FLAG: + iten = i2c_x->ctrl1_bit.tdcien; + break; + case I2C_BUSERR_FLAG: + case I2C_ARLOST_FLAG: + case I2C_OUF_FLAG: + case I2C_PECERR_FLAG: + case I2C_TMOUT_FLAG: + case I2C_ALERTF_FLAG: + iten = i2c_x->ctrl1_bit.errien; + break; + + default: + break; + } + + if(((i2c_x->sts & flag) != RESET) && (iten)) + { + return SET; + } + else + { + return RESET; + } +} + /** * @brief clear flag status * @param i2c_x: to select the i2c peripheral. diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_pwc.c b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_pwc.c index e9426f4266..91244e188a 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_pwc.c +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_pwc.c @@ -207,7 +207,6 @@ void pwc_deep_sleep_mode_enter(pwc_deep_sleep_enter_type pwc_deep_sleep_enter) * @param pwc_regulator: set the regulator state. * this parameter can be one of the following values: * - PWC_REGULATOR_ON - * - PWC_REGULATOR_LOW_POWER * - PWC_REGULATOR_EXTRA_LOW_POWER * @retval none */ @@ -215,15 +214,11 @@ void pwc_voltage_regulate_set(pwc_regulator_type pwc_regulator) { switch(pwc_regulator) { - case 0: + case PWC_REGULATOR_ON: PWC->ldoov_bit.vrexlpen = 0; PWC->ctrl_bit.vrsel = 0; break; - case 1: - PWC->ldoov_bit.vrexlpen = 0; - PWC->ctrl_bit.vrsel = 1; - break; - case 2: + case PWC_REGULATOR_EXTRA_LOW_POWER: PWC->ldoov_bit.vrexlpen = 1; PWC->ctrl_bit.vrsel = 1; break; @@ -242,7 +237,7 @@ void pwc_standby_mode_enter(void) PWC->ctrl_bit.clswef = TRUE; PWC->ctrl_bit.lpsel = TRUE; SCB->SCR |= 0x04; -#if defined (__CC_ARM) +#if defined (__ARMCC_VERSION) __force_stores(); #endif while(1) diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_qspi.c b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_qspi.c index 8137509255..fb5d13b94c 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_qspi.c +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_qspi.c @@ -39,6 +39,21 @@ * @{ */ +/** + * @brief deinitialize the qspi peripheral registers to their default reset values. + * @param qspi_x: select the qspi peripheral. + * this parameter can be one of the following values: + * QSPI1. + * @retval none + */ +void qspi_reset(qspi_type* qspi_x) +{ + { + crm_periph_reset(CRM_QSPI1_PERIPH_RESET, TRUE); + crm_periph_reset(CRM_QSPI1_PERIPH_RESET, FALSE); + } +} + /** * @brief enable/disable encryption for qspi. * @note the function must be configured only when qspi in command-port mode!!! @@ -131,7 +146,7 @@ void qspi_interrupt_enable(qspi_type* qspi_x, confirm_state new_state) * - QSPI_RXFIFORDY_FLAG * - QSPI_TXFIFORDY_FLAG * - QSPI_CMDSTS_FLAG - * @retval the new state of usart_flag (SET or RESET). + * @retval the new state of the flag (SET or RESET). */ flag_status qspi_flag_get(qspi_type* qspi_x, uint32_t flag) { @@ -153,6 +168,24 @@ flag_status qspi_flag_get(qspi_type* qspi_x, uint32_t flag) return bit_status; } +/** + * @brief get interrupt flags. + * @param qspi_x: select the qspi peripheral. + * this parameter can be one of the following values: + * QSPI1. + * @param flag: only QSPI_CMDSTS_FLAG valid. + * @retval the new state of the flag (SET or RESET). + */ +flag_status qspi_interrupt_flag_get(qspi_type* qspi_x, uint32_t flag) +{ + if(QSPI_CMDSTS_FLAG != flag) + return RESET; + if(qspi_x->cmdsts_bit.cmdsts && qspi_x->ctrl2_bit.cmdie) + return SET; + else + return RESET; +} + /** * @brief clear flags * @param qspi_x: select the qspi peripheral. @@ -163,7 +196,7 @@ flag_status qspi_flag_get(qspi_type* qspi_x, uint32_t flag) * - QSPI_CMDSTS_FLAG * @retval none */ -void qspi_flag_clear( qspi_type* qspi_x, uint32_t flag) +void qspi_flag_clear(qspi_type* qspi_x, uint32_t flag) { qspi_x->cmdsts = QSPI_CMDSTS_FLAG; } @@ -178,7 +211,7 @@ void qspi_flag_clear( qspi_type* qspi_x, uint32_t flag) * this parameter can be one of the following values: * - QSPI_DMA_FIFO_THOD_WORD08 * - QSPI_DMA_FIFO_THOD_WORD16 - * - QSPI_DMA_FIFO_THOD_WORD32 + * - QSPI_DMA_FIFO_THOD_WORD24 * @retval none */ void qspi_dma_rx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_threshold) @@ -196,7 +229,7 @@ void qspi_dma_rx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_th * this parameter can be one of the following values: * - QSPI_DMA_FIFO_THOD_WORD08 * - QSPI_DMA_FIFO_THOD_WORD16 - * - QSPI_DMA_FIFO_THOD_WORD32 + * - QSPI_DMA_FIFO_THOD_WORD24 * @retval none */ void qspi_dma_tx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_threshold) @@ -267,6 +300,7 @@ void qspi_xip_enable(qspi_type* qspi_x, confirm_state new_state) { __NOP(); } + /* flush and reset qspi state */ qspi_x->ctrl_bit.xiprcmdf = 1; @@ -425,6 +459,16 @@ void qspi_word_write(qspi_type* qspi_x, uint32_t value) qspi_x->dt = value; } +/** + * @brief enable auto input sampling phase correction + * @param qspi_x: select the qspi peripheral. + * @retval none. + */ +void qspi_auto_ispc_enable(qspi_type* qspi_x) +{ + qspi_x->ctrl3_bit.ispc = TRUE; +} + /** * @} */ diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_scfg.c b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_scfg.c index f01220b024..7ecdceccda 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_scfg.c +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_scfg.c @@ -55,8 +55,6 @@ void scfg_reset(void) * @param source * this parameter can be one of the following values: * - SCFG_IR_SOURCE_TMR10 - * - SCFG_IR_SOURCE_USART1 - * - SCFG_IR_SOURCE_USART2 * @param polarity * this parameter can be one of the following values: * - SCFG_IR_POLARITY_NO_AFFECTE @@ -116,18 +114,11 @@ void scfg_pvm_lock_enable(confirm_state new_state) /** * @brief scfg sram odd parity error status get * @param none - * @retval return sram odd parity error status (ERROR or SUCCESS) + * @retval return sram odd parity error status(SET or RESET) */ -error_status scfg_sram_operr_status_get(void) +flag_status scfg_sram_operr_status_get(void) { - error_status status = SUCCESS; - - if(SCFG->cfg2_bit.sram_operr_sts) - status = ERROR; - else - status = SUCCESS; - - return status ; + return (flag_status)SCFG->cfg2_bit.sram_operr_sts; } /** diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_spi.c b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_spi.c index 38268bf433..5f161f4b03 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_spi.c +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_spi.c @@ -674,6 +674,76 @@ flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag) return status; } +/** + * @brief get interrupt flag of the specified spi/i2s peripheral. + * @param spi_x: select the spi/i2s peripheral. + * this parameter can be one of the following values: + * SPI1, SPI2, SPI3, I2SF5 + * @param spi_i2s_flag: select the spi/i2s flag + * this parameter can be one of the following values: + * - SPI_I2S_RDBF_FLAG + * - SPI_I2S_TDBE_FLAG + * - I2S_TUERR_FLAG (this flag only use in i2s mode) + * - SPI_CCERR_FLAG (this flag only use in spi mode) + * - SPI_MMERR_FLAG (this flag only use in spi mode) + * - SPI_I2S_ROERR_FLAG + * - SPI_I2S_CSPAS_FLAG + * @retval the new state of spi/i2s flag + */ +flag_status spi_i2s_interrupt_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag) +{ + flag_status status = RESET; + + switch(spi_i2s_flag) + { + case SPI_I2S_RDBF_FLAG: + if(spi_x->sts_bit.rdbf && spi_x->ctrl2_bit.rdbfie) + { + status = SET; + } + break; + case SPI_I2S_TDBE_FLAG: + if(spi_x->sts_bit.tdbe && spi_x->ctrl2_bit.tdbeie) + { + status = SET; + } + break; + case I2S_TUERR_FLAG: + if(spi_x->sts_bit.tuerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_CCERR_FLAG: + if(spi_x->sts_bit.ccerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_MMERR_FLAG: + if(spi_x->sts_bit.mmerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_I2S_ROERR_FLAG: + if(spi_x->sts_bit.roerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_I2S_CSPAS_FLAG: + if(spi_x->sts_bit.cspas && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + default: + break; + }; + return status; +} + /** * @brief clear flag of the specified spi/i2s peripheral. * @param spi_x: select the spi/i2s peripheral. diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_tmr.c b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_tmr.c index 9335182f68..084ee6c602 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_tmr.c +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_tmr.c @@ -160,7 +160,6 @@ void tmr_input_default_para_init(tmr_input_config_type *tmr_input_struct) */ void tmr_brkdt_default_para_init(tmr_brkdt_config_type *tmr_brkdt_struct) { - tmr_brkdt_struct->brk_filter_value = 0x0; tmr_brkdt_struct->deadtime = 0x0; tmr_brkdt_struct->brk_polarity = TMR_BRK_INPUT_ACTIVE_LOW; tmr_brkdt_struct->wp_level = TMR_WP_OFF; @@ -1346,6 +1345,40 @@ void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state } } +/** + * @brief get tmr interrupt flag + * @param tmr_x: select the tmr peripheral. + * this parameter can be one of the following values: + * TMR1, TMR2, TMR3, TMR4, TMR6, TMR7, TMR9, TMR10, + * TMR11, TMR13, TMR14 + * @param tmr_flag + * this parameter can be one of the following values: + * - TMR_OVF_FLAG + * - TMR_C1_FLAG + * - TMR_C2_FLAG + * - TMR_C3_FLAG + * - TMR_C4_FLAG + * - TMR_HALL_FLAG + * - TMR_TRIGGER_FLAG + * - TMR_BRK_FLAG + * @retval state of tmr interrupt flag + */ +flag_status tmr_interrupt_flag_get(tmr_type *tmr_x, uint32_t tmr_flag) +{ + flag_status status = RESET; + + if((tmr_x->ists & tmr_flag) && (tmr_x->iden & tmr_flag)) + { + status = SET; + } + else + { + status = RESET; + } + + return status; +} + /** * @brief get tmr flag * @param tmr_x: select the tmr peripheral. @@ -1766,7 +1799,6 @@ void tmr_dma_control_config(tmr_type *tmr_x, tmr_dma_transfer_length_type dma_le */ void tmr_brkdt_config(tmr_type *tmr_x, tmr_brkdt_config_type *brkdt_struct) { - tmr_x->brk_bit.bkf = brkdt_struct->brk_filter_value; tmr_x->brk_bit.brken = brkdt_struct->brk_enable; tmr_x->brk_bit.dtc = brkdt_struct->deadtime; tmr_x->brk_bit.fcsodis = brkdt_struct->fcsodis_state; @@ -1776,6 +1808,19 @@ void tmr_brkdt_config(tmr_type *tmr_x, tmr_brkdt_config_type *brkdt_struct) tmr_x->brk_bit.wpc = brkdt_struct->wp_level; } +/** + * @brief set tmr break input filter value + * @param tmr_x: select the tmr peripheral. + * this parameter can be one of the following values: + * TMR1, TMR9, TMR10, TMR11, TMR13, TRM14 + * @param filter_value (0x0~0xf) + * @retval none + */ +void tmr_brk_filter_value_set(tmr_type *tmr_x, uint8_t filter_value) +{ + tmr_x->brk_bit.bkf = filter_value; +} + /** * @brief set tmr2 and tmr14 input channel remap * @param tmr_x: select the tmr peripheral. diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_usart.c b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_usart.c index 0b9c450f13..e2291d1ada 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_usart.c +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_usart.c @@ -607,6 +607,88 @@ flag_status usart_flag_get(usart_type* usart_x, uint32_t flag) } } +/** + * @brief check whether the specified usart interrupt flag is set or not. + * @param usart_x: select the usart or the uart peripheral. + * this parameter can be one of the following values: + * USART1, USART2, USART3, USART4, USART5, USART6, UART7 or UART8. + * @param flag: specifies the flag to check. + * this parameter can be one of the following values: + * - USART_RTODF_FLAG: receiver time out detection flag + * - USART_CMDF_FLAG: character match detection flag + * - USART_CTSCF_FLAG: cts change flag + * - USART_BFF_FLAG: break frame flag + * - USART_TDBE_FLAG: transmit data buffer empty flag + * - USART_TDC_FLAG: transmit data complete flag + * - USART_RDBF_FLAG: receive data buffer full flag + * - USART_IDLEF_FLAG: idle flag + * - USART_ROERR_FLAG: receiver overflow error flag + * - USART_NERR_FLAG: noise error flag + * - USART_FERR_FLAG: framing error flag + * - USART_PERR_FLAG: parity error flag + * @retval the new state of usart_flag (SET or RESET). + */ +flag_status usart_interrupt_flag_get(usart_type* usart_x, uint32_t flag) +{ + flag_status int_status = RESET; + + switch(flag) + { + case USART_CTSCF_FLAG: + int_status = (flag_status)usart_x->ctrl3_bit.ctscfien; + break; + case USART_BFF_FLAG: + int_status = (flag_status)usart_x->ctrl2_bit.bfien; + break; + case USART_TDBE_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.tdbeien; + break; + case USART_TDC_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.tdcien; + break; + case USART_RDBF_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.rdbfien; + break; + case USART_ROERR_FLAG: + int_status = (flag_status)(usart_x->ctrl1_bit.rdbfien || usart_x->ctrl3_bit.errien); + break; + case USART_IDLEF_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.idleien; + break; + case USART_NERR_FLAG: + case USART_FERR_FLAG: + int_status = (flag_status)usart_x->ctrl3_bit.errien; + break; + case USART_PERR_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.perrien; + break; + case USART_RTODF_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.retodie; + break; + case USART_CMDF_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.cmdie; + break; + default: + int_status = RESET; + break; + } + + if(int_status != SET) + { + return RESET; + } + + if(usart_x->sts & flag) + { + return SET; + } + else + { + return RESET; + } +} + + /** * @brief clear the usart's pending flags. * @param usart_x: select the usart or the uart peripheral. @@ -700,17 +782,17 @@ void usart_id_bit_num_set(usart_type* usart_x, usart_identification_bit_num_type } /** - * @brief enable or disable the usart's de polarity reverse. + * @brief set the usart's de polarity. * @param usart_x: select the usart or the uart peripheral. * this parameter can be one of the following values: * USART1, USART2, USART3 - * @param new_state: new state of the irda mode. - * this parameter can be: TRUE or FALSE. + * @param de_polarity: the usart de polarity selection. + * this parameter can be: USART_DE_POLARITY_HIGH or USART_DE_POLARITY_LOW. * @retval none */ -void usart_de_polarity_reverse(usart_type* usart_x, confirm_state new_state) +void usart_de_polarity_set(usart_type* usart_x, usart_de_polarity_type de_polarity) { - usart_x->ctrl3_bit.dep = new_state; + usart_x->ctrl3_bit.dep = (uint8_t)de_polarity; } /** diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_usb.c b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_usb.c index 1cc0c5d94d..49f796aaba 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_usb.c +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_usb.c @@ -1063,7 +1063,6 @@ void usb_hch_halt(otg_global_type *usbx, uint8_t chn) { usb_chh->hcchar_bit.chena = TRUE; } - } else { diff --git a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_wwdt.c b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_wwdt.c index 3a6ffcc49a..1e6bd9f35f 100644 --- a/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_wwdt.c +++ b/bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_wwdt.c @@ -104,6 +104,16 @@ flag_status wwdt_flag_get(void) return (flag_status)WWDT->sts_bit.rldf; } +/** + * @brief wwdt reload counter interrupt flag get + * @param none + * @retval state of reload counter interrupt flag + */ +flag_status wwdt_interrupt_flag_get(void) +{ + return (flag_status)(WWDT->sts_bit.rldf && WWDT->cfg_bit.rldien); +} + /** * @brief wwdt counter value set * @param wwdt_cnt (0x40~0x7f) diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/system_at32f403a_407.c b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/system_at32f403a_407.c index 1fea754ae4..e88ae74efd 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/system_at32f403a_407.c +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/system_at32f403a_407.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file system_at32f403a_407.c - * @version v2.0.9 - * @date 2022-04-25 * @brief contains all the functions for cmsis cortex-m4 system source file ************************************************************************** * Copyright notice & Disclaimer @@ -81,13 +79,13 @@ void SystemInit (void) /* wait sclk switch status */ while(CRM->cfg_bit.sclksts != CRM_SCLK_HICK); + /* reset hexten, hextbyps, cfden and pllen bits */ + CRM->ctrl &= ~(0x010D0000U); + /* reset cfg register, include sclk switch, ahbdiv, apb1div, apb2div, adcdiv, clkout pllrcs, pllhextdiv, pllmult, usbdiv and pllrange bits */ CRM->cfg = 0; - /* reset hexten, hextbyps, cfden and pllen bits */ - CRM->ctrl &= ~(0x010D0000U); - /* reset clkout[3], usbbufs, hickdiv, clkoutdiv */ CRM->misc1 = 0; diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/system_at32f403a_407.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/system_at32f403a_407.h index dd23713450..522de08919 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/system_at32f403a_407.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/system_at32f403a_407.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file system_at32f403a_407.h - * @version v2.0.9 - * @date 2022-04-25 * @brief cmsis cortex-m4 system header file. ************************************************************************** * Copyright notice & Disclaimer @@ -45,6 +43,11 @@ extern "C" { #define HEXT_STABLE_DELAY (5000u) #define PLL_STABLE_DELAY (500u) +#define SystemCoreClock system_core_clock +#define DUMMY_NOP() {__NOP();__NOP();__NOP();__NOP();__NOP(); \ + __NOP();__NOP();__NOP();__NOP();__NOP(); \ + __NOP();__NOP();__NOP();__NOP();__NOP(); \ + __NOP();__NOP();__NOP();__NOP();__NOP();} /** * @} diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_acc.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_acc.h index 5415a248b3..2955fd4706 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_acc.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_acc.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_acc.h - * @version v2.0.9 - * @date 2022-04-25 * @brief at32f403a_407 acc header file ************************************************************************** * Copyright notice & Disclaimer @@ -181,6 +179,7 @@ uint16_t acc_read_c1(void); uint16_t acc_read_c2(void); uint16_t acc_read_c3(void); flag_status acc_flag_get(uint16_t acc_flag); +flag_status acc_interrupt_flag_get(uint16_t acc_flag); void acc_flag_clear(uint16_t acc_flag); /** diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_adc.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_adc.h index cb072971f5..74c7a4f33c 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_adc.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_adc.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_adc.h - * @version v2.0.9 - * @date 2022-04-25 * @brief at32f403a_407 adc header file ************************************************************************** * Copyright notice & Disclaimer @@ -621,6 +619,7 @@ uint16_t adc_ordinary_conversion_data_get(adc_type *adc_x); uint32_t adc_combine_ordinary_conversion_data_get(void); uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel); flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag); +flag_status adc_interrupt_flag_get(adc_type *adc_x, uint8_t adc_flag); void adc_flag_clear(adc_type *adc_x, uint32_t adc_flag); /** diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_bpr.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_bpr.h index 03235e1068..08e15e3037 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_bpr.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_bpr.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_bpr.h - * @version v2.0.9 - * @date 2022-04-25 * @brief at32f403a_407 bpr header file ************************************************************************** * Copyright notice & Disclaimer @@ -761,6 +759,7 @@ typedef struct void bpr_reset(void); flag_status bpr_flag_get(uint32_t flag); +flag_status bpr_interrupt_flag_get(uint32_t flag); void bpr_flag_clear(uint32_t flag); void bpr_interrupt_enable(confirm_state new_state); uint16_t bpr_data_read(bpr_data_type bpr_data); diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_can.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_can.h index 247dfff393..b7d45564ac 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_can.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_can.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_can.h - * @version v2.0.9 - * @date 2022-04-25 * @brief at32f403a_407 can header file ************************************************************************** * Copyright notice & Disclaimer @@ -352,7 +350,7 @@ typedef struct */ typedef struct { - uint16_t baudrate_div; /*!< baudrate division,this parameter can be 0x001~0x400.*/ + uint16_t baudrate_div; /*!< baudrate division,this parameter can be 0x001~0x1000.*/ can_rsaw_type rsaw_size; /*!< resynchronization adjust width */ @@ -964,6 +962,7 @@ can_error_record_type can_error_type_record_get(can_type* can_x); uint8_t can_receive_error_counter_get(can_type* can_x); uint8_t can_transmit_error_counter_get(can_type* can_x); void can_interrupt_enable(can_type* can_x, uint32_t can_int, confirm_state new_state); +flag_status can_interrupt_flag_get(can_type* can_x, uint32_t can_flag); flag_status can_flag_get(can_type* can_x, uint32_t can_flag); void can_flag_clear(can_type* can_x, uint32_t can_flag); diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_crc.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_crc.h index 99a81578f9..30a8cbf8b6 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_crc.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_crc.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_crc.h - * @version v2.0.9 - * @date 2022-04-25 * @brief at32f403a_407 crc header file ************************************************************************** * Copyright notice & Disclaimer @@ -68,6 +66,17 @@ typedef enum CRC_REVERSE_OUTPUT_DATA = 0x01 /*!< output data reverse by word */ } crc_reverse_output_type; +/** + * @brief crc polynomial size + */ +typedef enum +{ + CRC_POLY_SIZE_32B = 0x00, /*!< polynomial size 32 bits */ + CRC_POLY_SIZE_16B = 0x01, /*!< polynomial size 16 bits */ + CRC_POLY_SIZE_8B = 0x02, /*!< polynomial size 8 bits */ + CRC_POLY_SIZE_7B = 0x03 /*!< polynomial size 7 bits */ +} crc_poly_size_type; + /** * @brief type define crc register all */ @@ -107,7 +116,8 @@ typedef struct struct { __IO uint32_t rst : 1 ; /* [0] */ - __IO uint32_t reserved1 : 4 ; /* [4:1] */ + __IO uint32_t reserved1 : 2 ; /* [2:1] */ + __IO uint32_t poly_size : 2 ; /* [4:3] */ __IO uint32_t revid : 2 ; /* [6:5] */ __IO uint32_t revod : 1 ; /* [7] */ __IO uint32_t reserved2 : 24 ;/* [31:8] */ @@ -131,6 +141,18 @@ typedef struct } idt_bit; }; + /** + * @brief crc polynomial register, offset:0x14 + */ + union + { + __IO uint32_t poly; + struct + { + __IO uint32_t poly : 32; /* [31:0] */ + } poly_bit; + }; + } crc_type; /** @@ -148,10 +170,14 @@ uint32_t crc_one_word_calculate(uint32_t data); uint32_t crc_block_calculate(uint32_t *pbuffer, uint32_t length); uint32_t crc_data_get(void); void crc_common_data_set(uint8_t cdt_value); -uint8_t crc_common_date_get(void); +uint8_t crc_common_data_get(void); void crc_init_data_set(uint32_t value); void crc_reverse_input_data_set(crc_reverse_input_type value); void crc_reverse_output_data_set(crc_reverse_output_type value); +void crc_poly_value_set(uint32_t value); +uint32_t crc_poly_value_get(void); +void crc_poly_size_set(crc_poly_size_type size); +crc_poly_size_type crc_poly_size_get(void); /** * @} diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_crm.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_crm.h index eaaa59e9b5..a3986aaf3d 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_crm.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_crm.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_crm.h - * @version v2.0.9 - * @date 2022-04-25 * @brief at32f403a_407 crm header file ************************************************************************** * Copyright notice & Disclaimer @@ -1088,6 +1086,7 @@ void crm_reset(void); void crm_lext_bypass(confirm_state new_state); void crm_hext_bypass(confirm_state new_state); flag_status crm_flag_get(uint32_t flag); +flag_status crm_interrupt_flag_get(uint32_t flag); error_status crm_hext_stable_wait(void); void crm_hick_clock_trimming_set(uint8_t trim_value); void crm_hick_clock_calibration_set(uint8_t cali_value); diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_dac.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_dac.h index 6b80067615..94e6051a8c 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_dac.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_dac.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_dac.h - * @version v2.0.9 - * @date 2022-04-25 * @brief at32f403a_407 dac header file ************************************************************************** * Copyright notice & Disclaimer diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_debug.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_debug.h index 7de5a36f5a..86a8d3bbf2 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_debug.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_debug.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_debug.h - * @version v2.0.9 - * @date 2022-04-25 * @brief at32f403a_407 debug header file ************************************************************************** * Copyright notice & Disclaimer diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_def.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_def.h index f54003a42d..a3ec690148 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_def.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_def.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_def.h - * @version v2.0.9 - * @date 2022-04-25 * @brief at32f403a_407 macros header file ************************************************************************** * Copyright notice & Disclaimer @@ -62,6 +60,8 @@ extern "C" { #endif #endif +#define UNUSED(x) (void)x /* to avoid gcc/g++ warnings */ + #ifdef __cplusplus } #endif diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_dma.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_dma.h index 7f755bb3ae..79e3a7c54e 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_dma.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_dma.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_dma.h - * @version v2.0.9 - * @date 2022-04-25 * @brief at32f403a_407 dma header file ************************************************************************** * Copyright notice & Disclaimer @@ -527,6 +525,7 @@ void dma_interrupt_enable(dma_channel_type* dmax_channely, uint32_t dma_int, con void dma_channel_enable(dma_channel_type* dmax_channely, confirm_state new_state); void dma_flexible_config(dma_type* dma_x, uint8_t flex_channelx, dma_flexible_request_type flexible_request); flag_status dma_flag_get(uint32_t dmax_flag); +flag_status dma_interrupt_flag_get(uint32_t dmax_flag); void dma_flag_clear(uint32_t dmax_flag); void dma_default_para_init(dma_init_type* dma_init_struct); void dma_init(dma_channel_type* dmax_channely, dma_init_type* dma_init_struct); diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_emac.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_emac.h index 7fb82a44ed..6de123086c 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_emac.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_emac.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_emac.h - * @version v2.0.9 - * @date 2022-04-25 * @brief at32f403a_407 emac header file ************************************************************************** * Copyright notice & Disclaimer @@ -46,6 +44,7 @@ extern "C" { */ #define PHY_TIMEOUT (0x000FFFFF) /*!< timeout for phy response */ +#define EMAC_USE_ENHANCED_DMA_DESCRIPTOR /** @defgroup EMAC_smi_clock_border_definition * @brief emac smi clock border @@ -99,7 +98,7 @@ extern "C" { * @{ */ -#define EMAC_MAX_PACKET_LENGTH 1520 /*!< emac_header + emac_extra + emac_max_payload + emac_crc */ +#define EMAC_MAX_PACKET_LENGTH 1524 /*!< emac_header + emac_extra + emac_max_payload + emac_crc */ #define EMAC_HEADER 14 /*!< 6 byte dest addr, 6 byte src addr, 2 byte length/ept_type */ #define EMAC_CRC 4 /*!< ethernet crc */ #define EMAC_EXTRA 2 /*!< extra bytes in some cases */ @@ -271,6 +270,15 @@ extern "C" { #define EMAC_DMA_AIS_FLAG ((uint32_t)0x00008000) /*!< emac dma abnormal interrupt summary */ #define EMAC_DMA_NIS_FLAG ((uint32_t)0x00010000) /*!< emac dma normal interrupt summary */ +/** + * @brief emac ptp time sign + */ +#define EMAC_PTP_POSITIVETIME ((uint32_t)0x00000000) /*!< Positive time value */ +#define EMAC_PTP_NEGATIVETIME ((uint32_t)0x80000000) /*!< Negative time value */ + +#define EMAC_PTP_TI_FLAG ((uint32_t)0x00000004) /*!< Time Stamp Initialized */ +#define EMAC_PTP_TU_FLAG ((uint32_t)0x00000008) /*!< Time Stamp Updated */ +#define EMAC_PTP_ARU_FLAG ((uint32_t)0x00000020) /*!< Addend Register Updated */ /** @defgroup EMAC_exported_types * @{ */ @@ -345,9 +353,10 @@ typedef enum */ typedef enum { - EMAC_CONTROL_FRAME_PASSING_NO = 0x00, /*!< don't pass any control frame to application */ - EMAC_CONTROL_FRAME_PASSING_ALL = 0x02, /*!< pass all control frames to application */ - EMAC_CONTROL_FRAME_PASSING_MATCH = 0x03 /*!< only pass filtered control frames to application */ + EMAC_CONTROL_FRAME_PASSING_NO = 0x00, /*!< don't pass any control frame to application */ + EMAC_CONTROL_FRAME_PASSING_ALL_EXCEPT_PAUSE = 0x01, /*!< pass all control frames to application except pause frame */ + EMAC_CONTROL_FRAME_PASSING_ALL = 0x02, /*!< pass all control frames to application */ + EMAC_CONTROL_FRAME_PASSING_MATCH = 0x03 /*!< only pass filtered control frames to application */ } emac_control_frames_filter_type; /** @@ -633,6 +642,10 @@ typedef struct { uint32_t controlsize; /*!< control and buffer1, buffer2 lengths */ uint32_t buf1addr; /*!< buffer1 address pointer */ uint32_t buf2nextdescaddr; /*!< buffer2 or next descriptor address pointer */ + uint32_t extendedstatus; + uint32_t reserved1; + uint32_t timestamp_l; + uint32_t timestamp_h; } emac_dma_desc_type; /** @@ -891,7 +904,7 @@ typedef struct __IO uint32_t reserved1 : 8; /* [16:23] */ __IO uint32_t mbc : 6; /* [24:29] */ __IO uint32_t sa : 1; /* [30] */ - __IO uint32_t ae : 1; /* [31] */ + __IO uint32_t ae : 1; /* [31] */ } a1h_bit; }; @@ -1328,7 +1341,7 @@ typedef struct __IO uint32_t swr : 1; /* [0] */ __IO uint32_t da : 1; /* [1] */ __IO uint32_t dsl : 5; /* [2:6] */ - __IO uint32_t reserved1 : 1; /* [7] */ + __IO uint32_t atds : 1; /* [7] */ __IO uint32_t pbl : 6; /* [8:13] */ __IO uint32_t pr : 2; /* [14:15] */ __IO uint32_t fb : 1; /* [16] */ @@ -1336,7 +1349,7 @@ typedef struct __IO uint32_t usp : 1; /* [23] */ __IO uint32_t pblx8 : 1; /* [24] */ __IO uint32_t aab : 1; /* [25] */ - __IO uint32_t reserved2 : 6; /* [26:31] */ + __IO uint32_t reserved : 6; /* [26:31] */ } bm_bit; }; @@ -1628,6 +1641,7 @@ void emac_address_filter_set(emac_address_type mac, emac_address_filter_type fil uint32_t emac_received_packet_size_get(void); uint32_t emac_dmarxdesc_frame_length_get(emac_dma_desc_type *dma_rx_desc); void emac_dma_descriptor_list_address_set(emac_dma_tx_rx_type transfer_type, emac_dma_desc_type *dma_desc_tab, uint8_t *buff, uint32_t buffer_count); +void emac_ptp_dma_descriptor_list_address_set(emac_dma_tx_rx_type transfer_type, emac_dma_desc_type *dma_desc_tab, emac_dma_desc_type *ptp_dma_desc_tab, uint8_t *buff, uint32_t buffer_count); uint32_t emac_dma_descriptor_list_address_get(emac_dma_tx_rx_type transfer_type); void emac_dma_rx_desc_interrupt_config(emac_dma_desc_type *dma_rx_desc, confirm_state new_state); void emac_dma_para_init(emac_dma_config_type *control_para); @@ -1650,6 +1664,7 @@ uint8_t emac_dma_missing_overflow_bit_get(void); uint16_t emac_dma_application_missing_frame_get(void); uint8_t emac_dma_fifo_overflow_bit_get(void); uint32_t emac_dma_tansfer_address_get(emac_dma_transfer_address_type transfer_type); +void emac_dma_alternate_desc_size(confirm_state new_state); void emac_mmc_counter_reset(void); void emac_mmc_rollover_stop(confirm_state new_state); void emac_mmc_reset_on_read_enable(confirm_state new_state); @@ -1676,19 +1691,19 @@ void emac_ptp_snapshot_event_message_enable(confirm_state new_state); void emac_ptp_snapshot_master_event_enable(confirm_state new_state); void emac_ptp_clock_node_set(emac_ptp_clock_node_type node); void emac_ptp_mac_address_filter_enable(confirm_state new_state); +flag_status emac_ptp_flag_get(uint32_t flag); void emac_ptp_subsecond_increment_set(uint8_t value); uint32_t emac_ptp_system_second_get(void); uint32_t emac_ptp_system_subsecond_get(void); confirm_state emac_ptp_system_time_sign_get(void); -void emac_ptp_system_second_set(uint32_t second); -void emac_ptp_system_subsecond_set(uint32_t subsecond); -void emac_ptp_system_time_sign_set(confirm_state sign); +void emac_ptp_system_time_set(uint32_t sign, uint32_t second, uint32_t subsecond); void emac_ptp_timestamp_addend_set(uint32_t value); void emac_ptp_target_second_set(uint32_t value); void emac_ptp_target_nanosecond_set(uint32_t value); confirm_state emac_ptp_timestamp_status_get(emac_ptp_timestamp_status_type status); void emac_ptp_pps_frequency_set(emac_ptp_pps_control_type freq); flag_status emac_dma_flag_get(uint32_t dma_flag); +flag_status emac_dma_interrupt_flag_get(uint32_t dma_flag); void emac_dma_flag_clear(uint32_t dma_flag); /** diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_exint.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_exint.h index a03d6e169a..cc32cfdd36 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_exint.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_exint.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_exint.h - * @version v2.0.9 - * @date 2022-04-25 * @brief at32f403a_407 exint header file ************************************************************************** * Copyright notice & Disclaimer @@ -208,6 +206,7 @@ void exint_default_para_init(exint_init_type *exint_struct); void exint_init(exint_init_type *exint_struct); void exint_flag_clear(uint32_t exint_line); flag_status exint_flag_get(uint32_t exint_line); +flag_status exint_interrupt_flag_get(uint32_t exint_line); void exint_software_interrupt_event_generate(uint32_t exint_line); void exint_interrupt_enable(uint32_t exint_line, confirm_state new_state); void exint_event_enable(uint32_t exint_line, confirm_state new_state); diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_flash.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_flash.h index 1e31aefff2..e41f839d3d 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_flash.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_flash.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_flash.h - * @version v2.0.9 - * @date 2022-04-25 * @brief at32f403a_407 flash header file ************************************************************************** * Copyright notice & Disclaimer @@ -190,7 +188,7 @@ typedef enum typedef enum { FLASH_SPIM_MODEL1 = 0x01, /*!< spim model 1 */ - FLASH_SPIM_MODEL2 = 0x02, /*!< spim model 2 */ + FLASH_SPIM_MODEL2 = 0x02 /*!< spim model 2 */ } flash_spim_model_type; /** @@ -700,12 +698,14 @@ uint8_t flash_ssb_status_get(void); void flash_interrupt_enable(uint32_t flash_int, confirm_state new_state); void flash_spim_model_select(flash_spim_model_type mode); void flash_spim_encryption_range_set(uint32_t decode_address); +void flash_spim_dummy_read(void); +flash_status_type flash_spim_mass_program(uint32_t address, uint8_t *buf, uint32_t cnt); flash_status_type flash_slib_enable(uint32_t pwd, uint16_t start_sector, uint16_t data_start_sector, uint16_t end_sector); error_status flash_slib_disable(uint32_t pwd); uint32_t flash_slib_remaining_count_get(void); flag_status flash_slib_state_get(void); uint16_t flash_slib_start_sector_get(void); -uint16_t flash_slib_datstart_sector_get(void); +uint16_t flash_slib_datastart_sector_get(void); uint16_t flash_slib_end_sector_get(void); uint32_t flash_crc_calibrate(uint32_t start_sector, uint32_t sector_cnt); diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_gpio.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_gpio.h index a4c3a9ae3f..00da64b61b 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_gpio.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_gpio.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_gpio.h - * @version v2.0.9 - * @date 2022-04-25 * @brief at32f403a_407 gpio header file ************************************************************************** * Copyright notice & Disclaimer @@ -215,8 +213,8 @@ extern "C" { #define SPI3_GMUX_0010 IOMUX_MAKE_VALUE(0x28, 24, 4, 0x02) /*!< spi3_cs/i2s3_ws(pa15), spi3_sck/i2s3_ck(pb3), spi3_miso(pb4), spi3_mosi/i2s3_sd(pb5), i2s3_mck(pb10) */ #define SPI3_GMUX_0011 IOMUX_MAKE_VALUE(0x28, 24, 4, 0x03) /*!< spi3_cs/i2s3_ws(pa4), spi3_sck/i2s3_ck(pc10), spi3_miso(pc11), spi3_mosi/i2s3_sd(pc12), i2s3_mck(pb10) */ #define SPI4_GMUX_0001 IOMUX_MAKE_VALUE(0x28, 28, 4, 0x01) /*!< spi4_cs/i2s4_ws(pe12), spi4_sck/i2s4_ck(pe11), spi4_miso(pe13), spi4_mosi/i2s4_sd(pe14), i2s4_mck(pc8) */ -#define SPI4_GMUX_0010 IOMUX_MAKE_VALUE(0x28, 28, 4, 0x02) /*!< spi4_cs/i2s4_ws(pb6), spi4_sck/i2s4_ck(pb7), spi4_miso(pb8), spi4_mosi/i2s4_sd(pb8), i2s4_mck(pc8) */ -#define SPI4_GMUX_0011 IOMUX_MAKE_VALUE(0x28, 28, 4, 0x03) /*!< spi4_cs/i2s4_ws(pb6), spi4_sck/i2s4_ck(pb7), spi4_miso(pb8), spi4_mosi/i2s4_sd(pb8), i2s4_mck(pa10) */ +#define SPI4_GMUX_0010 IOMUX_MAKE_VALUE(0x28, 28, 4, 0x02) /*!< spi4_cs/i2s4_ws(pb6), spi4_sck/i2s4_ck(pb7), spi4_miso(pb8), spi4_mosi/i2s4_sd(pb9), i2s4_mck(pc8) */ +#define SPI4_GMUX_0011 IOMUX_MAKE_VALUE(0x28, 28, 4, 0x03) /*!< spi4_cs/i2s4_ws(pb6), spi4_sck/i2s4_ck(pb7), spi4_miso(pb8), spi4_mosi/i2s4_sd(pb9), i2s4_mck(pa10) */ /** * @} @@ -914,7 +912,7 @@ uint16_t gpio_output_data_read(gpio_type *gpio_x); void gpio_bits_set(gpio_type *gpio_x, uint16_t pins); void gpio_bits_reset(gpio_type *gpio_x, uint16_t pins); void gpio_bits_write(gpio_type *gpio_x, uint16_t pins, confirm_state bit_state); -void gpio_port_wirte(gpio_type *gpio_x, uint16_t port_value); +void gpio_port_write(gpio_type *gpio_x, uint16_t port_value); void gpio_pin_wp_config(gpio_type *gpio_x, uint16_t pins); void gpio_pins_huge_driven_config(gpio_type *gpio_x, uint16_t pins, confirm_state new_state); void gpio_event_output_config(gpio_port_source_type gpio_port_source, gpio_pins_source_type gpio_pin_source); diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_i2c.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_i2c.h index bb46a0ac34..32f6badcdd 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_i2c.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_i2c.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_i2c.h - * @version v2.0.9 - * @date 2022-04-25 * @brief at32f403a_407 i2c header file ************************************************************************** * Copyright notice & Disclaimer @@ -381,6 +379,7 @@ void i2c_7bit_address_send(i2c_type *i2c_x, uint8_t address, i2c_direction_type void i2c_data_send(i2c_type *i2c_x, uint8_t data); uint8_t i2c_data_receive(i2c_type *i2c_x); flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag); +flag_status i2c_interrupt_flag_get(i2c_type *i2c_x, uint32_t flag); void i2c_flag_clear(i2c_type *i2c_x, uint32_t flag); /** diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_misc.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_misc.h index 1f06dc2b18..22e9c2ad8e 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_misc.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_misc.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_misc.h - * @version v2.0.9 - * @date 2022-04-25 * @brief at32f403a_407 misc header file ************************************************************************** * Copyright notice & Disclaimer @@ -76,9 +74,9 @@ typedef enum */ typedef enum { - NVIC_LP_SLEEPONEXIT = 0x02, /*!< send event on pending */ + NVIC_LP_SLEEPONEXIT = 0x02, /*!< enable sleep-on-exit feature */ NVIC_LP_SLEEPDEEP = 0x04, /*!< enable sleep-deep output signal when entering sleep mode */ - NVIC_LP_SEVONPEND = 0x10 /*!< enable sleep-on-exit feature */ + NVIC_LP_SEVONPEND = 0x10 /*!< send event on pending */ } nvic_lowpower_mode_type; /** diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_pwc.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_pwc.h index 7b154cd257..4d9e3544a2 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_pwc.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_pwc.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_pwc.h - * @version v2.0.9 - * @date 2022-04-25 * @brief at32f403a_407 pwc header file ************************************************************************** * Copyright notice & Disclaimer @@ -60,7 +58,7 @@ extern "C" { /** * @brief pwc wakeup pin num definition */ -#define PWC_WAKEUP_PIN_1 ((uint32_t)0x00000100) /*!< standby wake-up pin1 */ +#define PWC_WAKEUP_PIN_1 ((uint32_t)0x00000100) /*!< standby wake-up pin1(pa0) */ /** @defgroup PWC_exported_types * @{ diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_rtc.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_rtc.h index 5c4671db49..82318c91bf 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_rtc.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_rtc.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_rtc.h - * @version v2.0.9 - * @date 2022-04-25 * @brief at32f403a_407 rtc header file ************************************************************************** * Copyright notice & Disclaimer @@ -238,6 +236,7 @@ uint32_t rtc_divider_get(void); void rtc_alarm_set(uint32_t alarm_value); void rtc_interrupt_enable(uint16_t source, confirm_state new_state); flag_status rtc_flag_get(uint16_t flag); +flag_status rtc_interrupt_flag_get(uint16_t flag); void rtc_flag_clear(uint16_t flag); void rtc_wait_config_finish(void); void rtc_wait_update_finish(void); diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_sdio.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_sdio.h index f9b1238541..2ecbfa2919 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_sdio.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_sdio.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_sdio.h - * @version v2.0.9 - * @date 2022-04-25 * @brief at32f403a_407 sdio header file ************************************************************************** * Copyright notice & Disclaimer @@ -569,7 +567,10 @@ typedef struct * @} */ +#if defined (AT32F403ARx) || defined (AT32F403AVx) || defined (AT32F407Rx) || \ + defined (AT32F407Vx) #define SDIO1 ((sdio_type *) SDIO1_BASE) +#endif #define SDIO2 ((sdio_type *) SDIO2_BASE) /** @defgroup SDIO_exported_functions @@ -578,7 +579,7 @@ typedef struct void sdio_reset(sdio_type *sdio_x); void sdio_power_set(sdio_type *sdio_x, sdio_power_state_type power_state); -flag_status sdio_power_status_get(sdio_type *sdio_x); +sdio_power_state_type sdio_power_status_get(sdio_type *sdio_x); void sdio_clock_config(sdio_type *sdio_x, uint16_t clk_div, sdio_edge_phase_type clk_edg); void sdio_bus_width_config(sdio_type *sdio_x, sdio_bus_width_type width); void sdio_clock_bypass(sdio_type *sdio_x, confirm_state new_state); @@ -588,6 +589,7 @@ void sdio_clock_enable(sdio_type *sdio_x, confirm_state new_state); void sdio_dma_enable(sdio_type *sdio_x, confirm_state new_state); void sdio_interrupt_enable(sdio_type *sdio_x, uint32_t int_opt, confirm_state new_state); flag_status sdio_flag_get(sdio_type *sdio_x, uint32_t flag); +flag_status sdio_interrupt_flag_get(sdio_type *sdio_x, uint32_t flag); void sdio_flag_clear(sdio_type *sdio_x, uint32_t flag); void sdio_command_config(sdio_type *sdio_x, sdio_command_struct_type *command_struct); void sdio_command_state_machine_enable(sdio_type *sdio_x, confirm_state new_state); diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_spi.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_spi.h index 205363f454..125f0c9ad0 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_spi.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_spi.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_spi.h - * @version v2.0.9 - * @date 2022-04-25 * @brief at32f403a_407 spi header file ************************************************************************** * Copyright notice & Disclaimer @@ -478,6 +476,7 @@ void spi_i2s_dma_receiver_enable(spi_type* spi_x, confirm_state new_state); void spi_i2s_data_transmit(spi_type* spi_x, uint16_t tx_data); uint16_t spi_i2s_data_receive(spi_type* spi_x); flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag); +flag_status spi_i2s_interrupt_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag); void spi_i2s_flag_clear(spi_type* spi_x, uint32_t spi_i2s_flag); /** diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_tmr.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_tmr.h index 1404b70177..5b26f8d170 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_tmr.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_tmr.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_tmr.h - * @version v2.0.9 - * @date 2022-04-25 * @brief at32f403a_407 tmr header file ************************************************************************** * Copyright notice & Disclaimer @@ -238,7 +236,7 @@ typedef enum { TMR_CC_CHANNEL_MAPPED_DIRECT = 0x01, /*!< channel is configured as input, mapped direct */ TMR_CC_CHANNEL_MAPPED_INDIRECT = 0x02, /*!< channel is configured as input, mapped indirect */ - TMR_CC_CHANNEL_MAPPED_STI = 0x03 /*!< channel is configured as input, mapped trc */ + TMR_CC_CHANNEL_MAPPED_STI = 0x03 /*!< channel is configured as input, mapped sti */ } tmr_input_direction_mapped_type; /** @@ -888,7 +886,7 @@ void tmr_input_channel_filter_set(tmr_type *tmr_x, tmr_channel_select_type tmr_c uint16_t filter_value); void tmr_pwm_input_config(tmr_type *tmr_x, tmr_input_config_type *input_struct, \ tmr_channel_input_divider_type divider_factor); -void tmr_channel1_input_select(tmr_type *tmr_x, tmr_channel1_input_connected_type ti1_connect); +void tmr_channel1_input_select(tmr_type *tmr_x, tmr_channel1_input_connected_type ch1_connect); void tmr_input_channel_divider_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \ tmr_channel_input_divider_type divider_factor); void tmr_primary_mode_select(tmr_type *tmr_x, tmr_primary_select_type primary_mode); @@ -900,6 +898,7 @@ void tmr_trigger_input_select(tmr_type *tmr_x, sub_tmr_input_sel_type trigger_se void tmr_sub_sync_mode_set(tmr_type *tmr_x, confirm_state new_state); void tmr_dma_request_enable(tmr_type *tmr_x, tmr_dma_request_type dma_request, confirm_state new_state); void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state new_state); +flag_status tmr_interrupt_flag_get(tmr_type *tmr_x, uint32_t tmr_flag); flag_status tmr_flag_get(tmr_type *tmr_x, uint32_t tmr_flag); void tmr_flag_clear(tmr_type *tmr_x, uint32_t tmr_flag); void tmr_event_sw_trigger(tmr_type *tmr_x, tmr_event_trigger_type tmr_event); diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_usart.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_usart.h index c168b5a771..6c93ab86c7 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_usart.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_usart.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_usart.h - * @version v2.0.9 - * @date 2022-04-25 * @brief at32f403a_407 usart header file ************************************************************************** * Copyright notice & Disclaimer @@ -323,7 +321,10 @@ typedef struct #define UART5 ((usart_type *) UART5_BASE) #define USART6 ((usart_type *) USART6_BASE) #define UART7 ((usart_type *) UART7_BASE) +#if defined (AT32F403ARx) || defined (AT32F403AVx) || defined (AT32F407Rx) || \ + defined (AT32F407Vx) #define UART8 ((usart_type *) UART8_BASE) +#endif /** @defgroup USART_exported_functions * @{ @@ -357,6 +358,7 @@ void usart_irda_mode_enable(usart_type* usart_x, confirm_state new_state); void usart_irda_low_power_enable(usart_type* usart_x, confirm_state new_state); void usart_hardware_flow_control_set(usart_type* usart_x,usart_hardware_flow_control_type flow_state); flag_status usart_flag_get(usart_type* usart_x, uint32_t flag); +flag_status usart_interrupt_flag_get(usart_type* usart_x, uint32_t flag); void usart_flag_clear(usart_type* usart_x, uint32_t flag); /** diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_usb.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_usb.h index 21431c6eef..7c8976a8fa 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_usb.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_usb.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_usb.h - * @version v2.0.9 - * @date 2022-04-25 * @brief at32f403a_407 usb header file ************************************************************************** * Copyright notice & Disclaimer @@ -195,7 +193,6 @@ typedef enum #ifndef USB_EPT_MAX_NUM #define USB_EPT_MAX_NUM 8 /*!< usb device support endpoint number */ #endif - /** * @brief endpoint transfer type define */ @@ -692,6 +689,7 @@ void usb_remote_wkup_clear(usbd_type *usbx); uint16_t usb_buffer_malloc(uint16_t maxpacket); void usb_buffer_free(void); flag_status usb_flag_get(usbd_type *usbx, uint16_t flag); +flag_status usb_interrupt_flag_get(usbd_type *usbx, uint16_t flag); void usb_flag_clear(usbd_type *usbx, uint16_t flag); diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_wdt.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_wdt.h index f870840a7b..b581a567bf 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_wdt.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_wdt.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_wdt.h - * @version v2.0.9 - * @date 2022-04-25 * @brief at32f403a_407 wdt header file ************************************************************************** * Copyright notice & Disclaimer diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_wwdt.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_wwdt.h index 8c26c5a8b1..13a3023d0e 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_wwdt.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_wwdt.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_wwdt.h - * @version v2.0.9 - * @date 2022-04-25 * @brief at32f403a_407 wwdt header file ************************************************************************** * Copyright notice & Disclaimer @@ -136,6 +134,7 @@ void wwdt_flag_clear(void); void wwdt_enable(uint8_t wwdt_cnt); void wwdt_interrupt_enable(void); flag_status wwdt_flag_get(void); +flag_status wwdt_interrupt_flag_get(void); void wwdt_counter_set(uint8_t wwdt_cnt); void wwdt_window_counter_set(uint8_t window_cnt); diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_xmc.h b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_xmc.h index 67d26450fc..7f5c967281 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_xmc.h +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_xmc.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_xmc.h - * @version v2.0.9 - * @date 2022-04-25 * @brief at32f403a_407 xmc header file ************************************************************************** * Copyright notice & Disclaimer @@ -534,7 +532,7 @@ void xmc_norsram_default_para_init(xmc_norsram_init_type* xmc_nor_sram_init_stru void xmc_norsram_timing_default_para_init(xmc_norsram_timing_init_type* xmc_rw_timing_struct, xmc_norsram_timing_init_type* xmc_w_timing_struct); void xmc_nor_sram_enable(xmc_nor_sram_subbank_type xmc_subbank, confirm_state new_state); -void xmc_ext_timing_config(xmc_nor_sram_subbank_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing); +void xmc_ext_timing_config(volatile xmc_nor_sram_subbank_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing); void xmc_nand_reset(xmc_class_bank_type xmc_bank); void xmc_nand_init(xmc_nand_init_type* xmc_nand_init_struct); void xmc_nand_timing_config(xmc_nand_timinginit_type* xmc_common_spacetiming_struct, @@ -547,6 +545,7 @@ void xmc_nand_ecc_enable(xmc_class_bank_type xmc_bank, confirm_state new_state); uint32_t xmc_ecc_get(xmc_class_bank_type xmc_bank); void xmc_interrupt_enable(xmc_class_bank_type xmc_bank, xmc_interrupt_sources_type xmc_int, confirm_state new_state); flag_status xmc_flag_status_get(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag); +flag_status xmc_interrupt_flag_status_get(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag); void xmc_flag_clear(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag); /** diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_acc.c b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_acc.c index 770db6ac86..50ff284b86 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_acc.c +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_acc.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_acc.c - * @version v2.0.9 - * @date 2022-04-25 * @brief contains all the functions for the acc firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -190,6 +188,22 @@ flag_status acc_flag_get(uint16_t acc_flag) return (flag_status)(ACC->sts_bit.rslost); } +/** + * @brief check whether the specified acc interrupt flag is set or not. + * @param acc_flag: specifies the flag to check. + * this parameter can be one of the following values: + * - ACC_RSLOST_FLAG + * - ACC_CALRDY_FLAG + * @retval flag_status (SET or RESET) + */ +flag_status acc_interrupt_flag_get(uint16_t acc_flag) +{ + if(acc_flag == ACC_CALRDY_FLAG) + return (flag_status)(ACC->sts_bit.calrdy && ACC->ctrl1_bit.calrdyien); + else + return (flag_status)(ACC->sts_bit.rslost && ACC->ctrl1_bit.eien); +} + /** * @brief clear the specified acc flag is set or not. * @param acc_flag: specifies the flag to check. diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_adc.c b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_adc.c index 5161242761..d41d31d93d 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_adc.c +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_adc.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_adc.c - * @version v2.0.9 - * @date 2022-04-25 * @brief contains all the functions for the adc firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -116,7 +114,7 @@ void adc_combine_mode_select(adc_combine_mode_type combine_mode) * - ADC_LEFT_ALIGNMENT * @param ordinary_channel_length: configure the adc ordinary channel sequence length. * this parameter can be: - * - (0x1~0xf) + * - (0x1~0x10) * @retval none */ void adc_base_default_para_init(adc_base_config_type *adc_base_struct) @@ -142,7 +140,7 @@ void adc_base_default_para_init(adc_base_config_type *adc_base_struct) * - ADC_LEFT_ALIGNMENT * @param ordinary_channel_length: configure the adc ordinary channel sequence length. * this parameter can be: - * - (0x1~0xf) + * - (0x1~0x10) * @retval none */ void adc_base_config(adc_type *adc_x, adc_base_config_type *adc_base_struct) @@ -347,117 +345,42 @@ void adc_voltage_monitor_single_channel_select(adc_type *adc_x, adc_channel_sele */ void adc_ordinary_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime) { - switch(adc_channel) + uint32_t tmp_reg; + if(adc_channel < ADC_CHANNEL_10) { - case ADC_CHANNEL_0: - adc_x->spt2_bit.cspt0 = adc_sampletime; - break; - case ADC_CHANNEL_1: - adc_x->spt2_bit.cspt1 = adc_sampletime; - break; - case ADC_CHANNEL_2: - adc_x->spt2_bit.cspt2 = adc_sampletime; - break; - case ADC_CHANNEL_3: - adc_x->spt2_bit.cspt3 = adc_sampletime; - break; - case ADC_CHANNEL_4: - adc_x->spt2_bit.cspt4 = adc_sampletime; - break; - case ADC_CHANNEL_5: - adc_x->spt2_bit.cspt5 = adc_sampletime; - break; - case ADC_CHANNEL_6: - adc_x->spt2_bit.cspt6 = adc_sampletime; - break; - case ADC_CHANNEL_7: - adc_x->spt2_bit.cspt7 = adc_sampletime; - break; - case ADC_CHANNEL_8: - adc_x->spt2_bit.cspt8 = adc_sampletime; - break; - case ADC_CHANNEL_9: - adc_x->spt2_bit.cspt9 = adc_sampletime; - break; - case ADC_CHANNEL_10: - adc_x->spt1_bit.cspt10 = adc_sampletime; - break; - case ADC_CHANNEL_11: - adc_x->spt1_bit.cspt11 = adc_sampletime; - break; - case ADC_CHANNEL_12: - adc_x->spt1_bit.cspt12 = adc_sampletime; - break; - case ADC_CHANNEL_13: - adc_x->spt1_bit.cspt13 = adc_sampletime; - break; - case ADC_CHANNEL_14: - adc_x->spt1_bit.cspt14 = adc_sampletime; - break; - case ADC_CHANNEL_15: - adc_x->spt1_bit.cspt15 = adc_sampletime; - break; - case ADC_CHANNEL_16: - adc_x->spt1_bit.cspt16 = adc_sampletime; - break; - case ADC_CHANNEL_17: - adc_x->spt1_bit.cspt17 = adc_sampletime; - break; - default: - break; + tmp_reg = adc_x->spt2; + tmp_reg &= ~(0x07 << 3 * adc_channel); + tmp_reg |= adc_sampletime << 3 * adc_channel; + adc_x->spt2 = tmp_reg; } - switch(adc_sequence) + else { - case 1: - adc_x->osq3_bit.osn1 = adc_channel; - break; - case 2: - adc_x->osq3_bit.osn2 = adc_channel; - break; - case 3: - adc_x->osq3_bit.osn3 = adc_channel; - break; - case 4: - adc_x->osq3_bit.osn4 = adc_channel; - break; - case 5: - adc_x->osq3_bit.osn5 = adc_channel; - break; - case 6: - adc_x->osq3_bit.osn6 = adc_channel; - break; - case 7: - adc_x->osq2_bit.osn7 = adc_channel; - break; - case 8: - adc_x->osq2_bit.osn8 = adc_channel; - break; - case 9: - adc_x->osq2_bit.osn9 = adc_channel; - break; - case 10: - adc_x->osq2_bit.osn10 = adc_channel; - break; - case 11: - adc_x->osq2_bit.osn11 = adc_channel; - break; - case 12: - adc_x->osq2_bit.osn12 = adc_channel; - break; - case 13: - adc_x->osq1_bit.osn13 = adc_channel; - break; - case 14: - adc_x->osq1_bit.osn14 = adc_channel; - break; - case 15: - adc_x->osq1_bit.osn15 = adc_channel; - break; - case 16: - adc_x->osq1_bit.osn16 = adc_channel; - break; - default: - break; + tmp_reg = adc_x->spt1; + tmp_reg &= ~(0x07 << 3 * (adc_channel - ADC_CHANNEL_10)); + tmp_reg |= adc_sampletime << 3 * (adc_channel - ADC_CHANNEL_10); + adc_x->spt1 = tmp_reg; + } + + if(adc_sequence >= 13) + { + tmp_reg = adc_x->osq1; + tmp_reg &= ~(0x01F << 5 * (adc_sequence - 13)); + tmp_reg |= adc_channel << 5 * (adc_sequence - 13); + adc_x->osq1 = tmp_reg; + } + else if(adc_sequence >= 7) + { + tmp_reg = adc_x->osq2; + tmp_reg &= ~(0x01F << 5 * (adc_sequence - 7)); + tmp_reg |= adc_channel << 5 * (adc_sequence - 7); + adc_x->osq2 = tmp_reg; + } + else + { + tmp_reg = adc_x->osq3; + tmp_reg &= ~(0x01F << 5 * (adc_sequence - 1)); + tmp_reg |= adc_channel << 5 * (adc_sequence - 1); + adc_x->osq3 = tmp_reg; } } @@ -505,66 +428,23 @@ void adc_preempt_channel_length_set(adc_type *adc_x, uint8_t adc_channel_lenght) */ void adc_preempt_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime) { - uint16_t sequence_index=0; - switch(adc_channel) + uint32_t tmp_reg; + uint8_t sequence_index; + if(adc_channel < ADC_CHANNEL_10) { - case ADC_CHANNEL_0: - adc_x->spt2_bit.cspt0 = adc_sampletime; - break; - case ADC_CHANNEL_1: - adc_x->spt2_bit.cspt1 = adc_sampletime; - break; - case ADC_CHANNEL_2: - adc_x->spt2_bit.cspt2 = adc_sampletime; - break; - case ADC_CHANNEL_3: - adc_x->spt2_bit.cspt3 = adc_sampletime; - break; - case ADC_CHANNEL_4: - adc_x->spt2_bit.cspt4 = adc_sampletime; - break; - case ADC_CHANNEL_5: - adc_x->spt2_bit.cspt5 = adc_sampletime; - break; - case ADC_CHANNEL_6: - adc_x->spt2_bit.cspt6 = adc_sampletime; - break; - case ADC_CHANNEL_7: - adc_x->spt2_bit.cspt7 = adc_sampletime; - break; - case ADC_CHANNEL_8: - adc_x->spt2_bit.cspt8 = adc_sampletime; - break; - case ADC_CHANNEL_9: - adc_x->spt2_bit.cspt9 = adc_sampletime; - break; - case ADC_CHANNEL_10: - adc_x->spt1_bit.cspt10 = adc_sampletime; - break; - case ADC_CHANNEL_11: - adc_x->spt1_bit.cspt11 = adc_sampletime; - break; - case ADC_CHANNEL_12: - adc_x->spt1_bit.cspt12 = adc_sampletime; - break; - case ADC_CHANNEL_13: - adc_x->spt1_bit.cspt13 = adc_sampletime; - break; - case ADC_CHANNEL_14: - adc_x->spt1_bit.cspt14 = adc_sampletime; - break; - case ADC_CHANNEL_15: - adc_x->spt1_bit.cspt15 = adc_sampletime; - break; - case ADC_CHANNEL_16: - adc_x->spt1_bit.cspt16 = adc_sampletime; - break; - case ADC_CHANNEL_17: - adc_x->spt1_bit.cspt17 = adc_sampletime; - break; - default: - break; + tmp_reg = adc_x->spt2; + tmp_reg &= ~(0x07 << 3 * adc_channel); + tmp_reg |= adc_sampletime << 3 * adc_channel; + adc_x->spt2 = tmp_reg; } + else + { + tmp_reg = adc_x->spt1; + tmp_reg &= ~(0x07 << 3 * (adc_channel - ADC_CHANNEL_10)); + tmp_reg |= adc_sampletime << 3 * (adc_channel - ADC_CHANNEL_10); + adc_x->spt1 = tmp_reg; + } + sequence_index = adc_sequence + 3 - adc_x->psq_bit.pclen; switch(sequence_index) { @@ -857,10 +737,10 @@ uint32_t adc_combine_ordinary_conversion_data_get(void) * ADC1, ADC2, ADC3. * @param adc_preempt_channel: select the preempt channel. * this parameter can be one of the following values: - * - ADC_PREEMPTED_CHANNEL_1 - * - ADC_PREEMPTED_CHANNEL_2 - * - ADC_PREEMPTED_CHANNEL_3 - * - ADC_PREEMPTED_CHANNEL_4 + * - ADC_PREEMPT_CHANNEL_1 + * - ADC_PREEMPT_CHANNEL_2 + * - ADC_PREEMPT_CHANNEL_3 + * - ADC_PREEMPT_CHANNEL_4 * @retval the conversion data for selection preempt channel. */ uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel) @@ -915,6 +795,47 @@ flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag) return status; } +/** + * @brief get interrupt flag of the specified adc peripheral. + * @param adc_x: select the adc peripheral. + * this parameter can be one of the following values: + * ADC1, ADC2, ADC3. + * @param adc_flag: select the adc flag. + * this parameter can be one of the following values: + * - ADC_VMOR_FLAG + * - ADC_CCE_FLAG + * - ADC_PCCE_FLAG + * @retval the new state of adc flag status(SET or RESET). + */ +flag_status adc_interrupt_flag_get(adc_type *adc_x, uint8_t adc_flag) +{ + flag_status status = RESET; + switch(adc_flag) + { + case ADC_VMOR_FLAG: + if(adc_x->sts_bit.vmor && adc_x->ctrl1_bit.vmorien) + { + status = SET; + } + break; + case ADC_CCE_FLAG: + if(adc_x->sts_bit.cce && adc_x->ctrl1_bit.cceien) + { + status = SET; + } + break; + case ADC_PCCE_FLAG: + if(adc_x->sts_bit.pcce && adc_x->ctrl1_bit.pcceien) + { + status = SET; + } + break; + default: + break; + } + return status; +} + /** * @brief clear flag of the specified adc peripheral. * @param adc_x: select the adc peripheral. diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_bpr.c b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_bpr.c index 08e1922e1f..82d77a54dd 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_bpr.c +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_bpr.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_bpr.c - * @version v2.0.9 - * @date 2022-04-25 * @brief contains all the functions for the bpr firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -72,6 +70,26 @@ flag_status bpr_flag_get(uint32_t flag) } } +/** + * @brief bpr interrupt flag get + * @param flag: specifies the flag to check. + * this parameter can be one of the following values: + * - BPR_TAMPER_INTERRUPT_FLAG: tamper interrupt flag + * - BPR_TAMPER_EVENT_FLAG: tamper event flag + * @retval state of tamper event flag + */ +flag_status bpr_interrupt_flag_get(uint32_t flag) +{ + if(flag == BPR_TAMPER_INTERRUPT_FLAG) + { + return (flag_status)(BPR->ctrlsts_bit.tpif && BPR->ctrlsts_bit.tpien); + } + else + { + return (flag_status)(BPR->ctrlsts_bit.tpef && BPR->ctrlsts_bit.tpien); + } +} + /** * @brief clear bpr tamper flag * @param flag: specifies the flag to clear. diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_can.c b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_can.c index 12e4586d95..15496174fe 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_can.c +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_can.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_can.c - * @version v2.0.9 - * @date 2022-04-25 * @brief contains all the functions for the can firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -934,6 +932,102 @@ void can_interrupt_enable(can_type* can_x, uint32_t can_int, confirm_state new_s } } +/** + * @brief get interrupt flag of the specified can peripheral. + * @param can_x: select the can peripheral. + * this parameter can be one of the following values: + * CAN1,CAN2. + * @param can_flag: select the flag. + * this parameter can be one of the following flags: + * - CAN_EAF_FLAG + * - CAN_EPF_FLAG + * - CAN_BOF_FLAG + * - CAN_ETR_FLAG + * - CAN_EOIF_FLAG + * - CAN_TM0TCF_FLAG + * - CAN_TM1TCF_FLAG + * - CAN_TM2TCF_FLAG + * - CAN_RF0MN_FLAG + * - CAN_RF0FF_FLAG + * - CAN_RF0OF_FLAG + * - CAN_RF1MN_FLAG + * - CAN_RF1FF_FLAG + * - CAN_RF1OF_FLAG + * - CAN_QDZIF_FLAG + * - CAN_EDZC_FLAG + * - CAN_TMEF_FLAG + * note:the state of CAN_EDZC_FLAG need to check dzc and edzif bit + * note:the state of CAN_TMEF_FLAG need to check rqc0,rqc1 and rqc2 bit + * @retval status of can_flag, the returned value can be:SET or RESET. + */ +flag_status can_interrupt_flag_get(can_type* can_x, uint32_t can_flag) +{ + flag_status bit_status = RESET; + flag_status int_status = RESET; + + switch(can_flag) + { + case CAN_EAF_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.eaien); + break; + case CAN_EPF_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.epien); + break; + case CAN_BOF_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.boien); + break; + case CAN_ETR_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.etrien); + break; + case CAN_EOIF_FLAG: + int_status = (flag_status)can_x->inten_bit.eoien; + break; + case CAN_TM0TCF_FLAG: + case CAN_TM1TCF_FLAG: + case CAN_TM2TCF_FLAG: + int_status = (flag_status)can_x->inten_bit.tcien; + break; + case CAN_RF0MN_FLAG: + int_status = (flag_status)can_x->inten_bit.rf0mien; + break; + case CAN_RF0FF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf0fien; + break; + case CAN_RF0OF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf0oien; + break; + case CAN_RF1MN_FLAG: + int_status = (flag_status)can_x->inten_bit.rf1mien; + break; + case CAN_RF1FF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf1fien; + break; + case CAN_RF1OF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf1oien; + break; + case CAN_QDZIF_FLAG: + int_status = (flag_status)can_x->inten_bit.qdzien; + break; + case CAN_EDZC_FLAG: + int_status = (flag_status)can_x->inten_bit.edzien; + break; + case CAN_TMEF_FLAG: + int_status = (flag_status)can_x->inten_bit.tcien; + break; + default: + int_status = RESET; + break; + } + + if(int_status != SET) + { + return RESET; + } + bit_status = can_flag_get(can_x, can_flag); + + return bit_status; +} + /** * @brief get flag of the specified can peripheral. * @param can_x: select the can peripheral. diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_crc.c b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_crc.c index aa81315212..edd02a4898 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_crc.c +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_crc.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_crc.c - * @version v2.0.9 - * @date 2022-04-25 * @brief contains all the functions for the crc firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -106,7 +104,7 @@ void crc_common_data_set(uint8_t cdt_value) * @param none * @retval 8-bit value of the common data register */ -uint8_t crc_common_date_get(void) +uint8_t crc_common_data_get(void) { return (CRC->cdt_bit.cdt); } @@ -149,6 +147,52 @@ void crc_reverse_output_data_set(crc_reverse_output_type value) CRC->ctrl_bit.revod = value; } +/** + * @brief config crc polynomial value + * @param value + * 32-bit new data of crc poly value + * @retval none. + */ +void crc_poly_value_set(uint32_t value) +{ + CRC->poly = value; +} + +/** + * @brief return crc polynomial value + * @param none + * @retval 32-bit value of the polynomial value. + */ +uint32_t crc_poly_value_get(void) +{ + return (CRC->poly); +} + +/** + * @brief config crc polynomial data size + * @param size + * this parameter can be one of the following values: + * - CRC_POLY_SIZE_32B + * - CRC_POLY_SIZE_16B + * - CRC_POLY_SIZE_8B + * - CRC_POLY_SIZE_7B + * @retval none. + */ +void crc_poly_size_set(crc_poly_size_type size) +{ + CRC->ctrl_bit.poly_size = size; +} + +/** + * @brief return crc polynomial data size + * @param none + * @retval polynomial data size. + */ +crc_poly_size_type crc_poly_size_get(void) +{ + return (crc_poly_size_type)(CRC->ctrl_bit.poly_size); +} + /** * @} */ diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_crm.c b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_crm.c index c3ea29c3ae..8c58d81104 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_crm.c +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_crm.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_crm.c - * @version v2.0.9 - * @date 2022-04-25 * @brief contains all the functions for the crm firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -61,13 +59,13 @@ void crm_reset(void) /* wait sclk switch status */ while(CRM->cfg_bit.sclksts != CRM_SCLK_HICK); + /* reset hexten, hextbyps, cfden and pllen bits */ + CRM->ctrl &= ~(0x010D0000U); + /* reset cfg register, include sclk switch, ahbdiv, apb1div, apb2div, adcdiv, clkout pllrcs, pllhextdiv, pllmult, usbdiv and pllrange bits */ CRM->cfg = 0; - /* reset hexten, hextbyps, cfden and pllen bits */ - CRM->ctrl &= ~(0x010D0000U); - /* reset clkout[3], usbbufs, hickdiv, clkoutdiv */ CRM->misc1 = 0; @@ -133,6 +131,64 @@ flag_status crm_flag_get(uint32_t flag) return status; } +/** + * @brief get crm interrupt flag status + * @param flag + * this parameter can be one of the following values: + * - CRM_LICK_READY_INT_FLAG + * - CRM_LEXT_READY_INT_FLAG + * - CRM_HICK_READY_INT_FLAG + * - CRM_HEXT_READY_INT_FLAG + * - CRM_PLL_READY_INT_FLAG + * - CRM_CLOCK_FAILURE_INT_FLAG + * @retval flag_status (SET or RESET) + */ +flag_status crm_interrupt_flag_get(uint32_t flag) +{ + flag_status status = RESET; + switch(flag) + { + case CRM_LICK_READY_INT_FLAG: + if(CRM->clkint_bit.lickstblf && CRM->clkint_bit.lickstblien) + { + status = SET; + } + break; + case CRM_LEXT_READY_INT_FLAG: + if(CRM->clkint_bit.lextstblf && CRM->clkint_bit.lextstblien) + { + status = SET; + } + break; + case CRM_HICK_READY_INT_FLAG: + if(CRM->clkint_bit.hickstblf && CRM->clkint_bit.hickstblien) + { + status = SET; + } + break; + case CRM_HEXT_READY_INT_FLAG: + if(CRM->clkint_bit.hextstblf && CRM->clkint_bit.hextstblien) + { + status = SET; + } + break; + case CRM_PLL_READY_INT_FLAG: + if(CRM->clkint_bit.pllstblf && CRM->clkint_bit.pllstblien) + { + status = SET; + } + break; + case CRM_CLOCK_FAILURE_INT_FLAG: + if(CRM->clkint_bit.cfdf && CRM->ctrl_bit.cfden) + { + status = SET; + } + break; + } + + return status; +} + /** * @brief wait for hext stable * @param none @@ -348,6 +404,7 @@ void crm_flag_clear(uint32_t flag) case CRM_LOWPOWER_RESET_FLAG: case CRM_ALL_RESET_FLAG: CRM->ctrlsts_bit.rstfc = TRUE; + while(CRM->ctrlsts_bit.rstfc == TRUE); break; case CRM_LICK_READY_INT_FLAG: CRM->clkint_bit.lickstblfc = TRUE; @@ -418,6 +475,7 @@ void crm_ahb_div_set(crm_ahb_div_type value) /** * @brief set crm apb1 division + * @note the maximum frequency of APB1/APB2 clock is 120 MHz * @param value * this parameter can be one of the following values: * - CRM_APB1_DIV_1 @@ -434,6 +492,7 @@ void crm_apb1_div_set(crm_apb1_div_type value) /** * @brief set crm apb2 division + * @note the maximum frequency of APB1/APB2 clock is 120 MHz * @param value * this parameter can be one of the following values: * - CRM_APB2_DIV_1 @@ -525,6 +584,7 @@ void crm_pll_config(crm_pll_clock_source_type clock_source, crm_pll_mult_type mu if(clock_source == CRM_PLL_SOURCE_HICK) { CRM->cfg_bit.pllrcs = FALSE; + CRM->misc1_bit.hickdiv = CRM_HICK48_NODIV; } else { @@ -559,6 +619,7 @@ void crm_pll_config(crm_pll_clock_source_type clock_source, crm_pll_mult_type mu void crm_sysclk_switch(crm_sclk_type value) { CRM->cfg_bit.sclksel = value; + DUMMY_NOP(); } /** diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_dac.c b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_dac.c index b956361598..5791e8e2c8 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_dac.c +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_dac.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_dac.c - * @version v2.0.9 - * @date 2022-04-25 * @brief contains all the functions for the dac firmware library ************************************************************************** * Copyright notice & Disclaimer diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_debug.c b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_debug.c index 893cd604bd..d04d62a305 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_debug.c +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_debug.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_debug.c - * @version v2.0.9 - * @date 2022-04-25 * @brief contains all the functions for the debug firmware library ************************************************************************** * Copyright notice & Disclaimer diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_dma.c b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_dma.c index 39e036d0c7..ab2d16d9ab 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_dma.c +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_dma.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_dma.c - * @version v2.0.9 - * @date 2022-04-25 * @brief contains all the functions for the dma firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -280,6 +278,52 @@ void dma_flexible_config(dma_type* dma_x, uint8_t flex_channelx, dma_flexible_re } } +/** + * @brief get dma interrupt flag + * @param dmax_flag + * this parameter can be one of the following values: + * - DMA1_FDT1_FLAG - DMA1_HDT1_FLAG - DMA1_DTERR1_FLAG + * - DMA1_FDT2_FLAG - DMA1_HDT2_FLAG - DMA1_DTERR2_FLAG + * - DMA1_FDT3_FLAG - DMA1_HDT3_FLAG - DMA1_DTERR3_FLAG + * - DMA1_FDT4_FLAG - DMA1_HDT4_FLAG - DMA1_DTERR4_FLAG + * - DMA1_FDT5_FLAG - DMA1_HDT5_FLAG - DMA1_DTERR5_FLAG + * - DMA1_FDT6_FLAG - DMA1_HDT6_FLAG - DMA1_DTERR6_FLAG + * - DMA1_FDT7_FLAG - DMA1_HDT7_FLAG - DMA1_DTERR7_FLAG + * - DMA2_FDT1_FLAG - DMA2_HDT1_FLAG - DMA2_DTERR1_FLAG + * - DMA2_FDT2_FLAG - DMA2_HDT2_FLAG - DMA2_DTERR2_FLAG + * - DMA2_FDT3_FLAG - DMA2_HDT3_FLAG - DMA2_DTERR3_FLAG + * - DMA2_FDT4_FLAG - DMA2_HDT4_FLAG - DMA2_DTERR4_FLAG + * - DMA2_FDT5_FLAG - DMA2_HDT5_FLAG - DMA2_DTERR5_FLAG + * - DMA2_FDT6_FLAG - DMA2_HDT6_FLAG - DMA2_DTERR6_FLAG + * - DMA2_FDT7_FLAG - DMA2_HDT7_FLAG - DMA2_DTERR7_FLAG + * @retval state of dma flag + */ +flag_status dma_interrupt_flag_get(uint32_t dmax_flag) +{ + flag_status status = RESET; + uint32_t temp = 0; + + if(dmax_flag > 0x10000000) + { + temp = DMA2->sts; + } + else + { + temp = DMA1->sts; + } + + if ((temp & dmax_flag) != (uint16_t)RESET) + { + status = SET; + } + else + { + status = RESET; + } + + return status; +} + /** * @brief get dma flag * @param dmax_flag diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_emac.c b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_emac.c index a8b93ce5fe..5d25406723 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_emac.c +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_emac.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_emac.c - * @version v2.0.9 - * @date 2022-04-25 * @brief contains all the functions for the emac firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -45,8 +43,10 @@ /** * @brief global pointers on tx and rx descriptor used to track transmit and receive descriptors */ -emac_dma_desc_type *dma_tx_desc_to_set; -emac_dma_desc_type *dma_rx_desc_to_get; +__IO emac_dma_desc_type *dma_tx_desc_to_set; +__IO emac_dma_desc_type *dma_rx_desc_to_get; +__IO emac_dma_desc_type *ptp_dma_tx_desc_to_set; +__IO emac_dma_desc_type *ptp_dma_rx_desc_to_get; /* emac private function */ static void emac_delay(uint32_t delay); @@ -525,6 +525,7 @@ void emac_broadcast_frames_disable(confirm_state new_state) * @param condition: set what control frame can pass filter. * this parameter can be one of the following values: * - EMAC_CONTROL_FRAME_PASSING_NO + * - EMAC_CONTROL_FRAME_PASSING_ALL_EXCEPT_PAUSE * - EMAC_CONTROL_FRAME_PASSING_ALL * - EMAC_CONTROL_FRAME_PASSING_MATCH * @retval none @@ -984,6 +985,90 @@ void emac_dma_descriptor_list_address_set(emac_dma_tx_rx_type transfer_type, ema } } +/** + * @brief set transmit/receive descriptor list address + * @param transfer_type: it will be transmit or receive + * this parameter can be one of the following values: + * - EMAC_DMA_TRANSMIT + * - EMAC_DMA_RECEIVE + * @param dma_desc_tab: pointer on the first tx desc list + * @param buff: pointer on the first tx/rx buffer list + * @param buffer_count: number of the used Tx desc in the list + * @retval none + */ +void emac_ptp_dma_descriptor_list_address_set(emac_dma_tx_rx_type transfer_type, emac_dma_desc_type *dma_desc_tab, emac_dma_desc_type *ptp_dma_desc_tab, uint8_t *buff, uint32_t buffer_count) +{ + uint32_t i = 0; + emac_dma_desc_type *dma_descriptor; + + switch(transfer_type) + { + case EMAC_DMA_TRANSMIT: + { + dma_tx_desc_to_set = dma_desc_tab; + ptp_dma_tx_desc_to_set = ptp_dma_desc_tab; + + for(i = 0; i < buffer_count; i++) + { + dma_descriptor = dma_desc_tab + i; + + dma_descriptor->status = EMAC_DMATXDESC_TCH | EMAC_DMATXDESC_TTSE; + + dma_descriptor->buf1addr = (uint32_t)(&buff[i * EMAC_MAX_PACKET_LENGTH]); + + if(i < (buffer_count - 1)) + { + dma_descriptor->buf2nextdescaddr = (uint32_t)(dma_desc_tab + i + 1); + } + else + { + dma_descriptor->buf2nextdescaddr = (uint32_t) dma_desc_tab; + } + + (&ptp_dma_desc_tab[i])->buf1addr = dma_descriptor->buf1addr; + (&ptp_dma_desc_tab[i])->buf2nextdescaddr = dma_descriptor->buf2nextdescaddr; + } + + (&ptp_dma_desc_tab[i-1])->status = (uint32_t) ptp_dma_desc_tab; + + EMAC_DMA->tdladdr_bit.stl = (uint32_t) dma_desc_tab; + break; + } + case EMAC_DMA_RECEIVE: + { + dma_rx_desc_to_get = dma_desc_tab; + ptp_dma_rx_desc_to_get = ptp_dma_desc_tab; + + for(i = 0; i < buffer_count; i++) + { + dma_descriptor = dma_desc_tab + i; + + dma_descriptor->status = EMAC_DMARXDESC_OWN; + + dma_descriptor->controlsize = EMAC_DMARXDESC_RCH | (uint32_t)EMAC_MAX_PACKET_LENGTH; + + dma_descriptor->buf1addr = (uint32_t)(&buff[i * EMAC_MAX_PACKET_LENGTH]); + + if(i < (buffer_count - 1)) + { + dma_descriptor->buf2nextdescaddr = (uint32_t)(dma_desc_tab + i + 1); + } + else + { + dma_descriptor->buf2nextdescaddr = (uint32_t) dma_desc_tab; + } + + (&ptp_dma_desc_tab[i])->buf1addr = dma_descriptor->buf1addr; + (&ptp_dma_desc_tab[i])->buf2nextdescaddr = dma_descriptor->buf2nextdescaddr; + } + + (&ptp_dma_desc_tab[i-1])->status = (uint32_t) ptp_dma_desc_tab; + + EMAC_DMA->rdladdr_bit.srl = (uint32_t) dma_desc_tab; + break; + } + } +} /** * @brief enable or disable the specified dma rx descriptor receive interrupt * @param dma_rx_desc: pointer on a rx desc. @@ -1044,7 +1129,7 @@ uint32_t emac_received_packet_size_get(void) ((dma_rx_desc_to_get->status & EMAC_DMARXDESC_LS) != (uint32_t)RESET) && ((dma_rx_desc_to_get->status & EMAC_DMARXDESC_FS) != (uint32_t)RESET)) { - frame_length = emac_dmarxdesc_frame_length_get(dma_rx_desc_to_get); + frame_length = emac_dmarxdesc_frame_length_get((emac_dma_desc_type*) dma_rx_desc_to_get); } return frame_length; @@ -1655,6 +1740,16 @@ uint32_t emac_dma_tansfer_address_get(emac_dma_transfer_address_type transfer_ty return address; } +/** + * @brief alternate dma descriptor size + * @param new_state: TRUE or FALSE + * @retval none + */ +void emac_dma_alternate_desc_size(confirm_state new_state) +{ + EMAC_DMA->bm_bit.atds = new_state; +} + /** * @brief reset all counter * @param none @@ -2034,6 +2129,27 @@ void emac_ptp_mac_address_filter_enable(confirm_state new_state) EMAC_PTP->tsctrl_bit.emafpff = new_state; } +/** + * @brief check whether the specified emac ptp flag is set or not. + * @param flag: specifies the flag to check. + * this parameter can be one of the following values: + * - EMAC_PTP_TI_FLAG: time stamp initialized flag + * - EMAC_PTP_TU_FLAG: time stamp updtated flag + * - EMAC_PTP_ARU_FLAG: transmit data buffer empty flag + * @retval the new state of usart_flag (SET or RESET). + */ +flag_status emac_ptp_flag_get(uint32_t flag) +{ + if(EMAC_PTP->tsctrl & flag) + { + return SET; + } + else + { + return RESET; + } +} + /** * @brief set subsecond increment value * @param value: add to subsecond value for every update @@ -2084,42 +2200,19 @@ confirm_state emac_ptp_system_time_sign_get(void) } /** - * @brief set system time second + * @brief set system time + * @param sign: plus or minus * @param second: system time second - * @retval none - */ -void emac_ptp_system_second_set(uint32_t second) -{ - EMAC_PTP->tshud_bit.ts = second; -} - -/** - * @brief set system time subsecond * @param subsecond: system time subsecond * @retval none */ -void emac_ptp_system_subsecond_set(uint32_t subsecond) +void emac_ptp_system_time_set(uint32_t sign, uint32_t second, uint32_t subsecond) { + EMAC_PTP->tslud_bit.ast = sign ? 1 : 0; + EMAC_PTP->tshud_bit.ts = second; EMAC_PTP->tslud_bit.tss = subsecond; } -/** - * @brief set system time sign - * @param sign: TRUE or FALSE. - * @retval none - */ -void emac_ptp_system_time_sign_set(confirm_state sign) -{ - if(sign) - { - EMAC_PTP->tslud_bit.ast = 1; - } - else - { - EMAC_PTP->tslud_bit.ast = 0; - } -} - /** * @brief set time stamp addend * @param value: to achieve time synchronization @@ -2261,6 +2354,62 @@ flag_status emac_dma_flag_get(uint32_t dma_flag) return status; } +/** + * @brief check whether the specified emac dma interrupt flag is set or not. + * @param dma_flag: specifies the emac dma flag to check. + * this parameter can be one of emac dma flag status: + * - EMAC_DMA_TI_FLAG + * - EMAC_DMA_TPS_FLAG + * - EMAC_DMA_TBU_FLAG + * - EMAC_DMA_TJT_FLAG + * - EMAC_DMA_OVF_FLAG + * - EMAC_DMA_UNF_FLAG + * - EMAC_DMA_RI_FLAG + * - EMAC_DMA_RBU_FLAG + * - EMAC_DMA_RPS_FLAG + * - EMAC_DMA_RWT_FLAG + * - EMAC_DMA_ETI_FLAG + * - EMAC_DMA_FBEI_FLAG + * - EMAC_DMA_ERI_FLAG + * - EMAC_DMA_AIS_FLAG + * - EMAC_DMA_NIS_FLAG + * @retval the new state of dma_flag (SET or RESET). + */ +flag_status emac_dma_interrupt_flag_get(uint32_t dma_flag) +{ + flag_status status = RESET; + switch(dma_flag) + { + case EMAC_DMA_TI_FLAG: + case EMAC_DMA_TBU_FLAG: + case EMAC_DMA_RI_FLAG: + case EMAC_DMA_ERI_FLAG: + if((EMAC_DMA->sts & dma_flag) && + (EMAC_DMA->ie & dma_flag) && + (EMAC_DMA->sts & EMAC_DMA_NIS_FLAG)) + status = SET; + break; + case EMAC_DMA_TPS_FLAG: + case EMAC_DMA_TJT_FLAG: + case EMAC_DMA_OVF_FLAG: + case EMAC_DMA_UNF_FLAG: + case EMAC_DMA_RBU_FLAG: + case EMAC_DMA_RPS_FLAG: + case EMAC_DMA_RWT_FLAG: + case EMAC_DMA_ETI_FLAG: + case EMAC_DMA_FBEI_FLAG: + if((EMAC_DMA->sts & dma_flag) && + (EMAC_DMA->ie & dma_flag) && + (EMAC_DMA->sts & EMAC_DMA_AIS_FLAG)) + status = SET; + break; + default: + break; + } + /* return the new state (SET or RESET) */ + return status; +} + /** * @brief clear the emac dma flag. * @param dma_flag: specifies the emac dma flags to clear. diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_exint.c b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_exint.c index c6ef1c335e..0768afd3bf 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_exint.c +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_exint.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_exint.c - * @version v2.0.9 - * @date 2022-04-25 * @brief contains all the functions for the exint firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -125,7 +123,15 @@ void exint_init(exint_init_type *exint_struct) */ void exint_flag_clear(uint32_t exint_line) { - EXINT->intsts = exint_line; + if((EXINT->swtrg & exint_line) == exint_line) + { + EXINT->intsts = exint_line; + EXINT->intsts = exint_line; + } + else + { + EXINT->intsts = exint_line; + } } /** @@ -155,6 +161,35 @@ flag_status exint_flag_get(uint32_t exint_line) return status; } +/** + * @brief get exint interrupt flag + * @param exint_line + * this parameter can be one of the following values: + * - EXINT_LINE_0 + * - EXINT_LINE_1 + * ... + * - EXINT_LINE_18 + * - EXINT_LINE_19 + * @retval the new state of exint flag(SET or RESET). + */ +flag_status exint_interrupt_flag_get(uint32_t exint_line) +{ + flag_status status = RESET; + uint32_t exint_flag = 0; + exint_flag = EXINT->intsts & exint_line; + exint_flag = exint_flag & EXINT->inten; + + if((exint_flag != (uint16_t)RESET)) + { + status = SET; + } + else + { + status = RESET; + } + return status; +} + /** * @brief generate exint software interrupt event * @param exint_line diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_flash.c b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_flash.c index 98e7cb9922..3e1921e478 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_flash.c +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_flash.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_flash.c - * @version v2.0.9 - * @date 2022-04-25 * @brief contains all the functions for the flash firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -448,62 +446,43 @@ flash_status_type flash_sector_erase(uint32_t sector_address) flash_status_type status = FLASH_OPERATE_DONE; if((sector_address >= FLASH_BANK1_START_ADDR) && (sector_address <= FLASH_BANK1_END_ADDR)) { - /* wait for last operation to be completed */ + FLASH->ctrl_bit.secers = TRUE; + FLASH->addr = sector_address; + FLASH->ctrl_bit.erstr = TRUE; + + /* wait for operation to be completed */ status = flash_bank1_operation_wait_for(ERASE_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* if the previous operation is completed, continue to erase the sector */ - FLASH->ctrl_bit.secers = TRUE; - FLASH->addr = sector_address; - FLASH->ctrl_bit.erstr = TRUE; - - /* wait for operation to be completed */ - status = flash_bank1_operation_wait_for(ERASE_TIMEOUT); - - /* disable the secers bit */ - FLASH->ctrl_bit.secers = FALSE; - } + /* disable the secers bit */ + FLASH->ctrl_bit.secers = FALSE; } else if((sector_address >= FLASH_BANK2_START_ADDR) && (sector_address <= FLASH_BANK2_END_ADDR)) { - /* wait for last operation to be completed */ + FLASH->ctrl2_bit.secers = TRUE; + FLASH->addr2 = sector_address; + FLASH->ctrl2_bit.erstr = TRUE; + + /* wait for operation to be completed */ status = flash_bank2_operation_wait_for(ERASE_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* if the previous operation is completed, continue to erase the sector */ - FLASH->ctrl2_bit.secers = TRUE; - FLASH->addr2 = sector_address; - FLASH->ctrl2_bit.erstr = TRUE; - - /* wait for operation to be completed */ - status = flash_bank2_operation_wait_for(ERASE_TIMEOUT); - - /* disable the secers bit */ - FLASH->ctrl2_bit.secers = FALSE; - } + /* disable the secers bit */ + FLASH->ctrl2_bit.secers = FALSE; } /* spim : external flash */ else if(sector_address >= FLASH_SPIM_START_ADDR) { - /* wait for last operation to be completed */ + FLASH->ctrl3_bit.secers = TRUE; + FLASH->addr3 = sector_address; + FLASH->ctrl3_bit.erstr = TRUE; + + /* wait for operation to be completed */ status = flash_spim_operation_wait_for(SPIM_ERASE_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* if the previous operation is completed, continue to erase the sector */ - FLASH->ctrl3_bit.secers = TRUE; - FLASH->addr3 = sector_address; - FLASH->ctrl3_bit.erstr = TRUE; + /* disable the secers bit */ + FLASH->ctrl3_bit.secers = FALSE; - /* wait for operation to be completed */ - status = flash_spim_operation_wait_for(SPIM_ERASE_TIMEOUT); - - /* disable the secers bit */ - FLASH->ctrl3_bit.secers = FALSE; - } - return status; + /* dummy read */ + flash_spim_dummy_read(); } /* return the erase status */ @@ -519,21 +498,16 @@ flash_status_type flash_sector_erase(uint32_t sector_address) flash_status_type flash_internal_all_erase(void) { flash_status_type status = FLASH_OPERATE_DONE; - /* wait for last operation to be completed */ + + FLASH->ctrl_bit.bankers = TRUE; + FLASH->ctrl_bit.erstr = TRUE; + + /* wait for operation to be completed */ status = flash_bank1_operation_wait_for(ERASE_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* if the previous operation is completed, continue to erase bank1 */ - FLASH->ctrl_bit.bankers = TRUE; - FLASH->ctrl_bit.erstr = TRUE; + /* disable the bankers bit */ + FLASH->ctrl_bit.bankers = FALSE; - /* wait for operation to be completed */ - status = flash_bank1_operation_wait_for(ERASE_TIMEOUT); - - /* disable the bankers bit */ - FLASH->ctrl_bit.bankers = FALSE; - } if(status == FLASH_OPERATE_DONE) { /* if the previous operation is completed, continue to erase bank2 */ @@ -559,21 +533,16 @@ flash_status_type flash_internal_all_erase(void) flash_status_type flash_bank1_erase(void) { flash_status_type status = FLASH_OPERATE_DONE; - /* wait for last operation to be completed */ + + FLASH->ctrl_bit.bankers = TRUE; + FLASH->ctrl_bit.erstr = TRUE; + + /* wait for operation to be completed */ status = flash_bank1_operation_wait_for(ERASE_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* if the previous operation is completed, continue to erase bank1 */ - FLASH->ctrl_bit.bankers = TRUE; - FLASH->ctrl_bit.erstr = TRUE; + /* disable the bankers bit */ + FLASH->ctrl_bit.bankers = FALSE; - /* wait for operation to be completed */ - status = flash_bank1_operation_wait_for(ERASE_TIMEOUT); - - /* disable the bankers bit */ - FLASH->ctrl_bit.bankers = FALSE; - } /* return the erase status */ return status; } @@ -587,21 +556,16 @@ flash_status_type flash_bank1_erase(void) flash_status_type flash_bank2_erase(void) { flash_status_type status = FLASH_OPERATE_DONE; - /* wait for last operation to be completed */ + + FLASH->ctrl2_bit.bankers = TRUE; + FLASH->ctrl2_bit.erstr = TRUE; + + /* wait for operation to be completed */ status = flash_bank2_operation_wait_for(ERASE_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* if the previous operation is completed, continue to erase bank2 */ - FLASH->ctrl2_bit.bankers = TRUE; - FLASH->ctrl2_bit.erstr = TRUE; + /* disable the bankers bit */ + FLASH->ctrl2_bit.bankers = FALSE; - /* wait for operation to be completed */ - status = flash_bank2_operation_wait_for(ERASE_TIMEOUT); - - /* disable the bankers bit */ - FLASH->ctrl2_bit.bankers = FALSE; - } /* return the erase status */ return status; } @@ -615,21 +579,19 @@ flash_status_type flash_bank2_erase(void) flash_status_type flash_spim_all_erase(void) { flash_status_type status = FLASH_OPERATE_DONE; - /* wait for last operation to be completed */ + + FLASH->ctrl3_bit.chpers = TRUE; + FLASH->ctrl3_bit.erstr = TRUE; + + /* wait for operation to be completed */ status = flash_spim_operation_wait_for(SPIM_ERASE_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* if the previous operation is completed, continue to erase spim */ - FLASH->ctrl3_bit.chpers = TRUE; - FLASH->ctrl3_bit.erstr = TRUE; + /* disable the chpers bit */ + FLASH->ctrl3_bit.chpers = FALSE; - /* wait for operation to be completed */ - status = flash_spim_operation_wait_for(SPIM_ERASE_TIMEOUT); + /* dummy read */ + flash_spim_dummy_read(); - /* disable the chpers bit */ - FLASH->ctrl3_bit.chpers = FALSE; - } /* return the erase status */ return status; } @@ -645,47 +607,43 @@ flash_status_type flash_user_system_data_erase(void) { flash_status_type status = FLASH_OPERATE_DONE; uint16_t fap_val = FAP_RELIEVE_KEY; + /* get the flash access protection status */ if(flash_fap_status_get() != RESET) { fap_val = 0x0000; } - /* wait for last operation to be completed */ + /* unlock the user system data */ + FLASH->usd_unlock = FLASH_UNLOCK_KEY1; + FLASH->usd_unlock = FLASH_UNLOCK_KEY2; + while(FLASH->ctrl_bit.usdulks==RESET); + + /* erase the user system data */ + FLASH->ctrl_bit.usders = TRUE; + FLASH->ctrl_bit.erstr = TRUE; + + /* wait for operation to be completed */ status = flash_operation_wait_for(ERASE_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* unlock the user system data */ - FLASH->usd_unlock = FLASH_UNLOCK_KEY1; - FLASH->usd_unlock = FLASH_UNLOCK_KEY2; - while(FLASH->ctrl_bit.usdulks==RESET); + /* disable the usders bit */ + FLASH->ctrl_bit.usders = FALSE; - /* erase the user system data */ - FLASH->ctrl_bit.usders = TRUE; - FLASH->ctrl_bit.erstr = TRUE; + if((status == FLASH_OPERATE_DONE) && (fap_val == FAP_RELIEVE_KEY)) + { + /* enable the user system data programming operation */ + FLASH->ctrl_bit.usdprgm = TRUE; + + /* restore the last flash access protection value */ + USD->fap = (uint16_t)fap_val; /* wait for operation to be completed */ - status = flash_operation_wait_for(ERASE_TIMEOUT); + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - /* disable the usders bit */ - FLASH->ctrl_bit.usders = FALSE; - - if((status == FLASH_OPERATE_DONE) && (fap_val == FAP_RELIEVE_KEY)) - { - /* enable the user system data programming operation */ - FLASH->ctrl_bit.usdprgm = TRUE; - - /* restore the last flash access protection value */ - USD->fap = (uint16_t)fap_val; - - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - - /*disable the usdprgm bit */ - FLASH->ctrl_bit.usdprgm = FALSE; - } + /*disable the usdprgm bit */ + FLASH->ctrl_bit.usdprgm = FALSE; } + /* return the erase status */ return status; } @@ -702,52 +660,37 @@ flash_status_type flash_word_program(uint32_t address, uint32_t data) flash_status_type status = FLASH_OPERATE_DONE; if((address >= FLASH_BANK1_START_ADDR) && (address <= FLASH_BANK1_END_ADDR)) { - /* wait for last operation to be completed */ + FLASH->ctrl_bit.fprgm = TRUE; + *(__IO uint32_t*)address = data; + /* wait for operation to be completed */ status = flash_bank1_operation_wait_for(PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - FLASH->ctrl_bit.fprgm = TRUE; - *(__IO uint32_t*)address = data; - /* wait for operation to be completed */ - status = flash_bank1_operation_wait_for(PROGRAMMING_TIMEOUT); - - /* disable the fprgm bit */ - FLASH->ctrl_bit.fprgm = FALSE; - } + /* disable the fprgm bit */ + FLASH->ctrl_bit.fprgm = FALSE; } else if((address >= FLASH_BANK2_START_ADDR) && (address <= FLASH_BANK2_END_ADDR)) { - /* wait for last operation to be completed */ + FLASH->ctrl2_bit.fprgm = TRUE; + *(__IO uint32_t*)address = data; + /* wait for operation to be completed */ status = flash_bank2_operation_wait_for(PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - FLASH->ctrl2_bit.fprgm = TRUE; - *(__IO uint32_t*)address = data; - /* wait for operation to be completed */ - status = flash_bank2_operation_wait_for(PROGRAMMING_TIMEOUT); - - /* disable the fprgm bit */ - FLASH->ctrl2_bit.fprgm = FALSE; - } + /* disable the fprgm bit */ + FLASH->ctrl2_bit.fprgm = FALSE; } /* spim : external flash */ else if(address >= FLASH_SPIM_START_ADDR) { - /* wait for last operation to be completed */ + FLASH->ctrl3_bit.fprgm = TRUE; + *(__IO uint32_t*)address = data; + /* wait for operation to be completed */ status = flash_spim_operation_wait_for(SPIM_PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - FLASH->ctrl3_bit.fprgm = TRUE; - *(__IO uint32_t*)address = data; - /* wait for operation to be completed */ - status = flash_spim_operation_wait_for(SPIM_PROGRAMMING_TIMEOUT); + /* disable the fprgm bit */ + FLASH->ctrl3_bit.fprgm = FALSE; - /* disable the fprgm bit */ - FLASH->ctrl3_bit.fprgm = FALSE; - } + /* dummy read */ + flash_spim_dummy_read(); } /* return the program status */ @@ -766,52 +709,37 @@ flash_status_type flash_halfword_program(uint32_t address, uint16_t data) flash_status_type status = FLASH_OPERATE_DONE; if((address >= FLASH_BANK1_START_ADDR) && (address <= FLASH_BANK1_END_ADDR)) { - /* wait for last operation to be completed */ + FLASH->ctrl_bit.fprgm = TRUE; + *(__IO uint16_t*)address = data; + /* wait for operation to be completed */ status = flash_bank1_operation_wait_for(PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - FLASH->ctrl_bit.fprgm = TRUE; - *(__IO uint16_t*)address = data; - /* wait for operation to be completed */ - status = flash_bank1_operation_wait_for(PROGRAMMING_TIMEOUT); - - /* disable the fprgm bit */ - FLASH->ctrl_bit.fprgm = FALSE; - } + /* disable the fprgm bit */ + FLASH->ctrl_bit.fprgm = FALSE; } else if((address >= FLASH_BANK2_START_ADDR) && (address <= FLASH_BANK2_END_ADDR)) { - /* wait for last operation to be completed */ + FLASH->ctrl2_bit.fprgm = TRUE; + *(__IO uint16_t*)address = data; + /* wait for operation to be completed */ status = flash_bank2_operation_wait_for(PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - FLASH->ctrl2_bit.fprgm = TRUE; - *(__IO uint16_t*)address = data; - /* wait for operation to be completed */ - status = flash_bank2_operation_wait_for(PROGRAMMING_TIMEOUT); - - /* disable the fprgm bit */ - FLASH->ctrl2_bit.fprgm = FALSE; - } + /* disable the fprgm bit */ + FLASH->ctrl2_bit.fprgm = FALSE; } /* spim : external flash */ else if(address >= FLASH_SPIM_START_ADDR) { - /* wait for last operation to be completed */ + FLASH->ctrl3_bit.fprgm = TRUE; + *(__IO uint16_t*)address = data; + /* wait for operation to be completed */ status = flash_spim_operation_wait_for(SPIM_PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - FLASH->ctrl3_bit.fprgm = TRUE; - *(__IO uint16_t*)address = data; - /* wait for operation to be completed */ - status = flash_spim_operation_wait_for(SPIM_PROGRAMMING_TIMEOUT); + /* disable the fprgm bit */ + FLASH->ctrl3_bit.fprgm = FALSE; - /* disable the fprgm bit */ - FLASH->ctrl3_bit.fprgm = FALSE; - } + /* dummy read */ + flash_spim_dummy_read(); } /* return the program status */ @@ -831,35 +759,23 @@ flash_status_type flash_byte_program(uint32_t address, uint8_t data) flash_status_type status = FLASH_OPERATE_DONE; if((address >= FLASH_BANK1_START_ADDR) && (address <= FLASH_BANK1_END_ADDR)) { - /* wait for last operation to be completed */ + FLASH->ctrl_bit.fprgm = TRUE; + *(__IO uint8_t*)address = data; + /* wait for operation to be completed */ status = flash_bank1_operation_wait_for(PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - FLASH->ctrl_bit.fprgm = TRUE; - *(__IO uint8_t*)address = data; - /* wait for operation to be completed */ - status = flash_bank1_operation_wait_for(PROGRAMMING_TIMEOUT); - - /* disable the fprgm bit */ - FLASH->ctrl_bit.fprgm = FALSE; - } + /* disable the fprgm bit */ + FLASH->ctrl_bit.fprgm = FALSE; } else if((address >= FLASH_BANK2_START_ADDR) && (address <= FLASH_BANK2_END_ADDR)) { - /* wait for last operation to be completed */ + FLASH->ctrl2_bit.fprgm = TRUE; + *(__IO uint8_t*)address = data; + /* wait for operation to be completed */ status = flash_bank2_operation_wait_for(PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - FLASH->ctrl2_bit.fprgm = TRUE; - *(__IO uint8_t*)address = data; - /* wait for operation to be completed */ - status = flash_bank2_operation_wait_for(PROGRAMMING_TIMEOUT); - - /* disable the fprgm bit */ - FLASH->ctrl2_bit.fprgm = FALSE; - } + /* disable the fprgm bit */ + FLASH->ctrl2_bit.fprgm = FALSE; } /* return the program status */ return status; @@ -875,24 +791,28 @@ flash_status_type flash_byte_program(uint32_t address, uint8_t data) flash_status_type flash_user_system_data_program(uint32_t address, uint8_t data) { flash_status_type status = FLASH_OPERATE_DONE; - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) + + if(address == USD_BASE) { - /* unlock the user system data */ - FLASH->usd_unlock = FLASH_UNLOCK_KEY1; - FLASH->usd_unlock = FLASH_UNLOCK_KEY2; - while(FLASH->ctrl_bit.usdulks==RESET); - - /* enable the user system data programming operation */ - FLASH->ctrl_bit.usdprgm = TRUE; - *(__IO uint16_t*)address = data; - - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - - /* disable the usdprgm bit */ - FLASH->ctrl_bit.usdprgm = FALSE; + if(data != 0xA5) + return FLASH_OPERATE_DONE; } + + /* unlock the user system data */ + FLASH->usd_unlock = FLASH_UNLOCK_KEY1; + FLASH->usd_unlock = FLASH_UNLOCK_KEY2; + while(FLASH->ctrl_bit.usdulks==RESET); + + /* enable the user system data programming operation */ + FLASH->ctrl_bit.usdprgm = TRUE; + *(__IO uint16_t*)address = data; + + /* wait for operation to be completed */ + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); + + /* disable the usdprgm bit */ + FLASH->ctrl_bit.usdprgm = FALSE; + /* return the user system data program status */ return status; } @@ -915,42 +835,38 @@ flash_status_type flash_epp_set(uint32_t *sector_bits) epp_data[1] = (uint16_t)((sector_bits[0] >> 8) & 0xFF); epp_data[2] = (uint16_t)((sector_bits[0] >> 16) & 0xFF); epp_data[3] = (uint16_t)((sector_bits[0] >> 24) & 0xFF); - /* wait for last operation to be completed */ + + /* unlock the user system data */ + FLASH->usd_unlock = FLASH_UNLOCK_KEY1; + FLASH->usd_unlock = FLASH_UNLOCK_KEY2; + while(FLASH->ctrl_bit.usdulks==RESET); + + FLASH->ctrl_bit.usdprgm = TRUE; + USD->epp0 = epp_data[0]; + /* wait for operation to be completed */ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); if(status == FLASH_OPERATE_DONE) { - /* unlock the user system data */ - FLASH->usd_unlock = FLASH_UNLOCK_KEY1; - FLASH->usd_unlock = FLASH_UNLOCK_KEY2; - while(FLASH->ctrl_bit.usdulks==RESET); - - FLASH->ctrl_bit.usdprgm = TRUE; - USD->epp0 = epp_data[0]; + USD->epp1 = epp_data[1]; /* wait for operation to be completed */ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - - if(status == FLASH_OPERATE_DONE) - { - USD->epp1 = epp_data[1]; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - } - if(status == FLASH_OPERATE_DONE) - { - USD->epp2 = epp_data[2]; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - } - if(status == FLASH_OPERATE_DONE) - { - USD->epp3 = epp_data[3]; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - } - /* disable the usdprgm bit */ - FLASH->ctrl_bit.usdprgm = FALSE; } + if(status == FLASH_OPERATE_DONE) + { + USD->epp2 = epp_data[2]; + /* wait for operation to be completed */ + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); + } + if(status == FLASH_OPERATE_DONE) + { + USD->epp3 = epp_data[3]; + /* wait for operation to be completed */ + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); + } + /* disable the usdprgm bit */ + FLASH->ctrl_bit.usdprgm = FALSE; + /* return the erase/program protection operation status */ return status; } @@ -978,38 +894,36 @@ void flash_epp_status_get(uint32_t *sector_bits) flash_status_type flash_fap_enable(confirm_state new_state) { flash_status_type status = FLASH_OPERATE_DONE; + + /* unlock the user system data */ + FLASH->usd_unlock = FLASH_UNLOCK_KEY1; + FLASH->usd_unlock = FLASH_UNLOCK_KEY2; + while(FLASH->ctrl_bit.usdulks==RESET); + + FLASH->ctrl_bit.usders = TRUE; + FLASH->ctrl_bit.erstr = TRUE; + /* wait for operation to be completed */ status = flash_operation_wait_for(ERASE_TIMEOUT); + + /* disable the usders bit */ + FLASH->ctrl_bit.usders = FALSE; + if(status == FLASH_OPERATE_DONE) { - /* unlock the user system data */ - FLASH->usd_unlock = FLASH_UNLOCK_KEY1; - FLASH->usd_unlock = FLASH_UNLOCK_KEY2; - while(FLASH->ctrl_bit.usdulks==RESET); - - FLASH->ctrl_bit.usders = TRUE; - FLASH->ctrl_bit.erstr = TRUE; - /* wait for operation to be completed */ - status = flash_operation_wait_for(ERASE_TIMEOUT); - - /* disable the usders bit */ - FLASH->ctrl_bit.usders = FALSE; - - if(status == FLASH_OPERATE_DONE) + if(new_state == FALSE) { - if(new_state == FALSE) - { - /* enable the user system data programming operation */ - FLASH->ctrl_bit.usdprgm = TRUE; - USD->fap = FAP_RELIEVE_KEY; + /* enable the user system data programming operation */ + FLASH->ctrl_bit.usdprgm = TRUE; + USD->fap = FAP_RELIEVE_KEY; - /* Wait for operation to be completed */ - status = flash_operation_wait_for(ERASE_TIMEOUT); + /* wait for operation to be completed */ + status = flash_operation_wait_for(ERASE_TIMEOUT); - /* disable the usdprgm bit */ - FLASH->ctrl_bit.usdprgm = FALSE; - } + /* disable the usdprgm bit */ + FLASH->ctrl_bit.usdprgm = FALSE; } } + /* return the flash access protection operation status */ return status; } @@ -1050,26 +964,22 @@ flag_status flash_fap_status_get(void) flash_status_type flash_ssb_set(uint8_t usd_ssb) { flash_status_type status = FLASH_OPERATE_DONE; - /* wait for last operation to be completed */ + + /* unlock the user system data */ + FLASH->usd_unlock = FLASH_UNLOCK_KEY1; + FLASH->usd_unlock = FLASH_UNLOCK_KEY2; + while(FLASH->ctrl_bit.usdulks==RESET); + + /* enable the user system data programming operation */ + FLASH->ctrl_bit.usdprgm = TRUE; + + USD->ssb = usd_ssb; + /* wait for operation to be completed */ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* unlock the user system data */ - FLASH->usd_unlock = FLASH_UNLOCK_KEY1; - FLASH->usd_unlock = FLASH_UNLOCK_KEY2; - while(FLASH->ctrl_bit.usdulks==RESET); + /* disable the usdprgm bit */ + FLASH->ctrl_bit.usdprgm = FALSE; - /* enable the user system data programming operation */ - FLASH->ctrl_bit.usdprgm = TRUE; - - USD->ssb = usd_ssb; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - - /* disable the usdprgm bit */ - FLASH->ctrl_bit.usdprgm = FALSE; - } /* return the user system data program status */ return status; } @@ -1126,6 +1036,9 @@ void flash_interrupt_enable(uint32_t flash_int, confirm_state new_state) void flash_spim_model_select(flash_spim_model_type mode) { FLASH->select = mode; + + /* dummy read */ + flash_spim_dummy_read(); } /** @@ -1140,6 +1053,62 @@ void flash_spim_encryption_range_set(uint32_t decode_address) FLASH->da = decode_address; } +/** + * @brief operate the flash spim dummy read. + * @param none + * @retval none + */ +void flash_spim_dummy_read(void) +{ + UNUSED(*(__IO uint32_t*)FLASH_SPIM_START_ADDR); + UNUSED(*(__IO uint32_t*)(FLASH_SPIM_START_ADDR + 0x1000)); + UNUSED(*(__IO uint32_t*)(FLASH_SPIM_START_ADDR + 0x2000)); +} + +/** + * @brief mass program for flash spim. + * @param address: specifies the start address to be programmed, word or halfword alignment is recommended. + * @param buf: specifies the pointer of data to be programmed. + * @param cnt: specifies the data counter to be programmed. + * @retval status: the returned value can be: FLASH_PROGRAM_ERROR, + * FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT. + */ +flash_status_type flash_spim_mass_program(uint32_t address, uint8_t *buf, uint32_t cnt) +{ + flash_status_type status = FLASH_OPERATE_DONE; + uint32_t index, temp_offset; + if(address >= FLASH_SPIM_START_ADDR) + { + temp_offset = cnt % 4; + if((temp_offset != 0) && (temp_offset != 2)) + return status; + + FLASH->ctrl3_bit.fprgm = TRUE; + for(index = 0; index < cnt / 4; index++) + { + *(__IO uint32_t*)(address + index * 4) = *(uint32_t*)(buf + index * 4); + /* wait for operation to be completed */ + status = flash_spim_operation_wait_for(SPIM_PROGRAMMING_TIMEOUT); + if(status != FLASH_OPERATE_DONE) + return status; + } + if(temp_offset == 2) + { + *(__IO uint16_t*)(address + index * 4) = *(uint16_t*)(buf + index * 4); + /* wait for operation to be completed */ + status = flash_spim_operation_wait_for(SPIM_PROGRAMMING_TIMEOUT); + } + /* disable the fprgm bit */ + FLASH->ctrl3_bit.fprgm = FALSE; + + /* dummy read */ + flash_spim_dummy_read(); + } + + /* return the program status */ + return status; +} + /** * @brief enable security library function. * @param pwd: slib password @@ -1153,27 +1122,25 @@ flash_status_type flash_slib_enable(uint32_t pwd, uint16_t start_sector, uint16_ { uint32_t slib_range; flash_status_type status = FLASH_OPERATE_DONE; - /* wait for last operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); /*check range param limits*/ if((start_sector>=data_start_sector) || ((data_start_sector > end_sector) && \ (data_start_sector != 0x7FF)) || (start_sector > end_sector)) return FLASH_PROGRAM_ERROR; + /* unlock slib cfg register */ + FLASH->slib_unlock = SLIB_UNLOCK_KEY; + while(FLASH->slib_misc_sts_bit.slib_ulkf==RESET); + + slib_range = ((uint32_t)(data_start_sector << 11) & FLASH_SLIB_DATA_START_SECTOR) | \ + ((uint32_t)(end_sector << 22) & FLASH_SLIB_END_SECTOR) | \ + (start_sector & FLASH_SLIB_START_SECTOR); + /* configure slib, set pwd and range */ + FLASH->slib_set_pwd = pwd; + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); + FLASH->slib_set_range = slib_range; if(status == FLASH_OPERATE_DONE) { - /* unlock slib cfg register */ - FLASH->slib_unlock = SLIB_UNLOCK_KEY; - while(FLASH->slib_misc_sts_bit.slib_ulkf==RESET); - - slib_range = ((uint32_t)(data_start_sector << 11) & FLASH_SLIB_DATA_START_SECTOR) | \ - ((uint32_t)(end_sector << 22) & FLASH_SLIB_END_SECTOR) | \ - (start_sector & FLASH_SLIB_START_SECTOR); - /* configure slib, set pwd and range */ - FLASH->slib_set_pwd = pwd; - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - FLASH->slib_set_range = slib_range; status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); } return status; @@ -1239,7 +1206,7 @@ uint16_t flash_slib_start_sector_get(void) * @param none * @retval uint16_t */ -uint16_t flash_slib_datstart_sector_get(void) +uint16_t flash_slib_datastart_sector_get(void) { return (uint16_t)FLASH->slib_sts1_bit.slib_dat_ss; } diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_gpio.c b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_gpio.c index fbff02dd12..0803b4a4eb 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_gpio.c +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_gpio.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_gpio.c - * @version v2.0.9 - * @date 2022-04-25 * @brief contains all the functions for the gpio firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -390,7 +388,7 @@ void gpio_bits_write(gpio_type *gpio_x, uint16_t pins, confirm_state bit_state) * @param port_value: specifies the value to be written to the port output data register. * @retval none */ -void gpio_port_wirte(gpio_type *gpio_x, uint16_t port_value) +void gpio_port_write(gpio_type *gpio_x, uint16_t port_value) { gpio_x->odt = port_value; } diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_i2c.c b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_i2c.c index 8a55b48b3d..aa37679aaf 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_i2c.c +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_i2c.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_i2c.c - * @version v2.0.9 - * @date 2022-04-25 * @brief contains all the functions for the i2c firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -605,6 +603,85 @@ flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag) } } +/** + * @brief get interrupt flag status + * @param i2c_x: to select the i2c peripheral. + * this parameter can be one of the following values: + * I2C1, I2C2, I2C3. + * @param flag + * this parameter can be one of the following values: + * - I2C_STARTF_FLAG: start condition generation complete flag. + * - I2C_ADDR7F_FLAG: 0~7 bit address match flag. + * - I2C_TDC_FLAG: transmit data complete flag. + * - I2C_ADDRHF_FLAG: master 9~8 bit address header match flag. + * - I2C_STOPF_FLAG: stop condition generation complete flag. + * - I2C_RDBF_FLAG: receive data buffer full flag. + * - I2C_TDBE_FLAG: transmit data buffer empty flag. + * - I2C_BUSERR_FLAG: bus error flag. + * - I2C_ARLOST_FLAG: arbitration lost flag. + * - I2C_ACKFAIL_FLAG: acknowledge failure flag. + * - I2C_OUF_FLAG: overflow or underflow flag. + * - I2C_PECERR_FLAG: pec receive error flag. + * - I2C_TMOUT_FLAG: smbus timeout flag. + * - I2C_ALERTF_FLAG: smbus alert flag. + * @retval flag_status (SET or RESET) + */ +flag_status i2c_interrupt_flag_get(i2c_type *i2c_x, uint32_t flag) +{ + __IO uint32_t reg = 0, value = 0, iten = 0; + + switch(flag) + { + case I2C_STARTF_FLAG: + case I2C_ADDR7F_FLAG: + case I2C_TDC_FLAG: + case I2C_ADDRHF_FLAG: + case I2C_STOPF_FLAG: + iten = i2c_x->ctrl2_bit.evtien; + break; + case I2C_RDBF_FLAG: + case I2C_TDBE_FLAG: + iten = i2c_x->ctrl2_bit.dataien && i2c_x->ctrl2_bit.evtien; + break; + case I2C_BUSERR_FLAG: + case I2C_ARLOST_FLAG: + case I2C_ACKFAIL_FLAG: + case I2C_OUF_FLAG: + case I2C_PECERR_FLAG: + case I2C_TMOUT_FLAG: + case I2C_ALERTF_FLAG: + iten = i2c_x->ctrl2_bit.errien; + break; + + default: + break; + } + + reg = flag >> 28; + + flag &= (uint32_t)0x00FFFFFF; + + if(reg == 0) + { + value = i2c_x->sts1; + } + else + { + flag = (uint32_t)(flag >> 16); + + value = i2c_x->sts2; + } + + if(((value & flag) != (uint32_t)RESET) && (iten)) + { + return SET; + } + else + { + return RESET; + } +} + /** * @brief clear flag status * @param i2c_x: to select the i2c peripheral. @@ -619,11 +696,23 @@ flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag) * - I2C_PECERR_FLAG: pec receive error flag. * - I2C_TMOUT_FLAG: smbus timeout flag. * - I2C_ALERTF_FLAG: smbus alert flag. + * - I2C_STOPF_FLAG: stop condition generation complete flag. + * - I2C_ADDR7F_FLAG: i2c 0~7 bit address match flag. * @retval none */ void i2c_flag_clear(i2c_type *i2c_x, uint32_t flag) { - i2c_x->sts1 = (uint16_t)~(flag & (uint32_t)0x00FFFFFF); + i2c_x->sts1 = (uint16_t)~(flag & (uint32_t)0x0000DF00); + + if(i2c_x->sts1 & I2C_ADDR7F_FLAG) + { + UNUSED(i2c_x->sts2); + } + + if(i2c_x->sts1 & I2C_STOPF_FLAG) + { + i2c_x->ctrl1_bit.i2cen = TRUE; + } } /** diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_misc.c b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_misc.c index 25b34c1253..9691a8b0e9 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_misc.c +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_misc.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_misc.c - * @version v2.0.9 - * @date 2022-04-25 * @brief contains all the functions for the misc firmware library ************************************************************************** * Copyright notice & Disclaimer diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_pwc.c b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_pwc.c index fc945a9cf3..da9989a9e8 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_pwc.c +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_pwc.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_pwc.c - * @version v2.0.9 - * @date 2022-04-25 * @brief contains all the functions for the pwc firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -228,7 +226,10 @@ void pwc_standby_mode_enter(void) #if defined (__CC_ARM) __force_stores(); #endif - __WFI(); + while(1) + { + __WFI(); + } } /** diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_rtc.c b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_rtc.c index f6f453cdfb..1573b891b9 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_rtc.c +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_rtc.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_rtc.c - * @version v2.0.9 - * @date 2022-04-25 * @brief contains all the functions for the rtc firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -76,7 +74,7 @@ uint32_t rtc_counter_get(void) /** * @brief rtc divider set - * @param div_value (0x0000_0000 ~ 0xFFFF_FFFF) + * @param div_value (0x0000_0000 ~ 0x000F_FFFF) * @retval none */ void rtc_divider_set(uint32_t div_value) @@ -174,6 +172,31 @@ flag_status rtc_flag_get(uint16_t flag) return status; } +/** + * @brief rtc interrupt flag get + * @param flag + * this parameter can be one of the following values: + * - RTC_TS_FLAG: time second flag. + * - RTC_TA_FLAG: time alarm flag. + * - RTC_OVF_FLAG: overflow flag. + * @retval state of rtc flag + */ +flag_status rtc_interrupt_flag_get(uint16_t flag) +{ + flag_status status = RESET; + + if (((RTC->ctrll & flag) != (uint16_t)RESET) && ((RTC->ctrlh & flag) != (uint16_t)RESET)) + { + status = SET; + } + else + { + status = RESET; + } + + return status; +} + /** * @brief rtc flag clear * @param interrupt_flag @@ -181,7 +204,7 @@ flag_status rtc_flag_get(uint16_t flag) * - RTC_TS_FLAG: time second flag. * - RTC_TA_FLAG: time alarm flag. * - RTC_OVF_FLAG: overflow flag. - * - RTC_CFGF_FLAG: rtc configuration finish flag. + * - RTC_UPDF_FLAG: rtc update finish flag. * @retval none */ void rtc_flag_clear(uint16_t flag) diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_sdio.c b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_sdio.c index 8b66019283..55edf374c9 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_sdio.c +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_sdio.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_sdio.c - * @version v2.0.9 - * @date 2022-04-25 * @brief contains all the functions for the sdio firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -82,22 +80,11 @@ void sdio_power_set(sdio_type *sdio_x, sdio_power_state_type power_state) * @param sdio_x: to select the sdio peripheral. * this parameter can be one of the following values: * SDIO1, SDIO2. - * @retval flag_status (SET or RESET) + * @retval sdio_power_state_type (SDIO_POWER_ON or SDIO_POWER_OFF) */ -flag_status sdio_power_status_get(sdio_type *sdio_x) +sdio_power_state_type sdio_power_status_get(sdio_type *sdio_x) { - flag_status flag = RESET; - - if(sdio_x->pwrctrl_bit.ps == SDIO_POWER_ON) - { - flag = SET; - } - else if(sdio_x->pwrctrl_bit.ps == SDIO_POWER_OFF) - { - flag = RESET; - } - - return flag; + return (sdio_power_state_type)(sdio_x->pwrctrl_bit.ps); } /** @@ -254,6 +241,50 @@ void sdio_interrupt_enable(sdio_type *sdio_x, uint32_t int_opt, confirm_state n } } +/** + * @brief get sdio interrupt flag. + * @param sdio_x: to select the sdio peripheral. + * this parameter can be one of the following values: + * SDIO1, SDIO2. + * @param flag + * this parameter can be one of the following values: + * - SDIO_CMDFAIL_FLAG + * - SDIO_DTFAIL_FLAG + * - SDIO_CMDTIMEOUT_FLAG + * - SDIO_DTTIMEOUT_FLAG + * - SDIO_TXERRU_FLAG + * - SDIO_RXERRO_FLAG + * - SDIO_CMDRSPCMPL_FLAG + * - SDIO_CMDCMPL_FLAG + * - SDIO_DTCMPL_FLAG + * - SDIO_SBITERR_FLAG + * - SDIO_DTBLKCMPL_FLAG + * - SDIO_DOCMD_FLAG + * - SDIO_DOTX_FLAG + * - SDIO_DORX_FLAG + * - SDIO_TXBUFH_FLAG + * - SDIO_RXBUFH_FLAG + * - SDIO_TXBUFF_FLAG + * - SDIO_RXBUFF_FLAG + * - SDIO_TXBUFE_FLAG + * - SDIO_RXBUFE_FLAG + * - SDIO_TXBUF_FLAG + * - SDIO_RXBUF_FLAG + * - SDIO_SDIOIF_FLAG + * @retval flag_status (SET or RESET) + */ +flag_status sdio_interrupt_flag_get(sdio_type *sdio_x, uint32_t flag) +{ + flag_status status = RESET; + + if((sdio_x->inten & flag) && (sdio_x->sts & flag)) + { + status = SET; + } + + return status; +} + /** * @brief get sdio flag. * @param sdio_x: to select the sdio peripheral. diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_spi.c b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_spi.c index 720aa92117..489050c176 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_spi.c +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_spi.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_spi.c - * @version v2.0.9 - * @date 2022-04-25 * @brief contains all the functions for the spi firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -441,7 +439,7 @@ void i2s_init(spi_type* spi_x, i2s_init_type* i2s_init_struct) * @brief enable or disable i2s. * @param spi_x: select the i2s peripheral. * this parameter can be one of the following values: - * SPI1, SPI2, SPI3 ,SPI4 + * SPI1, SPI2, SPI3 ,SPI4, I2S2EXT, I2S3EXT * @param new_state: new state of i2s. * this parameter can be: TRUE or FALSE. * @retval none @@ -455,7 +453,7 @@ void i2s_enable(spi_type* spi_x, confirm_state new_state) * @brief enable or disable the specified spi/i2s interrupts. * @param spi_x: select the spi/i2s peripheral. * this parameter can be one of the following values: - * SPI1, SPI2, SPI3 ,SPI4 + * SPI1, SPI2, SPI3 ,SPI4, I2S2EXT, I2S3EXT * @param spi_i2s_int: specifies the spi/i2s interrupt sources to be enabled or disabled. * this parameter can be one of the following values: * - SPI_I2S_ERROR_INT @@ -481,7 +479,7 @@ void spi_i2s_interrupt_enable(spi_type* spi_x, uint32_t spi_i2s_int, confirm_sta * @brief enable or disable the spi/i2s dma transmitter mode. * @param spi_x: select the spi/i2s peripheral. * this parameter can be one of the following values: - * SPI1, SPI2, SPI3 ,SPI4 + * SPI1, SPI2, SPI3 ,SPI4, I2S2EXT, I2S3EXT * @param new_state: new state of the dma request. * this parameter can be: TRUE or FALSE. * @retval none @@ -495,7 +493,7 @@ void spi_i2s_dma_transmitter_enable(spi_type* spi_x, confirm_state new_state) * @brief enable or disable the spi/i2s dma receiver mode. * @param spi_x: select the spi/i2s peripheral. * this parameter can be one of the following values: - * SPI1, SPI2, SPI3 ,SPI4 + * SPI1, SPI2, SPI3 ,SPI4, I2S2EXT, I2S3EXT * @param new_state: new state of the dma request. * this parameter can be: TRUE or FALSE. * @retval none @@ -509,7 +507,7 @@ void spi_i2s_dma_receiver_enable(spi_type* spi_x, confirm_state new_state) * @brief spi/i2s data transmit * @param spi_x: select the spi/i2s peripheral. * this parameter can be one of the following values: - * SPI1, SPI2, SPI3 ,SPI4 + * SPI1, SPI2, SPI3 ,SPI4, I2S2EXT, I2S3EXT * @param tx_data: the data to be transmit. * this parameter can be: * - (0x0000~0xFFFF) @@ -524,7 +522,7 @@ void spi_i2s_data_transmit(spi_type* spi_x, uint16_t tx_data) * @brief spi/i2s data receive * @param spi_x: select the spi/i2s peripheral. * this parameter can be one of the following values: - * SPI1, SPI2, SPI3 ,SPI4 + * SPI1, SPI2, SPI3 ,SPI4, I2S2EXT, I2S3EXT * @retval the received data value */ uint16_t spi_i2s_data_receive(spi_type* spi_x) @@ -536,7 +534,7 @@ uint16_t spi_i2s_data_receive(spi_type* spi_x) * @brief get flag of the specified spi/i2s peripheral. * @param spi_x: select the spi/i2s peripheral. * this parameter can be one of the following values: - * SPI1, SPI2, SPI3 ,SPI4 + * SPI1, SPI2, SPI3 ,SPI4, I2S2EXT, I2S3EXT * @param spi_i2s_flag: select the spi/i2s flag * this parameter can be one of the following values: * - SPI_I2S_RDBF_FLAG @@ -563,11 +561,74 @@ flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag) return status; } +/** + * @brief get interrupt flag of the specified spi/i2s peripheral. + * @param spi_x: select the spi/i2s peripheral. + * this parameter can be one of the following values: + * SPI1, SPI2, SPI3 ,SPI4, I2S2EXT, I2S3EXT + * @param spi_i2s_flag: select the spi/i2s flag + * this parameter can be one of the following values: + * - SPI_I2S_RDBF_FLAG + * - SPI_I2S_TDBE_FLAG + * - I2S_TUERR_FLAG (this flag only use in i2s mode) + * - SPI_CCERR_FLAG (this flag only use in spi mode) + * - SPI_MMERR_FLAG (this flag only use in spi mode) + * - SPI_I2S_ROERR_FLAG + * @retval the new state of spi/i2s flag + */ +flag_status spi_i2s_interrupt_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag) +{ + flag_status status = RESET; + + switch(spi_i2s_flag) + { + case SPI_I2S_RDBF_FLAG: + if(spi_x->sts_bit.rdbf && spi_x->ctrl2_bit.rdbfie) + { + status = SET; + } + break; + case SPI_I2S_TDBE_FLAG: + if(spi_x->sts_bit.tdbe && spi_x->ctrl2_bit.tdbeie) + { + status = SET; + } + break; + case I2S_TUERR_FLAG: + if(spi_x->sts_bit.tuerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_CCERR_FLAG: + if(spi_x->sts_bit.ccerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_MMERR_FLAG: + if(spi_x->sts_bit.mmerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_I2S_ROERR_FLAG: + if(spi_x->sts_bit.roerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + default: + break; + }; + return status; +} + /** * @brief clear flag of the specified spi/i2s peripheral. * @param spi_x: select the spi/i2s peripheral. * this parameter can be one of the following values: - * SPI1, SPI2, SPI3 ,SPI4 + * SPI1, SPI2, SPI3 ,SPI4, I2S2EXT, I2S3EXT * @param spi_i2s_flag: select the spi/i2s flag * this parameter can be one of the following values: * - SPI_CCERR_FLAG @@ -583,23 +644,21 @@ flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag) */ void spi_i2s_flag_clear(spi_type* spi_x, uint32_t spi_i2s_flag) { - volatile uint32_t temp = 0; - temp = temp; if(spi_i2s_flag == SPI_CCERR_FLAG) spi_x->sts = ~SPI_CCERR_FLAG; else if(spi_i2s_flag == SPI_I2S_RDBF_FLAG) - temp = REG32(&spi_x->dt); + UNUSED(spi_x->dt); else if(spi_i2s_flag == I2S_TUERR_FLAG) - temp = REG32(&spi_x->sts); + UNUSED(spi_x->sts); else if(spi_i2s_flag == SPI_MMERR_FLAG) { - temp = REG32(&spi_x->sts); + UNUSED(spi_x->sts); spi_x->ctrl1 = spi_x->ctrl1; } else if(spi_i2s_flag == SPI_I2S_ROERR_FLAG) { - temp = REG32(&spi_x->dt); - temp = REG32(&spi_x->sts); + UNUSED(spi_x->dt); + UNUSED(spi_x->sts); } } diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_tmr.c b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_tmr.c index e92df95008..94e6e63f5c 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_tmr.c +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_tmr.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_tmr.c - * @version v2.0.9 - * @date 2022-04-25 * @brief contains all the functions for the tmr firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -260,11 +258,7 @@ void tmr_cnt_dir_set(tmr_type *tmr_x, tmr_count_mode_type tmr_cnt_dir) void tmr_repetition_counter_set(tmr_type *tmr_x, uint8_t tmr_rpr_value) { /* set the repetition counter value */ - if((tmr_x == TMR1) || (tmr_x == TMR8)) - - { - tmr_x->rpr_bit.rpr = tmr_rpr_value; - } + tmr_x->rpr_bit.rpr = tmr_rpr_value; } /** @@ -302,8 +296,7 @@ uint32_t tmr_counter_value_get(tmr_type *tmr_x) * this parameter can be one of the following values: * TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8, * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14 - * @param tmr_div_value (for 16 bit tmr 0x0000~0xFFFF, - * for 32 bit tmr 0x0000_0000~0xFFFF_FFFF) + * @param tmr_div_value (0x0000~0xFFFF) * @retval none */ void tmr_div_value_set(tmr_type *tmr_x, uint32_t tmr_div_value) @@ -344,23 +337,23 @@ uint32_t tmr_div_value_get(tmr_type *tmr_x) void tmr_output_channel_config(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, tmr_output_config_type *tmr_output_struct) { - uint16_t channel_index = 0, channel_c_index = 0, channel = 0; + uint16_t channel_index = 0, channel_c_index = 0, channel = 0, chx_offset, chcx_offset; + + chx_offset = (8 + tmr_channel); + chcx_offset = (9 + tmr_channel); /* get channel idle state bit position in ctrl2 register */ - channel_index = (uint16_t)(tmr_output_struct->oc_idle_state << (8 + tmr_channel)); + channel_index = (uint16_t)(tmr_output_struct->oc_idle_state << chx_offset); /* get channel complementary idle state bit position in ctrl2 register */ - channel_c_index = (uint16_t)(tmr_output_struct->occ_idle_state << (9 + tmr_channel)); + channel_c_index = (uint16_t)(tmr_output_struct->occ_idle_state << chcx_offset); - if((tmr_x == TMR1) || (tmr_x == TMR8)) - { - /* set output channel complementary idle state */ - tmr_x->ctrl2 &= ~channel_c_index; - tmr_x->ctrl2 |= channel_c_index; - } + /* set output channel complementary idle state */ + tmr_x->ctrl2 &= ~(1<ctrl2 |= channel_c_index; /* set output channel idle state */ - tmr_x->ctrl2 &= ~channel_index; + tmr_x->ctrl2 &= ~(1<ctrl2 |= channel_index; /* set channel output mode */ @@ -388,38 +381,38 @@ void tmr_output_channel_config(tmr_type *tmr_x, tmr_channel_select_type tmr_chan break; } + chx_offset = ((tmr_channel * 2) + 1); + chcx_offset = ((tmr_channel * 2) + 3); + /* get channel polarity bit position in cctrl register */ - channel_index = (uint16_t)(tmr_output_struct->oc_polarity << ((tmr_channel * 2) + 1)); + channel_index = (uint16_t)(tmr_output_struct->oc_polarity << chx_offset); /* get channel complementary polarity bit position in cctrl register */ - channel_c_index = (uint16_t)(tmr_output_struct->occ_polarity << ((tmr_channel * 2) + 3)); + channel_c_index = (uint16_t)(tmr_output_struct->occ_polarity << chcx_offset); - if((tmr_x == TMR1) || (tmr_x == TMR8)) - { - /* set output channel complementary polarity */ - tmr_x->cctrl &= ~channel_c_index; - tmr_x->cctrl |= channel_c_index; - } + /* set output channel complementary polarity */ + tmr_x->cctrl &= ~(1<cctrl |= channel_c_index; /* set output channel polarity */ - tmr_x->cctrl &= ~channel_index; + tmr_x->cctrl &= ~(1<cctrl |= channel_index; + chx_offset = (tmr_channel * 2); + chcx_offset = ((tmr_channel * 2) + 2); + /* get channel enable bit position in cctrl register */ channel_index = (uint16_t)(tmr_output_struct->oc_output_state << (tmr_channel * 2)); /* get channel complementary enable bit position in cctrl register */ channel_c_index = (uint16_t)(tmr_output_struct->occ_output_state << ((tmr_channel * 2) + 2)); - if((tmr_x == TMR1) || (tmr_x == TMR8)) - { - /* set output channel complementary enable bit */ - tmr_x->cctrl &= ~channel_c_index; - tmr_x->cctrl |= channel_c_index; - } + /* set output channel complementary enable bit */ + tmr_x->cctrl &= ~(1<cctrl |= channel_c_index; /* set output channel enable bit */ - tmr_x->cctrl &= ~channel_index; + tmr_x->cctrl &= ~(1<cctrl |= channel_index; } @@ -758,7 +751,8 @@ void tmr_output_channel_switch_set(tmr_type *tmr_x, tmr_channel_select_type tmr_ * @brief enable or disable tmr one cycle mode * @param tmr_x: select the tmr peripheral. * this parameter can be one of the following values: - * TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8, TMR9, TMR12 + * TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8, + * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14 * @param new_state (TRUE or FALSE) * @retval none */ @@ -840,6 +834,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct switch(channel) { case TMR_SELECT_CHANNEL_1: + tmr_x->cctrl_bit.c1en = FALSE; tmr_x->cctrl_bit.c1p = (uint32_t)input_struct->input_polarity_select; tmr_x->cctrl_bit.c1cp = (input_struct->input_polarity_select & 0x2) >> 1; tmr_x->cm1_input_bit.c1c = input_struct->input_mapped_select; @@ -849,6 +844,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct break; case TMR_SELECT_CHANNEL_2: + tmr_x->cctrl_bit.c2en = FALSE; tmr_x->cctrl_bit.c2p = (uint32_t)input_struct->input_polarity_select; tmr_x->cctrl_bit.c2cp = (input_struct->input_polarity_select & 0x2) >> 1; tmr_x->cm1_input_bit.c2c = input_struct->input_mapped_select; @@ -858,6 +854,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct break; case TMR_SELECT_CHANNEL_3: + tmr_x->cctrl_bit.c3en = FALSE; tmr_x->cctrl_bit.c3p = (uint32_t)input_struct->input_polarity_select; tmr_x->cctrl_bit.c3cp = (input_struct->input_polarity_select & 0x2) >> 1; tmr_x->cm2_input_bit.c3c = input_struct->input_mapped_select; @@ -867,6 +864,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct break; case TMR_SELECT_CHANNEL_4: + tmr_x->cctrl_bit.c4en = FALSE; tmr_x->cctrl_bit.c4p = (uint32_t)input_struct->input_polarity_select; tmr_x->cm2_input_bit.c4c = input_struct->input_mapped_select; tmr_x->cm2_input_bit.c4df = input_struct->input_filter_value; @@ -1101,15 +1099,15 @@ void tmr_pwm_input_config(tmr_type *tmr_x, tmr_input_config_type *input_struct, * @param tmr_x: select the tmr peripheral. * this parameter can be one of the following values: * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8 - * @param ti1_connect + * @param ch1_connect * this parameter can be one of the following values: * - TMR_CHANEL1_CONNECTED_C1IRAW * - TMR_CHANEL1_2_3_CONNECTED_C1IRAW_XOR * @retval none */ -void tmr_channel1_input_select(tmr_type *tmr_x, tmr_channel1_input_connected_type ti1_connect) +void tmr_channel1_input_select(tmr_type *tmr_x, tmr_channel1_input_connected_type ch1_connect) { - tmr_x->ctrl2_bit.c1insel = ti1_connect; + tmr_x->ctrl2_bit.c1insel = ch1_connect; } /** @@ -1207,7 +1205,7 @@ void tmr_sub_mode_select(tmr_type *tmr_x, tmr_sub_mode_select_type sub_mode) } /** - * @brief select tmr channel dma + * @brief select tmr channel dma request source * @param tmr_x: select the tmr peripheral. * this parameter can be one of the following values: * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR12 @@ -1344,6 +1342,40 @@ void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state } } +/** + * @brief get tmr interrupt flag + * @param tmr_x: select the tmr peripheral. + * this parameter can be one of the following values: + * TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8, + * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14 + * @param tmr_flag + * this parameter can be one of the following values: + * - TMR_OVF_FLAG + * - TMR_C1_FLAG + * - TMR_C2_FLAG + * - TMR_C3_FLAG + * - TMR_C4_FLAG + * - TMR_HALL_FLAG + * - TMR_TRIGGER_FLAG + * - TMR_BRK_FLAG + * @retval state of tmr interrupt flag + */ +flag_status tmr_interrupt_flag_get(tmr_type *tmr_x, uint32_t tmr_flag) +{ + flag_status status = RESET; + + if((tmr_x->ists & tmr_flag) && (tmr_x->iden & tmr_flag)) + { + status = SET; + } + else + { + status = RESET; + } + + return status; +} + /** * @brief get tmr flag * @param tmr_x: select the tmr peripheral. @@ -1729,7 +1761,7 @@ void tmr_dma_control_config(tmr_type *tmr_x, tmr_dma_transfer_length_type dma_le } /** - * @brief config tmr break mode and dead-time + * @brief config tmr brake mode and dead-time * @param tmr_x: select the tmr peripheral. * this parameter can be one of the following values: * TMR1, TMR8 diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_usart.c b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_usart.c index 2fde5c6780..aff174e4fc 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_usart.c +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_usart.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_usart.c - * @version v2.0.9 - * @date 2022-04-25 * @brief contains all the functions for the usart firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -86,11 +84,14 @@ void usart_reset(usart_type* usart_x) crm_periph_reset(CRM_UART7_PERIPH_RESET, TRUE); crm_periph_reset(CRM_UART7_PERIPH_RESET, FALSE); } +#if defined (AT32F403ARx) || defined (AT32F403AVx) || defined (AT32F407Rx) || \ + defined (AT32F407Vx) else if(usart_x == UART8) { crm_periph_reset(CRM_UART8_PERIPH_RESET, TRUE); crm_periph_reset(CRM_UART8_PERIPH_RESET, FALSE); } +#endif } /** @@ -103,6 +104,9 @@ void usart_reset(usart_type* usart_x) * this parameter can be one of the following values: * - USART_DATA_8BITS * - USART_DATA_9BITS. + * note: + * - when parity check is disabled, the data bit width is the actual data bit number. + * - when parity check is enabled, the data bit width is the actual data bit number minus 1, and the MSB bit is replaced with the parity bit. * @param stop_bit: stop bits transmitted * this parameter can be one of the following values: * - USART_STOP_1_BIT @@ -116,7 +120,12 @@ void usart_init(usart_type* usart_x, uint32_t baud_rate, usart_data_bit_num_type crm_clocks_freq_type clocks_freq; uint32_t apb_clock, temp_val; crm_clocks_freq_get(&clocks_freq); - if((usart_x == USART1) || (usart_x == USART6) || (usart_x == UART7) || (usart_x == UART8)) + if((usart_x == USART1) || (usart_x == USART6) || (usart_x == UART7) +#if defined (AT32F403ARx) || defined (AT32F403AVx) || defined (AT32F407Rx) || \ + defined (AT32F407Vx) + || (usart_x == UART8) +#endif + ) { apb_clock = clocks_freq.apb2_freq; } @@ -583,6 +592,79 @@ flag_status usart_flag_get(usart_type* usart_x, uint32_t flag) } } +/** + * @brief check whether the specified usart interrupt flag is set or not. + * @param usart_x: select the usart or the uart peripheral. + * this parameter can be one of the following values: + * USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8. + * @param flag: specifies the flag to check. + * this parameter can be one of the following values: + * - USART_CTSCF_FLAG: cts change flag (not available for UART4,UART5) + * - USART_BFF_FLAG: break frame flag + * - USART_TDBE_FLAG: transmit data buffer empty flag + * - USART_TDC_FLAG: transmit data complete flag + * - USART_RDBF_FLAG: receive data buffer full flag + * - USART_IDLEF_FLAG: idle flag + * - USART_ROERR_FLAG: receiver overflow error flag + * - USART_NERR_FLAG: noise error flag + * - USART_FERR_FLAG: framing error flag + * - USART_PERR_FLAG: parity error flag + * @retval the new state of usart_flag (SET or RESET). + */ +flag_status usart_interrupt_flag_get(usart_type* usart_x, uint32_t flag) +{ + flag_status int_status = RESET; + + switch(flag) + { + case USART_CTSCF_FLAG: + int_status = (flag_status)usart_x->ctrl3_bit.ctscfien; + break; + case USART_BFF_FLAG: + int_status = (flag_status)usart_x->ctrl2_bit.bfien; + break; + case USART_TDBE_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.tdbeien; + break; + case USART_TDC_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.tdcien; + break; + case USART_RDBF_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.rdbfien; + break; + case USART_ROERR_FLAG: + int_status = (flag_status)(usart_x->ctrl1_bit.rdbfien || usart_x->ctrl3_bit.errien); + break; + case USART_IDLEF_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.idleien; + break; + case USART_NERR_FLAG: + case USART_FERR_FLAG: + int_status = (flag_status)usart_x->ctrl3_bit.errien; + break; + case USART_PERR_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.perrien; + break; + default: + int_status = RESET; + break; + } + + if(int_status != SET) + { + return RESET; + } + + if(usart_x->sts & flag) + { + return SET; + } + else + { + return RESET; + } +} + /** * @brief clear the usart's pending flags. * @param usart_x: select the usart or the uart peripheral. @@ -594,6 +676,11 @@ flag_status usart_flag_get(usart_type* usart_x, uint32_t flag) * - USART_BFF_FLAG: * - USART_TDC_FLAG: * - USART_RDBF_FLAG: + * - USART_PERR_FLAG: + * - USART_FERR_FLAG: + * - USART_NERR_FLAG: + * - USART_ROERR_FLAG: + * - USART_IDLEF_FLAG: * @note * - USART_PERR_FLAG, USART_FERR_FLAG, USART_NERR_FLAG, USART_ROERR_FLAG and USART_IDLEF_FLAG are cleared by software * sequence: a read operation to usart sts register (usart_flag_get()) @@ -606,7 +693,15 @@ flag_status usart_flag_get(usart_type* usart_x, uint32_t flag) */ void usart_flag_clear(usart_type* usart_x, uint32_t flag) { - usart_x->sts = ~flag; + if(flag & (USART_PERR_FLAG | USART_FERR_FLAG | USART_NERR_FLAG | USART_ROERR_FLAG | USART_IDLEF_FLAG)) + { + UNUSED(usart_x->sts); + UNUSED(usart_x->dt); + } + else + { + usart_x->sts = ~flag; + } } /** diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_usb.c b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_usb.c index a177da5657..5f9dddb8b5 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_usb.c +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_usb.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_usb.c - * @version v2.0.9 - * @date 2022-04-25 * @brief contains the functions for the usb firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -133,6 +131,7 @@ void usb_usbbufs_enable(usbd_type *usbx, confirm_state state) g_usb_packet_address = USB_PACKET_BUFFER_ADDRESS; CRM->misc1_bit.usbbufs = FALSE; } + UNUSED(usbx); } /** @@ -251,6 +250,7 @@ void usb_ept_open(usbd_type *usbx, usb_ept_info *ept_info) USB_SET_TXSTS(ept_info->eptn, USB_TX_DISABLE); } } + UNUSED(usbx); } @@ -310,6 +310,7 @@ void usb_ept_close(usbd_type *usbx, usb_ept_info *ept_info) USB_SET_RXSTS(ept_info->eptn, USB_RX_DISABLE); } } + UNUSED(usbx); } /** @@ -424,6 +425,7 @@ void usb_ept_stall(usbd_type *usbx, usb_ept_info *ept_info) { USB_SET_RXSTS(ept_info->eptn, USB_RX_STALL) } + UNUSED(usbx); } /** @@ -525,6 +527,40 @@ flag_status usb_flag_get(usbd_type *usbx, uint16_t flag) return status; } +/** + * @brief get interrupt flag of usb. + * @param usbx: select the usb peripheral + * @param flag: select the usb flag + * this parameter can be one of the following values: + * - USB_LSOF_FLAG + * - USB_SOF_FLAG + * - USB_RST_FLAG + * - USB_SP_FLAG + * - USB_WK_FLAG + * - USB_BE_FLAG + * - USB_UCFOR_FLAG + * - USB_TC_FLAG + * @retval none + */ +flag_status usb_interrupt_flag_get(usbd_type *usbx, uint16_t flag) +{ + flag_status status = RESET; + + if(flag == USB_TC_FLAG) + { + if(usbx->intsts & USB_TC_FLAG) + status = SET; + } + else + { + if((usbx->intsts & flag) && (usbx->ctrl & flag)) + { + status = SET; + } + } + return status; +} + /** * @brief clear flag of usb. * @param usbx: select the usb peripheral diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_wdt.c b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_wdt.c index 782123fbb1..b1c55d483c 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_wdt.c +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_wdt.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_wdt.c - * @version v2.0.9 - * @date 2022-04-25 * @brief contains all the functions for the wdt firmware library ************************************************************************** * Copyright notice & Disclaimer diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_wwdt.c b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_wwdt.c index 8b543852c3..03bb3ffc53 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_wwdt.c +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_wwdt.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_wwdt.c - * @version v2.0.9 - * @date 2022-04-25 * @brief contains all the functions for the wwdt firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -106,6 +104,16 @@ flag_status wwdt_flag_get(void) return (flag_status)WWDT->sts_bit.rldf; } +/** + * @brief wwdt reload counter interrupt flag get + * @param none + * @retval state of reload counter interrupt flag + */ +flag_status wwdt_interrupt_flag_get(void) +{ + return (flag_status)(WWDT->sts_bit.rldf && WWDT->cfg_bit.rldien); +} + /** * @brief wwdt counter value set * @param wwdt_cnt (0x40~0x7f) diff --git a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_xmc.c b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_xmc.c index 6b215e91fa..723e69011f 100644 --- a/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_xmc.c +++ b/bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/src/at32f403a_407_xmc.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f403a_407_xmc.c - * @version v2.0.9 - * @date 2022-04-25 * @brief contains all the functions for the xmc firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -218,9 +216,9 @@ void xmc_nor_sram_enable(xmc_nor_sram_subbank_type xmc_subbank, confirm_state ne * @param r2r_timing :read timing * @retval none */ -void xmc_ext_timing_config(xmc_nor_sram_subbank_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing) +void xmc_ext_timing_config(volatile xmc_nor_sram_subbank_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing) { - XMC_BANK1->ext_bit[xmc_sub_bank].buslatr2r = r2r_timing<<8; + XMC_BANK1->ext_bit[xmc_sub_bank].buslatr2r = r2r_timing; XMC_BANK1->ext_bit[xmc_sub_bank].buslatw2w = w2w_timing; } @@ -470,6 +468,47 @@ flag_status xmc_flag_status_get(xmc_class_bank_type xmc_bank, xmc_interrupt_flag return status; } +/** + * @brief check whether the specified xmc interrupt flag is set or not. + * @param xmc_bank: specifies the xmc bank to be used + * this parameter can be one of the following values: + * - XMC_BANK2_NAND + * @param xmc_flag: specifies the flag to check. + * this parameter can be any combination of the following values: + * - XMC_RISINGEDGE_FLAG + * - XMC_LEVEL_FLAG + * - XMC_FALLINGEDGE_FLAG + * @retval none + */ +flag_status xmc_interrupt_flag_status_get(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag) +{ + flag_status status = RESET; + + switch(xmc_flag) + { + case XMC_RISINGEDGE_FLAG: + if(XMC_BANK2->bk2is_bit.reien && XMC_BANK2->bk2is_bit.res) + status = SET; + break; + + case XMC_LEVEL_FLAG: + if(XMC_BANK2->bk2is_bit.feien && XMC_BANK2->bk2is_bit.fes) + status = SET; + break; + + case XMC_FALLINGEDGE_FLAG: + if(XMC_BANK2->bk2is_bit.hlien && XMC_BANK2->bk2is_bit.hls) + status = SET; + break; + + default: + break; + } + + /* return the flag status */ + return status; +} + /** * @brief clear the xmc's pending flags. * @param xmc_bank: specifies the xmc bank to be used diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/cmsis/cm4/device_support/system_at32f413.c b/bsp/at32/libraries/AT32F413_Firmware_Library/cmsis/cm4/device_support/system_at32f413.c index 846d23e5bc..eb042c5b83 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/cmsis/cm4/device_support/system_at32f413.c +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/cmsis/cm4/device_support/system_at32f413.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file system_at32f413.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for cmsis cortex-m4 system source file ************************************************************************** * Copyright notice & Disclaimer diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/cmsis/cm4/device_support/system_at32f413.h b/bsp/at32/libraries/AT32F413_Firmware_Library/cmsis/cm4/device_support/system_at32f413.h index adc9926592..29e3345c66 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/cmsis/cm4/device_support/system_at32f413.h +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/cmsis/cm4/device_support/system_at32f413.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file system_at32f413.h - * @version v2.0.5 - * @date 2022-05-20 * @brief cmsis cortex-m4 system header file. ************************************************************************** * Copyright notice & Disclaimer @@ -45,6 +43,11 @@ extern "C" { #define HEXT_STABLE_DELAY (5000u) #define PLL_STABLE_DELAY (500u) +#define SystemCoreClock system_core_clock +#define DUMMY_NOP() {__NOP();__NOP();__NOP();__NOP();__NOP(); \ + __NOP();__NOP();__NOP();__NOP();__NOP(); \ + __NOP();__NOP();__NOP();__NOP();__NOP(); \ + __NOP();__NOP();__NOP();__NOP();__NOP();} /** * @} diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_acc.h b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_acc.h index 3607e36fb5..1cb8f11316 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_acc.h +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_acc.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_acc.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f413 acc header file ************************************************************************** * Copyright notice & Disclaimer @@ -181,6 +179,7 @@ uint16_t acc_read_c1(void); uint16_t acc_read_c2(void); uint16_t acc_read_c3(void); flag_status acc_flag_get(uint16_t acc_flag); +flag_status acc_interrupt_flag_get(uint16_t acc_flag); void acc_flag_clear(uint16_t acc_flag); /** diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_adc.h b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_adc.h index 2d16d8c1e5..1bf227c404 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_adc.h +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_adc.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_adc.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f413 adc header file ************************************************************************** * Copyright notice & Disclaimer @@ -596,6 +594,7 @@ uint16_t adc_ordinary_conversion_data_get(adc_type *adc_x); uint32_t adc_combine_ordinary_conversion_data_get(void); uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel); flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag); +flag_status adc_interrupt_flag_get(adc_type *adc_x, uint8_t adc_flag); void adc_flag_clear(adc_type *adc_x, uint32_t adc_flag); /** diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_bpr.h b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_bpr.h index c61839a1a3..335f08bc33 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_bpr.h +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_bpr.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_bpr.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f413 bpr header file ************************************************************************** * Copyright notice & Disclaimer @@ -118,9 +116,7 @@ typedef enum BPR_RTC_OUTPUT_CLOCK_CAL_BEFORE = 0x080, /*!< output clock before calibration */ BPR_RTC_OUTPUT_ALARM = 0x100, /*!< output alarm event with pluse mode */ BPR_RTC_OUTPUT_SECOND = 0x300, /*!< output second event with pluse mode */ - BPR_RTC_OUTPUT_CLOCK_CAL_AFTER = 0x480, /*!< output clock after calibration */ - BPR_RTC_OUTPUT_ALARM_TOGGLE = 0x900, /*!< output alarm event with toggle mode */ - BPR_RTC_OUTPUT_SECOND_TOGGLE = 0xB00 /*!< output second event with toggle mode */ + BPR_RTC_OUTPUT_CLOCK_CAL_AFTER = 0x480 /*!< output clock after calibration */ } bpr_rtc_output_type; /** @@ -761,6 +757,7 @@ typedef struct void bpr_reset(void); flag_status bpr_flag_get(uint32_t flag); +flag_status bpr_interrupt_flag_get(uint32_t flag); void bpr_flag_clear(uint32_t flag); void bpr_interrupt_enable(confirm_state new_state); uint16_t bpr_data_read(bpr_data_type bpr_data); diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_can.h b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_can.h index 5ba05a9704..298c4bb8df 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_can.h +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_can.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_can.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f413 can header file ************************************************************************** * Copyright notice & Disclaimer @@ -352,7 +350,7 @@ typedef struct */ typedef struct { - uint16_t baudrate_div; /*!< baudrate division,this parameter can be 0x001~0x400.*/ + uint16_t baudrate_div; /*!< baudrate division,this parameter can be 0x001~0x1000.*/ can_rsaw_type rsaw_size; /*!< resynchronization adjust width */ @@ -936,7 +934,10 @@ typedef struct */ #define CAN1 ((can_type *) CAN1_BASE) +#if defined (AT32F413TBU7) || defined (AT32F413Rx) || defined (AT32F413Cx) || \ + defined (AT32F413Kx) #define CAN2 ((can_type *) CAN2_BASE) +#endif /** @defgroup CAN_exported_functions * @{ @@ -964,6 +965,7 @@ can_error_record_type can_error_type_record_get(can_type* can_x); uint8_t can_receive_error_counter_get(can_type* can_x); uint8_t can_transmit_error_counter_get(can_type* can_x); void can_interrupt_enable(can_type* can_x, uint32_t can_int, confirm_state new_state); +flag_status can_interrupt_flag_get(can_type* can_x, uint32_t can_flag); flag_status can_flag_get(can_type* can_x, uint32_t can_flag); void can_flag_clear(can_type* can_x, uint32_t can_flag); diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_crc.h b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_crc.h index a3372dfd07..93276aae68 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_crc.h +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_crc.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_crc.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f413 crc header file ************************************************************************** * Copyright notice & Disclaimer @@ -68,6 +66,17 @@ typedef enum CRC_REVERSE_OUTPUT_DATA = 0x01 /*!< output data reverse by word */ } crc_reverse_output_type; +/** + * @brief crc polynomial size + */ +typedef enum +{ + CRC_POLY_SIZE_32B = 0x00, /*!< polynomial size 32 bits */ + CRC_POLY_SIZE_16B = 0x01, /*!< polynomial size 16 bits */ + CRC_POLY_SIZE_8B = 0x02, /*!< polynomial size 8 bits */ + CRC_POLY_SIZE_7B = 0x03 /*!< polynomial size 7 bits */ +} crc_poly_size_type; + /** * @brief type define crc register all */ @@ -107,7 +116,8 @@ typedef struct struct { __IO uint32_t rst : 1 ; /* [0] */ - __IO uint32_t reserved1 : 4 ; /* [4:1] */ + __IO uint32_t reserved1 : 2 ; /* [2:1] */ + __IO uint32_t poly_size : 2 ; /* [4:3] */ __IO uint32_t revid : 2 ; /* [6:5] */ __IO uint32_t revod : 1 ; /* [7] */ __IO uint32_t reserved2 : 24 ;/* [31:8] */ @@ -131,6 +141,18 @@ typedef struct } idt_bit; }; + /** + * @brief crc polynomial register, offset:0x14 + */ + union + { + __IO uint32_t poly; + struct + { + __IO uint32_t poly : 32; /* [31:0] */ + } poly_bit; + }; + } crc_type; /** @@ -148,10 +170,14 @@ uint32_t crc_one_word_calculate(uint32_t data); uint32_t crc_block_calculate(uint32_t *pbuffer, uint32_t length); uint32_t crc_data_get(void); void crc_common_data_set(uint8_t cdt_value); -uint8_t crc_common_date_get(void); +uint8_t crc_common_data_get(void); void crc_init_data_set(uint32_t value); void crc_reverse_input_data_set(crc_reverse_input_type value); void crc_reverse_output_data_set(crc_reverse_output_type value); +void crc_poly_value_set(uint32_t value); +uint32_t crc_poly_value_get(void); +void crc_poly_size_set(crc_poly_size_type size); +crc_poly_size_type crc_poly_size_get(void); /** * @} diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_crm.h b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_crm.h index 6cdfba68c4..88a4e7d492 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_crm.h +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_crm.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_crm.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f413 crm header file ************************************************************************** * Copyright notice & Disclaimer @@ -139,7 +137,7 @@ typedef enum CRM_CAN1_PERIPH_CLOCK = MAKE_VALUE(0x1C, 25), /*!< can1 periph clock */ CRM_BPR_PERIPH_CLOCK = MAKE_VALUE(0x1C, 27), /*!< bpr periph clock */ CRM_PWC_PERIPH_CLOCK = MAKE_VALUE(0x1C, 28), /*!< pwc periph clock */ - CRM_CAN2_PERIPH_CLOCK = MAKE_VALUE(0x1C, 31), /*!< can2 periph clock */ + CRM_CAN2_PERIPH_CLOCK = MAKE_VALUE(0x1C, 31) /*!< can2 periph clock */ } crm_periph_clock_type; @@ -183,7 +181,7 @@ typedef enum CRM_CAN1_PERIPH_RESET = MAKE_VALUE(0x10, 25), /*!< can1 periph reset */ CRM_BPR_PERIPH_RESET = MAKE_VALUE(0x10, 27), /*!< bpr periph reset */ CRM_PWC_PERIPH_RESET = MAKE_VALUE(0x10, 28), /*!< pwc periph reset */ - CRM_CAN2_PERIPH_RESET = MAKE_VALUE(0x10, 31), /*!< can2 periph reset */ + CRM_CAN2_PERIPH_RESET = MAKE_VALUE(0x10, 31) /*!< can2 periph reset */ } crm_periph_reset_type; @@ -851,6 +849,7 @@ void crm_reset(void); void crm_lext_bypass(confirm_state new_state); void crm_hext_bypass(confirm_state new_state); flag_status crm_flag_get(uint32_t flag); +flag_status crm_interrupt_flag_get(uint32_t flag); error_status crm_hext_stable_wait(void); void crm_hick_clock_trimming_set(uint8_t trim_value); void crm_hick_clock_calibration_set(uint8_t cali_value); diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_debug.h b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_debug.h index f83cde2342..cfe5b0d24b 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_debug.h +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_debug.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_debug.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f413 debug header file ************************************************************************** * Copyright notice & Disclaimer diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_def.h b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_def.h index a518d683c7..ecb19616bf 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_def.h +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_def.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_def.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f413 macros header file ************************************************************************** * Copyright notice & Disclaimer @@ -62,6 +60,8 @@ extern "C" { #endif #endif +#define UNUSED(x) (void)x /* to avoid gcc/g++ warnings */ + #ifdef __cplusplus } #endif diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_dma.h b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_dma.h index 62b6c6c663..97f1f826fc 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_dma.h +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_dma.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_dma.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f413 dma header file ************************************************************************** * Copyright notice & Disclaimer @@ -507,6 +505,7 @@ void dma_data_number_set(dma_channel_type* dmax_channely, uint16_t data_number); uint16_t dma_data_number_get(dma_channel_type* dmax_channely); void dma_interrupt_enable(dma_channel_type* dmax_channely, uint32_t dma_int, confirm_state new_state); flag_status dma_flag_get(uint32_t dmax_flag); +flag_status dma_interrupt_flag_get(uint32_t dmax_flag); void dma_flag_clear(uint32_t dmax_flag); diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_exint.h b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_exint.h index ff07816442..7c956ab333 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_exint.h +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_exint.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_exint.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f413 exint header file ************************************************************************** * Copyright notice & Disclaimer @@ -206,6 +204,7 @@ void exint_default_para_init(exint_init_type *exint_struct); void exint_init(exint_init_type *exint_struct); void exint_flag_clear(uint32_t exint_line); flag_status exint_flag_get(uint32_t exint_line); +flag_status exint_interrupt_flag_get(uint32_t exint_line); void exint_software_interrupt_event_generate(uint32_t exint_line); void exint_interrupt_enable(uint32_t exint_line, confirm_state new_state); void exint_event_enable(uint32_t exint_line, confirm_state new_state); diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_flash.h b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_flash.h index 790e78b9d6..5c349dcee5 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_flash.h +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_flash.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_flash.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f413 flash header file ************************************************************************** * Copyright notice & Disclaimer @@ -170,7 +168,7 @@ typedef enum typedef enum { FLASH_SPIM_MODEL1 = 0x01, /*!< spim model 1 */ - FLASH_SPIM_MODEL2 = 0x02, /*!< spim model 2 */ + FLASH_SPIM_MODEL2 = 0x02 /*!< spim model 2 */ } flash_spim_model_type; /** @@ -595,12 +593,14 @@ uint8_t flash_ssb_status_get(void); void flash_interrupt_enable(uint32_t flash_int, confirm_state new_state); void flash_spim_model_select(flash_spim_model_type mode); void flash_spim_encryption_range_set(uint32_t decode_address); +void flash_spim_dummy_read(void); +flash_status_type flash_spim_mass_program(uint32_t address, uint8_t *buf, uint32_t cnt); flash_status_type flash_slib_enable(uint32_t pwd, uint16_t start_sector, uint16_t data_start_sector, uint16_t end_sector); error_status flash_slib_disable(uint32_t pwd); uint32_t flash_slib_remaining_count_get(void); flag_status flash_slib_state_get(void); uint16_t flash_slib_start_sector_get(void); -uint16_t flash_slib_datstart_sector_get(void); +uint16_t flash_slib_datastart_sector_get(void); uint16_t flash_slib_end_sector_get(void); uint32_t flash_crc_calibrate(uint32_t start_sector, uint32_t sector_cnt); diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_gpio.h b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_gpio.h index bcc80b275d..ad33b4356a 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_gpio.h +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_gpio.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_gpio.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f413 gpio header file ************************************************************************** * Copyright notice & Disclaimer @@ -767,7 +765,7 @@ uint16_t gpio_output_data_read(gpio_type *gpio_x); void gpio_bits_set(gpio_type *gpio_x, uint16_t pins); void gpio_bits_reset(gpio_type *gpio_x, uint16_t pins); void gpio_bits_write(gpio_type *gpio_x, uint16_t pins, confirm_state bit_state); -void gpio_port_wirte(gpio_type *gpio_x, uint16_t port_value); +void gpio_port_write(gpio_type *gpio_x, uint16_t port_value); void gpio_pin_wp_config(gpio_type *gpio_x, uint16_t pins); void gpio_event_output_config(gpio_port_source_type gpio_port_source, gpio_pins_source_type gpio_pin_source); void gpio_event_output_enable(confirm_state new_state); diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_i2c.h b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_i2c.h index 6fd86930ec..f10d3472d5 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_i2c.h +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_i2c.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_i2c.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f413 i2c header file ************************************************************************** * Copyright notice & Disclaimer @@ -380,6 +378,7 @@ void i2c_7bit_address_send(i2c_type *i2c_x, uint8_t address, i2c_direction_type void i2c_data_send(i2c_type *i2c_x, uint8_t data); uint8_t i2c_data_receive(i2c_type *i2c_x); flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag); +flag_status i2c_interrupt_flag_get(i2c_type *i2c_x, uint32_t flag); void i2c_flag_clear(i2c_type *i2c_x, uint32_t flag); /** diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_misc.h b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_misc.h index 99e5094817..ec17e71470 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_misc.h +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_misc.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_misc.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f413 misc header file ************************************************************************** * Copyright notice & Disclaimer @@ -76,9 +74,9 @@ typedef enum */ typedef enum { - NVIC_LP_SLEEPONEXIT = 0x02, /*!< send event on pending */ + NVIC_LP_SLEEPONEXIT = 0x02, /*!< enable sleep-on-exit feature */ NVIC_LP_SLEEPDEEP = 0x04, /*!< enable sleep-deep output signal when entering sleep mode */ - NVIC_LP_SEVONPEND = 0x10 /*!< enable sleep-on-exit feature */ + NVIC_LP_SEVONPEND = 0x10 /*!< send event on pending */ } nvic_lowpower_mode_type; /** diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_pwc.h b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_pwc.h index 57fa5b2097..4a24cc1b45 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_pwc.h +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_pwc.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_pwc.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f413 pwc header file ************************************************************************** * Copyright notice & Disclaimer @@ -60,7 +58,7 @@ extern "C" { /** * @brief pwc wakeup pin num definition */ -#define PWC_WAKEUP_PIN_1 ((uint32_t)0x00000100) /*!< standby wake-up pin1 */ +#define PWC_WAKEUP_PIN_1 ((uint32_t)0x00000100) /*!< standby wake-up pin1(pa0) */ /** @defgroup PWC_exported_types * @{ @@ -98,15 +96,6 @@ typedef enum PWC_DEEP_SLEEP_ENTER_WFE = 0x01 /*!< use wfe enter deepsleep mode */ } pwc_deep_sleep_enter_type; -/** - * @brief pwc regulator type - */ -typedef enum -{ - PWC_REGULATOR_ON = 0x00, /*!< voltage regulator state on when deepsleep mode */ - PWC_REGULATOR_LOW_POWER = 0x01 /*!< voltage regulator state low power when deepsleep mode */ -} pwc_regulator_type; - /** * @brief type define pwc register all */ @@ -120,14 +109,14 @@ typedef struct __IO uint32_t ctrl; struct { - __IO uint32_t vrsel : 1; /* [0] */ + __IO uint32_t reserved1 : 1; /* [0] */ __IO uint32_t lpsel : 1; /* [1] */ __IO uint32_t clswef : 1; /* [2] */ __IO uint32_t clsef : 1; /* [3] */ __IO uint32_t pvmen : 1; /* [4] */ __IO uint32_t pvmsel : 3; /* [7:5] */ __IO uint32_t bpwen : 1; /* [8] */ - __IO uint32_t reserved1 : 23;/* [31:9] */ + __IO uint32_t reserved2 : 23;/* [31:9] */ } ctrl_bit; }; @@ -169,7 +158,6 @@ void pwc_flag_clear(uint32_t pwc_flag); flag_status pwc_flag_get(uint32_t pwc_flag); void pwc_sleep_mode_enter(pwc_sleep_enter_type pwc_sleep_enter); void pwc_deep_sleep_mode_enter(pwc_deep_sleep_enter_type pwc_deep_sleep_enter); -void pwc_voltage_regulate_set(pwc_regulator_type pwc_regulator); void pwc_standby_mode_enter(void); /** diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_rtc.h b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_rtc.h index 024b10e0a2..e31e3852a2 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_rtc.h +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_rtc.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_rtc.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f413 rtc header file ************************************************************************** * Copyright notice & Disclaimer @@ -238,6 +236,7 @@ uint32_t rtc_divider_get(void); void rtc_alarm_set(uint32_t alarm_value); void rtc_interrupt_enable(uint16_t source, confirm_state new_state); flag_status rtc_flag_get(uint16_t flag); +flag_status rtc_interrupt_flag_get(uint16_t flag); void rtc_flag_clear(uint16_t flag); void rtc_wait_config_finish(void); void rtc_wait_update_finish(void); diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_sdio.h b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_sdio.h index 42c8a1d2fa..c1085ddcda 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_sdio.h +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_sdio.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_sdio.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f413 sdio header file ************************************************************************** * Copyright notice & Disclaimer @@ -569,7 +567,10 @@ typedef struct * @} */ +#if defined (AT32F413TBU7) || defined (AT32F413Rx) || defined (AT32F413Cx) || \ + defined (AT32F413Kx) #define SDIO1 ((sdio_type *) SDIO1_BASE) +#endif /** @defgroup SDIO_exported_functions * @{ @@ -577,7 +578,7 @@ typedef struct void sdio_reset(sdio_type *sdio_x); void sdio_power_set(sdio_type *sdio_x, sdio_power_state_type power_state); -flag_status sdio_power_status_get(sdio_type *sdio_x); +sdio_power_state_type sdio_power_status_get(sdio_type *sdio_x); void sdio_clock_config(sdio_type *sdio_x, uint16_t clk_div, sdio_edge_phase_type clk_edg); void sdio_bus_width_config(sdio_type *sdio_x, sdio_bus_width_type width); void sdio_clock_bypass(sdio_type *sdio_x, confirm_state new_state); @@ -587,6 +588,7 @@ void sdio_clock_enable(sdio_type *sdio_x, confirm_state new_state); void sdio_dma_enable(sdio_type *sdio_x, confirm_state new_state); void sdio_interrupt_enable(sdio_type *sdio_x, uint32_t int_opt, confirm_state new_state); flag_status sdio_flag_get(sdio_type *sdio_x, uint32_t flag); +flag_status sdio_interrupt_flag_get(sdio_type *sdio_x, uint32_t flag); void sdio_flag_clear(sdio_type *sdio_x, uint32_t flag); void sdio_command_config(sdio_type *sdio_x, sdio_command_struct_type *command_struct); void sdio_command_state_machine_enable(sdio_type *sdio_x, confirm_state new_state); diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_spi.h b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_spi.h index ab2805133d..2fa0222b79 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_spi.h +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_spi.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_spi.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f413 spi header file ************************************************************************** * Copyright notice & Disclaimer @@ -475,6 +473,7 @@ void spi_i2s_dma_receiver_enable(spi_type* spi_x, confirm_state new_state); void spi_i2s_data_transmit(spi_type* spi_x, uint16_t tx_data); uint16_t spi_i2s_data_receive(spi_type* spi_x); flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag); +flag_status spi_i2s_interrupt_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag); void spi_i2s_flag_clear(spi_type* spi_x, uint32_t spi_i2s_flag); /** diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_tmr.h b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_tmr.h index 0654ca3432..2506c4b8f1 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_tmr.h +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_tmr.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_tmr.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f413 tmr header file ************************************************************************** * Copyright notice & Disclaimer @@ -238,7 +236,7 @@ typedef enum { TMR_CC_CHANNEL_MAPPED_DIRECT = 0x01, /*!< channel is configured as input, mapped direct */ TMR_CC_CHANNEL_MAPPED_INDIRECT = 0x02, /*!< channel is configured as input, mapped indirect */ - TMR_CC_CHANNEL_MAPPED_STI = 0x03 /*!< channel is configured as input, mapped trc */ + TMR_CC_CHANNEL_MAPPED_STI = 0x03 /*!< channel is configured as input, mapped sti */ } tmr_input_direction_mapped_type; /** @@ -833,11 +831,16 @@ typedef struct #define TMR2 ((tmr_type *) TMR2_BASE) #define TMR3 ((tmr_type *) TMR3_BASE) #define TMR4 ((tmr_type *) TMR4_BASE) +#if defined (AT32F413TBU7) || defined (AT32F413Rx) || defined (AT32F413Cx) || \ + defined (AT32F413Kx) #define TMR5 ((tmr_type *) TMR5_BASE) +#if defined (AT32F413CCU7) || defined (AT32F413CCT7) || defined (AT32F413RCT7) #define TMR8 ((tmr_type *) TMR8_BASE) +#endif #define TMR9 ((tmr_type *) TMR9_BASE) #define TMR10 ((tmr_type *) TMR10_BASE) #define TMR11 ((tmr_type *) TMR11_BASE) +#endif /** @defgroup TMR_exported_functions * @{ @@ -883,7 +886,7 @@ void tmr_input_channel_filter_set(tmr_type *tmr_x, tmr_channel_select_type tmr_c uint16_t filter_value); void tmr_pwm_input_config(tmr_type *tmr_x, tmr_input_config_type *input_struct, \ tmr_channel_input_divider_type divider_factor); -void tmr_channel1_input_select(tmr_type *tmr_x, tmr_channel1_input_connected_type ti1_connect); +void tmr_channel1_input_select(tmr_type *tmr_x, tmr_channel1_input_connected_type ch1_connect); void tmr_input_channel_divider_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \ tmr_channel_input_divider_type divider_factor); void tmr_primary_mode_select(tmr_type *tmr_x, tmr_primary_select_type primary_mode); @@ -895,6 +898,7 @@ void tmr_trigger_input_select(tmr_type *tmr_x, sub_tmr_input_sel_type trigger_se void tmr_sub_sync_mode_set(tmr_type *tmr_x, confirm_state new_state); void tmr_dma_request_enable(tmr_type *tmr_x, tmr_dma_request_type dma_request, confirm_state new_state); void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state new_state); +flag_status tmr_interrupt_flag_get(tmr_type *tmr_x, uint32_t tmr_flag); flag_status tmr_flag_get(tmr_type *tmr_x, uint32_t tmr_flag); void tmr_flag_clear(tmr_type *tmr_x, uint32_t tmr_flag); void tmr_event_sw_trigger(tmr_type *tmr_x, tmr_event_trigger_type tmr_event); diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_usart.h b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_usart.h index 062f359705..c8d332c29f 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_usart.h +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_usart.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_usart.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f413 usart header file ************************************************************************** * Copyright notice & Disclaimer @@ -318,9 +316,13 @@ typedef struct #define USART1 ((usart_type *) USART1_BASE) #define USART2 ((usart_type *) USART2_BASE) +#if defined (AT32F413Rx) || defined (AT32F413Cx) || defined (AT32FEBKC8T7) #define USART3 ((usart_type *) USART3_BASE) +#endif +#if defined (AT32F413Rx) #define UART4 ((usart_type *) UART4_BASE) #define UART5 ((usart_type *) UART5_BASE) +#endif /** @defgroup USART_exported_functions * @{ @@ -354,6 +356,7 @@ void usart_irda_mode_enable(usart_type* usart_x, confirm_state new_state); void usart_irda_low_power_enable(usart_type* usart_x, confirm_state new_state); void usart_hardware_flow_control_set(usart_type* usart_x,usart_hardware_flow_control_type flow_state); flag_status usart_flag_get(usart_type* usart_x, uint32_t flag); +flag_status usart_interrupt_flag_get(usart_type* usart_x, uint32_t flag); void usart_flag_clear(usart_type* usart_x, uint32_t flag); /** diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_usb.h b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_usb.h index 96232951d6..56310003bb 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_usb.h +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_usb.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_usb.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f413 usb header file ************************************************************************** * Copyright notice & Disclaimer @@ -195,7 +193,6 @@ typedef enum #ifndef USB_EPT_MAX_NUM #define USB_EPT_MAX_NUM 8 /*!< usb device support endpoint number */ #endif - /** * @brief endpoint transfer type define */ @@ -691,6 +688,7 @@ void usb_remote_wkup_clear(usbd_type *usbx); uint16_t usb_buffer_malloc(uint16_t maxpacket); void usb_buffer_free(void); flag_status usb_flag_get(usbd_type *usbx, uint16_t flag); +flag_status usb_interrupt_flag_get(usbd_type *usbx, uint16_t flag); void usb_flag_clear(usbd_type *usbx, uint16_t flag); diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_wdt.h b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_wdt.h index 39fa082557..c2cdb53e18 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_wdt.h +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_wdt.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_wdt.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f413 wdt header file ************************************************************************** * Copyright notice & Disclaimer diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_wwdt.h b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_wwdt.h index 5c26304542..2dcfa2bb9a 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_wwdt.h +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/inc/at32f413_wwdt.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_wwdt.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f413 wwdt header file ************************************************************************** * Copyright notice & Disclaimer @@ -136,6 +134,7 @@ void wwdt_flag_clear(void); void wwdt_enable(uint8_t wwdt_cnt); void wwdt_interrupt_enable(void); flag_status wwdt_flag_get(void); +flag_status wwdt_interrupt_flag_get(void); void wwdt_counter_set(uint8_t wwdt_cnt); void wwdt_window_counter_set(uint8_t window_cnt); diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_acc.c b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_acc.c index 1eec3f85ef..7947516b7b 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_acc.c +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_acc.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_acc.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the acc firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -190,6 +188,22 @@ flag_status acc_flag_get(uint16_t acc_flag) return (flag_status)(ACC->sts_bit.rslost); } +/** + * @brief check whether the specified acc interrupt flag is set or not. + * @param acc_flag: specifies the flag to check. + * this parameter can be one of the following values: + * - ACC_RSLOST_FLAG + * - ACC_CALRDY_FLAG + * @retval flag_status (SET or RESET) + */ +flag_status acc_interrupt_flag_get(uint16_t acc_flag) +{ + if(acc_flag == ACC_CALRDY_FLAG) + return (flag_status)(ACC->sts_bit.calrdy && ACC->ctrl1_bit.calrdyien); + else + return (flag_status)(ACC->sts_bit.rslost && ACC->ctrl1_bit.eien); +} + /** * @brief clear the specified acc flag is set or not. * @param acc_flag: specifies the flag to check. diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_adc.c b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_adc.c index ca75cd1cbb..be630faa92 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_adc.c +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_adc.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_adc.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the adc firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -111,7 +109,7 @@ void adc_combine_mode_select(adc_combine_mode_type combine_mode) * - ADC_LEFT_ALIGNMENT * @param ordinary_channel_length: configure the adc ordinary channel sequence length. * this parameter can be: - * - (0x1~0xf) + * - (0x1~0x10) * @retval none */ void adc_base_default_para_init(adc_base_config_type *adc_base_struct) @@ -137,7 +135,7 @@ void adc_base_default_para_init(adc_base_config_type *adc_base_struct) * - ADC_LEFT_ALIGNMENT * @param ordinary_channel_length: configure the adc ordinary channel sequence length. * this parameter can be: - * - (0x1~0xf) + * - (0x1~0x10) * @retval none */ void adc_base_config(adc_type *adc_x, adc_base_config_type *adc_base_struct) @@ -342,117 +340,42 @@ void adc_voltage_monitor_single_channel_select(adc_type *adc_x, adc_channel_sele */ void adc_ordinary_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime) { - switch(adc_channel) + uint32_t tmp_reg; + if(adc_channel < ADC_CHANNEL_10) { - case ADC_CHANNEL_0: - adc_x->spt2_bit.cspt0 = adc_sampletime; - break; - case ADC_CHANNEL_1: - adc_x->spt2_bit.cspt1 = adc_sampletime; - break; - case ADC_CHANNEL_2: - adc_x->spt2_bit.cspt2 = adc_sampletime; - break; - case ADC_CHANNEL_3: - adc_x->spt2_bit.cspt3 = adc_sampletime; - break; - case ADC_CHANNEL_4: - adc_x->spt2_bit.cspt4 = adc_sampletime; - break; - case ADC_CHANNEL_5: - adc_x->spt2_bit.cspt5 = adc_sampletime; - break; - case ADC_CHANNEL_6: - adc_x->spt2_bit.cspt6 = adc_sampletime; - break; - case ADC_CHANNEL_7: - adc_x->spt2_bit.cspt7 = adc_sampletime; - break; - case ADC_CHANNEL_8: - adc_x->spt2_bit.cspt8 = adc_sampletime; - break; - case ADC_CHANNEL_9: - adc_x->spt2_bit.cspt9 = adc_sampletime; - break; - case ADC_CHANNEL_10: - adc_x->spt1_bit.cspt10 = adc_sampletime; - break; - case ADC_CHANNEL_11: - adc_x->spt1_bit.cspt11 = adc_sampletime; - break; - case ADC_CHANNEL_12: - adc_x->spt1_bit.cspt12 = adc_sampletime; - break; - case ADC_CHANNEL_13: - adc_x->spt1_bit.cspt13 = adc_sampletime; - break; - case ADC_CHANNEL_14: - adc_x->spt1_bit.cspt14 = adc_sampletime; - break; - case ADC_CHANNEL_15: - adc_x->spt1_bit.cspt15 = adc_sampletime; - break; - case ADC_CHANNEL_16: - adc_x->spt1_bit.cspt16 = adc_sampletime; - break; - case ADC_CHANNEL_17: - adc_x->spt1_bit.cspt17 = adc_sampletime; - break; - default: - break; + tmp_reg = adc_x->spt2; + tmp_reg &= ~(0x07 << 3 * adc_channel); + tmp_reg |= adc_sampletime << 3 * adc_channel; + adc_x->spt2 = tmp_reg; } - switch(adc_sequence) + else { - case 1: - adc_x->osq3_bit.osn1 = adc_channel; - break; - case 2: - adc_x->osq3_bit.osn2 = adc_channel; - break; - case 3: - adc_x->osq3_bit.osn3 = adc_channel; - break; - case 4: - adc_x->osq3_bit.osn4 = adc_channel; - break; - case 5: - adc_x->osq3_bit.osn5 = adc_channel; - break; - case 6: - adc_x->osq3_bit.osn6 = adc_channel; - break; - case 7: - adc_x->osq2_bit.osn7 = adc_channel; - break; - case 8: - adc_x->osq2_bit.osn8 = adc_channel; - break; - case 9: - adc_x->osq2_bit.osn9 = adc_channel; - break; - case 10: - adc_x->osq2_bit.osn10 = adc_channel; - break; - case 11: - adc_x->osq2_bit.osn11 = adc_channel; - break; - case 12: - adc_x->osq2_bit.osn12 = adc_channel; - break; - case 13: - adc_x->osq1_bit.osn13 = adc_channel; - break; - case 14: - adc_x->osq1_bit.osn14 = adc_channel; - break; - case 15: - adc_x->osq1_bit.osn15 = adc_channel; - break; - case 16: - adc_x->osq1_bit.osn16 = adc_channel; - break; - default: - break; + tmp_reg = adc_x->spt1; + tmp_reg &= ~(0x07 << 3 * (adc_channel - ADC_CHANNEL_10)); + tmp_reg |= adc_sampletime << 3 * (adc_channel - ADC_CHANNEL_10); + adc_x->spt1 = tmp_reg; + } + + if(adc_sequence >= 13) + { + tmp_reg = adc_x->osq1; + tmp_reg &= ~(0x01F << 5 * (adc_sequence - 13)); + tmp_reg |= adc_channel << 5 * (adc_sequence - 13); + adc_x->osq1 = tmp_reg; + } + else if(adc_sequence >= 7) + { + tmp_reg = adc_x->osq2; + tmp_reg &= ~(0x01F << 5 * (adc_sequence - 7)); + tmp_reg |= adc_channel << 5 * (adc_sequence - 7); + adc_x->osq2 = tmp_reg; + } + else + { + tmp_reg = adc_x->osq3; + tmp_reg &= ~(0x01F << 5 * (adc_sequence - 1)); + tmp_reg |= adc_channel << 5 * (adc_sequence - 1); + adc_x->osq3 = tmp_reg; } } @@ -500,66 +423,23 @@ void adc_preempt_channel_length_set(adc_type *adc_x, uint8_t adc_channel_lenght) */ void adc_preempt_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime) { - uint16_t sequence_index=0; - switch(adc_channel) + uint32_t tmp_reg; + uint8_t sequence_index; + if(adc_channel < ADC_CHANNEL_10) { - case ADC_CHANNEL_0: - adc_x->spt2_bit.cspt0 = adc_sampletime; - break; - case ADC_CHANNEL_1: - adc_x->spt2_bit.cspt1 = adc_sampletime; - break; - case ADC_CHANNEL_2: - adc_x->spt2_bit.cspt2 = adc_sampletime; - break; - case ADC_CHANNEL_3: - adc_x->spt2_bit.cspt3 = adc_sampletime; - break; - case ADC_CHANNEL_4: - adc_x->spt2_bit.cspt4 = adc_sampletime; - break; - case ADC_CHANNEL_5: - adc_x->spt2_bit.cspt5 = adc_sampletime; - break; - case ADC_CHANNEL_6: - adc_x->spt2_bit.cspt6 = adc_sampletime; - break; - case ADC_CHANNEL_7: - adc_x->spt2_bit.cspt7 = adc_sampletime; - break; - case ADC_CHANNEL_8: - adc_x->spt2_bit.cspt8 = adc_sampletime; - break; - case ADC_CHANNEL_9: - adc_x->spt2_bit.cspt9 = adc_sampletime; - break; - case ADC_CHANNEL_10: - adc_x->spt1_bit.cspt10 = adc_sampletime; - break; - case ADC_CHANNEL_11: - adc_x->spt1_bit.cspt11 = adc_sampletime; - break; - case ADC_CHANNEL_12: - adc_x->spt1_bit.cspt12 = adc_sampletime; - break; - case ADC_CHANNEL_13: - adc_x->spt1_bit.cspt13 = adc_sampletime; - break; - case ADC_CHANNEL_14: - adc_x->spt1_bit.cspt14 = adc_sampletime; - break; - case ADC_CHANNEL_15: - adc_x->spt1_bit.cspt15 = adc_sampletime; - break; - case ADC_CHANNEL_16: - adc_x->spt1_bit.cspt16 = adc_sampletime; - break; - case ADC_CHANNEL_17: - adc_x->spt1_bit.cspt17 = adc_sampletime; - break; - default: - break; + tmp_reg = adc_x->spt2; + tmp_reg &= ~(0x07 << 3 * adc_channel); + tmp_reg |= adc_sampletime << 3 * adc_channel; + adc_x->spt2 = tmp_reg; } + else + { + tmp_reg = adc_x->spt1; + tmp_reg &= ~(0x07 << 3 * (adc_channel - ADC_CHANNEL_10)); + tmp_reg |= adc_sampletime << 3 * (adc_channel - ADC_CHANNEL_10); + adc_x->spt1 = tmp_reg; + } + sequence_index = adc_sequence + 3 - adc_x->psq_bit.pclen; switch(sequence_index) { @@ -844,10 +724,10 @@ uint32_t adc_combine_ordinary_conversion_data_get(void) * ADC1, ADC2. * @param adc_preempt_channel: select the preempt channel. * this parameter can be one of the following values: - * - ADC_PREEMPTED_CHANNEL_1 - * - ADC_PREEMPTED_CHANNEL_2 - * - ADC_PREEMPTED_CHANNEL_3 - * - ADC_PREEMPTED_CHANNEL_4 + * - ADC_PREEMPT_CHANNEL_1 + * - ADC_PREEMPT_CHANNEL_2 + * - ADC_PREEMPT_CHANNEL_3 + * - ADC_PREEMPT_CHANNEL_4 * @retval the conversion data for selection preempt channel. */ uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel) @@ -902,6 +782,47 @@ flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag) return status; } +/** + * @brief get interrupt flag of the specified adc peripheral. + * @param adc_x: select the adc peripheral. + * this parameter can be one of the following values: + * ADC1, ADC2. + * @param adc_flag: select the adc flag. + * this parameter can be one of the following values: + * - ADC_VMOR_FLAG + * - ADC_CCE_FLAG + * - ADC_PCCE_FLAG + * @retval the new state of adc flag status(SET or RESET). + */ +flag_status adc_interrupt_flag_get(adc_type *adc_x, uint8_t adc_flag) +{ + flag_status status = RESET; + switch(adc_flag) + { + case ADC_VMOR_FLAG: + if(adc_x->sts_bit.vmor && adc_x->ctrl1_bit.vmorien) + { + status = SET; + } + break; + case ADC_CCE_FLAG: + if(adc_x->sts_bit.cce && adc_x->ctrl1_bit.cceien) + { + status = SET; + } + break; + case ADC_PCCE_FLAG: + if(adc_x->sts_bit.pcce && adc_x->ctrl1_bit.pcceien) + { + status = SET; + } + break; + default: + break; + } + return status; +} + /** * @brief clear flag of the specified adc peripheral. * @param adc_x: select the adc peripheral. diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_bpr.c b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_bpr.c index 955b7a3908..ee31381124 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_bpr.c +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_bpr.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_bpr.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the bpr firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -72,6 +70,26 @@ flag_status bpr_flag_get(uint32_t flag) } } +/** + * @brief bpr interrupt flag get + * @param flag: specifies the flag to check. + * this parameter can be one of the following values: + * - BPR_TAMPER_INTERRUPT_FLAG: tamper interrupt flag + * - BPR_TAMPER_EVENT_FLAG: tamper event flag + * @retval state of tamper event flag + */ +flag_status bpr_interrupt_flag_get(uint32_t flag) +{ + if(flag == BPR_TAMPER_INTERRUPT_FLAG) + { + return (flag_status)(BPR->ctrlsts_bit.tpif && BPR->ctrlsts_bit.tpien); + } + else + { + return (flag_status)(BPR->ctrlsts_bit.tpef && BPR->ctrlsts_bit.tpien); + } +} + /** * @brief clear bpr tamper flag * @param flag: specifies the flag to clear. @@ -144,8 +162,6 @@ void bpr_data_write(bpr_data_type bpr_data, uint16_t data_value) * - BPR_RTC_OUTPUT_ALARM: output alarm event with pluse mode. * - BPR_RTC_OUTPUT_SECOND: output second event with pluse mode. * - BPR_RTC_OUTPUT_CLOCK_CAL_AFTER: output clock after calibration. - * - BPR_RTC_OUTPUT_ALARM_TOGGLE: output alarm event with toggle mode. - * - BPR_RTC_OUTPUT_SECOND_TOGGLE: output second event with toggle mode. * @retval none */ void bpr_rtc_output_select(bpr_rtc_output_type output_source) diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_can.c b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_can.c index feb5e4b7a6..113c8031d7 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_can.c +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_can.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_can.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the can firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -55,11 +53,14 @@ void can_reset(can_type* can_x) crm_periph_reset(CRM_CAN1_PERIPH_RESET, TRUE); crm_periph_reset(CRM_CAN1_PERIPH_RESET, FALSE); } +#if defined (AT32F413TBU7) || defined (AT32F413Rx) || defined (AT32F413Cx) || \ + defined (AT32F413Kx) else if(can_x == CAN2) { crm_periph_reset(CRM_CAN2_PERIPH_RESET, TRUE); crm_periph_reset(CRM_CAN2_PERIPH_RESET, FALSE); } +#endif } /** @@ -933,6 +934,102 @@ void can_interrupt_enable(can_type* can_x, uint32_t can_int, confirm_state new_s } } +/** + * @brief get interrupt flag of the specified can peripheral. + * @param can_x: select the can peripheral. + * this parameter can be one of the following values: + * CAN1,CAN2. + * @param can_flag: select the flag. + * this parameter can be one of the following flags: + * - CAN_EAF_FLAG + * - CAN_EPF_FLAG + * - CAN_BOF_FLAG + * - CAN_ETR_FLAG + * - CAN_EOIF_FLAG + * - CAN_TM0TCF_FLAG + * - CAN_TM1TCF_FLAG + * - CAN_TM2TCF_FLAG + * - CAN_RF0MN_FLAG + * - CAN_RF0FF_FLAG + * - CAN_RF0OF_FLAG + * - CAN_RF1MN_FLAG + * - CAN_RF1FF_FLAG + * - CAN_RF1OF_FLAG + * - CAN_QDZIF_FLAG + * - CAN_EDZC_FLAG + * - CAN_TMEF_FLAG + * note:the state of CAN_EDZC_FLAG need to check dzc and edzif bit + * note:the state of CAN_TMEF_FLAG need to check rqc0,rqc1 and rqc2 bit + * @retval status of can_flag, the returned value can be:SET or RESET. + */ +flag_status can_interrupt_flag_get(can_type* can_x, uint32_t can_flag) +{ + flag_status bit_status = RESET; + flag_status int_status = RESET; + + switch(can_flag) + { + case CAN_EAF_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.eaien); + break; + case CAN_EPF_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.epien); + break; + case CAN_BOF_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.boien); + break; + case CAN_ETR_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.etrien); + break; + case CAN_EOIF_FLAG: + int_status = (flag_status)can_x->inten_bit.eoien; + break; + case CAN_TM0TCF_FLAG: + case CAN_TM1TCF_FLAG: + case CAN_TM2TCF_FLAG: + int_status = (flag_status)can_x->inten_bit.tcien; + break; + case CAN_RF0MN_FLAG: + int_status = (flag_status)can_x->inten_bit.rf0mien; + break; + case CAN_RF0FF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf0fien; + break; + case CAN_RF0OF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf0oien; + break; + case CAN_RF1MN_FLAG: + int_status = (flag_status)can_x->inten_bit.rf1mien; + break; + case CAN_RF1FF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf1fien; + break; + case CAN_RF1OF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf1oien; + break; + case CAN_QDZIF_FLAG: + int_status = (flag_status)can_x->inten_bit.qdzien; + break; + case CAN_EDZC_FLAG: + int_status = (flag_status)can_x->inten_bit.edzien; + break; + case CAN_TMEF_FLAG: + int_status = (flag_status)can_x->inten_bit.tcien; + break; + default: + int_status = RESET; + break; + } + + if(int_status != SET) + { + return RESET; + } + bit_status = can_flag_get(can_x, can_flag); + + return bit_status; +} + /** * @brief get flag of the specified can peripheral. * @param can_x: select the can peripheral. diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_crc.c b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_crc.c index 6eed245d7f..025aa81f9f 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_crc.c +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_crc.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_crc.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the crc firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -106,7 +104,7 @@ void crc_common_data_set(uint8_t cdt_value) * @param none * @retval 8-bit value of the common data register */ -uint8_t crc_common_date_get(void) +uint8_t crc_common_data_get(void) { return (CRC->cdt_bit.cdt); } @@ -149,6 +147,52 @@ void crc_reverse_output_data_set(crc_reverse_output_type value) CRC->ctrl_bit.revod = value; } +/** + * @brief config crc polynomial value + * @param value + * 32-bit new data of crc poly value + * @retval none. + */ +void crc_poly_value_set(uint32_t value) +{ + CRC->poly = value; +} + +/** + * @brief return crc polynomial value + * @param none + * @retval 32-bit value of the polynomial value. + */ +uint32_t crc_poly_value_get(void) +{ + return (CRC->poly); +} + +/** + * @brief config crc polynomial data size + * @param size + * this parameter can be one of the following values: + * - CRC_POLY_SIZE_32B + * - CRC_POLY_SIZE_16B + * - CRC_POLY_SIZE_8B + * - CRC_POLY_SIZE_7B + * @retval none. + */ +void crc_poly_size_set(crc_poly_size_type size) +{ + CRC->ctrl_bit.poly_size = size; +} + +/** + * @brief return crc polynomial data size + * @param none + * @retval polynomial data size. + */ +crc_poly_size_type crc_poly_size_get(void) +{ + return (crc_poly_size_type)(CRC->ctrl_bit.poly_size); +} + /** * @} */ diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_crm.c b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_crm.c index f4451f9e32..5e54594f3f 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_crm.c +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_crm.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_crm.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the crm firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -133,6 +131,64 @@ flag_status crm_flag_get(uint32_t flag) return status; } +/** + * @brief get crm interrupt flag status + * @param flag + * this parameter can be one of the following values: + * - CRM_LICK_READY_INT_FLAG + * - CRM_LEXT_READY_INT_FLAG + * - CRM_HICK_READY_INT_FLAG + * - CRM_HEXT_READY_INT_FLAG + * - CRM_PLL_READY_INT_FLAG + * - CRM_CLOCK_FAILURE_INT_FLAG + * @retval flag_status (SET or RESET) + */ +flag_status crm_interrupt_flag_get(uint32_t flag) +{ + flag_status status = RESET; + switch(flag) + { + case CRM_LICK_READY_INT_FLAG: + if(CRM->clkint_bit.lickstblf && CRM->clkint_bit.lickstblien) + { + status = SET; + } + break; + case CRM_LEXT_READY_INT_FLAG: + if(CRM->clkint_bit.lextstblf && CRM->clkint_bit.lextstblien) + { + status = SET; + } + break; + case CRM_HICK_READY_INT_FLAG: + if(CRM->clkint_bit.hickstblf && CRM->clkint_bit.hickstblien) + { + status = SET; + } + break; + case CRM_HEXT_READY_INT_FLAG: + if(CRM->clkint_bit.hextstblf && CRM->clkint_bit.hextstblien) + { + status = SET; + } + break; + case CRM_PLL_READY_INT_FLAG: + if(CRM->clkint_bit.pllstblf && CRM->clkint_bit.pllstblien) + { + status = SET; + } + break; + case CRM_CLOCK_FAILURE_INT_FLAG: + if(CRM->clkint_bit.cfdf && CRM->ctrl_bit.cfden) + { + status = SET; + } + break; + } + + return status; +} + /** * @brief wait for hext stable * @param none @@ -410,6 +466,7 @@ void crm_ahb_div_set(crm_ahb_div_type value) /** * @brief set crm apb1 division + * @note the maximum frequency of APB1/APB2 clock is 100 MHz * @param value * this parameter can be one of the following values: * - CRM_APB1_DIV_1 @@ -426,6 +483,7 @@ void crm_apb1_div_set(crm_apb1_div_type value) /** * @brief set crm apb2 division + * @note the maximum frequency of APB1/APB2 clock is 100 MHz * @param value * this parameter can be one of the following values: * - CRM_APB2_DIV_1 @@ -517,6 +575,7 @@ void crm_pll_config(crm_pll_clock_source_type clock_source, crm_pll_mult_type mu if(clock_source == CRM_PLL_SOURCE_HICK) { CRM->cfg_bit.pllrcs = FALSE; + CRM->misc1_bit.hickdiv = CRM_HICK48_NODIV; } else { @@ -551,6 +610,7 @@ void crm_pll_config(crm_pll_clock_source_type clock_source, crm_pll_mult_type mu void crm_sysclk_switch(crm_sclk_type value) { CRM->cfg_bit.sclksel = value; + DUMMY_NOP(); } /** diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_debug.c b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_debug.c index c46f1fc721..d15d592e62 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_debug.c +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_debug.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_debug.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the debug firmware library ************************************************************************** * Copyright notice & Disclaimer diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_dma.c b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_dma.c index fc7c3167bd..bc37f7abfb 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_dma.c +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_dma.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_dma.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the dma firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -275,6 +273,52 @@ void dma_flexible_config(dma_type* dma_x, uint8_t flex_channelx, dma_flexible_re } } +/** + * @brief get dma interrupt flag + * @param dmax_flag + * this parameter can be one of the following values: + * - DMA1_FDT1_FLAG - DMA1_HDT1_FLAG - DMA1_DTERR1_FLAG + * - DMA1_FDT2_FLAG - DMA1_HDT2_FLAG - DMA1_DTERR2_FLAG + * - DMA1_FDT3_FLAG - DMA1_HDT3_FLAG - DMA1_DTERR3_FLAG + * - DMA1_FDT4_FLAG - DMA1_HDT4_FLAG - DMA1_DTERR4_FLAG + * - DMA1_FDT5_FLAG - DMA1_HDT5_FLAG - DMA1_DTERR5_FLAG + * - DMA1_FDT6_FLAG - DMA1_HDT6_FLAG - DMA1_DTERR6_FLAG + * - DMA1_FDT7_FLAG - DMA1_HDT7_FLAG - DMA1_DTERR7_FLAG + * - DMA2_FDT1_FLAG - DMA2_HDT1_FLAG - DMA2_DTERR1_FLAG + * - DMA2_FDT2_FLAG - DMA2_HDT2_FLAG - DMA2_DTERR2_FLAG + * - DMA2_FDT3_FLAG - DMA2_HDT3_FLAG - DMA2_DTERR3_FLAG + * - DMA2_FDT4_FLAG - DMA2_HDT4_FLAG - DMA2_DTERR4_FLAG + * - DMA2_FDT5_FLAG - DMA2_HDT5_FLAG - DMA2_DTERR5_FLAG + * - DMA2_FDT6_FLAG - DMA2_HDT6_FLAG - DMA2_DTERR6_FLAG + * - DMA2_FDT7_FLAG - DMA2_HDT7_FLAG - DMA2_DTERR7_FLAG + * @retval state of dma flag + */ +flag_status dma_interrupt_flag_get(uint32_t dmax_flag) +{ + flag_status status = RESET; + uint32_t temp = 0; + + if(dmax_flag > 0x10000000) + { + temp = DMA2->sts; + } + else + { + temp = DMA1->sts; + } + + if ((temp & dmax_flag) != (uint16_t)RESET) + { + status = SET; + } + else + { + status = RESET; + } + + return status; +} + /** * @brief get dma flag * @param dmax_flag diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_exint.c b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_exint.c index 38f6ff27d4..6f9f467c32 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_exint.c +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_exint.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_exint.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the exint firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -155,6 +153,35 @@ flag_status exint_flag_get(uint32_t exint_line) return status; } +/** + * @brief get exint interrupt flag + * @param exint_line + * this parameter can be one of the following values: + * - EXINT_LINE_0 + * - EXINT_LINE_1 + * ... + * - EXINT_LINE_17 + * - EXINT_LINE_18 + * @retval the new state of exint flag(SET or RESET). + */ +flag_status exint_interrupt_flag_get(uint32_t exint_line) +{ + flag_status status = RESET; + uint32_t exint_flag = 0; + exint_flag = EXINT->intsts & exint_line; + exint_flag = exint_flag & EXINT->inten; + + if((exint_flag != (uint16_t)RESET)) + { + status = SET; + } + else + { + status = RESET; + } + return status; +} + /** * @brief generate exint software interrupt event * @param exint_line diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_flash.c b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_flash.c index c5952f9807..6eaac07a62 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_flash.c +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_flash.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_flash.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the flash firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -275,42 +273,30 @@ flash_status_type flash_sector_erase(uint32_t sector_address) /* spim : external flash */ if(sector_address >= FLASH_SPIM_START_ADDR) { - /* wait for last operation to be completed */ + FLASH->ctrl3_bit.secers = TRUE; + FLASH->addr3 = sector_address; + FLASH->ctrl3_bit.erstr = TRUE; + + /* wait for operation to be completed */ status = flash_spim_operation_wait_for(SPIM_ERASE_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* if the previous operation is completed, continue to erase the sector */ - FLASH->ctrl3_bit.secers = TRUE; - FLASH->addr3 = sector_address; - FLASH->ctrl3_bit.erstr = TRUE; + /* disable the secers bit */ + FLASH->ctrl3_bit.secers = FALSE; - /* wait for operation to be completed */ - status = flash_spim_operation_wait_for(SPIM_ERASE_TIMEOUT); - - /* disable the secers bit */ - FLASH->ctrl3_bit.secers = FALSE; - } - return status; + /* dummy read */ + flash_spim_dummy_read(); } else { - /* wait for last operation to be completed */ + FLASH->ctrl_bit.secers = TRUE; + FLASH->addr = sector_address; + FLASH->ctrl_bit.erstr = TRUE; + + /* wait for operation to be completed */ status = flash_operation_wait_for(ERASE_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* if the previous operation is completed, continue to erase the sector */ - FLASH->ctrl_bit.secers = TRUE; - FLASH->addr = sector_address; - FLASH->ctrl_bit.erstr = TRUE; - - /* wait for operation to be completed */ - status = flash_operation_wait_for(ERASE_TIMEOUT); - - /* disable the secers bit */ - FLASH->ctrl_bit.secers = FALSE; - } + /* disable the secers bit */ + FLASH->ctrl_bit.secers = FALSE; } /* return the erase status */ return status; @@ -325,21 +311,16 @@ flash_status_type flash_sector_erase(uint32_t sector_address) flash_status_type flash_internal_all_erase(void) { flash_status_type status = FLASH_OPERATE_DONE; - /* wait for last operation to be completed */ + + FLASH->ctrl_bit.bankers = TRUE; + FLASH->ctrl_bit.erstr = TRUE; + + /* wait for operation to be completed */ status = flash_operation_wait_for(ERASE_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* if the previous operation is completed, continue to erase bank1 */ - FLASH->ctrl_bit.bankers = TRUE; - FLASH->ctrl_bit.erstr = TRUE; + /* disable the bankers bit */ + FLASH->ctrl_bit.bankers = FALSE; - /* wait for operation to be completed */ - status = flash_operation_wait_for(ERASE_TIMEOUT); - - /* disable the bankers bit */ - FLASH->ctrl_bit.bankers = FALSE; - } /* return the erase status */ return status; } @@ -353,21 +334,19 @@ flash_status_type flash_internal_all_erase(void) flash_status_type flash_spim_all_erase(void) { flash_status_type status = FLASH_OPERATE_DONE; - /* wait for last operation to be completed */ + + FLASH->ctrl3_bit.chpers = TRUE; + FLASH->ctrl3_bit.erstr = TRUE; + + /* wait for operation to be completed */ status = flash_spim_operation_wait_for(SPIM_ERASE_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* if the previous operation is completed, continue to erase spim */ - FLASH->ctrl3_bit.chpers = TRUE; - FLASH->ctrl3_bit.erstr = TRUE; + /* disable the chpers bit */ + FLASH->ctrl3_bit.chpers = FALSE; - /* wait for operation to be completed */ - status = flash_spim_operation_wait_for(SPIM_ERASE_TIMEOUT); + /* dummy read */ + flash_spim_dummy_read(); - /* disable the chpers bit */ - FLASH->ctrl3_bit.chpers = FALSE; - } /* return the erase status */ return status; } @@ -389,41 +368,36 @@ flash_status_type flash_user_system_data_erase(void) fap_val = 0x0000; } - /* wait for last operation to be completed */ + /* unlock the user system data */ + FLASH->usd_unlock = FLASH_UNLOCK_KEY1; + FLASH->usd_unlock = FLASH_UNLOCK_KEY2; + while(FLASH->ctrl_bit.usdulks == RESET); + + /* erase the user system data */ + FLASH->ctrl_bit.usders = TRUE; + FLASH->ctrl_bit.erstr = TRUE; + + /* wait for operation to be completed */ status = flash_operation_wait_for(ERASE_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* unlock the user system data */ - FLASH->usd_unlock = FLASH_UNLOCK_KEY1; - FLASH->usd_unlock = FLASH_UNLOCK_KEY2; - while(FLASH->ctrl_bit.usdulks==RESET); + /* disable the usders bit */ + FLASH->ctrl_bit.usders = FALSE; - /* erase the user system data */ - FLASH->ctrl_bit.usders = TRUE; - FLASH->ctrl_bit.erstr = TRUE; + if((status == FLASH_OPERATE_DONE) && (fap_val == FAP_RELIEVE_KEY)) + { + /* enable the user system data programming operation */ + FLASH->ctrl_bit.usdprgm = TRUE; + + /* restore the last flash access protection value */ + USD->fap = (uint16_t)fap_val; /* wait for operation to be completed */ - status = flash_operation_wait_for(ERASE_TIMEOUT); + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - /* disable the usders bit */ - FLASH->ctrl_bit.usders = FALSE; - - if((status == FLASH_OPERATE_DONE) && (fap_val == FAP_RELIEVE_KEY)) - { - /* enable the user system data programming operation */ - FLASH->ctrl_bit.usdprgm = TRUE; - - /* restore the last flash access protection value */ - USD->fap = (uint16_t)fap_val; - - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - - /*disable the usdprgm bit */ - FLASH->ctrl_bit.usdprgm = FALSE; - } + /*disable the usdprgm bit */ + FLASH->ctrl_bit.usdprgm = FALSE; } + /* return the erase status */ return status; } @@ -441,35 +415,26 @@ flash_status_type flash_word_program(uint32_t address, uint32_t data) /* spim : external flash */ if(address >= FLASH_SPIM_START_ADDR) { - /* wait for last operation to be completed */ + FLASH->ctrl3_bit.fprgm = TRUE; + *(__IO uint32_t*)address = data; + /* wait for operation to be completed */ status = flash_spim_operation_wait_for(SPIM_PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - FLASH->ctrl3_bit.fprgm = TRUE; - *(__IO uint32_t*)address = data; - /* wait for operation to be completed */ - status = flash_spim_operation_wait_for(SPIM_PROGRAMMING_TIMEOUT); + /* disable the fprgm bit */ + FLASH->ctrl3_bit.fprgm = FALSE; - /* disable the fprgm bit */ - FLASH->ctrl3_bit.fprgm = FALSE; - } + /* dummy read */ + flash_spim_dummy_read(); } else { - /* wait for last operation to be completed */ + FLASH->ctrl_bit.fprgm = TRUE; + *(__IO uint32_t*)address = data; + /* wait for operation to be completed */ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - FLASH->ctrl_bit.fprgm = TRUE; - *(__IO uint32_t*)address = data; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - - /* disable the fprgm bit */ - FLASH->ctrl_bit.fprgm = FALSE; - } + /* disable the fprgm bit */ + FLASH->ctrl_bit.fprgm = FALSE; } /* return the program status */ return status; @@ -488,35 +453,26 @@ flash_status_type flash_halfword_program(uint32_t address, uint16_t data) /* spim : external flash */ if(address >= FLASH_SPIM_START_ADDR) { - /* wait for last operation to be completed */ + FLASH->ctrl3_bit.fprgm = TRUE; + *(__IO uint16_t*)address = data; + /* wait for operation to be completed */ status = flash_spim_operation_wait_for(SPIM_PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - FLASH->ctrl3_bit.fprgm = TRUE; - *(__IO uint16_t*)address = data; - /* wait for operation to be completed */ - status = flash_spim_operation_wait_for(SPIM_PROGRAMMING_TIMEOUT); + /* disable the fprgm bit */ + FLASH->ctrl3_bit.fprgm = FALSE; - /* disable the fprgm bit */ - FLASH->ctrl3_bit.fprgm = FALSE; - } + /* dummy read */ + flash_spim_dummy_read(); } else { - /* wait for last operation to be completed */ + FLASH->ctrl_bit.fprgm = TRUE; + *(__IO uint16_t*)address = data; + /* wait for operation to be completed */ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - FLASH->ctrl_bit.fprgm = TRUE; - *(__IO uint16_t*)address = data; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - - /* disable the fprgm bit */ - FLASH->ctrl_bit.fprgm = FALSE; - } + /* disable the fprgm bit */ + FLASH->ctrl_bit.fprgm = FALSE; } /* return the program status */ return status; @@ -533,19 +489,15 @@ flash_status_type flash_halfword_program(uint32_t address, uint16_t data) flash_status_type flash_byte_program(uint32_t address, uint8_t data) { flash_status_type status = FLASH_OPERATE_DONE; - /* wait for last operation to be completed */ + + FLASH->ctrl_bit.fprgm = TRUE; + *(__IO uint8_t*)address = data; + /* wait for operation to be completed */ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - FLASH->ctrl_bit.fprgm = TRUE; - *(__IO uint8_t*)address = data; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); + /* disable the fprgm bit */ + FLASH->ctrl_bit.fprgm = FALSE; - /* disable the fprgm bit */ - FLASH->ctrl_bit.fprgm = FALSE; - } /* return the program status */ return status; } @@ -560,24 +512,28 @@ flash_status_type flash_byte_program(uint32_t address, uint8_t data) flash_status_type flash_user_system_data_program(uint32_t address, uint8_t data) { flash_status_type status = FLASH_OPERATE_DONE; - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) + + if(address == USD_BASE) { - /* unlock the user system data */ - FLASH->usd_unlock = FLASH_UNLOCK_KEY1; - FLASH->usd_unlock = FLASH_UNLOCK_KEY2; - while(FLASH->ctrl_bit.usdulks==RESET); - - /* enable the user system data programming operation */ - FLASH->ctrl_bit.usdprgm = TRUE; - *(__IO uint16_t*)address = data; - - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - - /* disable the usdprgm bit */ - FLASH->ctrl_bit.usdprgm = FALSE; + if(data != 0xA5) + return FLASH_OPERATE_DONE; } + + /* unlock the user system data */ + FLASH->usd_unlock = FLASH_UNLOCK_KEY1; + FLASH->usd_unlock = FLASH_UNLOCK_KEY2; + while(FLASH->ctrl_bit.usdulks==RESET); + + /* enable the user system data programming operation */ + FLASH->ctrl_bit.usdprgm = TRUE; + *(__IO uint16_t*)address = data; + + /* wait for operation to be completed */ + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); + + /* disable the usdprgm bit */ + FLASH->ctrl_bit.usdprgm = FALSE; + /* return the user system data program status */ return status; } @@ -600,42 +556,38 @@ flash_status_type flash_epp_set(uint32_t *sector_bits) epp_data[1] = (uint16_t)((sector_bits[0] >> 8) & 0xFF); epp_data[2] = (uint16_t)((sector_bits[0] >> 16) & 0xFF); epp_data[3] = (uint16_t)((sector_bits[0] >> 24) & 0xFF); - /* wait for last operation to be completed */ + + /* unlock the user system data */ + FLASH->usd_unlock = FLASH_UNLOCK_KEY1; + FLASH->usd_unlock = FLASH_UNLOCK_KEY2; + while(FLASH->ctrl_bit.usdulks==RESET); + + FLASH->ctrl_bit.usdprgm = TRUE; + USD->epp0 = epp_data[0]; + /* wait for operation to be completed */ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); if(status == FLASH_OPERATE_DONE) { - /* unlock the user system data */ - FLASH->usd_unlock = FLASH_UNLOCK_KEY1; - FLASH->usd_unlock = FLASH_UNLOCK_KEY2; - while(FLASH->ctrl_bit.usdulks==RESET); - - FLASH->ctrl_bit.usdprgm = TRUE; - USD->epp0 = epp_data[0]; + USD->epp1 = epp_data[1]; /* wait for operation to be completed */ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - - if(status == FLASH_OPERATE_DONE) - { - USD->epp1 = epp_data[1]; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - } - if(status == FLASH_OPERATE_DONE) - { - USD->epp2 = epp_data[2]; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - } - if(status == FLASH_OPERATE_DONE) - { - USD->epp3 = epp_data[3]; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - } - /* disable the usdprgm bit */ - FLASH->ctrl_bit.usdprgm = FALSE; } + if(status == FLASH_OPERATE_DONE) + { + USD->epp2 = epp_data[2]; + /* wait for operation to be completed */ + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); + } + if(status == FLASH_OPERATE_DONE) + { + USD->epp3 = epp_data[3]; + /* wait for operation to be completed */ + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); + } + /* disable the usdprgm bit */ + FLASH->ctrl_bit.usdprgm = FALSE; + /* return the erase/program protection operation status */ return status; } @@ -663,38 +615,36 @@ void flash_epp_status_get(uint32_t *sector_bits) flash_status_type flash_fap_enable(confirm_state new_state) { flash_status_type status = FLASH_OPERATE_DONE; + + /* unlock the user system data */ + FLASH->usd_unlock = FLASH_UNLOCK_KEY1; + FLASH->usd_unlock = FLASH_UNLOCK_KEY2; + while(FLASH->ctrl_bit.usdulks==RESET); + + FLASH->ctrl_bit.usders = TRUE; + FLASH->ctrl_bit.erstr = TRUE; + /* wait for operation to be completed */ status = flash_operation_wait_for(ERASE_TIMEOUT); + + /* disable the usders bit */ + FLASH->ctrl_bit.usders = FALSE; + if(status == FLASH_OPERATE_DONE) { - /* unlock the user system data */ - FLASH->usd_unlock = FLASH_UNLOCK_KEY1; - FLASH->usd_unlock = FLASH_UNLOCK_KEY2; - while(FLASH->ctrl_bit.usdulks==RESET); - - FLASH->ctrl_bit.usders = TRUE; - FLASH->ctrl_bit.erstr = TRUE; - /* wait for operation to be completed */ - status = flash_operation_wait_for(ERASE_TIMEOUT); - - /* disable the usders bit */ - FLASH->ctrl_bit.usders = FALSE; - - if(status == FLASH_OPERATE_DONE) + if(new_state == FALSE) { - if(new_state == FALSE) - { - /* enable the user system data programming operation */ - FLASH->ctrl_bit.usdprgm = TRUE; - USD->fap = FAP_RELIEVE_KEY; + /* enable the user system data programming operation */ + FLASH->ctrl_bit.usdprgm = TRUE; + USD->fap = FAP_RELIEVE_KEY; - /* Wait for operation to be completed */ - status = flash_operation_wait_for(ERASE_TIMEOUT); + /* Wait for operation to be completed */ + status = flash_operation_wait_for(ERASE_TIMEOUT); - /* disable the usdprgm bit */ - FLASH->ctrl_bit.usdprgm = FALSE; - } + /* disable the usdprgm bit */ + FLASH->ctrl_bit.usdprgm = FALSE; } } + /* return the flash access protection operation status */ return status; } @@ -731,26 +681,22 @@ flag_status flash_fap_status_get(void) flash_status_type flash_ssb_set(uint8_t usd_ssb) { flash_status_type status = FLASH_OPERATE_DONE; - /* wait for last operation to be completed */ + + /* unlock the user system data */ + FLASH->usd_unlock = FLASH_UNLOCK_KEY1; + FLASH->usd_unlock = FLASH_UNLOCK_KEY2; + while(FLASH->ctrl_bit.usdulks==RESET); + + /* enable the user system data programming operation */ + FLASH->ctrl_bit.usdprgm = TRUE; + + USD->ssb = usd_ssb; + /* wait for operation to be completed */ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* unlock the user system data */ - FLASH->usd_unlock = FLASH_UNLOCK_KEY1; - FLASH->usd_unlock = FLASH_UNLOCK_KEY2; - while(FLASH->ctrl_bit.usdulks==RESET); + /* disable the usdprgm bit */ + FLASH->ctrl_bit.usdprgm = FALSE; - /* enable the user system data programming operation */ - FLASH->ctrl_bit.usdprgm = TRUE; - - USD->ssb = usd_ssb; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - - /* disable the usdprgm bit */ - FLASH->ctrl_bit.usdprgm = FALSE; - } /* return the user system data program status */ return status; } @@ -798,6 +744,9 @@ void flash_interrupt_enable(uint32_t flash_int, confirm_state new_state) void flash_spim_model_select(flash_spim_model_type mode) { FLASH->select = mode; + + /* dummy read */ + flash_spim_dummy_read(); } /** @@ -812,6 +761,62 @@ void flash_spim_encryption_range_set(uint32_t decode_address) FLASH->da = decode_address; } +/** + * @brief operate the flash spim dummy read. + * @param none + * @retval none + */ +void flash_spim_dummy_read(void) +{ + UNUSED(*(__IO uint32_t*)FLASH_SPIM_START_ADDR); + UNUSED(*(__IO uint32_t*)(FLASH_SPIM_START_ADDR + 0x1000)); + UNUSED(*(__IO uint32_t*)(FLASH_SPIM_START_ADDR + 0x2000)); +} + +/** + * @brief mass program for flash spim. + * @param address: specifies the start address to be programmed, word or halfword alignment is recommended. + * @param buf: specifies the pointer of data to be programmed. + * @param cnt: specifies the data counter to be programmed. + * @retval status: the returned value can be: FLASH_PROGRAM_ERROR, + * FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT. + */ +flash_status_type flash_spim_mass_program(uint32_t address, uint8_t *buf, uint32_t cnt) +{ + flash_status_type status = FLASH_OPERATE_DONE; + uint32_t index, temp_offset; + if(address >= FLASH_SPIM_START_ADDR) + { + temp_offset = cnt % 4; + if((temp_offset != 0) && (temp_offset != 2)) + return status; + + FLASH->ctrl3_bit.fprgm = TRUE; + for(index = 0; index < cnt / 4; index++) + { + *(__IO uint32_t*)(address + index * 4) = *(uint32_t*)(buf + index * 4); + /* wait for operation to be completed */ + status = flash_spim_operation_wait_for(SPIM_PROGRAMMING_TIMEOUT); + if(status != FLASH_OPERATE_DONE) + return status; + } + if(temp_offset == 2) + { + *(__IO uint16_t*)(address + index * 4) = *(uint16_t*)(buf + index * 4); + /* wait for operation to be completed */ + status = flash_spim_operation_wait_for(SPIM_PROGRAMMING_TIMEOUT); + } + /* disable the fprgm bit */ + FLASH->ctrl3_bit.fprgm = FALSE; + + /* dummy read */ + flash_spim_dummy_read(); + } + + /* return the program status */ + return status; +} + /** * @brief enable security library function. * @param pwd: slib password @@ -825,29 +830,29 @@ flash_status_type flash_slib_enable(uint32_t pwd, uint16_t start_sector, uint16_ { uint32_t slib_range; flash_status_type status = FLASH_OPERATE_DONE; - /* wait for last operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); /*check range param limits*/ if((start_sector>=data_start_sector) || ((data_start_sector > end_sector) && \ (data_start_sector != 0x7FF)) || (start_sector > end_sector)) return FLASH_PROGRAM_ERROR; + + /* unlock slib cfg register */ + FLASH->slib_unlock = SLIB_UNLOCK_KEY; + while(FLASH->slib_misc_sts_bit.slib_ulkf==RESET); + + slib_range = ((uint32_t)(data_start_sector << 11) & FLASH_SLIB_DATA_START_SECTOR) | \ + ((uint32_t)(end_sector << 22) & FLASH_SLIB_END_SECTOR) | \ + (start_sector & FLASH_SLIB_START_SECTOR); + /* configure slib, set pwd and range */ + FLASH->slib_set_pwd = pwd; + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); if(status == FLASH_OPERATE_DONE) { - /* unlock slib cfg register */ - FLASH->slib_unlock = SLIB_UNLOCK_KEY; - while(FLASH->slib_misc_sts_bit.slib_ulkf==RESET); - - slib_range = ((uint32_t)(data_start_sector << 11) & FLASH_SLIB_DATA_START_SECTOR) | \ - ((uint32_t)(end_sector << 22) & FLASH_SLIB_END_SECTOR) | \ - (start_sector & FLASH_SLIB_START_SECTOR); - /* configure slib, set pwd and range */ - FLASH->slib_set_pwd = pwd; - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); FLASH->slib_set_range = slib_range; status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); } + return status; } @@ -911,7 +916,7 @@ uint16_t flash_slib_start_sector_get(void) * @param none * @retval uint16_t */ -uint16_t flash_slib_datstart_sector_get(void) +uint16_t flash_slib_datastart_sector_get(void) { return (uint16_t)FLASH->slib_sts1_bit.slib_dat_ss; } diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_gpio.c b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_gpio.c index cd96b527c6..7041f4b019 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_gpio.c +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_gpio.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_gpio.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the gpio firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -390,7 +388,7 @@ void gpio_bits_write(gpio_type *gpio_x, uint16_t pins, confirm_state bit_state) * @param port_value: specifies the value to be written to the port output data register. * @retval none */ -void gpio_port_wirte(gpio_type *gpio_x, uint16_t port_value) +void gpio_port_write(gpio_type *gpio_x, uint16_t port_value) { gpio_x->odt = port_value; } diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_i2c.c b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_i2c.c index 6612b6e16e..5590275503 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_i2c.c +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_i2c.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_i2c.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the i2c firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -597,11 +595,90 @@ flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag) } /** - * @brief clear flag status + * @brief get interrupt flag status * @param i2c_x: to select the i2c peripheral. * this parameter can be one of the following values: * I2C1, I2C2. * @param flag + * this parameter can be one of the following values: + * - I2C_STARTF_FLAG: start condition generation complete flag. + * - I2C_ADDR7F_FLAG: 0~7 bit address match flag. + * - I2C_TDC_FLAG: transmit data complete flag. + * - I2C_ADDRHF_FLAG: master 9~8 bit address header match flag. + * - I2C_STOPF_FLAG: stop condition generation complete flag. + * - I2C_RDBF_FLAG: receive data buffer full flag. + * - I2C_TDBE_FLAG: transmit data buffer empty flag. + * - I2C_BUSERR_FLAG: bus error flag. + * - I2C_ARLOST_FLAG: arbitration lost flag. + * - I2C_ACKFAIL_FLAG: acknowledge failure flag. + * - I2C_OUF_FLAG: overflow or underflow flag. + * - I2C_PECERR_FLAG: pec receive error flag. + * - I2C_TMOUT_FLAG: smbus timeout flag. + * - I2C_ALERTF_FLAG: smbus alert flag. + * @retval flag_status (SET or RESET) + */ +flag_status i2c_interrupt_flag_get(i2c_type *i2c_x, uint32_t flag) +{ + __IO uint32_t reg = 0, value = 0, iten = 0; + + switch(flag) + { + case I2C_STARTF_FLAG: + case I2C_ADDR7F_FLAG: + case I2C_TDC_FLAG: + case I2C_ADDRHF_FLAG: + case I2C_STOPF_FLAG: + iten = i2c_x->ctrl2_bit.evtien; + break; + case I2C_RDBF_FLAG: + case I2C_TDBE_FLAG: + iten = i2c_x->ctrl2_bit.dataien && i2c_x->ctrl2_bit.evtien; + break; + case I2C_BUSERR_FLAG: + case I2C_ARLOST_FLAG: + case I2C_ACKFAIL_FLAG: + case I2C_OUF_FLAG: + case I2C_PECERR_FLAG: + case I2C_TMOUT_FLAG: + case I2C_ALERTF_FLAG: + iten = i2c_x->ctrl2_bit.errien; + break; + + default: + break; + } + + reg = flag >> 28; + + flag &= (uint32_t)0x00FFFFFF; + + if(reg == 0) + { + value = i2c_x->sts1; + } + else + { + flag = (uint32_t)(flag >> 16); + + value = i2c_x->sts2; + } + + if(((value & flag) != (uint32_t)RESET) && (iten)) + { + return SET; + } + else + { + return RESET; + } +} + +/** + * @brief clear flag status + * @param i2c_x: to select the i2c peripheral. + * this parameter can be one of the following values: + * I2C1, I2C2, I2C3. + * @param flag * this parameter can be any combination of the following values: * - I2C_BUSERR_FLAG: bus error flag. * - I2C_ARLOST_FLAG: arbitration lost flag. @@ -610,11 +687,23 @@ flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag) * - I2C_PECERR_FLAG: pec receive error flag. * - I2C_TMOUT_FLAG: smbus timeout flag. * - I2C_ALERTF_FLAG: smbus alert flag. + * - I2C_STOPF_FLAG: stop condition generation complete flag. + * - I2C_ADDR7F_FLAG: i2c 0~7 bit address match flag. * @retval none */ void i2c_flag_clear(i2c_type *i2c_x, uint32_t flag) { - i2c_x->sts1 = (uint16_t)~(flag & (uint32_t)0x00FFFFFF); + i2c_x->sts1 = (uint16_t)~(flag & (uint32_t)0x0000DF00); + + if(i2c_x->sts1 & I2C_ADDR7F_FLAG) + { + UNUSED(i2c_x->sts2); + } + + if(i2c_x->sts1 & I2C_STOPF_FLAG) + { + i2c_x->ctrl1_bit.i2cen = TRUE; + } } /** diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_misc.c b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_misc.c index cb58807a86..c6d8560793 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_misc.c +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_misc.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_misc.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the misc firmware library ************************************************************************** * Copyright notice & Disclaimer diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_pwc.c b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_pwc.c index d0c93983aa..83960a0f8f 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_pwc.c +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_pwc.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_pwc.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the pwc firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -202,19 +200,6 @@ void pwc_deep_sleep_mode_enter(pwc_deep_sleep_enter_type pwc_deep_sleep_enter) SCB->SCR &= (uint32_t)~0x4; } -/** - * @brief regulate low power consumption in the deep sleep mode - * @param pwc_regulator: set the regulator state. - * this parameter can be one of the following values: - * - PWC_REGULATOR_ON - * - PWC_REGULATOR_LOW_POWER - * @retval none - */ -void pwc_voltage_regulate_set(pwc_regulator_type pwc_regulator) -{ - PWC->ctrl_bit.vrsel = pwc_regulator; -} - /** * @brief enter pwc standby mode * @param none @@ -228,7 +213,10 @@ void pwc_standby_mode_enter(void) #if defined (__CC_ARM) __force_stores(); #endif - __WFI(); + while(1) + { + __WFI(); + } } /** diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_rtc.c b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_rtc.c index a66158b056..d7211875b0 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_rtc.c +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_rtc.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_rtc.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the rtc firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -76,7 +74,7 @@ uint32_t rtc_counter_get(void) /** * @brief rtc divider set - * @param div_value (0x0000_0000 ~ 0xFFFF_FFFF) + * @param div_value (0x0000_0000 ~ 0x000F_FFFF) * @retval none */ void rtc_divider_set(uint32_t div_value) @@ -174,6 +172,31 @@ flag_status rtc_flag_get(uint16_t flag) return status; } +/** + * @brief rtc interrupt flag get + * @param flag + * this parameter can be one of the following values: + * - RTC_TS_FLAG: time second flag. + * - RTC_TA_FLAG: time alarm flag. + * - RTC_OVF_FLAG: overflow flag. + * @retval state of rtc flag + */ +flag_status rtc_interrupt_flag_get(uint16_t flag) +{ + flag_status status = RESET; + + if (((RTC->ctrll & flag) != (uint16_t)RESET) && ((RTC->ctrlh & flag) != (uint16_t)RESET)) + { + status = SET; + } + else + { + status = RESET; + } + + return status; +} + /** * @brief rtc flag clear * @param interrupt_flag @@ -181,7 +204,7 @@ flag_status rtc_flag_get(uint16_t flag) * - RTC_TS_FLAG: time second flag. * - RTC_TA_FLAG: time alarm flag. * - RTC_OVF_FLAG: overflow flag. - * - RTC_CFGF_FLAG: rtc configuration finish flag. + * - RTC_UPDF_FLAG: rtc update finish flag. * @retval none */ void rtc_flag_clear(uint16_t flag) diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_sdio.c b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_sdio.c index 10cfa0501b..e2fdd630d2 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_sdio.c +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_sdio.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_sdio.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the sdio firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -82,22 +80,11 @@ void sdio_power_set(sdio_type *sdio_x, sdio_power_state_type power_state) * @param sdio_x: to select the sdio peripheral. * this parameter can be one of the following values: * SDIO1. - * @retval flag_status (SET or RESET) + * @retval sdio_power_state_type (SDIO_POWER_ON or SDIO_POWER_OFF) */ -flag_status sdio_power_status_get(sdio_type *sdio_x) +sdio_power_state_type sdio_power_status_get(sdio_type *sdio_x) { - flag_status flag = RESET; - - if(sdio_x->pwrctrl_bit.ps == SDIO_POWER_ON) - { - flag = SET; - } - else if(sdio_x->pwrctrl_bit.ps == SDIO_POWER_OFF) - { - flag = RESET; - } - - return flag; + return (sdio_power_state_type)(sdio_x->pwrctrl_bit.ps); } /** @@ -254,6 +241,50 @@ void sdio_interrupt_enable(sdio_type *sdio_x, uint32_t int_opt, confirm_state n } } +/** + * @brief get sdio interrupt flag. + * @param sdio_x: to select the sdio peripheral. + * this parameter can be one of the following values: + * SDIO1. + * @param flag + * this parameter can be one of the following values: + * - SDIO_CMDFAIL_FLAG + * - SDIO_DTFAIL_FLAG + * - SDIO_CMDTIMEOUT_FLAG + * - SDIO_DTTIMEOUT_FLAG + * - SDIO_TXERRU_FLAG + * - SDIO_RXERRO_FLAG + * - SDIO_CMDRSPCMPL_FLAG + * - SDIO_CMDCMPL_FLAG + * - SDIO_DTCMPL_FLAG + * - SDIO_SBITERR_FLAG + * - SDIO_DTBLKCMPL_FLAG + * - SDIO_DOCMD_FLAG + * - SDIO_DOTX_FLAG + * - SDIO_DORX_FLAG + * - SDIO_TXBUFH_FLAG + * - SDIO_RXBUFH_FLAG + * - SDIO_TXBUFF_FLAG + * - SDIO_RXBUFF_FLAG + * - SDIO_TXBUFE_FLAG + * - SDIO_RXBUFE_FLAG + * - SDIO_TXBUF_FLAG + * - SDIO_RXBUF_FLAG + * - SDIO_SDIOIF_FLAG + * @retval flag_status (SET or RESET) + */ +flag_status sdio_interrupt_flag_get(sdio_type *sdio_x, uint32_t flag) +{ + flag_status status = RESET; + + if((sdio_x->inten & flag) && (sdio_x->sts & flag)) + { + status = SET; + } + + return status; +} + /** * @brief get sdio flag. * @param sdio_x: to select the sdio peripheral. diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_spi.c b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_spi.c index 656e4be81e..657f785bb1 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_spi.c +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_spi.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_spi.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the spi firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -559,6 +557,69 @@ flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag) return status; } +/** + * @brief get interrupt flag of the specified spi/i2s peripheral. + * @param spi_x: select the spi/i2s peripheral. + * this parameter can be one of the following values: + * SPI1, SPI2 + * @param spi_i2s_flag: select the spi/i2s flag + * this parameter can be one of the following values: + * - SPI_I2S_RDBF_FLAG + * - SPI_I2S_TDBE_FLAG + * - I2S_TUERR_FLAG (this flag only use in i2s mode) + * - SPI_CCERR_FLAG (this flag only use in spi mode) + * - SPI_MMERR_FLAG (this flag only use in spi mode) + * - SPI_I2S_ROERR_FLAG + * @retval the new state of spi/i2s flag + */ +flag_status spi_i2s_interrupt_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag) +{ + flag_status status = RESET; + + switch(spi_i2s_flag) + { + case SPI_I2S_RDBF_FLAG: + if(spi_x->sts_bit.rdbf && spi_x->ctrl2_bit.rdbfie) + { + status = SET; + } + break; + case SPI_I2S_TDBE_FLAG: + if(spi_x->sts_bit.tdbe && spi_x->ctrl2_bit.tdbeie) + { + status = SET; + } + break; + case I2S_TUERR_FLAG: + if(spi_x->sts_bit.tuerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_CCERR_FLAG: + if(spi_x->sts_bit.ccerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_MMERR_FLAG: + if(spi_x->sts_bit.mmerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_I2S_ROERR_FLAG: + if(spi_x->sts_bit.roerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + default: + break; + }; + return status; +} + /** * @brief clear flag of the specified spi/i2s peripheral. * @param spi_x: select the spi/i2s peripheral. @@ -579,23 +640,21 @@ flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag) */ void spi_i2s_flag_clear(spi_type* spi_x, uint32_t spi_i2s_flag) { - volatile uint32_t temp = 0; - temp = temp; if(spi_i2s_flag == SPI_CCERR_FLAG) spi_x->sts = ~SPI_CCERR_FLAG; else if(spi_i2s_flag == SPI_I2S_RDBF_FLAG) - temp = REG32(&spi_x->dt); + UNUSED(spi_x->dt); else if(spi_i2s_flag == I2S_TUERR_FLAG) - temp = REG32(&spi_x->sts); + UNUSED(spi_x->sts); else if(spi_i2s_flag == SPI_MMERR_FLAG) { - temp = REG32(&spi_x->sts); + UNUSED(spi_x->sts); spi_x->ctrl1 = spi_x->ctrl1; } else if(spi_i2s_flag == SPI_I2S_ROERR_FLAG) { - temp = REG32(&spi_x->dt); - temp = REG32(&spi_x->sts); + UNUSED(spi_x->dt); + UNUSED(spi_x->sts); } } diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_tmr.c b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_tmr.c index 44f3eeb9f3..2b9d367c33 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_tmr.c +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_tmr.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_tmr.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the tmr firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -71,16 +69,20 @@ void tmr_reset(tmr_type *tmr_x) crm_periph_reset(CRM_TMR4_PERIPH_RESET, TRUE); crm_periph_reset(CRM_TMR4_PERIPH_RESET, FALSE); } +#if defined (AT32F413TBU7) || defined (AT32F413Rx) || defined (AT32F413Cx) || \ + defined (AT32F413Kx) else if(tmr_x == TMR5) { crm_periph_reset(CRM_TMR5_PERIPH_RESET, TRUE); crm_periph_reset(CRM_TMR5_PERIPH_RESET, FALSE); } +#if defined (AT32F413CCU7) || defined (AT32F413CCT7) || defined (AT32F413RCT7) else if(tmr_x == TMR8) { crm_periph_reset(CRM_TMR8_PERIPH_RESET, TRUE); crm_periph_reset(CRM_TMR8_PERIPH_RESET, FALSE); } +#endif else if(tmr_x == TMR9) { crm_periph_reset(CRM_TMR9_PERIPH_RESET, TRUE); @@ -96,6 +98,7 @@ void tmr_reset(tmr_type *tmr_x) crm_periph_reset(CRM_TMR11_PERIPH_RESET, TRUE); crm_periph_reset(CRM_TMR11_PERIPH_RESET, FALSE); } +#endif } /** @@ -235,11 +238,7 @@ void tmr_cnt_dir_set(tmr_type *tmr_x, tmr_count_mode_type tmr_cnt_dir) void tmr_repetition_counter_set(tmr_type *tmr_x, uint8_t tmr_rpr_value) { /* set the repetition counter value */ - if((tmr_x == TMR1) || (tmr_x == TMR8)) - - { - tmr_x->rpr_bit.rpr = tmr_rpr_value; - } + tmr_x->rpr_bit.rpr = tmr_rpr_value; } /** @@ -277,8 +276,7 @@ uint32_t tmr_counter_value_get(tmr_type *tmr_x) * this parameter can be one of the following values: * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10, * TMR11 - * @param tmr_div_value (for 16 bit tmr 0x0000~0xFFFF, - * for 32 bit tmr 0x0000_0000~0xFFFF_FFFF) + * @param tmr_div_value (0x0000~0xFFFF) * @retval none */ void tmr_div_value_set(tmr_type *tmr_x, uint32_t tmr_div_value) @@ -319,23 +317,23 @@ uint32_t tmr_div_value_get(tmr_type *tmr_x) void tmr_output_channel_config(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, tmr_output_config_type *tmr_output_struct) { - uint16_t channel_index = 0, channel_c_index = 0, channel = 0; + uint16_t channel_index = 0, channel_c_index = 0, channel = 0, chx_offset, chcx_offset; + + chx_offset = (8 + tmr_channel); + chcx_offset = (9 + tmr_channel); /* get channel idle state bit position in ctrl2 register */ - channel_index = (uint16_t)(tmr_output_struct->oc_idle_state << (8 + tmr_channel)); + channel_index = (uint16_t)(tmr_output_struct->oc_idle_state << chx_offset); /* get channel complementary idle state bit position in ctrl2 register */ - channel_c_index = (uint16_t)(tmr_output_struct->occ_idle_state << (9 + tmr_channel)); + channel_c_index = (uint16_t)(tmr_output_struct->occ_idle_state << chcx_offset); - if((tmr_x == TMR1) || (tmr_x == TMR8)) - { - /* set output channel complementary idle state */ - tmr_x->ctrl2 &= ~channel_c_index; - tmr_x->ctrl2 |= channel_c_index; - } + /* set output channel complementary idle state */ + tmr_x->ctrl2 &= ~(1<ctrl2 |= channel_c_index; /* set output channel idle state */ - tmr_x->ctrl2 &= ~channel_index; + tmr_x->ctrl2 &= ~(1<ctrl2 |= channel_index; /* set channel output mode */ @@ -363,38 +361,38 @@ void tmr_output_channel_config(tmr_type *tmr_x, tmr_channel_select_type tmr_chan break; } + chx_offset = ((tmr_channel * 2) + 1); + chcx_offset = ((tmr_channel * 2) + 3); + /* get channel polarity bit position in cctrl register */ - channel_index = (uint16_t)(tmr_output_struct->oc_polarity << ((tmr_channel * 2) + 1)); + channel_index = (uint16_t)(tmr_output_struct->oc_polarity << chx_offset); /* get channel complementary polarity bit position in cctrl register */ - channel_c_index = (uint16_t)(tmr_output_struct->occ_polarity << ((tmr_channel * 2) + 3)); + channel_c_index = (uint16_t)(tmr_output_struct->occ_polarity << chcx_offset); - if((tmr_x == TMR1) || (tmr_x == TMR8)) - { - /* set output channel complementary polarity */ - tmr_x->cctrl &= ~channel_c_index; - tmr_x->cctrl |= channel_c_index; - } + /* set output channel complementary polarity */ + tmr_x->cctrl &= ~(1<cctrl |= channel_c_index; /* set output channel polarity */ - tmr_x->cctrl &= ~channel_index; + tmr_x->cctrl &= ~(1<cctrl |= channel_index; + chx_offset = (tmr_channel * 2); + chcx_offset = ((tmr_channel * 2) + 2); + /* get channel enable bit position in cctrl register */ channel_index = (uint16_t)(tmr_output_struct->oc_output_state << (tmr_channel * 2)); /* get channel complementary enable bit position in cctrl register */ channel_c_index = (uint16_t)(tmr_output_struct->occ_output_state << ((tmr_channel * 2) + 2)); - if((tmr_x == TMR1) || (tmr_x == TMR8)) - { - /* set output channel complementary enable bit */ - tmr_x->cctrl &= ~channel_c_index; - tmr_x->cctrl |= channel_c_index; - } + /* set output channel complementary enable bit */ + tmr_x->cctrl &= ~(1<cctrl |= channel_c_index; /* set output channel enable bit */ - tmr_x->cctrl &= ~channel_index; + tmr_x->cctrl &= ~(1<cctrl |= channel_index; } @@ -754,7 +752,12 @@ void tmr_one_cycle_mode_enable(tmr_type *tmr_x, confirm_state new_state) void tmr_32_bit_function_enable (tmr_type *tmr_x, confirm_state new_state) { /* tmr 32 bit function(plus mode) enable,only for TMR2/TMR5 */ - if((tmr_x == TMR2) || (tmr_x == TMR5)) + if((tmr_x == TMR2) +#if defined (AT32F413TBU7) || defined (AT32F413Rx) || defined (AT32F413Cx) || \ + defined (AT32F413Kx) + || (tmr_x == TMR5) +#endif + ) { tmr_x->ctrl1_bit.pmen = new_state; } @@ -815,6 +818,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct switch(channel) { case TMR_SELECT_CHANNEL_1: + tmr_x->cctrl_bit.c1en = FALSE; tmr_x->cctrl_bit.c1p = (uint32_t)input_struct->input_polarity_select; tmr_x->cctrl_bit.c1cp = (input_struct->input_polarity_select & 0x2) >> 1; tmr_x->cm1_input_bit.c1c = input_struct->input_mapped_select; @@ -824,6 +828,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct break; case TMR_SELECT_CHANNEL_2: + tmr_x->cctrl_bit.c2en = FALSE; tmr_x->cctrl_bit.c2p = (uint32_t)input_struct->input_polarity_select; tmr_x->cctrl_bit.c2cp = (input_struct->input_polarity_select & 0x2) >> 1; tmr_x->cm1_input_bit.c2c = input_struct->input_mapped_select; @@ -833,6 +838,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct break; case TMR_SELECT_CHANNEL_3: + tmr_x->cctrl_bit.c3en = FALSE; tmr_x->cctrl_bit.c3p = (uint32_t)input_struct->input_polarity_select; tmr_x->cctrl_bit.c3cp = (input_struct->input_polarity_select & 0x2) >> 1; tmr_x->cm2_input_bit.c3c = input_struct->input_mapped_select; @@ -842,6 +848,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct break; case TMR_SELECT_CHANNEL_4: + tmr_x->cctrl_bit.c4en = FALSE; tmr_x->cctrl_bit.c4p = (uint32_t)input_struct->input_polarity_select; tmr_x->cm2_input_bit.c4c = input_struct->input_mapped_select; tmr_x->cm2_input_bit.c4df = input_struct->input_filter_value; @@ -1076,15 +1083,15 @@ void tmr_pwm_input_config(tmr_type *tmr_x, tmr_input_config_type *input_struct, * @param tmr_x: select the tmr peripheral. * this parameter can be one of the following values: * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8 - * @param ti1_connect + * @param ch1_connect * this parameter can be one of the following values: * - TMR_CHANEL1_CONNECTED_C1IRAW * - TMR_CHANEL1_2_3_CONNECTED_C1IRAW_XOR * @retval none */ -void tmr_channel1_input_select(tmr_type *tmr_x, tmr_channel1_input_connected_type ti1_connect) +void tmr_channel1_input_select(tmr_type *tmr_x, tmr_channel1_input_connected_type ch1_connect) { - tmr_x->ctrl2_bit.c1insel = ti1_connect; + tmr_x->ctrl2_bit.c1insel = ch1_connect; } /** @@ -1319,6 +1326,40 @@ void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state } } +/** + * @brief get tmr interrupt flag + * @param tmr_x: select the tmr peripheral. + * this parameter can be one of the following values: + * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10, + * TMR11 + * @param tmr_flag + * this parameter can be one of the following values: + * - TMR_OVF_FLAG + * - TMR_C1_FLAG + * - TMR_C2_FLAG + * - TMR_C3_FLAG + * - TMR_C4_FLAG + * - TMR_HALL_FLAG + * - TMR_TRIGGER_FLAG + * - TMR_BRK_FLAG + * @retval state of tmr interrupt flag + */ +flag_status tmr_interrupt_flag_get(tmr_type *tmr_x, uint32_t tmr_flag) +{ + flag_status status = RESET; + + if((tmr_x->ists & tmr_flag) && (tmr_x->iden & tmr_flag)) + { + status = SET; + } + else + { + status = RESET; + } + + return status; +} + /** * @brief get tmr flag * @param tmr_x: select the tmr peripheral. @@ -1704,7 +1745,7 @@ void tmr_dma_control_config(tmr_type *tmr_x, tmr_dma_transfer_length_type dma_le } /** - * @brief config tmr break mode and dead-time + * @brief config tmr brake mode and dead-time * @param tmr_x: select the tmr peripheral. * this parameter can be one of the following values: * TMR1, TMR8 diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_usart.c b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_usart.c index 14e5210faa..4acbc62d8d 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_usart.c +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_usart.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_usart.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the usart firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -61,11 +59,14 @@ void usart_reset(usart_type* usart_x) crm_periph_reset(CRM_USART2_PERIPH_RESET, TRUE); crm_periph_reset(CRM_USART2_PERIPH_RESET, FALSE); } +#if defined (AT32F413Rx) || defined (AT32F413Cx) || defined (AT32FEBKC8T7) else if(usart_x == USART3) { crm_periph_reset(CRM_USART3_PERIPH_RESET, TRUE); crm_periph_reset(CRM_USART3_PERIPH_RESET, FALSE); } +#endif +#if defined (AT32F413Rx) else if(usart_x == UART4) { crm_periph_reset(CRM_UART4_PERIPH_RESET, TRUE); @@ -76,6 +77,7 @@ void usart_reset(usart_type* usart_x) crm_periph_reset(CRM_UART5_PERIPH_RESET, TRUE); crm_periph_reset(CRM_UART5_PERIPH_RESET, FALSE); } +#endif } /** @@ -88,6 +90,9 @@ void usart_reset(usart_type* usart_x) * this parameter can be one of the following values: * - USART_DATA_8BITS * - USART_DATA_9BITS. + * note: + * - when parity check is disabled, the data bit width is the actual data bit number. + * - when parity check is enabled, the data bit width is the actual data bit number minus 1, and the MSB bit is replaced with the parity bit. * @param stop_bit: stop bits transmitted * this parameter can be one of the following values: * - USART_STOP_1_BIT @@ -568,6 +573,79 @@ flag_status usart_flag_get(usart_type* usart_x, uint32_t flag) } } +/** + * @brief check whether the specified usart interrupt flag is set or not. + * @param usart_x: select the usart or the uart peripheral. + * this parameter can be one of the following values: + * USART1, USART2, USART3, UART4, UART5. + * @param flag: specifies the flag to check. + * this parameter can be one of the following values: + * - USART_CTSCF_FLAG: cts change flag (not available for UART4,UART5) + * - USART_BFF_FLAG: break frame flag + * - USART_TDBE_FLAG: transmit data buffer empty flag + * - USART_TDC_FLAG: transmit data complete flag + * - USART_RDBF_FLAG: receive data buffer full flag + * - USART_IDLEF_FLAG: idle flag + * - USART_ROERR_FLAG: receiver overflow error flag + * - USART_NERR_FLAG: noise error flag + * - USART_FERR_FLAG: framing error flag + * - USART_PERR_FLAG: parity error flag + * @retval the new state of usart_flag (SET or RESET). + */ +flag_status usart_interrupt_flag_get(usart_type* usart_x, uint32_t flag) +{ + flag_status int_status = RESET; + + switch(flag) + { + case USART_CTSCF_FLAG: + int_status = (flag_status)usart_x->ctrl3_bit.ctscfien; + break; + case USART_BFF_FLAG: + int_status = (flag_status)usart_x->ctrl2_bit.bfien; + break; + case USART_TDBE_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.tdbeien; + break; + case USART_TDC_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.tdcien; + break; + case USART_RDBF_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.rdbfien; + break; + case USART_ROERR_FLAG: + int_status = (flag_status)(usart_x->ctrl1_bit.rdbfien || usart_x->ctrl3_bit.errien); + break; + case USART_IDLEF_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.idleien; + break; + case USART_NERR_FLAG: + case USART_FERR_FLAG: + int_status = (flag_status)usart_x->ctrl3_bit.errien; + break; + case USART_PERR_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.perrien; + break; + default: + int_status = RESET; + break; + } + + if(int_status != SET) + { + return RESET; + } + + if(usart_x->sts & flag) + { + return SET; + } + else + { + return RESET; + } +} + /** * @brief clear the usart's pending flags. * @param usart_x: select the usart or the uart peripheral. @@ -579,6 +657,11 @@ flag_status usart_flag_get(usart_type* usart_x, uint32_t flag) * - USART_BFF_FLAG: * - USART_TDC_FLAG: * - USART_RDBF_FLAG: + * - USART_PERR_FLAG: + * - USART_FERR_FLAG: + * - USART_NERR_FLAG: + * - USART_ROERR_FLAG: + * - USART_IDLEF_FLAG: * @note * - USART_PERR_FLAG, USART_FERR_FLAG, USART_NERR_FLAG, USART_ROERR_FLAG and USART_IDLEF_FLAG are cleared by software * sequence: a read operation to usart sts register (usart_flag_get()) @@ -591,7 +674,15 @@ flag_status usart_flag_get(usart_type* usart_x, uint32_t flag) */ void usart_flag_clear(usart_type* usart_x, uint32_t flag) { - usart_x->sts = ~flag; + if(flag & (USART_PERR_FLAG | USART_FERR_FLAG | USART_NERR_FLAG | USART_ROERR_FLAG | USART_IDLEF_FLAG)) + { + UNUSED(usart_x->sts); + UNUSED(usart_x->dt); + } + else + { + usart_x->sts = ~flag; + } } /** diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_usb.c b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_usb.c index cea418ed99..5861f145a1 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_usb.c +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_usb.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_usb.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains the functions for the usb firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -127,6 +125,7 @@ void usb_usbbufs_enable(usbd_type *usbx, confirm_state state) g_usb_packet_address = USB_PACKET_BUFFER_ADDRESS; CRM->misc1_bit.usbbufs = FALSE; } + UNUSED(usbx); } /** @@ -245,6 +244,7 @@ void usb_ept_open(usbd_type *usbx, usb_ept_info *ept_info) USB_SET_TXSTS(ept_info->eptn, USB_TX_DISABLE); } } + UNUSED(usbx); } @@ -304,6 +304,7 @@ void usb_ept_close(usbd_type *usbx, usb_ept_info *ept_info) USB_SET_RXSTS(ept_info->eptn, USB_RX_DISABLE); } } + UNUSED(usbx); } /** @@ -418,6 +419,7 @@ void usb_ept_stall(usbd_type *usbx, usb_ept_info *ept_info) { USB_SET_RXSTS(ept_info->eptn, USB_RX_STALL) } + UNUSED(usbx); } /** @@ -519,6 +521,40 @@ flag_status usb_flag_get(usbd_type *usbx, uint16_t flag) return status; } +/** + * @brief get interrupt flag of usb. + * @param usbx: select the usb peripheral + * @param flag: select the usb flag + * this parameter can be one of the following values: + * - USB_LSOF_FLAG + * - USB_SOF_FLAG + * - USB_RST_FLAG + * - USB_SP_FLAG + * - USB_WK_FLAG + * - USB_BE_FLAG + * - USB_UCFOR_FLAG + * - USB_TC_FLAG + * @retval none + */ +flag_status usb_interrupt_flag_get(usbd_type *usbx, uint16_t flag) +{ + flag_status status = RESET; + + if(flag == USB_TC_FLAG) + { + if(usbx->intsts & USB_TC_FLAG) + status = SET; + } + else + { + if((usbx->intsts & flag) && (usbx->ctrl & flag)) + { + status = SET; + } + } + return status; +} + /** * @brief clear flag of usb. * @param usbx: select the usb peripheral diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_wdt.c b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_wdt.c index 94d779c7a8..d8d13dd61e 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_wdt.c +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_wdt.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_wdt.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the wdt firmware library ************************************************************************** * Copyright notice & Disclaimer diff --git a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_wwdt.c b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_wwdt.c index 6de009cf99..471531a604 100644 --- a/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_wwdt.c +++ b/bsp/at32/libraries/AT32F413_Firmware_Library/drivers/src/at32f413_wwdt.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f413_wwdt.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the wwdt firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -106,6 +104,16 @@ flag_status wwdt_flag_get(void) return (flag_status)WWDT->sts_bit.rldf; } +/** + * @brief wwdt reload counter interrupt flag get + * @param none + * @retval state of reload counter interrupt flag + */ +flag_status wwdt_interrupt_flag_get(void) +{ + return (flag_status)(WWDT->sts_bit.rldf && WWDT->cfg_bit.rldien); +} + /** * @brief wwdt counter value set * @param wwdt_cnt (0x40~0x7f) diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/cmsis/cm4/device_support/system_at32f415.c b/bsp/at32/libraries/AT32F415_Firmware_Library/cmsis/cm4/device_support/system_at32f415.c index bd1e931849..3d7cfff865 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/cmsis/cm4/device_support/system_at32f415.c +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/cmsis/cm4/device_support/system_at32f415.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file system_at32f415.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for cmsis cortex-m4 system source file ************************************************************************** * Copyright notice & Disclaimer diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/cmsis/cm4/device_support/system_at32f415.h b/bsp/at32/libraries/AT32F415_Firmware_Library/cmsis/cm4/device_support/system_at32f415.h index fee8791971..32f4107388 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/cmsis/cm4/device_support/system_at32f415.h +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/cmsis/cm4/device_support/system_at32f415.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file system_at32f415.h - * @version v2.0.5 - * @date 2022-05-20 * @brief cmsis cortex-m4 system header file. ************************************************************************** * Copyright notice & Disclaimer @@ -45,6 +43,11 @@ extern "C" { #define HEXT_STABLE_DELAY (5000u) #define PLL_STABLE_DELAY (500u) +#define SystemCoreClock system_core_clock +#define DUMMY_NOP() {__NOP();__NOP();__NOP();__NOP();__NOP(); \ + __NOP();__NOP();__NOP();__NOP();__NOP(); \ + __NOP();__NOP();__NOP();__NOP();__NOP(); \ + __NOP();__NOP();__NOP();__NOP();__NOP();} /** * @} diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_adc.h b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_adc.h index de84b42322..073592c72f 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_adc.h +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_adc.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_adc.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f415 adc header file ************************************************************************** * Copyright notice & Disclaimer @@ -571,6 +569,7 @@ flag_status adc_preempt_software_trigger_status_get(adc_type *adc_x); uint16_t adc_ordinary_conversion_data_get(adc_type *adc_x); uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel); flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag); +flag_status adc_interrupt_flag_get(adc_type *adc_x, uint8_t adc_flag); void adc_flag_clear(adc_type *adc_x, uint32_t adc_flag); /** diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_can.h b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_can.h index fb37904e87..cd0df047b9 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_can.h +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_can.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_can.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f415 can header file ************************************************************************** * Copyright notice & Disclaimer @@ -352,7 +350,7 @@ typedef struct */ typedef struct { - uint16_t baudrate_div; /*!< baudrate division,this parameter can be 0x001~0x400.*/ + uint16_t baudrate_div; /*!< baudrate division,this parameter can be 0x001~0x1000.*/ can_rsaw_type rsaw_size; /*!< resynchronization adjust width */ @@ -963,6 +961,7 @@ can_error_record_type can_error_type_record_get(can_type* can_x); uint8_t can_receive_error_counter_get(can_type* can_x); uint8_t can_transmit_error_counter_get(can_type* can_x); void can_interrupt_enable(can_type* can_x, uint32_t can_int, confirm_state new_state); +flag_status can_interrupt_flag_get(can_type* can_x, uint32_t can_flag); flag_status can_flag_get(can_type* can_x, uint32_t can_flag); void can_flag_clear(can_type* can_x, uint32_t can_flag); diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_cmp.h b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_cmp.h index f53353eeac..0800235613 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_cmp.h +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_cmp.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_cmp.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f415 cmp header file ************************************************************************** * Copyright notice & Disclaimer @@ -52,10 +50,9 @@ extern "C" { */ typedef enum { - CMP_NON_INVERTING_PA5 = 0x00, /*!< comparator non-inverting connect to pa5 */ - CMP_NON_INVERTING_PA1 = 0x01, /*!< comparator non-inverting connect to pa1 */ - CMP_NON_INVERTING_PA0 = 0x02, /*!< comparator non-inverting connect to pa0 */ - CMP_NON_INVERTING_VSSA = 0x03 /*!< comparator non-inverting connect to vssa */ + CMP_NON_INVERTING_PA5_PA7 = 0x00, /*!< comparator1/2 non-inverting connect to pa5/pa7 */ + CMP_NON_INVERTING_PA1_PA3 = 0x01, /*!< comparator1/2 non-inverting connect to pa1/pa3 */ + CMP_NON_INVERTING_PA0_PA2 = 0x02, /*!< comparator1/2 non-inverting connect to pa0/pa2 */ } cmp_non_inverting_type; /** @@ -69,8 +66,7 @@ typedef enum CMP_INVERTING_VREFINT = 0x03, /*!< comparator inverting connect to vrefint */ CMP_INVERTING_PA4 = 0x04, /*!< comparator inverting connect to pa4 */ CMP_INVERTING_PA5 = 0x05, /*!< comparator inverting connect to pa5 */ - CMP_INVERTING_PA0 = 0x06, /*!< comparator inverting connect to pa0 */ - CMP_INVERTING_PA2 = 0x07 /*!< comparator inverting connect to pa2 */ + CMP_INVERTING_PA0_PA2 = 0x06, /*!< comparator1/2 inverting connect to pa0/pa2 */ } cmp_inverting_type; /** @@ -79,11 +75,12 @@ typedef enum typedef enum { CMP_SPEED_FAST = 0x00, /*!< comparator selected fast speed */ - CMP_SPEED_MEDIUM = 0x01, /*!< comparator selected medium speed */ - CMP_SPEED_SLOW = 0x02, /*!< comparator selected slow speed */ - CMP_SPEED_ULTRALOW = 0x03 /*!< comparator selected ultralow speed */ + CMP_SPEED_SLOW = 0x01, /*!< comparator selected slow speed */ } cmp_speed_type; +#define CMP_OUTPUT_TMR1CXORAW_OFF CMP_OUTPUT_TMR1CHCLR +#define CMP_OUTPUT_TMR2CXORAW_OFF CMP_OUTPUT_TMR2CHCLR +#define CMP_OUTPUT_TMR3CXORAW_OFF CMP_OUTPUT_TMR3CHCLR /** * @brief cmp output type */ @@ -213,6 +210,7 @@ void cmp_enable(cmp_sel_type cmp_sel, confirm_state new_state); void cmp_input_shift_enable(confirm_state new_state); uint32_t cmp_output_value_get(cmp_sel_type cmp_sel); void cmp_write_protect_enable(cmp_sel_type cmp_sel); +void cmp_double_mode_enable(confirm_state new_state); /** * @} diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_crc.h b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_crc.h index 9b4ce4b8ba..980d0f6c27 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_crc.h +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_crc.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_crc.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f415 crc header file ************************************************************************** * Copyright notice & Disclaimer @@ -68,6 +66,17 @@ typedef enum CRC_REVERSE_OUTPUT_DATA = 0x01 /*!< output data reverse by word */ } crc_reverse_output_type; +/** + * @brief crc polynomial size + */ +typedef enum +{ + CRC_POLY_SIZE_32B = 0x00, /*!< polynomial size 32 bits */ + CRC_POLY_SIZE_16B = 0x01, /*!< polynomial size 16 bits */ + CRC_POLY_SIZE_8B = 0x02, /*!< polynomial size 8 bits */ + CRC_POLY_SIZE_7B = 0x03 /*!< polynomial size 7 bits */ +} crc_poly_size_type; + /** * @brief type define crc register all */ @@ -107,7 +116,8 @@ typedef struct struct { __IO uint32_t rst : 1 ; /* [0] */ - __IO uint32_t reserved1 : 4 ; /* [4:1] */ + __IO uint32_t reserved1 : 2 ; /* [2:1] */ + __IO uint32_t poly_size : 2 ; /* [4:3] */ __IO uint32_t revid : 2 ; /* [6:5] */ __IO uint32_t revod : 1 ; /* [7] */ __IO uint32_t reserved2 : 24 ;/* [31:8] */ @@ -131,6 +141,18 @@ typedef struct } idt_bit; }; + /** + * @brief crc polynomial register, offset:0x14 + */ + union + { + __IO uint32_t poly; + struct + { + __IO uint32_t poly : 32; /* [31:0] */ + } poly_bit; + }; + } crc_type; /** @@ -148,10 +170,14 @@ uint32_t crc_one_word_calculate(uint32_t data); uint32_t crc_block_calculate(uint32_t *pbuffer, uint32_t length); uint32_t crc_data_get(void); void crc_common_data_set(uint8_t cdt_value); -uint8_t crc_common_date_get(void); +uint8_t crc_common_data_get(void); void crc_init_data_set(uint32_t value); void crc_reverse_input_data_set(crc_reverse_input_type value); void crc_reverse_output_data_set(crc_reverse_output_type value); +void crc_poly_value_set(uint32_t value); +uint32_t crc_poly_value_get(void); +void crc_poly_size_set(crc_poly_size_type size); +crc_poly_size_type crc_poly_size_get(void); /** * @} diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_crm.h b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_crm.h index 60b14931a6..96d9c694ab 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_crm.h +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_crm.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_crm.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f415 crm header file ************************************************************************** * Copyright notice & Disclaimer @@ -135,7 +133,7 @@ typedef enum CRM_I2C1_PERIPH_CLOCK = MAKE_VALUE(0x1C, 21), /*!< i2c1 periph clock */ CRM_I2C2_PERIPH_CLOCK = MAKE_VALUE(0x1C, 22), /*!< i2c2 periph clock */ CRM_CAN1_PERIPH_CLOCK = MAKE_VALUE(0x1C, 25), /*!< can1 periph clock */ - CRM_PWC_PERIPH_CLOCK = MAKE_VALUE(0x1C, 28), /*!< pwc periph clock */ + CRM_PWC_PERIPH_CLOCK = MAKE_VALUE(0x1C, 28) /*!< pwc periph clock */ } crm_periph_clock_type; @@ -176,7 +174,7 @@ typedef enum CRM_I2C1_PERIPH_RESET = MAKE_VALUE(0x10, 21), /*!< i2c1 periph reset */ CRM_I2C2_PERIPH_RESET = MAKE_VALUE(0x10, 22), /*!< i2c2 periph reset */ CRM_CAN1_PERIPH_RESET = MAKE_VALUE(0x10, 25), /*!< can1 periph reset */ - CRM_PWC_PERIPH_RESET = MAKE_VALUE(0x10, 28), /*!< pwc periph reset */ + CRM_PWC_PERIPH_RESET = MAKE_VALUE(0x10, 28) /*!< pwc periph reset */ } crm_periph_reset_type; @@ -270,7 +268,7 @@ typedef enum CRM_PLL_FREF_8M = 2, /*!< pll refrence clock between 7.8125 mhz and 8.33 mhz */ CRM_PLL_FREF_12M = 3, /*!< pll refrence clock between 8.33 mhz and 12.5 mhz */ CRM_PLL_FREF_16M = 4, /*!< pll refrence clock between 15.625 mhz and 20.83 mhz */ - CRM_PLL_FREF_25M = 5, /*!< pll refrence clock between 20.83 mhz and 31.255 mhz */ + CRM_PLL_FREF_25M = 5 /*!< pll refrence clock between 20.83 mhz and 31.255 mhz */ } crm_pll_fref_type; /** @@ -866,6 +864,7 @@ void crm_reset(void); void crm_lext_bypass(confirm_state new_state); void crm_hext_bypass(confirm_state new_state); flag_status crm_flag_get(uint32_t flag); +flag_status crm_interrupt_flag_get(uint32_t flag); error_status crm_hext_stable_wait(void); void crm_hick_clock_trimming_set(uint8_t trim_value); void crm_hick_clock_calibration_set(uint8_t cali_value); @@ -896,7 +895,7 @@ void crm_hick_sclk_frequency_select(crm_hick_sclk_frequency_type value); void crm_usb_clock_source_select(crm_usb_clock_source_type value); void crm_clkout_div_set(crm_clkout_div_type clkout_div); void crm_otgfs_ep3_remap_enable(confirm_state new_state); -void crm_usbdiv_reset(confirm_state new_state); +void crm_usbdiv_reset(void); /** * @} diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_debug.h b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_debug.h index b44d57ff09..08c7ae6bdf 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_debug.h +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_debug.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_debug.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f415 debug header file ************************************************************************** * Copyright notice & Disclaimer diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_def.h b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_def.h index f861e3b7f8..33d584f40e 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_def.h +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_def.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_def.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f415 macros header file ************************************************************************** * Copyright notice & Disclaimer @@ -62,6 +60,8 @@ extern "C" { #endif #endif +#define UNUSED(x) (void)x /* to avoid gcc/g++ warnings */ + #ifdef __cplusplus } #endif diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_dma.h b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_dma.h index cf88b9ce99..c94c30ec5f 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_dma.h +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_dma.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_dma.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f415 dma header file ************************************************************************** * Copyright notice & Disclaimer @@ -500,6 +498,7 @@ void dma_data_number_set(dma_channel_type* dmax_channely, uint16_t data_number); uint16_t dma_data_number_get(dma_channel_type* dmax_channely); void dma_interrupt_enable(dma_channel_type* dmax_channely, uint32_t dma_int, confirm_state new_state); flag_status dma_flag_get(uint32_t dmax_flag); +flag_status dma_interrupt_flag_get(uint32_t dmax_flag); void dma_flag_clear(uint32_t dmax_flag); diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_ertc.h b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_ertc.h index 9afe8eb4a3..268654d395 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_ertc.h +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_ertc.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_ertc.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f415 ertc header file ************************************************************************** * Copyright notice & Disclaimer @@ -89,6 +87,12 @@ extern "C" { #define ERTC_ALARM_MASK_DATE_WEEK ((uint32_t)0x80000000) /*!< ertc alarm don't match date or week */ #define ERTC_ALARM_MASK_ALL ((uint32_t)0x80808080) /*!< ertc alarm don't match all */ +/** + * @brief compatible with older versions + */ +#define ERTC_WAT_CLK_CK_A_16BITS ERTC_WAT_CLK_CK_B_16BITS +#define ERTC_WAT_CLK_CK_A_17BITS ERTC_WAT_CLK_CK_B_17BITS + /** * @} */ @@ -166,8 +170,8 @@ typedef enum ERTC_WAT_CLK_ERTCCLK_DIV8 = 0x01, /*!< the wake up timer clock is ERTC_CLK / 8 */ ERTC_WAT_CLK_ERTCCLK_DIV4 = 0x02, /*!< the wake up timer clock is ERTC_CLK / 4 */ ERTC_WAT_CLK_ERTCCLK_DIV2 = 0x03, /*!< the wake up timer clock is ERTC_CLK / 2 */ - ERTC_WAT_CLK_CK_A_16BITS = 0x04, /*!< the wake up timer clock is CK_A, wakeup counter = ERTC_WAT */ - ERTC_WAT_CLK_CK_A_17BITS = 0x06 /*!< the wake up timer clock is CK_A, wakeup counter = ERTC_WAT + 65535 */ + ERTC_WAT_CLK_CK_B_16BITS = 0x04, /*!< the wake up timer clock is CK_B, wakeup counter = ERTC_WAT */ + ERTC_WAT_CLK_CK_B_17BITS = 0x06 /*!< the wake up timer clock is CK_B, wakeup counter = ERTC_WAT + 65535 */ } ertc_wakeup_clock_type; /** @@ -1172,6 +1176,7 @@ void ertc_tamper_enable(ertc_tamper_select_type tamper_x, confirm_state new_stat void ertc_interrupt_enable(uint32_t source, confirm_state new_state); flag_status ertc_interrupt_get(uint32_t source); flag_status ertc_flag_get(uint32_t flag); +flag_status ertc_interrupt_flag_get(uint32_t flag); void ertc_flag_clear(uint32_t flag); void ertc_bpr_data_write(ertc_dt_type dt, uint32_t data); uint32_t ertc_bpr_data_read(ertc_dt_type dt); diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_exint.h b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_exint.h index 76170acbaa..82cd8d1dc2 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_exint.h +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_exint.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_exint.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f415 exint header file ************************************************************************** * Copyright notice & Disclaimer @@ -211,6 +209,7 @@ void exint_default_para_init(exint_init_type *exint_struct); void exint_init(exint_init_type *exint_struct); void exint_flag_clear(uint32_t exint_line); flag_status exint_flag_get(uint32_t exint_line); +flag_status exint_interrupt_flag_get(uint32_t exint_line); void exint_software_interrupt_event_generate(uint32_t exint_line); void exint_interrupt_enable(uint32_t exint_line, confirm_state new_state); void exint_event_enable(uint32_t exint_line, confirm_state new_state); diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_flash.h b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_flash.h index 8880db8844..f8ac8aa348 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_flash.h +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_flash.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_flash.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f415 flash header file ************************************************************************** * Copyright notice & Disclaimer @@ -141,7 +139,7 @@ extern "C" { * - FLASH_WAIT_CYCLE_3 * - FLASH_WAIT_CYCLE_4 */ -#define flash_psr_set(wtcyc) (FLASH->psr |= (uint32_t)(0x150 | wtcyc)) +#define flash_psr_set(wtcyc) (FLASH->psr = (uint32_t)(0x10 | wtcyc)) /** @defgroup FLASH_exported_types * @{ diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_gpio.h b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_gpio.h index 8bf9de4c4a..0fcb059383 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_gpio.h +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_gpio.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_gpio.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f415 gpio header file ************************************************************************** * Copyright notice & Disclaimer @@ -789,7 +787,7 @@ uint16_t gpio_output_data_read(gpio_type *gpio_x); void gpio_bits_set(gpio_type *gpio_x, uint16_t pins); void gpio_bits_reset(gpio_type *gpio_x, uint16_t pins); void gpio_bits_write(gpio_type *gpio_x, uint16_t pins, confirm_state bit_state); -void gpio_port_wirte(gpio_type *gpio_x, uint16_t port_value); +void gpio_port_write(gpio_type *gpio_x, uint16_t port_value); void gpio_pin_wp_config(gpio_type *gpio_x, uint16_t pins); void gpio_event_output_config(gpio_port_source_type gpio_port_source, gpio_pins_source_type gpio_pin_source); void gpio_event_output_enable(confirm_state new_state); diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_i2c.h b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_i2c.h index d3786ba240..1887b2afbd 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_i2c.h +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_i2c.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_i2c.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f415 i2c header file ************************************************************************** * Copyright notice & Disclaimer @@ -380,6 +378,7 @@ void i2c_7bit_address_send(i2c_type *i2c_x, uint8_t address, i2c_direction_type void i2c_data_send(i2c_type *i2c_x, uint8_t data); uint8_t i2c_data_receive(i2c_type *i2c_x); flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag); +flag_status i2c_interrupt_flag_get(i2c_type *i2c_x, uint32_t flag); void i2c_flag_clear(i2c_type *i2c_x, uint32_t flag); /** diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_misc.h b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_misc.h index cc2cb6fb71..5bda9d89de 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_misc.h +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_misc.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_misc.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f415 misc header file ************************************************************************** * Copyright notice & Disclaimer @@ -76,9 +74,9 @@ typedef enum */ typedef enum { - NVIC_LP_SLEEPONEXIT = 0x02, /*!< send event on pending */ + NVIC_LP_SLEEPONEXIT = 0x02, /*!< enable sleep-on-exit feature */ NVIC_LP_SLEEPDEEP = 0x04, /*!< enable sleep-deep output signal when entering sleep mode */ - NVIC_LP_SEVONPEND = 0x10 /*!< enable sleep-on-exit feature */ + NVIC_LP_SEVONPEND = 0x10 /*!< send event on pending */ } nvic_lowpower_mode_type; /** diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_pwc.h b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_pwc.h index 48cb7b9ac6..363cf962ec 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_pwc.h +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_pwc.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_pwc.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f415 pwc header file ************************************************************************** * Copyright notice & Disclaimer @@ -60,7 +58,7 @@ extern "C" { /** * @brief pwc wakeup pin num definition */ -#define PWC_WAKEUP_PIN_1 ((uint32_t)0x00000100) /*!< standby wake-up pin1 */ +#define PWC_WAKEUP_PIN_1 ((uint32_t)0x00000100) /*!< standby wake-up pin1(pa0) */ /** @defgroup PWC_exported_types * @{ diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_sdio.h b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_sdio.h index f8bac257d9..764bf371da 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_sdio.h +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_sdio.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_sdio.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f415 sdio header file ************************************************************************** * Copyright notice & Disclaimer @@ -577,7 +575,7 @@ typedef struct void sdio_reset(sdio_type *sdio_x); void sdio_power_set(sdio_type *sdio_x, sdio_power_state_type power_state); -flag_status sdio_power_status_get(sdio_type *sdio_x); +sdio_power_state_type sdio_power_status_get(sdio_type *sdio_x); void sdio_clock_config(sdio_type *sdio_x, uint16_t clk_div, sdio_edge_phase_type clk_edg); void sdio_bus_width_config(sdio_type *sdio_x, sdio_bus_width_type width); void sdio_clock_bypass(sdio_type *sdio_x, confirm_state new_state); @@ -587,6 +585,7 @@ void sdio_clock_enable(sdio_type *sdio_x, confirm_state new_state); void sdio_dma_enable(sdio_type *sdio_x, confirm_state new_state); void sdio_interrupt_enable(sdio_type *sdio_x, uint32_t int_opt, confirm_state new_state); flag_status sdio_flag_get(sdio_type *sdio_x, uint32_t flag); +flag_status sdio_interrupt_flag_get(sdio_type *sdio_x, uint32_t flag); void sdio_flag_clear(sdio_type *sdio_x, uint32_t flag); void sdio_command_config(sdio_type *sdio_x, sdio_command_struct_type *command_struct); void sdio_command_state_machine_enable(sdio_type *sdio_x, confirm_state new_state); diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_spi.h b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_spi.h index d4852dfd16..484a7faeed 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_spi.h +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_spi.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_spi.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f415 spi header file ************************************************************************** * Copyright notice & Disclaimer @@ -474,6 +472,7 @@ void spi_i2s_dma_receiver_enable(spi_type* spi_x, confirm_state new_state); void spi_i2s_data_transmit(spi_type* spi_x, uint16_t tx_data); uint16_t spi_i2s_data_receive(spi_type* spi_x); flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag); +flag_status spi_i2s_interrupt_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag); void spi_i2s_flag_clear(spi_type* spi_x, uint32_t spi_i2s_flag); /** diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_tmr.h b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_tmr.h index 6f19fd6485..46e983c445 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_tmr.h +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_tmr.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_tmr.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f415 tmr header file ************************************************************************** * Copyright notice & Disclaimer @@ -238,7 +236,7 @@ typedef enum { TMR_CC_CHANNEL_MAPPED_DIRECT = 0x01, /*!< channel is configured as input, mapped direct */ TMR_CC_CHANNEL_MAPPED_INDIRECT = 0x02, /*!< channel is configured as input, mapped indirect */ - TMR_CC_CHANNEL_MAPPED_STI = 0x03 /*!< channel is configured as input, mapped trc */ + TMR_CC_CHANNEL_MAPPED_STI = 0x03 /*!< channel is configured as input, mapped sti */ } tmr_input_direction_mapped_type; /** @@ -391,6 +389,15 @@ typedef enum TMR_WP_LEVEL_1 = 0x03 /*!< tmr write protect level 1 */ }tmr_wp_level_type; +/** + * @brief tmr output channel switch selection type + */ +typedef enum +{ + TMR_CH_SWITCH_SELECT_EXT = 0x00, /*!< tmr output channel switch select ext pin */ + TMR_CH_SWITCH_SELECT_CXORAW_OFF = 0x01, /*!< tmr output channel switch select cxoraw off signal */ +}tmr_ch_switch_select_type ; + /** * @brief tmr output config type */ @@ -489,7 +496,7 @@ typedef struct struct { __IO uint32_t smsel : 3; /* [2:0] */ - __IO uint32_t reserved1 : 1; /* [3] */ + __IO uint32_t cossel : 1; /* [3] */ __IO uint32_t stis : 3; /* [6:4] */ __IO uint32_t sts : 1; /* [7] */ __IO uint32_t esf : 4; /* [11:8] */ @@ -869,6 +876,7 @@ void tmr_output_channel_buffer_enable(tmr_type *tmr_x, tmr_channel_select_type t confirm_state new_state); void tmr_output_channel_immediately_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \ confirm_state new_state); +void tmr_output_channel_switch_select(tmr_type *tmr_x, tmr_ch_switch_select_type switch_sel); void tmr_output_channel_switch_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \ confirm_state new_state); void tmr_one_cycle_mode_enable(tmr_type *tmr_x, confirm_state new_state); @@ -882,7 +890,7 @@ void tmr_input_channel_filter_set(tmr_type *tmr_x, tmr_channel_select_type tmr_c uint16_t filter_value); void tmr_pwm_input_config(tmr_type *tmr_x, tmr_input_config_type *input_struct, \ tmr_channel_input_divider_type divider_factor); -void tmr_channel1_input_select(tmr_type *tmr_x, tmr_channel1_input_connected_type ti1_connect); +void tmr_channel1_input_select(tmr_type *tmr_x, tmr_channel1_input_connected_type ch1_connect); void tmr_input_channel_divider_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \ tmr_channel_input_divider_type divider_factor); void tmr_primary_mode_select(tmr_type *tmr_x, tmr_primary_select_type primary_mode); @@ -894,6 +902,7 @@ void tmr_trigger_input_select(tmr_type *tmr_x, sub_tmr_input_sel_type trigger_se void tmr_sub_sync_mode_set(tmr_type *tmr_x, confirm_state new_state); void tmr_dma_request_enable(tmr_type *tmr_x, tmr_dma_request_type dma_request, confirm_state new_state); void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state new_state); +flag_status tmr_interrupt_flag_get(tmr_type *tmr_x, uint32_t tmr_flag); flag_status tmr_flag_get(tmr_type *tmr_x, uint32_t tmr_flag); void tmr_flag_clear(tmr_type *tmr_x, uint32_t tmr_flag); void tmr_event_sw_trigger(tmr_type *tmr_x, tmr_event_trigger_type tmr_event); diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_usart.h b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_usart.h index 20b43c6f99..4236e75311 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_usart.h +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_usart.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_usart.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f415 usart header file ************************************************************************** * Copyright notice & Disclaimer @@ -318,9 +316,13 @@ typedef struct #define USART1 ((usart_type *) USART1_BASE) #define USART2 ((usart_type *) USART2_BASE) +#if defined (AT32F415Cx) || defined (AT32F415Rx) #define USART3 ((usart_type *) USART3_BASE) +#endif +#if defined (AT32F415Rx) #define UART4 ((usart_type *) UART4_BASE) #define UART5 ((usart_type *) UART5_BASE) +#endif /** @defgroup USART_exported_functions * @{ @@ -354,6 +356,7 @@ void usart_irda_mode_enable(usart_type* usart_x, confirm_state new_state); void usart_irda_low_power_enable(usart_type* usart_x, confirm_state new_state); void usart_hardware_flow_control_set(usart_type* usart_x,usart_hardware_flow_control_type flow_state); flag_status usart_flag_get(usart_type* usart_x, uint32_t flag); +flag_status usart_interrupt_flag_get(usart_type* usart_x, uint32_t flag); void usart_flag_clear(usart_type* usart_x, uint32_t flag); /** diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_usb.h b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_usb.h index 41ec1d405d..2c02ba5fcc 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_usb.h +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_usb.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_usb.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f415 usb header file ************************************************************************** * Copyright notice & Disclaimer @@ -707,6 +705,7 @@ typedef struct __IO uint32_t nptxfspcavail : 16; /* [15:0] */ __IO uint32_t nptxqspcavail : 8; /* [23:16] */ __IO uint32_t nptxqtop : 7; /* [30:24] */ + __IO uint32_t reserved1 : 1; /* [31] */ } gnptxsts_bit; }; diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_wdt.h b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_wdt.h index 3881388747..58afd01f0c 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_wdt.h +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_wdt.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_wdt.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f415 wdt header file ************************************************************************** * Copyright notice & Disclaimer diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_wwdt.h b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_wwdt.h index a79ee9348f..8654f02a6f 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_wwdt.h +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/inc/at32f415_wwdt.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_wwdt.h - * @version v2.0.5 - * @date 2022-05-20 * @brief at32f415 wwdt header file ************************************************************************** * Copyright notice & Disclaimer @@ -136,6 +134,7 @@ void wwdt_flag_clear(void); void wwdt_enable(uint8_t wwdt_cnt); void wwdt_interrupt_enable(void); flag_status wwdt_flag_get(void); +flag_status wwdt_interrupt_flag_get(void); void wwdt_counter_set(uint8_t wwdt_cnt); void wwdt_window_counter_set(uint8_t window_cnt); diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_adc.c b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_adc.c index bb9a9ff73f..d08e298040 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_adc.c +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_adc.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_adc.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the adc firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -84,7 +82,7 @@ void adc_enable(adc_type *adc_x, confirm_state new_state) * - ADC_LEFT_ALIGNMENT * @param ordinary_channel_length: configure the adc ordinary channel sequence length. * this parameter can be: - * - (0x1~0xf) + * - (0x1~0x10) * @retval none */ void adc_base_default_para_init(adc_base_config_type *adc_base_struct) @@ -314,117 +312,42 @@ void adc_voltage_monitor_single_channel_select(adc_type *adc_x, adc_channel_sele */ void adc_ordinary_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime) { - switch(adc_channel) + uint32_t tmp_reg; + if(adc_channel < ADC_CHANNEL_10) { - case ADC_CHANNEL_0: - adc_x->spt2_bit.cspt0 = adc_sampletime; - break; - case ADC_CHANNEL_1: - adc_x->spt2_bit.cspt1 = adc_sampletime; - break; - case ADC_CHANNEL_2: - adc_x->spt2_bit.cspt2 = adc_sampletime; - break; - case ADC_CHANNEL_3: - adc_x->spt2_bit.cspt3 = adc_sampletime; - break; - case ADC_CHANNEL_4: - adc_x->spt2_bit.cspt4 = adc_sampletime; - break; - case ADC_CHANNEL_5: - adc_x->spt2_bit.cspt5 = adc_sampletime; - break; - case ADC_CHANNEL_6: - adc_x->spt2_bit.cspt6 = adc_sampletime; - break; - case ADC_CHANNEL_7: - adc_x->spt2_bit.cspt7 = adc_sampletime; - break; - case ADC_CHANNEL_8: - adc_x->spt2_bit.cspt8 = adc_sampletime; - break; - case ADC_CHANNEL_9: - adc_x->spt2_bit.cspt9 = adc_sampletime; - break; - case ADC_CHANNEL_10: - adc_x->spt1_bit.cspt10 = adc_sampletime; - break; - case ADC_CHANNEL_11: - adc_x->spt1_bit.cspt11 = adc_sampletime; - break; - case ADC_CHANNEL_12: - adc_x->spt1_bit.cspt12 = adc_sampletime; - break; - case ADC_CHANNEL_13: - adc_x->spt1_bit.cspt13 = adc_sampletime; - break; - case ADC_CHANNEL_14: - adc_x->spt1_bit.cspt14 = adc_sampletime; - break; - case ADC_CHANNEL_15: - adc_x->spt1_bit.cspt15 = adc_sampletime; - break; - case ADC_CHANNEL_16: - adc_x->spt1_bit.cspt16 = adc_sampletime; - break; - case ADC_CHANNEL_17: - adc_x->spt1_bit.cspt17 = adc_sampletime; - break; - default: - break; + tmp_reg = adc_x->spt2; + tmp_reg &= ~(0x07 << 3 * adc_channel); + tmp_reg |= adc_sampletime << 3 * adc_channel; + adc_x->spt2 = tmp_reg; } - switch(adc_sequence) + else { - case 1: - adc_x->osq3_bit.osn1 = adc_channel; - break; - case 2: - adc_x->osq3_bit.osn2 = adc_channel; - break; - case 3: - adc_x->osq3_bit.osn3 = adc_channel; - break; - case 4: - adc_x->osq3_bit.osn4 = adc_channel; - break; - case 5: - adc_x->osq3_bit.osn5 = adc_channel; - break; - case 6: - adc_x->osq3_bit.osn6 = adc_channel; - break; - case 7: - adc_x->osq2_bit.osn7 = adc_channel; - break; - case 8: - adc_x->osq2_bit.osn8 = adc_channel; - break; - case 9: - adc_x->osq2_bit.osn9 = adc_channel; - break; - case 10: - adc_x->osq2_bit.osn10 = adc_channel; - break; - case 11: - adc_x->osq2_bit.osn11 = adc_channel; - break; - case 12: - adc_x->osq2_bit.osn12 = adc_channel; - break; - case 13: - adc_x->osq1_bit.osn13 = adc_channel; - break; - case 14: - adc_x->osq1_bit.osn14 = adc_channel; - break; - case 15: - adc_x->osq1_bit.osn15 = adc_channel; - break; - case 16: - adc_x->osq1_bit.osn16 = adc_channel; - break; - default: - break; + tmp_reg = adc_x->spt1; + tmp_reg &= ~(0x07 << 3 * (adc_channel - ADC_CHANNEL_10)); + tmp_reg |= adc_sampletime << 3 * (adc_channel - ADC_CHANNEL_10); + adc_x->spt1 = tmp_reg; + } + + if(adc_sequence >= 13) + { + tmp_reg = adc_x->osq1; + tmp_reg &= ~(0x01F << 5 * (adc_sequence - 13)); + tmp_reg |= adc_channel << 5 * (adc_sequence - 13); + adc_x->osq1 = tmp_reg; + } + else if(adc_sequence >= 7) + { + tmp_reg = adc_x->osq2; + tmp_reg &= ~(0x01F << 5 * (adc_sequence - 7)); + tmp_reg |= adc_channel << 5 * (adc_sequence - 7); + adc_x->osq2 = tmp_reg; + } + else + { + tmp_reg = adc_x->osq3; + tmp_reg &= ~(0x01F << 5 * (adc_sequence - 1)); + tmp_reg |= adc_channel << 5 * (adc_sequence - 1); + adc_x->osq3 = tmp_reg; } } @@ -472,66 +395,23 @@ void adc_preempt_channel_length_set(adc_type *adc_x, uint8_t adc_channel_lenght) */ void adc_preempt_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime) { - uint16_t sequence_index=0; - switch(adc_channel) + uint32_t tmp_reg; + uint8_t sequence_index; + if(adc_channel < ADC_CHANNEL_10) { - case ADC_CHANNEL_0: - adc_x->spt2_bit.cspt0 = adc_sampletime; - break; - case ADC_CHANNEL_1: - adc_x->spt2_bit.cspt1 = adc_sampletime; - break; - case ADC_CHANNEL_2: - adc_x->spt2_bit.cspt2 = adc_sampletime; - break; - case ADC_CHANNEL_3: - adc_x->spt2_bit.cspt3 = adc_sampletime; - break; - case ADC_CHANNEL_4: - adc_x->spt2_bit.cspt4 = adc_sampletime; - break; - case ADC_CHANNEL_5: - adc_x->spt2_bit.cspt5 = adc_sampletime; - break; - case ADC_CHANNEL_6: - adc_x->spt2_bit.cspt6 = adc_sampletime; - break; - case ADC_CHANNEL_7: - adc_x->spt2_bit.cspt7 = adc_sampletime; - break; - case ADC_CHANNEL_8: - adc_x->spt2_bit.cspt8 = adc_sampletime; - break; - case ADC_CHANNEL_9: - adc_x->spt2_bit.cspt9 = adc_sampletime; - break; - case ADC_CHANNEL_10: - adc_x->spt1_bit.cspt10 = adc_sampletime; - break; - case ADC_CHANNEL_11: - adc_x->spt1_bit.cspt11 = adc_sampletime; - break; - case ADC_CHANNEL_12: - adc_x->spt1_bit.cspt12 = adc_sampletime; - break; - case ADC_CHANNEL_13: - adc_x->spt1_bit.cspt13 = adc_sampletime; - break; - case ADC_CHANNEL_14: - adc_x->spt1_bit.cspt14 = adc_sampletime; - break; - case ADC_CHANNEL_15: - adc_x->spt1_bit.cspt15 = adc_sampletime; - break; - case ADC_CHANNEL_16: - adc_x->spt1_bit.cspt16 = adc_sampletime; - break; - case ADC_CHANNEL_17: - adc_x->spt1_bit.cspt17 = adc_sampletime; - break; - default: - break; + tmp_reg = adc_x->spt2; + tmp_reg &= ~(0x07 << 3 * adc_channel); + tmp_reg |= adc_sampletime << 3 * adc_channel; + adc_x->spt2 = tmp_reg; } + else + { + tmp_reg = adc_x->spt1; + tmp_reg &= ~(0x07 << 3 * (adc_channel - ADC_CHANNEL_10)); + tmp_reg |= adc_sampletime << 3 * (adc_channel - ADC_CHANNEL_10); + adc_x->spt1 = tmp_reg; + } + sequence_index = adc_sequence + 3 - adc_x->psq_bit.pclen; switch(sequence_index) { @@ -807,10 +687,10 @@ uint16_t adc_ordinary_conversion_data_get(adc_type *adc_x) * ADC1. * @param adc_preempt_channel: select the preempt channel. * this parameter can be one of the following values: - * - ADC_PREEMPTED_CHANNEL_1 - * - ADC_PREEMPTED_CHANNEL_2 - * - ADC_PREEMPTED_CHANNEL_3 - * - ADC_PREEMPTED_CHANNEL_4 + * - ADC_PREEMPT_CHANNEL_1 + * - ADC_PREEMPT_CHANNEL_2 + * - ADC_PREEMPT_CHANNEL_3 + * - ADC_PREEMPT_CHANNEL_4 * @retval the conversion data for selection preempt channel. */ uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel) @@ -865,6 +745,47 @@ flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag) return status; } +/** + * @brief get interrupt flag of the specified adc peripheral. + * @param adc_x: select the adc peripheral. + * this parameter can be one of the following values: + * ADC1. + * @param adc_flag: select the adc flag. + * this parameter can be one of the following values: + * - ADC_VMOR_FLAG + * - ADC_CCE_FLAG + * - ADC_PCCE_FLAG + * @retval the new state of adc flag status(SET or RESET). + */ +flag_status adc_interrupt_flag_get(adc_type *adc_x, uint8_t adc_flag) +{ + flag_status status = RESET; + switch(adc_flag) + { + case ADC_VMOR_FLAG: + if(adc_x->sts_bit.vmor && adc_x->ctrl1_bit.vmorien) + { + status = SET; + } + break; + case ADC_CCE_FLAG: + if(adc_x->sts_bit.cce && adc_x->ctrl1_bit.cceien) + { + status = SET; + } + break; + case ADC_PCCE_FLAG: + if(adc_x->sts_bit.pcce && adc_x->ctrl1_bit.pcceien) + { + status = SET; + } + break; + default: + break; + } + return status; +} + /** * @brief clear flag of the specified adc peripheral. * @param adc_x: select the adc peripheral. diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_can.c b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_can.c index a9c16ccac4..e5ee91b32c 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_can.c +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_can.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_can.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the can firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -925,6 +923,102 @@ void can_interrupt_enable(can_type* can_x, uint32_t can_int, confirm_state new_s } } +/** + * @brief get interrupt flag of the specified can peripheral. + * @param can_x: select the can peripheral. + * this parameter can be one of the following values: + * CAN1. + * @param can_flag: select the flag. + * this parameter can be one of the following flags: + * - CAN_EAF_FLAG + * - CAN_EPF_FLAG + * - CAN_BOF_FLAG + * - CAN_ETR_FLAG + * - CAN_EOIF_FLAG + * - CAN_TM0TCF_FLAG + * - CAN_TM1TCF_FLAG + * - CAN_TM2TCF_FLAG + * - CAN_RF0MN_FLAG + * - CAN_RF0FF_FLAG + * - CAN_RF0OF_FLAG + * - CAN_RF1MN_FLAG + * - CAN_RF1FF_FLAG + * - CAN_RF1OF_FLAG + * - CAN_QDZIF_FLAG + * - CAN_EDZC_FLAG + * - CAN_TMEF_FLAG + * note:the state of CAN_EDZC_FLAG need to check dzc and edzif bit + * note:the state of CAN_TMEF_FLAG need to check rqc0,rqc1 and rqc2 bit + * @retval status of can_flag, the returned value can be:SET or RESET. + */ +flag_status can_interrupt_flag_get(can_type* can_x, uint32_t can_flag) +{ + flag_status bit_status = RESET; + flag_status int_status = RESET; + + switch(can_flag) + { + case CAN_EAF_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.eaien); + break; + case CAN_EPF_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.epien); + break; + case CAN_BOF_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.boien); + break; + case CAN_ETR_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.etrien); + break; + case CAN_EOIF_FLAG: + int_status = (flag_status)can_x->inten_bit.eoien; + break; + case CAN_TM0TCF_FLAG: + case CAN_TM1TCF_FLAG: + case CAN_TM2TCF_FLAG: + int_status = (flag_status)can_x->inten_bit.tcien; + break; + case CAN_RF0MN_FLAG: + int_status = (flag_status)can_x->inten_bit.rf0mien; + break; + case CAN_RF0FF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf0fien; + break; + case CAN_RF0OF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf0oien; + break; + case CAN_RF1MN_FLAG: + int_status = (flag_status)can_x->inten_bit.rf1mien; + break; + case CAN_RF1FF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf1fien; + break; + case CAN_RF1OF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf1oien; + break; + case CAN_QDZIF_FLAG: + int_status = (flag_status)can_x->inten_bit.qdzien; + break; + case CAN_EDZC_FLAG: + int_status = (flag_status)can_x->inten_bit.edzien; + break; + case CAN_TMEF_FLAG: + int_status = (flag_status)can_x->inten_bit.tcien; + break; + default: + int_status = RESET; + break; + } + + if(int_status != SET) + { + return RESET; + } + bit_status = can_flag_get(can_x, can_flag); + + return bit_status; +} + /** * @brief get flag of the specified can peripheral. * @param can_x: select the can peripheral. diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_cmp.c b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_cmp.c index 6463bd4154..34f31d14c9 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_cmp.c +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_cmp.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_cmp.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the gpio firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -95,7 +93,7 @@ void cmp_init(cmp_sel_type cmp_sel, cmp_init_type* cmp_init_struct) void cmp_default_para_init(cmp_init_type *cmp_init_struct) { /* reset cmp init structure parameters values */ - cmp_init_struct->cmp_non_inverting = CMP_NON_INVERTING_PA1; + cmp_init_struct->cmp_non_inverting = CMP_NON_INVERTING_PA1_PA3; cmp_init_struct->cmp_inverting = CMP_INVERTING_1_4VREFINT; cmp_init_struct->cmp_speed = CMP_SPEED_FAST; cmp_init_struct->cmp_output = CMP_OUTPUT_NONE; @@ -173,6 +171,16 @@ void cmp_write_protect_enable(cmp_sel_type cmp_sel) } } +/** + * @brief enable or disable double comparator mode + * @param new_state (TRUE or FALSE) + * @retval none + */ +void cmp_double_mode_enable(confirm_state new_state) +{ + CMP->ctrlsts1_bit.dcmpen = new_state; +} + /** * @} */ diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_crc.c b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_crc.c index a7826ae60f..3ed9f1f8cd 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_crc.c +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_crc.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_crc.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the crc firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -106,7 +104,7 @@ void crc_common_data_set(uint8_t cdt_value) * @param none * @retval 8-bit value of the common data register */ -uint8_t crc_common_date_get(void) +uint8_t crc_common_data_get(void) { return (CRC->cdt_bit.cdt); } @@ -149,6 +147,52 @@ void crc_reverse_output_data_set(crc_reverse_output_type value) CRC->ctrl_bit.revod = value; } +/** + * @brief config crc polynomial value + * @param value + * 32-bit new data of crc poly value + * @retval none. + */ +void crc_poly_value_set(uint32_t value) +{ + CRC->poly = value; +} + +/** + * @brief return crc polynomial value + * @param none + * @retval 32-bit value of the polynomial value. + */ +uint32_t crc_poly_value_get(void) +{ + return (CRC->poly); +} + +/** + * @brief config crc polynomial data size + * @param size + * this parameter can be one of the following values: + * - CRC_POLY_SIZE_32B + * - CRC_POLY_SIZE_16B + * - CRC_POLY_SIZE_8B + * - CRC_POLY_SIZE_7B + * @retval none. + */ +void crc_poly_size_set(crc_poly_size_type size) +{ + CRC->ctrl_bit.poly_size = size; +} + +/** + * @brief return crc polynomial data size + * @param none + * @retval polynomial data size. + */ +crc_poly_size_type crc_poly_size_get(void) +{ + return (crc_poly_size_type)(CRC->ctrl_bit.poly_size); +} + /** * @} */ diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_crm.c b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_crm.c index 989a3d9138..a1a6de1bf0 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_crm.c +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_crm.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_crm.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the crm firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -136,6 +134,64 @@ flag_status crm_flag_get(uint32_t flag) return status; } +/** + * @brief get crm interrupt flag status + * @param flag + * this parameter can be one of the following values: + * - CRM_LICK_READY_INT_FLAG + * - CRM_LEXT_READY_INT_FLAG + * - CRM_HICK_READY_INT_FLAG + * - CRM_HEXT_READY_INT_FLAG + * - CRM_PLL_READY_INT_FLAG + * - CRM_CLOCK_FAILURE_INT_FLAG + * @retval flag_status (SET or RESET) + */ +flag_status crm_interrupt_flag_get(uint32_t flag) +{ + flag_status status = RESET; + switch(flag) + { + case CRM_LICK_READY_INT_FLAG: + if(CRM->clkint_bit.lickstblf && CRM->clkint_bit.lickstblien) + { + status = SET; + } + break; + case CRM_LEXT_READY_INT_FLAG: + if(CRM->clkint_bit.lextstblf && CRM->clkint_bit.lextstblien) + { + status = SET; + } + break; + case CRM_HICK_READY_INT_FLAG: + if(CRM->clkint_bit.hickstblf && CRM->clkint_bit.hickstblien) + { + status = SET; + } + break; + case CRM_HEXT_READY_INT_FLAG: + if(CRM->clkint_bit.hextstblf && CRM->clkint_bit.hextstblien) + { + status = SET; + } + break; + case CRM_PLL_READY_INT_FLAG: + if(CRM->clkint_bit.pllstblf && CRM->clkint_bit.pllstblien) + { + status = SET; + } + break; + case CRM_CLOCK_FAILURE_INT_FLAG: + if(CRM->clkint_bit.cfdf && CRM->ctrl_bit.cfden) + { + status = SET; + } + break; + } + + return status; +} + /** * @brief wait for hext stable * @param none @@ -414,6 +470,7 @@ void crm_ahb_div_set(crm_ahb_div_type value) /** * @brief set crm apb1 division + * @note the maximum frequency of APB1/APB2 clock is 75 MHz * @param value * this parameter can be one of the following values: * - CRM_APB1_DIV_1 @@ -430,6 +487,7 @@ void crm_apb1_div_set(crm_apb1_div_type value) /** * @brief set crm apb2 division + * @note the maximum frequency of APB1/APB2 clock is 75 MHz * @param value * this parameter can be one of the following values: * - CRM_APB2_DIV_1 @@ -521,6 +579,7 @@ void crm_pll_config(crm_pll_clock_source_type clock_source, crm_pll_mult_type mu { CRM->cfg_bit.pllrcs = FALSE; pllrcfreq = (HICK_VALUE / 2); + CRM->misc1_bit.hickdiv = CRM_HICK48_NODIV; } else { @@ -610,6 +669,7 @@ void crm_pll_config2(crm_pll_clock_source_type clock_source, uint16_t pll_ns, \ if(clock_source == CRM_PLL_SOURCE_HICK) { CRM->cfg_bit.pllrcs = FALSE; + CRM->misc1_bit.hickdiv = CRM_HICK48_NODIV; } else { @@ -644,6 +704,7 @@ void crm_pll_config2(crm_pll_clock_source_type clock_source, uint16_t pll_ns, \ void crm_sysclk_switch(crm_sclk_type value) { CRM->cfg_bit.sclksel = value; + DUMMY_NOP(); } /** @@ -927,12 +988,13 @@ void crm_otgfs_ep3_remap_enable(confirm_state new_state) * * at32f415xx revision C: (support) * usb divider(CRM_CFG[usbdiv]) support to be reset. - * @param new_state (TRUE or FALSE) + * @param none * @retval none */ -void crm_usbdiv_reset(confirm_state new_state) +void crm_usbdiv_reset(void) { - CRM->otg_extctrl_bit.usbdivrst = new_state; + CRM->otg_extctrl_bit.usbdivrst = 1; + CRM->otg_extctrl_bit.usbdivrst = 0; } /** diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_debug.c b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_debug.c index c05cd3a76e..40f810e92a 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_debug.c +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_debug.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_debug.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the debug firmware library ************************************************************************** * Copyright notice & Disclaimer diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_dma.c b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_dma.c index e1aafacb00..436e2f488d 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_dma.c +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_dma.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_dma.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the dma firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -273,6 +271,52 @@ void dma_flexible_config(dma_type* dma_x, uint8_t flex_channelx, dma_flexible_re } } +/** + * @brief get dma interrupt flag + * @param dmax_flag + * this parameter can be one of the following values: + * - DMA1_FDT1_FLAG - DMA1_HDT1_FLAG - DMA1_DTERR1_FLAG + * - DMA1_FDT2_FLAG - DMA1_HDT2_FLAG - DMA1_DTERR2_FLAG + * - DMA1_FDT3_FLAG - DMA1_HDT3_FLAG - DMA1_DTERR3_FLAG + * - DMA1_FDT4_FLAG - DMA1_HDT4_FLAG - DMA1_DTERR4_FLAG + * - DMA1_FDT5_FLAG - DMA1_HDT5_FLAG - DMA1_DTERR5_FLAG + * - DMA1_FDT6_FLAG - DMA1_HDT6_FLAG - DMA1_DTERR6_FLAG + * - DMA1_FDT7_FLAG - DMA1_HDT7_FLAG - DMA1_DTERR7_FLAG + * - DMA2_FDT1_FLAG - DMA2_HDT1_FLAG - DMA2_DTERR1_FLAG + * - DMA2_FDT2_FLAG - DMA2_HDT2_FLAG - DMA2_DTERR2_FLAG + * - DMA2_FDT3_FLAG - DMA2_HDT3_FLAG - DMA2_DTERR3_FLAG + * - DMA2_FDT4_FLAG - DMA2_HDT4_FLAG - DMA2_DTERR4_FLAG + * - DMA2_FDT5_FLAG - DMA2_HDT5_FLAG - DMA2_DTERR5_FLAG + * - DMA2_FDT6_FLAG - DMA2_HDT6_FLAG - DMA2_DTERR6_FLAG + * - DMA2_FDT7_FLAG - DMA2_HDT7_FLAG - DMA2_DTERR7_FLAG + * @retval state of dma flag + */ +flag_status dma_interrupt_flag_get(uint32_t dmax_flag) +{ + flag_status status = RESET; + uint32_t temp = 0; + + if(dmax_flag > 0x10000000) + { + temp = DMA2->sts; + } + else + { + temp = DMA1->sts; + } + + if ((temp & dmax_flag) != (uint16_t)RESET) + { + status = SET; + } + else + { + status = RESET; + } + + return status; +} + /** * @brief get dma flag * @param dmax_flag diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_ertc.c b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_ertc.c index 40517dcb5d..6ee49f4f9e 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_ertc.c +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_ertc.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_ertc.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the ertc firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -98,15 +96,9 @@ error_status ertc_wait_update(void) { uint32_t timeout = ERTC_TIMEOUT * 2; - /* disable write protection */ - ertc_write_protect_disable(); - /* clear updf flag */ ERTC->sts = ~(ERTC_UPDF_FLAG | 0x00000080) | (ERTC->sts_bit.imen << 7); - /* enable write protection */ - ertc_write_protect_enable(); - while(ERTC->sts_bit.updf == 0) { if(timeout == 0) @@ -164,9 +156,6 @@ error_status ertc_init_mode_enter(void) { uint32_t timeout = ERTC_TIMEOUT * 2; - /* disable write protection */ - ertc_write_protect_disable(); - if(ERTC->sts_bit.imf == 0) { /* enter init mode */ @@ -331,7 +320,7 @@ error_status ertc_date_set(uint8_t year, uint8_t month, uint8_t date, uint8_t we return ERROR; } - /* Set the ertc_DR register */ + /* set the ertc_date register */ ERTC->date = reg.date; /* exit init mode */ @@ -406,7 +395,7 @@ void ertc_calendar_get(ertc_time_type* time) ertc_reg_time_type reg_tm; ertc_reg_date_type reg_dt; - (void) (ERTC->sts); + UNUSED(ERTC->sts); reg_tm.time = ERTC->time; reg_dt.date = ERTC->date; @@ -724,8 +713,8 @@ uint32_t ertc_alarm_sub_second_get(ertc_alarm_type alarm_x) * - ERTC_WAT_CLK_ERTCCLK_DIV8: ERTC_CLK / 8. * - ERTC_WAT_CLK_ERTCCLK_DIV4: ERTC_CLK / 4. * - ERTC_WAT_CLK_ERTCCLK_DIV2: ERTC_CLK / 2. - * - ERTC_WAT_CLK_CK_A_16BITS: CK_A, wakeup counter = ERTC_WAT - * - ERTC_WAT_CLK_CK_A_17BITS: CK_A, wakeup counter = ERTC_WAT + 65535. + * - ERTC_WAT_CLK_CK_B_16BITS: CK_B, wakeup counter = ERTC_WAT + * - ERTC_WAT_CLK_CK_B_17BITS: CK_B, wakeup counter = ERTC_WAT + 65535. * @retval none. */ void ertc_wakeup_clock_set(ertc_wakeup_clock_type clock) @@ -1437,6 +1426,53 @@ flag_status ertc_flag_get(uint32_t flag) } } +/** + * @brief get interrupt flag status. + * @param flag: specifies the flag to check. + * this parameter can be one of the following values: + * - ERTC_ALAF_FLAG: alarm clock a flag. + * - ERTC_ALBF_FLAG: alarm clock b flag. + * - ERTC_WATF_FLAG: wakeup timer flag. + * - ERTC_TSF_FLAG: timestamp flag. + * - ERTC_TP1F_FLAG: tamper detection 1 flag. + * @retval the new state of flag (SET or RESET). + */ +flag_status ertc_interrupt_flag_get(uint32_t flag) +{ + __IO uint32_t iten = 0; + + switch(flag) + { + case ERTC_ALAF_FLAG: + iten = ERTC->ctrl_bit.alaien; + break; + case ERTC_ALBF_FLAG: + iten = ERTC->ctrl_bit.albien; + break; + case ERTC_WATF_FLAG: + iten = ERTC->ctrl_bit.watien; + break; + case ERTC_TSF_FLAG: + iten = ERTC->ctrl_bit.tsien; + break; + case ERTC_TP1F_FLAG: + iten = ERTC->tamp_bit.tpien; + break; + + default: + break; + } + + if(((ERTC->sts & flag) != (uint32_t)RESET) && (iten)) + { + return SET; + } + else + { + return RESET; + } +} + /** * @brief clear flag status * @param flag: specifies the flag to clear. @@ -1481,13 +1517,7 @@ void ertc_bpr_data_write(ertc_dt_type dt, uint32_t data) reg = ERTC_BASE + 0x50 + (dt * 4); - /* disable write protection */ - ertc_write_protect_disable(); - *(__IO uint32_t *)reg = data; - - /* enable write protection */ - ertc_write_protect_enable(); } /** diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_exint.c b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_exint.c index 86be50c982..873a6445c5 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_exint.c +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_exint.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_exint.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the exint firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -155,6 +153,35 @@ flag_status exint_flag_get(uint32_t exint_line) return status; } +/** + * @brief get exint interrupt flag + * @param exint_line + * this parameter can be one of the following values: + * - EXINT_LINE_0 + * - EXINT_LINE_1 + * ... + * - EXINT_LINE_21 + * - EXINT_LINE_22 + * @retval the new state of exint flag(SET or RESET). + */ +flag_status exint_interrupt_flag_get(uint32_t exint_line) +{ + flag_status status = RESET; + uint32_t exint_flag = 0; + exint_flag = EXINT->intsts & exint_line; + exint_flag = exint_flag & EXINT->inten; + + if((exint_flag != (uint16_t)RESET)) + { + status = SET; + } + else + { + status = RESET; + } + return status; +} + /** * @brief generate exint software interrupt event * @param exint_line diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_flash.c b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_flash.c index 5922395942..8ab09d2f8e 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_flash.c +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_flash.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_flash.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the flash firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -173,22 +171,17 @@ void flash_lock(void) flash_status_type flash_sector_erase(uint32_t sector_address) { flash_status_type status = FLASH_OPERATE_DONE; - /* wait for last operation to be completed */ + + FLASH->ctrl_bit.secers = TRUE; + FLASH->addr = sector_address; + FLASH->ctrl_bit.erstr = TRUE; + + /* wait for operation to be completed */ status = flash_operation_wait_for(ERASE_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* if the previous operation is completed, continue to erase the sector */ - FLASH->ctrl_bit.secers = TRUE; - FLASH->addr = sector_address; - FLASH->ctrl_bit.erstr = TRUE; + /* disable the secers bit */ + FLASH->ctrl_bit.secers = FALSE; - /* wait for operation to be completed */ - status = flash_operation_wait_for(ERASE_TIMEOUT); - - /* disable the secers bit */ - FLASH->ctrl_bit.secers = FALSE; - } /* return the erase status */ return status; } @@ -202,21 +195,16 @@ flash_status_type flash_sector_erase(uint32_t sector_address) flash_status_type flash_internal_all_erase(void) { flash_status_type status = FLASH_OPERATE_DONE; - /* wait for last operation to be completed */ + + FLASH->ctrl_bit.bankers = TRUE; + FLASH->ctrl_bit.erstr = TRUE; + + /* wait for operation to be completed */ status = flash_operation_wait_for(ERASE_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* if the previous operation is completed, continue to erase */ - FLASH->ctrl_bit.bankers = TRUE; - FLASH->ctrl_bit.erstr = TRUE; + /* disable the bankers bit */ + FLASH->ctrl_bit.bankers = FALSE; - /* wait for operation to be completed */ - status = flash_operation_wait_for(ERASE_TIMEOUT); - - /* disable the bankers bit */ - FLASH->ctrl_bit.bankers = FALSE; - } /* return the erase status */ return status; } @@ -239,41 +227,36 @@ flash_status_type flash_user_system_data_erase(void) fap_val = 0x0000; } - /* wait for last operation to be completed */ + /* unlock the user system data */ + FLASH->usd_unlock = FLASH_UNLOCK_KEY1; + FLASH->usd_unlock = FLASH_UNLOCK_KEY2; + while(FLASH->ctrl_bit.usdulks==RESET); + + /* erase the user system data */ + FLASH->ctrl_bit.usders = TRUE; + FLASH->ctrl_bit.erstr = TRUE; + + /* wait for operation to be completed */ status = flash_operation_wait_for(ERASE_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* unlock the user system data */ - FLASH->usd_unlock = FLASH_UNLOCK_KEY1; - FLASH->usd_unlock = FLASH_UNLOCK_KEY2; - while(FLASH->ctrl_bit.usdulks==RESET); + /* disable the usders bit */ + FLASH->ctrl_bit.usders = FALSE; - /* erase the user system data */ - FLASH->ctrl_bit.usders = TRUE; - FLASH->ctrl_bit.erstr = TRUE; + if((status == FLASH_OPERATE_DONE) && (fap_val == FAP_RELIEVE_KEY)) + { + /* enable the user system data programming operation */ + FLASH->ctrl_bit.usdprgm = TRUE; + + /* restore the last flash access protection value */ + USD->fap = (uint16_t)fap_val; /* wait for operation to be completed */ - status = flash_operation_wait_for(ERASE_TIMEOUT); + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - /* disable the usders bit */ - FLASH->ctrl_bit.usders = FALSE; - - if((status == FLASH_OPERATE_DONE) && (fap_val == FAP_RELIEVE_KEY)) - { - /* enable the user system data programming operation */ - FLASH->ctrl_bit.usdprgm = TRUE; - - /* restore the last flash access protection value */ - USD->fap = (uint16_t)fap_val; - - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - - /*disable the usdprgm bit */ - FLASH->ctrl_bit.usdprgm = FALSE; - } + /*disable the usdprgm bit */ + FLASH->ctrl_bit.usdprgm = FALSE; } + /* return the erase status */ return status; } @@ -288,19 +271,15 @@ flash_status_type flash_user_system_data_erase(void) flash_status_type flash_word_program(uint32_t address, uint32_t data) { flash_status_type status = FLASH_OPERATE_DONE; - /* wait for last operation to be completed */ + + FLASH->ctrl_bit.fprgm = TRUE; + *(__IO uint32_t*)address = data; + /* wait for operation to be completed */ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - FLASH->ctrl_bit.fprgm = TRUE; - *(__IO uint32_t*)address = data; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); + /* disable the fprgm bit */ + FLASH->ctrl_bit.fprgm = FALSE; - /* disable the fprgm bit */ - FLASH->ctrl_bit.fprgm = FALSE; - } /* return the program status */ return status; } @@ -315,19 +294,15 @@ flash_status_type flash_word_program(uint32_t address, uint32_t data) flash_status_type flash_halfword_program(uint32_t address, uint16_t data) { flash_status_type status = FLASH_OPERATE_DONE; - /* wait for last operation to be completed */ + + FLASH->ctrl_bit.fprgm = TRUE; + *(__IO uint16_t*)address = data; + /* wait for operation to be completed */ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - FLASH->ctrl_bit.fprgm = TRUE; - *(__IO uint16_t*)address = data; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); + /* disable the fprgm bit */ + FLASH->ctrl_bit.fprgm = FALSE; - /* disable the fprgm bit */ - FLASH->ctrl_bit.fprgm = FALSE; - } /* return the program status */ return status; } @@ -342,19 +317,15 @@ flash_status_type flash_halfword_program(uint32_t address, uint16_t data) flash_status_type flash_byte_program(uint32_t address, uint8_t data) { flash_status_type status = FLASH_OPERATE_DONE; - /* wait for last operation to be completed */ + + FLASH->ctrl_bit.fprgm = TRUE; + *(__IO uint8_t*)address = data; + /* wait for operation to be completed */ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - FLASH->ctrl_bit.fprgm = TRUE; - *(__IO uint8_t*)address = data; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); + /* disable the fprgm bit */ + FLASH->ctrl_bit.fprgm = FALSE; - /* disable the fprgm bit */ - FLASH->ctrl_bit.fprgm = FALSE; - } /* return the program status */ return status; } @@ -369,24 +340,22 @@ flash_status_type flash_byte_program(uint32_t address, uint8_t data) flash_status_type flash_user_system_data_program(uint32_t address, uint8_t data) { flash_status_type status = FLASH_OPERATE_DONE; + + /* unlock the user system data */ + FLASH->usd_unlock = FLASH_UNLOCK_KEY1; + FLASH->usd_unlock = FLASH_UNLOCK_KEY2; + while(FLASH->ctrl_bit.usdulks==RESET); + + /* enable the user system data programming operation */ + FLASH->ctrl_bit.usdprgm = TRUE; + *(__IO uint16_t*)address = data; + + /* wait for operation to be completed */ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* unlock the user system data */ - FLASH->usd_unlock = FLASH_UNLOCK_KEY1; - FLASH->usd_unlock = FLASH_UNLOCK_KEY2; - while(FLASH->ctrl_bit.usdulks==RESET); - /* enable the user system data programming operation */ - FLASH->ctrl_bit.usdprgm = TRUE; - *(__IO uint16_t*)address = data; + /* disable the usdprgm bit */ + FLASH->ctrl_bit.usdprgm = FALSE; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - - /* disable the usdprgm bit */ - FLASH->ctrl_bit.usdprgm = FALSE; - } /* return the user system data program status */ return status; } @@ -409,42 +378,38 @@ flash_status_type flash_epp_set(uint32_t *sector_bits) epp_data[1] = (uint16_t)((sector_bits[0] >> 8) & 0xFF); epp_data[2] = (uint16_t)((sector_bits[0] >> 16) & 0xFF); epp_data[3] = (uint16_t)((sector_bits[0] >> 24) & 0xFF); - /* wait for last operation to be completed */ + + /* unlock the user system data */ + FLASH->usd_unlock = FLASH_UNLOCK_KEY1; + FLASH->usd_unlock = FLASH_UNLOCK_KEY2; + while(FLASH->ctrl_bit.usdulks==RESET); + + FLASH->ctrl_bit.usdprgm = TRUE; + USD->epp0 = epp_data[0]; + /* wait for operation to be completed */ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); if(status == FLASH_OPERATE_DONE) { - /* unlock the user system data */ - FLASH->usd_unlock = FLASH_UNLOCK_KEY1; - FLASH->usd_unlock = FLASH_UNLOCK_KEY2; - while(FLASH->ctrl_bit.usdulks==RESET); - - FLASH->ctrl_bit.usdprgm = TRUE; - USD->epp0 = epp_data[0]; + USD->epp1 = epp_data[1]; /* wait for operation to be completed */ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - - if(status == FLASH_OPERATE_DONE) - { - USD->epp1 = epp_data[1]; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - } - if(status == FLASH_OPERATE_DONE) - { - USD->epp2 = epp_data[2]; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - } - if(status == FLASH_OPERATE_DONE) - { - USD->epp3 = epp_data[3]; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - } - /* disable the usdprgm bit */ - FLASH->ctrl_bit.usdprgm = FALSE; } + if(status == FLASH_OPERATE_DONE) + { + USD->epp2 = epp_data[2]; + /* wait for operation to be completed */ + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); + } + if(status == FLASH_OPERATE_DONE) + { + USD->epp3 = epp_data[3]; + /* wait for operation to be completed */ + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); + } + /* disable the usdprgm bit */ + FLASH->ctrl_bit.usdprgm = FALSE; + /* return the erase/program protection operation status */ return status; } @@ -472,38 +437,36 @@ void flash_epp_status_get(uint32_t *sector_bits) flash_status_type flash_fap_enable(confirm_state new_state) { flash_status_type status = FLASH_OPERATE_DONE; + + /* unlock the user system data */ + FLASH->usd_unlock = FLASH_UNLOCK_KEY1; + FLASH->usd_unlock = FLASH_UNLOCK_KEY2; + while(FLASH->ctrl_bit.usdulks==RESET); + + FLASH->ctrl_bit.usders = TRUE; + FLASH->ctrl_bit.erstr = TRUE; + /* wait for operation to be completed */ status = flash_operation_wait_for(ERASE_TIMEOUT); + + /* disable the usders bit */ + FLASH->ctrl_bit.usders = FALSE; + if(status == FLASH_OPERATE_DONE) { - /* unlock the user system data */ - FLASH->usd_unlock = FLASH_UNLOCK_KEY1; - FLASH->usd_unlock = FLASH_UNLOCK_KEY2; - while(FLASH->ctrl_bit.usdulks==RESET); - - FLASH->ctrl_bit.usders = TRUE; - FLASH->ctrl_bit.erstr = TRUE; - /* wait for operation to be completed */ - status = flash_operation_wait_for(ERASE_TIMEOUT); - - /* disable the usders bit */ - FLASH->ctrl_bit.usders = FALSE; - - if(status == FLASH_OPERATE_DONE) + if(new_state == FALSE) { - if(new_state == FALSE) - { - /* enable the user system data programming operation */ - FLASH->ctrl_bit.usdprgm = TRUE; - USD->fap = FAP_RELIEVE_KEY; + /* enable the user system data programming operation */ + FLASH->ctrl_bit.usdprgm = TRUE; + USD->fap = FAP_RELIEVE_KEY; - /* Wait for operation to be completed */ - status = flash_operation_wait_for(ERASE_TIMEOUT); + /* Wait for operation to be completed */ + status = flash_operation_wait_for(ERASE_TIMEOUT); - /* disable the usdprgm bit */ - FLASH->ctrl_bit.usdprgm = FALSE; - } + /* disable the usdprgm bit */ + FLASH->ctrl_bit.usdprgm = FALSE; } } + /* return the flash access protection operation status */ return status; } @@ -530,65 +493,63 @@ flag_status flash_fap_status_get(void) flash_status_type flash_fap_high_level_enable(confirm_state new_state) { flash_status_type status = FLASH_OPERATE_DONE; - status = flash_operation_wait_for(ERASE_TIMEOUT); - if(status == FLASH_OPERATE_DONE) + + /* unlock the user system data */ + FLASH->usd_unlock = FLASH_UNLOCK_KEY1; + FLASH->usd_unlock = FLASH_UNLOCK_KEY2; + while(FLASH->ctrl_bit.usdulks==RESET); + + if(new_state == FALSE) { - /* unlock the user system data */ - FLASH->usd_unlock = FLASH_UNLOCK_KEY1; - FLASH->usd_unlock = FLASH_UNLOCK_KEY2; - while(FLASH->ctrl_bit.usdulks==RESET); + FLASH->ctrl_bit.fap_hl_dis = TRUE; + /* wait for operation to be completed */ + status = flash_operation_wait_for(ERASE_TIMEOUT); - if(new_state == FALSE) + FLASH->ctrl_bit.usders = TRUE; + FLASH->ctrl_bit.erstr = TRUE; + /* wait for operation to be completed */ + status = flash_operation_wait_for(ERASE_TIMEOUT); + + /* disable the usders bit */ + FLASH->ctrl_bit.usders = FALSE; + + if(status == FLASH_OPERATE_DONE) { - FLASH->ctrl_bit.fap_hl_dis = TRUE; + /* enable the user system data programming operation */ + FLASH->ctrl_bit.usdprgm = TRUE; + USD->fap = FAP_RELIEVE_KEY; + /* wait for operation to be completed */ status = flash_operation_wait_for(ERASE_TIMEOUT); - FLASH->ctrl_bit.usders = TRUE; - FLASH->ctrl_bit.erstr = TRUE; - /* wait for operation to be completed */ - status = flash_operation_wait_for(ERASE_TIMEOUT); - - /* disable the usders bit */ - FLASH->ctrl_bit.usders = FALSE; - - if(status == FLASH_OPERATE_DONE) - { - /* enable the user system data programming operation */ - FLASH->ctrl_bit.usdprgm = TRUE; - USD->fap = FAP_RELIEVE_KEY; - - /* wait for operation to be completed */ - status = flash_operation_wait_for(ERASE_TIMEOUT); - - /* disable the usdprgm bit */ - FLASH->ctrl_bit.usdprgm = FALSE; - } - } - else - { - FLASH->ctrl_bit.usders = TRUE; - FLASH->ctrl_bit.erstr = TRUE; - /* wait for operation to be completed */ - status = flash_operation_wait_for(ERASE_TIMEOUT); - - /* disable the usders bit */ - FLASH->ctrl_bit.usders = FALSE; - - if(status == FLASH_OPERATE_DONE) - { - /* enable the user system data programming operation */ - FLASH->ctrl_bit.usdprgm = TRUE; - USD->fap = FAP_HIGH_LEVEL_KEY; - - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - - /* disable the usdprgm bit */ - FLASH->ctrl_bit.usdprgm = FALSE; - } + /* disable the usdprgm bit */ + FLASH->ctrl_bit.usdprgm = FALSE; } } + else + { + FLASH->ctrl_bit.usders = TRUE; + FLASH->ctrl_bit.erstr = TRUE; + /* wait for operation to be completed */ + status = flash_operation_wait_for(ERASE_TIMEOUT); + + /* disable the usders bit */ + FLASH->ctrl_bit.usders = FALSE; + + if(status == FLASH_OPERATE_DONE) + { + /* enable the user system data programming operation */ + FLASH->ctrl_bit.usdprgm = TRUE; + USD->fap = FAP_HIGH_LEVEL_KEY; + + /* wait for operation to be completed */ + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); + + /* disable the usdprgm bit */ + FLASH->ctrl_bit.usdprgm = FALSE; + } + } + /* return the flash access protection operation status */ return status; } @@ -625,26 +586,22 @@ flag_status flash_fap_high_level_status_get(void) flash_status_type flash_ssb_set(uint8_t usd_ssb) { flash_status_type status = FLASH_OPERATE_DONE; - /* wait for last operation to be completed */ + + /* unlock the user system data */ + FLASH->usd_unlock = FLASH_UNLOCK_KEY1; + FLASH->usd_unlock = FLASH_UNLOCK_KEY2; + while(FLASH->ctrl_bit.usdulks==RESET); + + /* enable the user system data programming operation */ + FLASH->ctrl_bit.usdprgm = TRUE; + + USD->ssb = usd_ssb; + /* wait for operation to be completed */ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* unlock the user system data */ - FLASH->usd_unlock = FLASH_UNLOCK_KEY1; - FLASH->usd_unlock = FLASH_UNLOCK_KEY2; - while(FLASH->ctrl_bit.usdulks==RESET); + /* disable the usdprgm bit */ + FLASH->ctrl_bit.usdprgm = FALSE; - /* enable the user system data programming operation */ - FLASH->ctrl_bit.usdprgm = TRUE; - - USD->ssb = usd_ssb; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - - /* disable the usdprgm bit */ - FLASH->ctrl_bit.usdprgm = FALSE; - } /* return the user system data program status */ return status; } @@ -692,29 +649,28 @@ flash_status_type flash_slib_enable(uint32_t pwd, uint16_t start_sector, uint16_ { uint32_t slib_range; flash_status_type status = FLASH_OPERATE_DONE; - /* wait for last operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); /*check range param limits*/ if((start_sector>=data_start_sector) || ((data_start_sector > end_sector) && \ (data_start_sector != 0x7FF)) || (start_sector > end_sector)) return FLASH_PROGRAM_ERROR; + /* unlock slib cfg register */ + FLASH->slib_unlock = SLIB_UNLOCK_KEY; + while(FLASH->slib_misc_sts_bit.slib_ulkf==RESET); + + slib_range = ((uint32_t)(data_start_sector << 11) & FLASH_SLIB_DATA_START_SECTOR) | \ + ((uint32_t)(end_sector << 22) & FLASH_SLIB_END_SECTOR) | \ + (start_sector & FLASH_SLIB_START_SECTOR); + /* configure slib, set pwd and range */ + FLASH->slib_set_pwd = pwd; + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); if(status == FLASH_OPERATE_DONE) { - /* unlock slib cfg register */ - FLASH->slib_unlock = SLIB_UNLOCK_KEY; - while(FLASH->slib_misc_sts_bit.slib_ulkf==RESET); - - slib_range = ((uint32_t)(data_start_sector << 11) & FLASH_SLIB_DATA_START_SECTOR) | \ - ((uint32_t)(end_sector << 22) & FLASH_SLIB_END_SECTOR) | \ - (start_sector & FLASH_SLIB_START_SECTOR); - /* configure slib, set pwd and range */ - FLASH->slib_set_pwd = pwd; - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); FLASH->slib_set_range = slib_range; status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); } + return status; } @@ -824,21 +780,20 @@ void flash_boot_memory_extension_mode_enable(void) flash_status_type flash_extension_memory_slib_enable(uint32_t pwd, uint16_t data_start_sector) { flash_status_type status = FLASH_OPERATE_DONE; - /* wait for last operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); + /* unlock slib cfg register */ + FLASH->slib_unlock = SLIB_UNLOCK_KEY; + while(FLASH->slib_misc_sts_bit.slib_ulkf==RESET); + + /* configure slib, set pwd and range */ + FLASH->slib_set_pwd = pwd; + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); if(status == FLASH_OPERATE_DONE) { - /* unlock slib cfg register */ - FLASH->slib_unlock = SLIB_UNLOCK_KEY; - while(FLASH->slib_misc_sts_bit.slib_ulkf==RESET); - - /* configure slib, set pwd and range */ - FLASH->slib_set_pwd = pwd; - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); FLASH->em_slib_set = (uint32_t)(data_start_sector << 16) + (uint32_t)0x5AA5; status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); } + return status; } diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_gpio.c b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_gpio.c index 5e2cf8036b..8e15cd863f 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_gpio.c +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_gpio.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_gpio.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the gpio firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -390,7 +388,7 @@ void gpio_bits_write(gpio_type *gpio_x, uint16_t pins, confirm_state bit_state) * @param port_value: specifies the value to be written to the port output data register. * @retval none */ -void gpio_port_wirte(gpio_type *gpio_x, uint16_t port_value) +void gpio_port_write(gpio_type *gpio_x, uint16_t port_value) { gpio_x->odt = port_value; } diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_i2c.c b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_i2c.c index 47988ebe5e..ca00f85b02 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_i2c.c +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_i2c.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_i2c.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the i2c firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -597,11 +595,90 @@ flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag) } /** - * @brief clear flag status + * @brief get interrupt flag status * @param i2c_x: to select the i2c peripheral. * this parameter can be one of the following values: * I2C1, I2C2. * @param flag + * this parameter can be one of the following values: + * - I2C_STARTF_FLAG: start condition generation complete flag. + * - I2C_ADDR7F_FLAG: 0~7 bit address match flag. + * - I2C_TDC_FLAG: transmit data complete flag. + * - I2C_ADDRHF_FLAG: master 9~8 bit address header match flag. + * - I2C_STOPF_FLAG: stop condition generation complete flag. + * - I2C_RDBF_FLAG: receive data buffer full flag. + * - I2C_TDBE_FLAG: transmit data buffer empty flag. + * - I2C_BUSERR_FLAG: bus error flag. + * - I2C_ARLOST_FLAG: arbitration lost flag. + * - I2C_ACKFAIL_FLAG: acknowledge failure flag. + * - I2C_OUF_FLAG: overflow or underflow flag. + * - I2C_PECERR_FLAG: pec receive error flag. + * - I2C_TMOUT_FLAG: smbus timeout flag. + * - I2C_ALERTF_FLAG: smbus alert flag. + * @retval flag_status (SET or RESET) + */ +flag_status i2c_interrupt_flag_get(i2c_type *i2c_x, uint32_t flag) +{ + __IO uint32_t reg = 0, value = 0, iten = 0; + + switch(flag) + { + case I2C_STARTF_FLAG: + case I2C_ADDR7F_FLAG: + case I2C_TDC_FLAG: + case I2C_ADDRHF_FLAG: + case I2C_STOPF_FLAG: + iten = i2c_x->ctrl2_bit.evtien; + break; + case I2C_RDBF_FLAG: + case I2C_TDBE_FLAG: + iten = i2c_x->ctrl2_bit.dataien && i2c_x->ctrl2_bit.evtien; + break; + case I2C_BUSERR_FLAG: + case I2C_ARLOST_FLAG: + case I2C_ACKFAIL_FLAG: + case I2C_OUF_FLAG: + case I2C_PECERR_FLAG: + case I2C_TMOUT_FLAG: + case I2C_ALERTF_FLAG: + iten = i2c_x->ctrl2_bit.errien; + break; + + default: + break; + } + + reg = flag >> 28; + + flag &= (uint32_t)0x00FFFFFF; + + if(reg == 0) + { + value = i2c_x->sts1; + } + else + { + flag = (uint32_t)(flag >> 16); + + value = i2c_x->sts2; + } + + if(((value & flag) != (uint32_t)RESET) && (iten)) + { + return SET; + } + else + { + return RESET; + } +} + +/** + * @brief clear flag status + * @param i2c_x: to select the i2c peripheral. + * this parameter can be one of the following values: + * I2C1, I2C2, I2C3. + * @param flag * this parameter can be any combination of the following values: * - I2C_BUSERR_FLAG: bus error flag. * - I2C_ARLOST_FLAG: arbitration lost flag. @@ -610,11 +687,23 @@ flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag) * - I2C_PECERR_FLAG: pec receive error flag. * - I2C_TMOUT_FLAG: smbus timeout flag. * - I2C_ALERTF_FLAG: smbus alert flag. + * - I2C_STOPF_FLAG: stop condition generation complete flag. + * - I2C_ADDR7F_FLAG: i2c 0~7 bit address match flag. * @retval none */ void i2c_flag_clear(i2c_type *i2c_x, uint32_t flag) { - i2c_x->sts1 = (uint16_t)~(flag & (uint32_t)0x00FFFFFF); + i2c_x->sts1 = (uint16_t)~(flag & (uint32_t)0x0000DF00); + + if(i2c_x->sts1 & I2C_ADDR7F_FLAG) + { + UNUSED(i2c_x->sts2); + } + + if(i2c_x->sts1 & I2C_STOPF_FLAG) + { + i2c_x->ctrl1_bit.i2cen = TRUE; + } } /** diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_misc.c b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_misc.c index 90719fde7a..6d31cb3fca 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_misc.c +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_misc.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_misc.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the misc firmware library ************************************************************************** * Copyright notice & Disclaimer diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_pwc.c b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_pwc.c index 75f4134496..28e25dca53 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_pwc.c +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_pwc.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_pwc.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the pwc firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -228,7 +226,10 @@ void pwc_standby_mode_enter(void) #if defined (__CC_ARM) __force_stores(); #endif - __WFI(); + while(1) + { + __WFI(); + } } /** diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_sdio.c b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_sdio.c index d9d878261e..b5ca274473 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_sdio.c +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_sdio.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_sdio.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the sdio firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -82,22 +80,11 @@ void sdio_power_set(sdio_type *sdio_x, sdio_power_state_type power_state) * @param sdio_x: to select the sdio peripheral. * this parameter can be one of the following values: * SDIO1. - * @retval flag_status (SET or RESET) + * @retval sdio_power_state_type (SDIO_POWER_ON or SDIO_POWER_OFF) */ -flag_status sdio_power_status_get(sdio_type *sdio_x) +sdio_power_state_type sdio_power_status_get(sdio_type *sdio_x) { - flag_status flag = RESET; - - if(sdio_x->pwrctrl_bit.ps == SDIO_POWER_ON) - { - flag = SET; - } - else if(sdio_x->pwrctrl_bit.ps == SDIO_POWER_OFF) - { - flag = RESET; - } - - return flag; + return (sdio_power_state_type)(sdio_x->pwrctrl_bit.ps); } /** @@ -254,6 +241,50 @@ void sdio_interrupt_enable(sdio_type *sdio_x, uint32_t int_opt, confirm_state n } } +/** + * @brief get sdio interrupt flag. + * @param sdio_x: to select the sdio peripheral. + * this parameter can be one of the following values: + * SDIO1. + * @param flag + * this parameter can be one of the following values: + * - SDIO_CMDFAIL_FLAG + * - SDIO_DTFAIL_FLAG + * - SDIO_CMDTIMEOUT_FLAG + * - SDIO_DTTIMEOUT_FLAG + * - SDIO_TXERRU_FLAG + * - SDIO_RXERRO_FLAG + * - SDIO_CMDRSPCMPL_FLAG + * - SDIO_CMDCMPL_FLAG + * - SDIO_DTCMPL_FLAG + * - SDIO_SBITERR_FLAG + * - SDIO_DTBLKCMPL_FLAG + * - SDIO_DOCMD_FLAG + * - SDIO_DOTX_FLAG + * - SDIO_DORX_FLAG + * - SDIO_TXBUFH_FLAG + * - SDIO_RXBUFH_FLAG + * - SDIO_TXBUFF_FLAG + * - SDIO_RXBUFF_FLAG + * - SDIO_TXBUFE_FLAG + * - SDIO_RXBUFE_FLAG + * - SDIO_TXBUF_FLAG + * - SDIO_RXBUF_FLAG + * - SDIO_SDIOIF_FLAG + * @retval flag_status (SET or RESET) + */ +flag_status sdio_interrupt_flag_get(sdio_type *sdio_x, uint32_t flag) +{ + flag_status status = RESET; + + if((sdio_x->inten & flag) && (sdio_x->sts & flag)) + { + status = SET; + } + + return status; +} + /** * @brief get sdio flag. * @param sdio_x: to select the sdio peripheral. diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_spi.c b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_spi.c index fc0f41d5ff..b9081f4e41 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_spi.c +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_spi.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_spi.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the spi firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -559,6 +557,69 @@ flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag) return status; } +/** + * @brief get interrupt flag of the specified spi/i2s peripheral. + * @param spi_x: select the spi/i2s peripheral. + * this parameter can be one of the following values: + * SPI1, SPI2 + * @param spi_i2s_flag: select the spi/i2s flag + * this parameter can be one of the following values: + * - SPI_I2S_RDBF_FLAG + * - SPI_I2S_TDBE_FLAG + * - I2S_TUERR_FLAG (this flag only use in i2s mode) + * - SPI_CCERR_FLAG (this flag only use in spi mode) + * - SPI_MMERR_FLAG (this flag only use in spi mode) + * - SPI_I2S_ROERR_FLAG + * @retval the new state of spi/i2s flag + */ +flag_status spi_i2s_interrupt_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag) +{ + flag_status status = RESET; + + switch(spi_i2s_flag) + { + case SPI_I2S_RDBF_FLAG: + if(spi_x->sts_bit.rdbf && spi_x->ctrl2_bit.rdbfie) + { + status = SET; + } + break; + case SPI_I2S_TDBE_FLAG: + if(spi_x->sts_bit.tdbe && spi_x->ctrl2_bit.tdbeie) + { + status = SET; + } + break; + case I2S_TUERR_FLAG: + if(spi_x->sts_bit.tuerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_CCERR_FLAG: + if(spi_x->sts_bit.ccerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_MMERR_FLAG: + if(spi_x->sts_bit.mmerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_I2S_ROERR_FLAG: + if(spi_x->sts_bit.roerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + default: + break; + }; + return status; +} + /** * @brief clear flag of the specified spi/i2s peripheral. * @param spi_x: select the spi/i2s peripheral. @@ -579,23 +640,21 @@ flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag) */ void spi_i2s_flag_clear(spi_type* spi_x, uint32_t spi_i2s_flag) { - volatile uint32_t temp = 0; - temp = temp; if(spi_i2s_flag == SPI_CCERR_FLAG) spi_x->sts = ~SPI_CCERR_FLAG; else if(spi_i2s_flag == SPI_I2S_RDBF_FLAG) - temp = REG32(&spi_x->dt); + UNUSED(spi_x->dt); else if(spi_i2s_flag == I2S_TUERR_FLAG) - temp = REG32(&spi_x->sts); + UNUSED(spi_x->sts); else if(spi_i2s_flag == SPI_MMERR_FLAG) { - temp = REG32(&spi_x->sts); + UNUSED(spi_x->sts); spi_x->ctrl1 = spi_x->ctrl1; } else if(spi_i2s_flag == SPI_I2S_ROERR_FLAG) { - temp = REG32(&spi_x->dt); - temp = REG32(&spi_x->sts); + UNUSED(spi_x->dt); + UNUSED(spi_x->sts); } } diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_tmr.c b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_tmr.c index 9890d8c563..9fe05200ed 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_tmr.c +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_tmr.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_tmr.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the tmr firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -225,11 +223,7 @@ void tmr_cnt_dir_set(tmr_type *tmr_x, tmr_count_mode_type tmr_cnt_dir) void tmr_repetition_counter_set(tmr_type *tmr_x, uint8_t tmr_rpr_value) { /* set the repetition counter value */ - if(tmr_x == TMR1) - - { - tmr_x->rpr_bit.rpr = tmr_rpr_value; - } + tmr_x->rpr_bit.rpr = tmr_rpr_value; } /** @@ -264,8 +258,7 @@ uint32_t tmr_counter_value_get(tmr_type *tmr_x) * @param tmr_x: select the tmr peripheral. * this parameter can be one of the following values: * TMR1, TMR2, TMR3, TMR4, TMR5, TMR9, TMR10, TMR11 - * @param tmr_div_value (for 16 bit tmr 0x0000~0xFFFF, - * for 32 bit tmr 0x0000_0000~0xFFFF_FFFF) + * @param tmr_div_value (0x0000~0xFFFF) * @retval none */ void tmr_div_value_set(tmr_type *tmr_x, uint32_t tmr_div_value) @@ -304,23 +297,23 @@ uint32_t tmr_div_value_get(tmr_type *tmr_x) void tmr_output_channel_config(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, tmr_output_config_type *tmr_output_struct) { - uint16_t channel_index = 0, channel_c_index = 0, channel = 0; + uint16_t channel_index = 0, channel_c_index = 0, channel = 0, chx_offset, chcx_offset; + + chx_offset = (8 + tmr_channel); + chcx_offset = (9 + tmr_channel); /* get channel idle state bit position in ctrl2 register */ - channel_index = (uint16_t)(tmr_output_struct->oc_idle_state << (8 + tmr_channel)); + channel_index = (uint16_t)(tmr_output_struct->oc_idle_state << chx_offset); /* get channel complementary idle state bit position in ctrl2 register */ - channel_c_index = (uint16_t)(tmr_output_struct->occ_idle_state << (9 + tmr_channel)); + channel_c_index = (uint16_t)(tmr_output_struct->occ_idle_state << chcx_offset); - if(tmr_x == TMR1) - { - /* set output channel complementary idle state */ - tmr_x->ctrl2 &= ~channel_c_index; - tmr_x->ctrl2 |= channel_c_index; - } + /* set output channel complementary idle state */ + tmr_x->ctrl2 &= ~(1<ctrl2 |= channel_c_index; /* set output channel idle state */ - tmr_x->ctrl2 &= ~channel_index; + tmr_x->ctrl2 &= ~(1<ctrl2 |= channel_index; /* set channel output mode */ @@ -348,38 +341,38 @@ void tmr_output_channel_config(tmr_type *tmr_x, tmr_channel_select_type tmr_chan break; } + chx_offset = ((tmr_channel * 2) + 1); + chcx_offset = ((tmr_channel * 2) + 3); + /* get channel polarity bit position in cctrl register */ - channel_index = (uint16_t)(tmr_output_struct->oc_polarity << ((tmr_channel * 2) + 1)); + channel_index = (uint16_t)(tmr_output_struct->oc_polarity << chx_offset); /* get channel complementary polarity bit position in cctrl register */ - channel_c_index = (uint16_t)(tmr_output_struct->occ_polarity << ((tmr_channel * 2) + 3)); + channel_c_index = (uint16_t)(tmr_output_struct->occ_polarity << chcx_offset); - if(tmr_x == TMR1) - { - /* set output channel complementary polarity */ - tmr_x->cctrl &= ~channel_c_index; - tmr_x->cctrl |= channel_c_index; - } + /* set output channel complementary polarity */ + tmr_x->cctrl &= ~(1<cctrl |= channel_c_index; /* set output channel polarity */ - tmr_x->cctrl &= ~channel_index; + tmr_x->cctrl &= ~(1<cctrl |= channel_index; + chx_offset = (tmr_channel * 2); + chcx_offset = ((tmr_channel * 2) + 2); + /* get channel enable bit position in cctrl register */ channel_index = (uint16_t)(tmr_output_struct->oc_output_state << (tmr_channel * 2)); /* get channel complementary enable bit position in cctrl register */ channel_c_index = (uint16_t)(tmr_output_struct->occ_output_state << ((tmr_channel * 2) + 2)); - if(tmr_x == TMR1) - { - /* set output channel complementary enable bit */ - tmr_x->cctrl &= ~channel_c_index; - tmr_x->cctrl |= channel_c_index; - } + /* set output channel complementary enable bit */ + tmr_x->cctrl &= ~(1<cctrl |= channel_c_index; /* set output channel enable bit */ - tmr_x->cctrl &= ~channel_index; + tmr_x->cctrl &= ~(1<cctrl |= channel_index; } @@ -660,6 +653,23 @@ void tmr_output_channel_immediately_set(tmr_type *tmr_x, tmr_channel_select_type } } +/** + * @brief select tmr output channel switch source + * @param tmr_x: select the tmr peripheral. + * this parameter can be one of the following values: + * TMR1, TMR3 + * @param switch_sel + * this parameter can be one of the following values: + * - TMR_CH_SWITCH_SELECT_EXT + * - TMR_CH_SWITCH_SELECT_CXORAW_OFF + * @retval none + */ +void tmr_output_channel_switch_select(tmr_type *tmr_x, tmr_ch_switch_select_type switch_sel) +{ + /* select tmr output channel switch source */ + tmr_x->stctrl_bit.cossel = switch_sel; +} + /** * @brief set tmr output channel switch * @param tmr_x: select the tmr peripheral. @@ -788,6 +798,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct switch(channel) { case TMR_SELECT_CHANNEL_1: + tmr_x->cctrl_bit.c1en = FALSE; tmr_x->cctrl_bit.c1p = (uint32_t)input_struct->input_polarity_select; tmr_x->cctrl_bit.c1cp = (input_struct->input_polarity_select & 0x2) >> 1; tmr_x->cm1_input_bit.c1c = input_struct->input_mapped_select; @@ -797,6 +808,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct break; case TMR_SELECT_CHANNEL_2: + tmr_x->cctrl_bit.c2en = FALSE; tmr_x->cctrl_bit.c2p = (uint32_t)input_struct->input_polarity_select; tmr_x->cctrl_bit.c2cp = (input_struct->input_polarity_select & 0x2) >> 1; tmr_x->cm1_input_bit.c2c = input_struct->input_mapped_select; @@ -806,6 +818,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct break; case TMR_SELECT_CHANNEL_3: + tmr_x->cctrl_bit.c3en = FALSE; tmr_x->cctrl_bit.c3p = (uint32_t)input_struct->input_polarity_select; tmr_x->cctrl_bit.c3cp = (input_struct->input_polarity_select & 0x2) >> 1; tmr_x->cm2_input_bit.c3c = input_struct->input_mapped_select; @@ -815,6 +828,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct break; case TMR_SELECT_CHANNEL_4: + tmr_x->cctrl_bit.c4en = FALSE; tmr_x->cctrl_bit.c4p = (uint32_t)input_struct->input_polarity_select; tmr_x->cm2_input_bit.c4c = input_struct->input_mapped_select; tmr_x->cm2_input_bit.c4df = input_struct->input_filter_value; @@ -1046,15 +1060,15 @@ void tmr_pwm_input_config(tmr_type *tmr_x, tmr_input_config_type *input_struct, * @param tmr_x: select the tmr peripheral. * this parameter can be one of the following values: * TMR1, TMR2, TMR3, TMR4, TMR5 - * @param ti1_connect + * @param ch1_connect * this parameter can be one of the following values: * - TMR_CHANEL1_CONNECTED_C1IRAW * - TMR_CHANEL1_2_3_CONNECTED_C1IRAW_XOR * @retval none */ -void tmr_channel1_input_select(tmr_type *tmr_x, tmr_channel1_input_connected_type ti1_connect) +void tmr_channel1_input_select(tmr_type *tmr_x, tmr_channel1_input_connected_type ch1_connect) { - tmr_x->ctrl2_bit.c1insel = ti1_connect; + tmr_x->ctrl2_bit.c1insel = ch1_connect; } /** @@ -1286,6 +1300,39 @@ void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state } } +/** + * @brief get tmr interrupt flag + * @param tmr_x: select the tmr peripheral. + * this parameter can be one of the following values: + * TMR1, TMR2, TMR3, TMR4, TMR5, TMR9, TMR10, TMR11 + * @param tmr_flag + * this parameter can be one of the following values: + * - TMR_OVF_FLAG + * - TMR_C1_FLAG + * - TMR_C2_FLAG + * - TMR_C3_FLAG + * - TMR_C4_FLAG + * - TMR_HALL_FLAG + * - TMR_TRIGGER_FLAG + * - TMR_BRK_FLAG + * @retval state of tmr interrupt flag + */ +flag_status tmr_interrupt_flag_get(tmr_type *tmr_x, uint32_t tmr_flag) +{ + flag_status status = RESET; + + if((tmr_x->ists & tmr_flag) && (tmr_x->iden & tmr_flag)) + { + status = SET; + } + else + { + status = RESET; + } + + return status; +} + /** * @brief get tmr flag * @param tmr_x: select the tmr peripheral. @@ -1666,7 +1713,7 @@ void tmr_dma_control_config(tmr_type *tmr_x, tmr_dma_transfer_length_type dma_le } /** - * @brief config tmr break mode and dead-time + * @brief config tmr brake mode and dead-time * @param tmr_x: select the tmr peripheral. * this parameter can be one of the following values: * TMR1 diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_usart.c b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_usart.c index 3d5e17263f..b3a4c1d251 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_usart.c +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_usart.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_usart.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the usart firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -61,11 +59,14 @@ void usart_reset(usart_type* usart_x) crm_periph_reset(CRM_USART2_PERIPH_RESET, TRUE); crm_periph_reset(CRM_USART2_PERIPH_RESET, FALSE); } +#if defined (AT32F415Cx) || defined (AT32F415Rx) else if(usart_x == USART3) { crm_periph_reset(CRM_USART3_PERIPH_RESET, TRUE); crm_periph_reset(CRM_USART3_PERIPH_RESET, FALSE); } +#endif +#if defined (AT32F415Rx) else if(usart_x == UART4) { crm_periph_reset(CRM_UART4_PERIPH_RESET, TRUE); @@ -76,6 +77,7 @@ void usart_reset(usart_type* usart_x) crm_periph_reset(CRM_UART5_PERIPH_RESET, TRUE); crm_periph_reset(CRM_UART5_PERIPH_RESET, FALSE); } +#endif } /** @@ -88,6 +90,9 @@ void usart_reset(usart_type* usart_x) * this parameter can be one of the following values: * - USART_DATA_8BITS * - USART_DATA_9BITS. + * note: + * - when parity check is disabled, the data bit width is the actual data bit number. + * - when parity check is enabled, the data bit width is the actual data bit number minus 1, and the MSB bit is replaced with the parity bit. * @param stop_bit: stop bits transmitted * this parameter can be one of the following values: * - USART_STOP_1_BIT @@ -568,6 +573,79 @@ flag_status usart_flag_get(usart_type* usart_x, uint32_t flag) } } +/** + * @brief check whether the specified usart interrupt flag is set or not. + * @param usart_x: select the usart or the uart peripheral. + * this parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param flag: specifies the flag to check. + * this parameter can be one of the following values: + * - USART_CTSCF_FLAG: cts change flag (not available for UART4,UART5) + * - USART_BFF_FLAG: break frame flag + * - USART_TDBE_FLAG: transmit data buffer empty flag + * - USART_TDC_FLAG: transmit data complete flag + * - USART_RDBF_FLAG: receive data buffer full flag + * - USART_IDLEF_FLAG: idle flag + * - USART_ROERR_FLAG: receiver overflow error flag + * - USART_NERR_FLAG: noise error flag + * - USART_FERR_FLAG: framing error flag + * - USART_PERR_FLAG: parity error flag + * @retval the new state of usart_flag (SET or RESET). + */ +flag_status usart_interrupt_flag_get(usart_type* usart_x, uint32_t flag) +{ + flag_status int_status = RESET; + + switch(flag) + { + case USART_CTSCF_FLAG: + int_status = (flag_status)usart_x->ctrl3_bit.ctscfien; + break; + case USART_BFF_FLAG: + int_status = (flag_status)usart_x->ctrl2_bit.bfien; + break; + case USART_TDBE_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.tdbeien; + break; + case USART_TDC_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.tdcien; + break; + case USART_RDBF_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.rdbfien; + break; + case USART_ROERR_FLAG: + int_status = (flag_status)(usart_x->ctrl1_bit.rdbfien || usart_x->ctrl3_bit.errien); + break; + case USART_IDLEF_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.idleien; + break; + case USART_NERR_FLAG: + case USART_FERR_FLAG: + int_status = (flag_status)usart_x->ctrl3_bit.errien; + break; + case USART_PERR_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.perrien; + break; + default: + int_status = RESET; + break; + } + + if(int_status != SET) + { + return RESET; + } + + if(usart_x->sts & flag) + { + return SET; + } + else + { + return RESET; + } +} + /** * @brief clear the usart's pending flags. * @param usart_x: select the usart or the uart peripheral. @@ -579,6 +657,11 @@ flag_status usart_flag_get(usart_type* usart_x, uint32_t flag) * - USART_BFF_FLAG: * - USART_TDC_FLAG: * - USART_RDBF_FLAG: + * - USART_PERR_FLAG: + * - USART_FERR_FLAG: + * - USART_NERR_FLAG: + * - USART_ROERR_FLAG: + * - USART_IDLEF_FLAG: * @note * - USART_PERR_FLAG, USART_FERR_FLAG, USART_NERR_FLAG, USART_ROERR_FLAG and USART_IDLEF_FLAG are cleared by software * sequence: a read operation to usart sts register (usart_flag_get()) @@ -591,7 +674,15 @@ flag_status usart_flag_get(usart_type* usart_x, uint32_t flag) */ void usart_flag_clear(usart_type* usart_x, uint32_t flag) { - usart_x->sts = ~flag; + if(flag & (USART_PERR_FLAG | USART_FERR_FLAG | USART_NERR_FLAG | USART_ROERR_FLAG | USART_IDLEF_FLAG)) + { + UNUSED(usart_x->sts); + UNUSED(usart_x->dt); + } + else + { + usart_x->sts = ~flag; + } } /** diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_usb.c b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_usb.c index cb0c758dda..7ec0a09bae 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_usb.c +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_usb.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_usb.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the usb firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -102,7 +100,7 @@ void usb_global_init(otg_global_type *usbx) */ otg_global_type *usb_global_select_core(uint8_t usb_id) { - /* use otg1 */ + UNUSED(usb_id); return OTG1_GLOBAL; } @@ -442,6 +440,7 @@ void usb_read_packet(otg_global_type *usbx, uint8_t *pusr_buf, uint16_t num, uin uint32_t n_index; uint32_t nhbytes = (nbytes + 3) / 4; uint32_t *pbuf = (uint32_t *)pusr_buf; + UNUSED(num); for(n_index = 0; n_index < nhbytes; n_index ++) { #if defined (__ICCARM__) && (__VER__ < 7000000) @@ -1015,11 +1014,10 @@ void usb_hch_halt(otg_global_type *usbx, uint8_t chn) usb_chh->hcchar_bit.eptype == EPT_BULK_TYPE) { usb_chh->hcchar_bit.chdis = TRUE; - if((usbx->gnptxsts & 0xFFFF) == 0) + if((usbx->gnptxsts_bit.nptxqspcavail) == 0) { usb_chh->hcchar_bit.chena = FALSE; usb_chh->hcchar_bit.chena = TRUE; - usb_chh->hcchar_bit.eptdir = 0; do { if(count ++ > 1000) @@ -1034,11 +1032,10 @@ void usb_hch_halt(otg_global_type *usbx, uint8_t chn) else { usb_chh->hcchar_bit.chdis = TRUE; - if((usb_host->hptxsts & 0xFFFF) == 0) + if((usb_host->hptxsts_bit.ptxqspcavil) == 0) { usb_chh->hcchar_bit.chena = FALSE; usb_chh->hcchar_bit.chena = TRUE; - usb_chh->hcchar_bit.eptdir = 0; do { if(count ++ > 1000) diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_wdt.c b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_wdt.c index 24d1803bb7..cde5251a4d 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_wdt.c +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_wdt.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_wdt.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the wdt firmware library ************************************************************************** * Copyright notice & Disclaimer diff --git a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_wwdt.c b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_wwdt.c index 9a1e460baa..53d8f0a9b5 100644 --- a/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_wwdt.c +++ b/bsp/at32/libraries/AT32F415_Firmware_Library/drivers/src/at32f415_wwdt.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f415_wwdt.c - * @version v2.0.5 - * @date 2022-05-20 * @brief contains all the functions for the wwdt firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -106,6 +104,16 @@ flag_status wwdt_flag_get(void) return (flag_status)WWDT->sts_bit.rldf; } +/** + * @brief wwdt reload counter interrupt flag get + * @param none + * @retval state of reload counter interrupt flag + */ +flag_status wwdt_interrupt_flag_get(void) +{ + return (flag_status)(WWDT->sts_bit.rldf && WWDT->cfg_bit.rldien); +} + /** * @brief wwdt counter value set * @param wwdt_cnt (0x40~0x7f) diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/cmsis/cm4/device_support/system_at32f421.h b/bsp/at32/libraries/AT32F421_Firmware_Library/cmsis/cm4/device_support/system_at32f421.h index 26de400131..1a5c2cea5e 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/cmsis/cm4/device_support/system_at32f421.h +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/cmsis/cm4/device_support/system_at32f421.h @@ -44,6 +44,10 @@ extern "C" { #define HEXT_STABLE_DELAY (5000u) #define PLL_STABLE_DELAY (500u) #define SystemCoreClock system_core_clock +#define DUMMY_NOP() {__NOP();__NOP();__NOP();__NOP();__NOP(); \ + __NOP();__NOP();__NOP();__NOP();__NOP(); \ + __NOP();__NOP();__NOP();__NOP();__NOP(); \ + __NOP();__NOP();__NOP();__NOP();__NOP();} /** * @} diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_adc.h b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_adc.h index c0585c0500..20b80606bc 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_adc.h +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_adc.h @@ -252,17 +252,15 @@ typedef struct __IO uint32_t ocdmaen : 1; /* [8] */ __IO uint32_t reserved2 : 2; /* [10:9] */ __IO uint32_t dtalign : 1; /* [11] */ - __IO uint32_t pctesel_l : 3; /* [14:12] */ + __IO uint32_t pctesel : 3; /* [14:12] */ __IO uint32_t pcten : 1; /* [15] */ __IO uint32_t reserved3 : 1; /* [16] */ - __IO uint32_t octesel_l : 3; /* [19:17] */ + __IO uint32_t octesel : 3; /* [19:17] */ __IO uint32_t octen : 1; /* [20] */ __IO uint32_t pcswtrg : 1; /* [21] */ __IO uint32_t ocswtrg : 1; /* [22] */ __IO uint32_t itsrven : 1; /* [23] */ - __IO uint32_t pctesel_h : 1; /* [24] */ - __IO uint32_t octesel_h : 1; /* [25] */ - __IO uint32_t reserved4 : 6; /* [31:26] */ + __IO uint32_t reserved4 : 8; /* [31:24] */ } ctrl2_bit; }; @@ -564,6 +562,7 @@ flag_status adc_preempt_software_trigger_status_get(adc_type *adc_x); uint16_t adc_ordinary_conversion_data_get(adc_type *adc_x); uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel); flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag); +flag_status adc_interrupt_flag_get(adc_type *adc_x, uint8_t adc_flag); void adc_flag_clear(adc_type *adc_x, uint32_t adc_flag); /** diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_cmp.h b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_cmp.h index 564c171c92..625c622ef9 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_cmp.h +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_cmp.h @@ -82,6 +82,8 @@ typedef enum CMP_SPEED_ULTRALOW = 0x03 /*!< comparator selected ultralow speed */ } cmp_speed_type; +#define CMP_OUTPUT_TMR1CXORAW_OFF CMP_OUTPUT_TMR1CHCLR +#define CMP_OUTPUT_TMR3CXORAW_OFF CMP_OUTPUT_TMR3CHCLR /** * @brief cmp output type */ @@ -256,7 +258,7 @@ uint32_t cmp_output_value_get(cmp_sel_type cmp_sel); void cmp_write_protect_enable(cmp_sel_type cmp_sel); void cmp_filter_config(uint16_t high_pulse_cnt, uint16_t low_pulse_cnt, confirm_state new_state); void cmp_blanking_config(cmp_blanking_type blank_sel); -void cmp_scal_brg_config(uint32_t scal_brg); +void cmp_scal_brg_config(cmp_scal_brg_type scal_brg); /** * @} diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_crc.h b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_crc.h index b7d8d1e860..7a7e2d998a 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_crc.h +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_crc.h @@ -66,6 +66,17 @@ typedef enum CRC_REVERSE_OUTPUT_DATA = 0x01 /*!< output data reverse by word */ } crc_reverse_output_type; +/** + * @brief crc polynomial size + */ +typedef enum +{ + CRC_POLY_SIZE_32B = 0x00, /*!< polynomial size 32 bits */ + CRC_POLY_SIZE_16B = 0x01, /*!< polynomial size 16 bits */ + CRC_POLY_SIZE_8B = 0x02, /*!< polynomial size 8 bits */ + CRC_POLY_SIZE_7B = 0x03 /*!< polynomial size 7 bits */ +} crc_poly_size_type; + /** * @brief type define crc register all */ @@ -105,7 +116,8 @@ typedef struct struct { __IO uint32_t rst : 1 ; /* [0] */ - __IO uint32_t reserved1 : 4 ; /* [4:1] */ + __IO uint32_t reserved1 : 2 ; /* [2:1] */ + __IO uint32_t poly_size : 2 ; /* [4:3] */ __IO uint32_t revid : 2 ; /* [6:5] */ __IO uint32_t revod : 1 ; /* [7] */ __IO uint32_t reserved2 : 24 ;/* [31:8] */ @@ -129,6 +141,18 @@ typedef struct } idt_bit; }; + /** + * @brief crc polynomial register, offset:0x14 + */ + union + { + __IO uint32_t poly; + struct + { + __IO uint32_t poly : 32; /* [31:0] */ + } poly_bit; + }; + } crc_type; /** @@ -150,6 +174,10 @@ uint8_t crc_common_data_get(void); void crc_init_data_set(uint32_t value); void crc_reverse_input_data_set(crc_reverse_input_type value); void crc_reverse_output_data_set(crc_reverse_output_type value); +void crc_poly_value_set(uint32_t value); +uint32_t crc_poly_value_get(void); +void crc_poly_size_set(crc_poly_size_type size); +crc_poly_size_type crc_poly_size_get(void); /** * @} diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_crm.h b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_crm.h index da1c269736..bedf1179be 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_crm.h +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_crm.h @@ -124,7 +124,7 @@ typedef enum CRM_USART2_PERIPH_CLOCK = MAKE_VALUE(0x1C, 17), /*!< usart2 periph clock */ CRM_I2C1_PERIPH_CLOCK = MAKE_VALUE(0x1C, 21), /*!< i2c1 periph clock */ CRM_I2C2_PERIPH_CLOCK = MAKE_VALUE(0x1C, 22), /*!< i2c2 periph clock */ - CRM_PWC_PERIPH_CLOCK = MAKE_VALUE(0x1C, 28), /*!< pwc periph clock */ + CRM_PWC_PERIPH_CLOCK = MAKE_VALUE(0x1C, 28) /*!< pwc periph clock */ } crm_periph_clock_type; @@ -158,7 +158,7 @@ typedef enum CRM_USART2_PERIPH_RESET = MAKE_VALUE(0x10, 17), /*!< usart2 periph reset */ CRM_I2C1_PERIPH_RESET = MAKE_VALUE(0x10, 21), /*!< i2c1 periph reset */ CRM_I2C2_PERIPH_RESET = MAKE_VALUE(0x10, 22), /*!< i2c2 periph reset */ - CRM_PWC_PERIPH_RESET = MAKE_VALUE(0x10, 28), /*!< pwc periph reset */ + CRM_PWC_PERIPH_RESET = MAKE_VALUE(0x10, 28) /*!< pwc periph reset */ } crm_periph_reset_type; @@ -252,7 +252,7 @@ typedef enum CRM_PLL_FREF_8M = 2, /*!< pll refrence clock between 7.8125 mhz and 8.33 mhz */ CRM_PLL_FREF_12M = 3, /*!< pll refrence clock between 8.33 mhz and 12.5 mhz */ CRM_PLL_FREF_16M = 4, /*!< pll refrence clock between 15.625 mhz and 20.83 mhz */ - CRM_PLL_FREF_25M = 5, /*!< pll refrence clock between 20.83 mhz and 31.255 mhz */ + CRM_PLL_FREF_25M = 5 /*!< pll refrence clock between 20.83 mhz and 31.255 mhz */ } crm_pll_fref_type; /** @@ -789,6 +789,7 @@ void crm_reset(void); void crm_lext_bypass(confirm_state new_state); void crm_hext_bypass(confirm_state new_state); flag_status crm_flag_get(uint32_t flag); +flag_status crm_interrupt_flag_get(uint32_t flag); error_status crm_hext_stable_wait(void); void crm_hick_clock_trimming_set(uint8_t trim_value); void crm_hick_clock_calibration_set(uint8_t cali_value); diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_dma.h b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_dma.h index 58f50e3240..33fd6f779f 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_dma.h +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_dma.h @@ -366,6 +366,7 @@ uint16_t dma_data_number_get(dma_channel_type* dmax_channely); void dma_interrupt_enable(dma_channel_type* dmax_channely, uint32_t dma_int, confirm_state new_state); void dma_channel_enable(dma_channel_type* dmax_channely, confirm_state new_state); flag_status dma_flag_get(uint32_t dmax_flag); +flag_status dma_interrupt_flag_get(uint32_t dmax_flag); void dma_flag_clear(uint32_t dmax_flag); void dma_default_para_init(dma_init_type* dma_init_struct); void dma_init(dma_channel_type* dmax_channely, dma_init_type* dma_init_struct); diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_ertc.h b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_ertc.h index 65fc1dcdc2..0038e7a35f 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_ertc.h +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_ertc.h @@ -885,6 +885,7 @@ void ertc_tamper_enable(ertc_tamper_select_type tamper_x, confirm_state new_stat void ertc_interrupt_enable(uint32_t source, confirm_state new_state); flag_status ertc_interrupt_get(uint32_t source); flag_status ertc_flag_get(uint32_t flag); +flag_status ertc_interrupt_flag_get(uint32_t flag); void ertc_flag_clear(uint32_t flag); void ertc_bpr_data_write(ertc_dt_type dt, uint32_t data); uint32_t ertc_bpr_data_read(ertc_dt_type dt); diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_exint.h b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_exint.h index c29d44abcc..4cfd7c6b80 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_exint.h +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_exint.h @@ -206,6 +206,7 @@ void exint_default_para_init(exint_init_type *exint_struct); void exint_init(exint_init_type *exint_struct); void exint_flag_clear(uint32_t exint_line); flag_status exint_flag_get(uint32_t exint_line); +flag_status exint_interrupt_flag_get(uint32_t exint_line); void exint_software_interrupt_event_generate(uint32_t exint_line); void exint_interrupt_enable(uint32_t exint_line, confirm_state new_state); void exint_event_enable(uint32_t exint_line, confirm_state new_state); diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_gpio.h b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_gpio.h index 5498dfbf0b..c91f7d73d5 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_gpio.h +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_gpio.h @@ -25,45 +25,45 @@ /** porta iomux table -------------------------------------------------------------------------------------------------------------------------------- - pin name | mux0 | mux1 | mux2 | mux3 | mux4 | mux5 | mux6 | mux7 | + pin name | mux0 | mux1 | mux2 | mux3 | mux4 | mux5 | mux6 | mux7 | -------------------------------------------------------------------------------------------------------------------------------- - pa0 | | usart2_cts | | | i2c2_scl | tmr1_etr | | comp_out | + pa0 | | usart2_cts | | | i2c2_scl | tmr1_etr | | comp_out | -------------------------------------------------------------------------------------------------------------------------------- - pa1 | eventout | usart2_rts | | | i2c2_sda | tmr15_ch1c | | | + pa1 | eventout | usart2_rts | | | i2c2_sda | tmr15_ch1c | | | -------------------------------------------------------------------------------------------------------------------------------- - pa2 | tmr15_ch1 | usart2_tx | | | | | | | + pa2 | tmr15_ch1 | usart2_tx | | | | | | | -------------------------------------------------------------------------------------------------------------------------------- - pa3 | tmr15_ch2 | usart2_rx | | | | i2s2_mck | | | + pa3 | tmr15_ch2 | usart2_rx | | | | i2s2_mck | | | -------------------------------------------------------------------------------------------------------------------------------- - pa4 | spi1_nss | usart2_ck | | | tmr14_ch1 | | | | - | i2s1_ws | | | | | | | | + pa4 | spi1_nss | usart2_ck | | | tmr14_ch1 | | | | + | i2s1_ws | | | | | | | | -------------------------------------------------------------------------------------------------------------------------------- - pa5 | spi1_sck | | | | | | | | - | i2s1_ck | | | | | | | | + pa5 | spi1_sck | | | | | | | | + | i2s1_ck | | | | | | | | -------------------------------------------------------------------------------------------------------------------------------- - pa6 | spi1_miso | tmr3_ch1 | tmr1_bkin | i2s2_mck | | tmr16_ch1 | eventout | comp_out | + pa6 | spi1_miso | tmr3_ch1 | tmr1_bkin | i2s2_mck | | tmr16_ch1 | eventout | comp_out | | i2s1_mck | | | | | | | | -------------------------------------------------------------------------------------------------------------------------------- - pa7 | spi1_mosi | tmr3_ch2 | tmr1_ch1c | | tmr14_ch1 | tmr17_ch1 | eventout | | - | i2s1_sd | | | | | | | | + pa7 | spi1_mosi | tmr3_ch2 | tmr1_ch1c | | tmr14_ch1 | tmr17_ch1 | eventout | | + | i2s1_sd | | | | | | | | -------------------------------------------------------------------------------------------------------------------------------- - pa8 | clkout | usart1_ck | tmr1_ch1 | eventout | usart2_tx | | | i2c2_scl | + pa8 | clkout | usart1_ck | tmr1_ch1 | eventout | usart2_tx | | | i2c2_scl | -------------------------------------------------------------------------------------------------------------------------------- - pa9 | tmr15_bkin | usart1_tx | tmr1_ch2 | | i2c1_scl | clkout | | i2c2_smba | + pa9 | tmr15_bkin | usart1_tx | tmr1_ch2 | | i2c1_scl | clkout | | i2c2_smba | -------------------------------------------------------------------------------------------------------------------------------- - pa10 | tmr17_bkin | usart1_rx | tmr1_ch3 | | i2c1_sda | | | | + pa10 | tmr17_bkin | usart1_rx | tmr1_ch3 | | i2c1_sda | | | | -------------------------------------------------------------------------------------------------------------------------------- - pa11 | eventout | usart1_cts | tmr1_ch4 | | i2c1_smba | i2c2_scl | | comp_out | + pa11 | eventout | usart1_cts | tmr1_ch4 | | i2c1_smba | i2c2_scl | | comp_out | ----------------------------- -------------------------------------------------------------------------------------------------- - pa12 | eventout | usart1_rts | tmr1_etr | | | i2c2_sda | | | + pa12 | eventout | usart1_rts | tmr1_etr | | | i2c2_sda | | | -------------------------------------------------------------------------------------------------------------------------------- - pa13 | swdio | ir_out | | | | | spi2_miso | | + pa13 | swdio | ir_out | | | | | spi2_miso | | | | | | | | | i2s2_mck | | -------------------------------------------------------------------------------------------------------------------------------- - pa14 | swclk | usart2_tx | | | | | spi2_mosi | | + pa14 | swclk | usart2_tx | | | | | spi2_mosi | | | | | | | | | i2s2_sd | | -------------------------------------------------------------------------------------------------------------------------------- - pa15 | spi1_nss | usart2_rx | | | | | spi2_nss | | + pa15 | spi1_nss | usart2_rx | | | | | spi2_nss | | | i2s1_ws | | | eventout | | | i2s2_ws | | -------------------------------------------------------------------------------------------------------------------------------- */ @@ -71,20 +71,20 @@ /** portb iomux table -------------------------------------------------------------------------------------------------------------------------------- - pin name | mux0 | mux1 | mux2 | mux3 | mux4 | mux5 | mux6 | mux7 | + pin name | mux0 | mux1 | mux2 | mux3 | mux4 | mux5 | mux6 | mux7 | -------------------------------------------------------------------------------------------------------------------------------- - pb0 | eventout | tmr3_ch3 | tmr1_ch2c | usart2_rx | | | i2s1_mck | | + pb0 | eventout | tmr3_ch3 | tmr1_ch2c | usart2_rx | | | i2s1_mck | | -------------------------------------------------------------------------------------------------------------------------------- - pb1 | tmr14_ch1 | tmr3_ch4 | tmr1_ch3c | | | | spi2_sck | | - | | | | | | | i2s2_ck | | + pb1 | tmr14_ch1 | tmr3_ch4 | tmr1_ch3c | | | | spi2_sck | | + | | | | | | | i2s2_ck | | -------------------------------------------------------------------------------------------------------------------------------- - pb2 | | | tmr3_etr | | | | | | + pb2 | | | tmr3_etr | | | | | | -------------------------------------------------------------------------------------------------------------------------------- - pb3 | spi1_sck | eventout | | | | | spi2_sck | | - | i2s1_ck | | | | | | i2s2_ck | | + pb3 | spi1_sck | eventout | | | | | spi2_sck | | + | i2s1_ck | | | | | | i2s2_ck | | -------------------------------------------------------------------------------------------------------------------------------- - pb4 | spi1_miso | tmr3_ch1 | eventout | | | tmr17_bkin | spi2_miso | i2c2_sda | - | i2s1_mck | | | | | | spi2_mck | | + pb4 | spi1_miso | tmr3_ch1 | eventout | | | tmr17_bkin | spi2_miso | i2c2_sda | + | i2s1_mck | | | | | | spi2_mck | | -------------------------------------------------------------------------------------------------------------------------------- pb5 | spi1_mosi | tmr3_ch2 | tmr16_bkin | i2c1_smba | | | spi2_mosi | | | i2s1_sd | | | | | | i2s2_sd | | @@ -120,7 +120,7 @@ /** portf iomux table -------------------------------------------------------------------------------------------------------------------------------- - pin name | mux0 | mux1 | mux2 | mux3 | mux4 | mux5 | mux6 | mux7 | + pin name | mux0 | mux1 | mux2 | mux3 | mux4 | mux5 | mux6 | mux7 | -------------------------------------------------------------------------------------------------------------------------------- pf0 | | i2c1_sda | | | | | | | -------------------------------------------------------------------------------------------------------------------------------- diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_i2c.h b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_i2c.h index bd3ef09fe5..08ddaba607 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_i2c.h +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_i2c.h @@ -378,6 +378,7 @@ void i2c_7bit_address_send(i2c_type *i2c_x, uint8_t address, i2c_direction_type void i2c_data_send(i2c_type *i2c_x, uint8_t data); uint8_t i2c_data_receive(i2c_type *i2c_x); flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag); +flag_status i2c_interrupt_flag_get(i2c_type *i2c_x, uint32_t flag); void i2c_flag_clear(i2c_type *i2c_x, uint32_t flag); /** diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_pwc.h b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_pwc.h index 34a8fdfa34..83dcec74f9 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_pwc.h +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_pwc.h @@ -58,10 +58,10 @@ extern "C" { /** * @brief pwc wakeup pin num definition */ -#define PWC_WAKEUP_PIN_1 ((uint32_t)0x00000100) /*!< standby wake-up pin1 */ -#define PWC_WAKEUP_PIN_2 ((uint32_t)0x00000200) /*!< standby wake-up pin2 */ -#define PWC_WAKEUP_PIN_6 ((uint32_t)0x00002000) /*!< standby wake-up pin6 */ -#define PWC_WAKEUP_PIN_7 ((uint32_t)0x00004000) /*!< standby wake-up pin7 */ +#define PWC_WAKEUP_PIN_1 ((uint32_t)0x00000100) /*!< standby wake-up pin1(pa0) */ +#define PWC_WAKEUP_PIN_2 ((uint32_t)0x00000200) /*!< standby wake-up pin2(pc13) */ +#define PWC_WAKEUP_PIN_6 ((uint32_t)0x00002000) /*!< standby wake-up pin6(pb5) */ +#define PWC_WAKEUP_PIN_7 ((uint32_t)0x00004000) /*!< standby wake-up pin7(pb15) */ /** @defgroup PWC_exported_types * @{ diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_scfg.h b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_scfg.h index 6e16a408ad..d0c85b9958 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_scfg.h +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_scfg.h @@ -55,9 +55,7 @@ extern "C" { */ typedef enum { - SCFG_IR_SOURCE_TMR16 = 0x00, /* infrared signal source select tmr16 */ - SCFG_IR_SOURCE_USART1 = 0x01, /* infrared signal source select usart1 */ - SCFG_IR_SOURCE_USART2 = 0x02 /* infrared signal source select usart2 */ + SCFG_IR_SOURCE_TMR16 = 0x00 /* infrared signal source select tmr16 */ } scfg_ir_source_type; /** diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_spi.h b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_spi.h index ceba8caacb..a55543ff61 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_spi.h +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_spi.h @@ -474,6 +474,7 @@ void spi_i2s_dma_receiver_enable(spi_type* spi_x, confirm_state new_state); void spi_i2s_data_transmit(spi_type* spi_x, uint16_t tx_data); uint16_t spi_i2s_data_receive(spi_type* spi_x); flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag); +flag_status spi_i2s_interrupt_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag); void spi_i2s_flag_clear(spi_type* spi_x, uint32_t spi_i2s_flag); /** diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_tmr.h b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_tmr.h index f174215f3b..86075ba7e7 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_tmr.h +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_tmr.h @@ -236,7 +236,7 @@ typedef enum { TMR_CC_CHANNEL_MAPPED_DIRECT = 0x01, /*!< channel is configured as input, mapped direct */ TMR_CC_CHANNEL_MAPPED_INDIRECT = 0x02, /*!< channel is configured as input, mapped indirect */ - TMR_CC_CHANNEL_MAPPED_STI = 0x03 /*!< channel is configured as input, mapped trc */ + TMR_CC_CHANNEL_MAPPED_STI = 0x03 /*!< channel is configured as input, mapped sti */ } tmr_input_direction_mapped_type; /** @@ -923,6 +923,7 @@ void tmr_trigger_input_select(tmr_type *tmr_x, sub_tmr_input_sel_type trigger_se void tmr_sub_sync_mode_set(tmr_type *tmr_x, confirm_state new_state); void tmr_dma_request_enable(tmr_type *tmr_x, tmr_dma_request_type dma_request, confirm_state new_state); void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state new_state); +flag_status tmr_interrupt_flag_get(tmr_type *tmr_x, uint32_t tmr_flag); flag_status tmr_flag_get(tmr_type *tmr_x, uint32_t tmr_flag); void tmr_flag_clear(tmr_type *tmr_x, uint32_t tmr_flag); void tmr_event_sw_trigger(tmr_type *tmr_x, tmr_event_trigger_type tmr_event); diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_usart.h b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_usart.h index dc68e6413c..48846d6fe4 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_usart.h +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_usart.h @@ -351,6 +351,7 @@ void usart_irda_low_power_enable(usart_type* usart_x, confirm_state new_state); void usart_hardware_flow_control_set(usart_type* usart_x,usart_hardware_flow_control_type flow_state); void usart_transmit_receive_pin_swap(usart_type* usart_x, confirm_state new_state); flag_status usart_flag_get(usart_type* usart_x, uint32_t flag); +flag_status usart_interrupt_flag_get(usart_type* usart_x, uint32_t flag); void usart_flag_clear(usart_type* usart_x, uint32_t flag); /** diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_wwdt.h b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_wwdt.h index f058944305..d57e0af13c 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_wwdt.h +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/inc/at32f421_wwdt.h @@ -134,6 +134,7 @@ void wwdt_flag_clear(void); void wwdt_enable(uint8_t wwdt_cnt); void wwdt_interrupt_enable(void); flag_status wwdt_flag_get(void); +flag_status wwdt_interrupt_flag_get(void); void wwdt_counter_set(uint8_t wwdt_cnt); void wwdt_window_counter_set(uint8_t window_cnt); diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_adc.c b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_adc.c index e48745fce7..be56e90bae 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_adc.c +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_adc.c @@ -83,7 +83,7 @@ void adc_enable(adc_type *adc_x, confirm_state new_state) * - ADC_LEFT_ALIGNMENT * @param ordinary_channel_length: configure the adc ordinary channel sequence length. * this parameter can be: - * - (0x1~0xf) + * - (0x1~0x10) * @retval none */ void adc_base_default_para_init(adc_base_config_type *adc_base_struct) @@ -109,7 +109,7 @@ void adc_base_default_para_init(adc_base_config_type *adc_base_struct) * - ADC_LEFT_ALIGNMENT * @param ordinary_channel_length: configure the adc ordinary channel sequence length. * this parameter can be: - * - (0x1~0xf) + * - (0x1~0x10) * @retval none */ void adc_base_config(adc_type *adc_x, adc_base_config_type *adc_base_struct) @@ -313,117 +313,42 @@ void adc_voltage_monitor_single_channel_select(adc_type *adc_x, adc_channel_sele */ void adc_ordinary_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime) { - switch(adc_channel) + uint32_t tmp_reg; + if(adc_channel < ADC_CHANNEL_10) { - case ADC_CHANNEL_0: - adc_x->spt2_bit.cspt0 = adc_sampletime; - break; - case ADC_CHANNEL_1: - adc_x->spt2_bit.cspt1 = adc_sampletime; - break; - case ADC_CHANNEL_2: - adc_x->spt2_bit.cspt2 = adc_sampletime; - break; - case ADC_CHANNEL_3: - adc_x->spt2_bit.cspt3 = adc_sampletime; - break; - case ADC_CHANNEL_4: - adc_x->spt2_bit.cspt4 = adc_sampletime; - break; - case ADC_CHANNEL_5: - adc_x->spt2_bit.cspt5 = adc_sampletime; - break; - case ADC_CHANNEL_6: - adc_x->spt2_bit.cspt6 = adc_sampletime; - break; - case ADC_CHANNEL_7: - adc_x->spt2_bit.cspt7 = adc_sampletime; - break; - case ADC_CHANNEL_8: - adc_x->spt2_bit.cspt8 = adc_sampletime; - break; - case ADC_CHANNEL_9: - adc_x->spt2_bit.cspt9 = adc_sampletime; - break; - case ADC_CHANNEL_10: - adc_x->spt1_bit.cspt10 = adc_sampletime; - break; - case ADC_CHANNEL_11: - adc_x->spt1_bit.cspt11 = adc_sampletime; - break; - case ADC_CHANNEL_12: - adc_x->spt1_bit.cspt12 = adc_sampletime; - break; - case ADC_CHANNEL_13: - adc_x->spt1_bit.cspt13 = adc_sampletime; - break; - case ADC_CHANNEL_14: - adc_x->spt1_bit.cspt14 = adc_sampletime; - break; - case ADC_CHANNEL_15: - adc_x->spt1_bit.cspt15 = adc_sampletime; - break; - case ADC_CHANNEL_16: - adc_x->spt1_bit.cspt16 = adc_sampletime; - break; - case ADC_CHANNEL_17: - adc_x->spt1_bit.cspt17 = adc_sampletime; - break; - default: - break; + tmp_reg = adc_x->spt2; + tmp_reg &= ~(0x07 << 3 * adc_channel); + tmp_reg |= adc_sampletime << 3 * adc_channel; + adc_x->spt2 = tmp_reg; } - switch(adc_sequence) + else { - case 1: - adc_x->osq3_bit.osn1 = adc_channel; - break; - case 2: - adc_x->osq3_bit.osn2 = adc_channel; - break; - case 3: - adc_x->osq3_bit.osn3 = adc_channel; - break; - case 4: - adc_x->osq3_bit.osn4 = adc_channel; - break; - case 5: - adc_x->osq3_bit.osn5 = adc_channel; - break; - case 6: - adc_x->osq3_bit.osn6 = adc_channel; - break; - case 7: - adc_x->osq2_bit.osn7 = adc_channel; - break; - case 8: - adc_x->osq2_bit.osn8 = adc_channel; - break; - case 9: - adc_x->osq2_bit.osn9 = adc_channel; - break; - case 10: - adc_x->osq2_bit.osn10 = adc_channel; - break; - case 11: - adc_x->osq2_bit.osn11 = adc_channel; - break; - case 12: - adc_x->osq2_bit.osn12 = adc_channel; - break; - case 13: - adc_x->osq1_bit.osn13 = adc_channel; - break; - case 14: - adc_x->osq1_bit.osn14 = adc_channel; - break; - case 15: - adc_x->osq1_bit.osn15 = adc_channel; - break; - case 16: - adc_x->osq1_bit.osn16 = adc_channel; - break; - default: - break; + tmp_reg = adc_x->spt1; + tmp_reg &= ~(0x07 << 3 * (adc_channel - ADC_CHANNEL_10)); + tmp_reg |= adc_sampletime << 3 * (adc_channel - ADC_CHANNEL_10); + adc_x->spt1 = tmp_reg; + } + + if(adc_sequence >= 13) + { + tmp_reg = adc_x->osq1; + tmp_reg &= ~(0x01F << 5 * (adc_sequence - 13)); + tmp_reg |= adc_channel << 5 * (adc_sequence - 13); + adc_x->osq1 = tmp_reg; + } + else if(adc_sequence >= 7) + { + tmp_reg = adc_x->osq2; + tmp_reg &= ~(0x01F << 5 * (adc_sequence - 7)); + tmp_reg |= adc_channel << 5 * (adc_sequence - 7); + adc_x->osq2 = tmp_reg; + } + else + { + tmp_reg = adc_x->osq3; + tmp_reg &= ~(0x01F << 5 * (adc_sequence - 1)); + tmp_reg |= adc_channel << 5 * (adc_sequence - 1); + adc_x->osq3 = tmp_reg; } } @@ -471,66 +396,23 @@ void adc_preempt_channel_length_set(adc_type *adc_x, uint8_t adc_channel_lenght) */ void adc_preempt_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime) { - uint16_t sequence_index=0; - switch(adc_channel) + uint32_t tmp_reg; + uint8_t sequence_index; + if(adc_channel < ADC_CHANNEL_10) { - case ADC_CHANNEL_0: - adc_x->spt2_bit.cspt0 = adc_sampletime; - break; - case ADC_CHANNEL_1: - adc_x->spt2_bit.cspt1 = adc_sampletime; - break; - case ADC_CHANNEL_2: - adc_x->spt2_bit.cspt2 = adc_sampletime; - break; - case ADC_CHANNEL_3: - adc_x->spt2_bit.cspt3 = adc_sampletime; - break; - case ADC_CHANNEL_4: - adc_x->spt2_bit.cspt4 = adc_sampletime; - break; - case ADC_CHANNEL_5: - adc_x->spt2_bit.cspt5 = adc_sampletime; - break; - case ADC_CHANNEL_6: - adc_x->spt2_bit.cspt6 = adc_sampletime; - break; - case ADC_CHANNEL_7: - adc_x->spt2_bit.cspt7 = adc_sampletime; - break; - case ADC_CHANNEL_8: - adc_x->spt2_bit.cspt8 = adc_sampletime; - break; - case ADC_CHANNEL_9: - adc_x->spt2_bit.cspt9 = adc_sampletime; - break; - case ADC_CHANNEL_10: - adc_x->spt1_bit.cspt10 = adc_sampletime; - break; - case ADC_CHANNEL_11: - adc_x->spt1_bit.cspt11 = adc_sampletime; - break; - case ADC_CHANNEL_12: - adc_x->spt1_bit.cspt12 = adc_sampletime; - break; - case ADC_CHANNEL_13: - adc_x->spt1_bit.cspt13 = adc_sampletime; - break; - case ADC_CHANNEL_14: - adc_x->spt1_bit.cspt14 = adc_sampletime; - break; - case ADC_CHANNEL_15: - adc_x->spt1_bit.cspt15 = adc_sampletime; - break; - case ADC_CHANNEL_16: - adc_x->spt1_bit.cspt16 = adc_sampletime; - break; - case ADC_CHANNEL_17: - adc_x->spt1_bit.cspt17 = adc_sampletime; - break; - default: - break; + tmp_reg = adc_x->spt2; + tmp_reg &= ~(0x07 << 3 * adc_channel); + tmp_reg |= adc_sampletime << 3 * adc_channel; + adc_x->spt2 = tmp_reg; } + else + { + tmp_reg = adc_x->spt1; + tmp_reg &= ~(0x07 << 3 * (adc_channel - ADC_CHANNEL_10)); + tmp_reg |= adc_sampletime << 3 * (adc_channel - ADC_CHANNEL_10); + adc_x->spt1 = tmp_reg; + } + sequence_index = adc_sequence + 3 - adc_x->psq_bit.pclen; switch(sequence_index) { @@ -570,13 +452,11 @@ void adc_ordinary_conversion_trigger_set(adc_type *adc_x, adc_ordinary_trig_sele { if(adc_ordinary_trig > 7) { - adc_x->ctrl2_bit.octesel_h = 1; - adc_x->ctrl2_bit.octesel_l = adc_ordinary_trig & 0x7; + adc_x->ctrl2_bit.octesel = adc_ordinary_trig & 0x7; } else { - adc_x->ctrl2_bit.octesel_h = 0; - adc_x->ctrl2_bit.octesel_l = adc_ordinary_trig & 0x7; + adc_x->ctrl2_bit.octesel = adc_ordinary_trig & 0x7; } adc_x->ctrl2_bit.octen = new_state; } @@ -600,13 +480,11 @@ void adc_preempt_conversion_trigger_set(adc_type *adc_x, adc_preempt_trig_select { if(adc_preempt_trig > 7) { - adc_x->ctrl2_bit.pctesel_h = 1; - adc_x->ctrl2_bit.pctesel_l = adc_preempt_trig & 0x7; + adc_x->ctrl2_bit.pctesel = adc_preempt_trig & 0x7; } else { - adc_x->ctrl2_bit.pctesel_h = 0; - adc_x->ctrl2_bit.pctesel_l = adc_preempt_trig & 0x7; + adc_x->ctrl2_bit.pctesel = adc_preempt_trig & 0x7; } adc_x->ctrl2_bit.pcten = new_state; } @@ -804,10 +682,10 @@ uint16_t adc_ordinary_conversion_data_get(adc_type *adc_x) * ADC1. * @param adc_preempt_channel: select the preempt channel. * this parameter can be one of the following values: - * - ADC_PREEMPTED_CHANNEL_1 - * - ADC_PREEMPTED_CHANNEL_2 - * - ADC_PREEMPTED_CHANNEL_3 - * - ADC_PREEMPTED_CHANNEL_4 + * - ADC_PREEMPT_CHANNEL_1 + * - ADC_PREEMPT_CHANNEL_2 + * - ADC_PREEMPT_CHANNEL_3 + * - ADC_PREEMPT_CHANNEL_4 * @retval the conversion data for selection preempt channel. */ uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel) @@ -862,6 +740,47 @@ flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag) return status; } +/** + * @brief get interrupt flag of the specified adc peripheral. + * @param adc_x: select the adc peripheral. + * this parameter can be one of the following values: + * ADC1. + * @param adc_flag: select the adc flag. + * this parameter can be one of the following values: + * - ADC_VMOR_FLAG + * - ADC_CCE_FLAG + * - ADC_PCCE_FLAG + * @retval the new state of adc flag status(SET or RESET). + */ +flag_status adc_interrupt_flag_get(adc_type *adc_x, uint8_t adc_flag) +{ + flag_status status = RESET; + switch(adc_flag) + { + case ADC_VMOR_FLAG: + if(adc_x->sts_bit.vmor && adc_x->ctrl1_bit.vmorien) + { + status = SET; + } + break; + case ADC_CCE_FLAG: + if(adc_x->sts_bit.cce && adc_x->ctrl1_bit.cceien) + { + status = SET; + } + break; + case ADC_PCCE_FLAG: + if(adc_x->sts_bit.pcce && adc_x->ctrl1_bit.pcceien) + { + status = SET; + } + break; + default: + break; + } + return status; +} + /** * @brief clear flag of the specified adc peripheral. * @param adc_x: select the adc peripheral. diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_cmp.c b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_cmp.c index 314ec57009..ec623554bd 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_cmp.c +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_cmp.c @@ -206,7 +206,7 @@ void cmp_blanking_config(cmp_blanking_type blank_sel) * - CMP_SCAL_BRG_11: vrefint = 1.2v, 3/4 vrefint = 0.9v, 1/2 vrefint = 0.6v, 1/4 vrefint = 0.3v * @retval none */ -void cmp_scal_brg_config(uint32_t scal_brg) +void cmp_scal_brg_config(cmp_scal_brg_type scal_brg) { uint32_t tmp_scal = 0, tmp_brg = 0; tmp_scal = scal_brg >> 1; diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_crc.c b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_crc.c index 9bd0a26a8b..7b65324cfe 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_crc.c +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_crc.c @@ -147,6 +147,52 @@ void crc_reverse_output_data_set(crc_reverse_output_type value) CRC->ctrl_bit.revod = value; } +/** + * @brief config crc polynomial value + * @param value + * 32-bit new data of crc poly value + * @retval none. + */ +void crc_poly_value_set(uint32_t value) +{ + CRC->poly = value; +} + +/** + * @brief return crc polynomial value + * @param none + * @retval 32-bit value of the polynomial value. + */ +uint32_t crc_poly_value_get(void) +{ + return (CRC->poly); +} + +/** + * @brief config crc polynomial data size + * @param size + * this parameter can be one of the following values: + * - CRC_POLY_SIZE_32B + * - CRC_POLY_SIZE_16B + * - CRC_POLY_SIZE_8B + * - CRC_POLY_SIZE_7B + * @retval none. + */ +void crc_poly_size_set(crc_poly_size_type size) +{ + CRC->ctrl_bit.poly_size = size; +} + +/** + * @brief return crc polynomial data size + * @param none + * @retval polynomial data size. + */ +crc_poly_size_type crc_poly_size_get(void) +{ + return (crc_poly_size_type)(CRC->ctrl_bit.poly_size); +} + /** * @} */ diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_crm.c b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_crm.c index aa014455e7..d098fdadc2 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_crm.c +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_crm.c @@ -134,6 +134,64 @@ flag_status crm_flag_get(uint32_t flag) return status; } +/** + * @brief get crm interrupt flag status + * @param flag + * this parameter can be one of the following values: + * - CRM_LICK_READY_INT_FLAG + * - CRM_LEXT_READY_INT_FLAG + * - CRM_HICK_READY_INT_FLAG + * - CRM_HEXT_READY_INT_FLAG + * - CRM_PLL_READY_INT_FLAG + * - CRM_CLOCK_FAILURE_INT_FLAG + * @retval flag_status (SET or RESET) + */ +flag_status crm_interrupt_flag_get(uint32_t flag) +{ + flag_status status = RESET; + switch(flag) + { + case CRM_LICK_READY_INT_FLAG: + if(CRM->clkint_bit.lickstblf && CRM->clkint_bit.lickstblien) + { + status = SET; + } + break; + case CRM_LEXT_READY_INT_FLAG: + if(CRM->clkint_bit.lextstblf && CRM->clkint_bit.lextstblien) + { + status = SET; + } + break; + case CRM_HICK_READY_INT_FLAG: + if(CRM->clkint_bit.hickstblf && CRM->clkint_bit.hickstblien) + { + status = SET; + } + break; + case CRM_HEXT_READY_INT_FLAG: + if(CRM->clkint_bit.hextstblf && CRM->clkint_bit.hextstblien) + { + status = SET; + } + break; + case CRM_PLL_READY_INT_FLAG: + if(CRM->clkint_bit.pllstblf && CRM->clkint_bit.pllstblien) + { + status = SET; + } + break; + case CRM_CLOCK_FAILURE_INT_FLAG: + if(CRM->clkint_bit.cfdf && CRM->ctrl_bit.cfden) + { + status = SET; + } + break; + } + + return status; +} + /** * @brief wait for hext stable * @param none @@ -621,6 +679,7 @@ void crm_pll_config2(crm_pll_clock_source_type clock_source, uint16_t pll_ns, \ void crm_sysclk_switch(crm_sclk_type value) { CRM->cfg_bit.sclksel = value; + DUMMY_NOP(); } /** diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_dma.c b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_dma.c index 0fdf519008..80c6eabd5a 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_dma.c +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_dma.c @@ -145,6 +145,36 @@ void dma_channel_enable(dma_channel_type* dmax_channely, confirm_state new_state dmax_channely->ctrl_bit.chen = new_state; } +/** + * @brief get dma interrupt flag + * @param dmax_flag + * this parameter can be one of the following values: + * - DMA1_FDT1_FLAG - DMA1_HDT1_FLAG - DMA1_DTERR1_FLAG + * - DMA1_FDT2_FLAG - DMA1_HDT2_FLAG - DMA1_DTERR2_FLAG + * - DMA1_FDT3_FLAG - DMA1_HDT3_FLAG - DMA1_DTERR3_FLAG + * - DMA1_FDT4_FLAG - DMA1_HDT4_FLAG - DMA1_DTERR4_FLAG + * - DMA1_FDT5_FLAG - DMA1_HDT5_FLAG - DMA1_DTERR5_FLAG + * @retval state of dma flag + */ +flag_status dma_interrupt_flag_get(uint32_t dmax_flag) +{ + flag_status status = RESET; + uint32_t temp = 0; + + temp = DMA1->sts; + + if ((temp & dmax_flag) != (uint16_t)RESET) + { + status = SET; + } + else + { + status = RESET; + } + + return status; +} + /** * @brief get dma flag * @param dmax_flag diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_ertc.c b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_ertc.c index e09a8f23d8..f9a359b5d2 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_ertc.c +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_ertc.c @@ -314,7 +314,7 @@ error_status ertc_date_set(uint8_t year, uint8_t month, uint8_t date, uint8_t we return ERROR; } - /* Set the ertc_DR register */ + /* set the ertc_date register */ ERTC->date = reg.date; /* exit init mode */ @@ -1216,6 +1216,45 @@ flag_status ertc_flag_get(uint32_t flag) } } +/** + * @brief get interrupt flag status. + * @param flag: specifies the flag to check. + * this parameter can be one of the following values: + * - ERTC_ALAF_FLAG: alarm clock a flag. + * - ERTC_TSF_FLAG: timestamp flag. + * - ERTC_TP1F_FLAG: tamper detection 1 flag. + * @retval the new state of flag (SET or RESET). + */ +flag_status ertc_interrupt_flag_get(uint32_t flag) +{ + __IO uint32_t iten = 0; + + switch(flag) + { + case ERTC_ALAF_FLAG: + iten = ERTC->ctrl_bit.alaien; + break; + case ERTC_TSF_FLAG: + iten = ERTC->ctrl_bit.tsien; + break; + case ERTC_TP1F_FLAG: + iten = ERTC->tamp_bit.tpien; + break; + + default: + break; + } + + if(((ERTC->sts & flag) != (uint32_t)RESET) && (iten)) + { + return SET; + } + else + { + return RESET; + } +} + /** * @brief clear flag status * @param flag: specifies the flag to clear. @@ -1255,13 +1294,7 @@ void ertc_bpr_data_write(ertc_dt_type dt, uint32_t data) reg = ERTC_BASE + 0x50 + (dt * 4); - /* disable write protection */ - ertc_write_protect_disable(); - *(__IO uint32_t *)reg = data; - - /* enable write protection */ - ertc_write_protect_enable(); } /** diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_exint.c b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_exint.c index 8d600a63b2..da6c4d204c 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_exint.c +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_exint.c @@ -151,6 +151,34 @@ flag_status exint_flag_get(uint32_t exint_line) return status; } +/** + * @brief get exint interrupt flag + * @param exint_line + * this parameter can be one of the following values: + * - EXINT_LINE_0 + * - EXINT_LINE_1 + * ... + * - EXINT_LINE_21 + * @retval state of exint flag + */ +flag_status exint_interrupt_flag_get(uint32_t exint_line) +{ + flag_status status = RESET; + uint32_t exint_flag =0; + exint_flag = EXINT->intsts & exint_line; + exint_flag = exint_flag & EXINT->inten; + + if((exint_flag != (uint16_t)RESET)) + { + status = SET; + } + else + { + status = RESET; + } + return status; +} + /** * @brief generate exint software interrupt event * @param exint_line diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_flash.c b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_flash.c index 194482c507..1179dae1c4 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_flash.c +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_flash.c @@ -655,7 +655,7 @@ flash_status_type flash_slib_enable(uint32_t pwd, uint16_t start_sector, uint16_ flash_status_type status = FLASH_OPERATE_DONE; /*check range param limits*/ - if((start_sector>=inst_start_sector) || ((inst_start_sector > end_sector) && \ + if((start_sector > inst_start_sector) || ((inst_start_sector > end_sector) && \ (inst_start_sector != 0x7FF)) || (start_sector > end_sector)) return FLASH_PROGRAM_ERROR; diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_i2c.c b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_i2c.c index 345b85dd8e..0dea348122 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_i2c.c +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_i2c.c @@ -594,6 +594,85 @@ flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag) } } +/** + * @brief get interrupt flag status + * @param i2c_x: to select the i2c peripheral. + * this parameter can be one of the following values: + * I2C1, I2C2. + * @param flag + * this parameter can be one of the following values: + * - I2C_STARTF_FLAG: start condition generation complete flag. + * - I2C_ADDR7F_FLAG: 0~7 bit address match flag. + * - I2C_TDC_FLAG: transmit data complete flag. + * - I2C_ADDRHF_FLAG: master 9~8 bit address header match flag. + * - I2C_STOPF_FLAG: stop condition generation complete flag. + * - I2C_RDBF_FLAG: receive data buffer full flag. + * - I2C_TDBE_FLAG: transmit data buffer empty flag. + * - I2C_BUSERR_FLAG: bus error flag. + * - I2C_ARLOST_FLAG: arbitration lost flag. + * - I2C_ACKFAIL_FLAG: acknowledge failure flag. + * - I2C_OUF_FLAG: overflow or underflow flag. + * - I2C_PECERR_FLAG: pec receive error flag. + * - I2C_TMOUT_FLAG: smbus timeout flag. + * - I2C_ALERTF_FLAG: smbus alert flag. + * @retval flag_status (SET or RESET) + */ +flag_status i2c_interrupt_flag_get(i2c_type *i2c_x, uint32_t flag) +{ + __IO uint32_t reg = 0, value = 0, iten = 0; + + switch(flag) + { + case I2C_STARTF_FLAG: + case I2C_ADDR7F_FLAG: + case I2C_TDC_FLAG: + case I2C_ADDRHF_FLAG: + case I2C_STOPF_FLAG: + iten = i2c_x->ctrl2_bit.evtien; + break; + case I2C_RDBF_FLAG: + case I2C_TDBE_FLAG: + iten = i2c_x->ctrl2_bit.dataien && i2c_x->ctrl2_bit.evtien; + break; + case I2C_BUSERR_FLAG: + case I2C_ARLOST_FLAG: + case I2C_ACKFAIL_FLAG: + case I2C_OUF_FLAG: + case I2C_PECERR_FLAG: + case I2C_TMOUT_FLAG: + case I2C_ALERTF_FLAG: + iten = i2c_x->ctrl2_bit.errien; + break; + + default: + break; + } + + reg = flag >> 28; + + flag &= (uint32_t)0x00FFFFFF; + + if(reg == 0) + { + value = i2c_x->sts1; + } + else + { + flag = (uint32_t)(flag >> 16); + + value = i2c_x->sts2; + } + + if(((value & flag) != (uint32_t)RESET) && (iten)) + { + return SET; + } + else + { + return RESET; + } +} + /** * @brief clear flag status * @param i2c_x: to select the i2c peripheral. diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_pwc.c b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_pwc.c index 24991eff54..e0e671e72a 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_pwc.c +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_pwc.c @@ -216,17 +216,17 @@ void pwc_voltage_regulate_set(pwc_regulator_type pwc_regulator) { switch(pwc_regulator) { - case 0: - PWC->ctrl2_bit.vrexlpen = 0; - PWC->ctrl_bit.vrsel = 0; + case PWC_REGULATOR_ON: + PWC->ctrl2_bit.vrexlpen = FALSE; + PWC->ctrl_bit.vrsel = FALSE; break; - case 1: - PWC->ctrl2_bit.vrexlpen = 0; - PWC->ctrl_bit.vrsel = 1; + case PWC_REGULATOR_LOW_POWER: + PWC->ctrl2_bit.vrexlpen = FALSE; + PWC->ctrl_bit.vrsel = TRUE; break; - case 2: - PWC->ctrl2_bit.vrexlpen = 1; - PWC->ctrl_bit.vrsel = 1; + case PWC_REGULATOR_EXTRA_LOW_POWER: + PWC->ctrl2_bit.vrexlpen = TRUE; + PWC->ctrl_bit.vrsel = TRUE; break; default: break; diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_scfg.c b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_scfg.c index 26dfa7e2e3..4fc535ac98 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_scfg.c +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_scfg.c @@ -55,8 +55,6 @@ void scfg_reset(void) * @param source * this parameter can be one of the following values: * - SCFG_IR_SOURCE_TMR16 - * - SCFG_IR_SOURCE_USART1 - * - SCFG_IR_SOURCE_USART2 * @param polarity * this parameter can be one of the following values: * - SCFG_IR_POLARITY_NO_AFFECTE diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_spi.c b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_spi.c index 3b7a09bd1f..0e270de541 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_spi.c +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_spi.c @@ -559,6 +559,69 @@ flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag) return status; } +/** + * @brief get interrupt flag of the specified spi/i2s peripheral. + * @param spi_x: select the spi/i2s peripheral. + * this parameter can be one of the following values: + * SPI1, SPI2 + * @param spi_i2s_flag: select the spi/i2s flag + * this parameter can be one of the following values: + * - SPI_I2S_RDBF_FLAG + * - SPI_I2S_TDBE_FLAG + * - I2S_TUERR_FLAG (this flag only use in i2s mode) + * - SPI_CCERR_FLAG (this flag only use in spi mode) + * - SPI_MMERR_FLAG (this flag only use in spi mode) + * - SPI_I2S_ROERR_FLAG + * @retval the new state of spi/i2s flag + */ +flag_status spi_i2s_interrupt_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag) +{ + flag_status status = RESET; + + switch(spi_i2s_flag) + { + case SPI_I2S_RDBF_FLAG: + if(spi_x->sts_bit.rdbf && spi_x->ctrl2_bit.rdbfie) + { + status = SET; + } + break; + case SPI_I2S_TDBE_FLAG: + if(spi_x->sts_bit.tdbe && spi_x->ctrl2_bit.tdbeie) + { + status = SET; + } + break; + case I2S_TUERR_FLAG: + if(spi_x->sts_bit.tuerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_CCERR_FLAG: + if(spi_x->sts_bit.ccerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_MMERR_FLAG: + if(spi_x->sts_bit.mmerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_I2S_ROERR_FLAG: + if(spi_x->sts_bit.roerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + default: + break; + }; + return status; +} + /** * @brief clear flag of the specified spi/i2s peripheral. * @param spi_x: select the spi/i2s peripheral. diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_tmr.c b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_tmr.c index fecab82075..71ae0ab299 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_tmr.c +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_tmr.c @@ -770,7 +770,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct switch(channel) { case TMR_SELECT_CHANNEL_1: - tmr_x->cctrl_bit.c1en = FALSE; + tmr_x->cctrl_bit.c1en = FALSE; tmr_x->cctrl_bit.c1p = (uint32_t)input_struct->input_polarity_select; tmr_x->cctrl_bit.c1cp = (input_struct->input_polarity_select & 0x2) >> 1; tmr_x->cm1_input_bit.c1c = input_struct->input_mapped_select; @@ -780,7 +780,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct break; case TMR_SELECT_CHANNEL_2: - tmr_x->cctrl_bit.c2en = FALSE; + tmr_x->cctrl_bit.c2en = FALSE; tmr_x->cctrl_bit.c2p = (uint32_t)input_struct->input_polarity_select; tmr_x->cctrl_bit.c2cp = (input_struct->input_polarity_select & 0x2) >> 1; tmr_x->cm1_input_bit.c2c = input_struct->input_mapped_select; @@ -790,7 +790,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct break; case TMR_SELECT_CHANNEL_3: - tmr_x->cctrl_bit.c3en = FALSE; + tmr_x->cctrl_bit.c3en = FALSE; tmr_x->cctrl_bit.c3p = (uint32_t)input_struct->input_polarity_select; tmr_x->cctrl_bit.c3cp = (input_struct->input_polarity_select & 0x2) >> 1; tmr_x->cm2_input_bit.c3c = input_struct->input_mapped_select; @@ -800,7 +800,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct break; case TMR_SELECT_CHANNEL_4: - tmr_x->cctrl_bit.c4en = FALSE; + tmr_x->cctrl_bit.c4en = FALSE; tmr_x->cctrl_bit.c4p = (uint32_t)input_struct->input_polarity_select; tmr_x->cm2_input_bit.c4c = input_struct->input_mapped_select; tmr_x->cm2_input_bit.c4df = input_struct->input_filter_value; @@ -1272,6 +1272,39 @@ void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state } } +/** + * @brief get tmr interrupt flag + * @param tmr_x: select the tmr peripheral. + * this parameter can be one of the following values: + * TMR1, TMR3, TMR6, TMR14, TMR15, TMR16, TMR17 + * @param tmr_flag + * this parameter can be one of the following values: + * - TMR_OVF_FLAG + * - TMR_C1_FLAG + * - TMR_C2_FLAG + * - TMR_C3_FLAG + * - TMR_C4_FLAG + * - TMR_HALL_FLAG + * - TMR_TRIGGER_FLAG + * - TMR_BRK_FLAG + * @retval state of tmr interrupt flag + */ +flag_status tmr_interrupt_flag_get(tmr_type *tmr_x, uint32_t tmr_flag) +{ + flag_status status = RESET; + + if((tmr_x->ists & tmr_flag) && (tmr_x->iden & tmr_flag)) + { + status = SET; + } + else + { + status = RESET; + } + + return status; +} + /** * @brief get tmr flag * @param tmr_x: select the tmr peripheral. @@ -1651,7 +1684,7 @@ void tmr_dma_control_config(tmr_type *tmr_x, tmr_dma_transfer_length_type dma_le } /** - * @brief config tmr break mode and dead-time + * @brief config tmr brake mode and dead-time * @param tmr_x: select the tmr peripheral. * this parameter can be one of the following values: * TMR1, TMR15, TMR16, TMR17 diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_usart.c b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_usart.c index 2f115e22cb..19777709be 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_usart.c +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_usart.c @@ -71,6 +71,9 @@ void usart_reset(usart_type* usart_x) * this parameter can be one of the following values: * - USART_DATA_8BITS * - USART_DATA_9BITS. + * note: + * - when parity check is disabled, the data bit width is the actual data bit number. + * - when parity check is enabled, the data bit width is the actual data bit number minus 1, and the MSB bit is replaced with the parity bit. * @param stop_bit: stop bits transmitted * this parameter can be one of the following values: * - USART_STOP_1_BIT @@ -559,6 +562,79 @@ flag_status usart_flag_get(usart_type* usart_x, uint32_t flag) } } +/** + * @brief check whether the specified usart interrupt flag is set or not. + * @param usart_x: select the usart or the uart peripheral. + * this parameter can be one of the following values: + * USART1 or USART2. + * @param flag: specifies the flag to check. + * this parameter can be one of the following values: + * - USART_CTSCF_FLAG: cts change flag (not available for UART4,UART5) + * - USART_BFF_FLAG: break frame flag + * - USART_TDBE_FLAG: transmit data buffer empty flag + * - USART_TDC_FLAG: transmit data complete flag + * - USART_RDBF_FLAG: receive data buffer full flag + * - USART_IDLEF_FLAG: idle flag + * - USART_ROERR_FLAG: receiver overflow error flag + * - USART_NERR_FLAG: noise error flag + * - USART_FERR_FLAG: framing error flag + * - USART_PERR_FLAG: parity error flag + * @retval the new state of usart_flag (SET or RESET). + */ +flag_status usart_interrupt_flag_get(usart_type* usart_x, uint32_t flag) +{ + flag_status int_status = RESET; + + switch(flag) + { + case USART_CTSCF_FLAG: + int_status = (flag_status)usart_x->ctrl3_bit.ctscfien; + break; + case USART_BFF_FLAG: + int_status = (flag_status)usart_x->ctrl2_bit.bfien; + break; + case USART_TDBE_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.tdbeien; + break; + case USART_TDC_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.tdcien; + break; + case USART_RDBF_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.rdbfien; + break; + case USART_ROERR_FLAG: + int_status = (flag_status)(usart_x->ctrl1_bit.rdbfien || usart_x->ctrl3_bit.errien); + break; + case USART_IDLEF_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.idleien; + break; + case USART_NERR_FLAG: + case USART_FERR_FLAG: + int_status = (flag_status)usart_x->ctrl3_bit.errien; + break; + case USART_PERR_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.perrien; + break; + default: + int_status = RESET; + break; + } + + if(int_status != SET) + { + return RESET; + } + + if(usart_x->sts & flag) + { + return SET; + } + else + { + return RESET; + } +} + /** * @brief clear the usart's pending flags. * @param usart_x: select the usart or the uart peripheral. diff --git a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_wwdt.c b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_wwdt.c index 718fa9fff8..236b54529e 100644 --- a/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_wwdt.c +++ b/bsp/at32/libraries/AT32F421_Firmware_Library/drivers/src/at32f421_wwdt.c @@ -104,6 +104,16 @@ flag_status wwdt_flag_get(void) return (flag_status)WWDT->sts_bit.rldf; } +/** + * @brief wwdt reload counter interrupt flag get + * @param none + * @retval state of reload counter interrupt flag + */ +flag_status wwdt_interrupt_flag_get(void) +{ + return (flag_status)(WWDT->sts_bit.rldf && WWDT->cfg_bit.rldien); +} + /** * @brief wwdt counter value set * @param wwdt_cnt (0x40~0x7f) diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/cmsis/cm4/device_support/system_at32f423.c b/bsp/at32/libraries/AT32F423_Firmware_Library/cmsis/cm4/device_support/system_at32f423.c index 554d59dbd1..67641a9e70 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/cmsis/cm4/device_support/system_at32f423.c +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/cmsis/cm4/device_support/system_at32f423.c @@ -91,8 +91,9 @@ void SystemInit (void) /* reset pllms pllns pllfr pllrcs bits */ CRM->pllcfg = 0x00033002U; - /* reset clkout_sel, clkoutdiv, pllclk_to_adc, hick_to_sclk, hick_to_usb, hickdiv */ - CRM->misc1 = 0x000F0000U; + /* reset clkout_sel, clkoutdiv, pllclk_to_adc, hick_to_usb */ + CRM->misc1 &= 0x00005000U; + CRM->misc1 |= 0x000F0000U; /* disable all interrupts enable and clear pending bits */ CRM->clkint = 0x009F0000U; @@ -118,7 +119,7 @@ void SystemInit (void) void system_core_clock_update(void) { uint32_t pll_ns = 0, pll_ms = 0, pll_fr = 0, pll_clock_source = 0, pllrcsfreq = 0; - uint32_t temp = 0, div_value = 0; + uint32_t temp = 0, div_value = 0, psc = 0; crm_sclk_type sclk_source; static const uint8_t sys_ahb_div_table[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; @@ -134,9 +135,14 @@ void system_core_clock_update(void) system_core_clock = HICK_VALUE * 6; else system_core_clock = HICK_VALUE; + + psc = CRM->misc2_bit.hick_to_sclk_div; + system_core_clock = system_core_clock >> psc; break; case CRM_SCLK_HEXT: system_core_clock = HEXT_VALUE; + psc = CRM->misc2_bit.hext_to_sclk_div; + system_core_clock = system_core_clock >> psc; break; case CRM_SCLK_PLL: /* get pll clock source */ @@ -172,6 +178,18 @@ void system_core_clock_update(void) /* ahbclk frequency */ system_core_clock = system_core_clock >> div_value; } + +/** + * @brief take some delay for waiting power stable, delay is about 60ms with frequency 8MHz. + * @param none + * @retval none + */ +void wait_for_power_stable(void) +{ + volatile uint32_t delay = 0; + for(delay = 0; delay < 50000; delay++); +} + /** * @} */ diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/cmsis/cm4/device_support/system_at32f423.h b/bsp/at32/libraries/AT32F423_Firmware_Library/cmsis/cm4/device_support/system_at32f423.h index e94c0315e2..ddf3f21b26 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/cmsis/cm4/device_support/system_at32f423.h +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/cmsis/cm4/device_support/system_at32f423.h @@ -54,6 +54,7 @@ extern unsigned int system_core_clock; /*!< system clock frequency (core clock) extern void SystemInit(void); extern void system_core_clock_update(void); +extern void wait_for_power_stable(void); /** * @} diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_acc.h b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_acc.h index cdf746cf42..451390ffd6 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_acc.h +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_acc.h @@ -179,6 +179,7 @@ uint16_t acc_read_c1(void); uint16_t acc_read_c2(void); uint16_t acc_read_c3(void); flag_status acc_flag_get(uint16_t acc_flag); +flag_status acc_interrupt_flag_get(uint16_t acc_flag); void acc_flag_clear(uint16_t acc_flag); /** diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_adc.h b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_adc.h index 9ada0f9d0e..252b8d6226 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_adc.h +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_adc.h @@ -646,7 +646,7 @@ typedef struct }; /** - * @brief adc spt3 register, offset:0x10 + * @brief adc spt3 register, offset:0x50 */ union { @@ -666,7 +666,7 @@ typedef struct }; /** - * @brief adc osq4 register, offset:0x34 + * @brief adc osq4 register, offset:0x54 */ union { @@ -684,7 +684,7 @@ typedef struct }; /** - * @brief adc osq5 register, offset:0x34 + * @brief adc osq5 register, offset:0x58 */ union { @@ -702,7 +702,7 @@ typedef struct }; /** - * @brief adc osq6 register, offset:0x34 + * @brief adc osq6 register, offset:0x5c */ union { @@ -860,6 +860,7 @@ flag_status adc_preempt_software_trigger_status_get(adc_type *adc_x); uint16_t adc_ordinary_conversion_data_get(adc_type *adc_x); uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel); flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag); +flag_status adc_interrupt_flag_get(adc_type *adc_x, uint8_t adc_flag); void adc_flag_clear(adc_type *adc_x, uint32_t adc_flag); void adc_ordinary_oversample_enable(adc_type *adc_x, confirm_state new_state); void adc_preempt_oversample_enable(adc_type *adc_x, confirm_state new_state); diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_can.h b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_can.h index 144a8e298b..e6cb5294be 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_can.h +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_can.h @@ -962,6 +962,7 @@ can_error_record_type can_error_type_record_get(can_type* can_x); uint8_t can_receive_error_counter_get(can_type* can_x); uint8_t can_transmit_error_counter_get(can_type* can_x); void can_interrupt_enable(can_type* can_x, uint32_t can_int, confirm_state new_state); +flag_status can_interrupt_flag_get(can_type* can_x, uint32_t can_flag); flag_status can_flag_get(can_type* can_x, uint32_t can_flag); void can_flag_clear(can_type* can_x, uint32_t can_flag); diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_crc.h b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_crc.h index 0549818284..af2a297b88 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_crc.h +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_crc.h @@ -66,6 +66,17 @@ typedef enum CRC_REVERSE_OUTPUT_DATA = 0x01 /*!< output data reverse by word */ } crc_reverse_output_type; +/** + * @brief crc polynomial size + */ +typedef enum +{ + CRC_POLY_SIZE_32B = 0x00, /*!< polynomial size 32 bits */ + CRC_POLY_SIZE_16B = 0x01, /*!< polynomial size 16 bits */ + CRC_POLY_SIZE_8B = 0x02, /*!< polynomial size 8 bits */ + CRC_POLY_SIZE_7B = 0x03 /*!< polynomial size 7 bits */ +} crc_poly_size_type; + /** * @brief type define crc register all */ @@ -105,7 +116,8 @@ typedef struct struct { __IO uint32_t rst : 1 ; /* [0] */ - __IO uint32_t reserved1 : 4 ; /* [4:1] */ + __IO uint32_t reserved1 : 2 ; /* [2:1] */ + __IO uint32_t poly_size : 2 ; /* [4:3] */ __IO uint32_t revid : 2 ; /* [6:5] */ __IO uint32_t revod : 1 ; /* [7] */ __IO uint32_t reserved2 : 24 ;/* [31:8] */ @@ -129,6 +141,18 @@ typedef struct } idt_bit; }; + /** + * @brief crc polynomial register, offset:0x14 + */ + union + { + __IO uint32_t poly; + struct + { + __IO uint32_t poly : 32; /* [31:0] */ + } poly_bit; + }; + } crc_type; /** @@ -150,6 +174,10 @@ uint8_t crc_common_data_get(void); void crc_init_data_set(uint32_t value); void crc_reverse_input_data_set(crc_reverse_input_type value); void crc_reverse_output_data_set(crc_reverse_output_type value); +void crc_poly_value_set(uint32_t value); +uint32_t crc_poly_value_get(void); +void crc_poly_size_set(crc_poly_size_type size); +crc_poly_size_type crc_poly_size_get(void); /** * @} diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_crm.h b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_crm.h index 88be1015bc..c28177464a 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_crm.h +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_crm.h @@ -384,7 +384,7 @@ typedef enum CRM_USB_DIV_7 = 0x04, /*!< pllclk div7 to usbclk */ CRM_USB_DIV_6 = 0x05, /*!< pllclk div6 to usbclk */ CRM_USB_DIV_9 = 0x06, /*!< pllclk div9 to usbclk */ - CRM_USB_DIV_8 = 0x07, /*!< pllclk div8 to usbclk */ + CRM_USB_DIV_8 = 0x07 /*!< pllclk div8 to usbclk */ } crm_usb_div_type; /** @@ -1183,6 +1183,7 @@ void crm_reset(void); void crm_lext_bypass(confirm_state new_state); void crm_hext_bypass(confirm_state new_state); flag_status crm_flag_get(uint32_t flag); +flag_status crm_interrupt_flag_get(uint32_t flag); error_status crm_hext_stable_wait(void); void crm_hick_clock_trimming_set(uint8_t trim_value); void crm_hick_clock_calibration_set(uint8_t cali_value); diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_dac.h b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_dac.h index c13fd117b6..45756bf3f7 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_dac.h +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_dac.h @@ -371,6 +371,7 @@ void dac_2_data_set(dac2_aligned_data_type dac2_aligned, uint16_t dac2_data); void dac_dual_data_set(dac_dual_data_type dac_dual, uint16_t data1, uint16_t data2); void dac_udr_enable(dac_select_type dac_select, confirm_state new_state); flag_status dac_udr_flag_get(dac_select_type dac_select); +flag_status dac_udr_interrupt_flag_get(dac_select_type dac_select); void dac_udr_flag_clear(dac_select_type dac_select); /** diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_debug.h b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_debug.h index 142281933d..d0e1f34761 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_debug.h +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_debug.h @@ -115,6 +115,7 @@ typedef struct __IO uint32_t reserved1 : 29;/* [31:3] */ } ctrl_bit; }; + /** * @brief debug apb1 frz register, offset:0x08 */ @@ -147,8 +148,9 @@ typedef struct __IO uint32_t reserved5 : 3;/* [31:29] */ } apb1_frz_bit; }; + /** - * @brief debug apb2 frz register, offset:0x0c + * @brief debug apb2 frz register, offset:0x0C */ union { @@ -167,6 +169,26 @@ typedef struct } apb2_frz_bit; }; + /** + * @brief debug reserved1 register, offset:0x10~0x1C + */ + __IO uint32_t reserved1[4]; + + /** + * @brief debug ser id register, offset:0x20 + */ + union + { + __IO uint32_t ser_id; + struct + { + __IO uint32_t rev_id : 3;/* [2:0] */ + __IO uint32_t reserved1 : 5;/* [7:3] */ + __IO uint32_t ser_id : 8;/* [15:8] */ + __IO uint32_t reserved2 : 16;/* [31:16] */ + } ser_id_bit; + }; + } debug_type; /** diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_dma.h b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_dma.h index ee390acb8b..8a5304f86a 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_dma.h +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_dma.h @@ -730,6 +730,7 @@ uint16_t dma_data_number_get(dma_channel_type *dmax_channely); void dma_interrupt_enable(dma_channel_type *dmax_channely, uint32_t dma_int, confirm_state new_state); void dma_channel_enable(dma_channel_type *dmax_channely, confirm_state new_state); flag_status dma_flag_get(uint32_t dmax_flag); +flag_status dma_interrupt_flag_get(uint32_t dmax_flag); void dma_flag_clear(uint32_t dmax_flag); void dma_default_para_init(dma_init_type *dma_init_struct); void dma_init(dma_channel_type *dmax_channely, dma_init_type *dma_init_struct); @@ -745,8 +746,10 @@ void dmamux_generator_config(dmamux_generator_type *dmamux_gen_x, dmamux_gen_ini void dmamux_sync_interrupt_enable(dmamux_channel_type *dmamux_channelx, confirm_state new_state); void dmamux_generator_interrupt_enable(dmamux_generator_type *dmamux_gen_x, confirm_state new_state); flag_status dmamux_sync_flag_get(dma_type *dma_x, uint32_t flag); +flag_status dmamux_sync_interrupt_flag_get(dma_type *dma_x, uint32_t flag); void dmamux_sync_flag_clear(dma_type *dma_x, uint32_t flag); flag_status dmamux_generator_flag_get(dma_type *dma_x, uint32_t flag); +flag_status dmamux_generator_interrupt_flag_get(dma_type *dma_x, uint32_t flag); void dmamux_generator_flag_clear(dma_type *dma_x, uint32_t flag); /** diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_ertc.h b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_ertc.h index 9e2cd2727f..a9c23541cf 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_ertc.h +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_ertc.h @@ -1170,6 +1170,7 @@ void ertc_tamper_enable(ertc_tamper_select_type tamper_x, confirm_state new_stat void ertc_interrupt_enable(uint32_t source, confirm_state new_state); flag_status ertc_interrupt_get(uint32_t source); flag_status ertc_flag_get(uint32_t flag); +flag_status ertc_interrupt_flag_get(uint32_t flag); void ertc_flag_clear(uint32_t flag); void ertc_bpr_data_write(ertc_dt_type dt, uint32_t data); uint32_t ertc_bpr_data_read(ertc_dt_type dt); diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_exint.h b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_exint.h index ca07a6805d..9819749f22 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_exint.h +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_exint.h @@ -210,6 +210,7 @@ void exint_default_para_init(exint_init_type *exint_struct); void exint_init(exint_init_type *exint_struct); void exint_flag_clear(uint32_t exint_line); flag_status exint_flag_get(uint32_t exint_line); +flag_status exint_interrupt_flag_get(uint32_t exint_line); void exint_software_interrupt_event_generate(uint32_t exint_line); void exint_interrupt_enable(uint32_t exint_line, confirm_state new_state); void exint_event_enable(uint32_t exint_line, confirm_state new_state); diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_i2c.h b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_i2c.h index 7b2223e1cf..0b623ecb3a 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_i2c.h +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_i2c.h @@ -155,12 +155,12 @@ typedef enum { I2C_ADDR2_NOMASK = 0x00, /*!< compare bit [7:1] */ I2C_ADDR2_MASK01 = 0x01, /*!< only compare bit [7:2] */ - I2C_ADDR2_MASK02 = 0x02, /*!< only compare bit [7:2] */ - I2C_ADDR2_MASK03 = 0x03, /*!< only compare bit [7:3] */ - I2C_ADDR2_MASK04 = 0x04, /*!< only compare bit [7:4] */ - I2C_ADDR2_MASK05 = 0x05, /*!< only compare bit [7:5] */ - I2C_ADDR2_MASK06 = 0x06, /*!< only compare bit [7:6] */ - I2C_ADDR2_MASK07 = 0x07 /*!< only compare bit [7] */ + I2C_ADDR2_MASK02 = 0x02, /*!< only compare bit [7:3] */ + I2C_ADDR2_MASK03 = 0x03, /*!< only compare bit [7:4] */ + I2C_ADDR2_MASK04 = 0x04, /*!< only compare bit [7:5] */ + I2C_ADDR2_MASK05 = 0x05, /*!< only compare bit [7:6] */ + I2C_ADDR2_MASK06 = 0x06, /*!< only compare bit [7] */ + I2C_ADDR2_MASK07 = 0x07 /*!< response all addresses other than those reserved for i2c */ } i2c_addr2_mask_type; /** @@ -457,6 +457,7 @@ void i2c_stop_generate(i2c_type *i2c_x); void i2c_data_send(i2c_type *i2c_x, uint8_t data); uint8_t i2c_data_receive(i2c_type *i2c_x); flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag); +flag_status i2c_interrupt_flag_get(i2c_type *i2c_x, uint32_t flag); void i2c_flag_clear(i2c_type *i2c_x, uint32_t flag); void i2c_wakeup_enable(i2c_type *i2c_x, confirm_state new_state); void i2c_analog_filter_enable(i2c_type *i2c_x, confirm_state new_state); diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_pwc.h b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_pwc.h index a19b269ecc..5e19bbd32e 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_pwc.h +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_pwc.h @@ -58,10 +58,10 @@ extern "C" { /** * @brief pwc wakeup pin num definition */ -#define PWC_WAKEUP_PIN_1 ((uint32_t)0x00000100) /*!< standby wake-up pin1 */ -#define PWC_WAKEUP_PIN_2 ((uint32_t)0x00000200) /*!< standby wake-up pin2 */ -#define PWC_WAKEUP_PIN_6 ((uint32_t)0x00002000) /*!< standby wake-up pin6 */ -#define PWC_WAKEUP_PIN_7 ((uint32_t)0x00004000) /*!< standby wake-up pin7 */ +#define PWC_WAKEUP_PIN_1 ((uint32_t)0x00000100) /*!< standby wake-up pin1(pa0) */ +#define PWC_WAKEUP_PIN_2 ((uint32_t)0x00000200) /*!< standby wake-up pin2(pc13) */ +#define PWC_WAKEUP_PIN_6 ((uint32_t)0x00002000) /*!< standby wake-up pin6(pb5) */ +#define PWC_WAKEUP_PIN_7 ((uint32_t)0x00004000) /*!< standby wake-up pin7(pb15) */ /** * @brief select ldo output voltage. @@ -70,8 +70,7 @@ extern "C" { * - PWC_LDO_OUTPUT_1V3: system clock up to 150MHz. * - PWC_LDO_OUTPUT_1V2: system clock up to 120MHz. * - PWC_LDO_OUTPUT_1V0: system clock up to 64MHz. - * @note useage limited. - * PWC_LDO_OUTPUT_1V3: operation temperature range -40~85 degree, VDD must over 3.0V. + * @note none. */ #define pwc_ldo_output_voltage_set(val) (PWC->ldoov_bit.ldoovsel = val) diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_scfg.h b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_scfg.h index 30c2170587..85235fddea 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_scfg.h +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_scfg.h @@ -54,9 +54,7 @@ extern "C" { */ typedef enum { - SCFG_IR_SOURCE_TMR10 = 0x00, /* infrared signal source select tmr10 */ - SCFG_IR_SOURCE_USART1 = 0x01, /* infrared signal source select usart1 */ - SCFG_IR_SOURCE_USART2 = 0x02 /* infrared signal source select usart2 */ + SCFG_IR_SOURCE_TMR10 = 0x00 /* infrared signal source select tmr10 */ } scfg_ir_source_type; /** @@ -277,7 +275,7 @@ typedef struct void scfg_reset(void); void scfg_infrared_config(scfg_ir_source_type source, scfg_ir_polarity_type polarity); -uint8_t scfg_mem_map_get(void); +scfg_mem_map_type scfg_mem_map_get(void); void scfg_i2s_full_duplex_config(scfg_i2s_type i2s_full_duplex); void scfg_pvm_lock_enable(confirm_state new_state); void scfg_lockup_enable(confirm_state new_state); diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_spi.h b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_spi.h index 20b04d4207..93601d0b73 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_spi.h +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_spi.h @@ -479,6 +479,7 @@ void spi_i2s_dma_receiver_enable(spi_type* spi_x, confirm_state new_state); void spi_i2s_data_transmit(spi_type* spi_x, uint16_t tx_data); uint16_t spi_i2s_data_receive(spi_type* spi_x); flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag); +flag_status spi_i2s_interrupt_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag); void spi_i2s_flag_clear(spi_type* spi_x, uint32_t spi_i2s_flag); /** diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_tmr.h b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_tmr.h index 3a2c46c427..5b3333d1cc 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_tmr.h +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_tmr.h @@ -804,7 +804,8 @@ typedef struct __IO uint32_t brkv : 1; /* [13] */ __IO uint32_t aoen : 1; /* [14] */ __IO uint32_t oen : 1; /* [15] */ - __IO uint32_t reserved1 : 16; /* [31:16] */ + __IO uint32_t bkf : 4; /* [19:16] */ + __IO uint32_t reserved1 : 12;/* [31:20] */ } brk_bit; }; /** @@ -957,6 +958,7 @@ void tmr_trigger_input_select(tmr_type *tmr_x, sub_tmr_input_sel_type trigger_se void tmr_sub_sync_mode_set(tmr_type *tmr_x, confirm_state new_state); void tmr_dma_request_enable(tmr_type *tmr_x, tmr_dma_request_type dma_request, confirm_state new_state); void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state new_state); +flag_status tmr_interrupt_flag_get(tmr_type *tmr_x, uint32_t tmr_flag); flag_status tmr_flag_get(tmr_type *tmr_x, uint32_t tmr_flag); void tmr_flag_clear(tmr_type *tmr_x, uint32_t tmr_flag); void tmr_event_sw_trigger(tmr_type *tmr_x, tmr_event_trigger_type tmr_event); @@ -977,6 +979,7 @@ void tmr_force_output_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, void tmr_dma_control_config(tmr_type *tmr_x, tmr_dma_transfer_length_type dma_length, \ tmr_dma_address_type dma_base_address); void tmr_brkdt_config(tmr_type *tmr_x, tmr_brkdt_config_type *brkdt_struct); +void tmr_brk_filter_value_set(tmr_type *tmr_x, uint8_t filter_value); void tmr_iremap_config(tmr_type *tmr_x, tmr_input_remap_type input_remap); /** diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_usart.h b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_usart.h index c557e0dc46..083ba99fb3 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_usart.h +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_usart.h @@ -418,8 +418,7 @@ typedef struct #define USART5 ((usart_type *) USART5_BASE) #define USART6 ((usart_type *) USART6_BASE) #define USART7 ((usart_type *) USART7_BASE) -#if defined (AT32F423Kx) || defined (AT32F423Tx) || defined (AT32F423Cx) || \ - defined (AT32F423Rx) || defined (AT32F423Vx) +#if defined (AT32F423Rx) || defined (AT32F423Vx) #define USART8 ((usart_type *) USART8_BASE) #endif @@ -455,6 +454,7 @@ void usart_irda_mode_enable(usart_type* usart_x, confirm_state new_state); void usart_irda_low_power_enable(usart_type* usart_x, confirm_state new_state); void usart_hardware_flow_control_set(usart_type* usart_x,usart_hardware_flow_control_type flow_state); flag_status usart_flag_get(usart_type* usart_x, uint32_t flag); +flag_status usart_interrupt_flag_get(usart_type* usart_x, uint32_t flag); void usart_flag_clear(usart_type* usart_x, uint32_t flag); void usart_rs485_delay_time_config(usart_type* usart_x, uint8_t start_delay_time, uint8_t complete_delay_time); void usart_transmit_receive_pin_swap(usart_type* usart_x, confirm_state new_state); diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_wwdt.h b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_wwdt.h index 674f8c1ac3..68e059cbdb 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_wwdt.h +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_wwdt.h @@ -134,6 +134,7 @@ void wwdt_flag_clear(void); void wwdt_enable(uint8_t wwdt_cnt); void wwdt_interrupt_enable(void); flag_status wwdt_flag_get(void); +flag_status wwdt_interrupt_flag_get(void); void wwdt_counter_set(uint8_t wwdt_cnt); void wwdt_window_counter_set(uint8_t window_cnt); diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_xmc.h b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_xmc.h index f741308133..8e70019392 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_xmc.h +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/inc/at32f423_xmc.h @@ -368,7 +368,7 @@ void xmc_norsram_default_para_init(xmc_norsram_init_type* xmc_nor_sram_init_stru void xmc_norsram_timing_default_para_init(xmc_norsram_timing_init_type* xmc_rw_timing_struct, xmc_norsram_timing_init_type* xmc_w_timing_struct); void xmc_nor_sram_enable(xmc_nor_sram_subbank_type xmc_subbank, confirm_state new_state); -void xmc_ext_timing_config(xmc_nor_sram_subbank_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing); +void xmc_ext_timing_config(volatile xmc_nor_sram_subbank_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing); /** diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_acc.c b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_acc.c index 40286b3e6f..7d1e3d0f38 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_acc.c +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_acc.c @@ -189,6 +189,22 @@ flag_status acc_flag_get(uint16_t acc_flag) return (flag_status)(ACC->sts_bit.rslost); } +/** + * @brief check whether the specified acc interrupt flag is set or not. + * @param acc_flag: specifies the flag to check. + * this parameter can be one of the following values: + * - ACC_RSLOST_FLAG + * - ACC_CALRDY_FLAG + * @retval flag_status (SET or RESET) + */ +flag_status acc_interrupt_flag_get(uint16_t acc_flag) +{ + if(acc_flag == ACC_CALRDY_FLAG) + return (flag_status)(ACC->sts_bit.calrdy && ACC->ctrl1_bit.calrdyien); + else + return (flag_status)(ACC->sts_bit.rslost && ACC->ctrl1_bit.eien); +} + /** * @brief clear the specified acc flag is set or not. * @param acc_flag: specifies the flag to check. diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_adc.c b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_adc.c index 8a4649707f..6a3c970a8f 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_adc.c +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_adc.c @@ -888,6 +888,54 @@ flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag) return status; } +/** + * @brief get interrupt flag of the specified adc peripheral. + * @param adc_x: select the adc peripheral. + * this parameter can be one of the following values: + * - ADC1. + * @param adc_flag: select the adc flag. + * this parameter can be one of the following values: + * - ADC_VMOR_FLAG + * - ADC_OCCE_FLAG + * - ADC_PCCE_FLAG + * - ADC_OCCO_FLAG + * @retval the new state of adc flag status(SET or RESET). + */ +flag_status adc_interrupt_flag_get(adc_type *adc_x, uint8_t adc_flag) +{ + flag_status status = RESET; + switch(adc_flag) + { + case ADC_VMOR_FLAG: + if(adc_x->sts_bit.vmor && adc_x->ctrl1_bit.vmorien) + { + status = SET; + } + break; + case ADC_OCCE_FLAG: + if(adc_x->sts_bit.occe && adc_x->ctrl1_bit.occeien) + { + status = SET; + } + break; + case ADC_PCCE_FLAG: + if(adc_x->sts_bit.pcce && adc_x->ctrl1_bit.pcceien) + { + status = SET; + } + break; + case ADC_OCCO_FLAG: + if(adc_x->sts_bit.occo && adc_x->ctrl1_bit.occoien) + { + status = SET; + } + break; + default: + break; + } + return status; +} + /** * @brief clear flag of the specified adc peripheral. * @param adc_x: select the adc peripheral. diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_can.c b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_can.c index 37ddae02a7..4c73f31804 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_can.c +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_can.c @@ -931,6 +931,102 @@ void can_interrupt_enable(can_type* can_x, uint32_t can_int, confirm_state new_s } } +/** + * @brief get interrupt flag of the specified can peripheral. + * @param can_x: select the can peripheral. + * this parameter can be one of the following values: + * CAN1, CAN2. + * @param can_flag: select the flag. + * this parameter can be one of the following flags: + * - CAN_EAF_FLAG + * - CAN_EPF_FLAG + * - CAN_BOF_FLAG + * - CAN_ETR_FLAG + * - CAN_EOIF_FLAG + * - CAN_TM0TCF_FLAG + * - CAN_TM1TCF_FLAG + * - CAN_TM2TCF_FLAG + * - CAN_RF0MN_FLAG + * - CAN_RF0FF_FLAG + * - CAN_RF0OF_FLAG + * - CAN_RF1MN_FLAG + * - CAN_RF1FF_FLAG + * - CAN_RF1OF_FLAG + * - CAN_QDZIF_FLAG + * - CAN_EDZC_FLAG + * - CAN_TMEF_FLAG + * note:the state of CAN_EDZC_FLAG need to check dzc and edzif bit + * note:the state of CAN_TMEF_FLAG need to check rqc0,rqc1 and rqc2 bit + * @retval status of can_flag, the returned value can be:SET or RESET. + */ +flag_status can_interrupt_flag_get(can_type* can_x, uint32_t can_flag) +{ + flag_status bit_status = RESET; + flag_status int_status = RESET; + + switch(can_flag) + { + case CAN_EAF_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.eaien); + break; + case CAN_EPF_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.epien); + break; + case CAN_BOF_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.boien); + break; + case CAN_ETR_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.etrien); + break; + case CAN_EOIF_FLAG: + int_status = (flag_status)can_x->inten_bit.eoien; + break; + case CAN_TM0TCF_FLAG: + case CAN_TM1TCF_FLAG: + case CAN_TM2TCF_FLAG: + int_status = (flag_status)can_x->inten_bit.tcien; + break; + case CAN_RF0MN_FLAG: + int_status = (flag_status)can_x->inten_bit.rf0mien; + break; + case CAN_RF0FF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf0fien; + break; + case CAN_RF0OF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf0oien; + break; + case CAN_RF1MN_FLAG: + int_status = (flag_status)can_x->inten_bit.rf1mien; + break; + case CAN_RF1FF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf1fien; + break; + case CAN_RF1OF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf1oien; + break; + case CAN_QDZIF_FLAG: + int_status = (flag_status)can_x->inten_bit.qdzien; + break; + case CAN_EDZC_FLAG: + int_status = (flag_status)can_x->inten_bit.edzien; + break; + case CAN_TMEF_FLAG: + int_status = (flag_status)can_x->inten_bit.tcien; + break; + default: + int_status = RESET; + break; + } + + if(int_status != SET) + { + return RESET; + } + bit_status = can_flag_get(can_x, can_flag); + + return bit_status; +} + /** * @brief get flag of the specified can peripheral. * @param can_x: select the can peripheral. diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_crc.c b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_crc.c index 903c5fa9af..f0fa3b2c7d 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_crc.c +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_crc.c @@ -147,6 +147,52 @@ void crc_reverse_output_data_set(crc_reverse_output_type value) CRC->ctrl_bit.revod = value; } +/** + * @brief config crc polynomial value + * @param value + * 32-bit new data of crc poly value + * @retval none. + */ +void crc_poly_value_set(uint32_t value) +{ + CRC->poly = value; +} + +/** + * @brief return crc polynomial value + * @param none + * @retval 32-bit value of the polynomial value. + */ +uint32_t crc_poly_value_get(void) +{ + return (CRC->poly); +} + +/** + * @brief config crc polynomial data size + * @param size + * this parameter can be one of the following values: + * - CRC_POLY_SIZE_32B + * - CRC_POLY_SIZE_16B + * - CRC_POLY_SIZE_8B + * - CRC_POLY_SIZE_7B + * @retval none. + */ +void crc_poly_size_set(crc_poly_size_type size) +{ + CRC->ctrl_bit.poly_size = size; +} + +/** + * @brief return crc polynomial data size + * @param none + * @retval polynomial data size. + */ +crc_poly_size_type crc_poly_size_get(void) +{ + return (crc_poly_size_type)(CRC->ctrl_bit.poly_size); +} + /** * @} */ diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_crm.c b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_crm.c index b572e62dd7..da2b3aaf1c 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_crm.c +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_crm.c @@ -71,8 +71,9 @@ void crm_reset(void) /* reset pllms pllns pllfr pllrcs bits */ CRM->pllcfg = 0x00033002U; - /* reset clkout_sel, clkoutdiv, pllclk_to_adc, hick_to_sclk, hick_to_usb, hickdiv */ - CRM->misc1 = 0x000F0000U; + /* reset clkout_sel, clkoutdiv, pllclk_to_adc, hick_to_usb */ + CRM->misc1 &= 0x00005000U; + CRM->misc1 |= 0x000F0000U; /* disable all interrupts enable and clear pending bits */ CRM->clkint = 0x009F0000U; @@ -139,6 +140,64 @@ flag_status crm_flag_get(uint32_t flag) return status; } +/** + * @brief get crm interrupt flag status + * @param flag + * this parameter can be one of the following values: + * - CRM_LICK_READY_INT_FLAG + * - CRM_LEXT_READY_INT_FLAG + * - CRM_HICK_READY_INT_FLAG + * - CRM_HEXT_READY_INT_FLAG + * - CRM_PLL_READY_INT_FLAG + * - CRM_CLOCK_FAILURE_INT_FLAG + * @retval flag_status (SET or RESET) + */ +flag_status crm_interrupt_flag_get(uint32_t flag) +{ + flag_status status = RESET; + switch(flag) + { + case CRM_LICK_READY_INT_FLAG: + if(CRM->clkint_bit.lickstblf && CRM->clkint_bit.lickstblien) + { + status = SET; + } + break; + case CRM_LEXT_READY_INT_FLAG: + if(CRM->clkint_bit.lextstblf && CRM->clkint_bit.lextstblien) + { + status = SET; + } + break; + case CRM_HICK_READY_INT_FLAG: + if(CRM->clkint_bit.hickstblf && CRM->clkint_bit.hickstblien) + { + status = SET; + } + break; + case CRM_HEXT_READY_INT_FLAG: + if(CRM->clkint_bit.hextstblf && CRM->clkint_bit.hextstblien) + { + status = SET; + } + break; + case CRM_PLL_READY_INT_FLAG: + if(CRM->clkint_bit.pllstblf && CRM->clkint_bit.pllstblien) + { + status = SET; + } + break; + case CRM_CLOCK_FAILURE_INT_FLAG: + if(CRM->clkint_bit.cfdf && CRM->ctrl_bit.cfden) + { + status = SET; + } + break; + } + + return status; +} + /** * @brief wait for hext stable * @param none @@ -711,7 +770,22 @@ void crm_adc_clock_select(crm_adc_clock_source_type value) */ void crm_hick_divider_select(crm_hick_div_6_type value) { + __IO uint8_t temp_div = CRM->misc2_bit.hick_to_sclk_div; + __IO uint8_t temp_sclk = CRM->misc1_bit.hick_to_sclk; + + crm_hick_sclk_div_set(CRM_HICK_SCLK_DIV_16); + /* delay */ + { + __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP(); + __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP(); + __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP(); + __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP(); + } + + CRM->misc1_bit.hick_to_sclk = TRUE; CRM->misc1_bit.hickdiv = value; + CRM->misc1_bit.hick_to_sclk = temp_sclk; + crm_hick_sclk_div_set((crm_hick_sclk_div_type)temp_div); } /** @@ -724,7 +798,7 @@ void crm_hick_divider_select(crm_hick_div_6_type value) */ void crm_hick_sclk_frequency_select(crm_hick_sclk_frequency_type value) { - __IO uint8_t temp_reg = CRM->misc2_bit.hick_to_sclk_div; + __IO uint8_t temp_div = CRM->misc2_bit.hick_to_sclk_div; crm_hick_sclk_div_set(CRM_HICK_SCLK_DIV_16); /* delay */ @@ -736,9 +810,9 @@ void crm_hick_sclk_frequency_select(crm_hick_sclk_frequency_type value) } CRM->misc1_bit.hick_to_sclk = TRUE; - crm_hick_divider_select(CRM_HICK48_NODIV); + CRM->misc1_bit.hickdiv = CRM_HICK48_NODIV; CRM->misc1_bit.hick_to_sclk = value; - crm_hick_sclk_div_set((crm_hick_sclk_div_type)temp_reg); + crm_hick_sclk_div_set((crm_hick_sclk_div_type)temp_div); } /** @@ -849,7 +923,7 @@ crm_sclk_type crm_sysclk_switch_status_get(void) void crm_clocks_freq_get(crm_clocks_freq_type *clocks_struct) { uint32_t pll_ns = 0, pll_ms = 0, pll_fr = 0, pll_clock_source = 0, pllrcsfreq = 0; - uint32_t temp = 0, div_value = 0; + uint32_t temp = 0, div_value = 0, psc = 0; crm_sclk_type sclk_source; static const uint8_t sclk_ahb_div_table[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; @@ -867,9 +941,14 @@ void crm_clocks_freq_get(crm_clocks_freq_type *clocks_struct) clocks_struct->sclk_freq = HICK_VALUE * 6; else clocks_struct->sclk_freq = HICK_VALUE; + + psc = CRM->misc2_bit.hick_to_sclk_div; + clocks_struct->sclk_freq = clocks_struct->sclk_freq >> psc; break; case CRM_SCLK_HEXT: clocks_struct->sclk_freq = HEXT_VALUE; + psc = CRM->misc2_bit.hext_to_sclk_div; + clocks_struct->sclk_freq = clocks_struct->sclk_freq >> psc; break; case CRM_SCLK_PLL: /* get pll clock source */ diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_dac.c b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_dac.c index ca9fda4e3c..24bfb5e60e 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_dac.c +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_dac.c @@ -414,6 +414,34 @@ flag_status dac_udr_flag_get(dac_select_type dac_select) return status; } +/** + * @brief get flag of the dac udr interrupt flag. + * @param dac_select + * this parameter can be one of the following values: + * - DAC1_SELECT + * - DAC2_SELECT + * @retval the new state of dac udr flag status(SET or RESET). + */ +flag_status dac_udr_interrupt_flag_get(dac_select_type dac_select) +{ + flag_status status = RESET; + + switch(dac_select) + { + case DAC1_SELECT: + if((DAC->sts_bit.d1dmaudrf && DAC->ctrl_bit.d1dmaudrien) != 0) + status = SET; + break; + case DAC2_SELECT: + if((DAC->sts_bit.d2dmaudrf && DAC->ctrl_bit.d2dmaudrien) != 0) + status = SET; + break; + default: + break; + } + return status; +} + /** * @brief clear the dac udr flag. * @param dac_select diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_dma.c b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_dma.c index e0482717ed..b4d8c7c061 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_dma.c +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_dma.c @@ -197,6 +197,48 @@ void dma_channel_enable(dma_channel_type *dmax_channely, confirm_state new_state dmax_channely->ctrl_bit.chen = new_state; } +/** + * @brief dma interrupt flag get. + * @param dma_flag + * - DMA1_FDT1_FLAG - DMA1_HDT1_FLAG - DMA1_DTERR1_FLAG + * - DMA1_FDT2_FLAG - DMA1_HDT2_FLAG - DMA1_DTERR2_FLAG + * - DMA1_FDT3_FLAG - DMA1_HDT3_FLAG - DMA1_DTERR3_FLAG + * - DMA1_FDT4_FLAG - DMA1_HDT4_FLAG - DMA1_DTERR4_FLAG + * - DMA1_FDT5_FLAG - DMA1_HDT5_FLAG - DMA1_DTERR5_FLAG + * - DMA1_FDT6_FLAG - DMA1_HDT6_FLAG - DMA1_DTERR6_FLAG + * - DMA1_FDT7_FLAG - DMA1_HDT7_FLAG - DMA1_DTERR7_FLAG + * - DMA2_FDT1_FLAG - DMA2_HDT1_FLAG - DMA2_DTERR1_FLAG + * - DMA2_FDT2_FLAG - DMA2_HDT2_FLAG - DMA2_DTERR2_FLAG + * - DMA2_FDT3_FLAG - DMA2_HDT3_FLAG - DMA2_DTERR3_FLAG + * - DMA2_FDT4_FLAG - DMA2_HDT4_FLAG - DMA2_DTERR4_FLAG + * - DMA2_FDT5_FLAG - DMA2_HDT5_FLAG - DMA2_DTERR5_FLAG + * - DMA2_FDT6_FLAG - DMA2_HDT6_FLAG - DMA2_DTERR6_FLAG + * - DMA2_FDT7_FLAG - DMA2_HDT7_FLAG - DMA2_DTERR7_FLAG + * @retval state of dma flag. + */ +flag_status dma_interrupt_flag_get(uint32_t dmax_flag) +{ + uint32_t temp = 0; + + if(dmax_flag > 0x10000000) + { + temp = DMA2->sts; + } + else + { + temp = DMA1->sts; + } + + if((temp & dmax_flag) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + /** * @brief dma flag get. * @param dma_flag @@ -600,6 +642,78 @@ flag_status dmamux_sync_flag_get(dma_type *dma_x, uint32_t flag) } } +/** + * @brief dmamux sync interrupt flag get. + * @param dma_x : pointer to a dma_type structure, can be DMA1 or DMA2. + * @param flag + * this parameter can be any combination of the following values: + * - DMAMUX_SYNC_OV1_FLAG + * - DMAMUX_SYNC_OV2_FLAG + * - DMAMUX_SYNC_OV3_FLAG + * - DMAMUX_SYNC_OV4_FLAG + * - DMAMUX_SYNC_OV5_FLAG + * - DMAMUX_SYNC_OV6_FLAG + * - DMAMUX_SYNC_OV7_FLAG + * @retval state of dmamux sync flag. + */ +flag_status dmamux_sync_interrupt_flag_get(dma_type *dma_x, uint32_t flag) +{ + + flag_status bitstatus = RESET; + uint32_t sync_int_temp = flag; + uint32_t index = 0; + uint32_t tmpreg = 0, enablestatus = 0; + uint32_t regoffset = 0x4; + + while((sync_int_temp & 0x00000001) == RESET) + { + sync_int_temp = sync_int_temp >> 1; + index++; + } + + if(dma_x == DMA1) + { + tmpreg = *(uint32_t*)(DMA1MUX_BASE + (index * regoffset)); + } + else + { + tmpreg = *(uint32_t*)(DMA2MUX_BASE + (index * regoffset)); + } + + if((tmpreg & (uint32_t)0x00000100) != (uint32_t)RESET) + { + enablestatus = SET; + } + else + { + enablestatus = RESET; + } + + if(dma_x == DMA1) + { + if(((DMA1->muxsyncsts & flag) != (uint32_t)RESET) && (enablestatus != RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if(((DMA2->muxsyncsts & flag) != (uint32_t)RESET) && (enablestatus != RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + return bitstatus; +} + /** * @brief dmamux sync flag clear. * @param dma_x : pointer to a dma_type structure, can be DMA1 or DMA2. @@ -642,6 +756,70 @@ flag_status dmamux_generator_flag_get(dma_type *dma_x, uint32_t flag) } } +/** + * @brief dmamux request generator interrupt flag get. + * @param dma_x : pointer to a dma_type structure, can be DMA1 or DMA2. + * @param flag + * this parameter can be any combination of the following values: + * - DMAMUX_GEN_TRIG_OV1_FLAG + * - DMAMUX_GEN_TRIG_OV2_FLAG + * - DMAMUX_GEN_TRIG_OV3_FLAG + * - DMAMUX_GEN_TRIG_OV4_FLAG + * @retval state of dmamux sync flag. + */ +flag_status dmamux_generator_interrupt_flag_get(dma_type *dma_x, uint32_t flag) +{ + flag_status bitstatus = RESET; + uint32_t sync_int_temp = flag; + uint32_t index = 0; + uint32_t tmpreg = 0, enablestatus = 0; + uint32_t regoffset = 0x4; + + while((sync_int_temp & 0x00000001) == RESET) + { + sync_int_temp = sync_int_temp >> 1; + index++; + } + + if(dma_x == DMA1) + tmpreg = *(uint32_t*)(DMA1MUX_GENERATOR1_BASE + (index * regoffset)); + else + tmpreg = *(uint32_t*)(DMA2MUX_GENERATOR1_BASE + (index * regoffset)); + + if((tmpreg & (uint32_t)0x00000100) != (uint32_t)RESET) + { + enablestatus = SET; + } + else + { + enablestatus = RESET; + } + if(dma_x == DMA1) + { + if(((DMA1->muxgsts & flag) != (uint32_t)RESET) && (enablestatus != RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if(((DMA2->muxgsts & flag) != (uint32_t)RESET) && (enablestatus != RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + + return bitstatus; +} + /** * @brief dmamux request generator flag clear. * @param dma_x : pointer to a dma_type structure, can be DMA1 or DMA2. diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_ertc.c b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_ertc.c index 71aa4fb100..4dae593dd7 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_ertc.c +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_ertc.c @@ -1402,6 +1402,55 @@ flag_status ertc_flag_get(uint32_t flag) } } +/** + * @brief get interrupt flag status. + * @param flag: specifies the flag to check. + * this parameter can be one of the following values: + * - ERTC_ALAF_FLAG: alarm clock a flag. + * - ERTC_ALBF_FLAG: alarm clock b flag. + * - ERTC_WATF_FLAG: wakeup timer flag. + * - ERTC_TSF_FLAG: timestamp flag. + * - ERTC_TP1F_FLAG: tamper detection 1 flag. + * - ERTC_TP2F_FLAG: tamper detection 2 flag. + * @retval the new state of flag (SET or RESET). + */ +flag_status ertc_interrupt_flag_get(uint32_t flag) +{ + __IO uint32_t iten = 0; + + switch(flag) + { + case ERTC_ALAF_FLAG: + iten = ERTC->ctrl_bit.alaien; + break; + case ERTC_ALBF_FLAG: + iten = ERTC->ctrl_bit.albien; + break; + case ERTC_WATF_FLAG: + iten = ERTC->ctrl_bit.watien; + break; + case ERTC_TSF_FLAG: + iten = ERTC->ctrl_bit.tsien; + break; + case ERTC_TP1F_FLAG: + case ERTC_TP2F_FLAG: + iten = ERTC->tamp_bit.tpien; + break; + + default: + break; + } + + if(((ERTC->sts & flag) != (uint32_t)RESET) && (iten)) + { + return SET; + } + else + { + return RESET; + } +} + /** * @brief clear flag status * @param flag: specifies the flag to clear. diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_exint.c b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_exint.c index e3be6dd1a7..76947dcdb4 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_exint.c +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_exint.c @@ -163,6 +163,40 @@ flag_status exint_flag_get(uint32_t exint_line) return status; } +/** + * @brief get exint interrupt flag + * @param exint_line + * this parameter can be one of the following values: + * - EXINT_LINE_0 + * - EXINT_LINE_1 + * ... + * - EXINT_LINE_18 + * - EXINT_LINE_21 + * - EXINT_LINE_22 + * - EXINT_LINE_23 + * - EXINT_LINE_25 + * - EXINT_LINE_26 + * - EXINT_LINE_28 + * @retval the new state of exint flag(SET or RESET). + */ +flag_status exint_interrupt_flag_get(uint32_t exint_line) +{ + flag_status status = RESET; + uint32_t exint_flag = 0; + exint_flag = EXINT->intsts & exint_line; + exint_flag = exint_flag & EXINT->inten; + + if((exint_flag != (uint16_t)RESET)) + { + status = SET; + } + else + { + status = RESET; + } + return status; +} + /** * @brief generate exint software interrupt event * @param exint_line diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_gpio.c b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_gpio.c index 299fc41d94..14200f6860 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_gpio.c +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_gpio.c @@ -43,7 +43,7 @@ * @brief reset the gpio register * @param gpio_x: to select the gpio peripheral. * this parameter can be one of the following values: - * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH. + * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF. * @retval none */ void gpio_reset(gpio_type *gpio_x) @@ -84,7 +84,7 @@ void gpio_reset(gpio_type *gpio_x) * @brief initialize the gpio peripheral. * @param gpio_x: to select the gpio peripheral. * this parameter can be one of the following values: - * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH. + * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF. * @param gpio_init_struct: pointer to gpio init structure. * @retval none */ @@ -134,7 +134,7 @@ void gpio_default_para_init(gpio_init_type *gpio_init_struct) * @brief read the specified input port pin. * @param gpio_x: to select the gpio peripheral. * this parameter can be one of the following values: - * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH. + * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF. * @param pins: gpio pin number * this parameter can be one of the following values: * - GPIO_PINS_0 @@ -175,7 +175,7 @@ flag_status gpio_input_data_bit_read(gpio_type *gpio_x, uint16_t pins) * @brief read the specified gpio input data port. * @param gpio_x: to select the gpio peripheral. * this parameter can be one of the following values: - * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH. + * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF. * @retval gpio input data port value. */ uint16_t gpio_input_data_read(gpio_type *gpio_x) @@ -187,7 +187,7 @@ uint16_t gpio_input_data_read(gpio_type *gpio_x) * @brief read the specified output port pin. * @param gpio_x: to select the gpio peripheral. * this parameter can be one of the following values: - * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH. + * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF. * @param pins: gpio pin number * this parameter can be one of the following values: * - GPIO_PINS_0 @@ -228,7 +228,7 @@ flag_status gpio_output_data_bit_read(gpio_type *gpio_x, uint16_t pins) * @brief read the specified gpio ouput data port. * @param gpio_x: to select the gpio peripheral. * this parameter can be one of the following values: - * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH. + * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF. * @retval gpio input data port value. */ uint16_t gpio_output_data_read(gpio_type *gpio_x) @@ -240,7 +240,7 @@ uint16_t gpio_output_data_read(gpio_type *gpio_x) * @brief set the selected data port bits. * @param gpio_x: to select the gpio peripheral. * this parameter can be one of the following values: - * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH. + * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF. * @param pins: gpio pin number * parameter can be any combination of gpio_pin_x, gpio_pin_x as following values: * - GPIO_PINS_0 @@ -271,7 +271,7 @@ void gpio_bits_set(gpio_type *gpio_x, uint16_t pins) * @brief clear the selected data port bits. * @param gpio_x: to select the gpio peripheral. * this parameter can be one of the following values: - * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH. + * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF. * @param pins: gpio pin number * parameter can be any combination of gpio_pin_x, gpio_pin_x as following values: * - GPIO_PINS_0 @@ -302,7 +302,7 @@ void gpio_bits_reset(gpio_type *gpio_x, uint16_t pins) * @brief toggle the selected data port bits. * @param gpio_x: to select the gpio peripheral. * this parameter can be one of the following values: - * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH. + * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF. * @param pins: gpio pin number * parameter can be any combination of gpio_pin_x, gpio_pin_x as following values: * - GPIO_PINS_0 @@ -333,7 +333,7 @@ void gpio_bits_toggle(gpio_type *gpio_x, uint16_t pins) * @brief set or clear the selected data port bit. * @param gpio_x: to select the gpio peripheral. * this parameter can be one of the following values: - * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH. + * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF. * @param pins: gpio pin number * parameter can be any combination of gpio_pin_x, gpio_pin_x as following values: * - GPIO_PINS_0 @@ -372,7 +372,7 @@ void gpio_bits_write(gpio_type *gpio_x, uint16_t pins, confirm_state bit_state) * @brief write data to the specified gpio data port. * @param gpio_x: to select the gpio peripheral. * this parameter can be one of the following values: - * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH. + * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF. * @param port_value: specifies the value to be written to the port output data register. * @retval none */ @@ -385,7 +385,7 @@ void gpio_port_write(gpio_type *gpio_x, uint16_t port_value) * @brief write protect gpio pins configuration registers. * @param gpio_x: to select the gpio peripheral. * this parameter can be one of the following values: - * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH. + * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF. * @param pins: gpio pin number * this parameter can be any combination of the following: * - GPIO_PINS_0 @@ -428,7 +428,7 @@ void gpio_pin_wp_config(gpio_type *gpio_x, uint16_t pins) * @brief enable or disable gpio pins huge driven. * @param gpio_x: to select the gpio peripheral. * this parameter can be one of the following values: - * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH. + * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF. * @param pins: gpio pin number * parameter can be any combination of gpio_pin_x, gpio_pin_x as following values: * - GPIO_PINS_0 @@ -468,7 +468,7 @@ void gpio_pins_huge_driven_config(gpio_type *gpio_x, uint16_t pins, confirm_stat * @brief configure the pin's muxing function. * @param gpio_x: to select the gpio peripheral. * this parameter can be one of the following values: - * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH. + * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF. * @param gpio_pin_source: specifies the pin for the muxing function. * this parameter can be one of the following values: * - GPIO_PINS_SOURCE0 diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_i2c.c b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_i2c.c index 22fac2df2a..c9dbebe563 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_i2c.c +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_i2c.c @@ -120,12 +120,12 @@ void i2c_own_address1_set(i2c_type *i2c_x, i2c_address_mode_type mode, uint16_t * this parameter can be one of the following values: * - I2C_ADDR2_NOMASK: compare bit [7:1]. * - I2C_ADDR2_MASK01: only compare bit [7:2]. - * - I2C_ADDR2_MASK02: only compare bit [7:2]. - * - I2C_ADDR2_MASK03: only compare bit [7:3]. - * - I2C_ADDR2_MASK04: only compare bit [7:4]. - * - I2C_ADDR2_MASK05: only compare bit [7:5]. - * - I2C_ADDR2_MASK06: only compare bit [7:6]. - * - I2C_ADDR2_MASK07: only compare bit [7]. + * - I2C_ADDR2_MASK02: only compare bit [7:3]. + * - I2C_ADDR2_MASK03: only compare bit [7:4]. + * - I2C_ADDR2_MASK04: only compare bit [7:5]. + * - I2C_ADDR2_MASK05: only compare bit [7:6]. + * - I2C_ADDR2_MASK06: only compare bit [7]. + * - I2C_ADDR2_MASK07: response all addresses other than those reserved for i2c. * @retval none */ void i2c_own_address2_set(i2c_type *i2c_x, uint8_t address, i2c_addr2_mask_type mask) @@ -708,6 +708,77 @@ flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag) } } +/** + * @brief get interrupt flag status. + * @param i2c_x: to select the i2c peripheral. + * this parameter can be one of the following values: + * I2C1, I2C2, I2C3. + * @param flag: specifies the flag to check. + * this parameter can be one of the following values: + * - I2C_TDBE_FLAG: transmit data buffer empty flag. + * - I2C_TDIS_FLAG: send interrupt status. + * - I2C_RDBF_FLAG: receive data buffer full flag. + * - I2C_ADDRF_FLAG: 0~7 bit address match flag. + * - I2C_ACKFAIL_FLAG: acknowledge failure flag. + * - I2C_STOPF_FLAG: stop condition generation complete flag. + * - I2C_TDC_FLAG: transmit data complete flag. + * - I2C_TCRLD_FLAG: transmission is complete, waiting to load data. + * - I2C_BUSERR_FLAG: bus error flag. + * - I2C_ARLOST_FLAG: arbitration lost flag. + * - I2C_OUF_FLAG: overflow or underflow flag. + * - I2C_PECERR_FLAG: pec receive error flag. + * - I2C_TMOUT_FLAG: smbus timeout flag. + * - I2C_ALERTF_FLAG: smbus alert flag. + * @retval the new state of flag (SET or RESET). + */ +flag_status i2c_interrupt_flag_get(i2c_type *i2c_x, uint32_t flag) +{ + __IO uint32_t iten = 0; + + switch(flag) + { + case I2C_TDIS_FLAG: + iten = i2c_x->ctrl1_bit.tdien; + break; + case I2C_RDBF_FLAG: + iten = i2c_x->ctrl1_bit.rdien; + break; + case I2C_ADDRF_FLAG: + iten = i2c_x->ctrl1_bit.addrien; + break; + case I2C_ACKFAIL_FLAG: + iten = i2c_x->ctrl1_bit.ackfailien; + break; + case I2C_STOPF_FLAG: + iten = i2c_x->ctrl1_bit.stopien; + break; + case I2C_TDC_FLAG: + case I2C_TCRLD_FLAG: + iten = i2c_x->ctrl1_bit.tdcien; + break; + case I2C_BUSERR_FLAG: + case I2C_ARLOST_FLAG: + case I2C_OUF_FLAG: + case I2C_PECERR_FLAG: + case I2C_TMOUT_FLAG: + case I2C_ALERTF_FLAG: + iten = i2c_x->ctrl1_bit.errien; + break; + + default: + break; + } + + if(((i2c_x->sts & flag) != RESET) && (iten)) + { + return SET; + } + else + { + return RESET; + } +} + /** * @brief clear flag status * @param i2c_x: to select the i2c peripheral. diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_scfg.c b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_scfg.c index d485a17c39..c3e278403c 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_scfg.c +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_scfg.c @@ -55,8 +55,6 @@ void scfg_reset(void) * @param source * this parameter can be one of the following values: * - SCFG_IR_SOURCE_TMR10 - * - SCFG_IR_SOURCE_USART1 - * - SCFG_IR_SOURCE_USART2 * @param polarity * this parameter can be one of the following values: * - SCFG_IR_POLARITY_NO_AFFECTE @@ -77,9 +75,13 @@ void scfg_infrared_config(scfg_ir_source_type source, scfg_ir_polarity_type pola * - SCFG_MEM_MAP_BOOT_MEMORY * - SCFG_MEM_MAP_INTERNAL_SRAM */ -uint8_t scfg_mem_map_get(void) +scfg_mem_map_type scfg_mem_map_get(void) { - return (uint8_t)SCFG->cfg1_bit.mem_map_sel; + if(SCFG->cfg1_bit.mem_map_sel & 0x1) + { + return (scfg_mem_map_type)SCFG->cfg1_bit.mem_map_sel; + } + return SCFG_MEM_MAP_MAIN_MEMORY; } /** diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_spi.c b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_spi.c index 0794c3eeb1..9ae28ac20c 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_spi.c +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_spi.c @@ -587,6 +587,76 @@ flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag) return status; } +/** + * @brief get interrupt flag of the specified spi/i2s peripheral. + * @param spi_x: select the spi/i2s peripheral. + * this parameter can be one of the following values: + * SPI1, SPI2, SPI3 + * @param spi_i2s_flag: select the spi/i2s flag + * this parameter can be one of the following values: + * - SPI_I2S_RDBF_FLAG + * - SPI_I2S_TDBE_FLAG + * - I2S_TUERR_FLAG (this flag only use in i2s mode) + * - SPI_CCERR_FLAG (this flag only use in spi mode) + * - SPI_MMERR_FLAG (this flag only use in spi mode) + * - SPI_I2S_ROERR_FLAG + * - SPI_CSPAS_FLAG + * @retval the new state of spi/i2s flag + */ +flag_status spi_i2s_interrupt_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag) +{ + flag_status status = RESET; + + switch(spi_i2s_flag) + { + case SPI_I2S_RDBF_FLAG: + if(spi_x->sts_bit.rdbf && spi_x->ctrl2_bit.rdbfie) + { + status = SET; + } + break; + case SPI_I2S_TDBE_FLAG: + if(spi_x->sts_bit.tdbe && spi_x->ctrl2_bit.tdbeie) + { + status = SET; + } + break; + case I2S_TUERR_FLAG: + if(spi_x->sts_bit.tuerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_CCERR_FLAG: + if(spi_x->sts_bit.ccerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_MMERR_FLAG: + if(spi_x->sts_bit.mmerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_I2S_ROERR_FLAG: + if(spi_x->sts_bit.roerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_CSPAS_FLAG: + if(spi_x->sts_bit.cspas && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + default: + break; + }; + return status; +} + /** * @brief clear flag of the specified spi/i2s peripheral. * @param spi_x: select the spi/i2s peripheral. diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_tmr.c b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_tmr.c index 75f7f7f27e..72bba081ce 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_tmr.c +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_tmr.c @@ -242,7 +242,8 @@ void tmr_cnt_dir_set(tmr_type *tmr_x, tmr_count_mode_type tmr_cnt_dir) * @param tmr_x: select the tmr peripheral. * this parameter can be one of the following values: * TMR1, TMR9, TMR10, TMR11, TMR12, TMR13, TMR14 - * @param tmr_rpr_value (0x0000~0xFFFF) + * @param tmr_rpr_value for TMR1(0x0000~0xFFFF) + * for TMR9, TMR10, TMR11, TMR12, TMR13, TMR14(0x00~0xFF) * @retval none */ void tmr_repetition_counter_set(tmr_type *tmr_x, uint16_t tmr_rpr_value) @@ -286,8 +287,7 @@ uint32_t tmr_counter_value_get(tmr_type *tmr_x) * this parameter can be one of the following values: * TMR1, TMR2, TMR3, TMR4, TMR6, TMR7, * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14 - * @param tmr_div_value (for 16 bit tmr 0x0000~0xFFFF, - * for 32 bit tmr 0x0000_0000~0xFFFF_FFFF) + * @param tmr_div_value (0x0000~0xFFFF) * @retval none */ void tmr_div_value_set(tmr_type *tmr_x, uint32_t tmr_div_value) @@ -1383,6 +1383,40 @@ void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state } } +/** + * @brief get tmr interrupt flag + * @param tmr_x: select the tmr peripheral. + * this parameter can be one of the following values: + * TMR1, TMR2, TMR3, TMR4, TMR6, TMR7, + * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14 + * @param tmr_flag + * this parameter can be one of the following values: + * - TMR_OVF_FLAG + * - TMR_C1_FLAG + * - TMR_C2_FLAG + * - TMR_C3_FLAG + * - TMR_C4_FLAG + * - TMR_HALL_FLAG + * - TMR_TRIGGER_FLAG + * - TMR_BRK_FLAG + * @retval state of tmr interrupt flag + */ +flag_status tmr_interrupt_flag_get(tmr_type *tmr_x, uint32_t tmr_flag) +{ + flag_status status = RESET; + + if((tmr_x->ists & tmr_flag) && (tmr_x->iden & tmr_flag)) + { + status = SET; + } + else + { + status = RESET; + } + + return status; +} + /** * @brief get tmr flag * @param tmr_x: select the tmr peripheral. @@ -1642,7 +1676,7 @@ void tmr_external_clock_mode2_config(tmr_type *tmr_x, tmr_external_signal_divide * @brief config tmr encoder mode * @param tmr_x: select the tmr peripheral. * this parameter can be one of the following values: - * TMR1, TMR2, TMR3, TMR4 + * TMR1, TMR2, TMR3, TMR4, TMR9, TMR12 * @param encoder_mode * this parameter can be one of the following values: * - TMR_ENCODER_MODE_A @@ -1776,7 +1810,7 @@ void tmr_dma_control_config(tmr_type *tmr_x, tmr_dma_transfer_length_type dma_le } /** - * @brief config tmr break mode and dead-time + * @brief config tmr brake mode and dead-time * @param tmr_x: select the tmr peripheral. * this parameter can be one of the following values: * TMR1, TMR9, TMR10, TMR11, TMR12, TMR13, TMR14 @@ -1795,6 +1829,19 @@ void tmr_brkdt_config(tmr_type *tmr_x, tmr_brkdt_config_type *brkdt_struct) tmr_x->brk_bit.wpc = brkdt_struct->wp_level; } +/** + * @brief set tmr break input filter value + * @param tmr_x: select the tmr peripheral. + * this parameter can be one of the following values: + * TMR1, TMR9, TMR10, TMR11, TMR12, TMR13, TMR14 + * @param filter_value (0x0~0xf) + * @retval none + */ +void tmr_brk_filter_value_set(tmr_type *tmr_x, uint8_t filter_value) +{ + tmr_x->brk_bit.bkf = filter_value; +} + /** * @brief set tmr14 input channel remap * @param tmr_x: select the tmr peripheral. diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_usart.c b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_usart.c index dc3378dfd9..9e77885821 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_usart.c +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_usart.c @@ -84,8 +84,7 @@ void usart_reset(usart_type* usart_x) crm_periph_reset(CRM_USART7_PERIPH_RESET, TRUE); crm_periph_reset(CRM_USART7_PERIPH_RESET, FALSE); } -#if defined (AT32F423Kx) || defined (AT32F423Tx) || defined (AT32F423Cx) || \ - defined (AT32F423Rx) || defined (AT32F423Vx) +#if defined (AT32F423Rx) || defined (AT32F423Vx) else if(usart_x == USART8) { crm_periph_reset(CRM_USART8_PERIPH_RESET, TRUE); @@ -105,6 +104,9 @@ void usart_reset(usart_type* usart_x) * - USART_DATA_7BITS * - USART_DATA_8BITS * - USART_DATA_9BITS. + * note: + * - when parity check is disabled, the data bit width is the actual data bit number. + * - when parity check is enabled, the data bit width is the actual data bit number minus 1, and the MSB bit is replaced with the parity bit. * @param stop_bit: stop bits transmitted * this parameter can be one of the following values: * - USART_STOP_1_BIT @@ -139,6 +141,10 @@ void usart_init(usart_type* usart_x, uint32_t baud_rate, usart_data_bit_num_type else { apb_clock = HICK_VALUE; + if(CRM->misc1_bit.hickdiv == CRM_HICK48_NODIV) + { + apb_clock = apb_clock * 6; + } } } else if(usart_x == USART2) @@ -159,6 +165,10 @@ void usart_init(usart_type* usart_x, uint32_t baud_rate, usart_data_bit_num_type else { apb_clock = HICK_VALUE; + if(CRM->misc1_bit.hickdiv == CRM_HICK48_NODIV) + { + apb_clock = apb_clock * 6; + } } } else if(usart_x == USART3) @@ -179,6 +189,10 @@ void usart_init(usart_type* usart_x, uint32_t baud_rate, usart_data_bit_num_type else { apb_clock = HICK_VALUE; + if(CRM->misc1_bit.hickdiv == CRM_HICK48_NODIV) + { + apb_clock = apb_clock * 6; + } } } else if(usart_x == USART6) @@ -292,10 +306,9 @@ void usart_receiver_enable(usart_type* usart_x, confirm_state new_state) /** * @brief usart clock config. - * @note clock config are not available for USART4, USART5, USART7 and USART8. * @param usart_x: select the usart or the uart peripheral. * this parameter can be one of the following values: - * USART1, USART2, USART3 or USART6. + * USART1, USART2, USART3, USART4 ,USART5, USART6, USART7 or USART8. * @param clk_pol: polarity of the clock output on the ck pin. * this parameter can be one of the following values: * - USART_CLOCK_POLARITY_LOW @@ -319,10 +332,9 @@ void usart_clock_config(usart_type* usart_x, usart_clock_polarity_type clk_pol, /** * @brief usart enable the ck pin. - * @note clock enable are not available for USART4, USART5, USART7 and USART8. * @param usart_x: select the usart or the uart peripheral. * this parameter can be one of the following values: - * USART1, USART2, USART3 or USART6. + * USART1, USART2, USART3, USART4 ,USART5, USART6, USART7 or USART8. * @param new_state: TRUE or FALSE * @retval none */ @@ -507,10 +519,9 @@ void usart_break_send(usart_type* usart_x) /** * @brief config the specified usart smartcard guard time. - * @note The guard time bits are not available for USART4, USART5, USART7 or USART8. * @param usart_x: select the usart or the uart peripheral. * this parameter can be one of the following values: - * USART1, USART2, USART3 or USART6. + * USART1, USART2, USART3, USART4, USART5, USART6, USART7 or USART8. * @param guard_time_val: specifies the guard time (0x00~0xFF). * @retval none */ @@ -521,10 +532,9 @@ void usart_smartcard_guard_time_set(usart_type* usart_x, uint8_t guard_time_val) /** * @brief config the irda/smartcard division. - * @note the division are not available for USART4, USART5, USART7 or USART8. * @param usart_x: select the usart or the uart peripheral. * this parameter can be one of the following values: - * USART1, USART2, USART3 or USART6. + * USART1, USART2, USART3, USART4, USART5, USART6, USART7 or USART8. * @param div_val: specifies the division. * @retval none */ @@ -535,10 +545,9 @@ void usart_irda_smartcard_division_set(usart_type* usart_x, uint8_t div_val) /** * @brief enable or disable the usart smart card mode. - * @note the smart card mode are not available for USART4, USART5, USART7 or USART8. * @param usart_x: select the usart or the uart peripheral. * this parameter can be one of the following values: - * USART1, USART2, USART3 or USART6. + * USART1, USART2, USART3, USART4, USART5, USART6, USART7 or USART8. * @param new_state: new state of the smart card mode. * this parameter can be: TRUE or FALSE. * @retval none @@ -550,10 +559,9 @@ void usart_smartcard_mode_enable(usart_type* usart_x, confirm_state new_state) /** * @brief enable or disable nack transmission in smartcard mode. - * @note the smart card nack are not available for USART4, USART5, USART7 or USART8. * @param usart_x: select the usart or the uart peripheral. * this parameter can be one of the following values: - * USART1, USART2, USART3 or USART6. + * USART1, USART2, USART3, USART4, USART5, USART6, USART7 or USART8. * @param new_state: new state of the nack transmission. * this parameter can be: TRUE or FALSE. * @retval none @@ -609,7 +617,7 @@ void usart_irda_low_power_enable(usart_type* usart_x, confirm_state new_state) * @brief configure the usart's hardware flow control. * @param usart_x: select the usart or the uart peripheral. * this parameter can be one of the following values: - * USART1, USART2, USART3 + * USART1, USART2, USART3, USART4, USART5, USART6, USART7 or USART8. * @param flow_state: specifies the hardware flow control. * this parameter can be one of the following values: * - USART_HARDWARE_FLOW_NONE @@ -679,6 +687,91 @@ flag_status usart_flag_get(usart_type* usart_x, uint32_t flag) } } +/** + * @brief check whether the specified usart interrupt flag is set or not. + * @param usart_x: select the usart or the uart peripheral. + * this parameter can be one of the following values: + * USART1, USART2, USART3, USART4, USART5, USART6, USART7 or USART8. + * @param flag: specifies the flag to check. + * this parameter can be one of the following values: + * - USART_RTODF_FLAG: receiver time out detection flag + * - USART_CMDF_FLAG: character match detection flag + * - USART_LPWUF_FLAG: low power wake up flag + * - USART_CTSCF_FLAG: cts change flag + * - USART_BFF_FLAG: break frame flag + * - USART_TDBE_FLAG: transmit data buffer empty flag + * - USART_TDC_FLAG: transmit data complete flag + * - USART_RDBF_FLAG: receive data buffer full flag + * - USART_IDLEF_FLAG: idle flag + * - USART_ROERR_FLAG: receiver overflow error flag + * - USART_NERR_FLAG: noise error flag + * - USART_FERR_FLAG: framing error flag + * - USART_PERR_FLAG: parity error flag + * @retval the new state of usart_flag (SET or RESET). + */ +flag_status usart_interrupt_flag_get(usart_type* usart_x, uint32_t flag) +{ + flag_status int_status = RESET; + + switch(flag) + { + case USART_CTSCF_FLAG: + int_status = (flag_status)usart_x->ctrl3_bit.ctscfien; + break; + case USART_BFF_FLAG: + int_status = (flag_status)usart_x->ctrl2_bit.bfien; + break; + case USART_TDBE_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.tdbeien; + break; + case USART_TDC_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.tdcien; + break; + case USART_RDBF_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.rdbfien; + break; + case USART_ROERR_FLAG: + int_status = (flag_status)(usart_x->ctrl1_bit.rdbfien || usart_x->ctrl3_bit.errien); + break; + case USART_IDLEF_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.idleien; + break; + case USART_NERR_FLAG: + case USART_FERR_FLAG: + int_status = (flag_status)usart_x->ctrl3_bit.errien; + break; + case USART_PERR_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.perrien; + break; + case USART_RTODF_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.retodie; + break; + case USART_CMDF_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.cmdie; + break; + case USART_LPWUF_FLAG: + int_status = (flag_status)usart_x->ctrl3_bit.lpwufie; + break; + default: + int_status = RESET; + break; + } + + if(int_status != SET) + { + return RESET; + } + + if(usart_x->sts & flag) + { + return SET; + } + else + { + return RESET; + } +} + /** * @brief clear the usart's pending flags. * @param usart_x: select the usart or the uart peripheral. @@ -737,7 +830,7 @@ void usart_flag_clear(usart_type* usart_x, uint32_t flag) * @brief configure the usart's rs485 transmit delay time. * @param usart_x: select the usart or the uart peripheral. * this parameter can be one of the following values: - * USART1, USART2, USART3 + * USART1, USART2, USART3, USART4, USART5, USART6, USART7 or USART8. * @param start_delay_time: transmit start delay time. * @param complete_delay_time: transmit complete delay time. * @retval none diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_wwdt.c b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_wwdt.c index 651134c6ee..86774b5658 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_wwdt.c +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_wwdt.c @@ -104,6 +104,16 @@ flag_status wwdt_flag_get(void) return (flag_status)WWDT->sts_bit.rldf; } +/** + * @brief wwdt reload counter interrupt flag get + * @param none + * @retval state of reload counter interrupt flag + */ +flag_status wwdt_interrupt_flag_get(void) +{ + return (flag_status)(WWDT->sts_bit.rldf && WWDT->cfg_bit.rldien); +} + /** * @brief wwdt counter value set * @param wwdt_cnt (0x40~0x7f) diff --git a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_xmc.c b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_xmc.c index 2cf073e0cd..5d8626dfa5 100644 --- a/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_xmc.c +++ b/bsp/at32/libraries/AT32F423_Firmware_Library/drivers/src/at32f423_xmc.c @@ -222,7 +222,7 @@ void xmc_nor_sram_enable(xmc_nor_sram_subbank_type xmc_subbank, confirm_state ne * @param r2r_timing :read timing * @retval none */ -void xmc_ext_timing_config(xmc_nor_sram_subbank_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing) +void xmc_ext_timing_config(volatile xmc_nor_sram_subbank_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing) { XMC_BANK1->ext_bit[xmc_sub_bank].buslatr2r = r2r_timing<<8; XMC_BANK1->ext_bit[xmc_sub_bank].buslatw2w = w2w_timing; diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_acc.h b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_acc.h index ada93a9153..321ba563d2 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_acc.h +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_acc.h @@ -179,6 +179,7 @@ uint16_t acc_read_c1(void); uint16_t acc_read_c2(void); uint16_t acc_read_c3(void); flag_status acc_flag_get(uint16_t acc_flag); +flag_status acc_interrupt_flag_get(uint16_t acc_flag); void acc_flag_clear(uint16_t acc_flag); /** diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_adc.h b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_adc.h index fbca4102dc..e983e51b22 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_adc.h +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_adc.h @@ -630,6 +630,7 @@ flag_status adc_preempt_software_trigger_status_get(adc_type *adc_x); uint16_t adc_ordinary_conversion_data_get(adc_type *adc_x); uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel); flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag); +flag_status adc_interrupt_flag_get(adc_type *adc_x, uint8_t adc_flag); void adc_flag_clear(adc_type *adc_x, uint32_t adc_flag); void adc_ordinary_oversample_enable(adc_type *adc_x, confirm_state new_state); void adc_preempt_oversample_enable(adc_type *adc_x, confirm_state new_state); diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_can.h b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_can.h index 47a2c17017..0d35df2bb3 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_can.h +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_can.h @@ -961,6 +961,7 @@ can_error_record_type can_error_type_record_get(can_type* can_x); uint8_t can_receive_error_counter_get(can_type* can_x); uint8_t can_transmit_error_counter_get(can_type* can_x); void can_interrupt_enable(can_type* can_x, uint32_t can_int, confirm_state new_state); +flag_status can_interrupt_flag_get(can_type* can_x, uint32_t can_flag); flag_status can_flag_get(can_type* can_x, uint32_t can_flag); void can_flag_clear(can_type* can_x, uint32_t can_flag); diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_crc.h b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_crc.h index 9bcb925e14..f792ed3e70 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_crc.h +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_crc.h @@ -66,6 +66,17 @@ typedef enum CRC_REVERSE_OUTPUT_DATA = 0x01 /*!< output data reverse by word */ } crc_reverse_output_type; +/** + * @brief crc polynomial size + */ +typedef enum +{ + CRC_POLY_SIZE_32B = 0x00, /*!< polynomial size 32 bits */ + CRC_POLY_SIZE_16B = 0x01, /*!< polynomial size 16 bits */ + CRC_POLY_SIZE_8B = 0x02, /*!< polynomial size 8 bits */ + CRC_POLY_SIZE_7B = 0x03 /*!< polynomial size 7 bits */ +} crc_poly_size_type; + /** * @brief type define crc register all */ @@ -105,7 +116,8 @@ typedef struct struct { __IO uint32_t rst : 1 ; /* [0] */ - __IO uint32_t reserved1 : 4 ; /* [4:1] */ + __IO uint32_t reserved1 : 2 ; /* [2:1] */ + __IO uint32_t poly_size : 2 ; /* [4:3] */ __IO uint32_t revid : 2 ; /* [6:5] */ __IO uint32_t revod : 1 ; /* [7] */ __IO uint32_t reserved2 : 24 ;/* [31:8] */ @@ -129,6 +141,18 @@ typedef struct } idt_bit; }; + /** + * @brief crc polynomial register, offset:0x14 + */ + union + { + __IO uint32_t poly; + struct + { + __IO uint32_t poly : 32; /* [31:0] */ + } poly_bit; + }; + } crc_type; /** @@ -150,6 +174,10 @@ uint8_t crc_common_data_get(void); void crc_init_data_set(uint32_t value); void crc_reverse_input_data_set(crc_reverse_input_type value); void crc_reverse_output_data_set(crc_reverse_output_type value); +void crc_poly_value_set(uint32_t value); +uint32_t crc_poly_value_get(void); +void crc_poly_size_set(crc_poly_size_type size); +crc_poly_size_type crc_poly_size_get(void); /** * @} diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_crm.h b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_crm.h index b5fc424abb..ff85abd775 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_crm.h +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_crm.h @@ -133,7 +133,7 @@ typedef enum CRM_I2C2_PERIPH_CLOCK = MAKE_VALUE(0x1C, 22), /*!< i2c2 periph clock */ CRM_CAN1_PERIPH_CLOCK = MAKE_VALUE(0x1C, 25), /*!< can1 periph clock */ CRM_ACC_PERIPH_CLOCK = MAKE_VALUE(0x1C, 27), /*!< acc periph clock */ - CRM_PWC_PERIPH_CLOCK = MAKE_VALUE(0x1C, 28), /*!< pwc periph clock */ + CRM_PWC_PERIPH_CLOCK = MAKE_VALUE(0x1C, 28) /*!< pwc periph clock */ } crm_periph_clock_type; @@ -176,7 +176,7 @@ typedef enum CRM_I2C2_PERIPH_RESET = MAKE_VALUE(0x10, 22), /*!< i2c2 periph reset */ CRM_CAN1_PERIPH_RESET = MAKE_VALUE(0x10, 25), /*!< can1 periph reset */ CRM_ACC_PERIPH_RESET = MAKE_VALUE(0x10, 27), /*!< acc periph reset */ - CRM_PWC_PERIPH_RESET = MAKE_VALUE(0x10, 28), /*!< pwc periph reset */ + CRM_PWC_PERIPH_RESET = MAKE_VALUE(0x10, 28) /*!< pwc periph reset */ } crm_periph_reset_type; @@ -270,7 +270,7 @@ typedef enum CRM_PLL_FREF_8M = 2, /*!< pll refrence clock between 7.8125 mhz and 8.33 mhz */ CRM_PLL_FREF_12M = 3, /*!< pll refrence clock between 8.33 mhz and 12.5 mhz */ CRM_PLL_FREF_16M = 4, /*!< pll refrence clock between 15.625 mhz and 20.83 mhz */ - CRM_PLL_FREF_25M = 5, /*!< pll refrence clock between 20.83 mhz and 31.255 mhz */ + CRM_PLL_FREF_25M = 5 /*!< pll refrence clock between 20.83 mhz and 31.255 mhz */ } crm_pll_fref_type; /** @@ -862,6 +862,7 @@ void crm_reset(void); void crm_lext_bypass(confirm_state new_state); void crm_hext_bypass(confirm_state new_state); flag_status crm_flag_get(uint32_t flag); +flag_status crm_interrupt_flag_get(uint32_t flag); error_status crm_hext_stable_wait(void); void crm_hick_clock_trimming_set(uint8_t trim_value); void crm_hick_clock_calibration_set(uint8_t cali_value); diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_debug.h b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_debug.h index 07fa1714da..2f8531756b 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_debug.h +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_debug.h @@ -128,6 +128,26 @@ typedef struct } ctrl_bit; }; + /** + * @brief debug reserved1 register, offset:0x08~0x1C + */ + __IO uint32_t reserved1[6]; + + /** + * @brief debug ser id register, offset:0x20 + */ + union + { + __IO uint32_t ser_id; + struct + { + __IO uint32_t rev_id : 3;/* [2:0] */ + __IO uint32_t reserved1 : 5;/* [7:3] */ + __IO uint32_t ser_id : 8;/* [15:8] */ + __IO uint32_t reserved2 : 16;/* [31:16] */ + } ser_id_bit; + }; + } debug_type; /** diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_dma.h b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_dma.h index 192ca907d3..b5a0328793 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_dma.h +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_dma.h @@ -457,6 +457,7 @@ void dma_interrupt_enable(dma_channel_type* dmax_channely, uint32_t dma_int, con void dma_channel_enable(dma_channel_type* dmax_channely, confirm_state new_state); void dma_flexible_config(dma_type* dma_x, uint8_t flex_channelx, dma_flexible_request_type flexible_request); flag_status dma_flag_get(uint32_t dmax_flag); +flag_status dma_interrupt_flag_get(uint32_t dmax_flag); void dma_flag_clear(uint32_t dmax_flag); void dma_default_para_init(dma_init_type* dma_init_struct); void dma_init(dma_channel_type* dmax_channely, dma_init_type* dma_init_struct); diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_ertc.h b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_ertc.h index 619e0f59f3..786782e016 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_ertc.h +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_ertc.h @@ -84,10 +84,6 @@ extern "C" { #define ERTC_ALARM_MASK_DATE_WEEK ((uint32_t)0x80000000) /*!< ertc alarm don't match date or week */ #define ERTC_ALARM_MASK_ALL ((uint32_t)0x80808080) /*!< ertc alarm don't match all */ -/** - * @} - */ - /** * @brief compatible with older versions */ @@ -923,6 +919,7 @@ void ertc_tamper_enable(ertc_tamper_select_type tamper_x, confirm_state new_stat void ertc_interrupt_enable(uint32_t source, confirm_state new_state); flag_status ertc_interrupt_get(uint32_t source); flag_status ertc_flag_get(uint32_t flag); +flag_status ertc_interrupt_flag_get(uint32_t flag); void ertc_flag_clear(uint32_t flag); void ertc_bpr_data_write(ertc_dt_type dt, uint32_t data); uint32_t ertc_bpr_data_read(ertc_dt_type dt); diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_exint.h b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_exint.h index fe4379d21f..347bca09fb 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_exint.h +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_exint.h @@ -208,6 +208,7 @@ void exint_default_para_init(exint_init_type *exint_struct); void exint_init(exint_init_type *exint_struct); void exint_flag_clear(uint32_t exint_line); flag_status exint_flag_get(uint32_t exint_line); +flag_status exint_interrupt_flag_get(uint32_t exint_line); void exint_software_interrupt_event_generate(uint32_t exint_line); void exint_interrupt_enable(uint32_t exint_line, confirm_state new_state); void exint_event_enable(uint32_t exint_line, confirm_state new_state); diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_flash.h b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_flash.h index 47b046e41d..c2670deab9 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_flash.h +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_flash.h @@ -190,13 +190,13 @@ typedef struct struct { __IO uint32_t wtcyc : 3; /* [2:0] */ - __IO uint32_t hfcyc_en : 1; /* [3] */ + __IO uint32_t reserved1 : 1; /* [3] */ __IO uint32_t pft_en : 1; /* [4] */ __IO uint32_t pft_enf : 1; /* [5] */ __IO uint32_t pft_en2 : 1; /* [6] */ __IO uint32_t pft_enf2 : 1; /* [7] */ __IO uint32_t pft_lat_dis : 1; /* [8] */ - __IO uint32_t reserved1 : 23;/* [31:9] */ + __IO uint32_t reserved2 : 23;/* [31:9] */ } psr_bit; }; diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_i2c.h b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_i2c.h index 09f535c4eb..55166087fe 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_i2c.h +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_i2c.h @@ -155,12 +155,12 @@ typedef enum { I2C_ADDR2_NOMASK = 0x00, /*!< compare bit [7:1] */ I2C_ADDR2_MASK01 = 0x01, /*!< only compare bit [7:2] */ - I2C_ADDR2_MASK02 = 0x02, /*!< only compare bit [7:2] */ - I2C_ADDR2_MASK03 = 0x03, /*!< only compare bit [7:3] */ - I2C_ADDR2_MASK04 = 0x04, /*!< only compare bit [7:4] */ - I2C_ADDR2_MASK05 = 0x05, /*!< only compare bit [7:5] */ - I2C_ADDR2_MASK06 = 0x06, /*!< only compare bit [7:6] */ - I2C_ADDR2_MASK07 = 0x07 /*!< only compare bit [7] */ + I2C_ADDR2_MASK02 = 0x02, /*!< only compare bit [7:3] */ + I2C_ADDR2_MASK03 = 0x03, /*!< only compare bit [7:4] */ + I2C_ADDR2_MASK04 = 0x04, /*!< only compare bit [7:5] */ + I2C_ADDR2_MASK05 = 0x05, /*!< only compare bit [7:6] */ + I2C_ADDR2_MASK06 = 0x06, /*!< only compare bit [7] */ + I2C_ADDR2_MASK07 = 0x07 /*!< response all addresses other than those reserved for i2c */ } i2c_addr2_mask_type; /** @@ -455,6 +455,7 @@ void i2c_stop_generate(i2c_type *i2c_x); void i2c_data_send(i2c_type *i2c_x, uint8_t data); uint8_t i2c_data_receive(i2c_type *i2c_x); flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag); +flag_status i2c_interrupt_flag_get(i2c_type *i2c_x, uint32_t flag); void i2c_flag_clear(i2c_type *i2c_x, uint32_t flag); /** diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_pwc.h b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_pwc.h index daef96b898..907a0acc51 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_pwc.h +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_pwc.h @@ -58,12 +58,12 @@ extern "C" { /** * @brief pwc wakeup pin num definition */ -#define PWC_WAKEUP_PIN_1 ((uint32_t)0x00000100) /*!< standby wake-up pin1 */ -#define PWC_WAKEUP_PIN_2 ((uint32_t)0x00000200) /*!< standby wake-up pin2 */ -#define PWC_WAKEUP_PIN_4 ((uint32_t)0x00000800) /*!< standby wake-up pin4 */ -#define PWC_WAKEUP_PIN_5 ((uint32_t)0x00001000) /*!< standby wake-up pin5 */ -#define PWC_WAKEUP_PIN_6 ((uint32_t)0x00002000) /*!< standby wake-up pin6 */ -#define PWC_WAKEUP_PIN_7 ((uint32_t)0x00004000) /*!< standby wake-up pin7 */ +#define PWC_WAKEUP_PIN_1 ((uint32_t)0x00000100) /*!< standby wake-up pin1(pa0) */ +#define PWC_WAKEUP_PIN_2 ((uint32_t)0x00000200) /*!< standby wake-up pin2(pc13) */ +#define PWC_WAKEUP_PIN_4 ((uint32_t)0x00000800) /*!< standby wake-up pin4(pa2) */ +#define PWC_WAKEUP_PIN_5 ((uint32_t)0x00001000) /*!< standby wake-up pin5(pc5) */ +#define PWC_WAKEUP_PIN_6 ((uint32_t)0x00002000) /*!< standby wake-up pin6(pb5) */ +#define PWC_WAKEUP_PIN_7 ((uint32_t)0x00004000) /*!< standby wake-up pin7(pb15) */ /** @defgroup PWC_exported_types * @{ diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_scfg.h b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_scfg.h index e1afb481f8..fc124fce2d 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_scfg.h +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_scfg.h @@ -65,9 +65,7 @@ typedef enum */ typedef enum { - SCFG_IR_SOURCE_TMR16 = 0x00, /* infrared signal source select tmr16 */ - SCFG_IR_SOURCE_USART1 = 0x01, /* infrared signal source select usart1 */ - SCFG_IR_SOURCE_USART2 = 0x02 /* infrared signal source select usart2 */ + SCFG_IR_SOURCE_TMR16 = 0x00 /* infrared signal source select tmr16 */ } scfg_ir_source_type; /** @@ -268,7 +266,7 @@ typedef struct void scfg_reset(void); void scfg_infrared_config(scfg_ir_source_type source, scfg_ir_polarity_type polarity); -uint8_t scfg_mem_map_get(void); +scfg_mem_map_type scfg_mem_map_get(void); void scfg_pa11pa12_pin_remap(scfg_pa11pa12_remap_type pin_remap); void scfg_exint_line_config(scfg_port_source_type port_source, scfg_pins_source_type pin_source); void scfg_pins_ultra_driven_enable(scfg_ultra_driven_pins_type value, confirm_state new_state); diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_spi.h b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_spi.h index a10911ef6e..6249f428e1 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_spi.h +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_spi.h @@ -482,6 +482,7 @@ void spi_i2s_dma_receiver_enable(spi_type* spi_x, confirm_state new_state); void spi_i2s_data_transmit(spi_type* spi_x, uint16_t tx_data); uint16_t spi_i2s_data_receive(spi_type* spi_x); flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag); +flag_status spi_i2s_interrupt_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag); void spi_i2s_flag_clear(spi_type* spi_x, uint32_t spi_i2s_flag); /** diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_tmr.h b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_tmr.h index ec919c283a..68dd04f89d 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_tmr.h +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_tmr.h @@ -236,7 +236,7 @@ typedef enum { TMR_CC_CHANNEL_MAPPED_DIRECT = 0x01, /*!< channel is configured as input, mapped direct */ TMR_CC_CHANNEL_MAPPED_INDIRECT = 0x02, /*!< channel is configured as input, mapped indirect */ - TMR_CC_CHANNEL_MAPPED_STI = 0x03 /*!< channel is configured as input, mapped trc */ + TMR_CC_CHANNEL_MAPPED_STI = 0x03 /*!< channel is configured as input, mapped sti */ } tmr_input_direction_mapped_type; /** @@ -801,7 +801,8 @@ typedef struct __IO uint32_t brkv : 1; /* [13] */ __IO uint32_t aoen : 1; /* [14] */ __IO uint32_t oen : 1; /* [15] */ - __IO uint32_t reserved1 : 16; /* [31:16] */ + __IO uint32_t bkf : 4; /* [19:16] */ + __IO uint32_t reserved1 : 12;/* [31:20] */ } brk_bit; }; /** @@ -917,6 +918,7 @@ void tmr_trigger_input_select(tmr_type *tmr_x, sub_tmr_input_sel_type trigger_se void tmr_sub_sync_mode_set(tmr_type *tmr_x, confirm_state new_state); void tmr_dma_request_enable(tmr_type *tmr_x, tmr_dma_request_type dma_request, confirm_state new_state); void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state new_state); +flag_status tmr_interrupt_flag_get(tmr_type *tmr_x, uint32_t tmr_flag); flag_status tmr_flag_get(tmr_type *tmr_x, uint32_t tmr_flag); void tmr_flag_clear(tmr_type *tmr_x, uint32_t tmr_flag); void tmr_event_sw_trigger(tmr_type *tmr_x, tmr_event_trigger_type tmr_event); @@ -938,6 +940,7 @@ void tmr_force_output_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, void tmr_dma_control_config(tmr_type *tmr_x, tmr_dma_transfer_length_type dma_length, \ tmr_dma_address_type dma_base_address); void tmr_brkdt_config(tmr_type *tmr_x, tmr_brkdt_config_type *brkdt_struct); +void tmr_brk_filter_value_set(tmr_type *tmr_x, uint8_t filter_value); void tmr_iremap_config(tmr_type *tmr_x, tmr_input_remap_type input_remap); /** diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_usart.h b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_usart.h index f0457e9c1c..dc0bac389d 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_usart.h +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_usart.h @@ -380,6 +380,7 @@ void usart_irda_mode_enable(usart_type* usart_x, confirm_state new_state); void usart_irda_low_power_enable(usart_type* usart_x, confirm_state new_state); void usart_hardware_flow_control_set(usart_type* usart_x,usart_hardware_flow_control_type flow_state); flag_status usart_flag_get(usart_type* usart_x, uint32_t flag); +flag_status usart_interrupt_flag_get(usart_type* usart_x, uint32_t flag); void usart_flag_clear(usart_type* usart_x, uint32_t flag); void usart_rs485_delay_time_config(usart_type* usart_x, uint8_t start_delay_time, uint8_t complete_delay_time); void usart_transmit_receive_pin_swap(usart_type* usart_x, confirm_state new_state); diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_usb.h b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_usb.h index ff37f876a8..b6e5d2c9eb 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_usb.h +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_usb.h @@ -705,6 +705,7 @@ typedef struct __IO uint32_t nptxfspcavail : 16; /* [15:0] */ __IO uint32_t nptxqspcavail : 8; /* [23:16] */ __IO uint32_t nptxqtop : 7; /* [30:24] */ + __IO uint32_t reserved1 : 1; /* [31] */ } gnptxsts_bit; }; diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_wwdt.h b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_wwdt.h index 8c6429233e..3b8364e53d 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_wwdt.h +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/inc/at32f425_wwdt.h @@ -134,6 +134,7 @@ void wwdt_flag_clear(void); void wwdt_enable(uint8_t wwdt_cnt); void wwdt_interrupt_enable(void); flag_status wwdt_flag_get(void); +flag_status wwdt_interrupt_flag_get(void); void wwdt_counter_set(uint8_t wwdt_cnt); void wwdt_window_counter_set(uint8_t window_cnt); diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_acc.c b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_acc.c index b583b88f26..afdd42b1bd 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_acc.c +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_acc.c @@ -188,6 +188,22 @@ flag_status acc_flag_get(uint16_t acc_flag) return (flag_status)(ACC->sts_bit.rslost); } +/** + * @brief check whether the specified acc interrupt flag is set or not. + * @param acc_flag: specifies the flag to check. + * this parameter can be one of the following values: + * - ACC_RSLOST_FLAG + * - ACC_CALRDY_FLAG + * @retval flag_status (SET or RESET) + */ +flag_status acc_interrupt_flag_get(uint16_t acc_flag) +{ + if(acc_flag == ACC_CALRDY_FLAG) + return (flag_status)(ACC->sts_bit.calrdy && ACC->ctrl1_bit.calrdyien); + else + return (flag_status)(ACC->sts_bit.rslost && ACC->ctrl1_bit.eien); +} + /** * @brief clear the specified acc flag is set or not. * @param acc_flag: specifies the flag to check. diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_adc.c b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_adc.c index 9baceedbc3..c9306dadab 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_adc.c +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_adc.c @@ -82,7 +82,7 @@ void adc_enable(adc_type *adc_x, confirm_state new_state) * - ADC_LEFT_ALIGNMENT * @param ordinary_channel_length: configure the adc ordinary channel sequence length. * this parameter can be: - * - (0x1~0xf) + * - (0x1~0x10) * @retval none */ void adc_base_default_para_init(adc_base_config_type *adc_base_struct) @@ -108,7 +108,7 @@ void adc_base_default_para_init(adc_base_config_type *adc_base_struct) * - ADC_LEFT_ALIGNMENT * @param ordinary_channel_length: configure the adc ordinary channel sequence length. * this parameter can be: - * - (0x1~0xf) + * - (0x1~0x10) * @retval none */ void adc_base_config(adc_type *adc_x, adc_base_config_type *adc_base_struct) @@ -312,117 +312,42 @@ void adc_voltage_monitor_single_channel_select(adc_type *adc_x, adc_channel_sele */ void adc_ordinary_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime) { - switch(adc_channel) + uint32_t tmp_reg; + if(adc_channel < ADC_CHANNEL_10) { - case ADC_CHANNEL_0: - adc_x->spt2_bit.cspt0 = adc_sampletime; - break; - case ADC_CHANNEL_1: - adc_x->spt2_bit.cspt1 = adc_sampletime; - break; - case ADC_CHANNEL_2: - adc_x->spt2_bit.cspt2 = adc_sampletime; - break; - case ADC_CHANNEL_3: - adc_x->spt2_bit.cspt3 = adc_sampletime; - break; - case ADC_CHANNEL_4: - adc_x->spt2_bit.cspt4 = adc_sampletime; - break; - case ADC_CHANNEL_5: - adc_x->spt2_bit.cspt5 = adc_sampletime; - break; - case ADC_CHANNEL_6: - adc_x->spt2_bit.cspt6 = adc_sampletime; - break; - case ADC_CHANNEL_7: - adc_x->spt2_bit.cspt7 = adc_sampletime; - break; - case ADC_CHANNEL_8: - adc_x->spt2_bit.cspt8 = adc_sampletime; - break; - case ADC_CHANNEL_9: - adc_x->spt2_bit.cspt9 = adc_sampletime; - break; - case ADC_CHANNEL_10: - adc_x->spt1_bit.cspt10 = adc_sampletime; - break; - case ADC_CHANNEL_11: - adc_x->spt1_bit.cspt11 = adc_sampletime; - break; - case ADC_CHANNEL_12: - adc_x->spt1_bit.cspt12 = adc_sampletime; - break; - case ADC_CHANNEL_13: - adc_x->spt1_bit.cspt13 = adc_sampletime; - break; - case ADC_CHANNEL_14: - adc_x->spt1_bit.cspt14 = adc_sampletime; - break; - case ADC_CHANNEL_15: - adc_x->spt1_bit.cspt15 = adc_sampletime; - break; - case ADC_CHANNEL_16: - adc_x->spt1_bit.cspt16 = adc_sampletime; - break; - case ADC_CHANNEL_17: - adc_x->spt1_bit.cspt17 = adc_sampletime; - break; - default: - break; + tmp_reg = adc_x->spt2; + tmp_reg &= ~(0x07 << 3 * adc_channel); + tmp_reg |= adc_sampletime << 3 * adc_channel; + adc_x->spt2 = tmp_reg; } - switch(adc_sequence) + else { - case 1: - adc_x->osq3_bit.osn1 = adc_channel; - break; - case 2: - adc_x->osq3_bit.osn2 = adc_channel; - break; - case 3: - adc_x->osq3_bit.osn3 = adc_channel; - break; - case 4: - adc_x->osq3_bit.osn4 = adc_channel; - break; - case 5: - adc_x->osq3_bit.osn5 = adc_channel; - break; - case 6: - adc_x->osq3_bit.osn6 = adc_channel; - break; - case 7: - adc_x->osq2_bit.osn7 = adc_channel; - break; - case 8: - adc_x->osq2_bit.osn8 = adc_channel; - break; - case 9: - adc_x->osq2_bit.osn9 = adc_channel; - break; - case 10: - adc_x->osq2_bit.osn10 = adc_channel; - break; - case 11: - adc_x->osq2_bit.osn11 = adc_channel; - break; - case 12: - adc_x->osq2_bit.osn12 = adc_channel; - break; - case 13: - adc_x->osq1_bit.osn13 = adc_channel; - break; - case 14: - adc_x->osq1_bit.osn14 = adc_channel; - break; - case 15: - adc_x->osq1_bit.osn15 = adc_channel; - break; - case 16: - adc_x->osq1_bit.osn16 = adc_channel; - break; - default: - break; + tmp_reg = adc_x->spt1; + tmp_reg &= ~(0x07 << 3 * (adc_channel - ADC_CHANNEL_10)); + tmp_reg |= adc_sampletime << 3 * (adc_channel - ADC_CHANNEL_10); + adc_x->spt1 = tmp_reg; + } + + if(adc_sequence >= 13) + { + tmp_reg = adc_x->osq1; + tmp_reg &= ~(0x01F << 5 * (adc_sequence - 13)); + tmp_reg |= adc_channel << 5 * (adc_sequence - 13); + adc_x->osq1 = tmp_reg; + } + else if(adc_sequence >= 7) + { + tmp_reg = adc_x->osq2; + tmp_reg &= ~(0x01F << 5 * (adc_sequence - 7)); + tmp_reg |= adc_channel << 5 * (adc_sequence - 7); + adc_x->osq2 = tmp_reg; + } + else + { + tmp_reg = adc_x->osq3; + tmp_reg &= ~(0x01F << 5 * (adc_sequence - 1)); + tmp_reg |= adc_channel << 5 * (adc_sequence - 1); + adc_x->osq3 = tmp_reg; } } @@ -470,66 +395,23 @@ void adc_preempt_channel_length_set(adc_type *adc_x, uint8_t adc_channel_lenght) */ void adc_preempt_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime) { - uint16_t sequence_index=0; - switch(adc_channel) + uint32_t tmp_reg; + uint8_t sequence_index; + if(adc_channel < ADC_CHANNEL_10) { - case ADC_CHANNEL_0: - adc_x->spt2_bit.cspt0 = adc_sampletime; - break; - case ADC_CHANNEL_1: - adc_x->spt2_bit.cspt1 = adc_sampletime; - break; - case ADC_CHANNEL_2: - adc_x->spt2_bit.cspt2 = adc_sampletime; - break; - case ADC_CHANNEL_3: - adc_x->spt2_bit.cspt3 = adc_sampletime; - break; - case ADC_CHANNEL_4: - adc_x->spt2_bit.cspt4 = adc_sampletime; - break; - case ADC_CHANNEL_5: - adc_x->spt2_bit.cspt5 = adc_sampletime; - break; - case ADC_CHANNEL_6: - adc_x->spt2_bit.cspt6 = adc_sampletime; - break; - case ADC_CHANNEL_7: - adc_x->spt2_bit.cspt7 = adc_sampletime; - break; - case ADC_CHANNEL_8: - adc_x->spt2_bit.cspt8 = adc_sampletime; - break; - case ADC_CHANNEL_9: - adc_x->spt2_bit.cspt9 = adc_sampletime; - break; - case ADC_CHANNEL_10: - adc_x->spt1_bit.cspt10 = adc_sampletime; - break; - case ADC_CHANNEL_11: - adc_x->spt1_bit.cspt11 = adc_sampletime; - break; - case ADC_CHANNEL_12: - adc_x->spt1_bit.cspt12 = adc_sampletime; - break; - case ADC_CHANNEL_13: - adc_x->spt1_bit.cspt13 = adc_sampletime; - break; - case ADC_CHANNEL_14: - adc_x->spt1_bit.cspt14 = adc_sampletime; - break; - case ADC_CHANNEL_15: - adc_x->spt1_bit.cspt15 = adc_sampletime; - break; - case ADC_CHANNEL_16: - adc_x->spt1_bit.cspt16 = adc_sampletime; - break; - case ADC_CHANNEL_17: - adc_x->spt1_bit.cspt17 = adc_sampletime; - break; - default: - break; + tmp_reg = adc_x->spt2; + tmp_reg &= ~(0x07 << 3 * adc_channel); + tmp_reg |= adc_sampletime << 3 * adc_channel; + adc_x->spt2 = tmp_reg; } + else + { + tmp_reg = adc_x->spt1; + tmp_reg &= ~(0x07 << 3 * (adc_channel - ADC_CHANNEL_10)); + tmp_reg |= adc_sampletime << 3 * (adc_channel - ADC_CHANNEL_10); + adc_x->spt1 = tmp_reg; + } + sequence_index = adc_sequence + 3 - adc_x->psq_bit.pclen; switch(sequence_index) { @@ -803,10 +685,10 @@ uint16_t adc_ordinary_conversion_data_get(adc_type *adc_x) * ADC1. * @param adc_preempt_channel: select the preempt channel. * this parameter can be one of the following values: - * - ADC_PREEMPTED_CHANNEL_1 - * - ADC_PREEMPTED_CHANNEL_2 - * - ADC_PREEMPTED_CHANNEL_3 - * - ADC_PREEMPTED_CHANNEL_4 + * - ADC_PREEMPT_CHANNEL_1 + * - ADC_PREEMPT_CHANNEL_2 + * - ADC_PREEMPT_CHANNEL_3 + * - ADC_PREEMPT_CHANNEL_4 * @retval the conversion data for selection preempt channel. */ uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel) @@ -861,6 +743,47 @@ flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag) return status; } +/** + * @brief get interrupt flag of the specified adc peripheral. + * @param adc_x: select the adc peripheral. + * this parameter can be one of the following values: + * ADC1. + * @param adc_flag: select the adc flag. + * this parameter can be one of the following values: + * - ADC_VMOR_FLAG + * - ADC_CCE_FLAG + * - ADC_PCCE_FLAG + * @retval the new state of adc flag status(SET or RESET). + */ +flag_status adc_interrupt_flag_get(adc_type *adc_x, uint8_t adc_flag) +{ + flag_status status = RESET; + switch(adc_flag) + { + case ADC_VMOR_FLAG: + if(adc_x->sts_bit.vmor && adc_x->ctrl1_bit.vmorien) + { + status = SET; + } + break; + case ADC_CCE_FLAG: + if(adc_x->sts_bit.cce && adc_x->ctrl1_bit.cceien) + { + status = SET; + } + break; + case ADC_PCCE_FLAG: + if(adc_x->sts_bit.pcce && adc_x->ctrl1_bit.pcceien) + { + status = SET; + } + break; + default: + break; + } + return status; +} + /** * @brief clear flag of the specified adc peripheral. * @param adc_x: select the adc peripheral. diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_can.c b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_can.c index baa4e2b62a..bfcaf305d0 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_can.c +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_can.c @@ -923,6 +923,102 @@ void can_interrupt_enable(can_type* can_x, uint32_t can_int, confirm_state new_s } } +/** + * @brief get interrupt flag of the specified can peripheral. + * @param can_x: select the can peripheral. + * this parameter can be one of the following values: + * CAN1. + * @param can_flag: select the flag. + * this parameter can be one of the following flags: + * - CAN_EAF_FLAG + * - CAN_EPF_FLAG + * - CAN_BOF_FLAG + * - CAN_ETR_FLAG + * - CAN_EOIF_FLAG + * - CAN_TM0TCF_FLAG + * - CAN_TM1TCF_FLAG + * - CAN_TM2TCF_FLAG + * - CAN_RF0MN_FLAG + * - CAN_RF0FF_FLAG + * - CAN_RF0OF_FLAG + * - CAN_RF1MN_FLAG + * - CAN_RF1FF_FLAG + * - CAN_RF1OF_FLAG + * - CAN_QDZIF_FLAG + * - CAN_EDZC_FLAG + * - CAN_TMEF_FLAG + * note:the state of CAN_EDZC_FLAG need to check dzc and edzif bit + * note:the state of CAN_TMEF_FLAG need to check rqc0,rqc1 and rqc2 bit + * @retval status of can_flag, the returned value can be:SET or RESET. + */ +flag_status can_interrupt_flag_get(can_type* can_x, uint32_t can_flag) +{ + flag_status bit_status = RESET; + flag_status int_status = RESET; + + switch(can_flag) + { + case CAN_EAF_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.eaien); + break; + case CAN_EPF_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.epien); + break; + case CAN_BOF_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.boien); + break; + case CAN_ETR_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.etrien); + break; + case CAN_EOIF_FLAG: + int_status = (flag_status)can_x->inten_bit.eoien; + break; + case CAN_TM0TCF_FLAG: + case CAN_TM1TCF_FLAG: + case CAN_TM2TCF_FLAG: + int_status = (flag_status)can_x->inten_bit.tcien; + break; + case CAN_RF0MN_FLAG: + int_status = (flag_status)can_x->inten_bit.rf0mien; + break; + case CAN_RF0FF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf0fien; + break; + case CAN_RF0OF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf0oien; + break; + case CAN_RF1MN_FLAG: + int_status = (flag_status)can_x->inten_bit.rf1mien; + break; + case CAN_RF1FF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf1fien; + break; + case CAN_RF1OF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf1oien; + break; + case CAN_QDZIF_FLAG: + int_status = (flag_status)can_x->inten_bit.qdzien; + break; + case CAN_EDZC_FLAG: + int_status = (flag_status)can_x->inten_bit.edzien; + break; + case CAN_TMEF_FLAG: + int_status = (flag_status)can_x->inten_bit.tcien; + break; + default: + int_status = RESET; + break; + } + + if(int_status != SET) + { + return RESET; + } + bit_status = can_flag_get(can_x, can_flag); + + return bit_status; +} + /** * @brief get flag of the specified can peripheral. * @param can_x: select the can peripheral. diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_crc.c b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_crc.c index 9b702d4f34..7072f52a83 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_crc.c +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_crc.c @@ -147,6 +147,52 @@ void crc_reverse_output_data_set(crc_reverse_output_type value) CRC->ctrl_bit.revod = value; } +/** + * @brief config crc polynomial value + * @param value + * 32-bit new data of crc poly value + * @retval none. + */ +void crc_poly_value_set(uint32_t value) +{ + CRC->poly = value; +} + +/** + * @brief return crc polynomial value + * @param none + * @retval 32-bit value of the polynomial value. + */ +uint32_t crc_poly_value_get(void) +{ + return (CRC->poly); +} + +/** + * @brief config crc polynomial data size + * @param size + * this parameter can be one of the following values: + * - CRC_POLY_SIZE_32B + * - CRC_POLY_SIZE_16B + * - CRC_POLY_SIZE_8B + * - CRC_POLY_SIZE_7B + * @retval none. + */ +void crc_poly_size_set(crc_poly_size_type size) +{ + CRC->ctrl_bit.poly_size = size; +} + +/** + * @brief return crc polynomial data size + * @param none + * @retval polynomial data size. + */ +crc_poly_size_type crc_poly_size_get(void) +{ + return (crc_poly_size_type)(CRC->ctrl_bit.poly_size); +} + /** * @} */ diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_crm.c b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_crm.c index c278da1a18..104eea43d1 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_crm.c +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_crm.c @@ -134,6 +134,64 @@ flag_status crm_flag_get(uint32_t flag) return status; } +/** + * @brief get crm interrupt flag status + * @param flag + * this parameter can be one of the following values: + * - CRM_LICK_READY_INT_FLAG + * - CRM_LEXT_READY_INT_FLAG + * - CRM_HICK_READY_INT_FLAG + * - CRM_HEXT_READY_INT_FLAG + * - CRM_PLL_READY_INT_FLAG + * - CRM_CLOCK_FAILURE_INT_FLAG + * @retval flag_status (SET or RESET) + */ +flag_status crm_interrupt_flag_get(uint32_t flag) +{ + flag_status status = RESET; + switch(flag) + { + case CRM_LICK_READY_INT_FLAG: + if(CRM->clkint_bit.lickstblf && CRM->clkint_bit.lickstblien) + { + status = SET; + } + break; + case CRM_LEXT_READY_INT_FLAG: + if(CRM->clkint_bit.lextstblf && CRM->clkint_bit.lextstblien) + { + status = SET; + } + break; + case CRM_HICK_READY_INT_FLAG: + if(CRM->clkint_bit.hickstblf && CRM->clkint_bit.hickstblien) + { + status = SET; + } + break; + case CRM_HEXT_READY_INT_FLAG: + if(CRM->clkint_bit.hextstblf && CRM->clkint_bit.hextstblien) + { + status = SET; + } + break; + case CRM_PLL_READY_INT_FLAG: + if(CRM->clkint_bit.pllstblf && CRM->clkint_bit.pllstblien) + { + status = SET; + } + break; + case CRM_CLOCK_FAILURE_INT_FLAG: + if(CRM->clkint_bit.cfdf && CRM->ctrl_bit.cfden) + { + status = SET; + } + break; + } + + return status; +} + /** * @brief wait for hext stable * @param none diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_dma.c b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_dma.c index 5d63d5f69b..6345c012a1 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_dma.c +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_dma.c @@ -259,6 +259,38 @@ flag_status dma_flag_get(uint32_t dmax_flag) return status; } +/** + * @brief get dma interrupt flag + * @param dmax_flag + * this parameter can be one of the following values: + * - DMA1_FDT1_FLAG - DMA1_HDT1_FLAG - DMA1_DTERR1_FLAG + * - DMA1_FDT2_FLAG - DMA1_HDT2_FLAG - DMA1_DTERR2_FLAG + * - DMA1_FDT3_FLAG - DMA1_HDT3_FLAG - DMA1_DTERR3_FLAG + * - DMA1_FDT4_FLAG - DMA1_HDT4_FLAG - DMA1_DTERR4_FLAG + * - DMA1_FDT5_FLAG - DMA1_HDT5_FLAG - DMA1_DTERR5_FLAG + * - DMA1_FDT6_FLAG - DMA1_HDT6_FLAG - DMA1_DTERR6_FLAG + * - DMA1_FDT7_FLAG - DMA1_HDT7_FLAG - DMA1_DTERR7_FLAG + * @retval state of dma flag + */ +flag_status dma_interrupt_flag_get(uint32_t dmax_flag) +{ + flag_status status = RESET; + uint32_t temp = 0; + + temp = DMA1->sts; + + if ((temp & dmax_flag) != (uint16_t)RESET) + { + status = SET; + } + else + { + status = RESET; + } + + return status; +} + /** * @brief clear dma flag * @param dmax_flag diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_ertc.c b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_ertc.c index 96b533438a..176c41d763 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_ertc.c +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_ertc.c @@ -316,7 +316,7 @@ error_status ertc_date_set(uint8_t year, uint8_t month, uint8_t date, uint8_t we return ERROR; } - /* Set the ertc_DR register */ + /* set the ertc_date register */ ERTC->date = reg.date; /* exit init mode */ @@ -391,8 +391,6 @@ void ertc_calendar_get(ertc_time_type* time) ertc_reg_time_type reg_tm; ertc_reg_date_type reg_dt; - UNUSED(ERTC->sts); - reg_tm.time = ERTC->time; reg_dt.date = ERTC->date; @@ -1298,6 +1296,49 @@ flag_status ertc_flag_get(uint32_t flag) } } +/** + * @brief get interrupt flag status. + * @param flag: specifies the flag to check. + * this parameter can be one of the following values: + * - ERTC_ALAF_FLAG: alarm clock a flag. + * - ERTC_WATF_FLAG: wakeup timer flag. + * - ERTC_TSF_FLAG: timestamp flag. + * - ERTC_TP1F_FLAG: tamper detection 1 flag. + * @retval the new state of flag (SET or RESET). + */ +flag_status ertc_interrupt_flag_get(uint32_t flag) +{ + __IO uint32_t iten = 0; + + switch(flag) + { + case ERTC_ALAF_FLAG: + iten = ERTC->ctrl_bit.alaien; + break; + case ERTC_WATF_FLAG: + iten = ERTC->ctrl_bit.watien; + break; + case ERTC_TSF_FLAG: + iten = ERTC->ctrl_bit.tsien; + break; + case ERTC_TP1F_FLAG: + iten = ERTC->tamp_bit.tpien; + break; + + default: + break; + } + + if(((ERTC->sts & flag) != (uint32_t)RESET) && (iten)) + { + return SET; + } + else + { + return RESET; + } +} + /** * @brief clear flag status * @param flag: specifies the flag to clear. @@ -1339,13 +1380,7 @@ void ertc_bpr_data_write(ertc_dt_type dt, uint32_t data) reg = ERTC_BASE + 0x50 + (dt * 4); - /* disable write protection */ - ertc_write_protect_disable(); - *(__IO uint32_t *)reg = data; - - /* enable write protection */ - ertc_write_protect_enable(); } /** diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_exint.c b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_exint.c index e271211918..c5f013d240 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_exint.c +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_exint.c @@ -151,6 +151,34 @@ flag_status exint_flag_get(uint32_t exint_line) return status; } +/** + * @brief get exint interrupt flag + * @param exint_line + * this parameter can be one of the following values: + * - EXINT_LINE_0 + * - EXINT_LINE_1 + * ... + * - EXINT_LINE_20 + * @retval state of exint flag + */ +flag_status exint_interrupt_flag_get(uint32_t exint_line) +{ + flag_status status = RESET; + uint32_t exint_flag =0; + exint_flag = EXINT->intsts & exint_line; + exint_flag = exint_flag & EXINT->inten; + + if((exint_flag != (uint16_t)RESET)) + { + status = SET; + } + else + { + status = RESET; + } + return status; +} + /** * @brief generate exint software interrupt event * @param exint_line diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_flash.c b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_flash.c index 5425c073d3..739999ad71 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_flash.c +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_flash.c @@ -634,7 +634,7 @@ flash_status_type flash_slib_enable(uint32_t pwd, uint16_t start_sector, uint16_ flash_status_type status = FLASH_OPERATE_DONE; /*check range param limits*/ - if((start_sector>=inst_start_sector) || ((inst_start_sector > end_sector) && \ + if((start_sector > inst_start_sector) || ((inst_start_sector > end_sector) && \ (inst_start_sector != 0x7FF)) || (start_sector > end_sector)) return FLASH_PROGRAM_ERROR; diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_i2c.c b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_i2c.c index e25e8026dd..9b2376b94b 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_i2c.c +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_i2c.c @@ -115,12 +115,12 @@ void i2c_own_address1_set(i2c_type *i2c_x, i2c_address_mode_type mode, uint16_t * this parameter can be one of the following values: * - I2C_ADDR2_NOMASK: compare bit [7:1]. * - I2C_ADDR2_MASK01: only compare bit [7:2]. - * - I2C_ADDR2_MASK02: only compare bit [7:2]. - * - I2C_ADDR2_MASK03: only compare bit [7:3]. - * - I2C_ADDR2_MASK04: only compare bit [7:4]. - * - I2C_ADDR2_MASK05: only compare bit [7:5]. - * - I2C_ADDR2_MASK06: only compare bit [7:6]. - * - I2C_ADDR2_MASK07: only compare bit [7]. + * - I2C_ADDR2_MASK02: only compare bit [7:3]. + * - I2C_ADDR2_MASK03: only compare bit [7:4]. + * - I2C_ADDR2_MASK04: only compare bit [7:5]. + * - I2C_ADDR2_MASK05: only compare bit [7:6]. + * - I2C_ADDR2_MASK06: only compare bit [7]. + * - I2C_ADDR2_MASK07: response all addresses other than those reserved for i2c. * @retval none */ void i2c_own_address2_set(i2c_type *i2c_x, uint8_t address, i2c_addr2_mask_type mask) @@ -703,6 +703,77 @@ flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag) } } +/** + * @brief get interrupt flag status. + * @param i2c_x: to select the i2c peripheral. + * this parameter can be one of the following values: + * I2C1, I2C2. + * @param flag: specifies the flag to check. + * this parameter can be one of the following values: + * - I2C_TDBE_FLAG: transmit data buffer empty flag. + * - I2C_TDIS_FLAG: send interrupt status. + * - I2C_RDBF_FLAG: receive data buffer full flag. + * - I2C_ADDRF_FLAG: 0~7 bit address match flag. + * - I2C_ACKFAIL_FLAG: acknowledge failure flag. + * - I2C_STOPF_FLAG: stop condition generation complete flag. + * - I2C_TDC_FLAG: transmit data complete flag. + * - I2C_TCRLD_FLAG: transmission is complete, waiting to load data. + * - I2C_BUSERR_FLAG: bus error flag. + * - I2C_ARLOST_FLAG: arbitration lost flag. + * - I2C_OUF_FLAG: overflow or underflow flag. + * - I2C_PECERR_FLAG: pec receive error flag. + * - I2C_TMOUT_FLAG: smbus timeout flag. + * - I2C_ALERTF_FLAG: smbus alert flag. + * @retval the new state of flag (SET or RESET). + */ +flag_status i2c_interrupt_flag_get(i2c_type *i2c_x, uint32_t flag) +{ + __IO uint32_t iten = 0; + + switch(flag) + { + case I2C_TDIS_FLAG: + iten = i2c_x->ctrl1_bit.tdien; + break; + case I2C_RDBF_FLAG: + iten = i2c_x->ctrl1_bit.rdien; + break; + case I2C_ADDRF_FLAG: + iten = i2c_x->ctrl1_bit.addrien; + break; + case I2C_ACKFAIL_FLAG: + iten = i2c_x->ctrl1_bit.ackfailien; + break; + case I2C_STOPF_FLAG: + iten = i2c_x->ctrl1_bit.stopien; + break; + case I2C_TDC_FLAG: + case I2C_TCRLD_FLAG: + iten = i2c_x->ctrl1_bit.tdcien; + break; + case I2C_BUSERR_FLAG: + case I2C_ARLOST_FLAG: + case I2C_OUF_FLAG: + case I2C_PECERR_FLAG: + case I2C_TMOUT_FLAG: + case I2C_ALERTF_FLAG: + iten = i2c_x->ctrl1_bit.errien; + break; + + default: + break; + } + + if(((i2c_x->sts & flag) != RESET) && (iten)) + { + return SET; + } + else + { + return RESET; + } +} + /** * @brief clear flag status * @param i2c_x: to select the i2c peripheral. diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_pwc.c b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_pwc.c index ddee3898ae..8ec4982927 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_pwc.c +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_pwc.c @@ -218,17 +218,17 @@ void pwc_voltage_regulate_set(pwc_regulator_type pwc_regulator) { switch(pwc_regulator) { - case 0: - PWC->ctrl2_bit.vrexlpen = 0; - PWC->ctrl_bit.vrsel = 0; + case PWC_REGULATOR_ON: + PWC->ctrl2_bit.vrexlpen = FALSE; + PWC->ctrl_bit.vrsel = FALSE; break; - case 1: - PWC->ctrl2_bit.vrexlpen = 0; - PWC->ctrl_bit.vrsel = 1; + case PWC_REGULATOR_LOW_POWER: + PWC->ctrl2_bit.vrexlpen = FALSE; + PWC->ctrl_bit.vrsel = TRUE; break; - case 2: - PWC->ctrl2_bit.vrexlpen = 1; - PWC->ctrl_bit.vrsel = 1; + case PWC_REGULATOR_EXTRA_LOW_POWER: + PWC->ctrl2_bit.vrexlpen = TRUE; + PWC->ctrl_bit.vrsel = TRUE; break; default: break; diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_scfg.c b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_scfg.c index 42d1ad76fa..26a3b3858b 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_scfg.c +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_scfg.c @@ -55,8 +55,6 @@ void scfg_reset(void) * @param source * this parameter can be one of the following values: * - SCFG_IR_SOURCE_TMR10 - * - SCFG_IR_SOURCE_USART1 - * - SCFG_IR_SOURCE_USART2 * @param polarity * this parameter can be one of the following values: * - SCFG_IR_POLARITY_NO_AFFECTE @@ -77,9 +75,13 @@ void scfg_infrared_config(scfg_ir_source_type source, scfg_ir_polarity_type pola * - SCFG_MEM_MAP_BOOT_MEMORY * - SCFG_MEM_MAP_INTERNAL_SRAM */ -uint8_t scfg_mem_map_get(void) +scfg_mem_map_type scfg_mem_map_get(void) { - return (uint8_t)SCFG->cfg1_bit.mem_map_sel ; + if(SCFG->cfg1_bit.mem_map_sel & 0x1) + { + return (scfg_mem_map_type)SCFG->cfg1_bit.mem_map_sel; + } + return SCFG_MEM_MAP_MAIN_MEMORY; } /** diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_spi.c b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_spi.c index 880ccbe3b3..b1323e277c 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_spi.c +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_spi.c @@ -588,6 +588,77 @@ flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag) return status; } +/** + * @brief get flag of the specified spi/i2s peripheral. + * @param spi_x: select the spi/i2s peripheral. + * this parameter can be one of the following values: + * SPI1, SPI2, SPI3 + * @param spi_i2s_flag: select the spi/i2s flag + * this parameter can be one of the following values: + * - SPI_I2S_RDBF_FLAG + * - SPI_I2S_TDBE_FLAG + * - I2S_TUERR_FLAG (this flag only use in i2s mode) + * - SPI_CCERR_FLAG (this flag only use in spi mode) + * - SPI_MMERR_FLAG (this flag only use in spi mode) + * - SPI_I2S_ROERR_FLAG + * - SPI_CSPAS_FLAG + * @retval the new state of spi/i2s flag + */ +flag_status spi_i2s_interrupt_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag) +{ + flag_status status = RESET; + + switch(spi_i2s_flag) + { + case SPI_I2S_RDBF_FLAG: + if(spi_x->sts_bit.rdbf && spi_x->ctrl2_bit.rdbfie) + { + status = SET; + } + break; + case SPI_I2S_TDBE_FLAG: + if(spi_x->sts_bit.tdbe && spi_x->ctrl2_bit.tdbeie) + { + status = SET; + } + break; + case I2S_TUERR_FLAG: + if(spi_x->sts_bit.tuerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_CCERR_FLAG: + if(spi_x->sts_bit.ccerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_MMERR_FLAG: + if(spi_x->sts_bit.mmerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_I2S_ROERR_FLAG: + if(spi_x->sts_bit.roerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_CSPAS_FLAG: + if(spi_x->sts_bit.cspas && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + default: + break; + }; + return status; +} + + /** * @brief clear flag of the specified spi/i2s peripheral. * @param spi_x: select the spi/i2s peripheral. diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_tmr.c b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_tmr.c index 471ecdf035..68b860e7bf 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_tmr.c +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_tmr.c @@ -775,7 +775,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct switch(channel) { case TMR_SELECT_CHANNEL_1: - tmr_x->cctrl_bit.c1en = FALSE; + tmr_x->cctrl_bit.c1en = FALSE; tmr_x->cctrl_bit.c1p = (uint32_t)input_struct->input_polarity_select; tmr_x->cctrl_bit.c1cp = (input_struct->input_polarity_select & 0x2) >> 1; tmr_x->cm1_input_bit.c1c = input_struct->input_mapped_select; @@ -785,7 +785,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct break; case TMR_SELECT_CHANNEL_2: - tmr_x->cctrl_bit.c2en = FALSE; + tmr_x->cctrl_bit.c2en = FALSE; tmr_x->cctrl_bit.c2p = (uint32_t)input_struct->input_polarity_select; tmr_x->cctrl_bit.c2cp = (input_struct->input_polarity_select & 0x2) >> 1; tmr_x->cm1_input_bit.c2c = input_struct->input_mapped_select; @@ -795,7 +795,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct break; case TMR_SELECT_CHANNEL_3: - tmr_x->cctrl_bit.c3en = FALSE; + tmr_x->cctrl_bit.c3en = FALSE; tmr_x->cctrl_bit.c3p = (uint32_t)input_struct->input_polarity_select; tmr_x->cctrl_bit.c3cp = (input_struct->input_polarity_select & 0x2) >> 1; tmr_x->cm2_input_bit.c3c = input_struct->input_mapped_select; @@ -805,7 +805,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct break; case TMR_SELECT_CHANNEL_4: - tmr_x->cctrl_bit.c4en = FALSE; + tmr_x->cctrl_bit.c4en = FALSE; tmr_x->cctrl_bit.c4p = (uint32_t)input_struct->input_polarity_select; tmr_x->cm2_input_bit.c4c = input_struct->input_mapped_select; tmr_x->cm2_input_bit.c4df = input_struct->input_filter_value; @@ -1277,11 +1277,46 @@ void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state } } +/** + * @brief get tmr interrupt flag + * @param tmr_x: select the tmr peripheral. + * this parameter can be one of the following values: + * TMR1, TMR2, TMR3, TMR6, TMR7, TMR13, TMR14, TMR15, + * TMR16, TMR17 + * @param tmr_flag + * this parameter can be one of the following values: + * - TMR_OVF_FLAG + * - TMR_C1_FLAG + * - TMR_C2_FLAG + * - TMR_C3_FLAG + * - TMR_C4_FLAG + * - TMR_HALL_FLAG + * - TMR_TRIGGER_FLAG + * - TMR_BRK_FLAG + * @retval state of tmr interrupt flag + */ +flag_status tmr_interrupt_flag_get(tmr_type *tmr_x, uint32_t tmr_flag) +{ + flag_status status = RESET; + + if((tmr_x->ists & tmr_flag) && (tmr_x->iden & tmr_flag)) + { + status = SET; + } + else + { + status = RESET; + } + + return status; +} + /** * @brief get tmr flag * @param tmr_x: select the tmr peripheral. * this parameter can be one of the following values: - * TMR1, TMR2, TMR3, TMR6, TMR7, TMR13, TMR14, TMR15, TMR16, TMR17 + * TMR1, TMR2, TMR3, TMR6, TMR7, TMR13, TMR14, TMR15, + * TMR16, TMR17 * @param tmr_flag * this parameter can be one of the following values: * - TMR_OVF_FLAG @@ -1317,7 +1352,9 @@ flag_status tmr_flag_get(tmr_type *tmr_x, uint32_t tmr_flag) /** * @brief clear tmr flag * @param tmr_x: select the tmr peripheral. - * TMR1, TMR2, TMR3, TMR6, TMR7, TMR13, TMR14, TMR15, TMR16, TMR17 + * this parameter can be one of the following values: + * TMR1, TMR2, TMR3, TMR6, TMR7, TMR13, TMR14, TMR15, + * TMR16, TMR17 * @param tmr_flag * this parameter can be any combination of the following values: * - TMR_OVF_FLAG @@ -1343,7 +1380,8 @@ void tmr_flag_clear(tmr_type *tmr_x, uint32_t tmr_flag) * @brief generate tmr event * @param tmr_x: select the tmr peripheral. * this parameter can be one of the following values: - * TMR1, TMR2, TMR3, TMR6, TMR7, TMR13, TMR14, TMR15, TMR16, TMR17 + * TMR1, TMR2, TMR3, TMR6, TMR7, TMR13, TMR14, TMR15, + * TMR16, TMR17 * @param tmr_event * this parameter can be one of the following values: * - TMR_OVERFLOW_SWTRIG @@ -1656,7 +1694,7 @@ void tmr_dma_control_config(tmr_type *tmr_x, tmr_dma_transfer_length_type dma_le } /** - * @brief config tmr break mode and dead-time + * @brief config tmr brake mode and dead-time * @param tmr_x: select the tmr peripheral. * this parameter can be one of the following values: * TMR1, TMR15, TMR16, TMR17 @@ -1675,6 +1713,19 @@ void tmr_brkdt_config(tmr_type *tmr_x, tmr_brkdt_config_type *brkdt_struct) tmr_x->brk_bit.wpc = brkdt_struct->wp_level; } +/** + * @brief set tmr break input filter value + * @param tmr_x: select the tmr peripheral. + * this parameter can be one of the following values: + * TMR1, TMR15, TMR16, TMR17 + * @param filter_value (0x0~0xf) + * @retval none + */ +void tmr_brk_filter_value_set(tmr_type *tmr_x, uint8_t filter_value) +{ + tmr_x->brk_bit.bkf = filter_value; +} + /** * @brief set tmr14 input channel remap * @param tmr_x: select the tmr peripheral. diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_usart.c b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_usart.c index f4c2521fad..ddd04a0a49 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_usart.c +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_usart.c @@ -82,6 +82,9 @@ void usart_reset(usart_type* usart_x) * - USART_DATA_7BITS * - USART_DATA_8BITS * - USART_DATA_9BITS. + * note: + * - when parity check is disabled, the data bit width is the actual data bit number. + * - when parity check is enabled, the data bit width is the actual data bit number minus 1, and the MSB bit is replaced with the parity bit. * @param stop_bit: stop bits transmitted * this parameter can be one of the following values: * - USART_STOP_1_BIT @@ -579,6 +582,79 @@ flag_status usart_flag_get(usart_type* usart_x, uint32_t flag) } } +/** + * @brief check whether the specified usart interrupt flag is set or not. + * @param usart_x: select the usart or the uart peripheral. + * this parameter can be one of the following values: + * USART1, USART2, USART3 or USART4. + * @param flag: specifies the flag to check. + * this parameter can be one of the following values: + * - USART_CTSCF_FLAG: cts change flag (not available for UART4,UART5) + * - USART_BFF_FLAG: break frame flag + * - USART_TDBE_FLAG: transmit data buffer empty flag + * - USART_TDC_FLAG: transmit data complete flag + * - USART_RDBF_FLAG: receive data buffer full flag + * - USART_IDLEF_FLAG: idle flag + * - USART_ROERR_FLAG: receiver overflow error flag + * - USART_NERR_FLAG: noise error flag + * - USART_FERR_FLAG: framing error flag + * - USART_PERR_FLAG: parity error flag + * @retval the new state of usart_flag (SET or RESET). + */ +flag_status usart_interrupt_flag_get(usart_type* usart_x, uint32_t flag) +{ + flag_status int_status = RESET; + + switch(flag) + { + case USART_CTSCF_FLAG: + int_status = (flag_status)usart_x->ctrl3_bit.ctscfien; + break; + case USART_BFF_FLAG: + int_status = (flag_status)usart_x->ctrl2_bit.bfien; + break; + case USART_TDBE_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.tdbeien; + break; + case USART_TDC_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.tdcien; + break; + case USART_RDBF_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.rdbfien; + break; + case USART_ROERR_FLAG: + int_status = (flag_status)(usart_x->ctrl1_bit.rdbfien || usart_x->ctrl3_bit.errien); + break; + case USART_IDLEF_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.idleien; + break; + case USART_NERR_FLAG: + case USART_FERR_FLAG: + int_status = (flag_status)usart_x->ctrl3_bit.errien; + break; + case USART_PERR_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.perrien; + break; + default: + int_status = RESET; + break; + } + + if(int_status != SET) + { + return RESET; + } + + if(usart_x->sts & flag) + { + return SET; + } + else + { + return RESET; + } +} + /** * @brief clear the usart's pending flags. * @param usart_x: select the usart or the uart peripheral. diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_usb.c b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_usb.c index b9e8033e8a..c87a7b8a84 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_usb.c +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_usb.c @@ -97,7 +97,7 @@ void usb_global_init(otg_global_type *usbx) */ otg_global_type *usb_global_select_core(uint8_t usb_id) { - /* use otg1 */ + UNUSED(usb_id); return OTG1_GLOBAL; } @@ -438,6 +438,7 @@ void usb_read_packet(otg_global_type *usbx, uint8_t *pusr_buf, uint16_t num, uin uint32_t n_index; uint32_t nhbytes = (nbytes + 3) / 4; uint32_t *pbuf = (uint32_t *)pusr_buf; + UNUSED(num); for(n_index = 0; n_index < nhbytes; n_index ++) { #if defined (__ICCARM__) && (__VER__ < 7000000) diff --git a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_wwdt.c b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_wwdt.c index a3842fad3b..c1d824a43a 100644 --- a/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_wwdt.c +++ b/bsp/at32/libraries/AT32F425_Firmware_Library/drivers/src/at32f425_wwdt.c @@ -104,6 +104,16 @@ flag_status wwdt_flag_get(void) return (flag_status)WWDT->sts_bit.rldf; } +/** + * @brief wwdt reload counter interrupt flag get + * @param none + * @retval state of reload counter interrupt flag + */ +flag_status wwdt_interrupt_flag_get(void) +{ + return (flag_status)(WWDT->sts_bit.rldf && WWDT->cfg_bit.rldien); +} + /** * @brief wwdt counter value set * @param wwdt_cnt (0x40~0x7f) diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/system_at32f435_437.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/system_at32f435_437.c index 70070c7796..4b5e42178d 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/system_at32f435_437.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/system_at32f435_437.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file system_at32f435_437.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for cmsis cortex-m4 system source file ************************************************************************** * Copyright notice & Disclaimer @@ -37,7 +35,7 @@ /** @addtogroup AT32F435_437_system_private_defines * @{ */ -#define VECT_TAB_OFFSET 0x0 /*!< vector table base offset field. this value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x0 /*!< vector table base offset field. this value must be a multiple of 0x400. */ /** * @} */ @@ -81,12 +79,12 @@ void SystemInit (void) /* wait sclk switch status */ while(CRM->cfg_bit.sclksts != CRM_SCLK_HICK); - /* reset cfg register, include sclk switch, ahbdiv, apb1div, apb2div, adcdiv, clkout bits */ - CRM->cfg = 0; - /* reset hexten, hextbyps, cfden and pllen bits */ CRM->ctrl &= ~(0x010D0000U); + /* reset cfg register, include sclk switch, ahbdiv, apb1div, apb2div, adcdiv, clkout bits */ + CRM->cfg = 0; + /* reset pllms pllns pllfr pllrcs bits */ CRM->pllcfg = 0x00033002U; diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/system_at32f435_437.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/system_at32f435_437.h index 1365c30f43..9bff3b94fb 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/system_at32f435_437.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/cmsis/cm4/device_support/system_at32f435_437.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file system_at32f435_437.h - * @version v2.0.8 - * @date 2022-04-25 * @brief cmsis cortex-m4 system header file. ************************************************************************** * Copyright notice & Disclaimer @@ -39,6 +37,12 @@ extern "C" { * @{ */ +#define SystemCoreClock system_core_clock +#define DUMMY_NOP() {__NOP();__NOP();__NOP();__NOP();__NOP(); \ + __NOP();__NOP();__NOP();__NOP();__NOP(); \ + __NOP();__NOP();__NOP();__NOP();__NOP(); \ + __NOP();__NOP();__NOP();__NOP();__NOP();} + /** @defgroup AT32F435_437_system_exported_variables * @{ */ diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_acc.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_acc.h index 50eac602f0..91c0d91c58 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_acc.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_acc.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_acc.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 acc header file ************************************************************************** * Copyright notice & Disclaimer @@ -184,6 +182,7 @@ uint16_t acc_read_c1(void); uint16_t acc_read_c2(void); uint16_t acc_read_c3(void); flag_status acc_flag_get(uint16_t acc_flag); +flag_status acc_interrupt_flag_get(uint16_t acc_flag); void acc_flag_clear(uint16_t acc_flag); /** diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_adc.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_adc.h index 9f390c9ee8..80a7069b46 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_adc.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_adc.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_adc.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 adc header file ************************************************************************** * Copyright notice & Disclaimer @@ -912,6 +910,7 @@ uint16_t adc_ordinary_conversion_data_get(adc_type *adc_x); uint32_t adc_combine_ordinary_conversion_data_get(void); uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel); flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag); +flag_status adc_interrupt_flag_get(adc_type *adc_x, uint8_t adc_flag); void adc_flag_clear(adc_type *adc_x, uint32_t adc_flag); void adc_ordinary_oversample_enable(adc_type *adc_x, confirm_state new_state); void adc_preempt_oversample_enable(adc_type *adc_x, confirm_state new_state); diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_can.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_can.h index 9fcb209d15..3dd9011386 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_can.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_can.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_can.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 can header file ************************************************************************** * Copyright notice & Disclaimer @@ -352,7 +350,7 @@ typedef struct */ typedef struct { - uint16_t baudrate_div; /*!< baudrate division,this parameter can be 0x001~0x400.*/ + uint16_t baudrate_div; /*!< baudrate division,this parameter can be 0x001~0x1000.*/ can_rsaw_type rsaw_size; /*!< resynchronization adjust width */ @@ -1020,6 +1018,7 @@ can_error_record_type can_error_type_record_get(can_type* can_x); uint8_t can_receive_error_counter_get(can_type* can_x); uint8_t can_transmit_error_counter_get(can_type* can_x); void can_interrupt_enable(can_type* can_x, uint32_t can_int, confirm_state new_state); +flag_status can_interrupt_flag_get(can_type* can_x, uint32_t can_flag); flag_status can_flag_get(can_type* can_x, uint32_t can_flag); void can_flag_clear(can_type* can_x, uint32_t can_flag); diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_crc.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_crc.h index 484f3abfbb..a0ff483263 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_crc.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_crc.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_crc.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 crc header file ************************************************************************** * Copyright notice & Disclaimer @@ -68,6 +66,17 @@ typedef enum CRC_REVERSE_OUTPUT_DATA = 0x01 /*!< output data reverse by word */ } crc_reverse_output_type; +/** + * @brief crc polynomial size + */ +typedef enum +{ + CRC_POLY_SIZE_32B = 0x00, /*!< polynomial size 32 bits */ + CRC_POLY_SIZE_16B = 0x01, /*!< polynomial size 16 bits */ + CRC_POLY_SIZE_8B = 0x02, /*!< polynomial size 8 bits */ + CRC_POLY_SIZE_7B = 0x03 /*!< polynomial size 7 bits */ +} crc_poly_size_type; + /** * @brief type define crc register all */ @@ -107,7 +116,8 @@ typedef struct struct { __IO uint32_t rst : 1 ; /* [0] */ - __IO uint32_t reserved1 : 4 ; /* [4:1] */ + __IO uint32_t reserved1 : 2 ; /* [2:1] */ + __IO uint32_t poly_size : 2 ; /* [4:3] */ __IO uint32_t revid : 2 ; /* [6:5] */ __IO uint32_t revod : 1 ; /* [7] */ __IO uint32_t reserved2 : 24 ;/* [31:8] */ @@ -131,6 +141,18 @@ typedef struct } idt_bit; }; + /** + * @brief crc polynomial register, offset:0x14 + */ + union + { + __IO uint32_t poly; + struct + { + __IO uint32_t poly : 32; /* [31:0] */ + } poly_bit; + }; + } crc_type; /** @@ -148,10 +170,14 @@ uint32_t crc_one_word_calculate(uint32_t data); uint32_t crc_block_calculate(uint32_t *pbuffer, uint32_t length); uint32_t crc_data_get(void); void crc_common_data_set(uint8_t cdt_value); -uint8_t crc_common_date_get(void); +uint8_t crc_common_data_get(void); void crc_init_data_set(uint32_t value); void crc_reverse_input_data_set(crc_reverse_input_type value); void crc_reverse_output_data_set(crc_reverse_output_type value); +void crc_poly_value_set(uint32_t value); +uint32_t crc_poly_value_get(void); +void crc_poly_size_set(crc_poly_size_type size); +crc_poly_size_type crc_poly_size_get(void); /** * @} diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_crm.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_crm.h index 5358d720d3..4e24d97e19 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_crm.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_crm.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_crm.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 crm header file ************************************************************************** * Copyright notice & Disclaimer @@ -398,13 +396,12 @@ typedef enum CRM_GPIOG_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 6), /*!< gpiog sleep mode periph clock */ CRM_GPIOH_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 7), /*!< gpioh sleep mode periph clock */ CRM_CRC_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 12), /*!< crc sleep mode periph clock */ + CRM_FLASH_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 15), /*!< flash sleep mode periph clock */ + CRM_SRAM1_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 16), /*!< sram1 sleep mode periph clock */ + CRM_SRAM2_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 17), /*!< sram2 sleep mode periph clock */ CRM_EDMA_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 21), /*!< edma sleep mode periph clock */ CRM_DMA1_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 22), /*!< dma1 sleep mode periph clock */ CRM_DMA2_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 24), /*!< dma2 sleep mode periph clock */ - CRM_EMAC_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 25), /*!< emac sleep mode periph clock */ - CRM_EMACTX_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 26), /*!< emac tx sleep mode periph clock */ - CRM_EMACRX_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 27), /*!< emac rx sleep mode periph clock */ - CRM_EMACPTP_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 28), /*!< emac ptp sleep mode periph clock */ CRM_OTGFS2_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 29), /*!< otgfs2 sleep mode periph clock */ /* ahb periph2 */ CRM_DVP_PERIPH_LOWPOWER = MAKE_VALUE(0x54, 0), /*!< dvp sleep mode periph clock */ @@ -470,9 +467,16 @@ typedef enum CRM_GPIOG_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 6), /*!< gpiog sleep mode periph clock */ CRM_GPIOH_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 7), /*!< gpioh sleep mode periph clock */ CRM_CRC_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 12), /*!< crc sleep mode periph clock */ + CRM_FLASH_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 15), /*!< flash sleep mode periph clock */ + CRM_SRAM1_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 16), /*!< sram1 sleep mode periph clock */ + CRM_SRAM2_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 17), /*!< sram2 sleep mode periph clock */ CRM_EDMA_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 21), /*!< edma sleep mode periph clock */ CRM_DMA1_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 22), /*!< dma1 sleep mode periph clock */ CRM_DMA2_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 24), /*!< dma2 sleep mode periph clock */ + CRM_EMAC_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 25), /*!< emac sleep mode periph clock */ + CRM_EMACTX_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 26), /*!< emac tx sleep mode periph clock */ + CRM_EMACRX_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 27), /*!< emac rx sleep mode periph clock */ + CRM_EMACPTP_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 28), /*!< emac ptp sleep mode periph clock */ CRM_OTGFS2_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 29), /*!< otgfs2 sleep mode periph clock */ /* ahb periph2 */ CRM_DVP_PERIPH_LOWPOWER = MAKE_VALUE(0x54, 0), /*!< dvp sleep mode periph clock */ @@ -1115,9 +1119,11 @@ typedef struct __IO uint32_t reserved3 : 1; /* [23] */ __IO uint32_t dma2en : 1; /* [24] */ __IO uint32_t emacen : 1; /* [25] */ - __IO uint32_t reserved4 : 3; /* [28:26] */ + __IO uint32_t emactxen : 1; /* [26] */ + __IO uint32_t emacrxen : 1; /* [27] */ + __IO uint32_t emacptpen : 1; /* [28] */ __IO uint32_t otgfs2en : 1; /* [29] */ - __IO uint32_t reserved5 : 2; /* [31:30] */ + __IO uint32_t reserved4 : 2; /* [31:30] */ } ahben1_bit; #endif }; @@ -1287,9 +1293,11 @@ typedef struct __IO uint32_t reserved3 : 1; /* [23] */ __IO uint32_t dma2lpen : 1; /* [24] */ __IO uint32_t emaclpen : 1; /* [25] */ - __IO uint32_t reserved4 : 3; /* [28:26] */ + __IO uint32_t emactxlpen : 1; /* [26] */ + __IO uint32_t emacrxlpen : 1; /* [27] */ + __IO uint32_t emacptplpen : 1; /* [28] */ __IO uint32_t otgfs2lpen : 1; /* [29] */ - __IO uint32_t reserved5 : 2; /* [31:30] */ + __IO uint32_t reserved4 : 2; /* [31:30] */ } ahblpen1_bit; #endif }; @@ -1513,6 +1521,7 @@ void crm_reset(void); void crm_lext_bypass(confirm_state new_state); void crm_hext_bypass(confirm_state new_state); flag_status crm_flag_get(uint32_t flag); +flag_status crm_interrupt_flag_get(uint32_t flag); error_status crm_hext_stable_wait(void); void crm_hick_clock_trimming_set(uint8_t trim_value); void crm_hick_clock_calibration_set(uint8_t cali_value); diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_dac.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_dac.h index 01cb78b8aa..a09aac8512 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_dac.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_dac.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_dac.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 dac header file ************************************************************************** * Copyright notice & Disclaimer @@ -373,6 +371,7 @@ void dac_2_data_set(dac2_aligned_data_type dac2_aligned, uint16_t dac2_data); void dac_dual_data_set(dac_dual_data_type dac_dual, uint16_t data1, uint16_t data2); void dac_udr_enable(dac_select_type dac_select, confirm_state new_state); flag_status dac_udr_flag_get(dac_select_type dac_select); +flag_status dac_udr_interrupt_flag_get(dac_select_type dac_select); void dac_udr_flag_clear(dac_select_type dac_select); /** diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_debug.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_debug.h index 80adf93513..8e6ccd2846 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_debug.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_debug.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_mcudbg.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 mcudbg header file ************************************************************************** * Copyright notice & Disclaimer @@ -120,6 +118,7 @@ typedef struct __IO uint32_t reserved1 : 29;/* [31:3] */ } ctrl_bit; }; + /** * @brief debug apb1 frz register, offset:0x08 */ @@ -152,8 +151,9 @@ typedef struct __IO uint32_t reserved4 : 3;/* [31:29] */ } apb1_frz_bit; }; + /** - * @brief debug apb2 frz register, offset:0x0c + * @brief debug apb2 frz register, offset:0x0C */ union { @@ -172,6 +172,26 @@ typedef struct } apb2_frz_bit; }; + /** + * @brief debug reserved1 register, offset:0x10~0x1C + */ + __IO uint32_t reserved1[4]; + + /** + * @brief debug ser id register, offset:0x20 + */ + union + { + __IO uint32_t ser_id; + struct + { + __IO uint32_t rev_id : 3;/* [2:0] */ + __IO uint32_t reserved1 : 5;/* [7:3] */ + __IO uint32_t ser_id : 8;/* [15:8] */ + __IO uint32_t reserved2 : 16;/* [31:16] */ + } ser_id_bit; + }; + } debug_type; /** diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_def.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_def.h index 285988cd42..c6bb77604f 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_def.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_def.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_def.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 macros header file ************************************************************************** * Copyright notice & Disclaimer @@ -62,6 +60,8 @@ extern "C" { #endif #endif +#define UNUSED(x) (void)x /* to avoid gcc/g++ warnings */ + #ifdef __cplusplus } #endif diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_dma.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_dma.h index ce8adb3d7c..974cb96a7f 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_dma.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_dma.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_dma.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 dma header file ************************************************************************** * Copyright notice & Disclaimer @@ -747,6 +745,7 @@ uint16_t dma_data_number_get(dma_channel_type *dmax_channely); void dma_interrupt_enable(dma_channel_type *dmax_channely, uint32_t dma_int, confirm_state new_state); void dma_channel_enable(dma_channel_type *dmax_channely, confirm_state new_state); flag_status dma_flag_get(uint32_t dmax_flag); +flag_status dma_interrupt_flag_get(uint32_t dmax_flag); void dma_flag_clear(uint32_t dmax_flag); void dma_default_para_init(dma_init_type *dma_init_struct); void dma_init(dma_channel_type *dmax_channely, dma_init_type *dma_init_struct); @@ -762,8 +761,10 @@ void dmamux_generator_config(dmamux_generator_type *dmamux_gen_x, dmamux_gen_ini void dmamux_sync_interrupt_enable(dmamux_channel_type *dmamux_channelx, confirm_state new_state); void dmamux_generator_interrupt_enable(dmamux_generator_type *dmamux_gen_x, confirm_state new_state); flag_status dmamux_sync_flag_get(dma_type *dma_x, uint32_t flag); +flag_status dmamux_sync_interrupt_flag_get(dma_type *dma_x, uint32_t flag); void dmamux_sync_flag_clear(dma_type *dma_x, uint32_t flag); flag_status dmamux_generator_flag_get(dma_type *dma_x, uint32_t flag); +flag_status dmamux_generator_interrupt_flag_get(dma_type *dma_x, uint32_t flag); void dmamux_generator_flag_clear(dma_type *dma_x, uint32_t flag); /** diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_dvp.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_dvp.h index 3169c63fa2..65d1bc5c87 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_dvp.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_dvp.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_dvp.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 dvp header file ************************************************************************** * Copyright notice & Disclaimer @@ -204,17 +202,17 @@ typedef enum { DVP_STATUS_HSYN = 0x00, DVP_STATUS_VSYN = 0x01, - DVP_STATUS_OFS = 0x02 + DVP_STATUS_OFNE = 0x02 } dvp_status_basic_type; /** - * @brief dvp pcdse type + * @brief dvp pcdes type */ typedef enum { - DVP_PCDSE_CAP_FIRST = 0x00, - DVP_PCDSE_DROP_FIRST = 0x01 -} dvp_pcdse_type; + DVP_PCDES_CAP_FIRST = 0x00, + DVP_PCDES_DROP_FIRST = 0x01 +} dvp_pcdes_type; /** * @brief dvp efdf type @@ -224,18 +222,18 @@ typedef enum DVP_EFDF_BYPASS = 0x00, DVP_EFDF_YUV422_UYVY = 0x04, DVP_EFDF_YUV422_YUYV = 0x05, - DVP_EFDF_YUV444 = 0x06, + DVP_EFDF_RGB565_555 = 0x06, DVP_EFDF_Y8 = 0x07 } dvp_efdf_type; /** - * @brief dvp iduc type + * @brief dvp idus type */ typedef enum { - DVP_IDUC_MSB = 0x00, - DVP_IDUC_LSB = 0x01 -} dvp_iduc_type; + DVP_IDUS_MSB = 0x00, + DVP_IDUS_LSB = 0x01 +} dvp_idus_type; /** * @brief dvp dmabt type @@ -247,22 +245,22 @@ typedef enum } dvp_dmabt_type; /** - * @brief dvp hseis type + * @brief dvp hseid type */ typedef enum { - DVP_HSEIS_LINE_END = 0x00, - DVP_HSEIS_LINE_START = 0x01 -} dvp_hseis_type; + DVP_HSEID_LINE_END = 0x00, + DVP_HSEID_LINE_START = 0x01 +} dvp_hseid_type; /** - * @brief dvp vseis type + * @brief dvp vseid type */ typedef enum { - DVP_VSEIS_FRAME_END = 0x00, - DVP_VSEIS_FRMAE_START = 0x01 -} dvp_vseis_type; + DVP_VSEID_FRAME_END = 0x00, + DVP_VSEID_FRMAE_START = 0x01 +} dvp_vseid_type; /** * @brief dvp idun type */ @@ -301,7 +299,7 @@ typedef struct __IO uint32_t pcds : 1; /* [18] */ __IO uint32_t lcdc : 1; /* [19] */ __IO uint32_t lcds : 1; /* [20] */ - __IO uint32_t : 11;/* [31:21] */ + __IO uint32_t reserved3 : 11;/* [31:21] */ } ctrl_bit; }; @@ -315,7 +313,7 @@ typedef struct { __IO uint32_t hsyn : 1; /* [0] */ __IO uint32_t vsyn : 1; /* [1] */ - __IO uint32_t ofs : 1; /* [2] */ + __IO uint32_t ofne : 1; /* [2] */ __IO uint32_t reserved1 : 29;/* [31:3] */ } sts_bit; }; @@ -479,18 +477,18 @@ typedef struct __IO uint32_t eisre : 1; /* [0] */ __IO uint32_t efrce : 1; /* [1] */ __IO uint32_t mibe : 1; /* [2] */ - __IO uint32_t pcdse : 1; /* [3] */ + __IO uint32_t pcdes : 1; /* [3] */ __IO uint32_t efdf : 3; /* [6:4] */ __IO uint32_t reserved1 : 1; /* [7] */ __IO uint32_t idun : 2; /* [9:8] */ - __IO uint32_t iduc : 1; /* [10] */ + __IO uint32_t idus : 1; /* [10] */ __IO uint32_t reserved2 : 1; /* [11] */ __IO uint32_t dmabt : 1; /* [12] */ __IO uint32_t reserved3 : 1; /* [13] */ __IO uint32_t reserved4 : 1; /* [14] */ __IO uint32_t reserved5 : 1; /* [15] */ - __IO uint32_t hseis : 1; /* [16] */ - __IO uint32_t vseis : 1; /* [17] */ + __IO uint32_t hseid : 1; /* [16] */ + __IO uint32_t vseid : 1; /* [17] */ __IO uint32_t reserved6 : 1; /* [18] */ __IO uint32_t reserved7 : 2; /* [20:19] */ __IO uint32_t reserved8 : 11;/* [31:21] */ @@ -540,9 +538,9 @@ typedef struct __IO uint32_t frf; struct { - __IO uint32_t efrcfm : 5; /* [4:0] */ + __IO uint32_t efrcsf : 5; /* [4:0] */ __IO uint32_t reserved1 : 3; /* [7:5] */ - __IO uint32_t efrcfn : 5; /* [12:8] */ + __IO uint32_t efrctf : 5; /* [12:8] */ __IO uint32_t reserved2 : 19;/* [31:13] */ } frf_bit; }; @@ -572,10 +570,12 @@ typedef struct * @{ */ +void dvp_reset(void); +void dvp_capture_enable(confirm_state new_state); void dvp_capture_enable(confirm_state new_state); void dvp_capture_mode_set(dvp_cfm_type cap_mode); void dvp_window_crop_enable(confirm_state new_state); -void dvp_window_crop_set(uint16_t crop_x, uint16_t crop_y, uint16_t crop_w, uint16_t crop_h); +void dvp_window_crop_set(uint16_t crop_x, uint16_t crop_y, uint16_t crop_w, uint16_t crop_h, uint8_t bytes); void dvp_jpeg_enable(confirm_state new_state); void dvp_sync_mode_set(dvp_sm_type sync_mode); void dvp_sync_code_set(uint8_t fmsc, uint8_t fmec, uint8_t lnsc, uint8_t lnec); @@ -586,20 +586,21 @@ void dvp_vsync_polarity_set(dvp_vsp_type vsync_pol); void dvp_basic_frame_rate_control_set(dvp_bfrc_type dvp_bfrc); void dvp_pixel_data_length_set(dvp_pdl_type dvp_pdl); void dvp_enable(confirm_state new_state); -void dvp_zoomout_select(dvp_pcdse_type dvp_pcdse); +void dvp_zoomout_select(dvp_pcdes_type dvp_pcdes); void dvp_zoomout_set(dvp_pcdc_type dvp_pcdc, dvp_pcds_type dvp_pcds, dvp_lcdc_type dvp_lcdc, dvp_lcds_type dvp_lcds); flag_status dvp_basic_status_get(dvp_status_basic_type dvp_status_basic); void dvp_interrupt_enable(uint32_t dvp_int, confirm_state new_state); +flag_status dvp_interrupt_flag_get(uint32_t flag); flag_status dvp_flag_get(uint32_t flag); void dvp_flag_clear(uint32_t flag); void dvp_enhanced_scaling_resize_enable(confirm_state new_state); void dvp_enhanced_scaling_resize_set(uint16_t src_w, uint16_t des_w, uint16_t src_h, uint16_t des_h); -void dvp_enhanced_framerate_set(uint16_t efrcfm, uint16_t efrcfn, confirm_state new_state); +void dvp_enhanced_framerate_set(uint16_t efrcsf, uint16_t efrctf, confirm_state new_state); void dvp_monochrome_image_binarization_set(uint8_t mibthd, confirm_state new_state); void dvp_enhanced_data_format_set(dvp_efdf_type dvp_efdf); -void dvp_input_data_unused_set(dvp_iduc_type dvp_iduc, dvp_idun_type dvp_idun); +void dvp_input_data_unused_set(dvp_idus_type dvp_idus, dvp_idun_type dvp_idun); void dvp_dma_burst_set(dvp_dmabt_type dvp_dmabt); -void dvp_sync_event_interrupt_set(dvp_hseis_type dvp_hseis, dvp_vseis_type dvp_vseis); +void dvp_sync_event_interrupt_set(dvp_hseid_type dvp_hseid, dvp_vseid_type dvp_vseid); /** * @} diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_edma.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_edma.h index 9d0d408d6c..68286e90be 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_edma.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_edma.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_edma.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 edma header file ************************************************************************** * Copyright notice & Disclaimer @@ -49,10 +47,10 @@ extern "C" { * @{ */ -#define EDMA_DMERR_INT ((uint32_t)0x00000002) /* edma direct mode error intterrupt */ -#define EDMA_DTERR_INT ((uint32_t)0x00000004) /* edma data transfer error intterrupt */ -#define EDMA_HDT_INT ((uint32_t)0x00000008) /* edma half data transfer intterrupt */ -#define EDMA_FDT_INT ((uint32_t)0x00000010) /* edma full data transfer intterrupt */ +#define EDMA_DMERR_INT ((uint32_t)0x00000002) /* edma direct mode error interrupt */ +#define EDMA_DTERR_INT ((uint32_t)0x00000004) /* edma data transfer error interrupt */ +#define EDMA_HDT_INT ((uint32_t)0x00000008) /* edma half data transfer interrupt */ +#define EDMA_FDT_INT ((uint32_t)0x00000010) /* edma full data transfer interrupt */ #define EDMA_FERR_INT ((uint32_t)0x00000080) /* edma fifo error interrupt */ /** @@ -1021,6 +1019,7 @@ edma_memory_type edma_memory_target_get(edma_stream_type *edma_streamx); flag_status edma_stream_status_get(edma_stream_type *edma_streamx); uint8_t edma_fifo_status_get(edma_stream_type *edma_streamx); flag_status edma_flag_get(uint32_t edma_flag); +flag_status edma_interrupt_flag_get(uint32_t edma_flag); void edma_flag_clear(uint32_t edma_flag); /* edma 2d controller function */ @@ -1041,8 +1040,10 @@ void edmamux_generator_config(edmamux_generator_type *edmamux_gen_x, edmamux_gen void edmamux_sync_interrupt_enable(edmamux_channel_type *edmamux_channelx, confirm_state new_state); void edmamux_generator_interrupt_enable(edmamux_generator_type *edmamux_gen_x, confirm_state new_state); flag_status edmamux_sync_flag_get(uint32_t flag); +flag_status edmamux_sync_interrupt_flag_get(uint32_t flag); void edmamux_sync_flag_clear(uint32_t flag); flag_status edmamux_generator_flag_get(uint32_t flag); +flag_status edmamux_generator_interrupt_flag_get(uint32_t flag); void edmamux_generator_flag_clear(uint32_t flag); /** diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_emac.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_emac.h index 85c04805b6..12a5c338d0 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_emac.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_emac.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_emac.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 eth header file ************************************************************************** * Copyright notice & Disclaimer @@ -45,6 +43,7 @@ extern "C" { */ #define PHY_TIMEOUT (0x000FFFFF) /*!< timeout for phy response */ +#define EMAC_USE_ENHANCED_DMA_DESCRIPTOR /** @defgroup EMAC_smi_clock_border_definition * @brief emac smi clock border @@ -271,6 +270,15 @@ extern "C" { #define EMAC_DMA_AIS_FLAG ((uint32_t)0x00008000) /*!< emac dma abnormal interrupt summary */ #define EMAC_DMA_NIS_FLAG ((uint32_t)0x00010000) /*!< emac dma normal interrupt summary */ +/** + * @brief emac ptp time sign + */ +#define EMAC_PTP_POSITIVETIME ((uint32_t)0x00000000) /*!< Positive time value */ +#define EMAC_PTP_NEGATIVETIME ((uint32_t)0x80000000) /*!< Negative time value */ + +#define EMAC_PTP_TI_FLAG ((uint32_t)0x00000004) /*!< Time Stamp Initialized */ +#define EMAC_PTP_TU_FLAG ((uint32_t)0x00000008) /*!< Time Stamp Updated */ +#define EMAC_PTP_ARU_FLAG ((uint32_t)0x00000020) /*!< Addend Register Updated */ /** @defgroup EMAC_exported_types * @{ */ @@ -346,9 +354,10 @@ typedef enum */ typedef enum { - EMAC_CONTROL_FRAME_PASSING_NO = 0x00, /*!< don't pass any control frame to application */ - EMAC_CONTROL_FRAME_PASSING_ALL = 0x02, /*!< pass all control frames to application */ - EMAC_CONTROL_FRAME_PASSING_MATCH = 0x03 /*!< only pass filtered control frames to application */ + EMAC_CONTROL_FRAME_PASSING_NO = 0x00, /*!< don't pass any control frame to application */ + EMAC_CONTROL_FRAME_PASSING_ALL_EXCEPT_PAUSE = 0x01, /*!< pass all control frames to application except pause frame */ + EMAC_CONTROL_FRAME_PASSING_ALL = 0x02, /*!< pass all control frames to application */ + EMAC_CONTROL_FRAME_PASSING_MATCH = 0x03 /*!< only pass filtered control frames to application */ } emac_control_frames_filter_type; /** @@ -634,6 +643,10 @@ typedef struct { uint32_t controlsize; /*!< control and buffer1, buffer2 lengths */ uint32_t buf1addr; /*!< buffer1 address pointer */ uint32_t buf2nextdescaddr; /*!< buffer2 or next descriptor address pointer */ + uint32_t extendedstatus; + uint32_t reserved1; + uint32_t timestamp_l; + uint32_t timestamp_h; } emac_dma_desc_type; /** @@ -892,7 +905,7 @@ typedef struct __IO uint32_t reserved1 : 8; /* [16:23] */ __IO uint32_t mbc : 6; /* [24:29] */ __IO uint32_t sa : 1; /* [30] */ - __IO uint32_t ae : 1; /* [31] */ + __IO uint32_t ae : 1; /* [31] */ } a1h_bit; }; @@ -1329,7 +1342,7 @@ typedef struct __IO uint32_t swr : 1; /* [0] */ __IO uint32_t da : 1; /* [1] */ __IO uint32_t dsl : 5; /* [2:6] */ - __IO uint32_t reserved1 : 1; /* [7] */ + __IO uint32_t atds : 1; /* [7] */ __IO uint32_t pbl : 6; /* [8:13] */ __IO uint32_t pr : 2; /* [14:15] */ __IO uint32_t fb : 1; /* [16] */ @@ -1337,7 +1350,7 @@ typedef struct __IO uint32_t usp : 1; /* [23] */ __IO uint32_t pblx8 : 1; /* [24] */ __IO uint32_t aab : 1; /* [25] */ - __IO uint32_t reserved2 : 6; /* [26:31] */ + __IO uint32_t reserved : 6; /* [26:31] */ } bm_bit; }; @@ -1629,6 +1642,7 @@ void emac_address_filter_set(emac_address_type mac, emac_address_filter_type fil uint32_t emac_received_packet_size_get(void); uint32_t emac_dmarxdesc_frame_length_get(emac_dma_desc_type *dma_rx_desc); void emac_dma_descriptor_list_address_set(emac_dma_tx_rx_type transfer_type, emac_dma_desc_type *dma_desc_tab, uint8_t *buff, uint32_t buffer_count); +void emac_ptp_dma_descriptor_list_address_set(emac_dma_tx_rx_type transfer_type, emac_dma_desc_type *dma_desc_tab, emac_dma_desc_type *ptp_dma_desc_tab, uint8_t *buff, uint32_t buffer_count); uint32_t emac_dma_descriptor_list_address_get(emac_dma_tx_rx_type transfer_type); void emac_dma_rx_desc_interrupt_config(emac_dma_desc_type *dma_rx_desc, confirm_state new_state); void emac_dma_para_init(emac_dma_config_type *control_para); @@ -1651,6 +1665,7 @@ uint8_t emac_dma_missing_overflow_bit_get(void); uint16_t emac_dma_application_missing_frame_get(void); uint8_t emac_dma_fifo_overflow_bit_get(void); uint32_t emac_dma_tansfer_address_get(emac_dma_transfer_address_type transfer_type); +void emac_dma_alternate_desc_size(confirm_state new_state); void emac_mmc_counter_reset(void); void emac_mmc_rollover_stop(confirm_state new_state); void emac_mmc_reset_on_read_enable(confirm_state new_state); @@ -1677,19 +1692,19 @@ void emac_ptp_snapshot_event_message_enable(confirm_state new_state); void emac_ptp_snapshot_master_event_enable(confirm_state new_state); void emac_ptp_clock_node_set(emac_ptp_clock_node_type node); void emac_ptp_mac_address_filter_enable(confirm_state new_state); +flag_status emac_ptp_flag_get(uint32_t flag); void emac_ptp_subsecond_increment_set(uint8_t value); uint32_t emac_ptp_system_second_get(void); uint32_t emac_ptp_system_subsecond_get(void); confirm_state emac_ptp_system_time_sign_get(void); -void emac_ptp_system_second_set(uint32_t second); -void emac_ptp_system_subsecond_set(uint32_t subsecond); -void emac_ptp_system_time_sign_set(confirm_state sign); +void emac_ptp_system_time_set(uint32_t sign, uint32_t second, uint32_t subsecond); void emac_ptp_timestamp_addend_set(uint32_t value); void emac_ptp_target_second_set(uint32_t value); void emac_ptp_target_nanosecond_set(uint32_t value); confirm_state emac_ptp_timestamp_status_get(emac_ptp_timestamp_status_type status); void emac_ptp_pps_frequency_set(emac_ptp_pps_control_type freq); flag_status emac_dma_flag_get(uint32_t dma_flag); +flag_status emac_dma_interrupt_flag_get(uint32_t dma_flag); void emac_dma_flag_clear(uint32_t dma_flag); /** diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_ertc.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_ertc.h index a13eafd19c..ec65ad1384 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_ertc.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_ertc.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_ertc.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 ertc header file ************************************************************************** * Copyright notice & Disclaimer @@ -90,6 +88,12 @@ extern "C" { #define ERTC_ALARM_MASK_DATE_WEEK ((uint32_t)0x80000000) /*!< ertc alarm don't match date or week */ #define ERTC_ALARM_MASK_ALL ((uint32_t)0x80808080) /*!< ertc alarm don't match all */ +/** + * @brief compatible with older versions + */ +#define ERTC_WAT_CLK_CK_A_16BITS ERTC_WAT_CLK_CK_B_16BITS +#define ERTC_WAT_CLK_CK_A_17BITS ERTC_WAT_CLK_CK_B_17BITS + /** * @} */ @@ -167,8 +171,8 @@ typedef enum ERTC_WAT_CLK_ERTCCLK_DIV8 = 0x01, /*!< the wake up timer clock is ERTC_CLK / 8 */ ERTC_WAT_CLK_ERTCCLK_DIV4 = 0x02, /*!< the wake up timer clock is ERTC_CLK / 4 */ ERTC_WAT_CLK_ERTCCLK_DIV2 = 0x03, /*!< the wake up timer clock is ERTC_CLK / 2 */ - ERTC_WAT_CLK_CK_A_16BITS = 0x04, /*!< the wake up timer clock is CK_A, wakeup counter = ERTC_WAT */ - ERTC_WAT_CLK_CK_A_17BITS = 0x06 /*!< the wake up timer clock is CK_A, wakeup counter = ERTC_WAT + 65535 */ + ERTC_WAT_CLK_CK_B_16BITS = 0x04, /*!< the wake up timer clock is CK_B, wakeup counter = ERTC_WAT */ + ERTC_WAT_CLK_CK_B_17BITS = 0x06 /*!< the wake up timer clock is CK_B, wakeup counter = ERTC_WAT + 65535 */ } ertc_wakeup_clock_type; /** @@ -1176,6 +1180,7 @@ void ertc_tamper_enable(ertc_tamper_select_type tamper_x, confirm_state new_stat void ertc_interrupt_enable(uint32_t source, confirm_state new_state); flag_status ertc_interrupt_get(uint32_t source); flag_status ertc_flag_get(uint32_t flag); +flag_status ertc_interrupt_flag_get(uint32_t flag); void ertc_flag_clear(uint32_t flag); void ertc_bpr_data_write(ertc_dt_type dt, uint32_t data); uint32_t ertc_bpr_data_read(ertc_dt_type dt); diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_exint.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_exint.h index fe25afa692..ec3b73399a 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_exint.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_exint.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_exint.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 exint header file ************************************************************************** * Copyright notice & Disclaimer @@ -211,6 +209,7 @@ void exint_default_para_init(exint_init_type *exint_struct); void exint_init(exint_init_type *exint_struct); void exint_flag_clear(uint32_t exint_line); flag_status exint_flag_get(uint32_t exint_line); +flag_status exint_interrupt_flag_get(uint32_t exint_line); void exint_software_interrupt_event_generate(uint32_t exint_line); void exint_interrupt_enable(uint32_t exint_line, confirm_state new_state); void exint_event_enable(uint32_t exint_line, confirm_state new_state); diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_flash.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_flash.h index 19cf2d83f7..7b3e7f3df5 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_flash.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_flash.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_flash.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 flash header file ************************************************************************** * Copyright notice & Disclaimer diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_gpio.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_gpio.h index c6b487d505..0e8d91a702 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_gpio.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_gpio.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_gpio.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 gpio header file ************************************************************************** * Copyright notice & Disclaimer @@ -541,7 +539,7 @@ uint16_t gpio_output_data_read(gpio_type *gpio_x); void gpio_bits_set(gpio_type *gpio_x, uint16_t pins); void gpio_bits_reset(gpio_type *gpio_x, uint16_t pins); void gpio_bits_write(gpio_type *gpio_x, uint16_t pins, confirm_state bit_state); -void gpio_port_wirte(gpio_type *gpio_x, uint16_t port_value); +void gpio_port_write(gpio_type *gpio_x, uint16_t port_value); void gpio_pin_wp_config(gpio_type *gpio_x, uint16_t pins); void gpio_pins_huge_driven_config(gpio_type *gpio_x, uint16_t pins, confirm_state new_state); void gpio_pin_mux_config(gpio_type *gpio_x, gpio_pins_source_type gpio_pin_source, gpio_mux_sel_type gpio_mux); diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_i2c.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_i2c.h index cdab00e6fe..0d2e3ba653 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_i2c.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_i2c.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_i2c.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 i2c header file ************************************************************************** * Copyright notice & Disclaimer @@ -157,12 +155,12 @@ typedef enum { I2C_ADDR2_NOMASK = 0x00, /*!< compare bit [7:1] */ I2C_ADDR2_MASK01 = 0x01, /*!< only compare bit [7:2] */ - I2C_ADDR2_MASK02 = 0x02, /*!< only compare bit [7:2] */ - I2C_ADDR2_MASK03 = 0x03, /*!< only compare bit [7:3] */ - I2C_ADDR2_MASK04 = 0x04, /*!< only compare bit [7:4] */ - I2C_ADDR2_MASK05 = 0x05, /*!< only compare bit [7:5] */ - I2C_ADDR2_MASK06 = 0x06, /*!< only compare bit [7:6] */ - I2C_ADDR2_MASK07 = 0x07 /*!< only compare bit [7] */ + I2C_ADDR2_MASK02 = 0x02, /*!< only compare bit [7:3] */ + I2C_ADDR2_MASK03 = 0x03, /*!< only compare bit [7:4] */ + I2C_ADDR2_MASK04 = 0x04, /*!< only compare bit [7:5] */ + I2C_ADDR2_MASK05 = 0x05, /*!< only compare bit [7:6] */ + I2C_ADDR2_MASK06 = 0x06, /*!< only compare bit [7] */ + I2C_ADDR2_MASK07 = 0x07 /*!< response all addresses other than those reserved for i2c */ } i2c_addr2_mask_type; /** @@ -176,14 +174,14 @@ typedef enum } i2c_reload_stop_mode_type; /** - * @brief i2c start stop mode + * @brief i2c start mode */ typedef enum { I2C_WITHOUT_START = 0x00000000, /*!< transfer data without start condition */ I2C_GEN_START_READ = 0x00002400, /*!< read data and generate start */ I2C_GEN_START_WRITE = 0x00002000 /*!< send data and generate start */ -} i2c_start_stop_mode_type; +} i2c_start_mode_type; /** * @brief type define i2c register all @@ -452,12 +450,13 @@ void i2c_ext_timeout_enable(i2c_type *i2c_x, confirm_state new_state); void i2c_interrupt_enable(i2c_type *i2c_x, uint32_t source, confirm_state new_state); flag_status i2c_interrupt_get(i2c_type *i2c_x, uint16_t source); void i2c_dma_enable(i2c_type *i2c_x, i2c_dma_request_type dma_req, confirm_state new_state); -void i2c_transmit_set(i2c_type *i2c_x, uint16_t address, uint8_t cnt, i2c_reload_stop_mode_type rld_stop, i2c_start_stop_mode_type start_stop); +void i2c_transmit_set(i2c_type *i2c_x, uint16_t address, uint8_t cnt, i2c_reload_stop_mode_type rld_stop, i2c_start_mode_type start); void i2c_start_generate(i2c_type *i2c_x); void i2c_stop_generate(i2c_type *i2c_x); void i2c_data_send(i2c_type *i2c_x, uint8_t data); uint8_t i2c_data_receive(i2c_type *i2c_x); flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag); +flag_status i2c_interrupt_flag_get(i2c_type *i2c_x, uint32_t flag); void i2c_flag_clear(i2c_type *i2c_x, uint32_t flag); /** diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_misc.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_misc.h index 9d14517952..6189983be7 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_misc.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_misc.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_misc.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 misc header file ************************************************************************** * Copyright notice & Disclaimer @@ -76,9 +74,9 @@ typedef enum */ typedef enum { - NVIC_LP_SLEEPONEXIT = 0x02, /*!< send event on pending */ + NVIC_LP_SLEEPONEXIT = 0x02, /*!< enable sleep-on-exit feature */ NVIC_LP_SLEEPDEEP = 0x04, /*!< enable sleep-deep output signal when entering sleep mode */ - NVIC_LP_SEVONPEND = 0x10 /*!< enable sleep-on-exit feature */ + NVIC_LP_SEVONPEND = 0x10 /*!< send event on pending */ } nvic_lowpower_mode_type; /** diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_pwc.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_pwc.h index 0d302a43a6..c9e731cb36 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_pwc.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_pwc.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_pwc.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 pwr header file ************************************************************************** * Copyright notice & Disclaimer @@ -60,17 +58,19 @@ extern "C" { /** * @brief pwc wakeup pin num definition */ -#define PWC_WAKEUP_PIN_1 ((uint32_t)0x00000100) /*!< standby wake-up pin1 */ -#define PWC_WAKEUP_PIN_2 ((uint32_t)0x00000200) /*!< standby wake-up pin2 */ +#define PWC_WAKEUP_PIN_1 ((uint32_t)0x00000100) /*!< standby wake-up pin1(pa0) */ +#define PWC_WAKEUP_PIN_2 ((uint32_t)0x00000200) /*!< standby wake-up pin2(pc13) */ /** * @brief select ldo output voltage. * @param val: set the ldo output voltage. * this parameter can be one of the following values: - * - PWC_LDO_OUTPUT_1V2 - * - PWC_LDO_OUTPUT_1V3 - * - PWC_LDO_OUTPUT_1V1 - * - PWC_LDO_OUTPUT_1V0 + * - PWC_LDO_OUTPUT_1V3: system clock up to 288MHz. + * - PWC_LDO_OUTPUT_1V2: system clock up to 240MHz. + * - PWC_LDO_OUTPUT_1V1: system clock up to 192MHz. + * - PWC_LDO_OUTPUT_1V0: system clock up to 144MHz. + * @note useage limited. + * PWC_LDO_OUTPUT_1V3: operation temperature range -40~85 degree, VDD must over 3.0V. */ #define pwc_ldo_output_voltage_set(val) (PWC->ldoov_bit.ldoovsel = val) @@ -97,8 +97,8 @@ typedef enum */ typedef enum { - PWC_LDO_OUTPUT_1V2 = 0x00, /*!< ldo output voltage is 1.2v */ PWC_LDO_OUTPUT_1V3 = 0x01, /*!< ldo output voltage is 1.3v */ + PWC_LDO_OUTPUT_1V2 = 0x00, /*!< ldo output voltage is 1.2v */ PWC_LDO_OUTPUT_1V1 = 0x04, /*!< ldo output voltage is 1.1v */ PWC_LDO_OUTPUT_1V0 = 0x05, /*!< ldo output voltage is 1.0v */ } pwc_ldo_output_voltage_type; diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_qspi.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_qspi.h index 4cd235ec1c..02df07778b 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_qspi.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_qspi.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_qspi.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 qspi header file ************************************************************************** * Copyright notice & Disclaimer @@ -123,11 +121,11 @@ typedef enum typedef enum { QSPI_CLK_DIV_2 = 0x00, /*!< qspi clk divide by 2 */ + QSPI_CLK_DIV_3 = 0x04, /*!< qspi clk divide by 3 */ QSPI_CLK_DIV_4 = 0x01, /*!< qspi clk divide by 4 */ + QSPI_CLK_DIV_5 = 0x05, /*!< qspi clk divide by 5 */ QSPI_CLK_DIV_6 = 0x02, /*!< qspi clk divide by 6 */ QSPI_CLK_DIV_8 = 0x03, /*!< qspi clk divide by 8 */ - QSPI_CLK_DIV_3 = 0x04, /*!< qspi clk divide by 3 */ - QSPI_CLK_DIV_5 = 0x05, /*!< qspi clk divide by 5 */ QSPI_CLK_DIV_10 = 0x06, /*!< qspi clk divide by 10 */ QSPI_CLK_DIV_12 = 0x07 /*!< qspi clk divide by 12 */ } qspi_clk_div_type; @@ -179,7 +177,7 @@ typedef enum { QSPI_DMA_FIFO_THOD_WORD08 = 0x00, /*!< qspi dma fifo threshold 8 words */ QSPI_DMA_FIFO_THOD_WORD16 = 0x01, /*!< qspi dma fifo threshold 16 words */ - QSPI_DMA_FIFO_THOD_WORD32 = 0x02 /*!< qspi dma fifo threshold 32 words */ + QSPI_DMA_FIFO_THOD_WORD24 = 0x02 /*!< qspi dma fifo threshold 24 words */ } qspi_dma_fifo_thod_type; /** @@ -187,7 +185,7 @@ typedef enum */ typedef struct { - confirm_state pe_mode_enable; /*!< perfornance enhance mode enable */ + confirm_state pe_mode_enable; /*!< performance enhance mode enable */ uint8_t pe_mode_operate_code; /*!< performance enhance mode operate code */ uint8_t instruction_code; /*!< instruction code */ qspi_cmd_inslen_type instruction_length; /*!< instruction code length */ @@ -314,17 +312,9 @@ typedef struct }; /** - * @brief qspi actr register, offset:0x14 + * @brief qspi register, offset:0x14 */ - union - { - __IO uint32_t actr; - struct - { - __IO uint32_t csdly : 4; /* [3:0] */ - __IO uint32_t reserved1 : 28;/* [31:4] */ - } actr_bit; - }; + __IO uint32_t reserved0; /** * @brief qspi fifosts register, offset:0x18 @@ -441,12 +431,12 @@ typedef struct __IO uint32_t xip_cmd_w2; struct { - __IO uint32_t xipr_dcnt : 6; /* [5:0] */ - __IO uint32_t reserved1 : 2; /* [7:6] */ + __IO uint32_t xipr_dcnt : 5; /* [4:0] */ + __IO uint32_t reserved1 : 3; /* [7:5] */ __IO uint32_t xipr_tcnt : 7; /* [14:8] */ __IO uint32_t xipr_sel : 1; /* [15] */ - __IO uint32_t xipw_dcnt : 6; /* [21:16] */ - __IO uint32_t reserved2 : 2; /* [23:22] */ + __IO uint32_t xipw_dcnt : 5; /* [20:16] */ + __IO uint32_t reserved2 : 3; /* [23:21] */ __IO uint32_t xipw_tcnt : 7; /* [30:24] */ __IO uint32_t xipw_sel : 1; /* [31] */ } xip_cmd_w2_bit; @@ -468,9 +458,24 @@ typedef struct }; /** - * @brief qspi reserved register, offset:0x40~4C + * @brief qspi ctrl3 register, offset:0x40 */ - __IO uint32_t reserved2[4]; + union + { + __IO uint32_t ctrl3; + struct + { + __IO uint32_t ispd : 6; /* [5:0] */ + __IO uint32_t reserved1 : 2; /* [7:6] */ + __IO uint32_t ispc : 1; /* [8] */ + __IO uint32_t reserved2 : 23;/* [31:9] */ + } ctrl3_bit; + }; + + /** + * @brief qspi reserved register, offset:0x44~4C + */ + __IO uint32_t reserved2[3]; /** * @brief qspi rev register, offset:0x50 @@ -516,13 +521,15 @@ typedef struct * @{ */ +void qspi_reset(qspi_type* qspi_x); void qspi_encryption_enable(qspi_type* qspi_x, confirm_state new_state); -void qspi_sck_mode_set( qspi_type* qspi_x, qspi_clk_mode_type new_mode); +void qspi_sck_mode_set(qspi_type* qspi_x, qspi_clk_mode_type new_mode); void qspi_clk_division_set(qspi_type* qspi_x, qspi_clk_div_type new_clkdiv); void qspi_xip_cache_bypass_set(qspi_type* qspi_x, confirm_state new_state); void qspi_interrupt_enable(qspi_type* qspi_x, confirm_state new_state); flag_status qspi_flag_get(qspi_type* qspi_x, uint32_t flag); -void qspi_flag_clear( qspi_type* qspi_x, uint32_t flag); +flag_status qspi_interrupt_flag_get(qspi_type* qspi_x, uint32_t flag); +void qspi_flag_clear(qspi_type* qspi_x, uint32_t flag); void qspi_dma_rx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_threshold); void qspi_dma_tx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_threshold); void qspi_dma_enable(qspi_type* qspi_x, confirm_state new_state); @@ -536,6 +543,7 @@ uint32_t qspi_word_read(qspi_type* qspi_x); void qspi_word_write(qspi_type* qspi_x, uint32_t value); void qspi_half_word_write(qspi_type* qspi_x, uint16_t value); void qspi_byte_write(qspi_type* qspi_x, uint8_t value); +void qspi_auto_ispc_enable(qspi_type* qspi_x); /** * @} */ diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_scfg.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_scfg.h index 0c221880ca..1e11bf36dc 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_scfg.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_scfg.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_scfg.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 system config header file ************************************************************************** * Copyright notice & Disclaimer @@ -57,9 +55,9 @@ extern "C" { typedef enum { SCFG_XMC_SWAP_NONE = 0x00, /* no swap */ - SCFG_XMC_SWAP_MODE1 = 0x01, /* sdram nor psram sram nand2 swap */ - SCFG_XMC_SWAP_MODE2 = 0x02, /* nand3 qspi2 swap */ - SCFG_XMC_SWAP_MODE3 = 0x03 /* sdram nor psram sram nand2 nand3 qspi2 swap */ + SCFG_XMC_SWAP_MODE1 = 0x01, /* sdram 0x60000000 and 0x70000000, nor psram sram nand2 0xC00000000 and 0xD0000000 */ + SCFG_XMC_SWAP_MODE2 = 0x02, /* qspi2 0x80000000, nand3 0xB0000000 */ + SCFG_XMC_SWAP_MODE3 = 0x03 /* sdram 0x60000000 and 0x70000000, nor psram sram nand2 0xC00000000 and 0xD0000000, qspi2 0x80000000, nand3 0xB0000000 */ } scfg_xmc_swap_type; /** @@ -67,9 +65,7 @@ typedef enum */ typedef enum { - SCFG_IR_SOURCE_TMR10 = 0x00, /* infrared signal source select tmr10 */ - SCFG_IR_SOURCE_USART1 = 0x01, /* infrared signal source select usart1 */ - SCFG_IR_SOURCE_USART2 = 0x02 /* infrared signal source select usart2 */ + SCFG_IR_SOURCE_TMR10 = 0x00 /* infrared signal source select tmr10 */ } scfg_ir_source_type; /** diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_sdio.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_sdio.h index 33d5ca76f5..c78803e777 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_sdio.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_sdio.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_sdio.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 sdio header file ************************************************************************** * Copyright notice & Disclaimer @@ -578,7 +576,7 @@ typedef struct void sdio_reset(sdio_type *sdio_x); void sdio_power_set(sdio_type *sdio_x, sdio_power_state_type power_state); -flag_status sdio_power_status_get(sdio_type *sdio_x); +sdio_power_state_type sdio_power_status_get(sdio_type *sdio_x); void sdio_clock_config(sdio_type *sdio_x, uint16_t clk_div, sdio_edge_phase_type clk_edg); void sdio_bus_width_config(sdio_type *sdio_x, sdio_bus_width_type width); void sdio_clock_bypass(sdio_type *sdio_x, confirm_state new_state); @@ -588,6 +586,7 @@ void sdio_clock_enable(sdio_type *sdio_x, confirm_state new_state); void sdio_dma_enable(sdio_type *sdio_x, confirm_state new_state); void sdio_interrupt_enable(sdio_type *sdio_x, uint32_t int_opt, confirm_state new_state); flag_status sdio_flag_get(sdio_type *sdio_x, uint32_t flag); +flag_status sdio_interrupt_flag_get(sdio_type *sdio_x, uint32_t flag); void sdio_flag_clear(sdio_type *sdio_x, uint32_t flag); void sdio_command_config(sdio_type *sdio_x, sdio_command_struct_type *command_struct); void sdio_command_state_machine_enable(sdio_type *sdio_x, confirm_state new_state); diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_spi.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_spi.h index d28b3d90d6..ae99b541bd 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_spi.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_spi.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_spi.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 spi header file ************************************************************************** * Copyright notice & Disclaimer @@ -484,6 +482,7 @@ void spi_i2s_dma_receiver_enable(spi_type* spi_x, confirm_state new_state); void spi_i2s_data_transmit(spi_type* spi_x, uint16_t tx_data); uint16_t spi_i2s_data_receive(spi_type* spi_x); flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag); +flag_status spi_i2s_interrupt_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag); void spi_i2s_flag_clear(spi_type* spi_x, uint32_t spi_i2s_flag); /** diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_tmr.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_tmr.h index de800e971a..488dba8d5a 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_tmr.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_tmr.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_tmr.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 tmr header file ************************************************************************** * Copyright notice & Disclaimer @@ -54,6 +52,7 @@ extern "C" { #define TMR_C2_FLAG ((uint32_t)0x000004) /*!< tmr flag channel 2 */ #define TMR_C3_FLAG ((uint32_t)0x000008) /*!< tmr flag channel 3 */ #define TMR_C4_FLAG ((uint32_t)0x000010) /*!< tmr flag channel 4 */ +#define TMR_C5_FLAG ((uint32_t)0x010000) /*!< tmr flag channel 5 */ #define TMR_HALL_FLAG ((uint32_t)0x000020) /*!< tmr flag hall */ #define TMR_TRIGGER_FLAG ((uint32_t)0x000040) /*!< tmr flag trigger */ #define TMR_BRK_FLAG ((uint32_t)0x000080) /*!< tmr flag brake */ @@ -239,7 +238,7 @@ typedef enum { TMR_CC_CHANNEL_MAPPED_DIRECT = 0x01, /*!< channel is configured as input, mapped direct */ TMR_CC_CHANNEL_MAPPED_INDIRECT = 0x02, /*!< channel is configured as input, mapped indirect */ - TMR_CC_CHANNEL_MAPPED_STI = 0x03 /*!< channel is configured as input, mapped trc */ + TMR_CC_CHANNEL_MAPPED_STI = 0x03 /*!< channel is configured as input, mapped sti */ } tmr_input_direction_mapped_type; /** @@ -291,17 +290,6 @@ typedef enum TMR_BRK_SWTRIG = 0x00000080 /*!< tmr event triggered by software of brake */ }tmr_event_trigger_type; -/** - * @brief tmr channel output fast type - */ -typedef enum -{ - TMR_CHANNEL1_OUTPUT_FAST = MAKE_VALUE(0x18, 2), /*!< tmr channel 1 output fast mode */ - TMR_CHANNEL2_OUTPUT_FAST = MAKE_VALUE(0x18, 10), /*!< tmr channel 2 output fast mode */ - TMR_CHANNEL3_OUTPUT_FAST = MAKE_VALUE(0x1c, 2), /*!< tmr channel 3 output fast mode */ - TMR_CHANNEL4_OUTPUT_FAST = MAKE_VALUE(0x1c, 10) /*!< tmr channel 4 output fast mode */ -}tmr_channel_output_fast_type; - /** * @brief tmr polarity active type */ @@ -930,7 +918,7 @@ void tmr_brkdt_default_para_init(tmr_brkdt_config_type *tmr_brkdt_struct); void tmr_base_init(tmr_type* tmr_x, uint32_t tmr_pr, uint32_t tmr_div); void tmr_clock_source_div_set(tmr_type *tmr_x, tmr_clock_division_type tmr_clock_div); void tmr_cnt_dir_set(tmr_type *tmr_x, tmr_count_mode_type tmr_cnt_dir); -void tmr_repetition_counter_set(tmr_type *tmr_x, uint8_t tmr_rpr_value); +void tmr_repetition_counter_set(tmr_type *tmr_x, uint16_t tmr_rpr_value); void tmr_counter_value_set(tmr_type *tmr_x, uint32_t tmr_cnt_value); uint32_t tmr_counter_value_get(tmr_type *tmr_x); void tmr_div_value_set(tmr_type *tmr_x, uint32_t tmr_div_value); @@ -962,7 +950,7 @@ void tmr_input_channel_filter_set(tmr_type *tmr_x, tmr_channel_select_type tmr_c uint16_t filter_value); void tmr_pwm_input_config(tmr_type *tmr_x, tmr_input_config_type *input_struct, \ tmr_channel_input_divider_type divider_factor); -void tmr_channel1_input_select(tmr_type *tmr_x, tmr_channel1_input_connected_type ti1_connect); +void tmr_channel1_input_select(tmr_type *tmr_x, tmr_channel1_input_connected_type ch1_connect); void tmr_input_channel_divider_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \ tmr_channel_input_divider_type divider_factor); void tmr_primary_mode_select(tmr_type *tmr_x, tmr_primary_select_type primary_mode); @@ -975,12 +963,12 @@ void tmr_trigger_input_select(tmr_type *tmr_x, sub_tmr_input_sel_type trigger_se void tmr_sub_sync_mode_set(tmr_type *tmr_x, confirm_state new_state); void tmr_dma_request_enable(tmr_type *tmr_x, tmr_dma_request_type dma_request, confirm_state new_state); void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state new_state); +flag_status tmr_interrupt_flag_get(tmr_type *tmr_x, uint32_t tmr_flag); flag_status tmr_flag_get(tmr_type *tmr_x, uint32_t tmr_flag); void tmr_flag_clear(tmr_type *tmr_x, uint32_t tmr_flag); void tmr_event_sw_trigger(tmr_type *tmr_x, tmr_event_trigger_type tmr_event); void tmr_output_enable(tmr_type *tmr_x, confirm_state new_state); void tmr_internal_clock_set(tmr_type *tmr_x); -void tmr_output_channel_fast_set(tmr_type *tmr_x, tmr_channel_output_fast_type oc_fast); void tmr_output_channel_polarity_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \ tmr_polarity_active_type oc_polarity); void tmr_external_clock_config(tmr_type *tmr_x, tmr_external_signal_divider_type es_divide, \ diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_usart.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_usart.h index 4416c3a61d..9ac1bb87db 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_usart.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_usart.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_usart.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 usart header file ************************************************************************** * Copyright notice & Disclaimer @@ -352,7 +350,10 @@ typedef struct #define UART5 ((usart_type *) UART5_BASE) #define USART6 ((usart_type *) USART6_BASE) #define UART7 ((usart_type *) UART7_BASE) +#if defined (AT32F435Zx) || defined (AT32F435Vx) || defined (AT32F435Rx) || \ + defined (AT32F437Zx) || defined (AT32F437Vx) || defined (AT32F437Rx) #define UART8 ((usart_type *) UART8_BASE) +#endif /** @defgroup USART_exported_functions * @{ @@ -386,6 +387,7 @@ void usart_irda_mode_enable(usart_type* usart_x, confirm_state new_state); void usart_irda_low_power_enable(usart_type* usart_x, confirm_state new_state); void usart_hardware_flow_control_set(usart_type* usart_x,usart_hardware_flow_control_type flow_state); flag_status usart_flag_get(usart_type* usart_x, uint32_t flag); +flag_status usart_interrupt_flag_get(usart_type* usart_x, uint32_t flag); void usart_flag_clear(usart_type* usart_x, uint32_t flag); void usart_rs485_delay_time_config(usart_type* usart_x, uint8_t start_delay_time, uint8_t complete_delay_time); void usart_transmit_receive_pin_swap(usart_type* usart_x, confirm_state new_state); diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_usb.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_usb.h index 9e41b14cb9..2e5c0b0d40 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_usb.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_usb.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_usb.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 usb header file ************************************************************************** * Copyright notice & Disclaimer @@ -707,6 +705,7 @@ typedef struct __IO uint32_t nptxfspcavail : 16; /* [15:0] */ __IO uint32_t nptxqspcavail : 8; /* [23:16] */ __IO uint32_t nptxqtop : 7; /* [30:24] */ + __IO uint32_t reserved1 : 1; /* [31] */ } gnptxsts_bit; }; diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_wdt.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_wdt.h index 2b823eee1b..5cc24927e8 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_wdt.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_wdt.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_wdt.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 wdt header file ************************************************************************** * Copyright notice & Disclaimer diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_wwdt.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_wwdt.h index d8a572372e..f73217702e 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_wwdt.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_wwdt.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_wwdt.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 wwdt header file ************************************************************************** * Copyright notice & Disclaimer @@ -136,6 +134,7 @@ void wwdt_flag_clear(void); void wwdt_enable(uint8_t wwdt_cnt); void wwdt_interrupt_enable(void); flag_status wwdt_flag_get(void); +flag_status wwdt_interrupt_flag_get(void); void wwdt_counter_set(uint8_t wwdt_cnt); void wwdt_window_counter_set(uint8_t window_cnt); diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_xmc.h b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_xmc.h index 7d3b9e68dc..398ddb2893 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_xmc.h +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/inc/at32f435_437_xmc.h @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_xmc.h - * @version v2.0.8 - * @date 2022-04-25 * @brief at32f435_437 xmc header file ************************************************************************** * Copyright notice & Disclaimer @@ -605,7 +603,7 @@ typedef struct xmc_bank1_tmgwr_reg_type tmgwr_group[4]; /** - * @brief xmc bank1 reserved register, offset:0x120~0x21C + * @brief xmc bank1 reserved register, offset:0x120~0x220 */ __IO uint32_t reserved2[63]; @@ -1024,7 +1022,7 @@ void xmc_norsram_default_para_init(xmc_norsram_init_type* xmc_nor_sram_init_stru void xmc_norsram_timing_default_para_init(xmc_norsram_timing_init_type* xmc_rw_timing_struct, xmc_norsram_timing_init_type* xmc_w_timing_struct); void xmc_nor_sram_enable(xmc_nor_sram_subbank_type xmc_subbank, confirm_state new_state); -void xmc_ext_timing_config(xmc_nor_sram_subbank_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing); +void xmc_ext_timing_config(volatile xmc_nor_sram_subbank_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing); void xmc_nand_reset(xmc_class_bank_type xmc_bank); void xmc_nand_init(xmc_nand_init_type* xmc_nand_init_struct); void xmc_nand_timing_config(xmc_nand_pccard_timinginit_type* xmc_common_spacetiming_struct, @@ -1037,6 +1035,7 @@ void xmc_nand_ecc_enable(xmc_class_bank_type xmc_bank, confirm_state new_state); uint32_t xmc_ecc_get(xmc_class_bank_type xmc_bank); void xmc_interrupt_enable(xmc_class_bank_type xmc_bank, xmc_interrupt_sources_type xmc_int, confirm_state new_state); flag_status xmc_flag_status_get(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag); +flag_status xmc_interrupt_flag_status_get(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag); void xmc_flag_clear(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag); void xmc_pccard_reset(void); void xmc_pccard_init(xmc_pccard_init_type* xmc_pccard_init_struct); diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_acc.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_acc.c index 69a3ae74ee..7c1cdcedfb 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_acc.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_acc.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_acc.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the acc firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -203,6 +201,23 @@ flag_status acc_flag_get(uint16_t acc_flag) return (flag_status)(ACC->sts_bit.rslost); } +/** + * @brief check whether the specified acc interrupt flag is set or not. + * @param acc_flag: specifies the flag to check. + * this parameter can be one of the following values: + * - ACC_RSLOST_FLAG + * - ACC_CALRDY_FLAG + * @retval flag_status (SET or RESET) + */ +flag_status acc_interrupt_flag_get(uint16_t acc_flag) +{ + if(acc_flag == ACC_CALRDY_FLAG) + return (flag_status)(ACC->sts_bit.calrdy && ACC->ctrl1_bit.calrdyien); + else + return (flag_status)(ACC->sts_bit.rslost && ACC->ctrl1_bit.eien); +} + + /** * @brief clear the specified acc flag is set or not. * @param acc_flag: specifies the flag to check. diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_adc.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_adc.c index 5ca6d054bc..53eb738e11 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_adc.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_adc.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_adc.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the adc firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -78,7 +76,7 @@ void adc_enable(adc_type *adc_x, confirm_state new_state) * - ADC_LEFT_ALIGNMENT * @param ordinary_channel_length: configure the adc ordinary channel sequence length. * this parameter can be: - * - (0x1~0xf) + * - (0x1~0x10) * @retval none */ void adc_base_default_para_init(adc_base_config_type *adc_base_struct) @@ -104,7 +102,7 @@ void adc_base_default_para_init(adc_base_config_type *adc_base_struct) * - ADC_LEFT_ALIGNMENT * @param ordinary_channel_length: configure the adc ordinary channel sequence length. * this parameter can be: - * - (0x1~0xf) + * - (0x1~0x10) * @retval none */ void adc_base_config(adc_type *adc_x, adc_base_config_type *adc_base_struct) @@ -471,120 +469,42 @@ void adc_voltage_monitor_single_channel_select(adc_type *adc_x, adc_channel_sele */ void adc_ordinary_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime) { - switch(adc_channel) + uint32_t tmp_reg; + if(adc_channel < ADC_CHANNEL_10) { - case ADC_CHANNEL_0: - adc_x->spt2_bit.cspt0 = adc_sampletime; - break; - case ADC_CHANNEL_1: - adc_x->spt2_bit.cspt1 = adc_sampletime; - break; - case ADC_CHANNEL_2: - adc_x->spt2_bit.cspt2 = adc_sampletime; - break; - case ADC_CHANNEL_3: - adc_x->spt2_bit.cspt3 = adc_sampletime; - break; - case ADC_CHANNEL_4: - adc_x->spt2_bit.cspt4 = adc_sampletime; - break; - case ADC_CHANNEL_5: - adc_x->spt2_bit.cspt5 = adc_sampletime; - break; - case ADC_CHANNEL_6: - adc_x->spt2_bit.cspt6 = adc_sampletime; - break; - case ADC_CHANNEL_7: - adc_x->spt2_bit.cspt7 = adc_sampletime; - break; - case ADC_CHANNEL_8: - adc_x->spt2_bit.cspt8 = adc_sampletime; - break; - case ADC_CHANNEL_9: - adc_x->spt2_bit.cspt9 = adc_sampletime; - break; - case ADC_CHANNEL_10: - adc_x->spt1_bit.cspt10 = adc_sampletime; - break; - case ADC_CHANNEL_11: - adc_x->spt1_bit.cspt11 = adc_sampletime; - break; - case ADC_CHANNEL_12: - adc_x->spt1_bit.cspt12 = adc_sampletime; - break; - case ADC_CHANNEL_13: - adc_x->spt1_bit.cspt13 = adc_sampletime; - break; - case ADC_CHANNEL_14: - adc_x->spt1_bit.cspt14 = adc_sampletime; - break; - case ADC_CHANNEL_15: - adc_x->spt1_bit.cspt15 = adc_sampletime; - break; - case ADC_CHANNEL_16: - adc_x->spt1_bit.cspt16 = adc_sampletime; - break; - case ADC_CHANNEL_17: - adc_x->spt1_bit.cspt17 = adc_sampletime; - break; - case ADC_CHANNEL_18: - adc_x->spt1_bit.cspt18 = adc_sampletime; - break; - default: - break; + tmp_reg = adc_x->spt2; + tmp_reg &= ~(0x07 << 3 * adc_channel); + tmp_reg |= adc_sampletime << 3 * adc_channel; + adc_x->spt2 = tmp_reg; } - switch(adc_sequence) + else { - case 1: - adc_x->osq3_bit.osn1 = adc_channel; - break; - case 2: - adc_x->osq3_bit.osn2 = adc_channel; - break; - case 3: - adc_x->osq3_bit.osn3 = adc_channel; - break; - case 4: - adc_x->osq3_bit.osn4 = adc_channel; - break; - case 5: - adc_x->osq3_bit.osn5 = adc_channel; - break; - case 6: - adc_x->osq3_bit.osn6 = adc_channel; - break; - case 7: - adc_x->osq2_bit.osn7 = adc_channel; - break; - case 8: - adc_x->osq2_bit.osn8 = adc_channel; - break; - case 9: - adc_x->osq2_bit.osn9 = adc_channel; - break; - case 10: - adc_x->osq2_bit.osn10 = adc_channel; - break; - case 11: - adc_x->osq2_bit.osn11 = adc_channel; - break; - case 12: - adc_x->osq2_bit.osn12 = adc_channel; - break; - case 13: - adc_x->osq1_bit.osn13 = adc_channel; - break; - case 14: - adc_x->osq1_bit.osn14 = adc_channel; - break; - case 15: - adc_x->osq1_bit.osn15 = adc_channel; - break; - case 16: - adc_x->osq1_bit.osn16 = adc_channel; - break; - default: - break; + tmp_reg = adc_x->spt1; + tmp_reg &= ~(0x07 << 3 * (adc_channel - ADC_CHANNEL_10)); + tmp_reg |= adc_sampletime << 3 * (adc_channel - ADC_CHANNEL_10); + adc_x->spt1 = tmp_reg; + } + + if(adc_sequence >= 13) + { + tmp_reg = adc_x->osq1; + tmp_reg &= ~(0x01F << 5 * (adc_sequence - 13)); + tmp_reg |= adc_channel << 5 * (adc_sequence - 13); + adc_x->osq1 = tmp_reg; + } + else if(adc_sequence >= 7) + { + tmp_reg = adc_x->osq2; + tmp_reg &= ~(0x01F << 5 * (adc_sequence - 7)); + tmp_reg |= adc_channel << 5 * (adc_sequence - 7); + adc_x->osq2 = tmp_reg; + } + else + { + tmp_reg = adc_x->osq3; + tmp_reg &= ~(0x01F << 5 * (adc_sequence - 1)); + tmp_reg |= adc_channel << 5 * (adc_sequence - 1); + adc_x->osq3 = tmp_reg; } } @@ -632,69 +552,23 @@ void adc_preempt_channel_length_set(adc_type *adc_x, uint8_t adc_channel_lenght) */ void adc_preempt_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime) { - uint16_t sequence_index=0; - switch(adc_channel) + uint32_t tmp_reg; + uint8_t sequence_index; + if(adc_channel < ADC_CHANNEL_10) { - case ADC_CHANNEL_0: - adc_x->spt2_bit.cspt0 = adc_sampletime; - break; - case ADC_CHANNEL_1: - adc_x->spt2_bit.cspt1 = adc_sampletime; - break; - case ADC_CHANNEL_2: - adc_x->spt2_bit.cspt2 = adc_sampletime; - break; - case ADC_CHANNEL_3: - adc_x->spt2_bit.cspt3 = adc_sampletime; - break; - case ADC_CHANNEL_4: - adc_x->spt2_bit.cspt4 = adc_sampletime; - break; - case ADC_CHANNEL_5: - adc_x->spt2_bit.cspt5 = adc_sampletime; - break; - case ADC_CHANNEL_6: - adc_x->spt2_bit.cspt6 = adc_sampletime; - break; - case ADC_CHANNEL_7: - adc_x->spt2_bit.cspt7 = adc_sampletime; - break; - case ADC_CHANNEL_8: - adc_x->spt2_bit.cspt8 = adc_sampletime; - break; - case ADC_CHANNEL_9: - adc_x->spt2_bit.cspt9 = adc_sampletime; - break; - case ADC_CHANNEL_10: - adc_x->spt1_bit.cspt10 = adc_sampletime; - break; - case ADC_CHANNEL_11: - adc_x->spt1_bit.cspt11 = adc_sampletime; - break; - case ADC_CHANNEL_12: - adc_x->spt1_bit.cspt12 = adc_sampletime; - break; - case ADC_CHANNEL_13: - adc_x->spt1_bit.cspt13 = adc_sampletime; - break; - case ADC_CHANNEL_14: - adc_x->spt1_bit.cspt14 = adc_sampletime; - break; - case ADC_CHANNEL_15: - adc_x->spt1_bit.cspt15 = adc_sampletime; - break; - case ADC_CHANNEL_16: - adc_x->spt1_bit.cspt16 = adc_sampletime; - break; - case ADC_CHANNEL_17: - adc_x->spt1_bit.cspt17 = adc_sampletime; - break; - case ADC_CHANNEL_18: - adc_x->spt1_bit.cspt18 = adc_sampletime; - break; - default: - break; + tmp_reg = adc_x->spt2; + tmp_reg &= ~(0x07 << 3 * adc_channel); + tmp_reg |= adc_sampletime << 3 * adc_channel; + adc_x->spt2 = tmp_reg; } + else + { + tmp_reg = adc_x->spt1; + tmp_reg &= ~(0x07 << 3 * (adc_channel - ADC_CHANNEL_10)); + tmp_reg |= adc_sampletime << 3 * (adc_channel - ADC_CHANNEL_10); + adc_x->spt1 = tmp_reg; + } + sequence_index = adc_sequence + 3 - adc_x->psq_bit.pclen; switch(sequence_index) { @@ -978,6 +852,7 @@ flag_status adc_ordinary_software_trigger_status_get(adc_type *adc_x) void adc_preempt_software_trigger_enable(adc_type *adc_x, confirm_state new_state) { adc_x->ctrl2_bit.pcswtrg = new_state; + adc_x->ctrl2_bit.pcswtrg = FALSE; } /** @@ -1087,6 +962,54 @@ flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag) return status; } +/** + * @brief get interrupt flag of the specified adc peripheral. + * @param adc_x: select the adc peripheral. + * this parameter can be one of the following values: + * - ADC1, ADC2, ADC3. + * @param adc_flag: select the adc flag. + * this parameter can be one of the following values: + * - ADC_VMOR_FLAG + * - ADC_OCCE_FLAG + * - ADC_PCCE_FLAG + * - ADC_OCCO_FLAG + * @retval the new state of adc flag status(SET or RESET). + */ +flag_status adc_interrupt_flag_get(adc_type *adc_x, uint8_t adc_flag) +{ + flag_status status = RESET; + switch(adc_flag) + { + case ADC_VMOR_FLAG: + if(adc_x->sts_bit.vmor && adc_x->ctrl1_bit.vmorien) + { + status = SET; + } + break; + case ADC_OCCE_FLAG: + if(adc_x->sts_bit.occe && adc_x->ctrl1_bit.occeien) + { + status = SET; + } + break; + case ADC_PCCE_FLAG: + if(adc_x->sts_bit.pcce && adc_x->ctrl1_bit.pcceien) + { + status = SET; + } + break; + case ADC_OCCO_FLAG: + if(adc_x->sts_bit.occo && adc_x->ctrl1_bit.occoien) + { + status = SET; + } + break; + default: + break; + } + return status; +} + /** * @brief clear flag of the specified adc peripheral. * @param adc_x: select the adc peripheral. diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_can.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_can.c index e4df40f222..e1aa2d9021 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_can.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_can.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_can.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the can firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -933,6 +931,102 @@ void can_interrupt_enable(can_type* can_x, uint32_t can_int, confirm_state new_s } } +/** + * @brief get interrupt flag of the specified can peripheral. + * @param can_x: select the can peripheral. + * this parameter can be one of the following values: + * CAN1,CAN2. + * @param can_flag: select the flag. + * this parameter can be one of the following flags: + * - CAN_EAF_FLAG + * - CAN_EPF_FLAG + * - CAN_BOF_FLAG + * - CAN_ETR_FLAG + * - CAN_EOIF_FLAG + * - CAN_TM0TCF_FLAG + * - CAN_TM1TCF_FLAG + * - CAN_TM2TCF_FLAG + * - CAN_RF0MN_FLAG + * - CAN_RF0FF_FLAG + * - CAN_RF0OF_FLAG + * - CAN_RF1MN_FLAG + * - CAN_RF1FF_FLAG + * - CAN_RF1OF_FLAG + * - CAN_QDZIF_FLAG + * - CAN_EDZC_FLAG + * - CAN_TMEF_FLAG + * note:the state of CAN_EDZC_FLAG need to check dzc and edzif bit + * note:the state of CAN_TMEF_FLAG need to check rqc0,rqc1 and rqc2 bit + * @retval status of can_flag, the returned value can be:SET or RESET. + */ +flag_status can_interrupt_flag_get(can_type* can_x, uint32_t can_flag) +{ + flag_status bit_status = RESET; + flag_status int_status = RESET; + + switch(can_flag) + { + case CAN_EAF_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.eaien); + break; + case CAN_EPF_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.epien); + break; + case CAN_BOF_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.boien); + break; + case CAN_ETR_FLAG: + int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.etrien); + break; + case CAN_EOIF_FLAG: + int_status = (flag_status)can_x->inten_bit.eoien; + break; + case CAN_TM0TCF_FLAG: + case CAN_TM1TCF_FLAG: + case CAN_TM2TCF_FLAG: + int_status = (flag_status)can_x->inten_bit.tcien; + break; + case CAN_RF0MN_FLAG: + int_status = (flag_status)can_x->inten_bit.rf0mien; + break; + case CAN_RF0FF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf0fien; + break; + case CAN_RF0OF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf0oien; + break; + case CAN_RF1MN_FLAG: + int_status = (flag_status)can_x->inten_bit.rf1mien; + break; + case CAN_RF1FF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf1fien; + break; + case CAN_RF1OF_FLAG: + int_status = (flag_status)can_x->inten_bit.rf1oien; + break; + case CAN_QDZIF_FLAG: + int_status = (flag_status)can_x->inten_bit.qdzien; + break; + case CAN_EDZC_FLAG: + int_status = (flag_status)can_x->inten_bit.edzien; + break; + case CAN_TMEF_FLAG: + int_status = (flag_status)can_x->inten_bit.tcien; + break; + default: + int_status = RESET; + break; + } + + if(int_status != SET) + { + return RESET; + } + bit_status = can_flag_get(can_x, can_flag); + + return bit_status; +} + /** * @brief get flag of the specified can peripheral. * @param can_x: select the can peripheral. diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_crc.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_crc.c index 3d225cabea..1dd90c8358 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_crc.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_crc.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_crc.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the crc firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -106,7 +104,7 @@ void crc_common_data_set(uint8_t cdt_value) * @param none * @retval 8-bit value of the common data register */ -uint8_t crc_common_date_get(void) +uint8_t crc_common_data_get(void) { return (CRC->cdt_bit.cdt); } @@ -149,6 +147,52 @@ void crc_reverse_output_data_set(crc_reverse_output_type value) CRC->ctrl_bit.revod = value; } +/** + * @brief config crc polynomial value + * @param value + * 32-bit new data of crc poly value + * @retval none. + */ +void crc_poly_value_set(uint32_t value) +{ + CRC->poly = value; +} + +/** + * @brief return crc polynomial value + * @param none + * @retval 32-bit value of the polynomial value. + */ +uint32_t crc_poly_value_get(void) +{ + return (CRC->poly); +} + +/** + * @brief config crc polynomial data size + * @param size + * this parameter can be one of the following values: + * - CRC_POLY_SIZE_32B + * - CRC_POLY_SIZE_16B + * - CRC_POLY_SIZE_8B + * - CRC_POLY_SIZE_7B + * @retval none. + */ +void crc_poly_size_set(crc_poly_size_type size) +{ + CRC->ctrl_bit.poly_size = size; +} + +/** + * @brief return crc polynomial data size + * @param none + * @retval polynomial data size. + */ +crc_poly_size_type crc_poly_size_get(void) +{ + return (crc_poly_size_type)(CRC->ctrl_bit.poly_size); +} + /** * @} */ diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_crm.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_crm.c index 378aa9443a..de1eabb9fd 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_crm.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_crm.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_crm.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the crm firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -61,12 +59,12 @@ void crm_reset(void) /* wait sclk switch status */ while(CRM->cfg_bit.sclksts != CRM_SCLK_HICK); - /* reset cfg register, include sclk switch, ahbdiv, apb1div, apb2div, adcdiv, clkout bits */ - CRM->cfg = 0; - /* reset hexten, hextbyps, cfden and pllen bits */ CRM->ctrl &= ~(0x010D0000U); + /* reset cfg register, include sclk switch, ahbdiv, apb1div, apb2div, adcdiv, clkout bits */ + CRM->cfg = 0; + /* reset pllms pllns pllfr pllrcs bits */ CRM->pllcfg = 0x00033002U; @@ -135,6 +133,64 @@ flag_status crm_flag_get(uint32_t flag) return status; } +/** + * @brief get crm interrupt flag status + * @param flag + * this parameter can be one of the following values: + * - CRM_LICK_READY_INT_FLAG + * - CRM_LEXT_READY_INT_FLAG + * - CRM_HICK_READY_INT_FLAG + * - CRM_HEXT_READY_INT_FLAG + * - CRM_PLL_READY_INT_FLAG + * - CRM_CLOCK_FAILURE_INT_FLAG + * @retval flag_status (SET or RESET) + */ +flag_status crm_interrupt_flag_get(uint32_t flag) +{ + flag_status status = RESET; + switch(flag) + { + case CRM_LICK_READY_INT_FLAG: + if(CRM->clkint_bit.lickstblf && CRM->clkint_bit.lickstblien) + { + status = SET; + } + break; + case CRM_LEXT_READY_INT_FLAG: + if(CRM->clkint_bit.lextstblf && CRM->clkint_bit.lextstblien) + { + status = SET; + } + break; + case CRM_HICK_READY_INT_FLAG: + if(CRM->clkint_bit.hickstblf && CRM->clkint_bit.hickstblien) + { + status = SET; + } + break; + case CRM_HEXT_READY_INT_FLAG: + if(CRM->clkint_bit.hextstblf && CRM->clkint_bit.hextstblien) + { + status = SET; + } + break; + case CRM_PLL_READY_INT_FLAG: + if(CRM->clkint_bit.pllstblf && CRM->clkint_bit.pllstblien) + { + status = SET; + } + break; + case CRM_CLOCK_FAILURE_INT_FLAG: + if(CRM->clkint_bit.cfdf && CRM->ctrl_bit.cfden) + { + status = SET; + } + break; + } + + return status; +} + /** * @brief wait for hext stable * @param none @@ -282,6 +338,7 @@ void crm_periph_reset(crm_periph_reset_type value, confirm_state new_state) * - CRM_USART6_PERIPH_LOWPOWER - CRM_ADC1_PERIPH_LOWPOWER - CRM_ADC2_PERIPH_LOWPOWER - CRM_ADC3_PERIPH_LOWPOWER * - CRM_SPI1_PERIPH_LOWPOWER - CRM_SPI4_PERIPH_LOWPOWER - CRM_SCFG_PERIPH_LOWPOWER - CRM_TMR9_PERIPH_LOWPOWER * - CRM_TMR10_PERIPH_LOWPOWER - CRM_TMR11_PERIPH_LOWPOWER - CRM_TMR20_PERIPH_LOWPOWER - CRM_ACC_PERIPH_LOWPOWER + * - CRM_FLASH_PERIPH_LOWPOWER - CRM_SRAM1_PERIPH_LOWPOWER - CRM_SRAM2_PERIPH_LOWPOWER * @param new_state (TRUE or FALSE) * @retval none */ @@ -367,6 +424,7 @@ void crm_flag_clear(uint32_t flag) case CRM_LOWPOWER_RESET_FLAG: case CRM_ALL_RESET_FLAG: CRM->ctrlsts_bit.rstfc = TRUE; + while(CRM->ctrlsts_bit.rstfc == TRUE); break; case CRM_LICK_READY_INT_FLAG: CRM->clkint_bit.lickstblfc = TRUE; @@ -468,6 +526,7 @@ void crm_ahb_div_set(crm_ahb_div_type value) /** * @brief set crm apb1 division + * @note the maximum frequency of APB1/APB2 clock is 144 MHz * @param value * this parameter can be one of the following values: * - CRM_APB1_DIV_1 @@ -484,6 +543,7 @@ void crm_apb1_div_set(crm_apb1_div_type value) /** * @brief set crm apb2 division + * @note the maximum frequency of APB1/APB2 clock is 144 MHz * @param value * this parameter can be one of the following values: * - CRM_APB2_DIV_1 @@ -623,7 +683,7 @@ void crm_clkout_to_tmr10_enable(confirm_state new_state) * pll_ms * * pll_rcs_freq * pll_ns - * 500mhz <= -------------------------------- <= 1000mhz + * 500mhz <= -------------------------------- <= 1200mhz * pll_ms * @param clock_source * this parameter can be one of the following values: @@ -645,6 +705,10 @@ void crm_pll_config(crm_pll_clock_source_type clock_source, uint16_t pll_ns, \ uint16_t pll_ms, crm_pll_fr_type pll_fr) { /* config pll clock source */ + if(clock_source == CRM_PLL_SOURCE_HICK) + { + CRM->misc1_bit.hickdiv = CRM_HICK48_NODIV; + } CRM->pllcfg_bit.pllrcs = clock_source; /* config pll multiplication factor */ @@ -665,6 +729,7 @@ void crm_pll_config(crm_pll_clock_source_type clock_source, uint16_t pll_ns, \ void crm_sysclk_switch(crm_sclk_type value) { CRM->cfg_bit.sclksel = value; + DUMMY_NOP(); } /** @@ -888,7 +953,7 @@ void crm_interrupt_enable(uint32_t crm_int, confirm_state new_state) * pll_ms * * pll_rcs_freq * pll_ns - * 500mhz <= -------------------------------- <= 1000mhz + * 500mhz <= -------------------------------- <= 1200mhz * pll_ms * @param pll_rcs * this parameter can be one of the following values: @@ -903,9 +968,10 @@ void crm_interrupt_enable(uint32_t crm_int, confirm_state new_state) error_status crm_pll_parameter_calculate(crm_pll_clock_source_type pll_rcs, uint32_t target_sclk_freq, \ uint16_t *ret_ms, uint16_t *ret_ns, uint16_t *ret_fr) { - uint32_t pll_rcs_freq = 0, ns = 0, ms = 0, fr = 0; - uint32_t ms_min = 0, ms_max = 0, error_min = 0xFFFFFFFF; - uint32_t result = 0, absolute_value = 0; + uint32_t error_min = 0xFFFFFFFF; + uint32_t pll_rcs_freq = 0, result = 0, absolute_value = 0; + uint16_t ns = 0, ms = 0, ms_min = 0, ms_max = 0; + int16_t fr = 0; /* reduce calculate accuracy, target_sclk_freq accuracy with khz */ target_sclk_freq = target_sclk_freq / 1000; @@ -932,13 +998,13 @@ error_status crm_pll_parameter_calculate(crm_pll_clock_source_type pll_rcs, uint /* polling pll parameters */ for(ms = ms_min; ms <= ms_max; ms ++) { - for(fr = 0; fr <= 5; fr ++) + for(fr = 5; fr >= 0; fr --) { for(ns = 31; ns <= 500; ns ++) { result = (pll_rcs_freq * ns) / (ms); /* check vco frequency range, accuracy with khz */ - if((result < 500000U) || (result > 1000000U)) + if((result < 500000U) || (result > 1200000U)) { continue; } @@ -949,7 +1015,7 @@ error_status crm_pll_parameter_calculate(crm_pll_clock_source_type pll_rcs, uint { *ret_ms = ms; *ret_ns = ns; - *ret_fr = fr; + *ret_fr = (uint16_t)fr; /* the pll parameters that is equal to target_sclk_freq */ return SUCCESS; } @@ -960,7 +1026,7 @@ error_status crm_pll_parameter_calculate(crm_pll_clock_source_type pll_rcs, uint error_min = absolute_value; *ret_ms = ms; *ret_ns = ns; - *ret_fr = fr; + *ret_fr = (uint16_t)fr; } } } diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_dac.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_dac.c index daa9a528f6..eab69e080c 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_dac.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_dac.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_dac.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the dac firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -416,6 +414,34 @@ flag_status dac_udr_flag_get(dac_select_type dac_select) return status; } +/** + * @brief get flag of the dac udr interrupt flag. + * @param dac_select + * this parameter can be one of the following values: + * - DAC1_SELECT + * - DAC2_SELECT + * @retval the new state of dac udr flag status(SET or RESET). + */ +flag_status dac_udr_interrupt_flag_get(dac_select_type dac_select) +{ + flag_status status = RESET; + + switch(dac_select) + { + case DAC1_SELECT: + if((DAC->sts_bit.d1dmaudrf && DAC->ctrl_bit.d1dmaudrien) != 0) + status = SET; + break; + case DAC2_SELECT: + if((DAC->sts_bit.d2dmaudrf && DAC->ctrl_bit.d2dmaudrien) != 0) + status = SET; + break; + default: + break; + } + return status; +} + /** * @brief clear the dac udr flag. * @param dac_select diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_debug.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_debug.c index 86d07cdbac..dcad0d7de1 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_debug.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_debug.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_mcudbg.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the mcudbg firmware library ************************************************************************** * Copyright notice & Disclaimer diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_dma.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_dma.c index 24dce61dc4..0c15f350f1 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_dma.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_dma.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_dma.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the dma firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -241,6 +239,48 @@ flag_status dma_flag_get(uint32_t dmax_flag) } } +/** + * @brief dma interrupt flag get. + * @param dma_flag + * - DMA1_FDT1_FLAG - DMA1_HDT1_FLAG - DMA1_DTERR1_FLAG + * - DMA1_FDT2_FLAG - DMA1_HDT2_FLAG - DMA1_DTERR2_FLAG + * - DMA1_FDT3_FLAG - DMA1_HDT3_FLAG - DMA1_DTERR3_FLAG + * - DMA1_FDT4_FLAG - DMA1_HDT4_FLAG - DMA1_DTERR4_FLAG + * - DMA1_FDT5_FLAG - DMA1_HDT5_FLAG - DMA1_DTERR5_FLAG + * - DMA1_FDT6_FLAG - DMA1_HDT6_FLAG - DMA1_DTERR6_FLAG + * - DMA1_FDT7_FLAG - DMA1_HDT7_FLAG - DMA1_DTERR7_FLAG + * - DMA2_FDT1_FLAG - DMA2_HDT1_FLAG - DMA2_DTERR1_FLAG + * - DMA2_FDT2_FLAG - DMA2_HDT2_FLAG - DMA2_DTERR2_FLAG + * - DMA2_FDT3_FLAG - DMA2_HDT3_FLAG - DMA2_DTERR3_FLAG + * - DMA2_FDT4_FLAG - DMA2_HDT4_FLAG - DMA2_DTERR4_FLAG + * - DMA2_FDT5_FLAG - DMA2_HDT5_FLAG - DMA2_DTERR5_FLAG + * - DMA2_FDT6_FLAG - DMA2_HDT6_FLAG - DMA2_DTERR6_FLAG + * - DMA2_FDT7_FLAG - DMA2_HDT7_FLAG - DMA2_DTERR7_FLAG + * @retval state of dma flag. + */ +flag_status dma_interrupt_flag_get(uint32_t dmax_flag) +{ + uint32_t temp = 0; + + if(dmax_flag > 0x10000000) + { + temp = DMA2->sts; + } + else + { + temp = DMA1->sts; + } + + if((temp & dmax_flag) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + /** * @brief dma flag clear. * @param dma_flag @@ -363,9 +403,9 @@ void dma_init(dma_channel_type *dmax_channely, dma_init_type *dma_init_struct) * - DMAMUX_DMAREQ_ID_USART6_TX - DMAMUX_DMAREQ_ID_UART7_RX - DMAMUX_DMAREQ_ID_UART7_TX - DMAMUX_DMAREQ_ID_UART8_RX * - DMAMUX_DMAREQ_ID_UART8_TX - DMAMUX_DMAREQ_ID_SDIO1 - DMAMUX_DMAREQ_ID_SDIO2 - DMAMUX_DMAREQ_ID_QSPI1 * - DMAMUX_DMAREQ_ID_QSPI2 - DMAMUX_DMAREQ_ID_TMR1_CH1 - DMAMUX_DMAREQ_ID_TMR1_CH2 - DMAMUX_DMAREQ_ID_TMR1_CH3 - * - DMAMUX_DMAREQ_ID_TMR1_CH4 - DMAMUX_DMAREQ_ID_TMR1_OVERFLOW- DMAMUX_DMAREQ_ID_TMR1_TRIG - DMAMUX_DMAREQ_ID_TMR1_COM + * - DMAMUX_DMAREQ_ID_TMR1_CH4 - DMAMUX_DMAREQ_ID_TMR1_OVERFLOW- DMAMUX_DMAREQ_ID_TMR1_TRIG - DMAMUX_DMAREQ_ID_TMR1_HALL * - DMAMUX_DMAREQ_ID_TMR8_CH1 - DMAMUX_DMAREQ_ID_TMR8_CH2 - DMAMUX_DMAREQ_ID_TMR8_CH3 - DMAMUX_DMAREQ_ID_TMR8_CH4 - * - DMAMUX_DMAREQ_ID_TMR8_UP - DMAMUX_DMAREQ_ID_TMR8_TRIG - DMAMUX_DMAREQ_ID_TMR8_COM - DMAMUX_DMAREQ_ID_TMR2_CH1 + * - DMAMUX_DMAREQ_ID_TMR8_OVERFLOW- DMAMUX_DMAREQ_ID_TMR8_TRIG - DMAMUX_DMAREQ_ID_TMR8_HALL - DMAMUX_DMAREQ_ID_TMR2_CH1 * - DMAMUX_DMAREQ_ID_TMR2_CH2 - DMAMUX_DMAREQ_ID_TMR2_CH3 - DMAMUX_DMAREQ_ID_TMR2_CH4 - DMAMUX_DMAREQ_ID_TMR2_OVERFLOW * - DMAMUX_DMAREQ_ID_TMR2_TRIG - DMAMUX_DMAREQ_ID_TMR3_CH1 - DMAMUX_DMAREQ_ID_TMR3_CH2 - DMAMUX_DMAREQ_ID_TMR3_CH3 * - DMAMUX_DMAREQ_ID_TMR3_CH4 - DMAMUX_DMAREQ_ID_TMR3_OVERFLOW- DMAMUX_DMAREQ_ID_TMR3_TRIG - DMAMUX_DMAREQ_ID_TMR4_CH1 @@ -426,9 +466,9 @@ void dmamux_enable(dma_type *dma_x, confirm_state new_state) * - DMAMUX_DMAREQ_ID_USART6_TX - DMAMUX_DMAREQ_ID_UART7_RX - DMAMUX_DMAREQ_ID_UART7_TX - DMAMUX_DMAREQ_ID_UART8_RX * - DMAMUX_DMAREQ_ID_UART8_TX - DMAMUX_DMAREQ_ID_SDIO1 - DMAMUX_DMAREQ_ID_SDIO2 - DMAMUX_DMAREQ_ID_QSPI1 * - DMAMUX_DMAREQ_ID_QSPI2 - DMAMUX_DMAREQ_ID_TMR1_CH1 - DMAMUX_DMAREQ_ID_TMR1_CH2 - DMAMUX_DMAREQ_ID_TMR1_CH3 - * - DMAMUX_DMAREQ_ID_TMR1_CH4 - DMAMUX_DMAREQ_ID_TMR1_OVERFLOW- DMAMUX_DMAREQ_ID_TMR1_TRIG - DMAMUX_DMAREQ_ID_TMR1_COM + * - DMAMUX_DMAREQ_ID_TMR1_CH4 - DMAMUX_DMAREQ_ID_TMR1_OVERFLOW- DMAMUX_DMAREQ_ID_TMR1_TRIG - DMAMUX_DMAREQ_ID_TMR1_HALL * - DMAMUX_DMAREQ_ID_TMR8_CH1 - DMAMUX_DMAREQ_ID_TMR8_CH2 - DMAMUX_DMAREQ_ID_TMR8_CH3 - DMAMUX_DMAREQ_ID_TMR8_CH4 - * - DMAMUX_DMAREQ_ID_TMR8_UP - DMAMUX_DMAREQ_ID_TMR8_TRIG - DMAMUX_DMAREQ_ID_TMR8_COM - DMAMUX_DMAREQ_ID_TMR2_CH1 + * - DMAMUX_DMAREQ_ID_TMR8_OVERFLOW- DMAMUX_DMAREQ_ID_TMR8_TRIG - DMAMUX_DMAREQ_ID_TMR8_HALL - DMAMUX_DMAREQ_ID_TMR2_CH1 * - DMAMUX_DMAREQ_ID_TMR2_CH2 - DMAMUX_DMAREQ_ID_TMR2_CH3 - DMAMUX_DMAREQ_ID_TMR2_CH4 - DMAMUX_DMAREQ_ID_TMR2_OVERFLOW * - DMAMUX_DMAREQ_ID_TMR2_TRIG - DMAMUX_DMAREQ_ID_TMR3_CH1 - DMAMUX_DMAREQ_ID_TMR3_CH2 - DMAMUX_DMAREQ_ID_TMR3_CH3 * - DMAMUX_DMAREQ_ID_TMR3_CH4 - DMAMUX_DMAREQ_ID_TMR3_OVERFLOW- DMAMUX_DMAREQ_ID_TMR3_TRIG - DMAMUX_DMAREQ_ID_TMR4_CH1 @@ -483,7 +523,7 @@ void dmamux_sync_config(dmamux_channel_type *dmamux_channelx, dmamux_sync_init_t { dmamux_channelx->muxctrl_bit.syncsel = dmamux_sync_init_struct->sync_signal_sel; dmamux_channelx->muxctrl_bit.syncpol = dmamux_sync_init_struct->sync_polarity; - dmamux_channelx->muxctrl_bit.reqcnt = dmamux_sync_init_struct->sync_request_number; + dmamux_channelx->muxctrl_bit.reqcnt = dmamux_sync_init_struct->sync_request_number - 1; dmamux_channelx->muxctrl_bit.evtgen = dmamux_sync_init_struct->sync_event_enable; dmamux_channelx->muxctrl_bit.syncen = dmamux_sync_init_struct->sync_enable; } @@ -520,7 +560,7 @@ void dmamux_generator_config(dmamux_generator_type *dmamux_gen_x, dmamux_gen_ini { dmamux_gen_x->gctrl_bit.sigsel = dmamux_gen_init_struct->gen_signal_sel; dmamux_gen_x->gctrl_bit.gpol = dmamux_gen_init_struct->gen_polarity; - dmamux_gen_x->gctrl_bit.greqcnt = dmamux_gen_init_struct->gen_request_number; + dmamux_gen_x->gctrl_bit.greqcnt = dmamux_gen_init_struct->gen_request_number - 1; dmamux_gen_x->gctrl_bit.gen = dmamux_gen_init_struct->gen_enable; } @@ -610,6 +650,78 @@ flag_status dmamux_sync_flag_get(dma_type *dma_x, uint32_t flag) } } +/** + * @brief dmamux sync interrupt flag get. + * @param dma_x : pointer to a dma_type structure, can be DMA1 or DMA2. + * @param flag + * this parameter can be any combination of the following values: + * - DMAMUX_SYNC_OV1_FLAG + * - DMAMUX_SYNC_OV2_FLAG + * - DMAMUX_SYNC_OV3_FLAG + * - DMAMUX_SYNC_OV4_FLAG + * - DMAMUX_SYNC_OV5_FLAG + * - DMAMUX_SYNC_OV6_FLAG + * - DMAMUX_SYNC_OV7_FLAG + * @retval state of dmamux sync flag. + */ +flag_status dmamux_sync_interrupt_flag_get(dma_type *dma_x, uint32_t flag) +{ + + flag_status bitstatus = RESET; + uint32_t sync_int_temp = flag; + uint32_t index = 0; + uint32_t tmpreg = 0, enablestatus = 0; + uint32_t regoffset = 0x4; + + while((sync_int_temp & 0x00000001) == RESET) + { + sync_int_temp = sync_int_temp >> 1; + index++; + } + + if(dma_x == DMA1) + { + tmpreg = *(uint32_t*)(DMA1MUX_BASE + (index * regoffset)); + } + else + { + tmpreg = *(uint32_t*)(DMA2MUX_BASE + (index * regoffset)); + } + + if((tmpreg & (uint32_t)0x00000100) != (uint32_t)RESET) + { + enablestatus = SET; + } + else + { + enablestatus = RESET; + } + + if(dma_x == DMA1) + { + if(((DMA1->muxsyncsts & flag) != (uint32_t)RESET) && (enablestatus != RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if(((DMA2->muxsyncsts & flag) != (uint32_t)RESET) && (enablestatus != RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + return bitstatus; +} + /** * @brief dmamux sync flag clear. * @param dma_x : pointer to a dma_type structure, can be DMA1 or DMA2. @@ -652,6 +764,70 @@ flag_status dmamux_generator_flag_get(dma_type *dma_x, uint32_t flag) } } +/** + * @brief dmamux request generator interrupt flag get. + * @param dma_x : pointer to a dma_type structure, can be DMA1 or DMA2. + * @param flag + * this parameter can be any combination of the following values: + * - DMAMUX_GEN_TRIG_OV1_FLAG + * - DMAMUX_GEN_TRIG_OV2_FLAG + * - DMAMUX_GEN_TRIG_OV3_FLAG + * - DMAMUX_GEN_TRIG_OV4_FLAG + * @retval state of dmamux sync flag. + */ +flag_status dmamux_generator_interrupt_flag_get(dma_type *dma_x, uint32_t flag) +{ + flag_status bitstatus = RESET; + uint32_t sync_int_temp = flag; + uint32_t index = 0; + uint32_t tmpreg = 0, enablestatus = 0; + uint32_t regoffset = 0x4; + + while((sync_int_temp & 0x00000001) == RESET) + { + sync_int_temp = sync_int_temp >> 1; + index++; + } + + if(dma_x == DMA1) + tmpreg = *(uint32_t*)(DMA1MUX_GENERATOR1_BASE + (index * regoffset)); + else + tmpreg = *(uint32_t*)(DMA2MUX_GENERATOR1_BASE + (index * regoffset)); + + if((tmpreg & (uint32_t)0x00000100) != (uint32_t)RESET) + { + enablestatus = SET; + } + else + { + enablestatus = RESET; + } + if(dma_x == DMA1) + { + if(((DMA1->muxgsts & flag) != (uint32_t)RESET) && (enablestatus != RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if(((DMA2->muxgsts & flag) != (uint32_t)RESET) && (enablestatus != RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + + return bitstatus; +} + /** * @brief dmamux request generator flag clear. * @param dma_x : pointer to a dma_type structure, can be DMA1 or DMA2. diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_dvp.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_dvp.c index f8de9ada7d..9688236b12 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_dvp.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_dvp.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_dvp.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the dvp firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -41,6 +39,17 @@ * @{ */ +/** + * @brief reset the dvp register + * @param none + * @retval none + */ +void dvp_reset(void) +{ + crm_periph_reset(CRM_DVP_PERIPH_RESET, TRUE); + crm_periph_reset(CRM_DVP_PERIPH_RESET, FALSE); +} + /** * @brief enable or disable dvp capture * @param new_state (TRUE or FALSE) @@ -76,16 +85,18 @@ void dvp_window_crop_enable(confirm_state new_state) /** * @brief set dvp cropping window configuration - * @param crop_x(0x0000~0x3FFF): cropping window horizontal start pixel - * @param crop_y(0x0000~0x1FFF): cropping window vertical start pixel - * @param crop_w(0x0001~0x3FFF): cropping window horizontal pixel number - * @param crop_h(0x0001~0x3FFF): cropping window vertical pixel number + * @param crop_x: cropping window horizontal start pixel + * @param crop_y: cropping window vertical start line + * @param crop_w: cropping window horizontal pixel number + * @param crop_h: cropping window vertical line number + * @param bytes: the number of bytes corresponding to one pixel + * eg. y8:bytes = 1, rgb565:bytes = 2 * @retval none */ -void dvp_window_crop_set(uint16_t crop_x, uint16_t crop_y, uint16_t crop_w, uint16_t crop_h) +void dvp_window_crop_set(uint16_t crop_x, uint16_t crop_y, uint16_t crop_w, uint16_t crop_h, uint8_t bytes) { - DVP->cwst = ((crop_x * 2) | (crop_y << 16)); - DVP->cwsz = ((crop_w * 2 - 1) | ((crop_h - 1) << 16)); + DVP->cwst = ((crop_x * bytes) | (crop_y << 16)); + DVP->cwsz = ((crop_w * bytes - 1) | ((crop_h - 1) << 16)); } /** @@ -218,15 +229,15 @@ void dvp_enable(confirm_state new_state) /** * @brief set dvp zoomout select - * @param dvp_pcdse: pixel capture/drop selection extension (Only work when pcdc = 2) + * @param dvp_pcdes: pixel capture/drop selection extension (Only work when pcdc = 2) * this parameter can be one of the following values: - * - DVP_PCDSE_CAP_FIRST - * - DVP_PCDSE_DROP_FIRST + * - DVP_PCDES_CAP_FIRST + * - DVP_PCDES_DROP_FIRST * @retval none */ -void dvp_zoomout_select(dvp_pcdse_type dvp_pcdse) +void dvp_zoomout_select(dvp_pcdes_type dvp_pcdes) { - DVP->actrl_bit.pcdse = dvp_pcdse; + DVP->actrl_bit.pcdes = dvp_pcdes; } /** @@ -265,7 +276,7 @@ void dvp_zoomout_set(dvp_pcdc_type dvp_pcdc, dvp_pcds_type dvp_pcds, dvp_lcdc_ty * this parameter can be one of the following values: * - DVP_STATUS_HSYN * - DVP_STATUS_VSYN - * - DVP_STATUS_OFS + * - DVP_STATUS_OFNE * @retval flag_status (SET or RESET) */ flag_status dvp_basic_status_get(dvp_status_basic_type dvp_status_basic) @@ -309,16 +320,9 @@ void dvp_interrupt_enable(uint32_t dvp_int, confirm_state new_state) } /** - * @brief get dvp event/interrupt flag status + * @brief get dvp interrupt flag status * @param flag * this parameter can be one of the following values: - * event flag: - * - DVP_CFD_EVT_FLAG - * - DVP_OVR_EVT_FLAG - * - DVP_ESE_EVT_FLAG - * - DVP_VS_EVT_FLAG - * - DVP_HS_EVT_FLAG - * interrupt flag: * - DVP_CFD_INT_FLAG * - DVP_OVR_INT_FLAG * - DVP_ESE_INT_FLAG @@ -326,31 +330,47 @@ void dvp_interrupt_enable(uint32_t dvp_int, confirm_state new_state) * - DVP_HS_INT_FLAG * @retval flag_status (SET or RESET) */ -flag_status dvp_flag_get(uint32_t flag) +flag_status dvp_interrupt_flag_get(uint32_t flag) { flag_status status = RESET; - if(flag & 0x80000000) + + if((DVP->ists & flag) != RESET) { - if((DVP->ists & flag) != RESET) - { - status = SET; - } - else - { - status = RESET; - } + status = SET; } else { - if((DVP->ests & flag) != RESET) - { - status = SET; - } - else - { - status = RESET; - } + status = RESET; } + + return status; +} + +/** + * @brief get dvp event flag status + * @param flag + * this parameter can be one of the following values: + * - DVP_CFD_EVT_FLAG + * - DVP_OVR_EVT_FLAG + * - DVP_ESE_EVT_FLAG + * - DVP_VS_EVT_FLAG + * - DVP_HS_EVT_FLAG + * @retval flag_status (SET or RESET) + */ +flag_status dvp_flag_get(uint32_t flag) +{ + flag_status status = RESET; + flag &= ~0x80000000; + + if((DVP->ests & flag) != RESET) + { + status = SET; + } + else + { + status = RESET; + } + return status; } @@ -406,16 +426,16 @@ void dvp_enhanced_scaling_resize_set(uint16_t src_w, uint16_t des_w, uint16_t sr /** * @brief set enhanced frame rate control configuration - * @param efrcfm(0x00~0x1F): original frame rate contorl factor - * @param efrcfn(0x00~0x1F): enhanced frame rate contorl factor + * @param efrcsf(0x00~0x1F): original frame rate contorl factor + * @param efrctf(0x00~0x1F): enhanced frame rate contorl factor * @param new_state (TRUE or FALSE) * @retval none */ -void dvp_enhanced_framerate_set(uint16_t efrcfm, uint16_t efrcfn, confirm_state new_state) +void dvp_enhanced_framerate_set(uint16_t efrcsf, uint16_t efrctf, confirm_state new_state) { - if((!DVP->ctrl_bit.cfm) && (!DVP->ctrl_bit.bfrc) && (efrcfn <= efrcfm)) + if((!DVP->ctrl_bit.cfm) && (!DVP->ctrl_bit.bfrc) && (efrctf <= efrcsf)) { - DVP->frf = (efrcfm | (efrcfn << 8)); + DVP->frf = (efrcsf | (efrctf << 8)); } DVP->actrl_bit.efrce = new_state; @@ -440,7 +460,7 @@ void dvp_monochrome_image_binarization_set(uint8_t mibthd, confirm_state new_sta * - DVP_EFDF_BYPASS * - DVP_EFDF_YUV422_UYVY * - DVP_EFDF_YUV422_YUYV - * - DVP_EFDF_YUV444 + * - DVP_EFDF_RGB565_555 * - DVP_EFDF_Y8 * @retval none */ @@ -451,10 +471,10 @@ void dvp_enhanced_data_format_set(dvp_efdf_type dvp_efdf) /** * @brief set dvp input data un-used condition/number configuration - * @param dvp_iduc: input data un-used condition + * @param dvp_idus: input data un-used condition * this parameter can be one of the following values: - * - DVP_IDUC_MSB - * - DVP_IDUC_LSB + * - DVP_IDUS_MSB + * - DVP_IDUS_LSB * @param dvp_idun: input data un-used number * this parameter can be one of the following values: * - DVP_IDUN_0 @@ -463,9 +483,9 @@ void dvp_enhanced_data_format_set(dvp_efdf_type dvp_efdf) * - DVP_IDUN_6 * @retval none */ -void dvp_input_data_unused_set(dvp_iduc_type dvp_iduc, dvp_idun_type dvp_idun) +void dvp_input_data_unused_set(dvp_idus_type dvp_idus, dvp_idun_type dvp_idun) { - DVP->actrl_bit.iduc = dvp_iduc; + DVP->actrl_bit.idus = dvp_idus; DVP->actrl_bit.idun = dvp_idun; } @@ -484,20 +504,20 @@ void dvp_dma_burst_set(dvp_dmabt_type dvp_dmabt) /** * @brief set dvp hsync/vsync event interrupt strategy configuration - * @param dvp_hseis: hsync event interrupt strategy + * @param dvp_hseid: hsync event interrupt strategy * this parameter can be one of the following values: - * - DVP_HSEIS_LINE_END - * - DVP_HSEIS_LINE_START - * @param dvp_vseis: vsync event interrupt strategy + * - DVP_HSEID_LINE_END + * - DVP_HSEID_LINE_START + * @param dvp_vseid: vsync event interrupt strategy * this parameter can be one of the following values: - * - DVP_VSEIS_FRAME_END - * - DVP_VSEIS_FRMAE_START + * - DVP_VSEID_FRAME_END + * - DVP_VSEID_FRMAE_START * @retval none */ -void dvp_sync_event_interrupt_set(dvp_hseis_type dvp_hseis, dvp_vseis_type dvp_vseis) +void dvp_sync_event_interrupt_set(dvp_hseid_type dvp_hseid, dvp_vseid_type dvp_vseid) { - DVP->actrl_bit.hseis = dvp_hseis; - DVP->actrl_bit.vseis = dvp_vseis; + DVP->actrl_bit.hseid = dvp_hseid; + DVP->actrl_bit.vseid = dvp_vseid; } /** diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_edma.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_edma.c index 42cc0a28dd..ca6e9b8709 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_edma.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_edma.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_edma.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the edma firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -532,6 +530,43 @@ flag_status edma_flag_get(uint32_t edma_flag) } } +/** + * @brief get the edma interrupt flag. + * @param edma_flag: + * this parameter can be one of the following values: + * - EDMA_FERR1_FLAG - EDMA_DMERR1_FLAG - EDMA_DTERR1_FLAG - EDMA_HDT1_FLAG - EDMA_FDT1_FLAG + * - EDMA_FERR2_FLAG - EDMA_DMERR2_FLAG - EDMA_DTERR2_FLAG - EDMA_HDT2_FLAG - EDMA_FDT2_FLAG + * - EDMA_FERR3_FLAG - EDMA_DMERR3_FLAG - EDMA_DTERR3_FLAG - EDMA_HDT3_FLAG - EDMA_FDT3_FLAG + * - EDMA_FERR4_FLAG - EDMA_DMERR4_FLAG - EDMA_DTERR4_FLAG - EDMA_HDT4_FLAG - EDMA_FDT4_FLAG + * - EDMA_FERR5_FLAG - EDMA_DMERR5_FLAG - EDMA_DTERR5_FLAG - EDMA_HDT5_FLAG - EDMA_FDT5_FLAG + * - EDMA_FERR6_FLAG - EDMA_DMERR6_FLAG - EDMA_DTERR6_FLAG - EDMA_HDT6_FLAG - EDMA_FDT6_FLAG + * - EDMA_FERR7_FLAG - EDMA_DMERR7_FLAG - EDMA_DTERR7_FLAG - EDMA_HDT7_FLAG - EDMA_FDT7_FLAG + * - EDMA_FERR8_FLAG - EDMA_DMERR8_FLAG - EDMA_DTERR8_FLAG - EDMA_HDT8_FLAG - EDMA_FDT8_FLAG + * @retval the new state of edma flag (SET or RESET). + */ +flag_status edma_interrupt_flag_get(uint32_t edma_flag) +{ + uint32_t status; + + if(edma_flag > ((uint32_t)0x20000000)) + { + status = EDMA->sts2; + } + else + { + status = EDMA->sts1; + } + + if((status & edma_flag) != ((uint32_t)RESET)) + { + return SET; + } + else + { + return RESET; + } +} + /** * @brief clear the edma flag. * @param edma_flag: @@ -753,7 +788,7 @@ void edmamux_sync_config(edmamux_channel_type *edmamux_channelx, edmamux_sync_in { edmamux_channelx->muxctrl_bit.syncsel = edmamux_sync_init_struct->sync_signal_sel; edmamux_channelx->muxctrl_bit.syncpol = edmamux_sync_init_struct->sync_polarity; - edmamux_channelx->muxctrl_bit.reqcnt = edmamux_sync_init_struct->sync_request_number; + edmamux_channelx->muxctrl_bit.reqcnt = edmamux_sync_init_struct->sync_request_number - 1; edmamux_channelx->muxctrl_bit.evtgen = edmamux_sync_init_struct->sync_event_enable; edmamux_channelx->muxctrl_bit.syncen = edmamux_sync_init_struct->sync_enable; } @@ -780,7 +815,7 @@ void edmamux_generator_config(edmamux_generator_type *edmamux_gen_x, edmamux_gen { edmamux_gen_x->gctrl_bit.sigsel = edmamux_gen_init_struct->gen_signal_sel; edmamux_gen_x->gctrl_bit.gpol = edmamux_gen_init_struct->gen_polarity; - edmamux_gen_x->gctrl_bit.greqcnt = edmamux_gen_init_struct->gen_request_number; + edmamux_gen_x->gctrl_bit.greqcnt = edmamux_gen_init_struct->gen_request_number - 1; edmamux_gen_x->gctrl_bit.gen = edmamux_gen_init_struct->gen_enable; } @@ -860,6 +895,63 @@ flag_status edmamux_sync_flag_get(uint32_t flag) } } +/** + * @brief edmamux sync interrupt flag get. + * @param flag + * this parameter can be any combination of the following values: + * - EDMAMUX_SYNC_OV1_FLAG + * - EDMAMUX_SYNC_OV2_FLAG + * - EDMAMUX_SYNC_OV3_FLAG + * - EDMAMUX_SYNC_OV4_FLAG + * - EDMAMUX_SYNC_OV5_FLAG + * - EDMAMUX_SYNC_OV6_FLAG + * - EDMAMUX_SYNC_OV7_FLAG + * - EDMAMUX_SYNC_OV8_FLAG + * @retval state of edmamux sync flag. + */ +flag_status edmamux_sync_interrupt_flag_get(uint32_t flag) +{ + uint32_t int_stat = 0; + + if(flag == EDMAMUX_SYNC_OV1_FLAG) + { + int_stat = (uint32_t)EDMAMUX_CHANNEL1->muxctrl_bit.syncovien; + } + else if(flag == EDMAMUX_SYNC_OV2_FLAG) + { + int_stat = (uint32_t)EDMAMUX_CHANNEL2->muxctrl_bit.syncovien; + } + else if(flag == EDMAMUX_SYNC_OV3_FLAG) + { + int_stat = (uint32_t)EDMAMUX_CHANNEL3->muxctrl_bit.syncovien; + } + else if(flag == EDMAMUX_SYNC_OV4_FLAG) + { + int_stat = (uint32_t)EDMAMUX_CHANNEL4->muxctrl_bit.syncovien; + } + else if(flag == EDMAMUX_SYNC_OV5_FLAG) + { + int_stat = (uint32_t)EDMAMUX_CHANNEL5->muxctrl_bit.syncovien; + } + else if(flag == EDMAMUX_SYNC_OV6_FLAG) + { + int_stat = (uint32_t)EDMAMUX_CHANNEL6->muxctrl_bit.syncovien; + } + else if(flag == EDMAMUX_SYNC_OV7_FLAG) + { + int_stat = (uint32_t)EDMAMUX_CHANNEL7->muxctrl_bit.syncovien; + } + else + { + int_stat = (uint32_t)EDMAMUX_CHANNEL8->muxctrl_bit.syncovien; + } + + if((int_stat != RESET) && ((EDMA->muxsyncsts & flag) != RESET)) + return SET; + else + return RESET; +} + /** * @brief edmamux sync flag clear. * @param flag @@ -901,6 +993,43 @@ flag_status edmamux_generator_flag_get(uint32_t flag) } } +/** + * @brief edmamux request generator interrupt flag get. + * @param flag + * this parameter can be any combination of the following values: + * - EDMAMUX_GEN_TRIG_OV1_FLAG + * - EDMAMUX_GEN_TRIG_OV2_FLAG + * - EDMAMUX_GEN_TRIG_OV3_FLAG + * - EDMAMUX_GEN_TRIG_OV4_FLAG + * @retval state of edmamux sync flag. + */ +flag_status edmamux_generator_interrupt_flag_get(uint32_t flag) +{ + uint32_t int_stat = 0; + + if(flag == EDMAMUX_GEN_TRIG_OV1_FLAG) + { + int_stat = EDMAMUX_GENERATOR1->gctrl_bit.trgovien; + } + else if(flag == EDMAMUX_GEN_TRIG_OV2_FLAG) + { + int_stat = EDMAMUX_GENERATOR2->gctrl_bit.trgovien; + } + else if(flag == EDMAMUX_GEN_TRIG_OV3_FLAG) + { + int_stat = EDMAMUX_GENERATOR3->gctrl_bit.trgovien; + } + else + { + int_stat = EDMAMUX_GENERATOR4->gctrl_bit.trgovien; + } + + if((int_stat != RESET) && ((EDMA->muxgsts & flag) != RESET)) + return SET; + else + return RESET; +} + /** * @brief edmamux request generator flag clear. * @param flag diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_emac.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_emac.c index 749766eeb5..a90ff38b36 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_emac.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_emac.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_emac.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the emac firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -45,8 +43,10 @@ /** * @brief global pointers on tx and rx descriptor used to track transmit and receive descriptors */ -emac_dma_desc_type *dma_tx_desc_to_set; -emac_dma_desc_type *dma_rx_desc_to_get; +__IO emac_dma_desc_type *dma_tx_desc_to_set; +__IO emac_dma_desc_type *dma_rx_desc_to_get; +__IO emac_dma_desc_type *ptp_dma_tx_desc_to_set; +__IO emac_dma_desc_type *ptp_dma_rx_desc_to_get; /* emac private function */ static void emac_delay(uint32_t delay); @@ -221,7 +221,6 @@ void emac_stop(void) emac_trasmitter_enable(FALSE); } - /** * @brief write phy data. * @param address: phy address. @@ -530,6 +529,7 @@ void emac_broadcast_frames_disable(confirm_state new_state) * @param condition: set what control frame can pass filter. * this parameter can be one of the following values: * - EMAC_CONTROL_FRAME_PASSING_NO + * - EMAC_CONTROL_FRAME_PASSING_ALL_EXCEPT_PAUSE * - EMAC_CONTROL_FRAME_PASSING_ALL * - EMAC_CONTROL_FRAME_PASSING_MATCH * @retval none @@ -989,6 +989,90 @@ void emac_dma_descriptor_list_address_set(emac_dma_tx_rx_type transfer_type, ema } } +/** + * @brief set transmit/receive descriptor list address + * @param transfer_type: it will be transmit or receive + * this parameter can be one of the following values: + * - EMAC_DMA_TRANSMIT + * - EMAC_DMA_RECEIVE + * @param dma_desc_tab: pointer on the first tx desc list + * @param buff: pointer on the first tx/rx buffer list + * @param buffer_count: number of the used Tx desc in the list + * @retval none + */ +void emac_ptp_dma_descriptor_list_address_set(emac_dma_tx_rx_type transfer_type, emac_dma_desc_type *dma_desc_tab, emac_dma_desc_type *ptp_dma_desc_tab, uint8_t *buff, uint32_t buffer_count) +{ + uint32_t i = 0; + emac_dma_desc_type *dma_descriptor; + + switch(transfer_type) + { + case EMAC_DMA_TRANSMIT: + { + dma_tx_desc_to_set = dma_desc_tab; + ptp_dma_tx_desc_to_set = ptp_dma_desc_tab; + + for(i = 0; i < buffer_count; i++) + { + dma_descriptor = dma_desc_tab + i; + + dma_descriptor->status = EMAC_DMATXDESC_TCH | EMAC_DMATXDESC_TTSE; + + dma_descriptor->buf1addr = (uint32_t)(&buff[i * EMAC_MAX_PACKET_LENGTH]); + + if(i < (buffer_count - 1)) + { + dma_descriptor->buf2nextdescaddr = (uint32_t)(dma_desc_tab + i + 1); + } + else + { + dma_descriptor->buf2nextdescaddr = (uint32_t) dma_desc_tab; + } + + (&ptp_dma_desc_tab[i])->buf1addr = dma_descriptor->buf1addr; + (&ptp_dma_desc_tab[i])->buf2nextdescaddr = dma_descriptor->buf2nextdescaddr; + } + + (&ptp_dma_desc_tab[i-1])->status = (uint32_t) ptp_dma_desc_tab; + + EMAC_DMA->tdladdr_bit.stl = (uint32_t) dma_desc_tab; + break; + } + case EMAC_DMA_RECEIVE: + { + dma_rx_desc_to_get = dma_desc_tab; + ptp_dma_rx_desc_to_get = ptp_dma_desc_tab; + + for(i = 0; i < buffer_count; i++) + { + dma_descriptor = dma_desc_tab + i; + + dma_descriptor->status = EMAC_DMARXDESC_OWN; + + dma_descriptor->controlsize = EMAC_DMARXDESC_RCH | (uint32_t)EMAC_MAX_PACKET_LENGTH; + + dma_descriptor->buf1addr = (uint32_t)(&buff[i * EMAC_MAX_PACKET_LENGTH]); + + if(i < (buffer_count - 1)) + { + dma_descriptor->buf2nextdescaddr = (uint32_t)(dma_desc_tab + i + 1); + } + else + { + dma_descriptor->buf2nextdescaddr = (uint32_t) dma_desc_tab; + } + + (&ptp_dma_desc_tab[i])->buf1addr = dma_descriptor->buf1addr; + (&ptp_dma_desc_tab[i])->buf2nextdescaddr = dma_descriptor->buf2nextdescaddr; + } + + (&ptp_dma_desc_tab[i-1])->status = (uint32_t) ptp_dma_desc_tab; + + EMAC_DMA->rdladdr_bit.srl = (uint32_t) dma_desc_tab; + break; + } + } +} /** * @brief enable or disable the specified dma rx descriptor receive interrupt * @param dma_rx_desc: pointer on a rx desc. @@ -1049,7 +1133,7 @@ uint32_t emac_received_packet_size_get(void) ((dma_rx_desc_to_get->status & EMAC_DMARXDESC_LS) != (uint32_t)RESET) && ((dma_rx_desc_to_get->status & EMAC_DMARXDESC_FS) != (uint32_t)RESET)) { - frame_length = emac_dmarxdesc_frame_length_get(dma_rx_desc_to_get); + frame_length = emac_dmarxdesc_frame_length_get((emac_dma_desc_type*) dma_rx_desc_to_get); } return frame_length; @@ -1660,6 +1744,16 @@ uint32_t emac_dma_tansfer_address_get(emac_dma_transfer_address_type transfer_ty return address; } +/** + * @brief alternate dma descriptor size + * @param new_state: TRUE or FALSE + * @retval none + */ +void emac_dma_alternate_desc_size(confirm_state new_state) +{ + EMAC_DMA->bm_bit.atds = new_state; +} + /** * @brief reset all counter * @param none @@ -2039,6 +2133,27 @@ void emac_ptp_mac_address_filter_enable(confirm_state new_state) EMAC_PTP->tsctrl_bit.emafpff = new_state; } +/** + * @brief check whether the specified emac ptp flag is set or not. + * @param flag: specifies the flag to check. + * this parameter can be one of the following values: + * - EMAC_PTP_TI_FLAG: time stamp initialized flag + * - EMAC_PTP_TU_FLAG: time stamp updtated flag + * - EMAC_PTP_ARU_FLAG: transmit data buffer empty flag + * @retval the new state of usart_flag (SET or RESET). + */ +flag_status emac_ptp_flag_get(uint32_t flag) +{ + if(EMAC_PTP->tsctrl & flag) + { + return SET; + } + else + { + return RESET; + } +} + /** * @brief set subsecond increment value * @param value: add to subsecond value for every update @@ -2089,42 +2204,19 @@ confirm_state emac_ptp_system_time_sign_get(void) } /** - * @brief set system time second + * @brief set system time + * @param sign: plus or minus * @param second: system time second - * @retval none - */ -void emac_ptp_system_second_set(uint32_t second) -{ - EMAC_PTP->tshud_bit.ts = second; -} - -/** - * @brief set system time subsecond * @param subsecond: system time subsecond * @retval none */ -void emac_ptp_system_subsecond_set(uint32_t subsecond) +void emac_ptp_system_time_set(uint32_t sign, uint32_t second, uint32_t subsecond) { + EMAC_PTP->tslud_bit.ast = sign ? 1 : 0; + EMAC_PTP->tshud_bit.ts = second; EMAC_PTP->tslud_bit.tss = subsecond; } -/** - * @brief set system time sign - * @param sign: TRUE or FALSE. - * @retval none - */ -void emac_ptp_system_time_sign_set(confirm_state sign) -{ - if(sign) - { - EMAC_PTP->tslud_bit.ast = 1; - } - else - { - EMAC_PTP->tslud_bit.ast = 0; - } -} - /** * @brief set time stamp addend * @param value: to achieve time synchronization @@ -2266,6 +2358,62 @@ flag_status emac_dma_flag_get(uint32_t dma_flag) return status; } +/** + * @brief check whether the specified emac dma interrupt flag is set or not. + * @param dma_flag: specifies the emac dma flag to check. + * this parameter can be one of emac dma flag status: + * - EMAC_DMA_TI_FLAG + * - EMAC_DMA_TPS_FLAG + * - EMAC_DMA_TBU_FLAG + * - EMAC_DMA_TJT_FLAG + * - EMAC_DMA_OVF_FLAG + * - EMAC_DMA_UNF_FLAG + * - EMAC_DMA_RI_FLAG + * - EMAC_DMA_RBU_FLAG + * - EMAC_DMA_RPS_FLAG + * - EMAC_DMA_RWT_FLAG + * - EMAC_DMA_ETI_FLAG + * - EMAC_DMA_FBEI_FLAG + * - EMAC_DMA_ERI_FLAG + * - EMAC_DMA_AIS_FLAG + * - EMAC_DMA_NIS_FLAG + * @retval the new state of dma_flag (SET or RESET). + */ +flag_status emac_dma_interrupt_flag_get(uint32_t dma_flag) +{ + flag_status status = RESET; + switch(dma_flag) + { + case EMAC_DMA_TI_FLAG: + case EMAC_DMA_TBU_FLAG: + case EMAC_DMA_RI_FLAG: + case EMAC_DMA_ERI_FLAG: + if((EMAC_DMA->sts & dma_flag) && + (EMAC_DMA->ie & dma_flag) && + (EMAC_DMA->sts & EMAC_DMA_NIS_FLAG)) + status = SET; + break; + case EMAC_DMA_TPS_FLAG: + case EMAC_DMA_TJT_FLAG: + case EMAC_DMA_OVF_FLAG: + case EMAC_DMA_UNF_FLAG: + case EMAC_DMA_RBU_FLAG: + case EMAC_DMA_RPS_FLAG: + case EMAC_DMA_RWT_FLAG: + case EMAC_DMA_ETI_FLAG: + case EMAC_DMA_FBEI_FLAG: + if((EMAC_DMA->sts & dma_flag) && + (EMAC_DMA->ie & dma_flag) && + (EMAC_DMA->sts & EMAC_DMA_AIS_FLAG)) + status = SET; + break; + default: + break; + } + /* return the new state (SET or RESET) */ + return status; +} + /** * @brief clear the emac dma flag. * @param dma_flag: specifies the emac dma flags to clear. diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_ertc.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_ertc.c index ab5aaed58f..ed60bac123 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_ertc.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_ertc.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_ertc.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the ertc firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -98,15 +96,9 @@ error_status ertc_wait_update(void) { uint32_t timeout = ERTC_TIMEOUT * 2; - /* disable write protection */ - ertc_write_protect_disable(); - /* clear updf flag */ ERTC->sts = ~(ERTC_UPDF_FLAG | 0x00000080) | (ERTC->sts_bit.imen << 7); - /* enable write protection */ - ertc_write_protect_enable(); - while(ERTC->sts_bit.updf == 0) { if(timeout == 0) @@ -164,9 +156,6 @@ error_status ertc_init_mode_enter(void) { uint32_t timeout = ERTC_TIMEOUT * 2; - /* disable write protection */ - ertc_write_protect_disable(); - if(ERTC->sts_bit.imf == 0) { /* enter init mode */ @@ -331,7 +320,7 @@ error_status ertc_date_set(uint8_t year, uint8_t month, uint8_t date, uint8_t we return ERROR; } - /* Set the ertc_DR register */ + /* set the ertc_date register */ ERTC->date = reg.date; /* exit init mode */ @@ -406,8 +395,6 @@ void ertc_calendar_get(ertc_time_type* time) ertc_reg_time_type reg_tm; ertc_reg_date_type reg_dt; - (void) (ERTC->sts); - reg_tm.time = ERTC->time; reg_dt.date = ERTC->date; @@ -724,8 +711,8 @@ uint32_t ertc_alarm_sub_second_get(ertc_alarm_type alarm_x) * - ERTC_WAT_CLK_ERTCCLK_DIV8: ERTC_CLK / 8. * - ERTC_WAT_CLK_ERTCCLK_DIV4: ERTC_CLK / 4. * - ERTC_WAT_CLK_ERTCCLK_DIV2: ERTC_CLK / 2. - * - ERTC_WAT_CLK_CK_A_16BITS: CK_A, wakeup counter = ERTC_WAT - * - ERTC_WAT_CLK_CK_A_17BITS: CK_A, wakeup counter = ERTC_WAT + 65535. + * - ERTC_WAT_CLK_CK_B_16BITS: CK_B, wakeup counter = ERTC_WAT + * - ERTC_WAT_CLK_CK_B_17BITS: CK_B, wakeup counter = ERTC_WAT + 65535. * @retval none. */ void ertc_wakeup_clock_set(ertc_wakeup_clock_type clock) @@ -1483,6 +1470,55 @@ flag_status ertc_flag_get(uint32_t flag) } } +/** + * @brief get interrupt flag status. + * @param flag: specifies the flag to check. + * this parameter can be one of the following values: + * - ERTC_ALAF_FLAG: alarm clock a flag. + * - ERTC_ALBF_FLAG: alarm clock b flag. + * - ERTC_WATF_FLAG: wakeup timer flag. + * - ERTC_TSF_FLAG: timestamp flag. + * - ERTC_TP1F_FLAG: tamper detection 1 flag. + * - ERTC_TP2F_FLAG: tamper detection 2 flag. + * @retval the new state of flag (SET or RESET). + */ +flag_status ertc_interrupt_flag_get(uint32_t flag) +{ + __IO uint32_t iten = 0; + + switch(flag) + { + case ERTC_ALAF_FLAG: + iten = ERTC->ctrl_bit.alaien; + break; + case ERTC_ALBF_FLAG: + iten = ERTC->ctrl_bit.albien; + break; + case ERTC_WATF_FLAG: + iten = ERTC->ctrl_bit.watien; + break; + case ERTC_TSF_FLAG: + iten = ERTC->ctrl_bit.tsien; + break; + case ERTC_TP1F_FLAG: + case ERTC_TP2F_FLAG: + iten = ERTC->tamp_bit.tpien; + break; + + default: + break; + } + + if(((ERTC->sts & flag) != (uint32_t)RESET) && (iten)) + { + return SET; + } + else + { + return RESET; + } +} + /** * @brief clear flag status * @param flag: specifies the flag to clear. @@ -1527,13 +1563,7 @@ void ertc_bpr_data_write(ertc_dt_type dt, uint32_t data) reg = ERTC_BASE + 0x50 + (dt * 4); - /* disable write protection */ - ertc_write_protect_disable(); - *(__IO uint32_t *)reg = data; - - /* enable write protection */ - ertc_write_protect_enable(); } /** diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_exint.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_exint.c index bade7c89b7..3269d3badb 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_exint.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_exint.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_exint.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the exint firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -155,6 +153,35 @@ flag_status exint_flag_get(uint32_t exint_line) return status; } +/** + * @brief get exint interrupt flag + * @param exint_line + * this parameter can be one of the following values: + * - EXINT_LINE_0 + * - EXINT_LINE_1 + * ... + * - EXINT_LINE_21 + * - EXINT_LINE_22 + * @retval the new state of exint flag(SET or RESET). + */ +flag_status exint_interrupt_flag_get(uint32_t exint_line) +{ + flag_status status = RESET; + uint32_t exint_flag = 0; + exint_flag = EXINT->intsts & exint_line; + exint_flag = exint_flag & EXINT->inten; + + if((exint_flag != (uint16_t)RESET)) + { + status = SET; + } + else + { + status = RESET; + } + return status; +} + /** * @brief generate exint software interrupt event * @param exint_line diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_flash.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_flash.c index 1003400d75..a49140e67c 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_flash.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_flash.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_flash.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the flash firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -359,41 +357,27 @@ flash_status_type flash_sector_erase(uint32_t sector_address) flash_status_type status = FLASH_OPERATE_DONE; if((sector_address >= FLASH_BANK1_START_ADDR) && (sector_address <= FLASH_BANK1_END_ADDR)) { - /* wait for last operation to be completed */ + FLASH->ctrl_bit.secers = TRUE; + FLASH->addr = sector_address; + FLASH->ctrl_bit.erstr = TRUE; + + /* wait for operation to be completed */ status = flash_bank1_operation_wait_for(ERASE_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* if the previous operation is completed, continue to erase the sector */ - FLASH->ctrl_bit.secers = TRUE; - FLASH->addr = sector_address; - FLASH->ctrl_bit.erstr = TRUE; - - /* wait for operation to be completed */ - status = flash_bank1_operation_wait_for(ERASE_TIMEOUT); - - /* disable the secers bit */ - FLASH->ctrl_bit.secers = FALSE; - } + /* disable the secers bit */ + FLASH->ctrl_bit.secers = FALSE; } else if((sector_address >= FLASH_BANK2_START_ADDR) && (sector_address <= FLASH_BANK2_END_ADDR)) { - /* wait for last operation to be completed */ + FLASH->ctrl2_bit.secers = TRUE; + FLASH->addr2 = sector_address; + FLASH->ctrl2_bit.erstr = TRUE; + + /* wait for operation to be completed */ status = flash_bank2_operation_wait_for(ERASE_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* if the previous operation is completed, continue to erase the sector */ - FLASH->ctrl2_bit.secers = TRUE; - FLASH->addr2 = sector_address; - FLASH->ctrl2_bit.erstr = TRUE; - - /* wait for operation to be completed */ - status = flash_bank2_operation_wait_for(ERASE_TIMEOUT); - - /* disable the secers bit */ - FLASH->ctrl2_bit.secers = FALSE; - } + /* disable the secers bit */ + FLASH->ctrl2_bit.secers = FALSE; } /* return the erase status */ @@ -411,41 +395,27 @@ flash_status_type flash_block_erase(uint32_t block_address) flash_status_type status = FLASH_OPERATE_DONE; if((block_address >= FLASH_BANK1_START_ADDR) && (block_address <= FLASH_BANK1_END_ADDR)) { - /* wait for last operation to be completed */ + FLASH->ctrl_bit.blkers = TRUE; + FLASH->addr = block_address; + FLASH->ctrl_bit.erstr = TRUE; + + /* wait for operation to be completed */ status = flash_bank1_operation_wait_for(ERASE_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* if the previous operation is completed, continue to erase the blkers */ - FLASH->ctrl_bit.blkers = TRUE; - FLASH->addr = block_address; - FLASH->ctrl_bit.erstr = TRUE; - - /* wait for operation to be completed */ - status = flash_bank1_operation_wait_for(ERASE_TIMEOUT); - - /* disable the blkers bit */ - FLASH->ctrl_bit.blkers = FALSE; - } + /* disable the blkers bit */ + FLASH->ctrl_bit.blkers = FALSE; } else if((block_address >= FLASH_BANK2_START_ADDR) && (block_address <= FLASH_BANK2_END_ADDR)) { - /* wait for last operation to be completed */ + FLASH->ctrl2_bit.blkers = TRUE; + FLASH->addr2 = block_address; + FLASH->ctrl2_bit.erstr = TRUE; + + /* wait for operation to be completed */ status = flash_bank2_operation_wait_for(ERASE_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* if the previous operation is completed, continue to erase the blkers */ - FLASH->ctrl2_bit.blkers = TRUE; - FLASH->addr2 = block_address; - FLASH->ctrl2_bit.erstr = TRUE; - - /* wait for operation to be completed */ - status = flash_bank2_operation_wait_for(ERASE_TIMEOUT); - - /* disable the blkers bit */ - FLASH->ctrl2_bit.blkers = FALSE; - } + /* disable the blkers bit */ + FLASH->ctrl2_bit.blkers = FALSE; } /* return the erase status */ @@ -461,21 +431,16 @@ flash_status_type flash_block_erase(uint32_t block_address) flash_status_type flash_internal_all_erase(void) { flash_status_type status = FLASH_OPERATE_DONE; - /* wait for last operation to be completed */ + + FLASH->ctrl_bit.bankers = TRUE; + FLASH->ctrl_bit.erstr = TRUE; + + /* wait for operation to be completed */ status = flash_bank1_operation_wait_for(ERASE_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* if the previous operation is completed, continue to erase bank1 */ - FLASH->ctrl_bit.bankers = TRUE; - FLASH->ctrl_bit.erstr = TRUE; + /* disable the bankers bit */ + FLASH->ctrl_bit.bankers = FALSE; - /* wait for operation to be completed */ - status = flash_bank1_operation_wait_for(ERASE_TIMEOUT); - - /* disable the bankers bit */ - FLASH->ctrl_bit.bankers = FALSE; - } if(status == FLASH_OPERATE_DONE) { /* if the previous operation is completed, continue to erase bank2 */ @@ -501,21 +466,16 @@ flash_status_type flash_internal_all_erase(void) flash_status_type flash_bank1_erase(void) { flash_status_type status = FLASH_OPERATE_DONE; - /* wait for last operation to be completed */ + + FLASH->ctrl_bit.bankers = TRUE; + FLASH->ctrl_bit.erstr = TRUE; + + /* wait for operation to be completed */ status = flash_bank1_operation_wait_for(ERASE_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* if the previous operation is completed, continue to erase bank1 */ - FLASH->ctrl_bit.bankers = TRUE; - FLASH->ctrl_bit.erstr = TRUE; + /* disable the bankers bit */ + FLASH->ctrl_bit.bankers = FALSE; - /* wait for operation to be completed */ - status = flash_bank1_operation_wait_for(ERASE_TIMEOUT); - - /* disable the bankers bit */ - FLASH->ctrl_bit.bankers = FALSE; - } /* return the erase status */ return status; } @@ -529,21 +489,16 @@ flash_status_type flash_bank1_erase(void) flash_status_type flash_bank2_erase(void) { flash_status_type status = FLASH_OPERATE_DONE; - /* wait for last operation to be completed */ + + FLASH->ctrl2_bit.bankers = TRUE; + FLASH->ctrl2_bit.erstr = TRUE; + + /* wait for operation to be completed */ status = flash_bank2_operation_wait_for(ERASE_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* if the previous operation is completed, continue to erase bank2 */ - FLASH->ctrl2_bit.bankers = TRUE; - FLASH->ctrl2_bit.erstr = TRUE; + /* disable the bankers bit */ + FLASH->ctrl2_bit.bankers = FALSE; - /* wait for operation to be completed */ - status = flash_bank2_operation_wait_for(ERASE_TIMEOUT); - - /* disable the bankers bit */ - FLASH->ctrl2_bit.bankers = FALSE; - } /* return the erase status */ return status; } @@ -566,41 +521,36 @@ flash_status_type flash_user_system_data_erase(void) fap_val = 0x0000; } - /* wait for last operation to be completed */ + /* unlock the user system data */ + FLASH->usd_unlock = FLASH_UNLOCK_KEY1; + FLASH->usd_unlock = FLASH_UNLOCK_KEY2; + while(FLASH->ctrl_bit.usdulks==RESET); + + /* erase the user system data */ + FLASH->ctrl_bit.usders = TRUE; + FLASH->ctrl_bit.erstr = TRUE; + + /* wait for operation to be completed */ status = flash_operation_wait_for(ERASE_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* unlock the user system data */ - FLASH->usd_unlock = FLASH_UNLOCK_KEY1; - FLASH->usd_unlock = FLASH_UNLOCK_KEY2; - while(FLASH->ctrl_bit.usdulks==RESET); + /* disable the usders bit */ + FLASH->ctrl_bit.usders = FALSE; - /* erase the user system data */ - FLASH->ctrl_bit.usders = TRUE; - FLASH->ctrl_bit.erstr = TRUE; + if((status == FLASH_OPERATE_DONE) && (fap_val == FAP_RELIEVE_KEY)) + { + /* enable the user system data programming operation */ + FLASH->ctrl_bit.usdprgm = TRUE; + + /* restore the last flash access protection value */ + USD->fap = (uint16_t)fap_val; /* wait for operation to be completed */ - status = flash_operation_wait_for(ERASE_TIMEOUT); + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - /* disable the usders bit */ - FLASH->ctrl_bit.usders = FALSE; - - if((status == FLASH_OPERATE_DONE) && (fap_val == FAP_RELIEVE_KEY)) - { - /* enable the user system data programming operation */ - FLASH->ctrl_bit.usdprgm = TRUE; - - /* restore the last flash access protection value */ - USD->fap = (uint16_t)fap_val; - - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - - /*disable the usdprgm bit */ - FLASH->ctrl_bit.usdprgm = FALSE; - } + /*disable the usdprgm bit */ + FLASH->ctrl_bit.usdprgm = FALSE; } + /* return the status */ return status; } @@ -625,28 +575,23 @@ flash_status_type flash_eopb0_config(flash_usd_eopb0_type data) { flash_status_type status = FLASH_OPERATE_DONE; - /* wait for last operation to be completed */ - status = flash_operation_wait_for(ERASE_TIMEOUT); + /* unlock the user system data */ + FLASH->usd_unlock = FLASH_UNLOCK_KEY1; + FLASH->usd_unlock = FLASH_UNLOCK_KEY2; + while(FLASH->ctrl_bit.usdulks==RESET); - if(status == FLASH_OPERATE_DONE) - { - /* unlock the user system data */ - FLASH->usd_unlock = FLASH_UNLOCK_KEY1; - FLASH->usd_unlock = FLASH_UNLOCK_KEY2; - while(FLASH->ctrl_bit.usdulks==RESET); + /* enable the user system data programming operation */ + FLASH->ctrl_bit.usdprgm = TRUE; - /* enable the user system data programming operation */ - FLASH->ctrl_bit.usdprgm = TRUE; + /* restore the default eopb0 value */ + USD->eopb0 = (uint16_t)data; - /* restore the default eopb0 value */ - USD->eopb0 = (uint16_t)data; + /* wait for operation to be completed */ + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); + /*disable the usdprgm bit */ + FLASH->ctrl_bit.usdprgm = FALSE; - /*disable the usdprgm bit */ - FLASH->ctrl_bit.usdprgm = FALSE; - } /* return the status */ return status; } @@ -663,35 +608,23 @@ flash_status_type flash_word_program(uint32_t address, uint32_t data) flash_status_type status = FLASH_OPERATE_DONE; if((address >= FLASH_BANK1_START_ADDR) && (address <= FLASH_BANK1_END_ADDR)) { - /* wait for last operation to be completed */ + FLASH->ctrl_bit.fprgm = TRUE; + *(__IO uint32_t*)address = data; + /* wait for operation to be completed */ status = flash_bank1_operation_wait_for(PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - FLASH->ctrl_bit.fprgm = TRUE; - *(__IO uint32_t*)address = data; - /* wait for operation to be completed */ - status = flash_bank1_operation_wait_for(PROGRAMMING_TIMEOUT); - - /* disable the fprgm bit */ - FLASH->ctrl_bit.fprgm = FALSE; - } + /* disable the fprgm bit */ + FLASH->ctrl_bit.fprgm = FALSE; } else if((address >= FLASH_BANK2_START_ADDR) && (address <= FLASH_BANK2_END_ADDR)) { - /* wait for last operation to be completed */ + FLASH->ctrl2_bit.fprgm = TRUE; + *(__IO uint32_t*)address = data; + /* wait for operation to be completed */ status = flash_bank2_operation_wait_for(PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - FLASH->ctrl2_bit.fprgm = TRUE; - *(__IO uint32_t*)address = data; - /* wait for operation to be completed */ - status = flash_bank2_operation_wait_for(PROGRAMMING_TIMEOUT); - - /* disable the fprgm bit */ - FLASH->ctrl2_bit.fprgm = FALSE; - } + /* disable the fprgm bit */ + FLASH->ctrl2_bit.fprgm = FALSE; } /* return the program status */ @@ -710,35 +643,23 @@ flash_status_type flash_halfword_program(uint32_t address, uint16_t data) flash_status_type status = FLASH_OPERATE_DONE; if((address >= FLASH_BANK1_START_ADDR) && (address <= FLASH_BANK1_END_ADDR)) { - /* wait for last operation to be completed */ + FLASH->ctrl_bit.fprgm = TRUE; + *(__IO uint16_t*)address = data; + /* wait for operation to be completed */ status = flash_bank1_operation_wait_for(PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - FLASH->ctrl_bit.fprgm = TRUE; - *(__IO uint16_t*)address = data; - /* wait for operation to be completed */ - status = flash_bank1_operation_wait_for(PROGRAMMING_TIMEOUT); - - /* disable the fprgm bit */ - FLASH->ctrl_bit.fprgm = FALSE; - } + /* disable the fprgm bit */ + FLASH->ctrl_bit.fprgm = FALSE; } else if((address >= FLASH_BANK2_START_ADDR) && (address <= FLASH_BANK2_END_ADDR)) { - /* wait for last operation to be completed */ + FLASH->ctrl2_bit.fprgm = TRUE; + *(__IO uint16_t*)address = data; + /* wait for operation to be completed */ status = flash_bank2_operation_wait_for(PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - FLASH->ctrl2_bit.fprgm = TRUE; - *(__IO uint16_t*)address = data; - /* wait for operation to be completed */ - status = flash_bank2_operation_wait_for(PROGRAMMING_TIMEOUT); - - /* disable the fprgm bit */ - FLASH->ctrl2_bit.fprgm = FALSE; - } + /* disable the fprgm bit */ + FLASH->ctrl2_bit.fprgm = FALSE; } /* return the program status */ @@ -758,35 +679,23 @@ flash_status_type flash_byte_program(uint32_t address, uint8_t data) flash_status_type status = FLASH_OPERATE_DONE; if((address >= FLASH_BANK1_START_ADDR) && (address <= FLASH_BANK1_END_ADDR)) { - /* wait for last operation to be completed */ + FLASH->ctrl_bit.fprgm = TRUE; + *(__IO uint8_t*)address = data; + /* wait for operation to be completed */ status = flash_bank1_operation_wait_for(PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - FLASH->ctrl_bit.fprgm = TRUE; - *(__IO uint8_t*)address = data; - /* wait for operation to be completed */ - status = flash_bank1_operation_wait_for(PROGRAMMING_TIMEOUT); - - /* disable the fprgm bit */ - FLASH->ctrl_bit.fprgm = FALSE; - } + /* disable the fprgm bit */ + FLASH->ctrl_bit.fprgm = FALSE; } else if((address >= FLASH_BANK2_START_ADDR) && (address <= FLASH_BANK2_END_ADDR)) { - /* wait for last operation to be completed */ + FLASH->ctrl2_bit.fprgm = TRUE; + *(__IO uint8_t*)address = data; + /* wait for operation to be completed */ status = flash_bank2_operation_wait_for(PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - FLASH->ctrl2_bit.fprgm = TRUE; - *(__IO uint8_t*)address = data; - /* wait for operation to be completed */ - status = flash_bank2_operation_wait_for(PROGRAMMING_TIMEOUT); - - /* disable the fprgm bit */ - FLASH->ctrl2_bit.fprgm = FALSE; - } + /* disable the fprgm bit */ + FLASH->ctrl2_bit.fprgm = FALSE; } /* return the program status */ return status; @@ -802,24 +711,28 @@ flash_status_type flash_byte_program(uint32_t address, uint8_t data) flash_status_type flash_user_system_data_program(uint32_t address, uint8_t data) { flash_status_type status = FLASH_OPERATE_DONE; - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) + + if(address == USD_BASE) { - /* unlock the user system data */ - FLASH->usd_unlock = FLASH_UNLOCK_KEY1; - FLASH->usd_unlock = FLASH_UNLOCK_KEY2; - while(FLASH->ctrl_bit.usdulks==RESET); - - /* enable the user system data programming operation */ - FLASH->ctrl_bit.usdprgm = TRUE; - *(__IO uint16_t*)address = data; - - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - - /* disable the usdprgm bit */ - FLASH->ctrl_bit.usdprgm = FALSE; + if(data != 0xA5) + return FLASH_OPERATE_DONE; } + + /* unlock the user system data */ + FLASH->usd_unlock = FLASH_UNLOCK_KEY1; + FLASH->usd_unlock = FLASH_UNLOCK_KEY2; + while(FLASH->ctrl_bit.usdulks==RESET); + + /* enable the user system data programming operation */ + FLASH->ctrl_bit.usdprgm = TRUE; + *(__IO uint16_t*)address = data; + + /* wait for operation to be completed */ + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); + + /* disable the usdprgm bit */ + FLASH->ctrl_bit.usdprgm = FALSE; + /* return the user system data program status */ return status; } @@ -842,73 +755,69 @@ flash_status_type flash_epp_set(uint32_t *sector_bits) epp_data[1] = (uint16_t)((sector_bits[0] >> 8) & 0xFF); epp_data[2] = (uint16_t)((sector_bits[0] >> 16) & 0xFF); epp_data[3] = (uint16_t)((sector_bits[0] >> 24) & 0xFF); - /* wait for last operation to be completed */ + + /* unlock the user system data */ + FLASH->usd_unlock = FLASH_UNLOCK_KEY1; + FLASH->usd_unlock = FLASH_UNLOCK_KEY2; + while(FLASH->ctrl_bit.usdulks==RESET); + + FLASH->ctrl_bit.usdprgm = TRUE; + USD->epp0 = epp_data[0]; + /* wait for operation to be completed */ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); if(status == FLASH_OPERATE_DONE) { - /* unlock the user system data */ - FLASH->usd_unlock = FLASH_UNLOCK_KEY1; - FLASH->usd_unlock = FLASH_UNLOCK_KEY2; - while(FLASH->ctrl_bit.usdulks==RESET); - - FLASH->ctrl_bit.usdprgm = TRUE; - USD->epp0 = epp_data[0]; + USD->epp1 = epp_data[1]; /* wait for operation to be completed */ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - - if(status == FLASH_OPERATE_DONE) - { - USD->epp1 = epp_data[1]; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - } - if(status == FLASH_OPERATE_DONE) - { - USD->epp2 = epp_data[2]; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - } - if(status == FLASH_OPERATE_DONE) - { - USD->epp3 = epp_data[3]; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - } - - sector_bits[1] = (uint32_t)(~sector_bits[1]); - epp_data[0] = (uint16_t)((sector_bits[1] >> 0) & 0xFF); - epp_data[1] = (uint16_t)((sector_bits[1] >> 8) & 0xFF); - epp_data[2] = (uint16_t)((sector_bits[1] >> 16) & 0xFF); - epp_data[3] = (uint16_t)((sector_bits[1] >> 24) & 0xFF); - if(status == FLASH_OPERATE_DONE) - { - USD->epp4 = epp_data[0]; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - } - if(status == FLASH_OPERATE_DONE) - { - USD->epp5 = epp_data[1]; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - } - if(status == FLASH_OPERATE_DONE) - { - USD->epp6 = epp_data[2]; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - } - if(status == FLASH_OPERATE_DONE) - { - USD->epp7 = epp_data[3]; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - } - - /* disable the usdprgm bit */ - FLASH->ctrl_bit.usdprgm = FALSE; } + if(status == FLASH_OPERATE_DONE) + { + USD->epp2 = epp_data[2]; + /* wait for operation to be completed */ + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); + } + if(status == FLASH_OPERATE_DONE) + { + USD->epp3 = epp_data[3]; + /* wait for operation to be completed */ + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); + } + + sector_bits[1] = (uint32_t)(~sector_bits[1]); + epp_data[0] = (uint16_t)((sector_bits[1] >> 0) & 0xFF); + epp_data[1] = (uint16_t)((sector_bits[1] >> 8) & 0xFF); + epp_data[2] = (uint16_t)((sector_bits[1] >> 16) & 0xFF); + epp_data[3] = (uint16_t)((sector_bits[1] >> 24) & 0xFF); + if(status == FLASH_OPERATE_DONE) + { + USD->epp4 = epp_data[0]; + /* wait for operation to be completed */ + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); + } + if(status == FLASH_OPERATE_DONE) + { + USD->epp5 = epp_data[1]; + /* wait for operation to be completed */ + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); + } + if(status == FLASH_OPERATE_DONE) + { + USD->epp6 = epp_data[2]; + /* wait for operation to be completed */ + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); + } + if(status == FLASH_OPERATE_DONE) + { + USD->epp7 = epp_data[3]; + /* wait for operation to be completed */ + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); + } + + /* disable the usdprgm bit */ + FLASH->ctrl_bit.usdprgm = FALSE; + /* return the erase/program protection operation status */ return status; } @@ -937,43 +846,41 @@ void flash_epp_status_get(uint32_t *sector_bits) flash_status_type flash_fap_enable(confirm_state new_state) { flash_status_type status = FLASH_OPERATE_DONE; + + /* unlock the user system data */ + FLASH->usd_unlock = FLASH_UNLOCK_KEY1; + FLASH->usd_unlock = FLASH_UNLOCK_KEY2; + while(FLASH->ctrl_bit.usdulks==RESET); + + FLASH->ctrl_bit.usders = TRUE; + FLASH->ctrl_bit.erstr = TRUE; + /* wait for operation to be completed */ status = flash_operation_wait_for(ERASE_TIMEOUT); + + /* disable the usders bit */ + FLASH->ctrl_bit.usders = FALSE; + if(status == FLASH_OPERATE_DONE) { - /* unlock the user system data */ - FLASH->usd_unlock = FLASH_UNLOCK_KEY1; - FLASH->usd_unlock = FLASH_UNLOCK_KEY2; - while(FLASH->ctrl_bit.usdulks==RESET); + /* enable the user system data programming operation */ + FLASH->ctrl_bit.usdprgm = TRUE; - FLASH->ctrl_bit.usders = TRUE; - FLASH->ctrl_bit.erstr = TRUE; - /* wait for operation to be completed */ + /* restore the default eopb0 value */ + USD->eopb0 = (uint16_t)0x0002; + + /* Wait for operation to be completed */ status = flash_operation_wait_for(ERASE_TIMEOUT); - /* disable the usders bit */ - FLASH->ctrl_bit.usders = FALSE; - - if(status == FLASH_OPERATE_DONE) + if(new_state == FALSE) { - /* enable the user system data programming operation */ - FLASH->ctrl_bit.usdprgm = TRUE; - - /* restore the default eopb0 value */ - USD->eopb0 = (uint16_t)0x0002; - + USD->fap = FAP_RELIEVE_KEY; /* Wait for operation to be completed */ status = flash_operation_wait_for(ERASE_TIMEOUT); - - if(new_state == FALSE) - { - USD->fap = FAP_RELIEVE_KEY; - /* Wait for operation to be completed */ - status = flash_operation_wait_for(ERASE_TIMEOUT); - } - /* disable the usdprgm bit */ - FLASH->ctrl_bit.usdprgm = FALSE; } + /* disable the usdprgm bit */ + FLASH->ctrl_bit.usdprgm = FALSE; } + /* return the flash access protection operation status */ return status; } @@ -1022,26 +929,22 @@ flag_status flash_fap_status_get(void) flash_status_type flash_ssb_set(uint8_t usd_ssb) { flash_status_type status = FLASH_OPERATE_DONE; - /* wait for last operation to be completed */ + + /* unlock the user system data */ + FLASH->usd_unlock = FLASH_UNLOCK_KEY1; + FLASH->usd_unlock = FLASH_UNLOCK_KEY2; + while(FLASH->ctrl_bit.usdulks==RESET); + + /* enable the user system data programming operation */ + FLASH->ctrl_bit.usdprgm = TRUE; + + USD->ssb = usd_ssb; + /* wait for operation to be completed */ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - if(status == FLASH_OPERATE_DONE) - { - /* unlock the user system data */ - FLASH->usd_unlock = FLASH_UNLOCK_KEY1; - FLASH->usd_unlock = FLASH_UNLOCK_KEY2; - while(FLASH->ctrl_bit.usdulks==RESET); + /* disable the usdprgm bit */ + FLASH->ctrl_bit.usdprgm = FALSE; - /* enable the user system data programming operation */ - FLASH->ctrl_bit.usdprgm = TRUE; - - USD->ssb = usd_ssb; - /* wait for operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - - /* disable the usdprgm bit */ - FLASH->ctrl_bit.usdprgm = FALSE; - } /* return the user system data program status */ return status; } @@ -1097,30 +1000,32 @@ flash_status_type flash_slib_enable(uint32_t pwd, uint16_t start_sector, uint16_ { uint32_t slib_range; flash_status_type status = FLASH_OPERATE_DONE; - /* wait for last operation to be completed */ - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); /*check range param limits*/ - if((start_sector>=inst_start_sector) || ((inst_start_sector > end_sector) && \ + if((start_sector > inst_start_sector) || ((inst_start_sector > end_sector) && \ (inst_start_sector != 0xFFFF)) || (start_sector > end_sector)) return FLASH_PROGRAM_ERROR; + /* unlock slib cfg register */ + FLASH->slib_unlock = SLIB_UNLOCK_KEY; + while(FLASH->slib_misc_sts_bit.slib_ulkf==RESET); + + /* configure slib, set pwd and range */ + FLASH->slib_set_pwd = pwd; + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); if(status == FLASH_OPERATE_DONE) { - /* unlock slib cfg register */ - FLASH->slib_unlock = SLIB_UNLOCK_KEY; - while(FLASH->slib_misc_sts_bit.slib_ulkf==RESET); - - /* configure slib, set pwd and range */ - FLASH->slib_set_pwd = pwd; - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); slib_range = ((uint32_t)(end_sector << 16) & FLASH_SLIB_END_SECTOR) | (start_sector & FLASH_SLIB_START_SECTOR); FLASH->slib_set_range0 = slib_range; status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); - slib_range = (inst_start_sector & FLASH_SLIB_INST_START_SECTOR) | 0x80000000; - FLASH->slib_set_range1 = slib_range; - status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); + if(status == FLASH_OPERATE_DONE) + { + slib_range = (inst_start_sector & FLASH_SLIB_INST_START_SECTOR) | 0x80000000; + FLASH->slib_set_range1 = slib_range; + status = flash_operation_wait_for(PROGRAMMING_TIMEOUT); + } } + return status; } diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_gpio.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_gpio.c index e6af8067db..1250c81d8d 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_gpio.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_gpio.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_gpio.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the gpio firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -357,7 +355,7 @@ void gpio_bits_write(gpio_type *gpio_x, uint16_t pins, confirm_state bit_state) * @param port_value: specifies the value to be written to the port output data register. * @retval none */ -void gpio_port_wirte(gpio_type *gpio_x, uint16_t port_value) +void gpio_port_write(gpio_type *gpio_x, uint16_t port_value) { gpio_x->odt = port_value; } diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_i2c.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_i2c.c index 5bf12026e3..6b3de028ff 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_i2c.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_i2c.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_i2c.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the i2c firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -122,12 +120,12 @@ void i2c_own_address1_set(i2c_type *i2c_x, i2c_address_mode_type mode, uint16_t * this parameter can be one of the following values: * - I2C_ADDR2_NOMASK: compare bit [7:1]. * - I2C_ADDR2_MASK01: only compare bit [7:2]. - * - I2C_ADDR2_MASK02: only compare bit [7:2]. - * - I2C_ADDR2_MASK03: only compare bit [7:3]. - * - I2C_ADDR2_MASK04: only compare bit [7:4]. - * - I2C_ADDR2_MASK05: only compare bit [7:5]. - * - I2C_ADDR2_MASK06: only compare bit [7:6]. - * - I2C_ADDR2_MASK07: only compare bit [7]. + * - I2C_ADDR2_MASK02: only compare bit [7:3]. + * - I2C_ADDR2_MASK03: only compare bit [7:4]. + * - I2C_ADDR2_MASK04: only compare bit [7:5]. + * - I2C_ADDR2_MASK05: only compare bit [7:6]. + * - I2C_ADDR2_MASK06: only compare bit [7]. + * - I2C_ADDR2_MASK07: response all addresses other than those reserved for i2c. * @retval none */ void i2c_own_address2_set(i2c_type *i2c_x, uint8_t address, i2c_addr2_mask_type mask) @@ -271,11 +269,13 @@ void i2c_transfer_dir_set(i2c_type *i2c_x, i2c_transfer_dir_type i2c_direction) } /** - * @brief get the i2c slave received direction. + * @brief slave get the i2c transfer direction. * @param i2c_x: to select the i2c peripheral. * this parameter can be one of the following values: * I2C1, I2C2, I2C3. - * @retval the value of the received direction. + * @retval the value of the slave direction + * - I2C_DIR_TRANSMIT: master request a write transfer, slave enters receiver mode. + * - I2C_DIR_RECEIVE: master request a read transfer, slave enters transmitter mode. */ i2c_transfer_dir_type i2c_transfer_dir_get(i2c_type *i2c_x) { @@ -595,14 +595,14 @@ void i2c_dma_enable(i2c_type *i2c_x, i2c_dma_request_type dma_req, confirm_state * - I2C_AUTO_STOP_MODE: auto generate stop mode. * - I2C_SOFT_STOP_MODE: soft generate stop mode. * - I2C_RELOAD_MODE: reload mode. - * @param start_stop: config gen start condition mode. + * @param start: config gen start condition mode. * this parameter can be one of the following values: * - I2C_WITHOUT_START: transfer data without start condition. * - I2C_GEN_START_READ: read data and generate start. * - I2C_GEN_START_WRITE: send data and generate start. * @retval none */ -void i2c_transmit_set(i2c_type *i2c_x, uint16_t address, uint8_t cnt, i2c_reload_stop_mode_type rld_stop, i2c_start_stop_mode_type start_stop) +void i2c_transmit_set(i2c_type *i2c_x, uint16_t address, uint8_t cnt, i2c_reload_stop_mode_type rld_stop, i2c_start_mode_type start) { uint32_t temp; @@ -613,7 +613,7 @@ void i2c_transmit_set(i2c_type *i2c_x, uint16_t address, uint8_t cnt, i2c_reload temp &= ~0x03FF67FF; /* transfer mode and address set */ - temp |= address | rld_stop | start_stop; + temp |= address | rld_stop | start; /* transfer counter set */ temp |= (uint32_t)cnt << 16; @@ -708,6 +708,77 @@ flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag) } } +/** + * @brief get interrupt flag status. + * @param i2c_x: to select the i2c peripheral. + * this parameter can be one of the following values: + * I2C1, I2C2, I2C3. + * @param flag: specifies the flag to check. + * this parameter can be one of the following values: + * - I2C_TDBE_FLAG: transmit data buffer empty flag. + * - I2C_TDIS_FLAG: send interrupt status. + * - I2C_RDBF_FLAG: receive data buffer full flag. + * - I2C_ADDRF_FLAG: 0~7 bit address match flag. + * - I2C_ACKFAIL_FLAG: acknowledge failure flag. + * - I2C_STOPF_FLAG: stop condition generation complete flag. + * - I2C_TDC_FLAG: transmit data complete flag. + * - I2C_TCRLD_FLAG: transmission is complete, waiting to load data. + * - I2C_BUSERR_FLAG: bus error flag. + * - I2C_ARLOST_FLAG: arbitration lost flag. + * - I2C_OUF_FLAG: overflow or underflow flag. + * - I2C_PECERR_FLAG: pec receive error flag. + * - I2C_TMOUT_FLAG: smbus timeout flag. + * - I2C_ALERTF_FLAG: smbus alert flag. + * @retval the new state of flag (SET or RESET). + */ +flag_status i2c_interrupt_flag_get(i2c_type *i2c_x, uint32_t flag) +{ + __IO uint32_t iten = 0; + + switch(flag) + { + case I2C_TDIS_FLAG: + iten = i2c_x->ctrl1_bit.tdien; + break; + case I2C_RDBF_FLAG: + iten = i2c_x->ctrl1_bit.rdien; + break; + case I2C_ADDRF_FLAG: + iten = i2c_x->ctrl1_bit.addrien; + break; + case I2C_ACKFAIL_FLAG: + iten = i2c_x->ctrl1_bit.ackfailien; + break; + case I2C_STOPF_FLAG: + iten = i2c_x->ctrl1_bit.stopien; + break; + case I2C_TDC_FLAG: + case I2C_TCRLD_FLAG: + iten = i2c_x->ctrl1_bit.tdcien; + break; + case I2C_BUSERR_FLAG: + case I2C_ARLOST_FLAG: + case I2C_OUF_FLAG: + case I2C_PECERR_FLAG: + case I2C_TMOUT_FLAG: + case I2C_ALERTF_FLAG: + iten = i2c_x->ctrl1_bit.errien; + break; + + default: + break; + } + + if(((i2c_x->sts & flag) != RESET) && (iten)) + { + return SET; + } + else + { + return RESET; + } +} + /** * @brief clear flag status * @param i2c_x: to select the i2c peripheral. diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_misc.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_misc.c index c94394eca8..3fd5305895 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_misc.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_misc.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_misc.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the misc firmware library ************************************************************************** * Copyright notice & Disclaimer diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_pwc.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_pwc.c index 0ea1c278d5..5c106ddaea 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_pwc.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_pwc.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_pwc.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the pwc firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -226,10 +224,13 @@ void pwc_standby_mode_enter(void) PWC->ctrl_bit.clswef = TRUE; PWC->ctrl_bit.lpsel = TRUE; SCB->SCR |= 0x04; -#if defined (__CC_ARM) +#if defined (__ARMCC_VERSION) __force_stores(); #endif - __WFI(); + while(1) + { + __WFI(); + } } /** diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_qspi.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_qspi.c index e46c06506a..7ee585c1d3 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_qspi.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_qspi.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_qspi.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contain all the functions for qspi firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -41,6 +39,27 @@ * @{ */ +/** + * @brief deinitialize the qspi peripheral registers to their default reset values. + * @param qspi_x: select the qspi peripheral. + * this parameter can be one of the following values: + * QSPI1,QSPI2. + * @retval none + */ +void qspi_reset(qspi_type* qspi_x) +{ + if(qspi_x == QSPI1) + { + crm_periph_reset(CRM_QSPI1_PERIPH_RESET, TRUE); + crm_periph_reset(CRM_QSPI1_PERIPH_RESET, FALSE); + } + else if(qspi_x == QSPI2) + { + crm_periph_reset(CRM_QSPI2_PERIPH_RESET, TRUE); + crm_periph_reset(CRM_QSPI2_PERIPH_RESET, FALSE); + } +} + /** * @brief enable/disable encryption for qspi. * @note the function must be configured only when qspi in command-port mode!!! @@ -67,7 +86,7 @@ void qspi_encryption_enable(qspi_type* qspi_x, confirm_state new_state) * - QSPI_SCK_MODE_3 * @retval none */ -void qspi_sck_mode_set( qspi_type* qspi_x, qspi_clk_mode_type new_mode) +void qspi_sck_mode_set(qspi_type* qspi_x, qspi_clk_mode_type new_mode) { qspi_x->ctrl_bit.sckmode = new_mode; } @@ -102,6 +121,8 @@ void qspi_clk_division_set(qspi_type* qspi_x, qspi_clk_div_type new_clkdiv) * this parameter can be one of the following values: * QSPI1,QSPI2. * @param new_state (TRUE or FALSE) + * TRUE: disable cache + * FALSE: enable cache * @retval none */ void qspi_xip_cache_bypass_set(qspi_type* qspi_x, confirm_state new_state) @@ -133,7 +154,7 @@ void qspi_interrupt_enable(qspi_type* qspi_x, confirm_state new_state) * - QSPI_RXFIFORDY_FLAG * - QSPI_TXFIFORDY_FLAG * - QSPI_CMDSTS_FLAG - * @retval the new state of usart_flag (SET or RESET). + * @retval the new state of the flag (SET or RESET). */ flag_status qspi_flag_get(qspi_type* qspi_x, uint32_t flag) { @@ -155,6 +176,24 @@ flag_status qspi_flag_get(qspi_type* qspi_x, uint32_t flag) return bit_status; } +/** + * @brief get interrupt flags. + * @param qspi_x: select the qspi peripheral. + * this parameter can be one of the following values: + * QSPI1,QSPI2. + * @param flag: only QSPI_CMDSTS_FLAG valid. + * @retval the new state of the flag (SET or RESET). + */ +flag_status qspi_interrupt_flag_get(qspi_type* qspi_x, uint32_t flag) +{ + if(QSPI_CMDSTS_FLAG != flag) + return RESET; + if(qspi_x->cmdsts_bit.cmdsts && qspi_x->ctrl2_bit.cmdie) + return SET; + else + return RESET; +} + /** * @brief clear flags * @param qspi_x: select the qspi peripheral. @@ -165,7 +204,7 @@ flag_status qspi_flag_get(qspi_type* qspi_x, uint32_t flag) * - QSPI_CMDSTS_FLAG * @retval none */ -void qspi_flag_clear( qspi_type* qspi_x, uint32_t flag) +void qspi_flag_clear(qspi_type* qspi_x, uint32_t flag) { qspi_x->cmdsts = QSPI_CMDSTS_FLAG; } @@ -180,7 +219,7 @@ void qspi_flag_clear( qspi_type* qspi_x, uint32_t flag) * this parameter can be one of the following values: * - QSPI_DMA_FIFO_THOD_WORD08 * - QSPI_DMA_FIFO_THOD_WORD16 - * - QSPI_DMA_FIFO_THOD_WORD32 + * - QSPI_DMA_FIFO_THOD_WORD24 * @retval none */ void qspi_dma_rx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_threshold) @@ -198,7 +237,7 @@ void qspi_dma_rx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_th * this parameter can be one of the following values: * - QSPI_DMA_FIFO_THOD_WORD08 * - QSPI_DMA_FIFO_THOD_WORD16 - * - QSPI_DMA_FIFO_THOD_WORD32 + * - QSPI_DMA_FIFO_THOD_WORD24 * @retval none */ void qspi_dma_tx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_threshold) @@ -253,21 +292,35 @@ void qspi_busy_config(qspi_type* qspi_x, qspi_busy_pos_type busy_pos) */ void qspi_xip_enable(qspi_type* qspi_x, confirm_state new_state) { + register uint16_t dly=0; /* skip if state is no change */ if(new_state == (confirm_state)(qspi_x->ctrl_bit.xipsel)) { return; } - /* wait until tx fifo emoty*/ + /* wait until tx fifo is empty*/ while(qspi_x->fifosts_bit.txfifordy == 0); + /* make sure IO is transmitted */ + dly = 64; + while(dly--) + { + __NOP(); + } + /* flush and reset qspi state */ qspi_x->ctrl_bit.xiprcmdf = 1; /* wait until action is finished */ while(qspi_x->ctrl_bit.abort); + /* make sure IO is transmitted */ + dly = 64; + while(dly--) + { + __NOP(); + } /* set xip mode to new state */ qspi_x->ctrl_bit.xipsel = new_state; @@ -414,6 +467,20 @@ void qspi_word_write(qspi_type* qspi_x, uint32_t value) qspi_x->dt = value; } +/** + * @brief enable auto input sampling phase correction + * @param qspi_x: select the qspi peripheral. + * @retval none. + */ +void qspi_auto_ispc_enable(qspi_type* qspi_x) +{ + qspi_x->ctrl3_bit.ispc = TRUE; + if(qspi_x == QSPI1) + qspi_x->ctrl3_bit.ispd = 56; + else if(qspi_x == QSPI2) + qspi_x->ctrl3_bit.ispd = 50; +} + /** * @} */ diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_scfg.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_scfg.c index 3d31f26f2f..9ad6c0093c 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_scfg.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_scfg.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_scfg.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the system config firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -72,8 +70,6 @@ void scfg_xmc_mapping_swap_set(scfg_xmc_swap_type xmc_swap) * @param source * this parameter can be one of the following values: * - SCFG_IR_SOURCE_TMR10 - * - SCFG_IR_SOURCE_USART1 - * - SCFG_IR_SOURCE_USART2 * @param polarity * this parameter can be one of the following values: * - SCFG_IR_POLARITY_NO_AFFECTE diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_sdio.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_sdio.c index f5b53efa38..a22a280798 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_sdio.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_sdio.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_sdio.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the sdio firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -82,22 +80,11 @@ void sdio_power_set(sdio_type *sdio_x, sdio_power_state_type power_state) * @param sdio_x: to select the sdio peripheral. * this parameter can be one of the following values: * SDIO1, SDIO2. - * @retval flag_status (SET or RESET) + * @retval sdio_power_state_type (SDIO_POWER_ON or SDIO_POWER_OFF) */ -flag_status sdio_power_status_get(sdio_type *sdio_x) +sdio_power_state_type sdio_power_status_get(sdio_type *sdio_x) { - flag_status flag = RESET; - - if(sdio_x->pwrctrl_bit.ps == SDIO_POWER_ON) - { - flag = SET; - } - else if(sdio_x->pwrctrl_bit.ps == SDIO_POWER_OFF) - { - flag = RESET; - } - - return flag; + return (sdio_power_state_type)(sdio_x->pwrctrl_bit.ps); } /** @@ -254,6 +241,50 @@ void sdio_interrupt_enable(sdio_type *sdio_x, uint32_t int_opt, confirm_state n } } +/** + * @brief get sdio interrupt flag. + * @param sdio_x: to select the sdio peripheral. + * this parameter can be one of the following values: + * SDIO1, SDIO2. + * @param flag + * this parameter can be one of the following values: + * - SDIO_CMDFAIL_FLAG + * - SDIO_DTFAIL_FLAG + * - SDIO_CMDTIMEOUT_FLAG + * - SDIO_DTTIMEOUT_FLAG + * - SDIO_TXERRU_FLAG + * - SDIO_RXERRO_FLAG + * - SDIO_CMDRSPCMPL_FLAG + * - SDIO_CMDCMPL_FLAG + * - SDIO_DTCMPL_FLAG + * - SDIO_SBITERR_FLAG + * - SDIO_DTBLKCMPL_FLAG + * - SDIO_DOCMD_FLAG + * - SDIO_DOTX_FLAG + * - SDIO_DORX_FLAG + * - SDIO_TXBUFH_FLAG + * - SDIO_RXBUFH_FLAG + * - SDIO_TXBUFF_FLAG + * - SDIO_RXBUFF_FLAG + * - SDIO_TXBUFE_FLAG + * - SDIO_RXBUFE_FLAG + * - SDIO_TXBUF_FLAG + * - SDIO_RXBUF_FLAG + * - SDIO_SDIOIF_FLAG + * @retval flag_status (SET or RESET) + */ +flag_status sdio_interrupt_flag_get(sdio_type *sdio_x, uint32_t flag) +{ + flag_status status = RESET; + + if((sdio_x->inten & flag) && (sdio_x->sts & flag)) + { + status = SET; + } + + return status; +} + /** * @brief get sdio flag. * @param sdio_x: to select the sdio peripheral. diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_spi.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_spi.c index abc26cd272..e759e32b61 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_spi.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_spi.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_spi.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the spi firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -594,6 +592,76 @@ flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag) return status; } +/** + * @brief get interrupt flag of the specified spi/i2s peripheral. + * @param spi_x: select the spi/i2s peripheral. + * this parameter can be one of the following values: + * SPI1, SPI2, SPI3 ,SPI4 , I2S2EXT, I2S3EXT + * @param spi_i2s_flag: select the spi/i2s flag + * this parameter can be one of the following values: + * - SPI_I2S_RDBF_FLAG + * - SPI_I2S_TDBE_FLAG + * - I2S_TUERR_FLAG (this flag only use in i2s mode) + * - SPI_CCERR_FLAG (this flag only use in spi mode) + * - SPI_MMERR_FLAG (this flag only use in spi mode) + * - SPI_I2S_ROERR_FLAG + * - SPI_CSPAS_FLAG + * @retval the new state of spi/i2s flag + */ +flag_status spi_i2s_interrupt_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag) +{ + flag_status status = RESET; + + switch(spi_i2s_flag) + { + case SPI_I2S_RDBF_FLAG: + if(spi_x->sts_bit.rdbf && spi_x->ctrl2_bit.rdbfie) + { + status = SET; + } + break; + case SPI_I2S_TDBE_FLAG: + if(spi_x->sts_bit.tdbe && spi_x->ctrl2_bit.tdbeie) + { + status = SET; + } + break; + case I2S_TUERR_FLAG: + if(spi_x->sts_bit.tuerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_CCERR_FLAG: + if(spi_x->sts_bit.ccerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_MMERR_FLAG: + if(spi_x->sts_bit.mmerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_I2S_ROERR_FLAG: + if(spi_x->sts_bit.roerr && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + case SPI_CSPAS_FLAG: + if(spi_x->sts_bit.cspas && spi_x->ctrl2_bit.errie) + { + status = SET; + } + break; + default: + break; + }; + return status; +} + /** * @brief clear flag of the specified spi/i2s peripheral. * @param spi_x: select the spi/i2s peripheral. @@ -615,25 +683,23 @@ flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag) */ void spi_i2s_flag_clear(spi_type* spi_x, uint32_t spi_i2s_flag) { - volatile uint32_t temp = 0; - temp = temp; if(spi_i2s_flag == SPI_CCERR_FLAG) spi_x->sts = ~SPI_CCERR_FLAG; else if(spi_i2s_flag == SPI_I2S_RDBF_FLAG) - temp = REG32(&spi_x->dt); + UNUSED(spi_x->dt); else if(spi_i2s_flag == I2S_TUERR_FLAG) - temp = REG32(&spi_x->sts); + UNUSED(spi_x->sts); else if(spi_i2s_flag == SPI_CSPAS_FLAG) - temp = REG32(&spi_x->sts); + UNUSED(spi_x->sts); else if(spi_i2s_flag == SPI_MMERR_FLAG) { - temp = REG32(&spi_x->sts); + UNUSED(spi_x->sts); spi_x->ctrl1 = spi_x->ctrl1; } else if(spi_i2s_flag == SPI_I2S_ROERR_FLAG) { - temp = REG32(&spi_x->dt); - temp = REG32(&spi_x->sts); + UNUSED(spi_x->dt); + UNUSED(spi_x->sts); } } diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_tmr.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_tmr.c index cc62736683..063f0563db 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_tmr.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_tmr.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_tmr.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the tmr firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -262,14 +260,10 @@ void tmr_cnt_dir_set(tmr_type *tmr_x, tmr_count_mode_type tmr_cnt_dir) * @param tmr_rpr_value (0x0000~0xFFFF) * @retval none */ -void tmr_repetition_counter_set(tmr_type *tmr_x, uint8_t tmr_rpr_value) +void tmr_repetition_counter_set(tmr_type *tmr_x, uint16_t tmr_rpr_value) { /* set the repetition counter value */ - if((tmr_x == TMR1) || (tmr_x == TMR8)) - - { - tmr_x->rpr_bit.rpr = tmr_rpr_value; - } + tmr_x->rpr_bit.rpr = tmr_rpr_value; } /** @@ -307,8 +301,7 @@ uint32_t tmr_counter_value_get(tmr_type *tmr_x) * this parameter can be one of the following values: * TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8, * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14, TMR20 - * @param tmr_div_value (for 16 bit tmr 0x0000~0xFFFF, - * for 32 bit tmr 0x0000_0000~0xFFFF_FFFF) + * @param tmr_div_value (0x0000~0xFFFF) * @retval none */ void tmr_div_value_set(tmr_type *tmr_x, uint32_t tmr_div_value) @@ -350,23 +343,23 @@ uint32_t tmr_div_value_get(tmr_type *tmr_x) void tmr_output_channel_config(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \ tmr_output_config_type *tmr_output_struct) { - uint16_t channel_index = 0, channel_c_index = 0, channel = 0; + uint16_t channel_index = 0, channel_c_index = 0, channel = 0, chx_offset, chcx_offset; + + chx_offset = (8 + tmr_channel); + chcx_offset = (9 + tmr_channel); /* get channel idle state bit position in ctrl2 register */ - channel_index = (uint16_t)(tmr_output_struct->oc_idle_state << (8 + tmr_channel)); + channel_index = (uint16_t)(tmr_output_struct->oc_idle_state << chx_offset); /* get channel complementary idle state bit position in ctrl2 register */ - channel_c_index = (uint16_t)(tmr_output_struct->occ_idle_state << (9 + tmr_channel)); + channel_c_index = (uint16_t)(tmr_output_struct->occ_idle_state << chcx_offset); - if((tmr_x == TMR1) || (tmr_x == TMR8)) - { - /* set output channel complementary idle state */ - tmr_x->ctrl2 &= ~channel_c_index; - tmr_x->ctrl2 |= channel_c_index; - } + /* set output channel complementary idle state */ + tmr_x->ctrl2 &= ~(1<ctrl2 |= channel_c_index; /* set output channel idle state */ - tmr_x->ctrl2 &= ~channel_index; + tmr_x->ctrl2 &= ~(1<ctrl2 |= channel_index; /* set channel output mode */ @@ -398,38 +391,38 @@ void tmr_output_channel_config(tmr_type *tmr_x, tmr_channel_select_type tmr_chan break; } + chx_offset = ((tmr_channel * 2) + 1); + chcx_offset = ((tmr_channel * 2) + 3); + /* get channel polarity bit position in cctrl register */ - channel_index = (uint16_t)(tmr_output_struct->oc_polarity << ((tmr_channel * 2) + 1)); + channel_index = (uint16_t)(tmr_output_struct->oc_polarity << chx_offset); /* get channel complementary polarity bit position in cctrl register */ - channel_c_index = (uint16_t)(tmr_output_struct->occ_polarity << ((tmr_channel * 2) + 3)); + channel_c_index = (uint16_t)(tmr_output_struct->occ_polarity << chcx_offset); - if((tmr_x == TMR1) || (tmr_x == TMR8)) - { - /* set output channel complementary polarity */ - tmr_x->cctrl &= ~channel_c_index; - tmr_x->cctrl |= channel_c_index; - } + /* set output channel complementary polarity */ + tmr_x->cctrl &= ~(1<cctrl |= channel_c_index; /* set output channel polarity */ - tmr_x->cctrl &= ~channel_index; + tmr_x->cctrl &= ~(1<cctrl |= channel_index; + chx_offset = (tmr_channel * 2); + chcx_offset = ((tmr_channel * 2) + 2); + /* get channel enable bit position in cctrl register */ channel_index = (uint16_t)(tmr_output_struct->oc_output_state << (tmr_channel * 2)); /* get channel complementary enable bit position in cctrl register */ channel_c_index = (uint16_t)(tmr_output_struct->occ_output_state << ((tmr_channel * 2) + 2)); - if((tmr_x == TMR1) || (tmr_x == TMR8)) - { - /* set output channel complementary enable bit */ - tmr_x->cctrl &= ~channel_c_index; - tmr_x->cctrl |= channel_c_index; - } + /* set output channel complementary enable bit */ + tmr_x->cctrl &= ~(1<cctrl |= channel_c_index; /* set output channel enable bit */ - tmr_x->cctrl &= ~channel_index; + tmr_x->cctrl &= ~(1<cctrl |= channel_index; } @@ -880,6 +873,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct switch(channel) { case TMR_SELECT_CHANNEL_1: + tmr_x->cctrl_bit.c1en = FALSE; tmr_x->cctrl_bit.c1p = (uint32_t)input_struct->input_polarity_select; tmr_x->cctrl_bit.c1cp = (input_struct->input_polarity_select & 0x2) >> 1; tmr_x->cm1_input_bit.c1c = input_struct->input_mapped_select; @@ -889,6 +883,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct break; case TMR_SELECT_CHANNEL_2: + tmr_x->cctrl_bit.c2en = FALSE; tmr_x->cctrl_bit.c2p = (uint32_t)input_struct->input_polarity_select; tmr_x->cctrl_bit.c2cp = (input_struct->input_polarity_select & 0x2) >> 1; tmr_x->cm1_input_bit.c2c = input_struct->input_mapped_select; @@ -898,6 +893,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct break; case TMR_SELECT_CHANNEL_3: + tmr_x->cctrl_bit.c3en = FALSE; tmr_x->cctrl_bit.c3p = (uint32_t)input_struct->input_polarity_select; tmr_x->cctrl_bit.c3cp = (input_struct->input_polarity_select & 0x2) >> 1; tmr_x->cm2_input_bit.c3c = input_struct->input_mapped_select; @@ -907,6 +903,7 @@ void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct break; case TMR_SELECT_CHANNEL_4: + tmr_x->cctrl_bit.c4en = FALSE; tmr_x->cctrl_bit.c4p = (uint32_t)input_struct->input_polarity_select; tmr_x->cm2_input_bit.c4c = input_struct->input_mapped_select; tmr_x->cm2_input_bit.c4df = input_struct->input_filter_value; @@ -1141,15 +1138,15 @@ void tmr_pwm_input_config(tmr_type *tmr_x, tmr_input_config_type *input_struct, * @param tmr_x: select the tmr peripheral. * this parameter can be one of the following values: * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR20 - * @param ti1_connect + * @param ch1_connect * this parameter can be one of the following values: * - TMR_CHANEL1_CONNECTED_C1IRAW * - TMR_CHANEL1_2_3_CONNECTED_C1IRAW_XOR * @retval none */ -void tmr_channel1_input_select(tmr_type *tmr_x, tmr_channel1_input_connected_type ti1_connect) +void tmr_channel1_input_select(tmr_type *tmr_x, tmr_channel1_input_connected_type ch1_connect) { - tmr_x->ctrl2_bit.c1insel = ti1_connect; + tmr_x->ctrl2_bit.c1insel = ch1_connect; } /** @@ -1398,6 +1395,40 @@ void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state } } +/** + * @brief get tmr interrupt flag + * @param tmr_x: select the tmr peripheral. + * this parameter can be one of the following values: + * TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8, + * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14, TMR20 + * @param tmr_flag + * this parameter can be one of the following values: + * - TMR_OVF_FLAG + * - TMR_C1_FLAG + * - TMR_C2_FLAG + * - TMR_C3_FLAG + * - TMR_C4_FLAG + * - TMR_HALL_FLAG + * - TMR_TRIGGER_FLAG + * - TMR_BRK_FLAG + * @retval state of tmr interrupt flag + */ +flag_status tmr_interrupt_flag_get(tmr_type *tmr_x, uint32_t tmr_flag) +{ + flag_status status = RESET; + + if((tmr_x->ists & tmr_flag) && (tmr_x->iden & tmr_flag)) + { + status = SET; + } + else + { + status = RESET; + } + + return status; +} + /** * @brief get tmr flag * @param tmr_x: select the tmr peripheral. @@ -1411,6 +1442,7 @@ void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state * - TMR_C2_FLAG * - TMR_C3_FLAG * - TMR_C4_FLAG + * - TMR_C5_FLAG * - TMR_HALL_FLAG * - TMR_TRIGGER_FLAG * - TMR_BRK_FLAG @@ -1449,6 +1481,7 @@ flag_status tmr_flag_get(tmr_type *tmr_x, uint32_t tmr_flag) * - TMR_C2_FLAG * - TMR_C3_FLAG * - TMR_C4_FLAG + * - TMR_C5_FLAG * - TMR_HALL_FLAG * - TMR_TRIGGER_FLAG * - TMR_BRK_FLAG @@ -1511,25 +1544,6 @@ void tmr_internal_clock_set(tmr_type *tmr_x) tmr_x->stctrl_bit.smsel = TMR_SUB_MODE_DIABLE; } -/** - * @brief set tmr output channel fast - * @param tmr_x: select the tmr peripheral. - * this parameter can be one of the following values: - * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10, - * TMR11, TMR12, TMR13, TMR14, TMR20 - * @param oc_fast - * this parameter can be one of the following values: - * - TMR_CHANNEL1_OUTPUT_FAST - * - TMR_CHANNEL2_OUTPUT_FAST - * - TMR_CHANNEL3_OUTPUT_FAST - * - TMR_CHANNEL4_OUTPUT_FAST - * @retval none - */ -void tmr_output_channel_fast_set(tmr_type *tmr_x, tmr_channel_output_fast_type oc_fast) -{ - PERIPH_REG((uint32_t)(tmr_x), oc_fast) |= PERIPH_REG_BIT(oc_fast); -} - /** * @brief set tmr output channel polarity * @param tmr_x: select the tmr peripheral. @@ -1807,7 +1821,7 @@ void tmr_dma_control_config(tmr_type *tmr_x, tmr_dma_transfer_length_type dma_le } /** - * @brief config tmr break mode and dead-time + * @brief config tmr brake mode and dead-time * @param tmr_x: select the tmr peripheral. * this parameter can be one of the following values: * TMR1, TMR8, TMR20 diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_usart.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_usart.c index 58803c89ba..acf8702c56 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_usart.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_usart.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_usart.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the usart firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -86,11 +84,14 @@ void usart_reset(usart_type* usart_x) crm_periph_reset(CRM_UART7_PERIPH_RESET, TRUE); crm_periph_reset(CRM_UART7_PERIPH_RESET, FALSE); } +#if defined (AT32F435Zx) || defined (AT32F435Vx) || defined (AT32F435Rx) || \ + defined (AT32F437Zx) || defined (AT32F437Vx) || defined (AT32F437Rx) else if(usart_x == UART8) { crm_periph_reset(CRM_UART8_PERIPH_RESET, TRUE); crm_periph_reset(CRM_UART8_PERIPH_RESET, FALSE); } +#endif } /** @@ -104,6 +105,9 @@ void usart_reset(usart_type* usart_x) * - USART_DATA_7BITS * - USART_DATA_8BITS * - USART_DATA_9BITS. + * note: + * - when parity check is disabled, the data bit width is the actual data bit number. + * - when parity check is enabled, the data bit width is the actual data bit number minus 1, and the MSB bit is replaced with the parity bit. * @param stop_bit: stop bits transmitted * this parameter can be one of the following values: * - USART_STOP_1_BIT @@ -607,6 +611,79 @@ flag_status usart_flag_get(usart_type* usart_x, uint32_t flag) } } +/** + * @brief check whether the specified usart interrupt flag is set or not. + * @param usart_x: select the usart or the uart peripheral. + * this parameter can be one of the following values: + * USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8. + * @param flag: specifies the flag to check. + * this parameter can be one of the following values: + * - USART_CTSCF_FLAG: cts change flag (not available for UART4,UART5) + * - USART_BFF_FLAG: break frame flag + * - USART_TDBE_FLAG: transmit data buffer empty flag + * - USART_TDC_FLAG: transmit data complete flag + * - USART_RDBF_FLAG: receive data buffer full flag + * - USART_IDLEF_FLAG: idle flag + * - USART_ROERR_FLAG: receiver overflow error flag + * - USART_NERR_FLAG: noise error flag + * - USART_FERR_FLAG: framing error flag + * - USART_PERR_FLAG: parity error flag + * @retval the new state of usart_flag (SET or RESET). + */ +flag_status usart_interrupt_flag_get(usart_type* usart_x, uint32_t flag) +{ + flag_status int_status = RESET; + + switch(flag) + { + case USART_CTSCF_FLAG: + int_status = (flag_status)usart_x->ctrl3_bit.ctscfien; + break; + case USART_BFF_FLAG: + int_status = (flag_status)usart_x->ctrl2_bit.bfien; + break; + case USART_TDBE_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.tdbeien; + break; + case USART_TDC_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.tdcien; + break; + case USART_RDBF_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.rdbfien; + break; + case USART_ROERR_FLAG: + int_status = (flag_status)(usart_x->ctrl1_bit.rdbfien || usart_x->ctrl3_bit.errien); + break; + case USART_IDLEF_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.idleien; + break; + case USART_NERR_FLAG: + case USART_FERR_FLAG: + int_status = (flag_status)usart_x->ctrl3_bit.errien; + break; + case USART_PERR_FLAG: + int_status = (flag_status)usart_x->ctrl1_bit.perrien; + break; + default: + int_status = RESET; + break; + } + + if(int_status != SET) + { + return RESET; + } + + if(usart_x->sts & flag) + { + return SET; + } + else + { + return RESET; + } +} + /** * @brief clear the usart's pending flags. * @param usart_x: select the usart or the uart peripheral. @@ -618,6 +695,11 @@ flag_status usart_flag_get(usart_type* usart_x, uint32_t flag) * - USART_BFF_FLAG: * - USART_TDC_FLAG: * - USART_RDBF_FLAG: + * - USART_PERR_FLAG: + * - USART_FERR_FLAG: + * - USART_NERR_FLAG: + * - USART_ROERR_FLAG: + * - USART_IDLEF_FLAG: * @note * - USART_PERR_FLAG, USART_FERR_FLAG, USART_NERR_FLAG, USART_ROERR_FLAG and USART_IDLEF_FLAG are cleared by software * sequence: a read operation to usart sts register (usart_flag_get()) @@ -630,7 +712,15 @@ flag_status usart_flag_get(usart_type* usart_x, uint32_t flag) */ void usart_flag_clear(usart_type* usart_x, uint32_t flag) { - usart_x->sts = ~flag; + if(flag & (USART_PERR_FLAG | USART_FERR_FLAG | USART_NERR_FLAG | USART_ROERR_FLAG | USART_IDLEF_FLAG)) + { + UNUSED(usart_x->sts); + UNUSED(usart_x->dt); + } + else + { + usart_x->sts = ~flag; + } } /** diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_usb.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_usb.c index 8f63015236..15d42075d9 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_usb.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_usb.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_usb.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the usb firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -447,6 +445,7 @@ void usb_read_packet(otg_global_type *usbx, uint8_t *pusr_buf, uint16_t num, uin uint32_t n_index; uint32_t nhbytes = (nbytes + 3) / 4; uint32_t *pbuf = (uint32_t *)pusr_buf; + UNUSED(num); for(n_index = 0; n_index < nhbytes; n_index ++) { #if defined (__ICCARM__) && (__VER__ < 7000000) @@ -1020,11 +1019,10 @@ void usb_hch_halt(otg_global_type *usbx, uint8_t chn) usb_chh->hcchar_bit.eptype == EPT_BULK_TYPE) { usb_chh->hcchar_bit.chdis = TRUE; - if((usbx->gnptxsts & 0xFFFF) == 0) + if((usbx->gnptxsts_bit.nptxqspcavail) == 0) { usb_chh->hcchar_bit.chena = FALSE; usb_chh->hcchar_bit.chena = TRUE; - usb_chh->hcchar_bit.eptdir = 0; do { if(count ++ > 1000) @@ -1039,11 +1037,10 @@ void usb_hch_halt(otg_global_type *usbx, uint8_t chn) else { usb_chh->hcchar_bit.chdis = TRUE; - if((usb_host->hptxsts & 0xFFFF) == 0) + if((usb_host->hptxsts_bit.ptxqspcavil) == 0) { usb_chh->hcchar_bit.chena = FALSE; usb_chh->hcchar_bit.chena = TRUE; - usb_chh->hcchar_bit.eptdir = 0; do { if(count ++ > 1000) diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_wdt.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_wdt.c index a93eec352a..5e9e54ce4a 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_wdt.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_wdt.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_wdt.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the wdt firmware library ************************************************************************** * Copyright notice & Disclaimer diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_wwdt.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_wwdt.c index 967af61a40..1b338f47bf 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_wwdt.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_wwdt.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_wwdt.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the wwdt firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -106,6 +104,16 @@ flag_status wwdt_flag_get(void) return (flag_status)WWDT->sts_bit.rldf; } +/** + * @brief wwdt reload counter interrupt flag get + * @param none + * @retval state of reload counter interrupt flag + */ +flag_status wwdt_interrupt_flag_get(void) +{ + return (flag_status)(WWDT->sts_bit.rldf && WWDT->cfg_bit.rldien); +} + /** * @brief wwdt counter value set * @param wwdt_cnt (0x40~0x7f) diff --git a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_xmc.c b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_xmc.c index ac6df0b167..7ef0c11a2e 100644 --- a/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_xmc.c +++ b/bsp/at32/libraries/AT32F435_437_Firmware_Library/drivers/src/at32f435_437_xmc.c @@ -1,8 +1,6 @@ /** ************************************************************************** * @file at32f435_437_xmc.c - * @version v2.0.8 - * @date 2022-04-25 * @brief contains all the functions for the xmc firmware library ************************************************************************** * Copyright notice & Disclaimer @@ -224,9 +222,9 @@ void xmc_nor_sram_enable(xmc_nor_sram_subbank_type xmc_subbank, confirm_state ne * @param r2r_timing :read timing * @retval none */ -void xmc_ext_timing_config(xmc_nor_sram_subbank_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing) +void xmc_ext_timing_config(volatile xmc_nor_sram_subbank_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing) { - XMC_BANK1->ext_bit[xmc_sub_bank].buslatr2r = r2r_timing<<8; + XMC_BANK1->ext_bit[xmc_sub_bank].buslatr2r = r2r_timing; XMC_BANK1->ext_bit[xmc_sub_bank].buslatw2w = w2w_timing; } @@ -726,6 +724,97 @@ flag_status xmc_flag_status_get(xmc_class_bank_type xmc_bank, xmc_interrupt_flag return status; } +/** + * @brief check whether the specified xmc interrupt flag is set or not. + * @param xmc_bank: specifies the xmc bank to be used + * this parameter can be one of the following values: + * - XMC_BANK2_NAND + * - XMC_BANK3_NAND + * - XMC_BANK4_PCCARD + * @param xmc_flag: specifies the flag to check. + * this parameter can be any combination of the following values: + * - XMC_RISINGEDGE_FLAG + * - XMC_LEVEL_FLAG + * - XMC_FALLINGEDGE_FLAG + * @retval none + */ +flag_status xmc_interrupt_flag_status_get(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag) +{ + flag_status status = RESET; + + if(xmc_bank == XMC_BANK2_NAND) + { + switch(xmc_flag) + { + case XMC_RISINGEDGE_FLAG: + if(XMC_BANK2->bk2is_bit.reien && XMC_BANK2->bk2is_bit.res) + status = SET; + break; + + case XMC_LEVEL_FLAG: + if(XMC_BANK2->bk2is_bit.feien && XMC_BANK2->bk2is_bit.fes) + status = SET; + break; + + case XMC_FALLINGEDGE_FLAG: + if(XMC_BANK2->bk2is_bit.hlien && XMC_BANK2->bk2is_bit.hls) + status = SET; + break; + + default: + break; + } + } + else if(xmc_bank == XMC_BANK3_NAND) + { + switch(xmc_flag) + { + case XMC_RISINGEDGE_FLAG: + if(XMC_BANK3->bk3is_bit.reien && XMC_BANK3->bk3is_bit.res) + status = SET; + break; + + case XMC_LEVEL_FLAG: + if(XMC_BANK3->bk3is_bit.feien && XMC_BANK3->bk3is_bit.fes) + status = SET; + break; + + case XMC_FALLINGEDGE_FLAG: + if(XMC_BANK3->bk3is_bit.hlien && XMC_BANK3->bk3is_bit.hls) + status = SET; + break; + + default: + break; + } + } + else if(xmc_bank == XMC_BANK4_PCCARD) + { + switch(xmc_flag) + { + case XMC_RISINGEDGE_FLAG: + if(XMC_BANK4->bk4is_bit.reien && XMC_BANK4->bk4is_bit.res) + status = SET; + break; + + case XMC_LEVEL_FLAG: + if(XMC_BANK4->bk4is_bit.feien && XMC_BANK4->bk4is_bit.fes) + status = SET; + break; + + case XMC_FALLINGEDGE_FLAG: + if(XMC_BANK4->bk4is_bit.hlien && XMC_BANK4->bk4is_bit.hls) + status = SET; + break; + + default: + break; + } + } + /* return the flag status */ + return status; +} + /** * @brief clear the xmc's pending flags. * @param xmc_bank: specifies the xmc bank to be used diff --git a/bsp/at32/libraries/rt_drivers/SConscript b/bsp/at32/libraries/rt_drivers/SConscript index 7589393620..051e02dd33 100644 --- a/bsp/at32/libraries/rt_drivers/SConscript +++ b/bsp/at32/libraries/rt_drivers/SConscript @@ -44,6 +44,9 @@ if GetDepend(['RT_USING_I2C', 'RT_USING_I2C_BITOPS']): if GetDepend('BSP_USING_I2C1') or GetDepend('BSP_USING_I2C2') or GetDepend('BSP_USING_I2C3') or GetDepend('BSP_USING_I2C4'): src += ['drv_soft_i2c.c'] +if GetDepend(['BSP_USING_HARD_I2C']): + src += Glob('drv_hard_i2c.c') + if GetDepend(['BSP_USING_ADC']): src += Glob('drv_adc.c') diff --git a/bsp/at32/libraries/rt_drivers/config/a403a/dma_config.h b/bsp/at32/libraries/rt_drivers/config/a403a/dma_config.h index 51d1869d68..bc9577a313 100644 --- a/bsp/at32/libraries/rt_drivers/config/a403a/dma_config.h +++ b/bsp/at32/libraries/rt_drivers/config/a403a/dma_config.h @@ -29,6 +29,11 @@ extern "C" { #define UART3_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define UART3_TX_DMA_CHANNEL DMA1_CHANNEL2 #define UART3_TX_DMA_IRQ DMA1_Channel2_IRQn +#elif defined(BSP_I2C3_TX_USING_DMA) && !defined(I2C3_TX_DMA_CHANNEL) +#define I2C3_TX_DMA_IRQHandler DMA1_Channel2_IRQHandler +#define I2C3_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C3_TX_DMA_CHANNEL DMA1_CHANNEL2 +#define I2C3_TX_DMA_IRQ DMA1_Channel2_IRQn #endif /* DMA1 channel3 */ @@ -42,6 +47,11 @@ extern "C" { #define UART3_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define UART3_RX_DMA_CHANNEL DMA1_CHANNEL3 #define UART3_RX_DMA_IRQ DMA1_Channel3_IRQn +#elif defined(BSP_I2C3_RX_USING_DMA) && !defined(I2C3_RX_DMA_CHANNEL) +#define I2C3_RX_DMA_IRQHandler DMA1_Channel3_IRQHandler +#define I2C3_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C3_RX_DMA_CHANNEL DMA1_CHANNEL3 +#define I2C3_RX_DMA_IRQ DMA1_Channel3_IRQn #endif /* DMA1 channel4 */ @@ -55,6 +65,11 @@ extern "C" { #define UART1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define UART1_TX_DMA_CHANNEL DMA1_CHANNEL4 #define UART1_TX_DMA_IRQ DMA1_Channel4_IRQn +#elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_CHANNEL) +#define I2C2_TX_DMA_IRQHandler DMA1_Channel4_IRQHandler +#define I2C2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C2_TX_DMA_CHANNEL DMA1_CHANNEL4 +#define I2C2_TX_DMA_IRQ DMA1_Channel4_IRQn #endif /* DMA1 channel5 */ @@ -63,12 +78,16 @@ extern "C" { #define SPI2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define SPI2_TX_DMA_CHANNEL DMA1_CHANNEL5 #define SPI2_TX_DMA_IRQ DMA1_Channel5_IRQn - #elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_CHANNEL) #define UART1_RX_DMA_IRQHandler DMA1_Channel5_IRQHandler #define UART1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define UART1_RX_DMA_CHANNEL DMA1_CHANNEL5 #define UART1_RX_DMA_IRQ DMA1_Channel5_IRQn +#elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_CHANNEL) +#define I2C2_RX_DMA_IRQHandler DMA1_Channel5_IRQHandler +#define I2C2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C2_RX_DMA_CHANNEL DMA1_CHANNEL5 +#define I2C2_RX_DMA_IRQ DMA1_Channel5_IRQn #endif /* DMA1 channel6 */ @@ -77,6 +96,11 @@ extern "C" { #define UART2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define UART2_RX_DMA_CHANNEL DMA1_CHANNEL6 #define UART2_RX_DMA_IRQ DMA1_Channel6_IRQn +#elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_CHANNEL) +#define I2C1_TX_DMA_IRQHandler DMA1_Channel6_IRQHandler +#define I2C1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C1_TX_DMA_CHANNEL DMA1_CHANNEL6 +#define I2C1_TX_DMA_IRQ DMA1_Channel6_IRQn #endif /* DMA1 channel7 */ @@ -85,6 +109,11 @@ extern "C" { #define UART2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define UART2_TX_DMA_CHANNEL DMA1_CHANNEL7 #define UART2_TX_DMA_IRQ DMA1_Channel7_IRQn +#elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_CHANNEL) +#define I2C1_RX_DMA_IRQHandler DMA1_Channel7_IRQHandler +#define I2C1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C1_RX_DMA_CHANNEL DMA1_CHANNEL7 +#define I2C1_RX_DMA_IRQ DMA1_Channel7_IRQn #endif /* DMA2 channel1 */ diff --git a/bsp/at32/libraries/rt_drivers/config/a403a/i2c_config.h b/bsp/at32/libraries/rt_drivers/config/a403a/i2c_config.h new file mode 100644 index 0000000000..ed6b1e920c --- /dev/null +++ b/bsp/at32/libraries/rt_drivers/config/a403a/i2c_config.h @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-07-31 shelton first version + */ + +#ifndef __I2C_CONFIG_H__ +#define __I2C_CONFIG_H__ + +#include +#include "dma_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define HWI2C_OWN_ADDRESS 0x0 + +#define I2C1_EVT_IRQHandler I2C1_EVT_IRQHandler +#define I2C1_ERR_IRQHandler I2C1_ERR_IRQHandler +#define I2C2_EVT_IRQHandler I2C2_EVT_IRQHandler +#define I2C2_ERR_IRQHandler I2C2_ERR_IRQHandler +#define I2C3_EVT_IRQHandler I2C3_EVT_IRQHandler +#define I2C3_ERR_IRQHandler I2C3_ERR_IRQHandler + +#ifdef BSP_USING_HARD_I2C1 +#define I2C1_CONFIG \ + { \ + .i2c_x = I2C1, \ + .i2c_name = "hwi2c1", \ + .timing = 100000, \ + .ev_irqn = I2C1_EVT_IRQn, \ + .er_irqn = I2C1_ERR_IRQn, \ + } +#endif /* BSP_USING_HARD_I2C1 */ + +#ifdef BSP_I2C1_RX_USING_DMA +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_channel = I2C1_RX_DMA_CHANNEL, \ + .dma_clock = I2C1_RX_DMA_CLOCK, \ + .dma_irqn = I2C1_RX_DMA_IRQ, \ + } +#endif /* BSP_I2C1_RX_USING_DMA */ + +#ifdef BSP_I2C1_TX_USING_DMA +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_channel = I2C1_TX_DMA_CHANNEL, \ + .dma_clock = I2C1_TX_DMA_CLOCK, \ + .dma_irqn = I2C1_TX_DMA_IRQ, \ + } +#endif /* BSP_I2C1_TX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C2 +#define I2C2_CONFIG \ + { \ + .i2c_x = I2C2, \ + .i2c_name = "hwi2c2", \ + .timing = 100000, \ + .ev_irqn = I2C2_EVT_IRQn, \ + .er_irqn = I2C2_ERR_IRQn, \ + } +#endif /* BSP_USING_HARD_I2C2 */ + +#ifdef BSP_I2C2_RX_USING_DMA +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_channel = I2C2_RX_DMA_CHANNEL, \ + .dma_clock = I2C2_RX_DMA_CLOCK, \ + .dma_irqn = I2C2_RX_DMA_IRQ, \ + } +#endif /* BSP_I2C2_RX_USING_DMA */ + +#ifdef BSP_I2C2_TX_USING_DMA +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_channel = I2C2_TX_DMA_CHANNEL, \ + .dma_clock = I2C2_TX_DMA_CLOCK, \ + .dma_irqn = I2C2_TX_DMA_IRQ, \ + } +#endif /* BSP_I2C2_TX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C3 +#define I2C3_CONFIG \ + { \ + .i2c_x = I2C3, \ + .i2c_name = "hwi2c3", \ + .timing = 100000, \ + .ev_irqn = I2C3_EVT_IRQn, \ + .er_irqn = I2C3_ERR_IRQn, \ + } +#endif /* BSP_USING_HARD_I2C3 */ + +#ifdef BSP_I2C3_RX_USING_DMA +#define I2C3_RX_DMA_CONFIG \ + { \ + .dma_channel = I2C3_RX_DMA_CHANNEL, \ + .dma_clock = I2C3_RX_DMA_CLOCK, \ + .dma_irqn = I2C3_RX_DMA_IRQ, \ + } +#endif /* BSP_I2C3_RX_USING_DMA */ + +#ifdef BSP_I2C3_TX_USING_DMA +#define I2C3_TX_DMA_CONFIG \ + { \ + .dma_channel = I2C3_TX_DMA_CHANNEL, \ + .dma_clock = I2C3_TX_DMA_CLOCK, \ + .dma_irqn = I2C3_TX_DMA_IRQ, \ + } +#endif /* BSP_I2C3_TX_USING_DMA */ + +#ifdef __cplusplus +} +#endif + +#endif /*__I2C_CONFIG_H__ */ + diff --git a/bsp/at32/libraries/rt_drivers/config/a423/dma_config.h b/bsp/at32/libraries/rt_drivers/config/a423/dma_config.h index d913f31059..131284103b 100644 --- a/bsp/at32/libraries/rt_drivers/config/a423/dma_config.h +++ b/bsp/at32/libraries/rt_drivers/config/a423/dma_config.h @@ -32,6 +32,13 @@ extern "C" { #define UART1_RX_DMA_IRQ DMA1_Channel1_IRQn #define UART1_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL1 #define UART1_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART1_RX +#elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_CHANNEL) +#define I2C1_RX_DMA_IRQHandler DMA1_Channel1_IRQHandler +#define I2C1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C1_RX_DMA_CHANNEL DMA1_CHANNEL1 +#define I2C1_RX_DMA_IRQ DMA1_Channel1_IRQn +#define I2C1_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL1 +#define I2C1_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C1_RX #endif /* DMA1 channel2 */ @@ -49,6 +56,13 @@ extern "C" { #define UART1_TX_DMA_IRQ DMA1_Channel2_IRQn #define UART1_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL2 #define UART1_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART1_TX +#elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_CHANNEL) +#define I2C1_TX_DMA_IRQHandler DMA1_Channel2_IRQHandler +#define I2C1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C1_TX_DMA_CHANNEL DMA1_CHANNEL2 +#define I2C1_TX_DMA_IRQ DMA1_Channel2_IRQn +#define I2C1_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL2 +#define I2C1_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C1_TX #endif /* DMA1 channel3 */ @@ -66,6 +80,13 @@ extern "C" { #define UART2_RX_DMA_IRQ DMA1_Channel3_IRQn #define UART2_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL3 #define UART2_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART2_RX +#elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_CHANNEL) +#define I2C2_RX_DMA_IRQHandler DMA1_Channel3_IRQHandler +#define I2C2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C2_RX_DMA_CHANNEL DMA1_CHANNEL3 +#define I2C2_RX_DMA_IRQ DMA1_Channel3_IRQn +#define I2C2_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL3 +#define I2C2_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C2_RX #endif /* DMA1 channel4 */ @@ -83,6 +104,13 @@ extern "C" { #define UART2_TX_DMA_IRQ DMA1_Channel4_IRQn #define UART2_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL4 #define UART2_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART2_TX +#elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_CHANNEL) +#define I2C2_TX_DMA_IRQHandler DMA1_Channel4_IRQHandler +#define I2C2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C2_TX_DMA_CHANNEL DMA1_CHANNEL4 +#define I2C2_TX_DMA_IRQ DMA1_Channel4_IRQn +#define I2C2_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL4 +#define I2C2_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C2_TX #endif /* DMA1 channel5 */ @@ -100,6 +128,13 @@ extern "C" { #define UART3_RX_DMA_IRQ DMA1_Channel5_IRQn #define UART3_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL5 #define UART3_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART3_RX +#elif defined(BSP_I2C3_RX_USING_DMA) && !defined(I2C3_RX_DMA_CHANNEL) +#define I2C3_RX_DMA_IRQHandler DMA1_Channel5_IRQHandler +#define I2C3_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C3_RX_DMA_CHANNEL DMA1_CHANNEL5 +#define I2C3_RX_DMA_IRQ DMA1_Channel5_IRQn +#define I2C3_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL5 +#define I2C3_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C3_RX #endif /* DMA1 channel6 */ @@ -117,6 +152,13 @@ extern "C" { #define UART3_TX_DMA_IRQ DMA1_Channel6_IRQn #define UART3_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL6 #define UART3_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART3_TX +#elif defined(BSP_I2C3_TX_USING_DMA) && !defined(I2C3_TX_DMA_CHANNEL) +#define I2C3_TX_DMA_IRQHandler DMA1_Channel6_IRQHandler +#define I2C3_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C3_TX_DMA_CHANNEL DMA1_CHANNEL6 +#define I2C3_TX_DMA_IRQ DMA1_Channel6_IRQn +#define I2C3_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL6 +#define I2C3_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C3_TX #endif /* DMA1 channel7 */ @@ -162,7 +204,7 @@ extern "C" { /* DMA2 channel4 */ #if defined(BSP_UART6_RX_USING_DMA) && !defined(UART6_RX_DMA_CHANNEL) #define UART6_RX_DMA_IRQHandler DMA2_Channel4_IRQHandler -#define UART6_RX_DMA_CLOCK CRM_DMA4_PERIPH_CLOCK +#define UART6_RX_DMA_CLOCK CRM_DMA2_PERIPH_CLOCK #define UART6_RX_DMA_CHANNEL DMA2_CHANNEL4 #define UART6_RX_DMA_IRQ DMA2_Channel4_IRQn #define UART6_RX_DMA_MUX_CHANNEL DMA2MUX_CHANNEL4 diff --git a/bsp/at32/libraries/rt_drivers/config/a423/i2c_config.h b/bsp/at32/libraries/rt_drivers/config/a423/i2c_config.h new file mode 100644 index 0000000000..6bc2a184ef --- /dev/null +++ b/bsp/at32/libraries/rt_drivers/config/a423/i2c_config.h @@ -0,0 +1,134 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-07-31 shelton first version + */ + +#ifndef __I2C_CONFIG_H__ +#define __I2C_CONFIG_H__ + +#include +#include "dma_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define HWI2C_OWN_ADDRESS 0x0 + +#define I2C1_EVT_IRQHandler I2C1_EVT_IRQHandler +#define I2C1_ERR_IRQHandler I2C1_ERR_IRQHandler +#define I2C2_EVT_IRQHandler I2C2_EVT_IRQHandler +#define I2C2_ERR_IRQHandler I2C2_ERR_IRQHandler +#define I2C3_EVT_IRQHandler I2C3_EVT_IRQHandler +#define I2C3_ERR_IRQHandler I2C3_ERR_IRQHandler + +#ifdef BSP_USING_HARD_I2C1 +#define I2C1_CONFIG \ + { \ + .i2c_x = I2C1, \ + .i2c_name = "hwi2c1", \ + .timing = 0x60E02E2E, \ + .ev_irqn = I2C1_EVT_IRQn, \ + .er_irqn = I2C1_ERR_IRQn, \ + } +#endif /* BSP_USING_HARD_I2C1 */ + +#ifdef BSP_I2C1_RX_USING_DMA +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_channel = I2C1_RX_DMA_CHANNEL, \ + .dma_clock = I2C1_RX_DMA_CLOCK, \ + .dma_irqn = I2C1_RX_DMA_IRQ, \ + .dmamux_channel = I2C1_RX_DMA_MUX_CHANNEL, \ + .request_id = I2C1_RX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C1_RX_USING_DMA */ + +#ifdef BSP_I2C1_TX_USING_DMA +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_channel = I2C1_TX_DMA_CHANNEL, \ + .dma_clock = I2C1_TX_DMA_CLOCK, \ + .dma_irqn = I2C1_TX_DMA_IRQ, \ + .dmamux_channel = I2C1_TX_DMA_MUX_CHANNEL, \ + .request_id = I2C1_TX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C1_TX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C2 +#define I2C2_CONFIG \ + { \ + .i2c_x = I2C2, \ + .i2c_name = "hwi2c2", \ + .timing = 0x60E02E2E, \ + .ev_irqn = I2C2_EVT_IRQn, \ + .er_irqn = I2C2_ERR_IRQn, \ + } +#endif /* BSP_USING_HARD_I2C2 */ + +#ifdef BSP_I2C2_RX_USING_DMA +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_channel = I2C2_RX_DMA_CHANNEL, \ + .dma_clock = I2C2_RX_DMA_CLOCK, \ + .dma_irqn = I2C2_RX_DMA_IRQ, \ + .dmamux_channel = I2C2_RX_DMA_MUX_CHANNEL, \ + .request_id = I2C2_RX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C2_RX_USING_DMA */ + +#ifdef BSP_I2C2_TX_USING_DMA +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_channel = I2C2_TX_DMA_CHANNEL, \ + .dma_clock = I2C2_TX_DMA_CLOCK, \ + .dma_irqn = I2C2_TX_DMA_IRQ, \ + .dmamux_channel = I2C2_TX_DMA_MUX_CHANNEL, \ + .request_id = I2C2_TX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C2_TX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C3 +#define I2C3_CONFIG \ + { \ + .i2c_x = I2C3, \ + .i2c_name = "hwi2c3", \ + .timing = 0x60E02E2E, \ + .ev_irqn = I2C3_EVT_IRQn, \ + .er_irqn = I2C3_ERR_IRQn, \ + } +#endif /* BSP_USING_HARD_I2C3 */ + +#ifdef BSP_I2C3_RX_USING_DMA +#define I2C3_RX_DMA_CONFIG \ + { \ + .dma_channel = I2C3_RX_DMA_CHANNEL, \ + .dma_clock = I2C3_RX_DMA_CLOCK, \ + .dma_irqn = I2C3_RX_DMA_IRQ, \ + .dmamux_channel = I2C3_RX_DMA_MUX_CHANNEL, \ + .request_id = I2C3_RX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C3_RX_USING_DMA */ + +#ifdef BSP_I2C3_TX_USING_DMA +#define I2C3_TX_DMA_CONFIG \ + { \ + .dma_channel = I2C3_TX_DMA_CHANNEL, \ + .dma_clock = I2C3_TX_DMA_CLOCK, \ + .dma_irqn = I2C3_TX_DMA_IRQ, \ + .dmamux_channel = I2C3_TX_DMA_MUX_CHANNEL, \ + .request_id = I2C3_TX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C3_TX_USING_DMA */ + +#ifdef __cplusplus +} +#endif + +#endif /*__I2C_CONFIG_H__ */ + diff --git a/bsp/at32/libraries/rt_drivers/config/f402_405/dma_config.h b/bsp/at32/libraries/rt_drivers/config/f402_405/dma_config.h index 1dcb38d41f..c379be4185 100644 --- a/bsp/at32/libraries/rt_drivers/config/f402_405/dma_config.h +++ b/bsp/at32/libraries/rt_drivers/config/f402_405/dma_config.h @@ -32,6 +32,13 @@ extern "C" { #define UART1_RX_DMA_IRQ DMA1_Channel1_IRQn #define UART1_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL1 #define UART1_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART1_RX +#elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_CHANNEL) +#define I2C1_RX_DMA_IRQHandler DMA1_Channel1_IRQHandler +#define I2C1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C1_RX_DMA_CHANNEL DMA1_CHANNEL1 +#define I2C1_RX_DMA_IRQ DMA1_Channel1_IRQn +#define I2C1_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL1 +#define I2C1_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C1_RX #endif /* DMA1 channel2 */ @@ -49,6 +56,13 @@ extern "C" { #define UART1_TX_DMA_IRQ DMA1_Channel2_IRQn #define UART1_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL2 #define UART1_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART1_TX +#elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_CHANNEL) +#define I2C1_TX_DMA_IRQHandler DMA1_Channel2_IRQHandler +#define I2C1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C1_TX_DMA_CHANNEL DMA1_CHANNEL2 +#define I2C1_TX_DMA_IRQ DMA1_Channel2_IRQn +#define I2C1_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL2 +#define I2C1_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C1_TX #endif /* DMA1 channel3 */ @@ -66,6 +80,13 @@ extern "C" { #define UART2_RX_DMA_IRQ DMA1_Channel3_IRQn #define UART2_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL3 #define UART2_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART2_RX +#elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_CHANNEL) +#define I2C2_RX_DMA_IRQHandler DMA1_Channel3_IRQHandler +#define I2C2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C2_RX_DMA_CHANNEL DMA1_CHANNEL3 +#define I2C2_RX_DMA_IRQ DMA1_Channel3_IRQn +#define I2C2_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL3 +#define I2C2_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C2_RX #endif /* DMA1 channel4 */ @@ -83,6 +104,13 @@ extern "C" { #define UART2_TX_DMA_IRQ DMA1_Channel4_IRQn #define UART2_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL4 #define UART2_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART2_TX +#elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_CHANNEL) +#define I2C2_TX_DMA_IRQHandler DMA1_Channel4_IRQHandler +#define I2C2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C2_TX_DMA_CHANNEL DMA1_CHANNEL4 +#define I2C2_TX_DMA_IRQ DMA1_Channel4_IRQn +#define I2C2_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL4 +#define I2C2_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C2_TX #endif /* DMA1 channel5 */ @@ -100,6 +128,13 @@ extern "C" { #define UART3_RX_DMA_IRQ DMA1_Channel5_IRQn #define UART3_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL5 #define UART3_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART3_RX +#elif defined(BSP_I2C3_RX_USING_DMA) && !defined(I2C3_RX_DMA_CHANNEL) +#define I2C3_RX_DMA_IRQHandler DMA1_Channel5_IRQHandler +#define I2C3_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C3_RX_DMA_CHANNEL DMA1_CHANNEL5 +#define I2C3_RX_DMA_IRQ DMA1_Channel5_IRQn +#define I2C3_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL5 +#define I2C3_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C3_RX #endif /* DMA1 channel6 */ @@ -117,6 +152,13 @@ extern "C" { #define UART3_TX_DMA_IRQ DMA1_Channel6_IRQn #define UART3_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL6 #define UART3_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART3_TX +#elif defined(BSP_I2C3_TX_USING_DMA) && !defined(I2C3_TX_DMA_CHANNEL) +#define I2C3_TX_DMA_IRQHandler DMA1_Channel6_IRQHandler +#define I2C3_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C3_TX_DMA_CHANNEL DMA1_CHANNEL6 +#define I2C3_TX_DMA_IRQ DMA1_Channel6_IRQn +#define I2C3_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL6 +#define I2C3_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C3_TX #endif /* DMA1 channel7 */ @@ -162,7 +204,7 @@ extern "C" { /* DMA2 channel4 */ #if defined(BSP_UART6_RX_USING_DMA) && !defined(UART6_RX_DMA_CHANNEL) #define UART6_RX_DMA_IRQHandler DMA2_Channel4_IRQHandler -#define UART6_RX_DMA_CLOCK CRM_DMA4_PERIPH_CLOCK +#define UART6_RX_DMA_CLOCK CRM_DMA2_PERIPH_CLOCK #define UART6_RX_DMA_CHANNEL DMA2_CHANNEL4 #define UART6_RX_DMA_IRQ DMA2_Channel4_IRQn #define UART6_RX_DMA_MUX_CHANNEL DMA2MUX_CHANNEL4 diff --git a/bsp/at32/libraries/rt_drivers/config/f402_405/i2c_config.h b/bsp/at32/libraries/rt_drivers/config/f402_405/i2c_config.h new file mode 100644 index 0000000000..1700059a8a --- /dev/null +++ b/bsp/at32/libraries/rt_drivers/config/f402_405/i2c_config.h @@ -0,0 +1,134 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-07-31 shelton first version + */ + +#ifndef __I2C_CONFIG_H__ +#define __I2C_CONFIG_H__ + +#include +#include "dma_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define HWI2C_OWN_ADDRESS 0x0 + +#define I2C1_EVT_IRQHandler I2C1_EVT_IRQHandler +#define I2C1_ERR_IRQHandler I2C1_ERR_IRQHandler +#define I2C2_EVT_IRQHandler I2C2_EVT_IRQHandler +#define I2C2_ERR_IRQHandler I2C2_ERR_IRQHandler +#define I2C3_EVT_IRQHandler I2C3_EVT_IRQHandler +#define I2C3_ERR_IRQHandler I2C3_ERR_IRQHandler + +#ifdef BSP_USING_HARD_I2C1 +#define I2C1_CONFIG \ + { \ + .i2c_x = I2C1, \ + .i2c_name = "hwi2c1", \ + .timing = 0x90F02F2F, \ + .ev_irqn = I2C1_EVT_IRQn, \ + .er_irqn = I2C1_ERR_IRQn, \ + } +#endif /* BSP_USING_HARD_I2C1 */ + +#ifdef BSP_I2C1_RX_USING_DMA +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_channel = I2C1_RX_DMA_CHANNEL, \ + .dma_clock = I2C1_RX_DMA_CLOCK, \ + .dma_irqn = I2C1_RX_DMA_IRQ, \ + .dmamux_channel = I2C1_RX_DMA_MUX_CHANNEL, \ + .request_id = I2C1_RX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C1_RX_USING_DMA */ + +#ifdef BSP_I2C1_TX_USING_DMA +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_channel = I2C1_TX_DMA_CHANNEL, \ + .dma_clock = I2C1_TX_DMA_CLOCK, \ + .dma_irqn = I2C1_TX_DMA_IRQ, \ + .dmamux_channel = I2C1_TX_DMA_MUX_CHANNEL, \ + .request_id = I2C1_TX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C1_TX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C2 +#define I2C2_CONFIG \ + { \ + .i2c_x = I2C2, \ + .i2c_name = "hwi2c2", \ + .timing = 0x90F02F2F, \ + .ev_irqn = I2C2_EVT_IRQn, \ + .er_irqn = I2C2_ERR_IRQn, \ + } +#endif /* BSP_USING_HARD_I2C2 */ + +#ifdef BSP_I2C2_RX_USING_DMA +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_channel = I2C2_RX_DMA_CHANNEL, \ + .dma_clock = I2C2_RX_DMA_CLOCK, \ + .dma_irqn = I2C2_RX_DMA_IRQ, \ + .dmamux_channel = I2C2_RX_DMA_MUX_CHANNEL, \ + .request_id = I2C2_RX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C2_RX_USING_DMA */ + +#ifdef BSP_I2C2_TX_USING_DMA +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_channel = I2C2_TX_DMA_CHANNEL, \ + .dma_clock = I2C2_TX_DMA_CLOCK, \ + .dma_irqn = I2C2_TX_DMA_IRQ, \ + .dmamux_channel = I2C2_TX_DMA_MUX_CHANNEL, \ + .request_id = I2C2_TX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C2_TX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C3 +#define I2C3_CONFIG \ + { \ + .i2c_x = I2C3, \ + .i2c_name = "hwi2c3", \ + .timing = 0x90F02F2F, \ + .ev_irqn = I2C3_EVT_IRQn, \ + .er_irqn = I2C3_ERR_IRQn, \ + } +#endif /* BSP_USING_HARD_I2C3 */ + +#ifdef BSP_I2C3_RX_USING_DMA +#define I2C3_RX_DMA_CONFIG \ + { \ + .dma_channel = I2C3_RX_DMA_CHANNEL, \ + .dma_clock = I2C3_RX_DMA_CLOCK, \ + .dma_irqn = I2C3_RX_DMA_IRQ, \ + .dmamux_channel = I2C3_RX_DMA_MUX_CHANNEL, \ + .request_id = I2C3_RX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C3_RX_USING_DMA */ + +#ifdef BSP_I2C3_TX_USING_DMA +#define I2C3_TX_DMA_CONFIG \ + { \ + .dma_channel = I2C3_TX_DMA_CHANNEL, \ + .dma_clock = I2C3_TX_DMA_CLOCK, \ + .dma_irqn = I2C3_TX_DMA_IRQ, \ + .dmamux_channel = I2C3_TX_DMA_MUX_CHANNEL, \ + .request_id = I2C3_TX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C3_TX_USING_DMA */ + +#ifdef __cplusplus +} +#endif + +#endif /*__I2C_CONFIG_H__ */ + diff --git a/bsp/at32/libraries/rt_drivers/config/f403a_407/dma_config.h b/bsp/at32/libraries/rt_drivers/config/f403a_407/dma_config.h index cbbda889da..1ade3b7db4 100644 --- a/bsp/at32/libraries/rt_drivers/config/f403a_407/dma_config.h +++ b/bsp/at32/libraries/rt_drivers/config/f403a_407/dma_config.h @@ -29,6 +29,11 @@ extern "C" { #define UART3_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define UART3_TX_DMA_CHANNEL DMA1_CHANNEL2 #define UART3_TX_DMA_IRQ DMA1_Channel2_IRQn +#elif defined(BSP_I2C3_TX_USING_DMA) && !defined(I2C3_TX_DMA_CHANNEL) +#define I2C3_TX_DMA_IRQHandler DMA1_Channel2_IRQHandler +#define I2C3_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C3_TX_DMA_CHANNEL DMA1_CHANNEL2 +#define I2C3_TX_DMA_IRQ DMA1_Channel2_IRQn #endif /* DMA1 channel3 */ @@ -42,6 +47,11 @@ extern "C" { #define UART3_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define UART3_RX_DMA_CHANNEL DMA1_CHANNEL3 #define UART3_RX_DMA_IRQ DMA1_Channel3_IRQn +#elif defined(BSP_I2C3_RX_USING_DMA) && !defined(I2C3_RX_DMA_CHANNEL) +#define I2C3_RX_DMA_IRQHandler DMA1_Channel3_IRQHandler +#define I2C3_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C3_RX_DMA_CHANNEL DMA1_CHANNEL3 +#define I2C3_RX_DMA_IRQ DMA1_Channel3_IRQn #endif /* DMA1 channel4 */ @@ -55,6 +65,11 @@ extern "C" { #define UART1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define UART1_TX_DMA_CHANNEL DMA1_CHANNEL4 #define UART1_TX_DMA_IRQ DMA1_Channel4_IRQn +#elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_CHANNEL) +#define I2C2_TX_DMA_IRQHandler DMA1_Channel4_IRQHandler +#define I2C2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C2_TX_DMA_CHANNEL DMA1_CHANNEL4 +#define I2C2_TX_DMA_IRQ DMA1_Channel4_IRQn #endif /* DMA1 channel5 */ @@ -63,12 +78,16 @@ extern "C" { #define SPI2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define SPI2_TX_DMA_CHANNEL DMA1_CHANNEL5 #define SPI2_TX_DMA_IRQ DMA1_Channel5_IRQn - #elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_CHANNEL) #define UART1_RX_DMA_IRQHandler DMA1_Channel5_IRQHandler #define UART1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define UART1_RX_DMA_CHANNEL DMA1_CHANNEL5 #define UART1_RX_DMA_IRQ DMA1_Channel5_IRQn +#elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_CHANNEL) +#define I2C2_RX_DMA_IRQHandler DMA1_Channel5_IRQHandler +#define I2C2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C2_RX_DMA_CHANNEL DMA1_CHANNEL5 +#define I2C2_RX_DMA_IRQ DMA1_Channel5_IRQn #endif /* DMA1 channel6 */ @@ -77,6 +96,11 @@ extern "C" { #define UART2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define UART2_RX_DMA_CHANNEL DMA1_CHANNEL6 #define UART2_RX_DMA_IRQ DMA1_Channel6_IRQn +#elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_CHANNEL) +#define I2C1_TX_DMA_IRQHandler DMA1_Channel6_IRQHandler +#define I2C1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C1_TX_DMA_CHANNEL DMA1_CHANNEL6 +#define I2C1_TX_DMA_IRQ DMA1_Channel6_IRQn #endif /* DMA1 channel7 */ @@ -85,6 +109,11 @@ extern "C" { #define UART2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define UART2_TX_DMA_CHANNEL DMA1_CHANNEL7 #define UART2_TX_DMA_IRQ DMA1_Channel7_IRQn +#elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_CHANNEL) +#define I2C1_RX_DMA_IRQHandler DMA1_Channel7_IRQHandler +#define I2C1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C1_RX_DMA_CHANNEL DMA1_CHANNEL7 +#define I2C1_RX_DMA_IRQ DMA1_Channel7_IRQn #endif /* DMA2 channel1 */ diff --git a/bsp/at32/libraries/rt_drivers/config/f403a_407/i2c_config.h b/bsp/at32/libraries/rt_drivers/config/f403a_407/i2c_config.h new file mode 100644 index 0000000000..ed6b1e920c --- /dev/null +++ b/bsp/at32/libraries/rt_drivers/config/f403a_407/i2c_config.h @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-07-31 shelton first version + */ + +#ifndef __I2C_CONFIG_H__ +#define __I2C_CONFIG_H__ + +#include +#include "dma_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define HWI2C_OWN_ADDRESS 0x0 + +#define I2C1_EVT_IRQHandler I2C1_EVT_IRQHandler +#define I2C1_ERR_IRQHandler I2C1_ERR_IRQHandler +#define I2C2_EVT_IRQHandler I2C2_EVT_IRQHandler +#define I2C2_ERR_IRQHandler I2C2_ERR_IRQHandler +#define I2C3_EVT_IRQHandler I2C3_EVT_IRQHandler +#define I2C3_ERR_IRQHandler I2C3_ERR_IRQHandler + +#ifdef BSP_USING_HARD_I2C1 +#define I2C1_CONFIG \ + { \ + .i2c_x = I2C1, \ + .i2c_name = "hwi2c1", \ + .timing = 100000, \ + .ev_irqn = I2C1_EVT_IRQn, \ + .er_irqn = I2C1_ERR_IRQn, \ + } +#endif /* BSP_USING_HARD_I2C1 */ + +#ifdef BSP_I2C1_RX_USING_DMA +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_channel = I2C1_RX_DMA_CHANNEL, \ + .dma_clock = I2C1_RX_DMA_CLOCK, \ + .dma_irqn = I2C1_RX_DMA_IRQ, \ + } +#endif /* BSP_I2C1_RX_USING_DMA */ + +#ifdef BSP_I2C1_TX_USING_DMA +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_channel = I2C1_TX_DMA_CHANNEL, \ + .dma_clock = I2C1_TX_DMA_CLOCK, \ + .dma_irqn = I2C1_TX_DMA_IRQ, \ + } +#endif /* BSP_I2C1_TX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C2 +#define I2C2_CONFIG \ + { \ + .i2c_x = I2C2, \ + .i2c_name = "hwi2c2", \ + .timing = 100000, \ + .ev_irqn = I2C2_EVT_IRQn, \ + .er_irqn = I2C2_ERR_IRQn, \ + } +#endif /* BSP_USING_HARD_I2C2 */ + +#ifdef BSP_I2C2_RX_USING_DMA +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_channel = I2C2_RX_DMA_CHANNEL, \ + .dma_clock = I2C2_RX_DMA_CLOCK, \ + .dma_irqn = I2C2_RX_DMA_IRQ, \ + } +#endif /* BSP_I2C2_RX_USING_DMA */ + +#ifdef BSP_I2C2_TX_USING_DMA +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_channel = I2C2_TX_DMA_CHANNEL, \ + .dma_clock = I2C2_TX_DMA_CLOCK, \ + .dma_irqn = I2C2_TX_DMA_IRQ, \ + } +#endif /* BSP_I2C2_TX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C3 +#define I2C3_CONFIG \ + { \ + .i2c_x = I2C3, \ + .i2c_name = "hwi2c3", \ + .timing = 100000, \ + .ev_irqn = I2C3_EVT_IRQn, \ + .er_irqn = I2C3_ERR_IRQn, \ + } +#endif /* BSP_USING_HARD_I2C3 */ + +#ifdef BSP_I2C3_RX_USING_DMA +#define I2C3_RX_DMA_CONFIG \ + { \ + .dma_channel = I2C3_RX_DMA_CHANNEL, \ + .dma_clock = I2C3_RX_DMA_CLOCK, \ + .dma_irqn = I2C3_RX_DMA_IRQ, \ + } +#endif /* BSP_I2C3_RX_USING_DMA */ + +#ifdef BSP_I2C3_TX_USING_DMA +#define I2C3_TX_DMA_CONFIG \ + { \ + .dma_channel = I2C3_TX_DMA_CHANNEL, \ + .dma_clock = I2C3_TX_DMA_CLOCK, \ + .dma_irqn = I2C3_TX_DMA_IRQ, \ + } +#endif /* BSP_I2C3_TX_USING_DMA */ + +#ifdef __cplusplus +} +#endif + +#endif /*__I2C_CONFIG_H__ */ + diff --git a/bsp/at32/libraries/rt_drivers/config/f413/dma_config.h b/bsp/at32/libraries/rt_drivers/config/f413/dma_config.h index 5dd80c2422..89c3f242cd 100644 --- a/bsp/at32/libraries/rt_drivers/config/f413/dma_config.h +++ b/bsp/at32/libraries/rt_drivers/config/f413/dma_config.h @@ -55,6 +55,11 @@ extern "C" { #define UART1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define UART1_TX_DMA_CHANNEL DMA1_CHANNEL4 #define UART1_TX_DMA_IRQ DMA1_Channel4_IRQn +#elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_CHANNEL) +#define I2C2_TX_DMA_IRQHandler DMA1_Channel4_IRQHandler +#define I2C2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C2_TX_DMA_CHANNEL DMA1_CHANNEL4 +#define I2C2_TX_DMA_IRQ DMA1_Channel4_IRQn #endif /* DMA1 channel5 */ @@ -63,12 +68,16 @@ extern "C" { #define SPI2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define SPI2_TX_DMA_CHANNEL DMA1_CHANNEL5 #define SPI2_TX_DMA_IRQ DMA1_Channel5_IRQn - #elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_CHANNEL) #define UART1_RX_DMA_IRQHandler DMA1_Channel5_IRQHandler #define UART1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define UART1_RX_DMA_CHANNEL DMA1_CHANNEL5 #define UART1_RX_DMA_IRQ DMA1_Channel5_IRQn +#elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_CHANNEL) +#define I2C2_RX_DMA_IRQHandler DMA1_Channel5_IRQHandler +#define I2C2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C2_RX_DMA_CHANNEL DMA1_CHANNEL5 +#define I2C2_RX_DMA_IRQ DMA1_Channel5_IRQn #endif /* DMA1 channel6 */ @@ -77,6 +86,11 @@ extern "C" { #define UART2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define UART2_RX_DMA_CHANNEL DMA1_CHANNEL6 #define UART2_RX_DMA_IRQ DMA1_Channel6_IRQn +#elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_CHANNEL) +#define I2C1_TX_DMA_IRQHandler DMA1_Channel6_IRQHandler +#define I2C1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C1_TX_DMA_CHANNEL DMA1_CHANNEL6 +#define I2C1_TX_DMA_IRQ DMA1_Channel6_IRQn #endif /* DMA1 channel7 */ @@ -85,6 +99,11 @@ extern "C" { #define UART2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define UART2_TX_DMA_CHANNEL DMA1_CHANNEL7 #define UART2_TX_DMA_IRQ DMA1_Channel7_IRQn +#elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_CHANNEL) +#define I2C1_RX_DMA_IRQHandler DMA1_Channel7_IRQHandler +#define I2C1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C1_RX_DMA_CHANNEL DMA1_CHANNEL7 +#define I2C1_RX_DMA_IRQ DMA1_Channel7_IRQn #endif /* DMA2 channel3 */ diff --git a/bsp/at32/libraries/rt_drivers/config/f413/i2c_config.h b/bsp/at32/libraries/rt_drivers/config/f413/i2c_config.h new file mode 100644 index 0000000000..fe34d4bb32 --- /dev/null +++ b/bsp/at32/libraries/rt_drivers/config/f413/i2c_config.h @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-07-31 shelton first version + */ + +#ifndef __I2C_CONFIG_H__ +#define __I2C_CONFIG_H__ + +#include +#include "dma_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define HWI2C_OWN_ADDRESS 0x0 + +#define I2C1_EVT_IRQHandler I2C1_EVT_IRQHandler +#define I2C1_ERR_IRQHandler I2C1_ERR_IRQHandler +#define I2C2_EVT_IRQHandler I2C2_EVT_IRQHandler +#define I2C2_ERR_IRQHandler I2C2_ERR_IRQHandler + +#ifdef BSP_USING_HARD_I2C1 +#define I2C1_CONFIG \ + { \ + .i2c_x = I2C1, \ + .i2c_name = "hwi2c1", \ + .timing = 100000, \ + .ev_irqn = I2C1_EVT_IRQn, \ + .er_irqn = I2C1_ERR_IRQn, \ + } +#endif /* BSP_USING_HARD_I2C1 */ + +#ifdef BSP_I2C1_RX_USING_DMA +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_channel = I2C1_RX_DMA_CHANNEL, \ + .dma_clock = I2C1_RX_DMA_CLOCK, \ + .dma_irqn = I2C1_RX_DMA_IRQ, \ + } +#endif /* BSP_I2C1_RX_USING_DMA */ + +#ifdef BSP_I2C1_TX_USING_DMA +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_channel = I2C1_TX_DMA_CHANNEL, \ + .dma_clock = I2C1_TX_DMA_CLOCK, \ + .dma_irqn = I2C1_TX_DMA_IRQ, \ + } +#endif /* BSP_I2C1_TX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C2 +#define I2C2_CONFIG \ + { \ + .i2c_x = I2C2, \ + .i2c_name = "hwi2c2", \ + .timing = 100000, \ + .ev_irqn = I2C2_EVT_IRQn, \ + .er_irqn = I2C2_ERR_IRQn, \ + } +#endif /* BSP_USING_HARD_I2C2 */ + +#ifdef BSP_I2C2_RX_USING_DMA +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_channel = I2C2_RX_DMA_CHANNEL, \ + .dma_clock = I2C2_RX_DMA_CLOCK, \ + .dma_irqn = I2C2_RX_DMA_IRQ, \ + } +#endif /* BSP_I2C2_RX_USING_DMA */ + +#ifdef BSP_I2C2_TX_USING_DMA +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_channel = I2C2_TX_DMA_CHANNEL, \ + .dma_clock = I2C2_TX_DMA_CLOCK, \ + .dma_irqn = I2C2_TX_DMA_IRQ, \ + } +#endif /* BSP_I2C2_TX_USING_DMA */ + +#ifdef __cplusplus +} +#endif + +#endif /*__I2C_CONFIG_H__ */ + diff --git a/bsp/at32/libraries/rt_drivers/config/f415/dma_config.h b/bsp/at32/libraries/rt_drivers/config/f415/dma_config.h index baf1d36c5d..89c3f242cd 100644 --- a/bsp/at32/libraries/rt_drivers/config/f415/dma_config.h +++ b/bsp/at32/libraries/rt_drivers/config/f415/dma_config.h @@ -55,6 +55,11 @@ extern "C" { #define UART1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define UART1_TX_DMA_CHANNEL DMA1_CHANNEL4 #define UART1_TX_DMA_IRQ DMA1_Channel4_IRQn +#elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_CHANNEL) +#define I2C2_TX_DMA_IRQHandler DMA1_Channel4_IRQHandler +#define I2C2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C2_TX_DMA_CHANNEL DMA1_CHANNEL4 +#define I2C2_TX_DMA_IRQ DMA1_Channel4_IRQn #endif /* DMA1 channel5 */ @@ -68,6 +73,11 @@ extern "C" { #define UART1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define UART1_RX_DMA_CHANNEL DMA1_CHANNEL5 #define UART1_RX_DMA_IRQ DMA1_Channel5_IRQn +#elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_CHANNEL) +#define I2C2_RX_DMA_IRQHandler DMA1_Channel5_IRQHandler +#define I2C2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C2_RX_DMA_CHANNEL DMA1_CHANNEL5 +#define I2C2_RX_DMA_IRQ DMA1_Channel5_IRQn #endif /* DMA1 channel6 */ @@ -76,6 +86,11 @@ extern "C" { #define UART2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define UART2_RX_DMA_CHANNEL DMA1_CHANNEL6 #define UART2_RX_DMA_IRQ DMA1_Channel6_IRQn +#elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_CHANNEL) +#define I2C1_TX_DMA_IRQHandler DMA1_Channel6_IRQHandler +#define I2C1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C1_TX_DMA_CHANNEL DMA1_CHANNEL6 +#define I2C1_TX_DMA_IRQ DMA1_Channel6_IRQn #endif /* DMA1 channel7 */ @@ -84,6 +99,11 @@ extern "C" { #define UART2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define UART2_TX_DMA_CHANNEL DMA1_CHANNEL7 #define UART2_TX_DMA_IRQ DMA1_Channel7_IRQn +#elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_CHANNEL) +#define I2C1_RX_DMA_IRQHandler DMA1_Channel7_IRQHandler +#define I2C1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C1_RX_DMA_CHANNEL DMA1_CHANNEL7 +#define I2C1_RX_DMA_IRQ DMA1_Channel7_IRQn #endif /* DMA2 channel3 */ diff --git a/bsp/at32/libraries/rt_drivers/config/f415/i2c_config.h b/bsp/at32/libraries/rt_drivers/config/f415/i2c_config.h new file mode 100644 index 0000000000..fe34d4bb32 --- /dev/null +++ b/bsp/at32/libraries/rt_drivers/config/f415/i2c_config.h @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-07-31 shelton first version + */ + +#ifndef __I2C_CONFIG_H__ +#define __I2C_CONFIG_H__ + +#include +#include "dma_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define HWI2C_OWN_ADDRESS 0x0 + +#define I2C1_EVT_IRQHandler I2C1_EVT_IRQHandler +#define I2C1_ERR_IRQHandler I2C1_ERR_IRQHandler +#define I2C2_EVT_IRQHandler I2C2_EVT_IRQHandler +#define I2C2_ERR_IRQHandler I2C2_ERR_IRQHandler + +#ifdef BSP_USING_HARD_I2C1 +#define I2C1_CONFIG \ + { \ + .i2c_x = I2C1, \ + .i2c_name = "hwi2c1", \ + .timing = 100000, \ + .ev_irqn = I2C1_EVT_IRQn, \ + .er_irqn = I2C1_ERR_IRQn, \ + } +#endif /* BSP_USING_HARD_I2C1 */ + +#ifdef BSP_I2C1_RX_USING_DMA +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_channel = I2C1_RX_DMA_CHANNEL, \ + .dma_clock = I2C1_RX_DMA_CLOCK, \ + .dma_irqn = I2C1_RX_DMA_IRQ, \ + } +#endif /* BSP_I2C1_RX_USING_DMA */ + +#ifdef BSP_I2C1_TX_USING_DMA +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_channel = I2C1_TX_DMA_CHANNEL, \ + .dma_clock = I2C1_TX_DMA_CLOCK, \ + .dma_irqn = I2C1_TX_DMA_IRQ, \ + } +#endif /* BSP_I2C1_TX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C2 +#define I2C2_CONFIG \ + { \ + .i2c_x = I2C2, \ + .i2c_name = "hwi2c2", \ + .timing = 100000, \ + .ev_irqn = I2C2_EVT_IRQn, \ + .er_irqn = I2C2_ERR_IRQn, \ + } +#endif /* BSP_USING_HARD_I2C2 */ + +#ifdef BSP_I2C2_RX_USING_DMA +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_channel = I2C2_RX_DMA_CHANNEL, \ + .dma_clock = I2C2_RX_DMA_CLOCK, \ + .dma_irqn = I2C2_RX_DMA_IRQ, \ + } +#endif /* BSP_I2C2_RX_USING_DMA */ + +#ifdef BSP_I2C2_TX_USING_DMA +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_channel = I2C2_TX_DMA_CHANNEL, \ + .dma_clock = I2C2_TX_DMA_CLOCK, \ + .dma_irqn = I2C2_TX_DMA_IRQ, \ + } +#endif /* BSP_I2C2_TX_USING_DMA */ + +#ifdef __cplusplus +} +#endif + +#endif /*__I2C_CONFIG_H__ */ + diff --git a/bsp/at32/libraries/rt_drivers/config/f421/dma_config.h b/bsp/at32/libraries/rt_drivers/config/f421/dma_config.h index cb92ac4807..e68ca7a62e 100644 --- a/bsp/at32/libraries/rt_drivers/config/f421/dma_config.h +++ b/bsp/at32/libraries/rt_drivers/config/f421/dma_config.h @@ -29,6 +29,11 @@ extern "C" { #define UART1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define UART1_TX_DMA_CHANNEL DMA1_CHANNEL2 #define UART1_TX_DMA_IRQ DMA1_Channel3_2_IRQn +#elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_CHANNEL) +#define I2C1_TX_RX_DMA_IRQHandler DMA1_Channel3_2_IRQHandler +#define I2C1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C1_TX_DMA_CHANNEL DMA1_CHANNEL2 +#define I2C1_TX_DMA_IRQ DMA1_Channel3_2_IRQn #endif /* DMA1 channel3 */ @@ -42,6 +47,11 @@ extern "C" { #define UART1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define UART1_RX_DMA_CHANNEL DMA1_CHANNEL3 #define UART1_RX_DMA_IRQ DMA1_Channel3_2_IRQn +#elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_CHANNEL) +#define I2C1_TX_RX_DMA_IRQHandler DMA1_Channel3_2_IRQHandler +#define I2C1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C1_RX_DMA_CHANNEL DMA1_CHANNEL3 +#define I2C1_RX_DMA_IRQ DMA1_Channel3_2_IRQn #endif /* DMA1 channel4 */ @@ -55,6 +65,11 @@ extern "C" { #define UART2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define UART2_TX_DMA_CHANNEL DMA1_CHANNEL4 #define UART2_TX_DMA_IRQ DMA1_Channel5_4_IRQn +#elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_CHANNEL) +#define I2C2_TX_RX_DMA_IRQHandler DMA1_Channel5_4_IRQHandler +#define I2C2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C2_TX_DMA_CHANNEL DMA1_CHANNEL4 +#define I2C2_TX_DMA_IRQ DMA1_Channel5_4_IRQn #endif /* DMA1 channel5 */ @@ -68,6 +83,11 @@ extern "C" { #define UART2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK #define UART2_RX_DMA_CHANNEL DMA1_CHANNEL5 #define UART2_RX_DMA_IRQ DMA1_Channel5_4_IRQn +#elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_CHANNEL) +#define I2C2_TX_RX_DMA_IRQHandler DMA1_Channel5_4_IRQHandler +#define I2C2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C2_RX_DMA_CHANNEL DMA1_CHANNEL5 +#define I2C2_RX_DMA_IRQ DMA1_Channel5_4_IRQn #endif #ifdef __cplusplus diff --git a/bsp/at32/libraries/rt_drivers/config/f421/i2c_config.h b/bsp/at32/libraries/rt_drivers/config/f421/i2c_config.h new file mode 100644 index 0000000000..fe34d4bb32 --- /dev/null +++ b/bsp/at32/libraries/rt_drivers/config/f421/i2c_config.h @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-07-31 shelton first version + */ + +#ifndef __I2C_CONFIG_H__ +#define __I2C_CONFIG_H__ + +#include +#include "dma_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define HWI2C_OWN_ADDRESS 0x0 + +#define I2C1_EVT_IRQHandler I2C1_EVT_IRQHandler +#define I2C1_ERR_IRQHandler I2C1_ERR_IRQHandler +#define I2C2_EVT_IRQHandler I2C2_EVT_IRQHandler +#define I2C2_ERR_IRQHandler I2C2_ERR_IRQHandler + +#ifdef BSP_USING_HARD_I2C1 +#define I2C1_CONFIG \ + { \ + .i2c_x = I2C1, \ + .i2c_name = "hwi2c1", \ + .timing = 100000, \ + .ev_irqn = I2C1_EVT_IRQn, \ + .er_irqn = I2C1_ERR_IRQn, \ + } +#endif /* BSP_USING_HARD_I2C1 */ + +#ifdef BSP_I2C1_RX_USING_DMA +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_channel = I2C1_RX_DMA_CHANNEL, \ + .dma_clock = I2C1_RX_DMA_CLOCK, \ + .dma_irqn = I2C1_RX_DMA_IRQ, \ + } +#endif /* BSP_I2C1_RX_USING_DMA */ + +#ifdef BSP_I2C1_TX_USING_DMA +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_channel = I2C1_TX_DMA_CHANNEL, \ + .dma_clock = I2C1_TX_DMA_CLOCK, \ + .dma_irqn = I2C1_TX_DMA_IRQ, \ + } +#endif /* BSP_I2C1_TX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C2 +#define I2C2_CONFIG \ + { \ + .i2c_x = I2C2, \ + .i2c_name = "hwi2c2", \ + .timing = 100000, \ + .ev_irqn = I2C2_EVT_IRQn, \ + .er_irqn = I2C2_ERR_IRQn, \ + } +#endif /* BSP_USING_HARD_I2C2 */ + +#ifdef BSP_I2C2_RX_USING_DMA +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_channel = I2C2_RX_DMA_CHANNEL, \ + .dma_clock = I2C2_RX_DMA_CLOCK, \ + .dma_irqn = I2C2_RX_DMA_IRQ, \ + } +#endif /* BSP_I2C2_RX_USING_DMA */ + +#ifdef BSP_I2C2_TX_USING_DMA +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_channel = I2C2_TX_DMA_CHANNEL, \ + .dma_clock = I2C2_TX_DMA_CLOCK, \ + .dma_irqn = I2C2_TX_DMA_IRQ, \ + } +#endif /* BSP_I2C2_TX_USING_DMA */ + +#ifdef __cplusplus +} +#endif + +#endif /*__I2C_CONFIG_H__ */ + diff --git a/bsp/at32/libraries/rt_drivers/config/f423/dma_config.h b/bsp/at32/libraries/rt_drivers/config/f423/dma_config.h index be8118cf93..0777309a41 100644 --- a/bsp/at32/libraries/rt_drivers/config/f423/dma_config.h +++ b/bsp/at32/libraries/rt_drivers/config/f423/dma_config.h @@ -32,6 +32,13 @@ extern "C" { #define UART1_RX_DMA_IRQ DMA1_Channel1_IRQn #define UART1_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL1 #define UART1_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART1_RX +#elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_CHANNEL) +#define I2C1_RX_DMA_IRQHandler DMA1_Channel1_IRQHandler +#define I2C1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C1_RX_DMA_CHANNEL DMA1_CHANNEL1 +#define I2C1_RX_DMA_IRQ DMA1_Channel1_IRQn +#define I2C1_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL1 +#define I2C1_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C1_RX #endif /* DMA1 channel2 */ @@ -49,6 +56,13 @@ extern "C" { #define UART1_TX_DMA_IRQ DMA1_Channel2_IRQn #define UART1_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL2 #define UART1_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART1_TX +#elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_CHANNEL) +#define I2C1_TX_DMA_IRQHandler DMA1_Channel2_IRQHandler +#define I2C1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C1_TX_DMA_CHANNEL DMA1_CHANNEL2 +#define I2C1_TX_DMA_IRQ DMA1_Channel2_IRQn +#define I2C1_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL2 +#define I2C1_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C1_TX #endif /* DMA1 channel3 */ @@ -66,6 +80,13 @@ extern "C" { #define UART2_RX_DMA_IRQ DMA1_Channel3_IRQn #define UART2_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL3 #define UART2_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART2_RX +#elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_CHANNEL) +#define I2C2_RX_DMA_IRQHandler DMA1_Channel3_IRQHandler +#define I2C2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C2_RX_DMA_CHANNEL DMA1_CHANNEL3 +#define I2C2_RX_DMA_IRQ DMA1_Channel3_IRQn +#define I2C2_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL3 +#define I2C2_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C2_RX #endif /* DMA1 channel4 */ @@ -83,6 +104,13 @@ extern "C" { #define UART2_TX_DMA_IRQ DMA1_Channel4_IRQn #define UART2_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL4 #define UART2_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART2_TX +#elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_CHANNEL) +#define I2C2_TX_DMA_IRQHandler DMA1_Channel4_IRQHandler +#define I2C2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C2_TX_DMA_CHANNEL DMA1_CHANNEL4 +#define I2C2_TX_DMA_IRQ DMA1_Channel4_IRQn +#define I2C2_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL4 +#define I2C2_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C2_TX #endif /* DMA1 channel5 */ @@ -100,6 +128,13 @@ extern "C" { #define UART3_RX_DMA_IRQ DMA1_Channel5_IRQn #define UART3_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL5 #define UART3_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART3_RX +#elif defined(BSP_I2C3_RX_USING_DMA) && !defined(I2C3_RX_DMA_CHANNEL) +#define I2C3_RX_DMA_IRQHandler DMA1_Channel5_IRQHandler +#define I2C3_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C3_RX_DMA_CHANNEL DMA1_CHANNEL5 +#define I2C3_RX_DMA_IRQ DMA1_Channel5_IRQn +#define I2C3_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL5 +#define I2C3_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C3_RX #endif /* DMA1 channel6 */ @@ -117,6 +152,13 @@ extern "C" { #define UART3_TX_DMA_IRQ DMA1_Channel6_IRQn #define UART3_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL6 #define UART3_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART3_TX +#elif defined(BSP_I2C3_TX_USING_DMA) && !defined(I2C3_TX_DMA_CHANNEL) +#define I2C3_TX_DMA_IRQHandler DMA1_Channel6_IRQHandler +#define I2C3_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C3_TX_DMA_CHANNEL DMA1_CHANNEL6 +#define I2C3_TX_DMA_IRQ DMA1_Channel6_IRQn +#define I2C3_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL6 +#define I2C3_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C3_TX #endif /* DMA1 channel7 */ @@ -162,7 +204,7 @@ extern "C" { /* DMA2 channel4 */ #if defined(BSP_UART6_RX_USING_DMA) && !defined(UART6_RX_DMA_CHANNEL) #define UART6_RX_DMA_IRQHandler DMA2_Channel4_IRQHandler -#define UART6_RX_DMA_CLOCK CRM_DMA4_PERIPH_CLOCK +#define UART6_RX_DMA_CLOCK CRM_DMA2_PERIPH_CLOCK #define UART6_RX_DMA_CHANNEL DMA2_CHANNEL4 #define UART6_RX_DMA_IRQ DMA2_Channel4_IRQn #define UART6_RX_DMA_MUX_CHANNEL DMA2MUX_CHANNEL4 diff --git a/bsp/at32/libraries/rt_drivers/config/f423/i2c_config.h b/bsp/at32/libraries/rt_drivers/config/f423/i2c_config.h new file mode 100644 index 0000000000..6bc2a184ef --- /dev/null +++ b/bsp/at32/libraries/rt_drivers/config/f423/i2c_config.h @@ -0,0 +1,134 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-07-31 shelton first version + */ + +#ifndef __I2C_CONFIG_H__ +#define __I2C_CONFIG_H__ + +#include +#include "dma_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define HWI2C_OWN_ADDRESS 0x0 + +#define I2C1_EVT_IRQHandler I2C1_EVT_IRQHandler +#define I2C1_ERR_IRQHandler I2C1_ERR_IRQHandler +#define I2C2_EVT_IRQHandler I2C2_EVT_IRQHandler +#define I2C2_ERR_IRQHandler I2C2_ERR_IRQHandler +#define I2C3_EVT_IRQHandler I2C3_EVT_IRQHandler +#define I2C3_ERR_IRQHandler I2C3_ERR_IRQHandler + +#ifdef BSP_USING_HARD_I2C1 +#define I2C1_CONFIG \ + { \ + .i2c_x = I2C1, \ + .i2c_name = "hwi2c1", \ + .timing = 0x60E02E2E, \ + .ev_irqn = I2C1_EVT_IRQn, \ + .er_irqn = I2C1_ERR_IRQn, \ + } +#endif /* BSP_USING_HARD_I2C1 */ + +#ifdef BSP_I2C1_RX_USING_DMA +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_channel = I2C1_RX_DMA_CHANNEL, \ + .dma_clock = I2C1_RX_DMA_CLOCK, \ + .dma_irqn = I2C1_RX_DMA_IRQ, \ + .dmamux_channel = I2C1_RX_DMA_MUX_CHANNEL, \ + .request_id = I2C1_RX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C1_RX_USING_DMA */ + +#ifdef BSP_I2C1_TX_USING_DMA +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_channel = I2C1_TX_DMA_CHANNEL, \ + .dma_clock = I2C1_TX_DMA_CLOCK, \ + .dma_irqn = I2C1_TX_DMA_IRQ, \ + .dmamux_channel = I2C1_TX_DMA_MUX_CHANNEL, \ + .request_id = I2C1_TX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C1_TX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C2 +#define I2C2_CONFIG \ + { \ + .i2c_x = I2C2, \ + .i2c_name = "hwi2c2", \ + .timing = 0x60E02E2E, \ + .ev_irqn = I2C2_EVT_IRQn, \ + .er_irqn = I2C2_ERR_IRQn, \ + } +#endif /* BSP_USING_HARD_I2C2 */ + +#ifdef BSP_I2C2_RX_USING_DMA +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_channel = I2C2_RX_DMA_CHANNEL, \ + .dma_clock = I2C2_RX_DMA_CLOCK, \ + .dma_irqn = I2C2_RX_DMA_IRQ, \ + .dmamux_channel = I2C2_RX_DMA_MUX_CHANNEL, \ + .request_id = I2C2_RX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C2_RX_USING_DMA */ + +#ifdef BSP_I2C2_TX_USING_DMA +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_channel = I2C2_TX_DMA_CHANNEL, \ + .dma_clock = I2C2_TX_DMA_CLOCK, \ + .dma_irqn = I2C2_TX_DMA_IRQ, \ + .dmamux_channel = I2C2_TX_DMA_MUX_CHANNEL, \ + .request_id = I2C2_TX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C2_TX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C3 +#define I2C3_CONFIG \ + { \ + .i2c_x = I2C3, \ + .i2c_name = "hwi2c3", \ + .timing = 0x60E02E2E, \ + .ev_irqn = I2C3_EVT_IRQn, \ + .er_irqn = I2C3_ERR_IRQn, \ + } +#endif /* BSP_USING_HARD_I2C3 */ + +#ifdef BSP_I2C3_RX_USING_DMA +#define I2C3_RX_DMA_CONFIG \ + { \ + .dma_channel = I2C3_RX_DMA_CHANNEL, \ + .dma_clock = I2C3_RX_DMA_CLOCK, \ + .dma_irqn = I2C3_RX_DMA_IRQ, \ + .dmamux_channel = I2C3_RX_DMA_MUX_CHANNEL, \ + .request_id = I2C3_RX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C3_RX_USING_DMA */ + +#ifdef BSP_I2C3_TX_USING_DMA +#define I2C3_TX_DMA_CONFIG \ + { \ + .dma_channel = I2C3_TX_DMA_CHANNEL, \ + .dma_clock = I2C3_TX_DMA_CLOCK, \ + .dma_irqn = I2C3_TX_DMA_IRQ, \ + .dmamux_channel = I2C3_TX_DMA_MUX_CHANNEL, \ + .request_id = I2C3_TX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C3_TX_USING_DMA */ + +#ifdef __cplusplus +} +#endif + +#endif /*__I2C_CONFIG_H__ */ + diff --git a/bsp/at32/libraries/rt_drivers/config/f425/dma_config.h b/bsp/at32/libraries/rt_drivers/config/f425/dma_config.h index 1577a135f2..69119922b6 100644 --- a/bsp/at32/libraries/rt_drivers/config/f425/dma_config.h +++ b/bsp/at32/libraries/rt_drivers/config/f425/dma_config.h @@ -33,6 +33,13 @@ extern "C" { #define UART1_RX_DMA_IRQ DMA1_Channel3_2_IRQn #define UART1_RX_DMA_FLEX_CHANNEL FLEX_CHANNEL2 #define UART1_RX_DMA_REQ_ID DMA_FLEXIBLE_UART1_RX +#elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_CHANNEL) +#define I2C1_TX_RX_DMA_IRQHandler DMA1_Channel3_2_IRQHandler +#define I2C1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C1_RX_DMA_CHANNEL DMA1_CHANNEL2 +#define I2C1_RX_DMA_IRQ DMA1_Channel3_2_IRQn +#define I2C1_RX_DMA_FLEX_CHANNEL FLEX_CHANNEL2 +#define I2C1_RX_DMA_REQ_ID DMA_FLEXIBLE_I2C1_RX #endif /* DMA1 channel3 */ @@ -50,6 +57,13 @@ extern "C" { #define UART1_TX_DMA_IRQ DMA1_Channel3_2_IRQn #define UART1_TX_DMA_FLEX_CHANNEL FLEX_CHANNEL3 #define UART1_TX_DMA_REQ_ID DMA_FLEXIBLE_UART1_TX +#elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_CHANNEL) +#define I2C1_TX_RX_DMA_IRQHandler DMA1_Channel3_2_IRQHandler +#define I2C1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C1_TX_DMA_CHANNEL DMA1_CHANNEL3 +#define I2C1_TX_DMA_IRQ DMA1_Channel3_2_IRQn +#define I2C1_TX_DMA_FLEX_CHANNEL FLEX_CHANNEL3 +#define I2C1_TX_DMA_REQ_ID DMA_FLEXIBLE_I2C1_TX #endif /* DMA1 channel4 */ @@ -67,6 +81,13 @@ extern "C" { #define UART2_RX_DMA_IRQ DMA1_Channel7_4_IRQn #define UART2_RX_DMA_FLEX_CHANNEL FLEX_CHANNEL4 #define UART2_RX_DMA_REQ_ID DMA_FLEXIBLE_UART2_RX +#elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_CHANNEL) +#define I2C2_TX_RX_DMA_IRQHandler DMA1_Channel7_4_IRQHandler +#define I2C2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C2_RX_DMA_CHANNEL DMA1_CHANNEL4 +#define I2C2_RX_DMA_IRQ DMA1_Channel7_4_IRQn +#define I2C2_RX_DMA_FLEX_CHANNEL FLEX_CHANNEL4 +#define I2C2_RX_DMA_REQ_ID DMA_FLEXIBLE_I2C2_RX #endif /* DMA1 channel5 */ @@ -84,6 +105,13 @@ extern "C" { #define UART2_TX_DMA_IRQ DMA1_Channel7_4_IRQn #define UART2_TX_DMA_FLEX_CHANNEL FLEX_CHANNEL5 #define UART2_TX_DMA_REQ_ID DMA_FLEXIBLE_UART2_TX +#elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_CHANNEL) +#define I2C2_TX_RX_DMA_IRQHandler DMA1_Channel7_4_IRQHandler +#define I2C2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C2_TX_DMA_CHANNEL DMA1_CHANNEL5 +#define I2C2_TX_DMA_IRQ DMA1_Channel7_4_IRQn +#define I2C2_TX_DMA_FLEX_CHANNEL FLEX_CHANNEL5 +#define I2C2_TX_DMA_REQ_ID DMA_FLEXIBLE_I2C2_TX #endif /* DMA1 channel6 */ diff --git a/bsp/at32/libraries/rt_drivers/config/f425/i2c_config.h b/bsp/at32/libraries/rt_drivers/config/f425/i2c_config.h new file mode 100644 index 0000000000..3674786c0b --- /dev/null +++ b/bsp/at32/libraries/rt_drivers/config/f425/i2c_config.h @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-07-31 shelton first version + */ + +#ifndef __I2C_CONFIG_H__ +#define __I2C_CONFIG_H__ + +#include +#include "dma_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define HWI2C_OWN_ADDRESS 0x0 + +#define I2C1_EVT_IRQHandler I2C1_EVT_IRQHandler +#define I2C1_ERR_IRQHandler I2C1_ERR_IRQHandler +#define I2C2_EVT_IRQHandler I2C2_EVT_IRQHandler +#define I2C2_ERR_IRQHandler I2C2_ERR_IRQHandler + +#ifdef BSP_USING_HARD_I2C1 +#define I2C1_CONFIG \ + { \ + .i2c_x = I2C1, \ + .i2c_name = "hwi2c1", \ + .timing = 0x80E02E2E, \ + .ev_irqn = I2C1_EVT_IRQn, \ + .er_irqn = I2C1_ERR_IRQn, \ + } +#endif /* BSP_USING_HARD_I2C1 */ + +#ifdef BSP_I2C1_RX_USING_DMA +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_channel = I2C1_RX_DMA_CHANNEL, \ + .dma_clock = I2C1_RX_DMA_CLOCK, \ + .dma_irqn = I2C1_RX_DMA_IRQ, \ + .flex_channel = I2C1_RX_DMA_FLEX_CHANNEL, \ + .request_id = I2C1_RX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C1_RX_USING_DMA */ + +#ifdef BSP_I2C1_TX_USING_DMA +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_channel = I2C1_TX_DMA_CHANNEL, \ + .dma_clock = I2C1_TX_DMA_CLOCK, \ + .dma_irqn = I2C1_TX_DMA_IRQ, \ + .flex_channel = I2C1_TX_DMA_FLEX_CHANNEL, \ + .request_id = I2C1_TX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C1_TX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C2 +#define I2C2_CONFIG \ + { \ + .i2c_x = I2C2, \ + .i2c_name = "hwi2c2", \ + .timing = 0x80E02E2E, \ + .ev_irqn = I2C2_EVT_IRQn, \ + .er_irqn = I2C2_ERR_IRQn, \ + } +#endif /* BSP_USING_HARD_I2C2 */ + +#ifdef BSP_I2C2_RX_USING_DMA +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_channel = I2C2_RX_DMA_CHANNEL, \ + .dma_clock = I2C2_RX_DMA_CLOCK, \ + .dma_irqn = I2C2_RX_DMA_IRQ, \ + .flex_channel = I2C2_RX_DMA_FLEX_CHANNEL, \ + .request_id = I2C2_RX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C2_RX_USING_DMA */ + +#ifdef BSP_I2C2_TX_USING_DMA +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_channel = I2C2_TX_DMA_CHANNEL, \ + .dma_clock = I2C2_TX_DMA_CLOCK, \ + .dma_irqn = I2C2_TX_DMA_IRQ, \ + .flex_channel = I2C2_TX_DMA_FLEX_CHANNEL, \ + .request_id = I2C2_TX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C2_TX_USING_DMA */ + +#ifdef __cplusplus +} +#endif + +#endif /*__I2C_CONFIG_H__ */ + diff --git a/bsp/at32/libraries/rt_drivers/config/f435_437/dma_config.h b/bsp/at32/libraries/rt_drivers/config/f435_437/dma_config.h index 2ef2f1cf29..8fbdc4dcd3 100644 --- a/bsp/at32/libraries/rt_drivers/config/f435_437/dma_config.h +++ b/bsp/at32/libraries/rt_drivers/config/f435_437/dma_config.h @@ -32,6 +32,13 @@ extern "C" { #define UART1_RX_DMA_IRQ DMA1_Channel1_IRQn #define UART1_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL1 #define UART1_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART1_RX +#elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_CHANNEL) +#define I2C1_RX_DMA_IRQHandler DMA1_Channel1_IRQHandler +#define I2C1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C1_RX_DMA_CHANNEL DMA1_CHANNEL1 +#define I2C1_RX_DMA_IRQ DMA1_Channel1_IRQn +#define I2C1_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL1 +#define I2C1_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C1_RX #endif /* DMA1 channel2 */ @@ -49,6 +56,13 @@ extern "C" { #define UART1_TX_DMA_IRQ DMA1_Channel2_IRQn #define UART1_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL2 #define UART1_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART1_TX +#elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_CHANNEL) +#define I2C1_TX_DMA_IRQHandler DMA1_Channel2_IRQHandler +#define I2C1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C1_TX_DMA_CHANNEL DMA1_CHANNEL2 +#define I2C1_TX_DMA_IRQ DMA1_Channel2_IRQn +#define I2C1_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL2 +#define I2C1_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C1_TX #endif /* DMA1 channel3 */ @@ -66,6 +80,13 @@ extern "C" { #define UART2_RX_DMA_IRQ DMA1_Channel3_IRQn #define UART2_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL3 #define UART2_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART2_RX +#elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_CHANNEL) +#define I2C2_RX_DMA_IRQHandler DMA1_Channel3_IRQHandler +#define I2C2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C2_RX_DMA_CHANNEL DMA1_CHANNEL3 +#define I2C2_RX_DMA_IRQ DMA1_Channel3_IRQn +#define I2C2_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL3 +#define I2C2_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C2_RX #endif /* DMA1 channel4 */ @@ -83,6 +104,13 @@ extern "C" { #define UART2_TX_DMA_IRQ DMA1_Channel4_IRQn #define UART2_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL4 #define UART2_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART2_TX +#elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_CHANNEL) +#define I2C2_TX_DMA_IRQHandler DMA1_Channel4_IRQHandler +#define I2C2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C2_TX_DMA_CHANNEL DMA1_CHANNEL4 +#define I2C2_TX_DMA_IRQ DMA1_Channel4_IRQn +#define I2C2_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL4 +#define I2C2_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C2_TX #endif /* DMA1 channel5 */ @@ -100,6 +128,13 @@ extern "C" { #define UART3_RX_DMA_IRQ DMA1_Channel5_IRQn #define UART3_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL5 #define UART3_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART3_RX +#elif defined(BSP_I2C3_RX_USING_DMA) && !defined(I2C3_RX_DMA_CHANNEL) +#define I2C3_RX_DMA_IRQHandler DMA1_Channel5_IRQHandler +#define I2C3_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C3_RX_DMA_CHANNEL DMA1_CHANNEL5 +#define I2C3_RX_DMA_IRQ DMA1_Channel5_IRQn +#define I2C3_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL5 +#define I2C3_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C3_RX #endif /* DMA1 channel6 */ @@ -117,6 +152,13 @@ extern "C" { #define UART3_TX_DMA_IRQ DMA1_Channel6_IRQn #define UART3_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL6 #define UART3_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART3_TX +#elif defined(BSP_I2C3_TX_USING_DMA) && !defined(I2C3_TX_DMA_CHANNEL) +#define I2C3_TX_DMA_IRQHandler DMA1_Channel6_IRQHandler +#define I2C3_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK +#define I2C3_TX_DMA_CHANNEL DMA1_CHANNEL6 +#define I2C3_TX_DMA_IRQ DMA1_Channel6_IRQn +#define I2C3_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL6 +#define I2C3_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C3_TX #endif /* DMA1 channel7 */ diff --git a/bsp/at32/libraries/rt_drivers/config/f435_437/i2c_config.h b/bsp/at32/libraries/rt_drivers/config/f435_437/i2c_config.h new file mode 100644 index 0000000000..e4867c1336 --- /dev/null +++ b/bsp/at32/libraries/rt_drivers/config/f435_437/i2c_config.h @@ -0,0 +1,134 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-07-31 shelton first version + */ + +#ifndef __I2C_CONFIG_H__ +#define __I2C_CONFIG_H__ + +#include +#include "dma_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define HWI2C_OWN_ADDRESS 0x0 + +#define I2C1_EVT_IRQHandler I2C1_EVT_IRQHandler +#define I2C1_ERR_IRQHandler I2C1_ERR_IRQHandler +#define I2C2_EVT_IRQHandler I2C2_EVT_IRQHandler +#define I2C2_ERR_IRQHandler I2C2_ERR_IRQHandler +#define I2C3_EVT_IRQHandler I2C3_EVT_IRQHandler +#define I2C3_ERR_IRQHandler I2C3_ERR_IRQHandler + +#ifdef BSP_USING_HARD_I2C1 +#define I2C1_CONFIG \ + { \ + .i2c_x = I2C1, \ + .i2c_name = "hwi2c1", \ + .timing = 0xC0F03030, \ + .ev_irqn = I2C1_EVT_IRQn, \ + .er_irqn = I2C1_ERR_IRQn, \ + } +#endif /* BSP_USING_HARD_I2C1 */ + +#ifdef BSP_I2C1_RX_USING_DMA +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_channel = I2C1_RX_DMA_CHANNEL, \ + .dma_clock = I2C1_RX_DMA_CLOCK, \ + .dma_irqn = I2C1_RX_DMA_IRQ, \ + .dmamux_channel = I2C1_RX_DMA_MUX_CHANNEL, \ + .request_id = I2C1_RX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C1_RX_USING_DMA */ + +#ifdef BSP_I2C1_TX_USING_DMA +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_channel = I2C1_TX_DMA_CHANNEL, \ + .dma_clock = I2C1_TX_DMA_CLOCK, \ + .dma_irqn = I2C1_TX_DMA_IRQ, \ + .dmamux_channel = I2C1_TX_DMA_MUX_CHANNEL, \ + .request_id = I2C1_TX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C1_TX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C2 +#define I2C2_CONFIG \ + { \ + .i2c_x = I2C2, \ + .i2c_name = "hwi2c2", \ + .timing = 0xC0F03030, \ + .ev_irqn = I2C2_EVT_IRQn, \ + .er_irqn = I2C2_ERR_IRQn, \ + } +#endif /* BSP_USING_HARD_I2C2 */ + +#ifdef BSP_I2C2_RX_USING_DMA +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_channel = I2C2_RX_DMA_CHANNEL, \ + .dma_clock = I2C2_RX_DMA_CLOCK, \ + .dma_irqn = I2C2_RX_DMA_IRQ, \ + .dmamux_channel = I2C2_RX_DMA_MUX_CHANNEL, \ + .request_id = I2C2_RX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C2_RX_USING_DMA */ + +#ifdef BSP_I2C2_TX_USING_DMA +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_channel = I2C2_TX_DMA_CHANNEL, \ + .dma_clock = I2C2_TX_DMA_CLOCK, \ + .dma_irqn = I2C2_TX_DMA_IRQ, \ + .dmamux_channel = I2C2_TX_DMA_MUX_CHANNEL, \ + .request_id = I2C2_TX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C2_TX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C3 +#define I2C3_CONFIG \ + { \ + .i2c_x = I2C3, \ + .i2c_name = "hwi2c3", \ + .timing = 0xC0F03030, \ + .ev_irqn = I2C3_EVT_IRQn, \ + .er_irqn = I2C3_ERR_IRQn, \ + } +#endif /* BSP_USING_HARD_I2C3 */ + +#ifdef BSP_I2C3_RX_USING_DMA +#define I2C3_RX_DMA_CONFIG \ + { \ + .dma_channel = I2C3_RX_DMA_CHANNEL, \ + .dma_clock = I2C3_RX_DMA_CLOCK, \ + .dma_irqn = I2C3_RX_DMA_IRQ, \ + .dmamux_channel = I2C3_RX_DMA_MUX_CHANNEL, \ + .request_id = I2C3_RX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C3_RX_USING_DMA */ + +#ifdef BSP_I2C3_TX_USING_DMA +#define I2C3_TX_DMA_CONFIG \ + { \ + .dma_channel = I2C3_TX_DMA_CHANNEL, \ + .dma_clock = I2C3_TX_DMA_CLOCK, \ + .dma_irqn = I2C3_TX_DMA_IRQ, \ + .dmamux_channel = I2C3_TX_DMA_MUX_CHANNEL, \ + .request_id = I2C3_TX_DMA_REQ_ID, \ + } +#endif /* BSP_I2C3_TX_USING_DMA */ + +#ifdef __cplusplus +} +#endif + +#endif /*__I2C_CONFIG_H__ */ + diff --git a/bsp/at32/libraries/rt_drivers/drv_config.h b/bsp/at32/libraries/rt_drivers/drv_config.h index 988b172f99..891271d2f3 100644 --- a/bsp/at32/libraries/rt_drivers/drv_config.h +++ b/bsp/at32/libraries/rt_drivers/drv_config.h @@ -10,6 +10,7 @@ * 2023-04-08 shelton add support f423 * 2023-10-18 shelton add support f402/f405 * 2024-04-12 shelton add support a403a and a423 + * 2024-07-31 shelton add support hwi2c driver */ #ifndef __DRV_CONFIG_H__ @@ -25,54 +26,64 @@ extern "C" { #if defined(SOC_SERIES_AT32A403A) #include "a403a/dma_config.h" #include "a403a/uart_config.h" +#include "a403a/i2c_config.h" #include "a403a/spi_config.h" #include "a403a/usb_config.h" #include "a403a/dac_config.h" #elif defined(SOC_SERIES_AT32A423) #include "a423/dma_config.h" #include "a423/uart_config.h" +#include "a423/i2c_config.h" #include "a423/spi_config.h" #include "a423/usb_config.h" #include "a423/dac_config.h" #elif defined(SOC_SERIES_AT32F402) || defined (SOC_SERIES_AT32F405) #include "f402_405/dma_config.h" #include "f402_405/uart_config.h" +#include "f402_405/i2c_config.h" #include "f402_405/spi_config.h" #include "f402_405/usb_config.h" #elif defined(SOC_SERIES_AT32F403A) || defined (SOC_SERIES_AT32F407) #include "f403a_407/dma_config.h" #include "f403a_407/uart_config.h" +#include "f403a_407/i2c_config.h" #include "f403a_407/spi_config.h" #include "f403a_407/usb_config.h" #include "f403a_407/dac_config.h" #elif defined(SOC_SERIES_AT32F413) #include "f413/dma_config.h" #include "f413/uart_config.h" +#include "f413/i2c_config.h" #include "f413/spi_config.h" #include "f413/usb_config.h" #elif defined(SOC_SERIES_AT32F415) #include "f415/dma_config.h" #include "f415/uart_config.h" +#include "f415/i2c_config.h" #include "f415/spi_config.h" #include "f415/usb_config.h" #elif defined(SOC_SERIES_AT32F421) #include "f421/dma_config.h" #include "f421/uart_config.h" +#include "f421/i2c_config.h" #include "f421/spi_config.h" #elif defined(SOC_SERIES_AT32F423) #include "f423/dma_config.h" #include "f423/uart_config.h" +#include "f423/i2c_config.h" #include "f423/spi_config.h" #include "f423/usb_config.h" #include "f423/dac_config.h" #elif defined(SOC_SERIES_AT32F425) #include "f425/dma_config.h" #include "f425/uart_config.h" +#include "f425/i2c_config.h" #include "f425/spi_config.h" #include "f425/usb_config.h" #elif defined(SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) #include "f435_437/dma_config.h" #include "f435_437/uart_config.h" +#include "f435_437/i2c_config.h" #include "f435_437/spi_config.h" #include "f435_437/usb_config.h" #include "f435_437/dac_config.h" diff --git a/bsp/at32/libraries/rt_drivers/drv_hard_i2c.c b/bsp/at32/libraries/rt_drivers/drv_hard_i2c.c new file mode 100644 index 0000000000..b6f5202e5e --- /dev/null +++ b/bsp/at32/libraries/rt_drivers/drv_hard_i2c.c @@ -0,0 +1,1695 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-07-31 shelton first version + */ + +#include "drv_common.h" +#include "drv_hard_i2c.h" +#include "drv_config.h" +#include + +#if defined(BSP_USING_HARD_I2C1) || defined(BSP_USING_HARD_I2C2) || \ + defined(BSP_USING_HARD_I2C3) + +//#define DRV_DEBUG +#define LOG_TAG "drv.hwi2c" +#include + +enum +{ +#ifdef BSP_USING_HARD_I2C1 + I2C1_INDEX, +#endif +#ifdef BSP_USING_HARD_I2C2 + I2C2_INDEX, +#endif +#ifdef BSP_USING_HARD_I2C3 + I2C3_INDEX, +#endif +}; + +static struct at32_i2c_handle i2c_handle[] = { +#ifdef BSP_USING_HARD_I2C1 + I2C1_CONFIG, +#endif + +#ifdef BSP_USING_HARD_I2C2 + I2C2_CONFIG, +#endif + +#ifdef BSP_USING_HARD_I2C3 + I2C3_CONFIG, +#endif +}; + +static struct at32_i2c i2cs[sizeof(i2c_handle) / sizeof(i2c_handle[0])] = {0}; + +/* private rt-thread i2c ops function */ +static rt_ssize_t master_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], rt_uint32_t num); +static struct rt_i2c_bus_device_ops at32_i2c_ops = +{ + master_xfer, + RT_NULL, + RT_NULL +}; + +static rt_err_t at32_i2c_configure(struct rt_i2c_bus_device *bus) +{ + RT_ASSERT(RT_NULL != bus); + struct at32_i2c *instance = rt_container_of(bus, struct at32_i2c, i2c_bus); + + at32_msp_i2c_init(instance->handle->i2c_x); + +#if defined (SOC_SERIES_AT32F403A) || defined (SOC_SERIES_AT32F407) || \ + defined (SOC_SERIES_AT32F413) || defined (SOC_SERIES_AT32F415) || \ + defined (SOC_SERIES_AT32F421) || defined (SOC_SERIES_AT32A403A) + i2c_init(instance->handle->i2c_x, I2C_FSMODE_DUTY_2_1, instance->handle->timing); +#endif +#if defined (SOC_SERIES_AT32F402) || defined (SOC_SERIES_AT32F405) || \ + defined (SOC_SERIES_AT32F423) || defined (SOC_SERIES_AT32F425) || \ + defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \ + defined (SOC_SERIES_AT32A423) + i2c_init(instance->handle->i2c_x, 0x0F, instance->handle->timing); +#endif + i2c_own_address1_set(instance->handle->i2c_x, I2C_ADDRESS_MODE_7BIT, HWI2C_OWN_ADDRESS); + + nvic_irq_enable(instance->handle->ev_irqn, 0, 0); + nvic_irq_enable(instance->handle->er_irqn, 0, 0); + + i2c_enable(instance->handle->i2c_x, TRUE); + + return RT_EOK; +} + +static void i2c_dma_config(struct at32_i2c_handle *handle, rt_uint8_t *buffer, rt_uint32_t size) +{ + struct dma_config *dma = RT_NULL; + + if(handle->comm.mode == I2C_DMA_MA_TX) + { + dma = handle->dma_tx; +#if defined (SOC_SERIES_AT32F403A) || defined (SOC_SERIES_AT32F407) || \ + defined (SOC_SERIES_AT32F413) || defined (SOC_SERIES_AT32F415) || \ + defined (SOC_SERIES_AT32F421) || defined (SOC_SERIES_AT32A403A) + dma->dma_channel->paddr = (rt_uint32_t)&(handle->i2c_x->dt); +#endif +#if defined (SOC_SERIES_AT32F402) || defined (SOC_SERIES_AT32F405) || \ + defined (SOC_SERIES_AT32F423) || defined (SOC_SERIES_AT32F425) || \ + defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \ + defined (SOC_SERIES_AT32A423) + dma->dma_channel->paddr = (rt_uint32_t)&(handle->i2c_x->txdt); +#endif + } + else if(handle->comm.mode == I2C_DMA_MA_RX) + { + dma = handle->dma_rx; +#if defined (SOC_SERIES_AT32F403A) || defined (SOC_SERIES_AT32F407) || \ + defined (SOC_SERIES_AT32F413) || defined (SOC_SERIES_AT32F415) || \ + defined (SOC_SERIES_AT32F421) || defined (SOC_SERIES_AT32A403A) + dma->dma_channel->paddr = (rt_uint32_t)&(handle->i2c_x->dt); +#endif +#if defined (SOC_SERIES_AT32F402) || defined (SOC_SERIES_AT32F405) || \ + defined (SOC_SERIES_AT32F423) || defined (SOC_SERIES_AT32F425) || \ + defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \ + defined (SOC_SERIES_AT32A423) + dma->dma_channel->paddr = (rt_uint32_t)&(handle->i2c_x->rxdt); +#endif + } + + dma->dma_channel->dtcnt = size; + dma->dma_channel->maddr = (rt_uint32_t)buffer; + + /* enable transmit complete interrupt */ + dma_interrupt_enable(dma->dma_channel, DMA_FDT_INT, TRUE); + + /* mark dma flag */ + dma->dma_done = RT_FALSE; + /* enable dma channel */ + dma_channel_enable(dma->dma_channel, TRUE); +} + +#if defined (SOC_SERIES_AT32F402) || defined (SOC_SERIES_AT32F405) || \ + defined (SOC_SERIES_AT32F423) || defined (SOC_SERIES_AT32F425) || \ + defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \ + defined (SOC_SERIES_AT32A423) +void i2c_refresh_txdt_register(i2c_type *i2c_x) +{ + /* clear tdis flag */ + if (i2c_flag_get(i2c_x, I2C_TDIS_FLAG) != RESET) + { + i2c_x->txdt = 0x00; + } + /* refresh txdt register*/ + if (i2c_flag_get(i2c_x, I2C_TDBE_FLAG) == RESET) + { + i2c_x->sts_bit.tdbe = 1; + } +} + +void i2c_reset_ctrl2_register(i2c_type *i2c_x) +{ + i2c_x->ctrl2_bit.saddr = 0; + i2c_x->ctrl2_bit.readh10 = 0; + i2c_x->ctrl2_bit.cnt = 0; + i2c_x->ctrl2_bit.rlden = 0; + i2c_x->ctrl2_bit.dir = 0; +} +#endif + +i2c_status_type i2c_wait_end(struct at32_i2c_handle *handle, uint32_t timeout) +{ + while(handle->comm.status != I2C_END) + { + /* check timeout */ + if((timeout--) == 0) + { + return I2C_ERR_TIMEOUT; + } + } + + if(handle->comm.error_code != I2C_OK) + { + return handle->comm.error_code; + } + else + { + return I2C_OK; + } +} + +i2c_status_type i2c_wait_flag(struct at32_i2c_handle *handle, uint32_t flag, uint32_t event_check, uint32_t timeout) +{ + if(flag == I2C_BUSYF_FLAG) + { + while(i2c_flag_get(handle->i2c_x, flag) != RESET) + { + /* check timeout */ + if((timeout--) == 0) + { + handle->comm.error_code = I2C_ERR_TIMEOUT; + + return I2C_ERR_TIMEOUT; + } + } + } + else + { + while(i2c_flag_get(handle->i2c_x, flag) == RESET) + { + /* check the ack fail flag */ + if(event_check & I2C_EVENT_CHECK_ACKFAIL) + { + if(i2c_flag_get(handle->i2c_x, I2C_ACKFAIL_FLAG) != RESET) + { +#if defined (SOC_SERIES_AT32F403A) || defined (SOC_SERIES_AT32F407) || \ + defined (SOC_SERIES_AT32F413) || defined (SOC_SERIES_AT32F415) || \ + defined (SOC_SERIES_AT32F421) || defined (SOC_SERIES_AT32A403A) + /* generate stop condtion */ + i2c_stop_generate(handle->i2c_x); +#endif + /* clear ack fail flag */ + i2c_flag_clear(handle->i2c_x, I2C_ACKFAIL_FLAG); + + handle->comm.error_code = I2C_ERR_ACKFAIL; + + return I2C_ERR_ACKFAIL; + } + } + + /* check the stop flag */ + if(event_check & I2C_EVENT_CHECK_STOP) + { + if(i2c_flag_get(handle->i2c_x, I2C_STOPF_FLAG) != RESET) + { + /* clear stop flag */ + i2c_flag_clear(handle->i2c_x, I2C_STOPF_FLAG); +#if defined (SOC_SERIES_AT32F402) || defined (SOC_SERIES_AT32F405) || \ + defined (SOC_SERIES_AT32F423) || defined (SOC_SERIES_AT32F425) || \ + defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \ + defined (SOC_SERIES_AT32A423) + i2c_reset_ctrl2_register(handle->i2c_x); +#endif + handle->comm.error_code = I2C_ERR_STOP; + + return I2C_ERR_STOP; + } + } + + /* check timeout */ + if((timeout--) == 0) + { + handle->comm.error_code = I2C_ERR_TIMEOUT; + + return I2C_ERR_TIMEOUT; + } + } + } + + return I2C_OK; +} + +#if defined (SOC_SERIES_AT32F403A) || defined (SOC_SERIES_AT32F407) || \ + defined (SOC_SERIES_AT32F413) || defined (SOC_SERIES_AT32F415) || \ + defined (SOC_SERIES_AT32F421) || defined (SOC_SERIES_AT32A403A) +i2c_status_type i2c_master_write_addr(struct at32_i2c_handle *handle, uint16_t address, uint32_t timeout) +{ + /* generate start condtion */ + i2c_start_generate(handle->i2c_x); + + /* wait for the start flag to be set */ + if(i2c_wait_flag(handle, I2C_STARTF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK) + { + handle->comm.error_code = I2C_ERR_START; + + return I2C_ERR_START; + } + + if(handle->i2c_x->oaddr1_bit.addr1mode == I2C_ADDRESS_MODE_7BIT) + { + /* send slave address */ + i2c_7bit_address_send(handle->i2c_x, address, I2C_DIRECTION_TRANSMIT); + } + else + { + /* send slave 10-bit address header */ + i2c_data_send(handle->i2c_x, (uint8_t)((address & 0x0300) >> 7) | 0xF0); + + /* wait for the addrh flag to be set */ + if(i2c_wait_flag(handle, I2C_ADDRHF_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK) + { + handle->comm.error_code = I2C_ERR_ADDR10; + + return I2C_ERR_ADDR10; + } + + /* send slave address */ + i2c_data_send(handle->i2c_x, (uint8_t)(address & 0x00FF)); + } + + /* wait for the addr7 flag to be set */ + if(i2c_wait_flag(handle, I2C_ADDR7F_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK) + { + handle->comm.error_code = I2C_ERR_ADDR; + + return I2C_ERR_ADDR; + } + + return I2C_OK; +} + +i2c_status_type i2c_master_read_addr(struct at32_i2c_handle *handle, uint16_t address, uint32_t timeout) +{ + /* enable ack */ + i2c_ack_enable(handle->i2c_x, TRUE); + + /* generate start condtion */ + i2c_start_generate(handle->i2c_x); + + /* wait for the start flag to be set */ + if(i2c_wait_flag(handle, I2C_STARTF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK) + { + handle->comm.error_code = I2C_ERR_START; + + return I2C_ERR_START; + } + + if(handle->i2c_x->oaddr1_bit.addr1mode == I2C_ADDRESS_MODE_7BIT) + { + /* send slave address */ + i2c_7bit_address_send(handle->i2c_x, address, I2C_DIRECTION_RECEIVE); + } + else + { + /* send slave 10-bit address header */ + i2c_data_send(handle->i2c_x, (uint8_t)((address & 0x0300) >> 7) | 0xF0); + + /* wait for the addrh flag to be set */ + if(i2c_wait_flag(handle, I2C_ADDRHF_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK) + { + handle->comm.error_code = I2C_ERR_ADDR10; + + return I2C_ERR_ADDR10; + } + + /* send slave address */ + i2c_data_send(handle->i2c_x, (uint8_t)(address & 0x00FF)); + + /* wait for the addr7 flag to be set */ + if(i2c_wait_flag(handle, I2C_ADDR7F_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK) + { + handle->comm.error_code = I2C_ERR_ADDR; + + return I2C_ERR_ADDR; + } + + /* clear addr flag */ + i2c_flag_clear(handle->i2c_x, I2C_ADDR7F_FLAG); + + /* generate restart condtion */ + i2c_start_generate(handle->i2c_x); + + /* wait for the start flag to be set */ + if(i2c_wait_flag(handle, I2C_STARTF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK) + { + handle->comm.error_code = I2C_ERR_START; + + return I2C_ERR_START; + } + + /* send slave 10-bit address header */ + i2c_data_send(handle->i2c_x, (uint8_t)((address & 0x0300) >> 7) | 0xF1); + } + + /* wait for the addr7 flag to be set */ + if(i2c_wait_flag(handle, I2C_ADDR7F_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK) + { + handle->comm.error_code = I2C_ERR_ADDR; + + return I2C_ERR_ADDR; + } + + return I2C_OK; +} + +i2c_status_type i2c_master_transmit_int(struct at32_i2c_handle *handle, uint16_t address, uint8_t *pdata, uint16_t size, uint32_t timeout) +{ + /* initialization parameters */ + handle->comm.mode = I2C_INT_MA_TX; + handle->comm.status = I2C_START; + + handle->comm.pbuff = pdata; + handle->comm.pcount = size; + + handle->comm.timeout = timeout; + handle->comm.error_code = I2C_OK; + + /* wait for the busy flag to be reset */ + if(i2c_wait_flag(handle, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK) + { + return I2C_ERR_STEP_1; + } + + /* ack acts on the current byte */ + i2c_master_receive_ack_set(handle->i2c_x, I2C_MASTER_ACK_CURRENT); + + /* send slave address */ + if(i2c_master_write_addr(handle, address, timeout) != I2C_OK) + { + /* generate stop condtion */ + i2c_stop_generate(handle->i2c_x); + + return I2C_ERR_STEP_2; + } + + /* clear addr flag */ + i2c_flag_clear(handle->i2c_x, I2C_ADDR7F_FLAG); + + /* enable interrupt */ + i2c_interrupt_enable(handle->i2c_x, I2C_EVT_INT | I2C_DATA_INT | I2C_ERR_INT, TRUE); + + return I2C_OK; +} + +i2c_status_type i2c_master_receive_int(struct at32_i2c_handle *handle, uint16_t address, uint8_t *pdata, uint16_t size, uint32_t timeout) +{ + /* initialization parameters */ + handle->comm.mode = I2C_INT_MA_RX; + handle->comm.status = I2C_START; + + handle->comm.pbuff = pdata; + handle->comm.pcount = size; + + handle->comm.timeout = timeout; + handle->comm.error_code = I2C_OK; + + /* wait for the busy flag to be reset */ + if(i2c_wait_flag(handle, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK) + { + return I2C_ERR_STEP_1; + } + + /* ack acts on the current byte */ + i2c_master_receive_ack_set(handle->i2c_x, I2C_MASTER_ACK_CURRENT); + + /* enable ack */ + i2c_ack_enable(handle->i2c_x, TRUE); + + /* send slave address */ + if(i2c_master_read_addr(handle, address, timeout) != I2C_OK) + { + /* generate stop condtion */ + i2c_stop_generate(handle->i2c_x); + + return I2C_ERR_STEP_2; + } + + if(handle->comm.pcount == 1) + { + /* disable ack */ + i2c_ack_enable(handle->i2c_x, FALSE); + + /* clear addr flag */ + i2c_flag_clear(handle->i2c_x, I2C_ADDR7F_FLAG); + + /* generate stop condtion */ + i2c_stop_generate(handle->i2c_x); + } + else if(handle->comm.pcount == 2) + { + /* ack acts on the next byte */ + i2c_master_receive_ack_set(handle->i2c_x, I2C_MASTER_ACK_NEXT); + + /* clear addr flag */ + i2c_flag_clear(handle->i2c_x, I2C_ADDR7F_FLAG); + + /* disable ack */ + i2c_ack_enable(handle->i2c_x, FALSE); + } + else + { + /* enable ack */ + i2c_ack_enable(handle->i2c_x, TRUE); + + /* clear addr flag */ + i2c_flag_clear(handle->i2c_x, I2C_ADDR7F_FLAG); + } + + /* enable interrupt */ + i2c_interrupt_enable(handle->i2c_x, I2C_EVT_INT | I2C_DATA_INT | I2C_ERR_INT, TRUE); + + return I2C_OK; +} + +i2c_status_type i2c_master_transmit_dma(struct at32_i2c_handle *handle, uint16_t address, uint8_t *pdata, uint16_t size, uint32_t timeout) +{ + /* initialization parameters */ + handle->comm.mode = I2C_DMA_MA_TX; + handle->comm.status = I2C_START; + + handle->comm.pbuff = pdata; + handle->comm.pcount = size; + + handle->comm.timeout = timeout; + handle->comm.error_code = I2C_OK; + + /* wait for the busy flag to be reset */ + if(i2c_wait_flag(handle, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK) + { + return I2C_ERR_STEP_1; + } + + /* ack acts on the current byte */ + i2c_master_receive_ack_set(handle->i2c_x, I2C_MASTER_ACK_CURRENT); + + /* disable dma request */ + i2c_dma_enable(handle->i2c_x, FALSE); + + /* configure the dma channel */ + i2c_dma_config(handle, pdata, size); + + /* send slave address */ + if(i2c_master_write_addr(handle, address, timeout) != I2C_OK) + { + /* generate stop condtion */ + i2c_stop_generate(handle->i2c_x); + + return I2C_ERR_STEP_2; + } + + /* clear addr flag */ + i2c_flag_clear(handle->i2c_x, I2C_ADDR7F_FLAG); + + /* enable dma request */ + i2c_dma_enable(handle->i2c_x, TRUE); + + return I2C_OK; +} + +i2c_status_type i2c_master_receive_dma(struct at32_i2c_handle *handle, uint16_t address, uint8_t *pdata, uint16_t size, uint32_t timeout) +{ + /* initialization parameters */ + handle->comm.mode = I2C_DMA_MA_RX; + handle->comm.status = I2C_START; + + handle->comm.pbuff = pdata; + handle->comm.pcount = size; + + handle->comm.timeout = timeout; + handle->comm.error_code = I2C_OK; + + /* wait for the busy flag to be reset */ + if(i2c_wait_flag(handle, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK) + { + return I2C_ERR_STEP_1; + } + + /* ack acts on the current byte */ + i2c_master_receive_ack_set(handle->i2c_x, I2C_MASTER_ACK_CURRENT); + + /* enable ack */ + i2c_ack_enable(handle->i2c_x, TRUE); + + /* disable dma request */ + i2c_dma_enable(handle->i2c_x, FALSE); + + /* configure the dma channel */ + i2c_dma_config(handle, pdata, size); + + /* send slave address */ + if(i2c_master_read_addr(handle, address, timeout) != I2C_OK) + { + /* generate stop condtion */ + i2c_stop_generate(handle->i2c_x); + + return I2C_ERR_STEP_2; + } + + if(size == 1) + { + /* clear addr flag */ + i2c_flag_clear(handle->i2c_x, I2C_ADDR7F_FLAG); + + /* disable ack */ + i2c_ack_enable(handle->i2c_x, FALSE); + + /* generate stop condtion */ + i2c_stop_generate(handle->i2c_x); + + /* enable dma request */ + i2c_dma_enable(handle->i2c_x, TRUE); + } + else + { + /* enable dma end transfer */ + i2c_dma_end_transfer_set(handle->i2c_x, TRUE); + + /* enable dma request */ + i2c_dma_enable(handle->i2c_x, TRUE); + + /* clear addr flag */ + i2c_flag_clear(handle->i2c_x, I2C_ADDR7F_FLAG); + } + + return I2C_OK; +} + + +void i2c_master_tx_isr_int(struct at32_i2c_handle *handle) +{ + /* step 1: transfer data */ + if(i2c_flag_get(handle->i2c_x, I2C_TDBE_FLAG) != RESET) + { + if(handle->comm.pcount == 0) + { + rt_completion_done(&handle->completion); + + /* transfer complete */ + handle->comm.status = I2C_END; + + /* disable interrupt */ + i2c_interrupt_enable(handle->i2c_x, I2C_EVT_INT | I2C_DATA_INT | I2C_ERR_INT, FALSE); + + /* generate stop condtion */ + i2c_stop_generate(handle->i2c_x); + } + else + { + /* write data */ + i2c_data_send(handle->i2c_x, *handle->comm.pbuff++); + handle->comm.pcount--; + } + } +} + +void i2c_master_rx_isr_int(struct at32_i2c_handle *handle) +{ + if(i2c_flag_get(handle->i2c_x, I2C_TDC_FLAG) != RESET) + { + if(handle->comm.pcount == 3) + { + /* disable ack */ + i2c_ack_enable(handle->i2c_x, FALSE); + + /* read data */ + (*handle->comm.pbuff++) = i2c_data_receive(handle->i2c_x); + handle->comm.pcount--; + } + else if(handle->comm.pcount == 2) + { + /* generate stop condtion */ + i2c_stop_generate(handle->i2c_x); + + /* read data */ + (*handle->comm.pbuff++) = i2c_data_receive(handle->i2c_x); + handle->comm.pcount--; + + /* read data */ + (*handle->comm.pbuff++) = i2c_data_receive(handle->i2c_x); + handle->comm.pcount--; + + /* transfer complete */ + rt_completion_done(&handle->completion); + handle->comm.status = I2C_END; + + /* disable interrupt */ + i2c_interrupt_enable(handle->i2c_x, I2C_EVT_INT | I2C_DATA_INT | I2C_ERR_INT, FALSE); + } + else + { + /* read data */ + (*handle->comm.pbuff++) = i2c_data_receive(handle->i2c_x); + handle->comm.pcount--; + } + } + else if(i2c_flag_get(handle->i2c_x, I2C_RDBF_FLAG) != RESET) + { + if(handle->comm.pcount > 3) + { + /* read data */ + (*handle->comm.pbuff++) = i2c_data_receive(handle->i2c_x); + handle->comm.pcount--; + } + else if((handle->comm.pcount == 3) || (handle->comm.pcount == 2)) + { + /* disable rdbf interrupt */ + i2c_interrupt_enable(handle->i2c_x, I2C_DATA_INT, FALSE); + } + else + { + /* read data */ + (*handle->comm.pbuff++) = i2c_data_receive(handle->i2c_x); + handle->comm.pcount--; + + /* transfer complete */ + rt_completion_done(&handle->completion); + handle->comm.status = I2C_END; + + /* disable interrupt */ + i2c_interrupt_enable(handle->i2c_x, I2C_EVT_INT | I2C_DATA_INT | I2C_ERR_INT, FALSE); + } + } +} + +void i2c_master_tx_isr_dma(struct at32_i2c_handle *handle) +{ + /* tdc interrupt */ + if(i2c_flag_get(handle->i2c_x, I2C_TDC_FLAG) != RESET) + { + rt_completion_done(&handle->completion); + + /* generate stop condtion */ + i2c_stop_generate(handle->i2c_x); + + /* disable evt interrupt */ + i2c_interrupt_enable(handle->i2c_x, I2C_EVT_INT, FALSE); + + /* transfer complete */ + handle->comm.status = I2C_END; + } +} + +void i2c_evt_isr(struct at32_i2c_handle *handle) +{ + switch(handle->comm.mode) + { + case I2C_INT_MA_TX: + i2c_master_tx_isr_int(handle); + break; + case I2C_INT_MA_RX: + i2c_master_rx_isr_int(handle); + break; + case I2C_DMA_MA_TX: + i2c_master_tx_isr_dma(handle); + break; + default: + break; + } +} +#endif + +#if defined (SOC_SERIES_AT32F402) || defined (SOC_SERIES_AT32F405) || \ + defined (SOC_SERIES_AT32F423) || defined (SOC_SERIES_AT32F425) || \ + defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \ + defined (SOC_SERIES_AT32A423) +void i2c_start_transfer(struct at32_i2c_handle *handle, uint16_t address, i2c_start_mode_type start) +{ + if (handle->comm.pcount > MAX_TRANSFER_CNT) + { + handle->comm.psize = MAX_TRANSFER_CNT; + + i2c_transmit_set(handle->i2c_x, address, handle->comm.psize, I2C_RELOAD_MODE, start); + } + else + { + handle->comm.psize = handle->comm.pcount; + + i2c_transmit_set(handle->i2c_x, address, handle->comm.psize, I2C_AUTO_STOP_MODE, start); + } +} + +void i2c_start_transfer_dma(struct at32_i2c_handle *handle, uint16_t address, i2c_start_mode_type start) +{ + if (handle->comm.pcount > MAX_TRANSFER_CNT) + { + handle->comm.psize = MAX_TRANSFER_CNT; + + /* config dma */ + i2c_dma_config(handle, handle->comm.pbuff, handle->comm.psize); + + i2c_transmit_set(handle->i2c_x, address, handle->comm.psize, I2C_RELOAD_MODE, start); + } + else + { + handle->comm.psize = handle->comm.pcount; + + /* config dma */ + i2c_dma_config(handle, handle->comm.pbuff, handle->comm.psize); + + i2c_transmit_set(handle->i2c_x, address, handle->comm.psize, I2C_AUTO_STOP_MODE, start); + } +} + +i2c_status_type i2c_master_transmit_int(struct at32_i2c_handle *handle, uint16_t address, uint8_t *pdata, uint16_t size, uint32_t timeout) +{ + /* initialization parameters */ + handle->comm.mode = I2C_INT_MA_TX; + handle->comm.status = I2C_START; + + handle->comm.pbuff = pdata; + handle->comm.pcount = size; + + handle->comm.error_code = I2C_OK; + + /* wait for the busy flag to be reset */ + if (i2c_wait_flag(handle, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK) + { + return I2C_ERR_STEP_1; + } + + /* start transfer */ + i2c_start_transfer(handle, address, I2C_GEN_START_WRITE); + + /* enable interrupt */ + i2c_interrupt_enable(handle->i2c_x, I2C_ERR_INT | I2C_TDC_INT | I2C_STOP_INT | I2C_ACKFIAL_INT | I2C_TD_INT, TRUE); + + return I2C_OK; +} + +i2c_status_type i2c_master_receive_int(struct at32_i2c_handle *handle, uint16_t address, uint8_t *pdata, uint16_t size, uint32_t timeout) +{ + /* initialization parameters */ + handle->comm.mode = I2C_INT_MA_RX; + handle->comm.status = I2C_START; + + handle->comm.pbuff = pdata; + handle->comm.pcount = size; + + handle->comm.error_code = I2C_OK; + + /* wait for the busy flag to be reset */ + if (i2c_wait_flag(handle, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK) + { + return I2C_ERR_STEP_1; + } + + /* start transfer */ + i2c_start_transfer(handle, address, I2C_GEN_START_READ); + + /* enable interrupt */ + i2c_interrupt_enable(handle->i2c_x, I2C_ERR_INT | I2C_TDC_INT | I2C_STOP_INT | I2C_ACKFIAL_INT | I2C_RD_INT, TRUE); + + return I2C_OK; +} + +i2c_status_type i2c_master_transmit_dma(struct at32_i2c_handle *handle, uint16_t address, uint8_t *pdata, uint16_t size, uint32_t timeout) +{ + /* initialization parameters */ + handle->comm.mode = I2C_DMA_MA_TX; + handle->comm.status = I2C_START; + + handle->comm.pbuff = pdata; + handle->comm.pcount = size; + + handle->comm.error_code = I2C_OK; + + /* wait for the busy flag to be reset */ + if(i2c_wait_flag(handle, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK) + { + return I2C_ERR_STEP_1; + } + + /* disable dma request */ + i2c_dma_enable(handle->i2c_x, I2C_DMA_REQUEST_TX, FALSE); + + /* start transfer */ + i2c_start_transfer_dma(handle, address, I2C_GEN_START_WRITE); + + /* enable i2c interrupt */ + i2c_interrupt_enable(handle->i2c_x, I2C_ERR_INT | I2C_ACKFIAL_INT, TRUE); + + /* enable dma request */ + i2c_dma_enable(handle->i2c_x, I2C_DMA_REQUEST_TX, TRUE); + + return I2C_OK; +} + +i2c_status_type i2c_master_receive_dma(struct at32_i2c_handle *handle, uint16_t address, uint8_t *pdata, uint16_t size, uint32_t timeout) +{ + /* initialization parameters */ + handle->comm.mode = I2C_DMA_MA_RX; + handle->comm.status = I2C_START; + + handle->comm.pbuff = pdata; + handle->comm.pcount = size; + + handle->comm.error_code = I2C_OK; + + /* wait for the busy flag to be reset */ + if(i2c_wait_flag(handle, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK) + { + return I2C_ERR_STEP_1; + } + + /* disable dma request */ + i2c_dma_enable(handle->i2c_x, I2C_DMA_REQUEST_RX, FALSE); + + /* start transfer */ + i2c_start_transfer_dma(handle, address, I2C_GEN_START_READ); + + /* enable i2c interrupt */ + i2c_interrupt_enable(handle->i2c_x, I2C_ERR_INT | I2C_ACKFIAL_INT, TRUE); + + /* enable dma request */ + i2c_dma_enable(handle->i2c_x, I2C_DMA_REQUEST_RX, TRUE); + + return I2C_OK; +} + +void i2c_master_isr_int(struct at32_i2c_handle *handle) +{ + if (i2c_flag_get(handle->i2c_x, I2C_ACKFAIL_FLAG) != RESET) + { + /* clear ackfail flag */ + i2c_flag_clear(handle->i2c_x, I2C_ACKFAIL_FLAG); + + /* refresh tx register */ + i2c_refresh_txdt_register(handle->i2c_x); + + if(handle->comm.pcount != 0) + { + handle->comm.error_code = I2C_ERR_ACKFAIL; + } + } + else if (i2c_flag_get(handle->i2c_x, I2C_TDIS_FLAG) != RESET) + { + /* send data */ + i2c_data_send(handle->i2c_x, *handle->comm.pbuff++); + handle->comm.pcount--; + handle->comm.psize--; + } + else if (i2c_flag_get(handle->i2c_x, I2C_TCRLD_FLAG) != RESET) + { + if ((handle->comm.psize == 0) && (handle->comm.pcount != 0)) + { + /* continue transfer */ + i2c_start_transfer(handle, i2c_transfer_addr_get(handle->i2c_x), I2C_WITHOUT_START); + } + } + else if (i2c_flag_get(handle->i2c_x, I2C_RDBF_FLAG) != RESET) + { + /* read data */ + (*handle->comm.pbuff++) = i2c_data_receive(handle->i2c_x); + handle->comm.pcount--; + handle->comm.psize--; + } + else if (i2c_flag_get(handle->i2c_x, I2C_TDC_FLAG) != RESET) + { + if (handle->comm.pcount == 0) + { + if (handle->i2c_x->ctrl2_bit.astopen == 0) + { + /* generate stop condtion */ + i2c_stop_generate(handle->i2c_x); + } + } + } + else if (i2c_flag_get(handle->i2c_x, I2C_STOPF_FLAG) != RESET) + { + /* clear stop flag */ + i2c_flag_clear(handle->i2c_x, I2C_STOPF_FLAG); + + /* reset ctrl2 register */ + i2c_reset_ctrl2_register(handle->i2c_x); + + if (i2c_flag_get(handle->i2c_x, I2C_ACKFAIL_FLAG) != RESET) + { + /* clear ackfail flag */ + i2c_flag_clear(handle->i2c_x, I2C_ACKFAIL_FLAG); + } + + /* refresh tx dt register */ + i2c_refresh_txdt_register(handle->i2c_x); + + /* disable interrupts */ + i2c_interrupt_enable(handle->i2c_x, I2C_ERR_INT | I2C_TDC_INT | I2C_STOP_INT | I2C_ACKFIAL_INT | I2C_TD_INT | I2C_RD_INT, FALSE); + + /* transfer complete */ + handle->comm.status = I2C_END; + rt_completion_done(&handle->completion); + } +} + +void i2c_master_isr_dma(struct at32_i2c_handle *handle) +{ + if (i2c_flag_get(handle->i2c_x, I2C_ACKFAIL_FLAG) != RESET) + { + /* clear ackfail flag */ + i2c_flag_clear(handle->i2c_x, I2C_ACKFAIL_FLAG); + + /* enable stop interrupt to wait for stop generate stop */ + i2c_interrupt_enable(handle->i2c_x, I2C_STOP_INT, TRUE); + + /* refresh tx dt register */ + i2c_refresh_txdt_register(handle->i2c_x); + + if(handle->comm.pcount != 0) + { + handle->comm.error_code = I2C_ERR_ACKFAIL; + } + } + else if (i2c_flag_get(handle->i2c_x, I2C_TCRLD_FLAG) != RESET) + { + /* disable tdc interrupt */ + i2c_interrupt_enable(handle->i2c_x, I2C_TDC_INT, FALSE); + + if (handle->comm.pcount != 0) + { + /* continue transfer */ + i2c_start_transfer(handle, i2c_transfer_addr_get(handle->i2c_x), I2C_WITHOUT_START); + + /* enable dma request */ + if(handle->comm.mode == I2C_DMA_MA_TX) + i2c_dma_enable(handle->i2c_x, I2C_DMA_REQUEST_TX, TRUE); + else if(handle->comm.mode == I2C_DMA_MA_RX) + i2c_dma_enable(handle->i2c_x, I2C_DMA_REQUEST_RX, TRUE); + } + } + else if (i2c_flag_get(handle->i2c_x, I2C_STOPF_FLAG) != RESET) + { + /* clear stop flag */ + i2c_flag_clear(handle->i2c_x, I2C_STOPF_FLAG); + + /* reset ctrl2 register */ + i2c_reset_ctrl2_register(handle->i2c_x); + + if (i2c_flag_get(handle->i2c_x, I2C_ACKFAIL_FLAG) != RESET) + { + /* clear ackfail flag */ + i2c_flag_clear(handle->i2c_x, I2C_ACKFAIL_FLAG); + } + + /* refresh tx dt register */ + i2c_refresh_txdt_register(handle->i2c_x); + + /* disable interrupts */ + i2c_interrupt_enable(handle->i2c_x, I2C_ERR_INT | I2C_TDC_INT | I2C_STOP_INT | I2C_ACKFIAL_INT | I2C_TD_INT | I2C_RD_INT, FALSE); + + /* transfer complete */ + handle->comm.status = I2C_END; + rt_completion_done(&handle->completion); + } +} + +void i2c_evt_isr(struct at32_i2c_handle *handle) +{ + switch(handle->comm.mode) + { + case I2C_INT_MA_TX: + case I2C_INT_MA_RX: + i2c_master_isr_int(handle); + break; + case I2C_DMA_MA_TX: + case I2C_DMA_MA_RX: + i2c_master_isr_dma(handle); + break; + default: + break; + } +} +#endif + +static rt_ssize_t master_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], rt_uint32_t num) +{ + /* for dma may more stability */ +#define DMA_TRANS_MIN_LEN 2 /* only buffer length >= DMA_TRANS_MIN_LEN will use DMA mode */ +#define TRANS_TIMEOUT_PERSEC 8 /* per ms will trans nums bytes */ + + rt_int32_t i, ret; + struct rt_i2c_msg *msg = msgs; + struct rt_completion *completion; + rt_uint32_t timeout; + if (num == 0) + { + return 0; + } + RT_ASSERT((msgs != RT_NULL) && (bus != RT_NULL)); + struct at32_i2c *instance = rt_container_of(bus, struct at32_i2c, i2c_bus); + completion = &instance->handle->completion; + + LOG_D("xfer start %d mags", num); + for (i = 0; i < (num - 1); i++) + { + msg = &msgs[i]; + LOG_D("xfer msgs[%d] addr=0x%2x buf=0x%x len= 0x%x flags= 0x%x", i, msg->addr, msg->buf, msg->len, msg->flags); + timeout = msg->len / TRANS_TIMEOUT_PERSEC + 2; + + if (msg->flags & RT_I2C_RD) + { + if ((instance->handle->i2c_dma_flag & RT_DEVICE_FLAG_DMA_RX) && (msg->len >= DMA_TRANS_MIN_LEN)) + { + ret = i2c_master_receive_dma(instance->handle, (msg->addr << 1) , msg->buf, msg->len, 0xFFFFFFFF); + } + else + { + ret = i2c_master_receive_int(instance->handle, (msg->addr << 1) , msg->buf, msg->len, 0xFFFFFFFF); + } + if (ret != RT_EOK) + { + LOG_E("[%s:%d]i2c read error(%d)!\n", __func__, __LINE__, ret); + goto out; + } + if (rt_completion_wait(completion, timeout) != RT_EOK) + { + LOG_D("receive time out"); + goto out; + } + } + else + { + if ((instance->handle->i2c_dma_flag & RT_DEVICE_FLAG_DMA_TX) && (msg->len >= DMA_TRANS_MIN_LEN)) + { + ret = i2c_master_transmit_dma(instance->handle, (msg->addr << 1) , msg->buf, msg->len, 0xFFFFFFFF); + } + else + { + ret = i2c_master_transmit_int(instance->handle, (msg->addr << 1) , msg->buf, msg->len, 0xFFFFFFFF); + } + if (ret != RT_EOK) + { + LOG_D("[%s:%d]i2c write error(%d)!\n", __func__, __LINE__, ret); + goto out; + } + if (rt_completion_wait(completion, timeout) != RT_EOK) + { + LOG_D("transmit time out"); + goto out; + } + } + } + /* last msg */ + msg = &msgs[i]; + timeout = msg->len / TRANS_TIMEOUT_PERSEC + 2; + + LOG_D("xfer last msgs[%d] addr=0x%2x buf= 0x%x len= 0x%x flags = 0x%x", i, msg->addr, msg->buf, msg->len, msg->flags); + if (msg->flags & RT_I2C_RD) + { + if ((instance->handle->i2c_dma_flag & RT_DEVICE_FLAG_DMA_RX) && (msg->len >= DMA_TRANS_MIN_LEN)) + { + ret = i2c_master_receive_dma(instance->handle, (msg->addr << 1), msg->buf, msg->len, 0xFFFFFFFF); + } + else + { + ret = i2c_master_receive_int(instance->handle, (msg->addr << 1), msg->buf, msg->len, 0xFFFFFFFF); + } + if (ret != RT_EOK) + { + LOG_D("[%s:%d]i2c read error(%d)!\n", __func__, __LINE__, ret); + goto out; + } + if (rt_completion_wait(completion, timeout) != RT_EOK) + { + LOG_D("receive time out"); + goto out; + } + } + else + { + if ((instance->handle->i2c_dma_flag & RT_DEVICE_FLAG_DMA_TX) && (msg->len >= DMA_TRANS_MIN_LEN)) + { + ret = i2c_master_transmit_dma(instance->handle, (msg->addr << 1), msg->buf, msg->len, 0xFFFFFFFF); + } + else + { + ret = i2c_master_transmit_int(instance->handle, (msg->addr << 1), msg->buf, msg->len, 0xFFFFFFFF); + } + if (ret != RT_EOK) + { + LOG_D("[%s:%d]i2c write error(%d)!\n", __func__, __LINE__, ret); + goto out; + } + if (rt_completion_wait(completion, timeout) != RT_EOK) + { + LOG_D("transmit time out"); + goto out; + } + } + ret = num; + LOG_D("xfer end %d mags\r\n", num); + return ret; + +out: + if(instance->handle->comm.error_code == I2C_ERR_ACKFAIL) + { + LOG_D("i2c nack error now stoped"); + } + if(instance->handle->comm.error_code == I2C_ERR_INTERRUPT) + { + LOG_D("i2c bus error now stoped"); + ret = i - 1; + } + /* generate stop */ + i2c_stop_generate(instance->handle->i2c_x); + return ret; +} + +static void _dma_base_channel_check(struct at32_i2c *instance) +{ + dma_channel_type *rx_channel = instance->handle->dma_rx->dma_channel; + dma_channel_type *tx_channel = instance->handle->dma_tx->dma_channel; + + if(instance->handle->i2c_dma_flag & RT_DEVICE_FLAG_DMA_RX) + { + instance->handle->dma_rx->dma_done = RT_TRUE; + instance->handle->dma_rx->dma_x = (dma_type *)((rt_uint32_t)rx_channel & ~0xFF); + instance->handle->dma_rx->channel_index = ((((rt_uint32_t)rx_channel & 0xFF) - 8) / 0x14) + 1; + } + + if(instance->handle->i2c_dma_flag & RT_DEVICE_FLAG_DMA_TX) + { + instance->handle->dma_tx->dma_done = RT_TRUE; + instance->handle->dma_tx->dma_x = (dma_type *)((rt_uint32_t)tx_channel & ~0xFF); + instance->handle->dma_tx->channel_index = ((((rt_uint32_t)tx_channel & 0xFF) - 8) / 0x14) + 1; + } +} + +static void at32_i2c_dma_init(struct at32_i2c *instance) +{ + dma_init_type dma_init_struct; + + /* search dma base and channel index */ + _dma_base_channel_check(instance); + + /* config dma channel */ + dma_default_para_init(&dma_init_struct); + dma_init_struct.peripheral_inc_enable = FALSE; + dma_init_struct.memory_inc_enable = TRUE; + dma_init_struct.peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_BYTE; + dma_init_struct.memory_data_width = DMA_MEMORY_DATA_WIDTH_BYTE; + dma_init_struct.priority = DMA_PRIORITY_MEDIUM; + dma_init_struct.loop_mode_enable = FALSE; + + if (instance->handle->i2c_dma_flag & RT_DEVICE_FLAG_DMA_RX) + { + crm_periph_clock_enable(instance->handle->dma_rx->dma_clock, TRUE); + dma_init_struct.direction = DMA_DIR_PERIPHERAL_TO_MEMORY; + + dma_reset(instance->handle->dma_rx->dma_channel); + dma_init(instance->handle->dma_rx->dma_channel, &dma_init_struct); +#if defined (SOC_SERIES_AT32F425) + dma_flexible_config(instance->handle->dma_rx->dma_x, instance->handle->dma_rx->flex_channel, \ + (dma_flexible_request_type)instance->handle->dma_rx->request_id); +#endif +#if defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \ + defined (SOC_SERIES_AT32F423) || defined (SOC_SERIES_AT32F402) || \ + defined (SOC_SERIES_AT32F405) || defined (SOC_SERIES_AT32A423) + dmamux_enable(instance->handle->dma_rx->dma_x, TRUE); + dmamux_init(instance->handle->dma_rx->dmamux_channel, (dmamux_requst_id_sel_type)instance->handle->dma_rx->request_id); +#endif + /* dma irq should set in dma rx mode */ + nvic_irq_enable(instance->handle->dma_rx->dma_irqn, 0, 1); + } + + if (instance->handle->i2c_dma_flag & RT_DEVICE_FLAG_DMA_TX) + { + crm_periph_clock_enable(instance->handle->dma_tx->dma_clock, TRUE); + dma_init_struct.direction = DMA_DIR_MEMORY_TO_PERIPHERAL; + + dma_reset(instance->handle->dma_tx->dma_channel); + dma_init(instance->handle->dma_tx->dma_channel, &dma_init_struct); +#if defined (SOC_SERIES_AT32F425) + dma_flexible_config(instance->handle->dma_tx->dma_x, instance->handle->dma_tx->flex_channel, \ + (dma_flexible_request_type)instance->handle->dma_tx->request_id); +#endif +#if defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \ + defined (SOC_SERIES_AT32F423) || defined (SOC_SERIES_AT32F402) || \ + defined (SOC_SERIES_AT32F405) || defined (SOC_SERIES_AT32A423) + dmamux_enable(instance->handle->dma_tx->dma_x, TRUE); + dmamux_init(instance->handle->dma_tx->dmamux_channel, (dmamux_requst_id_sel_type)instance->handle->dma_tx->request_id); +#endif + /* dma irq should set in dma tx mode */ + nvic_irq_enable(instance->handle->dma_tx->dma_irqn, 0, 1); + } +} + +void i2c_err_isr(struct at32_i2c_handle *handle) +{ + /* buserr */ + if(i2c_flag_get(handle->i2c_x, I2C_BUSERR_FLAG) != RESET) + { + i2c_flag_clear(handle->i2c_x, I2C_BUSERR_FLAG); + + handle->comm.error_code = I2C_ERR_INTERRUPT; + } + + /* arlost */ + if(i2c_flag_get(handle->i2c_x, I2C_ARLOST_FLAG) != RESET) + { + i2c_flag_clear(handle->i2c_x, I2C_ARLOST_FLAG); + + handle->comm.error_code = I2C_ERR_INTERRUPT; + } + +#if defined (SOC_SERIES_AT32F403A) || defined (SOC_SERIES_AT32F407) || \ + defined (SOC_SERIES_AT32F413) || defined (SOC_SERIES_AT32F415) || \ + defined (SOC_SERIES_AT32F421) || defined (SOC_SERIES_AT32A403A) + /* ackfail */ + if(i2c_flag_get(handle->i2c_x, I2C_ACKFAIL_FLAG) != RESET) + { + i2c_flag_clear(handle->i2c_x, I2C_ACKFAIL_FLAG); + + switch(handle->comm.mode) + { + case I2C_DMA_SLA_TX: + /* disable ack */ + i2c_ack_enable(handle->i2c_x, FALSE); + + /* disable evt interrupt */ + i2c_interrupt_enable(handle->i2c_x, I2C_EVT_INT, FALSE); + + /* transfer complete */ + handle->comm.status = I2C_END; + break; + default: + handle->comm.error_code = I2C_ERR_INTERRUPT; + break; + } + } +#endif + + /* ouf */ + if(i2c_flag_get(handle->i2c_x, I2C_OUF_FLAG) != RESET) + { + i2c_flag_clear(handle->i2c_x, I2C_OUF_FLAG); + + handle->comm.error_code = I2C_ERR_INTERRUPT; + } + + /* pecerr */ + if(i2c_flag_get(handle->i2c_x, I2C_PECERR_FLAG) != RESET) + { + i2c_flag_clear(handle->i2c_x, I2C_PECERR_FLAG); + + handle->comm.error_code = I2C_ERR_INTERRUPT; + } + + /* tmout */ + if(i2c_flag_get(handle->i2c_x, I2C_TMOUT_FLAG) != RESET) + { + i2c_flag_clear(handle->i2c_x, I2C_TMOUT_FLAG); + + handle->comm.error_code = I2C_ERR_INTERRUPT; + } + + /* alertf */ + if(i2c_flag_get(handle->i2c_x, I2C_ALERTF_FLAG) != RESET) + { + i2c_flag_clear(handle->i2c_x, I2C_ALERTF_FLAG); + + handle->comm.error_code = I2C_ERR_INTERRUPT; + } + + /* disable all interrupts */ + i2c_interrupt_enable(handle->i2c_x, I2C_ERR_INT, FALSE); +} + +void dma_isr(struct at32_i2c_handle *handle) +{ + volatile rt_uint32_t reg_sts = 0, index = 0; + struct dma_config *dma = RT_NULL; + + if(handle->comm.mode == I2C_DMA_MA_TX) + { + dma = handle->dma_tx; + } + else if(handle->comm.mode == I2C_DMA_MA_RX) + { + dma = handle->dma_rx; + } + + reg_sts = dma->dma_x->sts; + index = dma->channel_index; + + /* transfer complete */ + if((reg_sts & (DMA_FDT_FLAG << (4 * (index - 1)))) != RESET) + { + /* clear dma flag */ + dma->dma_x->clr |= (rt_uint32_t)((DMA_FDT_FLAG << (4 * (index - 1))) | \ + (DMA_HDT_FLAG << (4 * (index - 1)))); + /* disable the transfer complete interrupt */ + dma_interrupt_enable(dma->dma_channel, DMA_FDT_INT, FALSE); + /* mark done */ + dma->dma_done = RT_TRUE; +#if defined (SOC_SERIES_AT32F403A) || defined (SOC_SERIES_AT32F407) || \ + defined (SOC_SERIES_AT32F413) || defined (SOC_SERIES_AT32F415) || \ + defined (SOC_SERIES_AT32F421) || defined (SOC_SERIES_AT32A403A) + /* disable dma request */ + i2c_dma_enable(handle->i2c_x, FALSE); +#endif +#if defined (SOC_SERIES_AT32F402) || defined (SOC_SERIES_AT32F405) || \ + defined (SOC_SERIES_AT32F423) || defined (SOC_SERIES_AT32F425) || \ + defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \ + defined (SOC_SERIES_AT32A423) + /* disable dma request */ + if(handle->comm.mode == I2C_DMA_MA_TX) + i2c_dma_enable(handle->i2c_x, I2C_DMA_REQUEST_TX, FALSE); + else if(handle->comm.mode == I2C_DMA_MA_RX) + i2c_dma_enable(handle->i2c_x, I2C_DMA_REQUEST_RX, FALSE); +#endif + /* disable dma channel */ + dma_channel_enable(dma->dma_channel, FALSE); + + switch(handle->comm.mode) + { +#if defined (SOC_SERIES_AT32F403A) || defined (SOC_SERIES_AT32F407) || \ + defined (SOC_SERIES_AT32F413) || defined (SOC_SERIES_AT32F415) || \ + defined (SOC_SERIES_AT32F421) || defined (SOC_SERIES_AT32A403A) + case I2C_DMA_MA_TX: + /* enable tdc interrupt, generate stop condition in tdc interrupt */ + handle->comm.pcount = 0; + i2c_interrupt_enable(handle->i2c_x, I2C_EVT_INT, TRUE); + break; + case I2C_DMA_MA_RX: + /* clear ackfail flag */ + i2c_flag_clear(handle->i2c_x, I2C_ACKFAIL_FLAG); + handle->comm.pcount = 0; + /* generate stop condtion */ + i2c_stop_generate(handle->i2c_x); + + /* transfer complete */ + rt_completion_done(&handle->completion); + handle->comm.status = I2C_END; + break; + default: + break; +#endif +#if defined (SOC_SERIES_AT32F402) || defined (SOC_SERIES_AT32F405) || \ + defined (SOC_SERIES_AT32F423) || defined (SOC_SERIES_AT32F425) || \ + defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \ + defined (SOC_SERIES_AT32A423) + case I2C_DMA_MA_TX: + case I2C_DMA_MA_RX: + { + /* update the number of transfers */ + handle->comm.pcount -= handle->comm.psize; + + /* transfer complete */ + if (handle->comm.pcount == 0) + { + /* enable stop interrupt */ + i2c_interrupt_enable(handle->i2c_x, I2C_STOP_INT, TRUE); + } + /* the transfer has not been completed */ + else + { + /* update the buffer pointer of transfers */ + handle->comm.pbuff += handle->comm.psize; + + /* set the number to be transferred */ + if (handle->comm.pcount > MAX_TRANSFER_CNT) + { + handle->comm.psize = MAX_TRANSFER_CNT; + } + else + { + handle->comm.psize = handle->comm.pcount; + } + + /* config dma channel, continue to transfer data */ + i2c_dma_config(handle, handle->comm.pbuff, handle->comm.psize); + + /* enable tdc interrupt */ + i2c_interrupt_enable(handle->i2c_x, I2C_TDC_INT, TRUE); + } + } + break; + default: + break; +#endif + } + } +} + +#ifdef BSP_USING_HARD_I2C1 +void I2C1_EVT_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + i2c_evt_isr(i2cs[I2C1_INDEX].handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +void I2C1_ERR_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + i2c_err_isr(i2cs[I2C1_INDEX].handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(BSP_I2C1_RX_USING_DMA) +void I2C1_RX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + dma_isr(i2cs[I2C1_INDEX].handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(BSP_I2C1_RX_USING_DMA) */ +#if defined(BSP_I2C1_TX_USING_DMA) +void I2C1_TX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + dma_isr(i2cs[I2C1_INDEX].handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(BSP_I2C1_TX_USING_DMA) */ +#endif +#ifdef BSP_USING_HARD_I2C2 +void I2C2_EVT_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + i2c_evt_isr(i2cs[I2C2_INDEX].handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +void I2C2_ERR_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + i2c_err_isr(i2cs[I2C2_INDEX].handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(BSP_I2C2_RX_USING_DMA) +void I2C2_RX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + dma_isr(i2cs[I2C2_INDEX].handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(BSP_I2C2_RX_USING_DMA) */ +#if defined(BSP_I2C2_TX_USING_DMA) +void I2C2_TX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + dma_isr(i2cs[I2C2_INDEX].handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(BSP_I2C2_TX_USING_DMA) */ +#endif +#ifdef BSP_USING_HARD_I2C3 +void I2C3_EVT_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + i2c_evt_isr(i2cs[I2C3_INDEX].handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +void I2C3_ERR_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + i2c_err_isr(i2cs[I2C3_INDEX].handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(BSP_I2C3_RX_USING_DMA) +void I2C3_RX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + dma_isr(i2cs[I2C3_INDEX].handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(BSP_I2C3_RX_USING_DMA) */ +#if defined(BSP_I2C3_TX_USING_DMA) +void I2C3_TX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + dma_isr(i2cs[I2C3_INDEX].handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(BSP_I2C3_TX_USING_DMA) */ +#endif + +#if defined (SOC_SERIES_AT32F421) || defined (SOC_SERIES_AT32F425) +void I2C1_TX_RX_DMA_IRQHandler(void) +{ +#if defined(BSP_USING_HARD_I2C1) && defined(BSP_I2C1_TX_USING_DMA) + I2C1_TX_DMA_IRQHandler(); +#endif + +#if defined(BSP_USING_HARD_I2C1) && defined(BSP_I2C1_RX_USING_DMA) + I2C1_RX_DMA_IRQHandler(); +#endif +} + +void I2C2_TX_RX_DMA_IRQHandler(void) +{ +#if defined(BSP_USING_HARD_I2C2) && defined(BSP_I2C2_TX_USING_DMA) + I2C2_TX_DMA_IRQHandler(); +#endif + +#if defined(BSP_USING_HARD_I2C2) && defined(BSP_I2C2_RX_USING_DMA) + I2C2_RX_DMA_IRQHandler(); +#endif +} +#endif + +static void at32_i2c_get_dma_config(void) +{ +#ifdef BSP_USING_HARD_I2C1 + i2c_handle[I2C1_INDEX].i2c_dma_flag = 0; +#ifdef BSP_I2C1_RX_USING_DMA + i2c_handle[I2C1_INDEX].i2c_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config i2c1_dma_rx = I2C1_RX_DMA_CONFIG; + i2c_handle[I2C1_INDEX].dma_rx = &i2c1_dma_rx; +#endif +#ifdef BSP_I2C1_TX_USING_DMA + i2c_handle[I2C1_INDEX].i2c_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config i2c1_dma_tx = I2C1_TX_DMA_CONFIG; + i2c_handle[I2C1_INDEX].dma_tx = &i2c1_dma_tx; +#endif +#endif + +#ifdef BSP_USING_HARD_I2C2 + i2c_handle[I2C2_INDEX].i2c_dma_flag = 0; +#ifdef BSP_I2C2_RX_USING_DMA + i2c_handle[I2C2_INDEX].i2c_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config i2c2_dma_rx = I2C2_RX_DMA_CONFIG; + i2c_handle[I2C2_INDEX].dma_rx = &i2c2_dma_rx; +#endif +#ifdef BSP_I2C2_TX_USING_DMA + i2c_handle[I2C2_INDEX].i2c_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config i2c2_dma_tx = I2C2_TX_DMA_CONFIG; + i2c_handle[I2C2_INDEX].dma_tx = &i2c2_dma_tx; +#endif +#endif + +#ifdef BSP_USING_HARD_I2C3 + i2c_handle[I2C3_INDEX].i2c_dma_flag = 0; +#ifdef BSP_I2C3_RX_USING_DMA + i2c_handle[I2C3_INDEX].i2c_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config i2c3_dma_rx = I2C3_RX_DMA_CONFIG; + i2c_handle[I2C3_INDEX].dma_rx = &i2c3_dma_rx; +#endif +#ifdef BSP_I2C3_TX_USING_DMA + i2c_handle[I2C3_INDEX].i2c_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config i2c3_dma_tx = I2C3_TX_DMA_CONFIG; + i2c_handle[I2C3_INDEX].dma_tx = &i2c3_dma_tx; +#endif +#endif +} + +int rt_hw_hwi2c_init(void) +{ + int i; + rt_err_t result; + rt_size_t obj_num = sizeof(i2c_handle) / sizeof(i2c_handle[0]); + + at32_i2c_get_dma_config(); + + for (i = 0; i < obj_num; i++) + { + i2cs[i].handle = &i2c_handle[i]; + i2cs[i].i2c_bus.ops = &at32_i2c_ops; + + if(i2cs[i].handle->i2c_dma_flag & (RT_DEVICE_FLAG_DMA_RX | RT_DEVICE_FLAG_DMA_TX)) + { + at32_i2c_dma_init(&i2cs[i]); + } + rt_completion_init(&i2cs[i].handle->completion); + at32_i2c_configure(&(i2cs[i].i2c_bus)); + result = rt_i2c_bus_device_register(&(i2cs[i].i2c_bus), i2cs[i].handle->i2c_name); + } + + return result; +} + +INIT_BOARD_EXPORT(rt_hw_hwi2c_init); + +#endif diff --git a/bsp/at32/libraries/rt_drivers/drv_hard_i2c.h b/bsp/at32/libraries/rt_drivers/drv_hard_i2c.h new file mode 100644 index 0000000000..bc34abf1c9 --- /dev/null +++ b/bsp/at32/libraries/rt_drivers/drv_hard_i2c.h @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-07-31 shelton first version + */ + +#ifndef __DRV_HARD_I2C_H__ +#define __DRV_HARD_I2C_H__ + +#include +#include +#include "drv_common.h" +#include "drv_dma.h" + +#define I2C_START 0 +#define I2C_END 1 + +#define I2C_EVENT_CHECK_NONE ((uint32_t)0x00000000) +#define I2C_EVENT_CHECK_ACKFAIL ((uint32_t)0x00000001) +#define I2C_EVENT_CHECK_STOP ((uint32_t)0x00000002) + +typedef enum +{ + I2C_INT_MA_TX = 0, + I2C_INT_MA_RX, + I2C_INT_SLA_TX, + I2C_INT_SLA_RX, + I2C_DMA_MA_TX, + I2C_DMA_MA_RX, + I2C_DMA_SLA_TX, + I2C_DMA_SLA_RX, +} i2c_mode_type; + +typedef enum +{ + I2C_OK = 0, + I2C_ERR_STEP_1, + I2C_ERR_STEP_2, + I2C_ERR_STEP_3, + I2C_ERR_STEP_4, + I2C_ERR_STEP_5, + I2C_ERR_STEP_6, + I2C_ERR_STEP_7, + I2C_ERR_STEP_8, + I2C_ERR_STEP_9, + I2C_ERR_STEP_10, + I2C_ERR_STEP_11, + I2C_ERR_STEP_12, + I2C_ERR_START, + I2C_ERR_ADDR10, + I2C_ERR_TCRLD, + I2C_ERR_TDC, + I2C_ERR_ADDR, + I2C_ERR_STOP, + I2C_ERR_ACKFAIL, + I2C_ERR_TIMEOUT, + I2C_ERR_INTERRUPT, +} i2c_status_type; + +struct i2c_comm_type +{ + rt_uint8_t *pbuff; + rt_uint16_t psize; + rt_uint16_t pcount; + i2c_mode_type mode; + rt_uint32_t timeout; + rt_uint32_t status; + i2c_status_type error_code; +}; + +struct at32_i2c_handle +{ + i2c_type *i2c_x; + const char *i2c_name; + rt_uint32_t timing; + IRQn_Type ev_irqn; + IRQn_Type er_irqn; + struct dma_config *dma_rx; + struct dma_config *dma_tx; + struct i2c_comm_type comm; + rt_uint16_t i2c_dma_flag; + struct rt_completion completion; +}; + +struct at32_i2c +{ + struct at32_i2c_handle *handle; + struct rt_i2c_bus_device i2c_bus; +}; + +#endif From a1b01ee86582811cfec569376dd5815d9b43eda9 Mon Sep 17 00:00:00 2001 From: Z8MAN8 <1468559561@qq.com> Date: Thu, 25 Jul 2024 15:14:16 +0800 Subject: [PATCH 48/48] bsp: cvitek: fix cv18xx_aarch64 mnt init blocking The aarch64 core of duo on the master cannot enter the console interface. It can only print the RT flag and hold it. Analysis: The latest commit that can work is ae6a328 ("Add psoc62, 61 config"). This phenomenon will occur after adding 754c59a ("[Feature] DFS mount auto by kernel parameters"). The specific reason is that when aarch bsp enables the device tree, the current u-boot will pass in bootargs, which contains "root=/dev/mmcblk0p2 rootwait rw", which means that the kernel is required to wait until the rootfs in /dev/mmcblk0p2 loaded successfully. However, the current aarch64 bsp default does not implement sdmmc device mounting, causing the kernel file system mounting module (rootfs_mnt_init() of components/drivers/core/mnt.c) to enter an infinite loop waiting. Solution: At present, we do not plan to modify the startup parameters of u-boot. The temporary solution adopted is to create a pseudo /dev/mmcblk0p2 device during the board initialization process, and then cancel the pseudo device after mnt is completed. This allows the kernel boot to be completed successfully. Signed-off-by: Shicheng Chu <1468559561@qq.com> Reviewed-by: Chen Wang --- bsp/cvitek/cv18xx_aarch64/board/board.c | 40 +++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/bsp/cvitek/cv18xx_aarch64/board/board.c b/bsp/cvitek/cv18xx_aarch64/board/board.c index de7778704f..d60396044d 100644 --- a/bsp/cvitek/cv18xx_aarch64/board/board.c +++ b/bsp/cvitek/cv18xx_aarch64/board/board.c @@ -81,6 +81,46 @@ void rt_hw_board_init(void) { rt_hw_common_setup(); } + +/* + * FIXME: This is a temporary workaround. + * When aarch bsp enables the device tree, the current u-boot will + * pass in bootargs, which contains "root=/dev/mmcblk0p2 rootwait rw", + * which means that the kernel is required to wait until the rootfs + * in /dev/mmcblk0p2 loaded successfully. However, the current aarch64 bsp + * default does not implement sdmmc device mounting, causing the kernel file + * system mounting module (rootfs_mnt_init() of components/drivers/core/mnt.c) + * to enter an infinite loop waiting. + * Solution: At present, we do not plan to modify the startup parameters + * of u-boot. The temporary solution adopted is to create a pseudo + * /dev/mmcblk0p2 device during the board initialization process, and + * then cancel the pseudo device after mnt is completed. This allows the + * kernel boot to be completed successfully. + */ +static struct rt_device *pseudo_mmcblk; + +static int pseudo_mmcblk_setup(void) +{ + pseudo_mmcblk = rt_calloc(1, sizeof(*pseudo_mmcblk)); + + RT_ASSERT(pseudo_mmcblk != RT_NULL); + + pseudo_mmcblk->type = RT_Device_Class_Graphic; + + return (int)rt_device_register(pseudo_mmcblk, "/dev/mmcblk0p2", RT_DEVICE_FLAG_DEACTIVATE); +} +INIT_BOARD_EXPORT(pseudo_mmcblk_setup); + +static int pseudo_mmcblk_remove(void) +{ + if (pseudo_mmcblk) + { + return (int)rt_device_unregister(pseudo_mmcblk); + } + + return 0; +} +INIT_FS_EXPORT(pseudo_mmcblk_remove); #endif /* RT_USING_OFW */ static rt_ubase_t pinmux_base = RT_NULL;