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Merge remote-tracking branch 'origin/master' into p2000

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This commit is contained in:
chinky 2024-07-27 17:14:51 +08:00
commit e3a82d08e7
567 changed files with 21761 additions and 7396 deletions
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8
.github/CODEOWNERS vendored
View File

@ -7,9 +7,8 @@
/.hooks @supperthomas
/.devcontainer @supperthomas
/bsp/ESP32_C3 @supperthomas
/bsp/nr5x/ @supperthomas
/bsp/stm32/stm32l496-st-nucleo @supperthomas
/bsp/stm32/stm32f407-rt-spark @supperthomas
/bsp/stm32/stm32f407-rt-spark @Rbb666
/bsp/stm32/stm32h743-openmv-h7plus @supperthomas
/bsp/stm32/stm32l4r9-st-sensortile-box/ @supperthomas
/bsp/stm32/stm32l475-atk-pandora/ @mysterywolf
@ -17,7 +16,10 @@
/bsp/stm32/stm32f411-st-nucleo/ @mysterywolf
/bsp/stm32/stm32f412-st-nucleo/ @mysterywolf
/bsp/stm32/stm32l476-st-nucleo/ @mysterywolf
/bsp/stm32/stm32h750-artpi/ @Rbb666
/bsp/maxim @supperthomas
/bsp/nxp @Rbb666
/bsp/renesas @Rbb666
*arduino* @mysterywolf
*.attach @mysterywolf
@ -30,5 +32,5 @@
/components/drivers/tty/ @BernardXiong
/documentation @mysterywolf @Cathy-lulu
/examples @Guozhanxin
/examples @Rbb666

56
.github/workflows/action_runner.yml vendored Normal file
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@ -0,0 +1,56 @@
#
# Copyright (c) 2006-2024, RT-Thread Development Team
#
# SPDX-License-Identifier: Apache-2.0
#
# Change Logs:
# Date Author Notes
# 2024-07-19 supperthomas the first version
#
name: action_runner
on:
workflow_dispatch:
inputs:
bsp_options:
description: 'Which bsp path Would you want dist in bsp?like stm32/stm32f103-blue-pill'
required: false
type: string
default: 'stm32/stm32f103-blue-pill'
bsp_tool_chain:
description: 'Choice tool_chain'
required: false
default: 'KEIL'
type: choice
options:
- "KEIL"
- "IAR"
bsp_config:
description: 'Type a config you want mannual test in .config, like: CONFIG_RT_USING_DEBUG=y,CONFIG_RT_DEBUGING_COLOR=y,CONFIG_RT_DEBUGING_CONTEXT=y'
required: false
type: string
default: 'CONFIG_RT_USING_DEBUG=y,CONFIG_RT_DEBUGING_COLOR=y,CONFIG_RT_DEBUGING_CONTEXT=y'
permissions:
contents: read
jobs:
build:
runs-on: [self-hosted, windows, x64]
name: ${{ github.event.inputs.bsp_options }}
steps:
- uses: actions/checkout@v3
- name: Bsp Scons Compile
if: ${{ success() }}
env:
RTT_BSP: ${{ github.event.inputs.bsp_options }}
RTT_TOOL_CHAIN: ${{ github.event.inputs.bsp_tool_chain}}
run: |
ls
echo $RTT_BSP
cd bsp/stm32/stm32f103-blue-pill
scons --target=mdk5
UV4.exe -b project.uvprojx -q -j0 -t rt-thread -o action_runner.log
ls
sleep 10
cat action_runner.log

330
bsp/allwinner/d1s/.config
View File

@ -101,6 +101,7 @@ CONFIG_ARCH_MM_MMU=y
CONFIG_KERNEL_VADDR_START=0x40000000
CONFIG_ARCH_RISCV=y
CONFIG_ARCH_RISCV64=y
CONFIG_ARCH_USING_RISCV_COMMON64=y
#
# RT-Thread Components
@ -202,7 +203,9 @@ CONFIG_RT_USING_SERIAL=y
CONFIG_RT_USING_SERIAL_V2=y
# CONFIG_RT_SERIAL_USING_DMA is not set
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_CPUTIME is not set
CONFIG_RT_USING_CPUTIME=y
CONFIG_RT_USING_CPUTIME_RISCV=y
CONFIG_CPUTIME_TIMER_FREQ=24000000
# CONFIG_RT_USING_I2C is not set
# CONFIG_RT_USING_PHY is not set
# CONFIG_RT_USING_ADC is not set
@ -379,9 +382,9 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64
# CONFIG_PKG_USING_KAWAII_MQTT is not set
# CONFIG_PKG_USING_BC28_MQTT is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_LIBMODBUS is not set
# CONFIG_PKG_USING_FREEMODBUS is not set
# CONFIG_PKG_USING_NANOPB is not set
# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set
#
# Wi-Fi
@ -400,6 +403,24 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64
# end of Wiced WiFi
# CONFIG_PKG_USING_RW007 is not set
#
# CYW43012 WiFi
#
# CONFIG_PKG_USING_WLAN_CYW43012 is not set
# end of CYW43012 WiFi
#
# BL808 WiFi
#
# CONFIG_PKG_USING_WLAN_BL808 is not set
# end of BL808 WiFi
#
# CYW43439 WiFi
#
# CONFIG_PKG_USING_WLAN_CYW43439 is not set
# end of CYW43439 WiFi
# end of Wi-Fi
# CONFIG_PKG_USING_COAP is not set
@ -423,7 +444,6 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64
# CONFIG_PKG_USING_JIOT-C-SDK is not set
# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
# CONFIG_PKG_USING_JOYLINK is not set
# CONFIG_PKG_USING_EZ_IOT_OS is not set
# CONFIG_PKG_USING_IOTSHARP_SDK is not set
# end of IoT Cloud
@ -446,6 +466,8 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64
# CONFIG_PKG_USING_NMEALIB is not set
# CONFIG_PKG_USING_PDULIB is not set
# CONFIG_PKG_USING_BTSTACK is not set
# CONFIG_PKG_USING_BT_CYW43012 is not set
# CONFIG_PKG_USING_CYW43XX is not set
# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
# CONFIG_PKG_USING_MAVLINK is not set
@ -454,6 +476,8 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64
# CONFIG_PKG_USING_AGILE_FTP is not set
# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
# CONFIG_PKG_USING_RT_LINK_HW is not set
# CONFIG_PKG_USING_RYANMQTT is not set
# CONFIG_PKG_USING_RYANW5500 is not set
# CONFIG_PKG_USING_LORA_PKT_FWD is not set
# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
@ -461,6 +485,11 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64
# CONFIG_PKG_USING_SMALL_MODBUS is not set
# CONFIG_PKG_USING_NET_SERVER is not set
# CONFIG_PKG_USING_ZFTP is not set
# CONFIG_PKG_USING_WOL is not set
# CONFIG_PKG_USING_ZEPHYR_POLLING is not set
# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set
# CONFIG_PKG_USING_LHC_MODBUS is not set
# CONFIG_PKG_USING_QMODBUS is not set
# end of IoT - internet of things
#
@ -513,7 +542,6 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64
# LVGL: powerful and easy-to-use embedded GUI library
#
# CONFIG_PKG_USING_LVGL is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
# end of LVGL: powerful and easy-to-use embedded GUI library
@ -538,19 +566,12 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64
# CONFIG_PKG_USING_MP3PLAYER is not set
# CONFIG_PKG_USING_TINYJPEG is not set
# CONFIG_PKG_USING_UGUI is not set
#
# PainterEngine: A cross-platform graphics application framework written in C language
#
# CONFIG_PKG_USING_PAINTERENGINE is not set
# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set
# end of PainterEngine: A cross-platform graphics application framework written in C language
# CONFIG_PKG_USING_MCURSES is not set
# CONFIG_PKG_USING_TERMBOX is not set
# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_GUIENGINE is not set
# CONFIG_PKG_USING_3GPP_AMRNB is not set
# end of multimedia packages
#
@ -561,9 +582,9 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_SEGGER_RTT is not set
# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_ULOG_FILE is not set
# CONFIG_PKG_USING_LOGMGR is not set
# CONFIG_PKG_USING_ADBD is not set
# CONFIG_PKG_USING_COREMARK is not set
@ -597,9 +618,9 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64
# CONFIG_PKG_USING_CBOX is not set
# CONFIG_PKG_USING_SNOWFLAKE is not set
# CONFIG_PKG_USING_HASH_MATCH is not set
# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
# CONFIG_PKG_USING_VOFA_PLUS is not set
# CONFIG_PKG_USING_ZDEBUG is not set
# end of tools packages
#
@ -614,6 +635,8 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64
# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
# end of enhanced kernel services
# CONFIG_PKG_USING_AUNITY is not set
#
# acceleration: Assembly language or algorithmic acceleration packages
#
@ -626,6 +649,9 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64
# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
#
# CONFIG_PKG_USING_CMSIS_5 is not set
# CONFIG_PKG_USING_CMSIS_CORE is not set
# CONFIG_PKG_USING_CMSIS_DSP is not set
# CONFIG_PKG_USING_CMSIS_NN is not set
# CONFIG_PKG_USING_CMSIS_RTOS1 is not set
# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
@ -642,10 +668,14 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64
# end of Micrium: Micrium software products porting for RT-Thread
# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
# CONFIG_PKG_USING_LITEOS_SDK is not set
# CONFIG_PKG_USING_TZ_DATABASE is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_PERF_COUNTER is not set
# CONFIG_PKG_USING_FILEX is not set
# CONFIG_PKG_USING_LEVELX is not set
# CONFIG_PKG_USING_FLASHDB is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
@ -665,6 +695,7 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64
# CONFIG_PKG_USING_QBOOT is not set
# CONFIG_PKG_USING_PPOOL is not set
# CONFIG_PKG_USING_OPENAMP is not set
# CONFIG_PKG_USING_RPMSG_LITE is not set
# CONFIG_PKG_USING_LPM is not set
# CONFIG_PKG_USING_TLSF is not set
# CONFIG_PKG_USING_EVENT_RECORDER is not set
@ -676,30 +707,52 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64
# CONFIG_PKG_USING_TFDB is not set
# CONFIG_PKG_USING_QPC is not set
# CONFIG_PKG_USING_AGILE_UPGRADE is not set
# CONFIG_PKG_USING_FLASH_BLOB is not set
# CONFIG_PKG_USING_MLIBC is not set
# CONFIG_PKG_USING_TASK_MSG_BUS is not set
# CONFIG_PKG_USING_SFDB is not set
# CONFIG_PKG_USING_RTP is not set
# CONFIG_PKG_USING_REB is not set
# CONFIG_PKG_USING_R_RHEALSTONE is not set
# end of system packages
#
# peripheral libraries and drivers
#
# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_SHT3X is not set
# CONFIG_PKG_USING_ADT74XX is not set
# CONFIG_PKG_USING_AS7341 is not set
#
# HAL & SDK Drivers
#
#
# STM32 HAL & SDK Drivers
#
# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set
# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set
# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set
# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set
# CONFIG_PKG_USING_STM32WB55_SDK is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# end of STM32 HAL & SDK Drivers
#
# Infineon HAL Packages
#
# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set
# CONFIG_PKG_USING_INFINEON_CMSIS is not set
# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set
# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set
# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set
# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set
# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set
# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set
# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set
# CONFIG_PKG_USING_INFINEON_USBDEV is not set
# end of Infineon HAL Packages
# CONFIG_PKG_USING_BLUETRUM_SDK is not set
# CONFIG_PKG_USING_EMBARC_BSP is not set
# CONFIG_PKG_USING_ESP_IDF is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_SX12XX is not set
# CONFIG_PKG_USING_SIGNAL_LED is not set
# CONFIG_PKG_USING_LEDBLINK is not set
# CONFIG_PKG_USING_LITTLED is not set
# CONFIG_PKG_USING_LKDGUI is not set
# CONFIG_PKG_USING_NRF5X_SDK is not set
# CONFIG_PKG_USING_NRFX is not set
# CONFIG_PKG_USING_WM_LIBRARIES is not set
#
# Kendryte SDK
@ -708,34 +761,128 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
# end of Kendryte SDK
# CONFIG_PKG_USING_NRF5X_SDK is not set
# CONFIG_PKG_USING_NRFX is not set
# CONFIG_PKG_USING_NUCLEI_SDK is not set
# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
# end of HAL & SDK Drivers
#
# sensors drivers
#
# CONFIG_PKG_USING_LSM6DSM is not set
# CONFIG_PKG_USING_LSM6DSL is not set
# CONFIG_PKG_USING_LPS22HB is not set
# CONFIG_PKG_USING_HTS221 is not set
# CONFIG_PKG_USING_LSM303AGR is not set
# CONFIG_PKG_USING_BME280 is not set
# CONFIG_PKG_USING_BME680 is not set
# CONFIG_PKG_USING_BMA400 is not set
# CONFIG_PKG_USING_BMI160_BMX160 is not set
# CONFIG_PKG_USING_SPL0601 is not set
# CONFIG_PKG_USING_MS5805 is not set
# CONFIG_PKG_USING_DA270 is not set
# CONFIG_PKG_USING_DF220 is not set
# CONFIG_PKG_USING_HSHCAL001 is not set
# CONFIG_PKG_USING_BH1750 is not set
# CONFIG_PKG_USING_MPU6XXX is not set
# CONFIG_PKG_USING_AHT10 is not set
# CONFIG_PKG_USING_AP3216C is not set
# CONFIG_PKG_USING_TSL4531 is not set
# CONFIG_PKG_USING_DS18B20 is not set
# CONFIG_PKG_USING_DHT11 is not set
# CONFIG_PKG_USING_DHTXX is not set
# CONFIG_PKG_USING_GY271 is not set
# CONFIG_PKG_USING_GP2Y10 is not set
# CONFIG_PKG_USING_SGP30 is not set
# CONFIG_PKG_USING_HDC1000 is not set
# CONFIG_PKG_USING_BMP180 is not set
# CONFIG_PKG_USING_BMP280 is not set
# CONFIG_PKG_USING_SHTC1 is not set
# CONFIG_PKG_USING_BMI088 is not set
# CONFIG_PKG_USING_HMC5883 is not set
# CONFIG_PKG_USING_MAX6675 is not set
# CONFIG_PKG_USING_TMP1075 is not set
# CONFIG_PKG_USING_SR04 is not set
# CONFIG_PKG_USING_CCS811 is not set
# CONFIG_PKG_USING_PMSXX is not set
# CONFIG_PKG_USING_RT3020 is not set
# CONFIG_PKG_USING_MLX90632 is not set
# CONFIG_PKG_USING_MLX90393 is not set
# CONFIG_PKG_USING_MLX90392 is not set
# CONFIG_PKG_USING_MLX90397 is not set
# CONFIG_PKG_USING_MS5611 is not set
# CONFIG_PKG_USING_MAX31865 is not set
# CONFIG_PKG_USING_VL53L0X is not set
# CONFIG_PKG_USING_INA260 is not set
# CONFIG_PKG_USING_MAX30102 is not set
# CONFIG_PKG_USING_INA226 is not set
# CONFIG_PKG_USING_LIS2DH12 is not set
# CONFIG_PKG_USING_HS300X is not set
# CONFIG_PKG_USING_ZMOD4410 is not set
# CONFIG_PKG_USING_ISL29035 is not set
# CONFIG_PKG_USING_MMC3680KJ is not set
# CONFIG_PKG_USING_QMP6989 is not set
# CONFIG_PKG_USING_BALANCE is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_SHT3X is not set
# CONFIG_PKG_USING_SHT4X is not set
# CONFIG_PKG_USING_AD7746 is not set
# CONFIG_PKG_USING_ADT74XX is not set
# CONFIG_PKG_USING_MAX17048 is not set
# CONFIG_PKG_USING_AS7341 is not set
# CONFIG_PKG_USING_CW2015 is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_PAJ7620 is not set
# CONFIG_PKG_USING_STHS34PF80 is not set
# end of sensors drivers
#
# touch drivers
#
# CONFIG_PKG_USING_GT9147 is not set
# CONFIG_PKG_USING_GT1151 is not set
# CONFIG_PKG_USING_GT917S is not set
# CONFIG_PKG_USING_GT911 is not set
# CONFIG_PKG_USING_FT6206 is not set
# CONFIG_PKG_USING_FT5426 is not set
# CONFIG_PKG_USING_FT6236 is not set
# CONFIG_PKG_USING_XPT2046_TOUCH is not set
# CONFIG_PKG_USING_CST816X is not set
# CONFIG_PKG_USING_CST812T is not set
# end of touch drivers
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_SX12XX is not set
# CONFIG_PKG_USING_SIGNAL_LED is not set
# CONFIG_PKG_USING_LEDBLINK is not set
# CONFIG_PKG_USING_LITTLED is not set
# CONFIG_PKG_USING_LKDGUI is not set
# CONFIG_PKG_USING_INFRARED is not set
# CONFIG_PKG_USING_MULTI_INFRARED is not set
# CONFIG_PKG_USING_AGILE_BUTTON is not set
# CONFIG_PKG_USING_AGILE_LED is not set
# CONFIG_PKG_USING_AT24CXX is not set
# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
# CONFIG_PKG_USING_AD7746 is not set
# CONFIG_PKG_USING_PCA9685 is not set
# CONFIG_PKG_USING_ILI9341 is not set
# CONFIG_PKG_USING_I2C_TOOLS is not set
# CONFIG_PKG_USING_NRF24L01 is not set
# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
# CONFIG_PKG_USING_MAX17048 is not set
# CONFIG_PKG_USING_RPLIDAR is not set
# CONFIG_PKG_USING_AS608 is not set
# CONFIG_PKG_USING_RC522 is not set
# CONFIG_PKG_USING_WS2812B is not set
# CONFIG_PKG_USING_EMBARC_BSP is not set
# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
# CONFIG_PKG_USING_MULTI_RTIMER is not set
# CONFIG_PKG_USING_MAX7219 is not set
# CONFIG_PKG_USING_BEEP is not set
# CONFIG_PKG_USING_EASYBLINK is not set
# CONFIG_PKG_USING_PMS_SERIES is not set
# CONFIG_PKG_USING_NUCLEI_SDK is not set
# CONFIG_PKG_USING_CAN_YMODEM is not set
# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
# CONFIG_PKG_USING_QLED is not set
# CONFIG_PKG_USING_PAJ7620 is not set
# CONFIG_PKG_USING_AGILE_CONSOLE is not set
# CONFIG_PKG_USING_LD3320 is not set
# CONFIG_PKG_USING_WK2124 is not set
@ -749,7 +896,6 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64
# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
# CONFIG_PKG_USING_VDEVICE is not set
# CONFIG_PKG_USING_SGM706 is not set
# CONFIG_PKG_USING_STM32WB55_SDK is not set
# CONFIG_PKG_USING_RDA58XX is not set
# CONFIG_PKG_USING_LIBNFC is not set
# CONFIG_PKG_USING_MFOC is not set
@ -759,17 +905,25 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64
# CONFIG_PKG_USING_ROSSERIAL is not set
# CONFIG_PKG_USING_MICRO_ROS is not set
# CONFIG_PKG_USING_MCP23008 is not set
# CONFIG_PKG_USING_BLUETRUM_SDK is not set
# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
# CONFIG_PKG_USING_BL_MCU_SDK is not set
# CONFIG_PKG_USING_SOFT_SERIAL is not set
# CONFIG_PKG_USING_MB85RS16 is not set
# CONFIG_PKG_USING_CW2015 is not set
# CONFIG_PKG_USING_RFM300 is not set
# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
# CONFIG_PKG_USING_AIP650 is not set
# CONFIG_PKG_USING_FINGERPRINT is not set
# CONFIG_PKG_USING_BT_ECB02C is not set
# CONFIG_PKG_USING_UAT is not set
# CONFIG_PKG_USING_ST7789 is not set
# CONFIG_PKG_USING_VS1003 is not set
# CONFIG_PKG_USING_X9555 is not set
# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set
# CONFIG_PKG_USING_BT_MX01 is not set
# CONFIG_PKG_USING_RGPOWER is not set
# CONFIG_PKG_USING_SPI_TOOLS is not set
# end of peripheral libraries and drivers
#
@ -784,8 +938,20 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_QUEST is not set
# CONFIG_PKG_USING_NAXOS is not set
# CONFIG_PKG_USING_R_TINYMAIX is not set
# end of AI packages
#
# Signal Processing and Control Algorithm Packages
#
# CONFIG_PKG_USING_APID is not set
# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
# CONFIG_PKG_USING_QPID is not set
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_DIGITALCTRL is not set
# CONFIG_PKG_USING_KISSFFT is not set
# end of Signal Processing and Control Algorithm Packages
#
# miscellaneous packages
#
@ -817,6 +983,7 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64
# CONFIG_PKG_USING_TETRIS is not set
# CONFIG_PKG_USING_DONUT is not set
# CONFIG_PKG_USING_COWSAY is not set
# CONFIG_PKG_USING_MORSE is not set
# end of entertainment: terminal games and other interesting software packages
# CONFIG_PKG_USING_LIBCSV is not set
@ -825,6 +992,7 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64
# CONFIG_PKG_USING_MINILZO is not set
# CONFIG_PKG_USING_QUICKLZ is not set
# CONFIG_PKG_USING_LZMA is not set
# CONFIG_PKG_USING_RALARAM is not set
# CONFIG_PKG_USING_MULTIBUTTON is not set
# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set
@ -834,14 +1002,12 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64
# CONFIG_PKG_USING_DSTR is not set
# CONFIG_PKG_USING_TINYFRAME is not set
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
# CONFIG_PKG_USING_DIGITALCTRL is not set
# CONFIG_PKG_USING_UPACKER is not set
# CONFIG_PKG_USING_UPARAM is not set
# CONFIG_PKG_USING_HELLO is not set
# CONFIG_PKG_USING_VI is not set
# CONFIG_PKG_USING_KI is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_CRCLIB is not set
# CONFIG_PKG_USING_LWGPS is not set
# CONFIG_PKG_USING_STATE_MACHINE is not set
@ -852,6 +1018,7 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64
# CONFIG_PKG_USING_SLCAN2RTT is not set
# CONFIG_PKG_USING_SOEM is not set
# CONFIG_PKG_USING_QPARAM is not set
# CONFIG_PKG_USING_CorevMCU_CLI is not set
# end of miscellaneous packages
#
@ -860,26 +1027,30 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64
# CONFIG_PKG_USING_RTDUINO is not set
#
# Projects
# Projects and Demos
#
# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set
# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set
# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set
# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
# end of Projects
# end of Projects and Demos
#
# Sensors
#
# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set
# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
@ -921,7 +1092,7 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
@ -971,18 +1142,61 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set
# end of Sensors
#
# Display
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set
# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set
# CONFIG_PKG_USING_SEEED_TM1637 is not set
# end of Display
#
# Timing
#
# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
# CONFIG_PKG_USING_ARDUINO_TICKER is not set
# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set
# end of Timing
#
@ -990,6 +1204,8 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64
#
# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set
# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set
# end of Data Processing
#
@ -1008,11 +1224,19 @@ CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
# end of Device Control
#
# Other
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
# end of Other
#
# Signal IO

1
bsp/allwinner/d1s/Kconfig
View File

@ -12,6 +12,7 @@ osource "$PKGS_DIR/Kconfig"
config BOARD_allwinnerd1s
bool
select ARCH_RISCV64
select ARCH_USING_RISCV_COMMON64
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
select RT_USING_CACHE

48
bsp/allwinner/d1s/rtconfig.h
View File

@ -68,6 +68,7 @@
#define KERNEL_VADDR_START 0x40000000
#define ARCH_RISCV
#define ARCH_RISCV64
#define ARCH_USING_RISCV_COMMON64
/* RT-Thread Components */
@ -143,6 +144,9 @@
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V2
#define RT_USING_CPUTIME
#define RT_USING_CPUTIME_RISCV
#define CPUTIME_TIMER_FREQ 24000000
#define RT_USING_NULL
#define RT_USING_ZERO
#define RT_USING_RANDOM
@ -243,6 +247,18 @@
/* Wiced WiFi */
/* end of Wiced WiFi */
/* CYW43012 WiFi */
/* end of CYW43012 WiFi */
/* BL808 WiFi */
/* end of BL808 WiFi */
/* CYW43439 WiFi */
/* end of CYW43439 WiFi */
/* end of Wi-Fi */
/* IoT Cloud */
@ -274,10 +290,6 @@
/* u8g2: a monochrome graphic library */
/* end of u8g2: a monochrome graphic library */
/* PainterEngine: A cross-platform graphics application framework written in C language */
/* end of PainterEngine: A cross-platform graphics application framework written in C language */
/* end of multimedia packages */
/* tools packages */
@ -305,16 +317,38 @@
/* peripheral libraries and drivers */
/* HAL & SDK Drivers */
/* STM32 HAL & SDK Drivers */
/* end of STM32 HAL & SDK Drivers */
/* Infineon HAL Packages */
/* end of Infineon HAL Packages */
/* Kendryte SDK */
/* end of Kendryte SDK */
/* end of HAL & SDK Drivers */
/* sensors drivers */
/* end of sensors drivers */
/* touch drivers */
/* end of touch drivers */
/* end of peripheral libraries and drivers */
/* AI packages */
/* end of AI packages */
/* Signal Processing and Control Algorithm Packages */
/* end of Signal Processing and Control Algorithm Packages */
/* miscellaneous packages */
/* project laboratory */
@ -333,9 +367,9 @@
/* Arduino libraries */
/* Projects */
/* Projects and Demos */
/* end of Projects */
/* end of Projects and Demos */
/* Sensors */
@ -365,6 +399,8 @@
/* Other */
/* end of Other */
/* Signal IO */
/* end of Signal IO */

1
bsp/at32/at32a403a-start/README.md
View File

@ -41,6 +41,7 @@ AT32A403A-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以
| UART | 支持 | USART1/2/3 |
| GPIO | 支持 | PA0...PF7 |
| IIC | 支持 | GPIO模拟I2C |
| HWIIC | 支持 | I2C1/2/3 |
| SPI | 支持 | SPI1/2 |
| ADC | 支持 | ADC1/2 |
| DAC | 支持 | DAC1 |

51
bsp/at32/at32a403a-start/board/Kconfig
View File

@ -265,6 +265,57 @@ menu "On-chip Peripheral Drivers"
endif
endif
menuconfig BSP_USING_HARD_I2C
bool "Enable I2C BUS (hardware driver)"
default n
select RT_USING_I2C
if BSP_USING_HARD_I2C
config BSP_USING_HARD_I2C1
bool "Enable I2C1 BUS"
default n
config BSP_I2C1_TX_USING_DMA
bool "Enable I2C1 TX DMA"
depends on BSP_USING_HARD_I2C1
default n
config BSP_I2C1_RX_USING_DMA
bool "Enable I2C1 RX DMA"
depends on BSP_USING_HARD_I2C1
select BSP_I2C1_TX_USING_DMA
default n
config BSP_USING_HARD_I2C2
bool "Enable I2C2 BUS"
default n
config BSP_I2C2_TX_USING_DMA
bool "Enable I2C2 TX DMA"
depends on BSP_USING_HARD_I2C2
default n
config BSP_I2C2_RX_USING_DMA
bool "Enable I2C2 RX DMA"
depends on BSP_USING_HARD_I2C2
select BSP_I2C2_TX_USING_DMA
default n
config BSP_USING_HARD_I2C3
bool "Enable I2C3 BUS"
default n
config BSP_I2C3_TX_USING_DMA
bool "Enable I2C3 TX DMA"
depends on BSP_USING_HARD_I2C3
default n
config BSP_I2C3_RX_USING_DMA
bool "Enable I2C3 RX DMA"
depends on BSP_USING_HARD_I2C3
select BSP_I2C3_TX_USING_DMA
default n
endif
menuconfig BSP_USING_ADC
bool "Enable ADC"
default n

54
bsp/at32/at32a403a-start/board/src/at32_msp.c
View File

@ -129,6 +129,60 @@ void at32_msp_spi_init(void *instance)
}
#endif /* BSP_USING_SPI */
#ifdef BSP_USING_HARD_I2C
void at32_msp_i2c_init(void *instance)
{
gpio_init_type gpio_init_struct;
i2c_type *i2c_x = (i2c_type *)instance;
gpio_default_para_init(&gpio_init_struct);
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
#ifdef BSP_USING_HARD_I2C1
if(I2C1 == i2c_x)
{
crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7;
gpio_init(GPIOB, &gpio_init_struct);
}
#endif
#ifdef BSP_USING_HARD_I2C2
if(I2C2 == i2c_x)
{
crm_periph_clock_enable(CRM_I2C2_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init_struct.gpio_pins = GPIO_PINS_10 | GPIO_PINS_11;
gpio_init(GPIOB, &gpio_init_struct);
}
#endif
#ifdef BSP_USING_HARD_I2C3
if(I2C3 == i2c_x)
{
crm_periph_clock_enable(CRM_I2C3_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE);
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init_struct.gpio_pins = GPIO_PINS_8;
gpio_init(GPIOA, &gpio_init_struct);
gpio_init_struct.gpio_pins = GPIO_PINS_9;
gpio_init(GPIOC, &gpio_init_struct);
}
#endif
/* add others */
}
#endif /* BSP_USING_HARD_I2C */
#ifdef BSP_USING_SDIO
void at32_msp_sdio_init(void *instance)
{

1
bsp/at32/at32a423-start/README.md
View File

@ -41,6 +41,7 @@ AT32A423-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以
| UART | 支持 | USART1/2/3 |
| GPIO | 支持 | PA0...PF10 |
| IIC | 支持 | GPIO模拟I2C |
| HWIIC | 支持 | I2C1/2/3 |
| SPI | 支持 | SPI1/2 |
| ADC | 支持 | ADC1 |
| DAC | 支持 | DAC1 |

51
bsp/at32/at32a423-start/board/Kconfig
View File

@ -277,6 +277,57 @@ menu "On-chip Peripheral Drivers"
endif
endif
menuconfig BSP_USING_HARD_I2C
bool "Enable I2C BUS (hardware driver)"
default n
select RT_USING_I2C
if BSP_USING_HARD_I2C
config BSP_USING_HARD_I2C1
bool "Enable I2C1 BUS"
default n
config BSP_I2C1_TX_USING_DMA
bool "Enable I2C1 TX DMA"
depends on BSP_USING_HARD_I2C1
default n
config BSP_I2C1_RX_USING_DMA
bool "Enable I2C1 RX DMA"
depends on BSP_USING_HARD_I2C1
select BSP_I2C1_TX_USING_DMA
default n
config BSP_USING_HARD_I2C2
bool "Enable I2C2 BUS"
default n
config BSP_I2C2_TX_USING_DMA
bool "Enable I2C2 TX DMA"
depends on BSP_USING_HARD_I2C2
default n
config BSP_I2C2_RX_USING_DMA
bool "Enable I2C2 RX DMA"
depends on BSP_USING_HARD_I2C2
select BSP_I2C2_TX_USING_DMA
default n
config BSP_USING_HARD_I2C3
bool "Enable I2C3 BUS"
default n
config BSP_I2C3_TX_USING_DMA
bool "Enable I2C3 TX DMA"
depends on BSP_USING_HARD_I2C3
default n
config BSP_I2C3_RX_USING_DMA
bool "Enable I2C3 RX DMA"
depends on BSP_USING_HARD_I2C3
select BSP_I2C3_TX_USING_DMA
default n
endif
menuconfig BSP_USING_ADC
bool "Enable ADC"
default n

1
bsp/at32/at32a423-start/board/inc/at32_msp.h
View File

@ -19,5 +19,6 @@ void at32_msp_hwtmr_init(void *instance);
void at32_msp_can_init(void *instance);
void at32_msp_usb_init(void *instance);
void at32_msp_dac_init(void *instance);
void at32_msp_i2c_init(void *instance);
#endif /* __AT32_MSP_H__ */

62
bsp/at32/at32a423-start/board/src/at32_msp.c
View File

@ -134,6 +134,68 @@ void at32_msp_spi_init(void *instance)
/* add others */
}
#endif /* BSP_USING_SPI */
#ifdef BSP_USING_HARD_I2C
void at32_msp_i2c_init(void *instance)
{
gpio_init_type gpio_init_struct;
i2c_type *i2c_x = (i2c_type *)instance;
gpio_default_para_init(&gpio_init_struct);
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
#ifdef BSP_USING_HARD_I2C1
if(I2C1 == i2c_x)
{
crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7;
gpio_init(GPIOB, &gpio_init_struct);
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE6, GPIO_MUX_4);
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE7, GPIO_MUX_4);
}
#endif
#ifdef BSP_USING_HARD_I2C2
if(I2C2 == i2c_x)
{
crm_periph_clock_enable(CRM_I2C2_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init_struct.gpio_pins = GPIO_PINS_10 | GPIO_PINS_11;
gpio_init(GPIOB, &gpio_init_struct);
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE10, GPIO_MUX_4);
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE11, GPIO_MUX_4);
}
#endif
#ifdef BSP_USING_HARD_I2C3
if(I2C3 == i2c_x)
{
crm_periph_clock_enable(CRM_I2C3_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE);
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init_struct.gpio_pins = GPIO_PINS_8;
gpio_init(GPIOA, &gpio_init_struct);
gpio_init_struct.gpio_pins = GPIO_PINS_9;
gpio_init(GPIOC, &gpio_init_struct);
gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE8, GPIO_MUX_4);
gpio_pin_mux_config(GPIOC, GPIO_PINS_SOURCE9, GPIO_MUX_4);
}
#endif
/* add others */
}
#endif /* BSP_USING_HARD_I2C */
#ifdef BSP_USING_PWM
void at32_msp_tmr_init(void *instance)

1
bsp/at32/at32f402-start/README.md
View File

@ -41,6 +41,7 @@ AT32F402-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以
| UART | 支持 | USART1/2/3 |
| GPIO | 支持 | PA0...PF7 |
| IIC | 支持 | GPIO模拟I2C |
| HWIIC | 支持 | I2C1/2/3 |
| SPI | 支持 | SPI1/2 |
| ADC | 支持 | ADC1 |
| PWM | 支持 | TMR1/2 |

51
bsp/at32/at32f402-start/board/Kconfig
View File

@ -288,6 +288,57 @@ menu "On-chip Peripheral Drivers"
endif
endif
menuconfig BSP_USING_HARD_I2C
bool "Enable I2C BUS (hardware driver)"
default n
select RT_USING_I2C
if BSP_USING_HARD_I2C
config BSP_USING_HARD_I2C1
bool "Enable I2C1 BUS"
default n
config BSP_I2C1_TX_USING_DMA
bool "Enable I2C1 TX DMA"
depends on BSP_USING_HARD_I2C1
default n
config BSP_I2C1_RX_USING_DMA
bool "Enable I2C1 RX DMA"
depends on BSP_USING_HARD_I2C1
select BSP_I2C1_TX_USING_DMA
default n
config BSP_USING_HARD_I2C2
bool "Enable I2C2 BUS"
default n
config BSP_I2C2_TX_USING_DMA
bool "Enable I2C2 TX DMA"
depends on BSP_USING_HARD_I2C2
default n
config BSP_I2C2_RX_USING_DMA
bool "Enable I2C2 RX DMA"
depends on BSP_USING_HARD_I2C2
select BSP_I2C2_TX_USING_DMA
default n
config BSP_USING_HARD_I2C3
bool "Enable I2C3 BUS"
default n
config BSP_I2C3_TX_USING_DMA
bool "Enable I2C3 TX DMA"
depends on BSP_USING_HARD_I2C3
default n
config BSP_I2C3_RX_USING_DMA
bool "Enable I2C3 RX DMA"
depends on BSP_USING_HARD_I2C3
select BSP_I2C3_TX_USING_DMA
default n
endif
menuconfig BSP_USING_ADC
bool "Enable ADC"
default n

63
bsp/at32/at32f402-start/board/src/at32_msp.c
View File

@ -127,6 +127,69 @@ void at32_msp_spi_init(void *instance)
}
#endif /* BSP_USING_SPI */
#ifdef BSP_USING_HARD_I2C
void at32_msp_i2c_init(void *instance)
{
gpio_init_type gpio_init_struct;
i2c_type *i2c_x = (i2c_type *)instance;
gpio_default_para_init(&gpio_init_struct);
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
#ifdef BSP_USING_HARD_I2C1
if(I2C1 == i2c_x)
{
crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7;
gpio_init(GPIOB, &gpio_init_struct);
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE6, GPIO_MUX_4);
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE7, GPIO_MUX_4);
}
#endif
#ifdef BSP_USING_HARD_I2C2
if(I2C2 == i2c_x)
{
crm_periph_clock_enable(CRM_I2C2_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init_struct.gpio_pins = GPIO_PINS_3 | GPIO_PINS_10;
gpio_init(GPIOB, &gpio_init_struct);
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE3, GPIO_MUX_4);
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE10, GPIO_MUX_4);
}
#endif
#ifdef BSP_USING_HARD_I2C3
if(I2C3 == i2c_x)
{
crm_periph_clock_enable(CRM_I2C3_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE);
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init_struct.gpio_pins = GPIO_PINS_8;
gpio_init(GPIOA, &gpio_init_struct);
gpio_init_struct.gpio_pins = GPIO_PINS_9;
gpio_init(GPIOC, &gpio_init_struct);
gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE8, GPIO_MUX_4);
gpio_pin_mux_config(GPIOC, GPIO_PINS_SOURCE9, GPIO_MUX_4);
}
#endif
/* add others */
}
#endif /* BSP_USING_HARD_I2C */
#ifdef BSP_USING_PWM
void at32_msp_tmr_init(void *instance)
{

1
bsp/at32/at32f403a-start/README.md
View File

@ -41,6 +41,7 @@ AT32F403A-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以
| UART | 支持 | USART1/2/3 |
| GPIO | 支持 | PA0...PF7 |
| IIC | 支持 | GPIO模拟I2C |
| HWIIC | 支持 | I2C1/2/3 |
| SPI | 支持 | SPI1/2 |
| ADC | 支持 | ADC1/2 |
| DAC | 支持 | DAC1 |

51
bsp/at32/at32f403a-start/board/Kconfig
View File

@ -265,6 +265,57 @@ menu "On-chip Peripheral Drivers"
endif
endif
menuconfig BSP_USING_HARD_I2C
bool "Enable I2C BUS (hardware driver)"
default n
select RT_USING_I2C
if BSP_USING_HARD_I2C
config BSP_USING_HARD_I2C1
bool "Enable I2C1 BUS"
default n
config BSP_I2C1_TX_USING_DMA
bool "Enable I2C1 TX DMA"
depends on BSP_USING_HARD_I2C1
default n
config BSP_I2C1_RX_USING_DMA
bool "Enable I2C1 RX DMA"
depends on BSP_USING_HARD_I2C1
select BSP_I2C1_TX_USING_DMA
default n
config BSP_USING_HARD_I2C2
bool "Enable I2C2 BUS"
default n
config BSP_I2C2_TX_USING_DMA
bool "Enable I2C2 TX DMA"
depends on BSP_USING_HARD_I2C2
default n
config BSP_I2C2_RX_USING_DMA
bool "Enable I2C2 RX DMA"
depends on BSP_USING_HARD_I2C2
select BSP_I2C2_TX_USING_DMA
default n
config BSP_USING_HARD_I2C3
bool "Enable I2C3 BUS"
default n
config BSP_I2C3_TX_USING_DMA
bool "Enable I2C3 TX DMA"
depends on BSP_USING_HARD_I2C3
default n
config BSP_I2C3_RX_USING_DMA
bool "Enable I2C3 RX DMA"
depends on BSP_USING_HARD_I2C3
select BSP_I2C3_TX_USING_DMA
default n
endif
menuconfig BSP_USING_ADC
bool "Enable ADC"
default n

54
bsp/at32/at32f403a-start/board/src/at32_msp.c
View File

@ -129,6 +129,60 @@ void at32_msp_spi_init(void *instance)
}
#endif /* BSP_USING_SPI */
#ifdef BSP_USING_HARD_I2C
void at32_msp_i2c_init(void *instance)
{
gpio_init_type gpio_init_struct;
i2c_type *i2c_x = (i2c_type *)instance;
gpio_default_para_init(&gpio_init_struct);
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
#ifdef BSP_USING_HARD_I2C1
if(I2C1 == i2c_x)
{
crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7;
gpio_init(GPIOB, &gpio_init_struct);
}
#endif
#ifdef BSP_USING_HARD_I2C2
if(I2C2 == i2c_x)
{
crm_periph_clock_enable(CRM_I2C2_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init_struct.gpio_pins = GPIO_PINS_10 | GPIO_PINS_11;
gpio_init(GPIOB, &gpio_init_struct);
}
#endif
#ifdef BSP_USING_HARD_I2C3
if(I2C3 == i2c_x)
{
crm_periph_clock_enable(CRM_I2C3_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE);
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init_struct.gpio_pins = GPIO_PINS_8;
gpio_init(GPIOA, &gpio_init_struct);
gpio_init_struct.gpio_pins = GPIO_PINS_9;
gpio_init(GPIOC, &gpio_init_struct);
}
#endif
/* add others */
}
#endif /* BSP_USING_HARD_I2C */
#ifdef BSP_USING_SDIO
void at32_msp_sdio_init(void *instance)
{

1
bsp/at32/at32f405-start/README.md
View File

@ -41,6 +41,7 @@ AT32F405-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以
| UART | 支持 | USART1/2/3 |
| GPIO | 支持 | PA0...PF7 |
| IIC | 支持 | GPIO模拟I2C |
| HWIIC | 支持 | I2C1/2/3 |
| SPI | 支持 | SPI1/2 |
| ADC | 支持 | ADC1 |
| PWM | 支持 | TMR1/2 |

51
bsp/at32/at32f405-start/board/Kconfig
View File

@ -307,6 +307,57 @@ menu "On-chip Peripheral Drivers"
endif
endif
menuconfig BSP_USING_HARD_I2C
bool "Enable I2C BUS (hardware driver)"
default n
select RT_USING_I2C
if BSP_USING_HARD_I2C
config BSP_USING_HARD_I2C1
bool "Enable I2C1 BUS"
default n
config BSP_I2C1_TX_USING_DMA
bool "Enable I2C1 TX DMA"
depends on BSP_USING_HARD_I2C1
default n
config BSP_I2C1_RX_USING_DMA
bool "Enable I2C1 RX DMA"
depends on BSP_USING_HARD_I2C1
select BSP_I2C1_TX_USING_DMA
default n
config BSP_USING_HARD_I2C2
bool "Enable I2C2 BUS"
default n
config BSP_I2C2_TX_USING_DMA
bool "Enable I2C2 TX DMA"
depends on BSP_USING_HARD_I2C2
default n
config BSP_I2C2_RX_USING_DMA
bool "Enable I2C2 RX DMA"
depends on BSP_USING_HARD_I2C2
select BSP_I2C2_TX_USING_DMA
default n
config BSP_USING_HARD_I2C3
bool "Enable I2C3 BUS"
default n
config BSP_I2C3_TX_USING_DMA
bool "Enable I2C3 TX DMA"
depends on BSP_USING_HARD_I2C3
default n
config BSP_I2C3_RX_USING_DMA
bool "Enable I2C3 RX DMA"
depends on BSP_USING_HARD_I2C3
select BSP_I2C3_TX_USING_DMA
default n
endif
menuconfig BSP_USING_ADC
bool "Enable ADC"
default n

63
bsp/at32/at32f405-start/board/src/at32_msp.c
View File

@ -127,6 +127,69 @@ void at32_msp_spi_init(void *instance)
}
#endif /* BSP_USING_SPI */
#ifdef BSP_USING_HARD_I2C
void at32_msp_i2c_init(void *instance)
{
gpio_init_type gpio_init_struct;
i2c_type *i2c_x = (i2c_type *)instance;
gpio_default_para_init(&gpio_init_struct);
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
#ifdef BSP_USING_HARD_I2C1
if(I2C1 == i2c_x)
{
crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7;
gpio_init(GPIOB, &gpio_init_struct);
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE6, GPIO_MUX_4);
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE7, GPIO_MUX_4);
}
#endif
#ifdef BSP_USING_HARD_I2C2
if(I2C2 == i2c_x)
{
crm_periph_clock_enable(CRM_I2C2_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init_struct.gpio_pins = GPIO_PINS_3 | GPIO_PINS_10;
gpio_init(GPIOB, &gpio_init_struct);
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE3, GPIO_MUX_4);
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE10, GPIO_MUX_4);
}
#endif
#ifdef BSP_USING_HARD_I2C3
if(I2C3 == i2c_x)
{
crm_periph_clock_enable(CRM_I2C3_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE);
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init_struct.gpio_pins = GPIO_PINS_8;
gpio_init(GPIOA, &gpio_init_struct);
gpio_init_struct.gpio_pins = GPIO_PINS_9;
gpio_init(GPIOC, &gpio_init_struct);
gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE8, GPIO_MUX_4);
gpio_pin_mux_config(GPIOC, GPIO_PINS_SOURCE9, GPIO_MUX_4);
}
#endif
/* add others */
}
#endif /* BSP_USING_HARD_I2C */
#ifdef BSP_USING_PWM
void at32_msp_tmr_init(void *instance)
{

1
bsp/at32/at32f407-start/README.md
View File

@ -41,6 +41,7 @@ AT32F407-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以
| UART | 支持 | USART1/2/3 |
| GPIO | 支持 | PA0...PF7 |
| IIC | 支持 | GPIO模拟I2C |
| HWIIC | 支持 | I2C1/2/3 |
| SPI | 支持 | SPI1/2 |
| ADC | 支持 | ADC1/2 |
| DAC | 支持 | DAC1 |

51
bsp/at32/at32f407-start/board/Kconfig
View File

@ -282,6 +282,57 @@ menu "On-chip Peripheral Drivers"
endif
endif
menuconfig BSP_USING_HARD_I2C
bool "Enable I2C BUS (hardware driver)"
default n
select RT_USING_I2C
if BSP_USING_HARD_I2C
config BSP_USING_HARD_I2C1
bool "Enable I2C1 BUS"
default n
config BSP_I2C1_TX_USING_DMA
bool "Enable I2C1 TX DMA"
depends on BSP_USING_HARD_I2C1
default n
config BSP_I2C1_RX_USING_DMA
bool "Enable I2C1 RX DMA"
depends on BSP_USING_HARD_I2C1
select BSP_I2C1_TX_USING_DMA
default n
config BSP_USING_HARD_I2C2
bool "Enable I2C2 BUS"
default n
config BSP_I2C2_TX_USING_DMA
bool "Enable I2C2 TX DMA"
depends on BSP_USING_HARD_I2C2
default n
config BSP_I2C2_RX_USING_DMA
bool "Enable I2C2 RX DMA"
depends on BSP_USING_HARD_I2C2
select BSP_I2C2_TX_USING_DMA
default n
config BSP_USING_HARD_I2C3
bool "Enable I2C3 BUS"
default n
config BSP_I2C3_TX_USING_DMA
bool "Enable I2C3 TX DMA"
depends on BSP_USING_HARD_I2C3
default n
config BSP_I2C3_RX_USING_DMA
bool "Enable I2C3 RX DMA"
depends on BSP_USING_HARD_I2C3
select BSP_I2C3_TX_USING_DMA
default n
endif
menuconfig BSP_USING_ADC
bool "Enable ADC"
default n

54
bsp/at32/at32f407-start/board/src/at32_msp.c
View File

@ -131,6 +131,60 @@ void at32_msp_spi_init(void *instance)
}
#endif /* BSP_USING_SPI */
#ifdef BSP_USING_HARD_I2C
void at32_msp_i2c_init(void *instance)
{
gpio_init_type gpio_init_struct;
i2c_type *i2c_x = (i2c_type *)instance;
gpio_default_para_init(&gpio_init_struct);
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
#ifdef BSP_USING_HARD_I2C1
if(I2C1 == i2c_x)
{
crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7;
gpio_init(GPIOB, &gpio_init_struct);
}
#endif
#ifdef BSP_USING_HARD_I2C2
if(I2C2 == i2c_x)
{
crm_periph_clock_enable(CRM_I2C2_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init_struct.gpio_pins = GPIO_PINS_10 | GPIO_PINS_11;
gpio_init(GPIOB, &gpio_init_struct);
}
#endif
#ifdef BSP_USING_HARD_I2C3
if(I2C3 == i2c_x)
{
crm_periph_clock_enable(CRM_I2C3_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE);
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init_struct.gpio_pins = GPIO_PINS_8;
gpio_init(GPIOA, &gpio_init_struct);
gpio_init_struct.gpio_pins = GPIO_PINS_9;
gpio_init(GPIOC, &gpio_init_struct);
}
#endif
/* add others */
}
#endif /* BSP_USING_HARD_I2C */
#ifdef BSP_USING_SDIO
void at32_msp_sdio_init(void *instance)
{

1
bsp/at32/at32f413-start/README.md
View File

@ -41,6 +41,7 @@ AT32F413-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以
| UART | 支持 | USART1/2/3 |
| GPIO | 支持 | PA0...PF5 |
| IIC | 支持 | GPIO模拟I2C |
| HWIIC | 支持 | I2C1/2 |
| SPI | 支持 | SPI1/2 |
| ADC | 支持 | ADC1/2 |
| PWM | 支持 | TMR1/2 |

36
bsp/at32/at32f413-start/board/Kconfig
View File

@ -253,6 +253,42 @@ menu "On-chip Peripheral Drivers"
endif
endif
menuconfig BSP_USING_HARD_I2C
bool "Enable I2C BUS (hardware driver)"
default n
select RT_USING_I2C
if BSP_USING_HARD_I2C
config BSP_USING_HARD_I2C1
bool "Enable I2C1 BUS"
default n
config BSP_I2C1_TX_USING_DMA
bool "Enable I2C1 TX DMA"
depends on BSP_USING_HARD_I2C1
default n
config BSP_I2C1_RX_USING_DMA
bool "Enable I2C1 RX DMA"
depends on BSP_USING_HARD_I2C1
select BSP_I2C1_TX_USING_DMA
default n
config BSP_USING_HARD_I2C2
bool "Enable I2C2 BUS"
default n
config BSP_I2C2_TX_USING_DMA
bool "Enable I2C2 TX DMA"
depends on BSP_USING_HARD_I2C2
default n
config BSP_I2C2_RX_USING_DMA
bool "Enable I2C2 RX DMA"
depends on BSP_USING_HARD_I2C2
select BSP_I2C2_TX_USING_DMA
default n
endif
menuconfig BSP_USING_ADC
bool "Enable ADC"
default n

38
bsp/at32/at32f413-start/board/src/at32_msp.c
View File

@ -129,6 +129,44 @@ void at32_msp_spi_init(void *instance)
}
#endif /* BSP_USING_SPI */
#ifdef BSP_USING_HARD_I2C
void at32_msp_i2c_init(void *instance)
{
gpio_init_type gpio_init_struct;
i2c_type *i2c_x = (i2c_type *)instance;
gpio_default_para_init(&gpio_init_struct);
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
#ifdef BSP_USING_HARD_I2C1
if(I2C1 == i2c_x)
{
crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7;
gpio_init(GPIOB, &gpio_init_struct);
}
#endif
#ifdef BSP_USING_HARD_I2C2
if(I2C2 == i2c_x)
{
crm_periph_clock_enable(CRM_I2C2_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init_struct.gpio_pins = GPIO_PINS_10 | GPIO_PINS_11;
gpio_init(GPIOB, &gpio_init_struct);
}
#endif
/* add others */
}
#endif /* BSP_USING_HARD_I2C */
#ifdef BSP_USING_SDIO
void at32_msp_sdio_init(void *instance)
{

1
bsp/at32/at32f415-start/README.md
View File

@ -41,6 +41,7 @@ AT32F415-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以
| UART | 支持 | USART1/2/3 |
| GPIO | 支持 | PA0...PF5 |
| IIC | 支持 | GPIO模拟I2C |
| HWIIC | 支持 | I2C1/2 |
| SPI | 支持 | SPI1/2 |
| ADC | 支持 | ADC1 |
| PWM | 支持 | TMR1/2 |

36
bsp/at32/at32f415-start/board/Kconfig
View File

@ -268,6 +268,42 @@ menu "On-chip Peripheral Drivers"
endif
endif
menuconfig BSP_USING_HARD_I2C
bool "Enable I2C BUS (hardware driver)"
default n
select RT_USING_I2C
if BSP_USING_HARD_I2C
config BSP_USING_HARD_I2C1
bool "Enable I2C1 BUS"
default n
config BSP_I2C1_TX_USING_DMA
bool "Enable I2C1 TX DMA"
depends on BSP_USING_HARD_I2C1
default n
config BSP_I2C1_RX_USING_DMA
bool "Enable I2C1 RX DMA"
depends on BSP_USING_HARD_I2C1
select BSP_I2C1_TX_USING_DMA
default n
config BSP_USING_HARD_I2C2
bool "Enable I2C2 BUS"
default n
config BSP_I2C2_TX_USING_DMA
bool "Enable I2C2 TX DMA"
depends on BSP_USING_HARD_I2C2
default n
config BSP_I2C2_RX_USING_DMA
bool "Enable I2C2 RX DMA"
depends on BSP_USING_HARD_I2C2
select BSP_I2C2_TX_USING_DMA
default n
endif
menuconfig BSP_USING_ADC
bool "Enable ADC"
default n

38
bsp/at32/at32f415-start/board/src/at32_msp.c
View File

@ -129,6 +129,44 @@ void at32_msp_spi_init(void *instance)
}
#endif /* BSP_USING_SPI */
#ifdef BSP_USING_HARD_I2C
void at32_msp_i2c_init(void *instance)
{
gpio_init_type gpio_init_struct;
i2c_type *i2c_x = (i2c_type *)instance;
gpio_default_para_init(&gpio_init_struct);
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
#ifdef BSP_USING_HARD_I2C1
if(I2C1 == i2c_x)
{
crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7;
gpio_init(GPIOB, &gpio_init_struct);
}
#endif
#ifdef BSP_USING_HARD_I2C2
if(I2C2 == i2c_x)
{
crm_periph_clock_enable(CRM_I2C2_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init_struct.gpio_pins = GPIO_PINS_10 | GPIO_PINS_11;
gpio_init(GPIOB, &gpio_init_struct);
}
#endif
/* add others */
}
#endif /* BSP_USING_HARD_I2C */
#ifdef BSP_USING_SDIO
void at32_msp_sdio_init(void *instance)
{

1
bsp/at32/at32f421-start/README.md
View File

@ -41,6 +41,7 @@ AT32F421-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以
| UART | 支持 | USART1/2 |
| GPIO | 支持 | PA0...PF7 |
| IIC | 支持 | GPIO模拟I2C |
| HWIIC | 支持 | I2C1/2 |
| SPI | 支持 | SPI1/2 |
| ADC | 支持 | ADC1 |
| PWM | 支持 | TMR1 |

36
bsp/at32/at32f421-start/board/Kconfig
View File

@ -203,6 +203,42 @@ menu "On-chip Peripheral Drivers"
endif
endif
menuconfig BSP_USING_HARD_I2C
bool "Enable I2C BUS (hardware driver)"
default n
select RT_USING_I2C
if BSP_USING_HARD_I2C
config BSP_USING_HARD_I2C1
bool "Enable I2C1 BUS"
default n
config BSP_I2C1_TX_USING_DMA
bool "Enable I2C1 TX DMA"
depends on BSP_USING_HARD_I2C1
default n
config BSP_I2C1_RX_USING_DMA
bool "Enable I2C1 RX DMA"
depends on BSP_USING_HARD_I2C1
select BSP_I2C1_TX_USING_DMA
default n
config BSP_USING_HARD_I2C2
bool "Enable I2C2 BUS"
default n
config BSP_I2C2_TX_USING_DMA
bool "Enable I2C2 TX DMA"
depends on BSP_USING_HARD_I2C2
default n
config BSP_I2C2_RX_USING_DMA
bool "Enable I2C2 RX DMA"
depends on BSP_USING_HARD_I2C2
select BSP_I2C2_TX_USING_DMA
default n
endif
menuconfig BSP_USING_ADC
bool "Enable ADC"
default n

1
bsp/at32/at32f421-start/board/inc/at32_msp.h
View File

@ -16,5 +16,6 @@ void at32_msp_spi_init(void *instance);
void at32_msp_tmr_init(void *instance);
void at32_msp_adc_init(void *instance);
void at32_msp_hwtmr_init(void *instance);
void at32_msp_i2c_init(void *instance);
#endif /* __AT32_MSP_H__ */

44
bsp/at32/at32f421-start/board/src/at32_msp.c
View File

@ -116,6 +116,50 @@ void at32_msp_spi_init(void *instance)
}
#endif /* BSP_USING_SPI */
#ifdef BSP_USING_HARD_I2C
void at32_msp_i2c_init(void *instance)
{
gpio_init_type gpio_init_struct;
i2c_type *i2c_x = (i2c_type *)instance;
gpio_default_para_init(&gpio_init_struct);
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
#ifdef BSP_USING_HARD_I2C1
if(I2C1 == i2c_x)
{
crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7;
gpio_init(GPIOB, &gpio_init_struct);
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE6, GPIO_MUX_1);
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE7, GPIO_MUX_1);
}
#endif
#ifdef BSP_USING_HARD_I2C2
if(I2C2 == i2c_x)
{
crm_periph_clock_enable(CRM_I2C2_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init_struct.gpio_pins = GPIO_PINS_10 | GPIO_PINS_11;
gpio_init(GPIOB, &gpio_init_struct);
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE10, GPIO_MUX_1);
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE11, GPIO_MUX_1);
}
#endif
/* add others */
}
#endif /* BSP_USING_HARD_I2C */
#ifdef BSP_USING_PWM
void at32_msp_tmr_init(void *instance)
{

1
bsp/at32/at32f423-start/README.md
View File

@ -41,6 +41,7 @@ AT32F423-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以
| UART | 支持 | USART1/2/3 |
| GPIO | 支持 | PA0...PF10 |
| IIC | 支持 | GPIO模拟I2C |
| HWIIC | 支持 | I2C1/2/3 |
| SPI | 支持 | SPI1/2 |
| ADC | 支持 | ADC1 |
| DAC | 支持 | DAC1 |

51
bsp/at32/at32f423-start/board/Kconfig
View File

@ -277,6 +277,57 @@ menu "On-chip Peripheral Drivers"
endif
endif
menuconfig BSP_USING_HARD_I2C
bool "Enable I2C BUS (hardware driver)"
default n
select RT_USING_I2C
if BSP_USING_HARD_I2C
config BSP_USING_HARD_I2C1
bool "Enable I2C1 BUS"
default n
config BSP_I2C1_TX_USING_DMA
bool "Enable I2C1 TX DMA"
depends on BSP_USING_HARD_I2C1
default n
config BSP_I2C1_RX_USING_DMA
bool "Enable I2C1 RX DMA"
depends on BSP_USING_HARD_I2C1
select BSP_I2C1_TX_USING_DMA
default n
config BSP_USING_HARD_I2C2
bool "Enable I2C2 BUS"
default n
config BSP_I2C2_TX_USING_DMA
bool "Enable I2C2 TX DMA"
depends on BSP_USING_HARD_I2C2
default n
config BSP_I2C2_RX_USING_DMA
bool "Enable I2C2 RX DMA"
depends on BSP_USING_HARD_I2C2
select BSP_I2C2_TX_USING_DMA
default n
config BSP_USING_HARD_I2C3
bool "Enable I2C3 BUS"
default n
config BSP_I2C3_TX_USING_DMA
bool "Enable I2C3 TX DMA"
depends on BSP_USING_HARD_I2C3
default n
config BSP_I2C3_RX_USING_DMA
bool "Enable I2C3 RX DMA"
depends on BSP_USING_HARD_I2C3
select BSP_I2C3_TX_USING_DMA
default n
endif
menuconfig BSP_USING_ADC
bool "Enable ADC"
default n

1
bsp/at32/at32f423-start/board/inc/at32_msp.h
View File

@ -19,5 +19,6 @@ void at32_msp_hwtmr_init(void *instance);
void at32_msp_can_init(void *instance);
void at32_msp_usb_init(void *instance);
void at32_msp_dac_init(void *instance);
void at32_msp_i2c_init(void *instance);
#endif /* __AT32_MSP_H__ */

63
bsp/at32/at32f423-start/board/src/at32_msp.c
View File

@ -135,6 +135,69 @@ void at32_msp_spi_init(void *instance)
}
#endif /* BSP_USING_SPI */
#ifdef BSP_USING_HARD_I2C
void at32_msp_i2c_init(void *instance)
{
gpio_init_type gpio_init_struct;
i2c_type *i2c_x = (i2c_type *)instance;
gpio_default_para_init(&gpio_init_struct);
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
#ifdef BSP_USING_HARD_I2C1
if(I2C1 == i2c_x)
{
crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7;
gpio_init(GPIOB, &gpio_init_struct);
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE6, GPIO_MUX_4);
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE7, GPIO_MUX_4);
}
#endif
#ifdef BSP_USING_HARD_I2C2
if(I2C2 == i2c_x)
{
crm_periph_clock_enable(CRM_I2C2_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init_struct.gpio_pins = GPIO_PINS_10 | GPIO_PINS_11;
gpio_init(GPIOB, &gpio_init_struct);
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE10, GPIO_MUX_4);
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE11, GPIO_MUX_4);
}
#endif
#ifdef BSP_USING_HARD_I2C3
if(I2C3 == i2c_x)
{
crm_periph_clock_enable(CRM_I2C3_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE);
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init_struct.gpio_pins = GPIO_PINS_8;
gpio_init(GPIOA, &gpio_init_struct);
gpio_init_struct.gpio_pins = GPIO_PINS_9;
gpio_init(GPIOC, &gpio_init_struct);
gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE8, GPIO_MUX_4);
gpio_pin_mux_config(GPIOC, GPIO_PINS_SOURCE9, GPIO_MUX_4);
}
#endif
/* add others */
}
#endif /* BSP_USING_HARD_I2C */
#ifdef BSP_USING_PWM
void at32_msp_tmr_init(void *instance)
{

1
bsp/at32/at32f425-start/README.md
View File

@ -41,6 +41,7 @@ AT32F425-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以
| UART | 支持 | USART1/2/3 |
| GPIO | 支持 | PA0...PF7 |
| IIC | 支持 | GPIO模拟I2C |
| HWIIC | 支持 | I2C1/2 |
| SPI | 支持 | SPI1/2 |
| ADC | 支持 | ADC1 |
| PWM | 支持 | TMR1/2 |

36
bsp/at32/at32f425-start/board/Kconfig
View File

@ -277,6 +277,42 @@ menu "On-chip Peripheral Drivers"
endif
endif
menuconfig BSP_USING_HARD_I2C
bool "Enable I2C BUS (hardware driver)"
default n
select RT_USING_I2C
if BSP_USING_HARD_I2C
config BSP_USING_HARD_I2C1
bool "Enable I2C1 BUS"
default n
config BSP_I2C1_TX_USING_DMA
bool "Enable I2C1 TX DMA"
depends on BSP_USING_HARD_I2C1
default n
config BSP_I2C1_RX_USING_DMA
bool "Enable I2C1 RX DMA"
depends on BSP_USING_HARD_I2C1
select BSP_I2C1_TX_USING_DMA
default n
config BSP_USING_HARD_I2C2
bool "Enable I2C2 BUS"
default n
config BSP_I2C2_TX_USING_DMA
bool "Enable I2C2 TX DMA"
depends on BSP_USING_HARD_I2C2
default n
config BSP_I2C2_RX_USING_DMA
bool "Enable I2C2 RX DMA"
depends on BSP_USING_HARD_I2C2
select BSP_I2C2_TX_USING_DMA
default n
endif
menuconfig BSP_USING_ADC
bool "Enable ADC"
default n

1
bsp/at32/at32f425-start/board/inc/at32_msp.h
View File

@ -18,5 +18,6 @@ void at32_msp_adc_init(void *instance);
void at32_msp_hwtmr_init(void *instance);
void at32_msp_can_init(void *instance);
void at32_msp_usb_init(void *instance);
void at32_msp_i2c_init(void *instance);
#endif /* __AT32_MSP_H__ */

44
bsp/at32/at32f425-start/board/src/at32_msp.c
View File

@ -135,6 +135,50 @@ void at32_msp_spi_init(void *instance)
}
#endif /* BSP_USING_SPI */
#ifdef BSP_USING_HARD_I2C
void at32_msp_i2c_init(void *instance)
{
gpio_init_type gpio_init_struct;
i2c_type *i2c_x = (i2c_type *)instance;
gpio_default_para_init(&gpio_init_struct);
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
#ifdef BSP_USING_HARD_I2C1
if(I2C1 == i2c_x)
{
crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7;
gpio_init(GPIOB, &gpio_init_struct);
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE6, GPIO_MUX_1);
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE7, GPIO_MUX_1);
}
#endif
#ifdef BSP_USING_HARD_I2C2
if(I2C2 == i2c_x)
{
crm_periph_clock_enable(CRM_I2C2_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init_struct.gpio_pins = GPIO_PINS_10 | GPIO_PINS_11;
gpio_init(GPIOB, &gpio_init_struct);
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE10, GPIO_MUX_1);
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE11, GPIO_MUX_1);
}
#endif
/* add others */
}
#endif /* BSP_USING_HARD_I2C */
#ifdef BSP_USING_PWM
void at32_msp_tmr_init(void *instance)
{

1
bsp/at32/at32f435-start/README.md
View File

@ -41,6 +41,7 @@ AT32F437-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以
| UART | 支持 | USART1/2/3 |
| GPIO | 支持 | PA0...PH7 |
| IIC | 支持 | GPIO模拟I2C |
| HWIIC | 支持 | I2C1/2/3 |
| SPI | 支持 | SPI1/2 |
| ADC | 支持 | ADC1/2 |
| DAC | 支持 | DAC1 |

51
bsp/at32/at32f435-start/board/Kconfig
View File

@ -314,6 +314,57 @@ menu "On-chip Peripheral Drivers"
endif
endif
menuconfig BSP_USING_HARD_I2C
bool "Enable I2C BUS (hardware driver)"
default n
select RT_USING_I2C
if BSP_USING_HARD_I2C
config BSP_USING_HARD_I2C1
bool "Enable I2C1 BUS"
default n
config BSP_I2C1_TX_USING_DMA
bool "Enable I2C1 TX DMA"
depends on BSP_USING_HARD_I2C1
default n
config BSP_I2C1_RX_USING_DMA
bool "Enable I2C1 RX DMA"
depends on BSP_USING_HARD_I2C1
select BSP_I2C1_TX_USING_DMA
default n
config BSP_USING_HARD_I2C2
bool "Enable I2C2 BUS"
default n
config BSP_I2C2_TX_USING_DMA
bool "Enable I2C2 TX DMA"
depends on BSP_USING_HARD_I2C2
default n
config BSP_I2C2_RX_USING_DMA
bool "Enable I2C2 RX DMA"
depends on BSP_USING_HARD_I2C2
select BSP_I2C2_TX_USING_DMA
default n
config BSP_USING_HARD_I2C3
bool "Enable I2C3 BUS"
default n
config BSP_I2C3_TX_USING_DMA
bool "Enable I2C3 TX DMA"
depends on BSP_USING_HARD_I2C3
default n
config BSP_I2C3_RX_USING_DMA
bool "Enable I2C3 RX DMA"
depends on BSP_USING_HARD_I2C3
select BSP_I2C3_TX_USING_DMA
default n
endif
menuconfig BSP_USING_ADC
bool "Enable ADC"
default n

63
bsp/at32/at32f435-start/board/src/at32_msp.c
View File

@ -126,6 +126,69 @@ void at32_msp_spi_init(void *instance)
}
#endif /* BSP_USING_SPI */
#ifdef BSP_USING_HARD_I2C
void at32_msp_i2c_init(void *instance)
{
gpio_init_type gpio_init_struct;
i2c_type *i2c_x = (i2c_type *)instance;
gpio_default_para_init(&gpio_init_struct);
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
#ifdef BSP_USING_HARD_I2C1
if(I2C1 == i2c_x)
{
crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7;
gpio_init(GPIOB, &gpio_init_struct);
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE6, GPIO_MUX_4);
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE7, GPIO_MUX_4);
}
#endif
#ifdef BSP_USING_HARD_I2C2
if(I2C2 == i2c_x)
{
crm_periph_clock_enable(CRM_I2C2_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init_struct.gpio_pins = GPIO_PINS_10 | GPIO_PINS_11;
gpio_init(GPIOB, &gpio_init_struct);
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE10, GPIO_MUX_4);
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE11, GPIO_MUX_4);
}
#endif
#ifdef BSP_USING_HARD_I2C3
if(I2C3 == i2c_x)
{
crm_periph_clock_enable(CRM_I2C3_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE);
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init_struct.gpio_pins = GPIO_PINS_8;
gpio_init(GPIOA, &gpio_init_struct);
gpio_init_struct.gpio_pins = GPIO_PINS_9;
gpio_init(GPIOC, &gpio_init_struct);
gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE8, GPIO_MUX_4);
gpio_pin_mux_config(GPIOC, GPIO_PINS_SOURCE9, GPIO_MUX_4);
}
#endif
/* add others */
}
#endif /* BSP_USING_HARD_I2C */
#ifdef BSP_USING_SDIO
void at32_msp_sdio_init(void *instance)
{

1
bsp/at32/at32f437-start/README.md
View File

@ -41,6 +41,7 @@ AT32F437-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以
| UART | 支持 | USART1/2/3 |
| GPIO | 支持 | PA0...PH7 |
| IIC | 支持 | GPIO模拟I2C |
| HWIIC | 支持 | I2C1/2/3 |
| SPI | 支持 | SPI1/2 |
| ADC | 支持 | ADC1/2 |
| DAC | 支持 | DAC1 |

51
bsp/at32/at32f437-start/board/Kconfig
View File

@ -331,6 +331,57 @@ menu "On-chip Peripheral Drivers"
endif
endif
menuconfig BSP_USING_HARD_I2C
bool "Enable I2C BUS (hardware driver)"
default n
select RT_USING_I2C
if BSP_USING_HARD_I2C
config BSP_USING_HARD_I2C1
bool "Enable I2C1 BUS"
default n
config BSP_I2C1_TX_USING_DMA
bool "Enable I2C1 TX DMA"
depends on BSP_USING_HARD_I2C1
default n
config BSP_I2C1_RX_USING_DMA
bool "Enable I2C1 RX DMA"
depends on BSP_USING_HARD_I2C1
select BSP_I2C1_TX_USING_DMA
default n
config BSP_USING_HARD_I2C2
bool "Enable I2C2 BUS"
default n
config BSP_I2C2_TX_USING_DMA
bool "Enable I2C2 TX DMA"
depends on BSP_USING_HARD_I2C2
default n
config BSP_I2C2_RX_USING_DMA
bool "Enable I2C2 RX DMA"
depends on BSP_USING_HARD_I2C2
select BSP_I2C2_TX_USING_DMA
default n
config BSP_USING_HARD_I2C3
bool "Enable I2C3 BUS"
default n
config BSP_I2C3_TX_USING_DMA
bool "Enable I2C3 TX DMA"
depends on BSP_USING_HARD_I2C3
default n
config BSP_I2C3_RX_USING_DMA
bool "Enable I2C3 RX DMA"
depends on BSP_USING_HARD_I2C3
select BSP_I2C3_TX_USING_DMA
default n
endif
menuconfig BSP_USING_ADC
bool "Enable ADC"
default n

63
bsp/at32/at32f437-start/board/src/at32_msp.c
View File

@ -127,6 +127,69 @@ void at32_msp_spi_init(void *instance)
}
#endif /* BSP_USING_SPI */
#ifdef BSP_USING_HARD_I2C
void at32_msp_i2c_init(void *instance)
{
gpio_init_type gpio_init_struct;
i2c_type *i2c_x = (i2c_type *)instance;
gpio_default_para_init(&gpio_init_struct);
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
#ifdef BSP_USING_HARD_I2C1
if(I2C1 == i2c_x)
{
crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7;
gpio_init(GPIOB, &gpio_init_struct);
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE6, GPIO_MUX_4);
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE7, GPIO_MUX_4);
}
#endif
#ifdef BSP_USING_HARD_I2C2
if(I2C2 == i2c_x)
{
crm_periph_clock_enable(CRM_I2C2_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init_struct.gpio_pins = GPIO_PINS_10 | GPIO_PINS_11;
gpio_init(GPIOB, &gpio_init_struct);
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE10, GPIO_MUX_4);
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE11, GPIO_MUX_4);
}
#endif
#ifdef BSP_USING_HARD_I2C3
if(I2C3 == i2c_x)
{
crm_periph_clock_enable(CRM_I2C3_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE);
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init_struct.gpio_pins = GPIO_PINS_8;
gpio_init(GPIOA, &gpio_init_struct);
gpio_init_struct.gpio_pins = GPIO_PINS_9;
gpio_init(GPIOC, &gpio_init_struct);
gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE8, GPIO_MUX_4);
gpio_pin_mux_config(GPIOC, GPIO_PINS_SOURCE9, GPIO_MUX_4);
}
#endif
/* add others */
}
#endif /* BSP_USING_HARD_I2C */
#ifdef BSP_USING_SDIO
void at32_msp_sdio_init(void *instance)
{

15
bsp/at32/libraries/.ignore_format.yml Normal file
View File

@ -0,0 +1,15 @@
# files format check exclude path, please follow the instructions below to modify;
# If you need to exclude an entire folder, add the folder path in dir_path;
# If you need to exclude a file, add the path to the file in file_path.
dir_path:
- AT32A403A_Firmware_Library
- AT32A423_Firmware_Library
- AT32F402_405_Firmware_Library
- AT32F403A_407_Firmware_Library
- AT32F413_Firmware_Library
- AT32F415_Firmware_Library
- AT32F421_Firmware_Library
- AT32F423_Firmware_Library
- AT32F425_Firmware_Library
- AT32F435_437_Firmware_Library

44
bsp/at32/libraries/AT32F402_405_Firmware_Library/cmsis/cm4/device_support/system_at32f402_405.c
View File

@ -179,6 +179,50 @@ void system_core_clock_update(void)
system_core_clock = system_core_clock >> div_value;
}
/**
* @brief reduce power consumption initialize
* If OTGHS is not used, call this function to reduce power consumption.
* PLL or HEXT should be enabled when calling this function.
*
* If OTGHS is required, initialize OTGHS to reduce power consumption,
* without the need to call this function.
* @param none
* @retval none
*/
void reduce_power_consumption(void)
{
volatile uint32_t delay = 0x34BC0;
if(CRM->ctrl_bit.hextstbl)
{
*(__IO uint32_t *)0x40023878 = 0x00;
}
else if(CRM->ctrl_bit.pllstbl == SET)
{
CRM->pllcfg_bit.plluen = TRUE;
while(CRM->ctrl_bit.pllstbl != SET || CRM->ctrl_bit.pllustbl != SET);
*(__IO uint32_t *)0x40023878 = 0x10;
}
else
{
/* the pll or hext need to be enable */
return;
}
CRM->ahben1 |= 1 << 29;
*(__IO uint32_t *)0x40040038 = 0x210000;
*(__IO uint32_t *)0x4004000C |= 0x40000000;
*(__IO uint32_t *)0x40040804 &= ~0x2;
while(delay --)
{
if(*(__IO uint32_t *)0x40040808 & 0x1)
break;
}
*(__IO uint32_t *)0x40040038 |= 0x400000;
*(__IO uint32_t *)0x40040E00 |= 0x1;
*(__IO uint32_t *)0x40040038 &= ~0x10000;
*(__IO uint32_t *)0x40023878 = 0x0;
return;
}
/**
* @}
*/

1
bsp/at32/libraries/AT32F402_405_Firmware_Library/cmsis/cm4/device_support/system_at32f402_405.h
View File

@ -52,6 +52,7 @@ extern unsigned int system_core_clock; /*!< system clock frequency (core clock)
extern void SystemInit(void);
extern void system_core_clock_update(void);
extern void reduce_power_consumption(void);
/**
* @}

1
bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_acc.h
View File

@ -178,6 +178,7 @@ uint16_t acc_read_c1(void);
uint16_t acc_read_c2(void);
uint16_t acc_read_c3(void);
flag_status acc_flag_get(uint16_t acc_flag);
flag_status acc_interrupt_flag_get(uint16_t acc_flag);
void acc_flag_clear(uint16_t acc_flag);
/**

7
bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_adc.h
View File

@ -1,7 +1,7 @@
/**
**************************************************************************
* @file at32f425_adc.h
* @brief at32f425 adc header file
* @file at32f402_405_adc.h
* @brief at32f402_405 adc header file
**************************************************************************
* Copyright notice & Disclaimer
*
@ -34,7 +34,7 @@ extern "C" {
/* Includes ------------------------------------------------------------------*/
#include "at32f402_405.h"
/** @addtogroup AT32F425_periph_driver
/** @addtogroup AT32F402_405_periph_driver
* @{
*/
@ -688,6 +688,7 @@ flag_status adc_preempt_software_trigger_status_get(adc_type *adc_x);
uint16_t adc_ordinary_conversion_data_get(adc_type *adc_x);
uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel);
flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag);
flag_status adc_interrupt_flag_get(adc_type *adc_x, uint8_t adc_flag);
void adc_flag_clear(adc_type *adc_x, uint32_t adc_flag);
void adc_ordinary_oversample_enable(adc_type *adc_x, confirm_state new_state);
void adc_preempt_oversample_enable(adc_type *adc_x, confirm_state new_state);

1
bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_can.h
View File

@ -1018,6 +1018,7 @@ can_error_record_type can_error_type_record_get(can_type* can_x);
uint8_t can_receive_error_counter_get(can_type* can_x);
uint8_t can_transmit_error_counter_get(can_type* can_x);
void can_interrupt_enable(can_type* can_x, uint32_t can_int, confirm_state new_state);
flag_status can_interrupt_flag_get(can_type* can_x, uint32_t can_flag);
flag_status can_flag_get(can_type* can_x, uint32_t can_flag);
void can_flag_clear(can_type* can_x, uint32_t can_flag);

4
bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_crm.h
View File

@ -461,8 +461,7 @@ typedef enum
CRM_CLKOUT_ADC = 0x11, /*!< output adcclk to clkout pin */
CRM_CLKOUT_HICK = 0x12, /*!< output high speed internal clock to clkout pin */
CRM_CLKOUT_LICK = 0x13, /*!< output low speed internal clock to clkout pin */
CRM_CLKOUT_LEXT = 0x14, /*!< output low speed external crystal to clkout pin */
CRM_CLKOUT_USBHS = 0x15 /*!< output usbhsclk to clkout pin */
CRM_CLKOUT_LEXT = 0x14 /*!< output low speed external crystal to clkout pin */
} crm_clkout_select_type;
/**
@ -1179,6 +1178,7 @@ void crm_reset(void);
void crm_lext_bypass(confirm_state new_state);
void crm_hext_bypass(confirm_state new_state);
flag_status crm_flag_get(uint32_t flag);
flag_status crm_interrupt_flag_get(uint32_t flag);
error_status crm_hext_stable_wait(void);
void crm_hick_clock_trimming_set(uint8_t trim_value);
void crm_hick_clock_calibration_set(uint8_t cali_value);

24
bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_debug.h
View File

@ -113,6 +113,7 @@ typedef struct
__IO uint32_t reserved1 : 29;/* [31:3] */
} ctrl_bit;
};
/**
* @brief debug apb1 frz register, offset:0x08
*/
@ -145,8 +146,9 @@ typedef struct
__IO uint32_t reserved6 : 3;/* [31:29] */
} apb1_frz_bit;
};
/**
* @brief debug apb2 frz register, offset:0x0c
* @brief debug apb2 frz register, offset:0x0C
*/
union
{
@ -163,6 +165,26 @@ typedef struct
} apb2_frz_bit;
};
/**
* @brief debug reserved1 register, offset:0x10~0x1C
*/
__IO uint32_t reserved1[4];
/**
* @brief debug ser id register, offset:0x20
*/
union
{
__IO uint32_t ser_id;
struct
{
__IO uint32_t rev_id : 3;/* [2:0] */
__IO uint32_t reserved1 : 5;/* [7:3] */
__IO uint32_t ser_id : 8;/* [15:8] */
__IO uint32_t reserved2 : 16;/* [31:16] */
} ser_id_bit;
};
} debug_type;
/**

3
bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_dma.h
View File

@ -727,6 +727,7 @@ uint16_t dma_data_number_get(dma_channel_type *dmax_channely);
void dma_interrupt_enable(dma_channel_type *dmax_channely, uint32_t dma_int, confirm_state new_state);
void dma_channel_enable(dma_channel_type *dmax_channely, confirm_state new_state);
flag_status dma_flag_get(uint32_t dmax_flag);
flag_status dma_interrupt_flag_get(uint32_t dmax_flag);
void dma_flag_clear(uint32_t dmax_flag);
void dma_default_para_init(dma_init_type *dma_init_struct);
void dma_init(dma_channel_type *dmax_channely, dma_init_type *dma_init_struct);
@ -742,8 +743,10 @@ void dmamux_generator_config(dmamux_generator_type *dmamux_gen_x, dmamux_gen_ini
void dmamux_sync_interrupt_enable(dmamux_channel_type *dmamux_channelx, confirm_state new_state);
void dmamux_generator_interrupt_enable(dmamux_generator_type *dmamux_gen_x, confirm_state new_state);
flag_status dmamux_sync_flag_get(dma_type *dma_x, uint32_t flag);
flag_status dmamux_sync_interrupt_flag_get(dma_type *dma_x, uint32_t flag);
void dmamux_sync_flag_clear(dma_type *dma_x, uint32_t flag);
flag_status dmamux_generator_flag_get(dma_type *dma_x, uint32_t flag);
flag_status dmamux_generator_interrupt_flag_get(dma_type *dma_x, uint32_t flag);
void dmamux_generator_flag_clear(dma_type *dma_x, uint32_t flag);
/**

1
bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_ertc.h
View File

@ -1174,6 +1174,7 @@ void ertc_tamper_enable(ertc_tamper_select_type tamper_x, confirm_state new_stat
void ertc_interrupt_enable(uint32_t source, confirm_state new_state);
flag_status ertc_interrupt_get(uint32_t source);
flag_status ertc_flag_get(uint32_t flag);
flag_status ertc_interrupt_flag_get(uint32_t flag);
void ertc_flag_clear(uint32_t flag);
void ertc_bpr_data_write(ertc_dt_type dt, uint32_t data);
uint32_t ertc_bpr_data_read(ertc_dt_type dt);

1
bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_exint.h
View File

@ -209,6 +209,7 @@ void exint_default_para_init(exint_init_type *exint_struct);
void exint_init(exint_init_type *exint_struct);
void exint_flag_clear(uint32_t exint_line);
flag_status exint_flag_get(uint32_t exint_line);
flag_status exint_interrupt_flag_get(uint32_t exint_line);
void exint_software_interrupt_event_generate(uint32_t exint_line);
void exint_interrupt_enable(uint32_t exint_line, confirm_state new_state);
void exint_event_enable(uint32_t exint_line, confirm_state new_state);

13
bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_i2c.h
View File

@ -155,12 +155,12 @@ typedef enum
{
I2C_ADDR2_NOMASK = 0x00, /*!< compare bit [7:1] */
I2C_ADDR2_MASK01 = 0x01, /*!< only compare bit [7:2] */
I2C_ADDR2_MASK02 = 0x02, /*!< only compare bit [7:2] */
I2C_ADDR2_MASK03 = 0x03, /*!< only compare bit [7:3] */
I2C_ADDR2_MASK04 = 0x04, /*!< only compare bit [7:4] */
I2C_ADDR2_MASK05 = 0x05, /*!< only compare bit [7:5] */
I2C_ADDR2_MASK06 = 0x06, /*!< only compare bit [7:6] */
I2C_ADDR2_MASK07 = 0x07 /*!< only compare bit [7] */
I2C_ADDR2_MASK02 = 0x02, /*!< only compare bit [7:3] */
I2C_ADDR2_MASK03 = 0x03, /*!< only compare bit [7:4] */
I2C_ADDR2_MASK04 = 0x04, /*!< only compare bit [7:5] */
I2C_ADDR2_MASK05 = 0x05, /*!< only compare bit [7:6] */
I2C_ADDR2_MASK06 = 0x06, /*!< only compare bit [7] */
I2C_ADDR2_MASK07 = 0x07 /*!< response all addresses other than those reserved for i2c */
} i2c_addr2_mask_type;
/**
@ -456,6 +456,7 @@ void i2c_stop_generate(i2c_type *i2c_x);
void i2c_data_send(i2c_type *i2c_x, uint8_t data);
uint8_t i2c_data_receive(i2c_type *i2c_x);
flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag);
flag_status i2c_interrupt_flag_get(i2c_type *i2c_x, uint32_t flag);
void i2c_flag_clear(i2c_type *i2c_x, uint32_t flag);
/**

3
bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_pwc.h
View File

@ -126,8 +126,7 @@ typedef enum
typedef enum
{
PWC_REGULATOR_ON = 0x00, /*!< voltage regulator state on when deepsleep mode */
PWC_REGULATOR_LOW_POWER = 0x01, /*!< voltage regulator state low power when deepsleep mode */
PWC_REGULATOR_EXTRA_LOW_POWER = 0x02 /*!< voltage regulator state extra low power when deepsleep mode */
PWC_REGULATOR_EXTRA_LOW_POWER = 0x01 /*!< voltage regulator state extra low power when deepsleep mode */
} pwc_regulator_type ;
/**

33
bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_qspi.h
View File

@ -121,11 +121,11 @@ typedef enum
typedef enum
{
QSPI_CLK_DIV_2 = 0x00, /*!< qspi clk divide by 2 */
QSPI_CLK_DIV_3 = 0x04, /*!< qspi clk divide by 3 */
QSPI_CLK_DIV_4 = 0x01, /*!< qspi clk divide by 4 */
QSPI_CLK_DIV_5 = 0x05, /*!< qspi clk divide by 5 */
QSPI_CLK_DIV_6 = 0x02, /*!< qspi clk divide by 6 */
QSPI_CLK_DIV_8 = 0x03, /*!< qspi clk divide by 8 */
QSPI_CLK_DIV_3 = 0x04, /*!< qspi clk divide by 3 */
QSPI_CLK_DIV_5 = 0x05, /*!< qspi clk divide by 5 */
QSPI_CLK_DIV_10 = 0x06, /*!< qspi clk divide by 10 */
QSPI_CLK_DIV_12 = 0x07 /*!< qspi clk divide by 12 */
} qspi_clk_div_type;
@ -177,7 +177,7 @@ typedef enum
{
QSPI_DMA_FIFO_THOD_WORD08 = 0x00, /*!< qspi dma fifo threshold 8 words */
QSPI_DMA_FIFO_THOD_WORD16 = 0x01, /*!< qspi dma fifo threshold 16 words */
QSPI_DMA_FIFO_THOD_WORD32 = 0x02 /*!< qspi dma fifo threshold 32 words */
QSPI_DMA_FIFO_THOD_WORD24 = 0x02 /*!< qspi dma fifo threshold 24 words */
} qspi_dma_fifo_thod_type;
/**
@ -185,7 +185,7 @@ typedef enum
*/
typedef struct
{
confirm_state pe_mode_enable; /*!< perfornance enhance mode enable */
confirm_state pe_mode_enable; /*!< performance enhance mode enable */
uint8_t pe_mode_operate_code; /*!< performance enhance mode operate code */
uint8_t instruction_code; /*!< instruction code */
qspi_cmd_inslen_type instruction_length; /*!< instruction code length */
@ -458,9 +458,23 @@ typedef struct
};
/**
* @brief qspi reserved register, offset:0x40~4C
* @brief qspi ctrl3 register, offset:0x40
*/
__IO uint32_t reserved2[4];
union
{
__IO uint32_t ctrl3;
struct
{
__IO uint32_t reserved1 : 8; /* [7:0] */
__IO uint32_t ispc : 1; /* [8] */
__IO uint32_t reserved2 : 23;/* [31:9] */
} ctrl3_bit;
};
/**
* @brief qspi reserved register, offset:0x44~4C
*/
__IO uint32_t reserved2[3];
/**
* @brief qspi rev register, offset:0x50
@ -505,13 +519,15 @@ typedef struct
* @{
*/
void qspi_reset(qspi_type* qspi_x);
void qspi_encryption_enable(qspi_type* qspi_x, confirm_state new_state);
void qspi_sck_mode_set( qspi_type* qspi_x, qspi_clk_mode_type new_mode);
void qspi_sck_mode_set(qspi_type* qspi_x, qspi_clk_mode_type new_mode);
void qspi_clk_division_set(qspi_type* qspi_x, qspi_clk_div_type new_clkdiv);
void qspi_xip_cache_bypass_set(qspi_type* qspi_x, confirm_state new_state);
void qspi_interrupt_enable(qspi_type* qspi_x, confirm_state new_state);
flag_status qspi_flag_get(qspi_type* qspi_x, uint32_t flag);
void qspi_flag_clear( qspi_type* qspi_x, uint32_t flag);
flag_status qspi_interrupt_flag_get(qspi_type* qspi_x, uint32_t flag);
void qspi_flag_clear(qspi_type* qspi_x, uint32_t flag);
void qspi_dma_rx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_threshold);
void qspi_dma_tx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_threshold);
void qspi_dma_enable(qspi_type* qspi_x, confirm_state new_state);
@ -525,6 +541,7 @@ uint32_t qspi_word_read(qspi_type* qspi_x);
void qspi_word_write(qspi_type* qspi_x, uint32_t value);
void qspi_half_word_write(qspi_type* qspi_x, uint16_t value);
void qspi_byte_write(qspi_type* qspi_x, uint8_t value);
void qspi_auto_ispc_enable(qspi_type* qspi_x);
/**
* @}
*/

4
bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_scfg.h
View File

@ -55,8 +55,6 @@ extern "C" {
typedef enum
{
SCFG_IR_SOURCE_TMR10 = 0x00, /* infrared signal source select tmr10 */
SCFG_IR_SOURCE_USART1 = 0x01, /* infrared signal source select usart1 */
SCFG_IR_SOURCE_USART2 = 0x02 /* infrared signal source select usart2 */
} scfg_ir_source_type;
/**
@ -277,7 +275,7 @@ void scfg_infrared_config(scfg_ir_source_type source, scfg_ir_polarity_type pola
scfg_mem_map_type scfg_mem_map_get(void);
void scfg_i2s_full_duplex_config(scfg_i2s_type i2s_full_duplex);
void scfg_pvm_lock_enable(confirm_state new_state);
error_status scfg_sram_operr_status_get(void);
flag_status scfg_sram_operr_status_get(void);
void scfg_sram_operr_lock_enable(confirm_state new_state);
void scfg_lockup_enable(confirm_state new_state);
void scfg_exint_line_config(scfg_port_source_type port_source, scfg_pins_source_type pin_source);

1
bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_spi.h
View File

@ -508,6 +508,7 @@ void spi_i2s_dma_receiver_enable(spi_type* spi_x, confirm_state new_state);
void spi_i2s_data_transmit(spi_type* spi_x, uint16_t tx_data);
uint16_t spi_i2s_data_receive(spi_type* spi_x);
flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag);
flag_status spi_i2s_interrupt_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag);
void spi_i2s_flag_clear(spi_type* spi_x, uint32_t spi_i2s_flag);
void i2sf_full_duplex_mode_enable(spi_type* spi_x, confirm_state new_state);
void i2sf_pcm_sample_clock_set(spi_type* spi_x, i2s_pcm_sample_clock_type pcm_sample_clock);

3
bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_tmr.h
View File

@ -444,7 +444,6 @@ typedef struct
*/
typedef struct
{
uint8_t brk_filter_value; /*!< tmr brake filter value */
uint8_t deadtime; /*!< dead-time generator setup */
tmr_brk_polarity_type brk_polarity; /*!< tmr brake polarity */
tmr_wp_level_type wp_level; /*!< write protect configuration */
@ -972,6 +971,7 @@ void tmr_trigger_input_select(tmr_type *tmr_x, sub_tmr_input_sel_type trigger_se
void tmr_sub_sync_mode_set(tmr_type *tmr_x, confirm_state new_state);
void tmr_dma_request_enable(tmr_type *tmr_x, tmr_dma_request_type dma_request, confirm_state new_state);
void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state new_state);
flag_status tmr_interrupt_flag_get(tmr_type *tmr_x, uint32_t tmr_flag);
flag_status tmr_flag_get(tmr_type *tmr_x, uint32_t tmr_flag);
void tmr_flag_clear(tmr_type *tmr_x, uint32_t tmr_flag);
void tmr_event_sw_trigger(tmr_type *tmr_x, tmr_event_trigger_type tmr_event);
@ -993,6 +993,7 @@ void tmr_force_output_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel,
void tmr_dma_control_config(tmr_type *tmr_x, tmr_dma_transfer_length_type dma_length, \
tmr_dma_address_type dma_base_address);
void tmr_brkdt_config(tmr_type *tmr_x, tmr_brkdt_config_type *brkdt_struct);
void tmr_brk_filter_value_set(tmr_type *tmr_x, uint8_t filter_value);
void tmr_iremap_config(tmr_type *tmr_x, tmr_input_remap_type input_remap);
/**

12
bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_usart.h
View File

@ -184,6 +184,15 @@ typedef enum
USART_ID_RELATED_DATA_BIT = 0x01 /*!< usart id bit num related data bits */
} usart_identification_bit_num_type;
/**
* @brief usart de polarity type
*/
typedef enum
{
USART_DE_POLARITY_HIGH = 0x00, /*!< usart de polarity high */
USART_DE_POLARITY_LOW = 0x01 /*!< usart de polarity low */
} usart_de_polarity_type;
/**
* @brief type define usart register all
*/
@ -418,11 +427,12 @@ void usart_irda_mode_enable(usart_type* usart_x, confirm_state new_state);
void usart_irda_low_power_enable(usart_type* usart_x, confirm_state new_state);
void usart_hardware_flow_control_set(usart_type* usart_x,usart_hardware_flow_control_type flow_state);
flag_status usart_flag_get(usart_type* usart_x, uint32_t flag);
flag_status usart_interrupt_flag_get(usart_type* usart_x, uint32_t flag);
void usart_flag_clear(usart_type* usart_x, uint32_t flag);
void usart_rs485_delay_time_config(usart_type* usart_x, uint8_t start_delay_time, uint8_t complete_delay_time);
void usart_transmit_receive_pin_swap(usart_type* usart_x, confirm_state new_state);
void usart_id_bit_num_set(usart_type* usart_x, usart_identification_bit_num_type id_bit_num);
void usart_de_polarity_reverse(usart_type* usart_x, confirm_state new_state);
void usart_de_polarity_set(usart_type* usart_x, usart_de_polarity_type de_polarity);
void usart_rs485_mode_enable(usart_type* usart_x, confirm_state new_state);
void usart_msb_transmit_first_enable(usart_type* usart_x, confirm_state new_state);
void usart_dt_polarity_reverse(usart_type* usart_x, confirm_state new_state);

1
bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/inc/at32f402_405_wwdt.h
View File

@ -134,6 +134,7 @@ void wwdt_flag_clear(void);
void wwdt_enable(uint8_t wwdt_cnt);
void wwdt_interrupt_enable(void);
flag_status wwdt_flag_get(void);
flag_status wwdt_interrupt_flag_get(void);
void wwdt_counter_set(uint8_t wwdt_cnt);
void wwdt_window_counter_set(uint8_t window_cnt);

16
bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_acc.c
View File

@ -188,6 +188,22 @@ flag_status acc_flag_get(uint16_t acc_flag)
return (flag_status)(ACC->sts_bit.rslost);
}
/**
* @brief check whether the specified acc interrupt flag is set or not.
* @param acc_flag: specifies the flag to check.
* this parameter can be one of the following values:
* - ACC_RSLOST_FLAG
* - ACC_CALRDY_FLAG
* @retval flag_status (SET or RESET)
*/
flag_status acc_interrupt_flag_get(uint16_t acc_flag)
{
if(acc_flag == ACC_CALRDY_FLAG)
return (flag_status)(ACC->sts_bit.calrdy && ACC->ctrl1_bit.calrdyien);
else
return (flag_status)(ACC->sts_bit.rslost && ACC->ctrl1_bit.eien);
}
/**
* @brief clear the specified acc flag is set or not.
* @param acc_flag: specifies the flag to check.

49
bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_adc.c
View File

@ -799,10 +799,10 @@ uint16_t adc_ordinary_conversion_data_get(adc_type *adc_x)
* ADC1.
* @param adc_preempt_channel: select the preempt channel.
* this parameter can be one of the following values:
* - ADC_PREEMPTED_CHANNEL_1
* - ADC_PREEMPTED_CHANNEL_2
* - ADC_PREEMPTED_CHANNEL_3
* - ADC_PREEMPTED_CHANNEL_4
* - ADC_PREEMPT_CHANNEL_1
* - ADC_PREEMPT_CHANNEL_2
* - ADC_PREEMPT_CHANNEL_3
* - ADC_PREEMPT_CHANNEL_4
* @retval the conversion data for selection preempt channel.
*/
uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel)
@ -857,6 +857,47 @@ flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag)
return status;
}
/**
* @brief get interrupt flag of the specified adc peripheral.
* @param adc_x: select the adc peripheral.
* this parameter can be one of the following values:
* ADC1.
* @param adc_flag: select the adc flag.
* this parameter can be one of the following values:
* - ADC_VMOR_FLAG
* - ADC_CCE_FLAG
* - ADC_PCCE_FLAG
* @retval the new state of adc flag status(SET or RESET).
*/
flag_status adc_interrupt_flag_get(adc_type *adc_x, uint8_t adc_flag)
{
flag_status status = RESET;
switch(adc_flag)
{
case ADC_VMOR_FLAG:
if(adc_x->sts_bit.vmor && adc_x->ctrl1_bit.vmorien)
{
status = SET;
}
break;
case ADC_CCE_FLAG:
if(adc_x->sts_bit.cce && adc_x->ctrl1_bit.cceien)
{
status = SET;
}
break;
case ADC_PCCE_FLAG:
if(adc_x->sts_bit.pcce && adc_x->ctrl1_bit.pcceien)
{
status = SET;
}
break;
default:
break;
}
return status;
}
/**
* @brief clear flag of the specified adc peripheral.
* @param adc_x: select the adc peripheral.

96
bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_can.c
View File

@ -928,6 +928,102 @@ void can_interrupt_enable(can_type* can_x, uint32_t can_int, confirm_state new_s
}
}
/**
* @brief get interrupt flag of the specified can peripheral.
* @param can_x: select the can peripheral.
* this parameter can be one of the following values:
* CAN1,CAN2.
* @param can_flag: select the flag.
* this parameter can be one of the following flags:
* - CAN_EAF_FLAG
* - CAN_EPF_FLAG
* - CAN_BOF_FLAG
* - CAN_ETR_FLAG
* - CAN_EOIF_FLAG
* - CAN_TM0TCF_FLAG
* - CAN_TM1TCF_FLAG
* - CAN_TM2TCF_FLAG
* - CAN_RF0MN_FLAG
* - CAN_RF0FF_FLAG
* - CAN_RF0OF_FLAG
* - CAN_RF1MN_FLAG
* - CAN_RF1FF_FLAG
* - CAN_RF1OF_FLAG
* - CAN_QDZIF_FLAG
* - CAN_EDZC_FLAG
* - CAN_TMEF_FLAG
* note:the state of CAN_EDZC_FLAG need to check dzc and edzif bit
* note:the state of CAN_TMEF_FLAG need to check rqc0,rqc1 and rqc2 bit
* @retval status of can_flag, the returned value can be:SET or RESET.
*/
flag_status can_interrupt_flag_get(can_type* can_x, uint32_t can_flag)
{
flag_status bit_status = RESET;
flag_status int_status = RESET;
switch(can_flag)
{
case CAN_EAF_FLAG:
int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.eaien);
break;
case CAN_EPF_FLAG:
int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.epien);
break;
case CAN_BOF_FLAG:
int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.boien);
break;
case CAN_ETR_FLAG:
int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.etrien);
break;
case CAN_EOIF_FLAG:
int_status = (flag_status)can_x->inten_bit.eoien;
break;
case CAN_TM0TCF_FLAG:
case CAN_TM1TCF_FLAG:
case CAN_TM2TCF_FLAG:
int_status = (flag_status)can_x->inten_bit.tcien;
break;
case CAN_RF0MN_FLAG:
int_status = (flag_status)can_x->inten_bit.rf0mien;
break;
case CAN_RF0FF_FLAG:
int_status = (flag_status)can_x->inten_bit.rf0fien;
break;
case CAN_RF0OF_FLAG:
int_status = (flag_status)can_x->inten_bit.rf0oien;
break;
case CAN_RF1MN_FLAG:
int_status = (flag_status)can_x->inten_bit.rf1mien;
break;
case CAN_RF1FF_FLAG:
int_status = (flag_status)can_x->inten_bit.rf1fien;
break;
case CAN_RF1OF_FLAG:
int_status = (flag_status)can_x->inten_bit.rf1oien;
break;
case CAN_QDZIF_FLAG:
int_status = (flag_status)can_x->inten_bit.qdzien;
break;
case CAN_EDZC_FLAG:
int_status = (flag_status)can_x->inten_bit.edzien;
break;
case CAN_TMEF_FLAG:
int_status = (flag_status)can_x->inten_bit.tcien;
break;
default:
int_status = RESET;
break;
}
if(int_status != SET)
{
return RESET;
}
bit_status = can_flag_get(can_x, can_flag);
return bit_status;
}
/**
* @brief get flag of the specified can peripheral.
* @param can_x: select the can peripheral.

63
bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_crm.c
View File

@ -141,6 +141,64 @@ flag_status crm_flag_get(uint32_t flag)
return status;
}
/**
* @brief get crm interrupt flag status
* @param flag
* this parameter can be one of the following values:
* - CRM_LICK_READY_INT_FLAG
* - CRM_LEXT_READY_INT_FLAG
* - CRM_HICK_READY_INT_FLAG
* - CRM_HEXT_READY_INT_FLAG
* - CRM_PLL_READY_INT_FLAG
* - CRM_CLOCK_FAILURE_INT_FLAG
* @retval flag_status (SET or RESET)
*/
flag_status crm_interrupt_flag_get(uint32_t flag)
{
flag_status status = RESET;
switch(flag)
{
case CRM_LICK_READY_INT_FLAG:
if(CRM->clkint_bit.lickstblf && CRM->clkint_bit.lickstblien)
{
status = SET;
}
break;
case CRM_LEXT_READY_INT_FLAG:
if(CRM->clkint_bit.lextstblf && CRM->clkint_bit.lextstblien)
{
status = SET;
}
break;
case CRM_HICK_READY_INT_FLAG:
if(CRM->clkint_bit.hickstblf && CRM->clkint_bit.hickstblien)
{
status = SET;
}
break;
case CRM_HEXT_READY_INT_FLAG:
if(CRM->clkint_bit.hextstblf && CRM->clkint_bit.hextstblien)
{
status = SET;
}
break;
case CRM_PLL_READY_INT_FLAG:
if(CRM->clkint_bit.pllstblf && CRM->clkint_bit.pllstblien)
{
status = SET;
}
break;
case CRM_CLOCK_FAILURE_INT_FLAG:
if(CRM->clkint_bit.cfdf && CRM->ctrl_bit.cfden)
{
status = SET;
}
break;
}
return status;
}
/**
* @brief wait for hext stable
* @param none
@ -871,7 +929,7 @@ void crm_clocks_freq_get(crm_clocks_freq_type *clocks_struct)
}
/**
* @brief set crm clkout2
* @brief set crm clkout
* @param clkout
* this parameter can be one of the following values:
* - CRM_CLKOUT_SCLK
@ -882,7 +940,6 @@ void crm_clocks_freq_get(crm_clocks_freq_type *clocks_struct)
* - CRM_CLKOUT_HICK
* - CRM_CLKOUT_LICK
* - CRM_CLKOUT_LEXT
* - CRM_CLKOUT_USBHS
* @retval none
*/
void crm_clock_out_set(crm_clkout_select_type clkout)
@ -899,7 +956,7 @@ void crm_clock_out_set(crm_clkout_select_type clkout)
}
/**
* @brief set crm clkout1 division1
* @brief set crm clkout division1
* @param div1
* this parameter can be one of the following values:
* - CRM_CLKOUT_DIV1_1

182
bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_dma.c
View File

@ -197,6 +197,52 @@ void dma_channel_enable(dma_channel_type *dmax_channely, confirm_state new_state
dmax_channely->ctrl_bit.chen = new_state;
}
/**
* @brief get dma interrupt flag
* @param dmax_flag
* this parameter can be one of the following values:
* - DMA1_FDT1_FLAG - DMA1_HDT1_FLAG - DMA1_DTERR1_FLAG
* - DMA1_FDT2_FLAG - DMA1_HDT2_FLAG - DMA1_DTERR2_FLAG
* - DMA1_FDT3_FLAG - DMA1_HDT3_FLAG - DMA1_DTERR3_FLAG
* - DMA1_FDT4_FLAG - DMA1_HDT4_FLAG - DMA1_DTERR4_FLAG
* - DMA1_FDT5_FLAG - DMA1_HDT5_FLAG - DMA1_DTERR5_FLAG
* - DMA1_FDT6_FLAG - DMA1_HDT6_FLAG - DMA1_DTERR6_FLAG
* - DMA1_FDT7_FLAG - DMA1_HDT7_FLAG - DMA1_DTERR7_FLAG
* - DMA2_FDT1_FLAG - DMA2_HDT1_FLAG - DMA2_DTERR1_FLAG
* - DMA2_FDT2_FLAG - DMA2_HDT2_FLAG - DMA2_DTERR2_FLAG
* - DMA2_FDT3_FLAG - DMA2_HDT3_FLAG - DMA2_DTERR3_FLAG
* - DMA2_FDT4_FLAG - DMA2_HDT4_FLAG - DMA2_DTERR4_FLAG
* - DMA2_FDT5_FLAG - DMA2_HDT5_FLAG - DMA2_DTERR5_FLAG
* - DMA2_FDT6_FLAG - DMA2_HDT6_FLAG - DMA2_DTERR6_FLAG
* - DMA2_FDT7_FLAG - DMA2_HDT7_FLAG - DMA2_DTERR7_FLAG
* @retval state of dma flag
*/
flag_status dma_interrupt_flag_get(uint32_t dmax_flag)
{
flag_status status = RESET;
uint32_t temp = 0;
if(dmax_flag > 0x10000000)
{
temp = DMA2->sts;
}
else
{
temp = DMA1->sts;
}
if ((temp & dmax_flag) != (uint16_t)RESET)
{
status = SET;
}
else
{
status = RESET;
}
return status;
}
/**
* @brief dma flag get.
* @param dma_flag
@ -599,6 +645,78 @@ flag_status dmamux_sync_flag_get(dma_type *dma_x, uint32_t flag)
}
}
/**
* @brief dmamux sync interrupt flag get.
* @param dma_x : pointer to a dma_type structure, can be DMA1 or DMA2.
* @param flag
* this parameter can be any combination of the following values:
* - DMAMUX_SYNC_OV1_FLAG
* - DMAMUX_SYNC_OV2_FLAG
* - DMAMUX_SYNC_OV3_FLAG
* - DMAMUX_SYNC_OV4_FLAG
* - DMAMUX_SYNC_OV5_FLAG
* - DMAMUX_SYNC_OV6_FLAG
* - DMAMUX_SYNC_OV7_FLAG
* @retval state of dmamux sync flag.
*/
flag_status dmamux_sync_interrupt_flag_get(dma_type *dma_x, uint32_t flag)
{
flag_status bitstatus = RESET;
uint32_t sync_int_temp = flag;
uint32_t index = 0;
uint32_t tmpreg = 0, enablestatus = 0;
uint32_t regoffset = 0x4;
while((sync_int_temp & 0x00000001) == RESET)
{
sync_int_temp = sync_int_temp >> 1;
index++;
}
if(dma_x == DMA1)
{
tmpreg = *(uint32_t*)(DMA1MUX_BASE + (index * regoffset));
}
else
{
tmpreg = *(uint32_t*)(DMA2MUX_BASE + (index * regoffset));
}
if((tmpreg & (uint32_t)0x00000100) != (uint32_t)RESET)
{
enablestatus = SET;
}
else
{
enablestatus = RESET;
}
if(dma_x == DMA1)
{
if(((DMA1->muxsyncsts & flag) != (uint32_t)RESET) && (enablestatus != RESET))
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
}
else
{
if(((DMA2->muxsyncsts & flag) != (uint32_t)RESET) && (enablestatus != RESET))
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
}
return bitstatus;
}
/**
* @brief dmamux sync flag clear.
* @param dma_x : pointer to a dma_type structure, can be DMA1 or DMA2.
@ -641,6 +759,70 @@ flag_status dmamux_generator_flag_get(dma_type *dma_x, uint32_t flag)
}
}
/**
* @brief dmamux request generator interrupt flag get.
* @param dma_x : pointer to a dma_type structure, can be DMA1 or DMA2.
* @param flag
* this parameter can be any combination of the following values:
* - DMAMUX_GEN_TRIG_OV1_FLAG
* - DMAMUX_GEN_TRIG_OV2_FLAG
* - DMAMUX_GEN_TRIG_OV3_FLAG
* - DMAMUX_GEN_TRIG_OV4_FLAG
* @retval state of dmamux sync flag.
*/
flag_status dmamux_generator_interrupt_flag_get(dma_type *dma_x, uint32_t flag)
{
flag_status bitstatus = RESET;
uint32_t sync_int_temp = flag;
uint32_t index = 0;
uint32_t tmpreg = 0, enablestatus = 0;
uint32_t regoffset = 0x4;
while((sync_int_temp & 0x00000001) == RESET)
{
sync_int_temp = sync_int_temp >> 1;
index++;
}
if(dma_x == DMA1)
tmpreg = *(uint32_t*)(DMA1MUX_GENERATOR1_BASE + (index * regoffset));
else
tmpreg = *(uint32_t*)(DMA2MUX_GENERATOR1_BASE + (index * regoffset));
if((tmpreg & (uint32_t)0x00000100) != (uint32_t)RESET)
{
enablestatus = SET;
}
else
{
enablestatus = RESET;
}
if(dma_x == DMA1)
{
if(((DMA1->muxgsts & flag) != (uint32_t)RESET) && (enablestatus != RESET))
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
}
else
{
if(((DMA2->muxgsts & flag) != (uint32_t)RESET) && (enablestatus != RESET))
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
}
return bitstatus;
}
/**
* @brief dmamux request generator flag clear.
* @param dma_x : pointer to a dma_type structure, can be DMA1 or DMA2.

49
bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_ertc.c
View File

@ -1482,6 +1482,55 @@ flag_status ertc_flag_get(uint32_t flag)
}
}
/**
* @brief get interrupt flag status.
* @param flag: specifies the flag to check.
* this parameter can be one of the following values:
* - ERTC_ALAF_FLAG: alarm clock a flag.
* - ERTC_ALBF_FLAG: alarm clock b flag.
* - ERTC_WATF_FLAG: wakeup timer flag.
* - ERTC_TSF_FLAG: timestamp flag.
* - ERTC_TP1F_FLAG: tamper detection 1 flag.
* - ERTC_TP2F_FLAG: tamper detection 2 flag.
* @retval the new state of flag (SET or RESET).
*/
flag_status ertc_interrupt_flag_get(uint32_t flag)
{
__IO uint32_t iten = 0;
switch(flag)
{
case ERTC_ALAF_FLAG:
iten = ERTC->ctrl_bit.alaien;
break;
case ERTC_ALBF_FLAG:
iten = ERTC->ctrl_bit.albien;
break;
case ERTC_WATF_FLAG:
iten = ERTC->ctrl_bit.watien;
break;
case ERTC_TSF_FLAG:
iten = ERTC->ctrl_bit.tsien;
break;
case ERTC_TP1F_FLAG:
case ERTC_TP2F_FLAG:
iten = ERTC->tamp_bit.tpien;
break;
default:
break;
}
if(((ERTC->sts & flag) != (uint32_t)RESET) && (iten))
{
return SET;
}
else
{
return RESET;
}
}
/**
* @brief clear flag status
* @param flag: specifies the flag to clear.

30
bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_exint.c
View File

@ -153,6 +153,36 @@ flag_status exint_flag_get(uint32_t exint_line)
return status;
}
/**
* @brief get exint interrupt flag
* @param exint_line
* this parameter can be one of the following values:
* - EXINT_LINE_0
* - EXINT_LINE_1
* ...
* - EXINT_LINE_21
* - EXINT_LINE_22
* @retval the new state of exint flag(SET or RESET).
*/
flag_status exint_interrupt_flag_get(uint32_t exint_line)
{
flag_status status = RESET;
uint32_t exint_flag = 0;
exint_flag = EXINT->intsts & exint_line;
exint_flag = exint_flag & EXINT->inten;
if((exint_flag != (uint16_t)RESET))
{
status = SET;
}
else
{
status = RESET;
}
return status;
}
/**
* @brief generate exint software interrupt event
* @param exint_line

8
bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_flash.c
View File

@ -536,7 +536,7 @@ flag_status flash_fap_high_level_status_get(void)
}
/**
* @brief program the flash system setting byte in usd: wdt_ato_en / depslp_rst / stdby_rst / boot1 / depslp_wdt / stdby_wdt.
* @brief program the flash system setting byte in usd: wdt_ato_en / depslp_rst / stdby_rst / boot1 / depslp_wdt / stdby_wdt / ram_prt_chk.
* @param usd_ssb: the system setting byte
* @note this parameter usd_ssb must contain a combination of all the following 6 types of data
* type 1: wdt_ato_en, select the wdt auto start
@ -563,6 +563,10 @@ flag_status flash_fap_high_level_status_get(void)
* this data can be one of the following values:
* - USD_STDBY_WDT_CONTINUE: wdt continue count when entering in standby
* - USD_STDBY_WDT_STOP: wdt stop count when entering in standby
* type 7: ram_prt_chk, ram parity check disable or enable.
* this data can be one of the following values:
* - USD_RAM_PRT_CHK_DISABLE: ram parity check disabled
* - USD_RAM_PRT_CHK_ENABLE: ram parity check enabled
* @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
* FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
*/
@ -593,7 +597,7 @@ flash_status_type flash_ssb_set(uint8_t usd_ssb)
* @brief return the flash system setting byte status.
* @param none
* @retval values from flash_usd register: wdt_ato_en(bit0), depslp_rst(bit1),
* stdby_rst(bit2), boot1(bit4), depslp_wdt(bit5) and stdby_wdt(bit6).
* stdby_rst(bit2), boot1(bit4), depslp_wdt(bit5), stdby_wdt(bit6) and ram_prt_chk(bit7).
*/
uint8_t flash_ssb_status_get(void)
{

83
bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_i2c.c
View File

@ -120,12 +120,12 @@ void i2c_own_address1_set(i2c_type *i2c_x, i2c_address_mode_type mode, uint16_t
* this parameter can be one of the following values:
* - I2C_ADDR2_NOMASK: compare bit [7:1].
* - I2C_ADDR2_MASK01: only compare bit [7:2].
* - I2C_ADDR2_MASK02: only compare bit [7:2].
* - I2C_ADDR2_MASK03: only compare bit [7:3].
* - I2C_ADDR2_MASK04: only compare bit [7:4].
* - I2C_ADDR2_MASK05: only compare bit [7:5].
* - I2C_ADDR2_MASK06: only compare bit [7:6].
* - I2C_ADDR2_MASK07: only compare bit [7].
* - I2C_ADDR2_MASK02: only compare bit [7:3].
* - I2C_ADDR2_MASK03: only compare bit [7:4].
* - I2C_ADDR2_MASK04: only compare bit [7:5].
* - I2C_ADDR2_MASK05: only compare bit [7:6].
* - I2C_ADDR2_MASK06: only compare bit [7].
* - I2C_ADDR2_MASK07: response all addresses other than those reserved for i2c.
* @retval none
*/
void i2c_own_address2_set(i2c_type *i2c_x, uint8_t address, i2c_addr2_mask_type mask)
@ -706,6 +706,77 @@ flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag)
}
}
/**
* @brief get interrupt flag status.
* @param i2c_x: to select the i2c peripheral.
* this parameter can be one of the following values:
* I2C1, I2C2, I2C3.
* @param flag: specifies the flag to check.
* this parameter can be one of the following values:
* - I2C_TDBE_FLAG: transmit data buffer empty flag.
* - I2C_TDIS_FLAG: send interrupt status.
* - I2C_RDBF_FLAG: receive data buffer full flag.
* - I2C_ADDRF_FLAG: 0~7 bit address match flag.
* - I2C_ACKFAIL_FLAG: acknowledge failure flag.
* - I2C_STOPF_FLAG: stop condition generation complete flag.
* - I2C_TDC_FLAG: transmit data complete flag.
* - I2C_TCRLD_FLAG: transmission is complete, waiting to load data.
* - I2C_BUSERR_FLAG: bus error flag.
* - I2C_ARLOST_FLAG: arbitration lost flag.
* - I2C_OUF_FLAG: overflow or underflow flag.
* - I2C_PECERR_FLAG: pec receive error flag.
* - I2C_TMOUT_FLAG: smbus timeout flag.
* - I2C_ALERTF_FLAG: smbus alert flag.
* @retval the new state of flag (SET or RESET).
*/
flag_status i2c_interrupt_flag_get(i2c_type *i2c_x, uint32_t flag)
{
__IO uint32_t iten = 0;
switch(flag)
{
case I2C_TDIS_FLAG:
iten = i2c_x->ctrl1_bit.tdien;
break;
case I2C_RDBF_FLAG:
iten = i2c_x->ctrl1_bit.rdien;
break;
case I2C_ADDRF_FLAG:
iten = i2c_x->ctrl1_bit.addrien;
break;
case I2C_ACKFAIL_FLAG:
iten = i2c_x->ctrl1_bit.ackfailien;
break;
case I2C_STOPF_FLAG:
iten = i2c_x->ctrl1_bit.stopien;
break;
case I2C_TDC_FLAG:
case I2C_TCRLD_FLAG:
iten = i2c_x->ctrl1_bit.tdcien;
break;
case I2C_BUSERR_FLAG:
case I2C_ARLOST_FLAG:
case I2C_OUF_FLAG:
case I2C_PECERR_FLAG:
case I2C_TMOUT_FLAG:
case I2C_ALERTF_FLAG:
iten = i2c_x->ctrl1_bit.errien;
break;
default:
break;
}
if(((i2c_x->sts & flag) != RESET) && (iten))
{
return SET;
}
else
{
return RESET;
}
}
/**
* @brief clear flag status
* @param i2c_x: to select the i2c peripheral.

11
bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_pwc.c
View File

@ -207,7 +207,6 @@ void pwc_deep_sleep_mode_enter(pwc_deep_sleep_enter_type pwc_deep_sleep_enter)
* @param pwc_regulator: set the regulator state.
* this parameter can be one of the following values:
* - PWC_REGULATOR_ON
* - PWC_REGULATOR_LOW_POWER
* - PWC_REGULATOR_EXTRA_LOW_POWER
* @retval none
*/
@ -215,15 +214,11 @@ void pwc_voltage_regulate_set(pwc_regulator_type pwc_regulator)
{
switch(pwc_regulator)
{
case 0:
case PWC_REGULATOR_ON:
PWC->ldoov_bit.vrexlpen = 0;
PWC->ctrl_bit.vrsel = 0;
break;
case 1:
PWC->ldoov_bit.vrexlpen = 0;
PWC->ctrl_bit.vrsel = 1;
break;
case 2:
case PWC_REGULATOR_EXTRA_LOW_POWER:
PWC->ldoov_bit.vrexlpen = 1;
PWC->ctrl_bit.vrsel = 1;
break;
@ -242,7 +237,7 @@ void pwc_standby_mode_enter(void)
PWC->ctrl_bit.clswef = TRUE;
PWC->ctrl_bit.lpsel = TRUE;
SCB->SCR |= 0x04;
#if defined (__CC_ARM)
#if defined (__ARMCC_VERSION)
__force_stores();
#endif
while(1)

52
bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_qspi.c
View File

@ -39,6 +39,21 @@
* @{
*/
/**
* @brief deinitialize the qspi peripheral registers to their default reset values.
* @param qspi_x: select the qspi peripheral.
* this parameter can be one of the following values:
* QSPI1.
* @retval none
*/
void qspi_reset(qspi_type* qspi_x)
{
{
crm_periph_reset(CRM_QSPI1_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_QSPI1_PERIPH_RESET, FALSE);
}
}
/**
* @brief enable/disable encryption for qspi.
* @note the function must be configured only when qspi in command-port mode!!!
@ -131,7 +146,7 @@ void qspi_interrupt_enable(qspi_type* qspi_x, confirm_state new_state)
* - QSPI_RXFIFORDY_FLAG
* - QSPI_TXFIFORDY_FLAG
* - QSPI_CMDSTS_FLAG
* @retval the new state of usart_flag (SET or RESET).
* @retval the new state of the flag (SET or RESET).
*/
flag_status qspi_flag_get(qspi_type* qspi_x, uint32_t flag)
{
@ -153,6 +168,24 @@ flag_status qspi_flag_get(qspi_type* qspi_x, uint32_t flag)
return bit_status;
}
/**
* @brief get interrupt flags.
* @param qspi_x: select the qspi peripheral.
* this parameter can be one of the following values:
* QSPI1.
* @param flag: only QSPI_CMDSTS_FLAG valid.
* @retval the new state of the flag (SET or RESET).
*/
flag_status qspi_interrupt_flag_get(qspi_type* qspi_x, uint32_t flag)
{
if(QSPI_CMDSTS_FLAG != flag)
return RESET;
if(qspi_x->cmdsts_bit.cmdsts && qspi_x->ctrl2_bit.cmdie)
return SET;
else
return RESET;
}
/**
* @brief clear flags
* @param qspi_x: select the qspi peripheral.
@ -163,7 +196,7 @@ flag_status qspi_flag_get(qspi_type* qspi_x, uint32_t flag)
* - QSPI_CMDSTS_FLAG
* @retval none
*/
void qspi_flag_clear( qspi_type* qspi_x, uint32_t flag)
void qspi_flag_clear(qspi_type* qspi_x, uint32_t flag)
{
qspi_x->cmdsts = QSPI_CMDSTS_FLAG;
}
@ -178,7 +211,7 @@ void qspi_flag_clear( qspi_type* qspi_x, uint32_t flag)
* this parameter can be one of the following values:
* - QSPI_DMA_FIFO_THOD_WORD08
* - QSPI_DMA_FIFO_THOD_WORD16
* - QSPI_DMA_FIFO_THOD_WORD32
* - QSPI_DMA_FIFO_THOD_WORD24
* @retval none
*/
void qspi_dma_rx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_threshold)
@ -196,7 +229,7 @@ void qspi_dma_rx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_th
* this parameter can be one of the following values:
* - QSPI_DMA_FIFO_THOD_WORD08
* - QSPI_DMA_FIFO_THOD_WORD16
* - QSPI_DMA_FIFO_THOD_WORD32
* - QSPI_DMA_FIFO_THOD_WORD24
* @retval none
*/
void qspi_dma_tx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_threshold)
@ -267,6 +300,7 @@ void qspi_xip_enable(qspi_type* qspi_x, confirm_state new_state)
{
__NOP();
}
/* flush and reset qspi state */
qspi_x->ctrl_bit.xiprcmdf = 1;
@ -425,6 +459,16 @@ void qspi_word_write(qspi_type* qspi_x, uint32_t value)
qspi_x->dt = value;
}
/**
* @brief enable auto input sampling phase correction
* @param qspi_x: select the qspi peripheral.
* @retval none.
*/
void qspi_auto_ispc_enable(qspi_type* qspi_x)
{
qspi_x->ctrl3_bit.ispc = TRUE;
}
/**
* @}
*/

15
bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_scfg.c
View File

@ -55,8 +55,6 @@ void scfg_reset(void)
* @param source
* this parameter can be one of the following values:
* - SCFG_IR_SOURCE_TMR10
* - SCFG_IR_SOURCE_USART1
* - SCFG_IR_SOURCE_USART2
* @param polarity
* this parameter can be one of the following values:
* - SCFG_IR_POLARITY_NO_AFFECTE
@ -116,18 +114,11 @@ void scfg_pvm_lock_enable(confirm_state new_state)
/**
* @brief scfg sram odd parity error status get
* @param none
* @retval return sram odd parity error status (ERROR or SUCCESS)
* @retval return sram odd parity error status(SET or RESET)
*/
error_status scfg_sram_operr_status_get(void)
flag_status scfg_sram_operr_status_get(void)
{
error_status status = SUCCESS;
if(SCFG->cfg2_bit.sram_operr_sts)
status = ERROR;
else
status = SUCCESS;
return status ;
return (flag_status)SCFG->cfg2_bit.sram_operr_sts;
}
/**

70
bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_spi.c
View File

@ -674,6 +674,76 @@ flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag)
return status;
}
/**
* @brief get interrupt flag of the specified spi/i2s peripheral.
* @param spi_x: select the spi/i2s peripheral.
* this parameter can be one of the following values:
* SPI1, SPI2, SPI3, I2SF5
* @param spi_i2s_flag: select the spi/i2s flag
* this parameter can be one of the following values:
* - SPI_I2S_RDBF_FLAG
* - SPI_I2S_TDBE_FLAG
* - I2S_TUERR_FLAG (this flag only use in i2s mode)
* - SPI_CCERR_FLAG (this flag only use in spi mode)
* - SPI_MMERR_FLAG (this flag only use in spi mode)
* - SPI_I2S_ROERR_FLAG
* - SPI_I2S_CSPAS_FLAG
* @retval the new state of spi/i2s flag
*/
flag_status spi_i2s_interrupt_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag)
{
flag_status status = RESET;
switch(spi_i2s_flag)
{
case SPI_I2S_RDBF_FLAG:
if(spi_x->sts_bit.rdbf && spi_x->ctrl2_bit.rdbfie)
{
status = SET;
}
break;
case SPI_I2S_TDBE_FLAG:
if(spi_x->sts_bit.tdbe && spi_x->ctrl2_bit.tdbeie)
{
status = SET;
}
break;
case I2S_TUERR_FLAG:
if(spi_x->sts_bit.tuerr && spi_x->ctrl2_bit.errie)
{
status = SET;
}
break;
case SPI_CCERR_FLAG:
if(spi_x->sts_bit.ccerr && spi_x->ctrl2_bit.errie)
{
status = SET;
}
break;
case SPI_MMERR_FLAG:
if(spi_x->sts_bit.mmerr && spi_x->ctrl2_bit.errie)
{
status = SET;
}
break;
case SPI_I2S_ROERR_FLAG:
if(spi_x->sts_bit.roerr && spi_x->ctrl2_bit.errie)
{
status = SET;
}
break;
case SPI_I2S_CSPAS_FLAG:
if(spi_x->sts_bit.cspas && spi_x->ctrl2_bit.errie)
{
status = SET;
}
break;
default:
break;
};
return status;
}
/**
* @brief clear flag of the specified spi/i2s peripheral.
* @param spi_x: select the spi/i2s peripheral.

49
bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_tmr.c
View File

@ -160,7 +160,6 @@ void tmr_input_default_para_init(tmr_input_config_type *tmr_input_struct)
*/
void tmr_brkdt_default_para_init(tmr_brkdt_config_type *tmr_brkdt_struct)
{
tmr_brkdt_struct->brk_filter_value = 0x0;
tmr_brkdt_struct->deadtime = 0x0;
tmr_brkdt_struct->brk_polarity = TMR_BRK_INPUT_ACTIVE_LOW;
tmr_brkdt_struct->wp_level = TMR_WP_OFF;
@ -1346,6 +1345,40 @@ void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state
}
}
/**
* @brief get tmr interrupt flag
* @param tmr_x: select the tmr peripheral.
* this parameter can be one of the following values:
* TMR1, TMR2, TMR3, TMR4, TMR6, TMR7, TMR9, TMR10,
* TMR11, TMR13, TMR14
* @param tmr_flag
* this parameter can be one of the following values:
* - TMR_OVF_FLAG
* - TMR_C1_FLAG
* - TMR_C2_FLAG
* - TMR_C3_FLAG
* - TMR_C4_FLAG
* - TMR_HALL_FLAG
* - TMR_TRIGGER_FLAG
* - TMR_BRK_FLAG
* @retval state of tmr interrupt flag
*/
flag_status tmr_interrupt_flag_get(tmr_type *tmr_x, uint32_t tmr_flag)
{
flag_status status = RESET;
if((tmr_x->ists & tmr_flag) && (tmr_x->iden & tmr_flag))
{
status = SET;
}
else
{
status = RESET;
}
return status;
}
/**
* @brief get tmr flag
* @param tmr_x: select the tmr peripheral.
@ -1766,7 +1799,6 @@ void tmr_dma_control_config(tmr_type *tmr_x, tmr_dma_transfer_length_type dma_le
*/
void tmr_brkdt_config(tmr_type *tmr_x, tmr_brkdt_config_type *brkdt_struct)
{
tmr_x->brk_bit.bkf = brkdt_struct->brk_filter_value;
tmr_x->brk_bit.brken = brkdt_struct->brk_enable;
tmr_x->brk_bit.dtc = brkdt_struct->deadtime;
tmr_x->brk_bit.fcsodis = brkdt_struct->fcsodis_state;
@ -1776,6 +1808,19 @@ void tmr_brkdt_config(tmr_type *tmr_x, tmr_brkdt_config_type *brkdt_struct)
tmr_x->brk_bit.wpc = brkdt_struct->wp_level;
}
/**
* @brief set tmr break input filter value
* @param tmr_x: select the tmr peripheral.
* this parameter can be one of the following values:
* TMR1, TMR9, TMR10, TMR11, TMR13, TRM14
* @param filter_value (0x0~0xf)
* @retval none
*/
void tmr_brk_filter_value_set(tmr_type *tmr_x, uint8_t filter_value)
{
tmr_x->brk_bit.bkf = filter_value;
}
/**
* @brief set tmr2 and tmr14 input channel remap
* @param tmr_x: select the tmr peripheral.

92
bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_usart.c
View File

@ -607,6 +607,88 @@ flag_status usart_flag_get(usart_type* usart_x, uint32_t flag)
}
}
/**
* @brief check whether the specified usart interrupt flag is set or not.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1, USART2, USART3, USART4, USART5, USART6, UART7 or UART8.
* @param flag: specifies the flag to check.
* this parameter can be one of the following values:
* - USART_RTODF_FLAG: receiver time out detection flag
* - USART_CMDF_FLAG: character match detection flag
* - USART_CTSCF_FLAG: cts change flag
* - USART_BFF_FLAG: break frame flag
* - USART_TDBE_FLAG: transmit data buffer empty flag
* - USART_TDC_FLAG: transmit data complete flag
* - USART_RDBF_FLAG: receive data buffer full flag
* - USART_IDLEF_FLAG: idle flag
* - USART_ROERR_FLAG: receiver overflow error flag
* - USART_NERR_FLAG: noise error flag
* - USART_FERR_FLAG: framing error flag
* - USART_PERR_FLAG: parity error flag
* @retval the new state of usart_flag (SET or RESET).
*/
flag_status usart_interrupt_flag_get(usart_type* usart_x, uint32_t flag)
{
flag_status int_status = RESET;
switch(flag)
{
case USART_CTSCF_FLAG:
int_status = (flag_status)usart_x->ctrl3_bit.ctscfien;
break;
case USART_BFF_FLAG:
int_status = (flag_status)usart_x->ctrl2_bit.bfien;
break;
case USART_TDBE_FLAG:
int_status = (flag_status)usart_x->ctrl1_bit.tdbeien;
break;
case USART_TDC_FLAG:
int_status = (flag_status)usart_x->ctrl1_bit.tdcien;
break;
case USART_RDBF_FLAG:
int_status = (flag_status)usart_x->ctrl1_bit.rdbfien;
break;
case USART_ROERR_FLAG:
int_status = (flag_status)(usart_x->ctrl1_bit.rdbfien || usart_x->ctrl3_bit.errien);
break;
case USART_IDLEF_FLAG:
int_status = (flag_status)usart_x->ctrl1_bit.idleien;
break;
case USART_NERR_FLAG:
case USART_FERR_FLAG:
int_status = (flag_status)usart_x->ctrl3_bit.errien;
break;
case USART_PERR_FLAG:
int_status = (flag_status)usart_x->ctrl1_bit.perrien;
break;
case USART_RTODF_FLAG:
int_status = (flag_status)usart_x->ctrl1_bit.retodie;
break;
case USART_CMDF_FLAG:
int_status = (flag_status)usart_x->ctrl1_bit.cmdie;
break;
default:
int_status = RESET;
break;
}
if(int_status != SET)
{
return RESET;
}
if(usart_x->sts & flag)
{
return SET;
}
else
{
return RESET;
}
}
/**
* @brief clear the usart's pending flags.
* @param usart_x: select the usart or the uart peripheral.
@ -700,17 +782,17 @@ void usart_id_bit_num_set(usart_type* usart_x, usart_identification_bit_num_type
}
/**
* @brief enable or disable the usart's de polarity reverse.
* @brief set the usart's de polarity.
* @param usart_x: select the usart or the uart peripheral.
* this parameter can be one of the following values:
* USART1, USART2, USART3
* @param new_state: new state of the irda mode.
* this parameter can be: TRUE or FALSE.
* @param de_polarity: the usart de polarity selection.
* this parameter can be: USART_DE_POLARITY_HIGH or USART_DE_POLARITY_LOW.
* @retval none
*/
void usart_de_polarity_reverse(usart_type* usart_x, confirm_state new_state)
void usart_de_polarity_set(usart_type* usart_x, usart_de_polarity_type de_polarity)
{
usart_x->ctrl3_bit.dep = new_state;
usart_x->ctrl3_bit.dep = (uint8_t)de_polarity;
}
/**

1
bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_usb.c
View File

@ -1063,7 +1063,6 @@ void usb_hch_halt(otg_global_type *usbx, uint8_t chn)
{
usb_chh->hcchar_bit.chena = TRUE;
}
}
else
{

10
bsp/at32/libraries/AT32F402_405_Firmware_Library/drivers/src/at32f402_405_wwdt.c
View File

@ -104,6 +104,16 @@ flag_status wwdt_flag_get(void)
return (flag_status)WWDT->sts_bit.rldf;
}
/**
* @brief wwdt reload counter interrupt flag get
* @param none
* @retval state of reload counter interrupt flag
*/
flag_status wwdt_interrupt_flag_get(void)
{
return (flag_status)(WWDT->sts_bit.rldf && WWDT->cfg_bit.rldien);
}
/**
* @brief wwdt counter value set
* @param wwdt_cnt (0x40~0x7f)

8
bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/system_at32f403a_407.c
View File

@ -1,8 +1,6 @@
/**
**************************************************************************
* @file system_at32f403a_407.c
* @version v2.0.9
* @date 2022-04-25
* @brief contains all the functions for cmsis cortex-m4 system source file
**************************************************************************
* Copyright notice & Disclaimer
@ -81,13 +79,13 @@ void SystemInit (void)
/* wait sclk switch status */
while(CRM->cfg_bit.sclksts != CRM_SCLK_HICK);
/* reset hexten, hextbyps, cfden and pllen bits */
CRM->ctrl &= ~(0x010D0000U);
/* reset cfg register, include sclk switch, ahbdiv, apb1div, apb2div, adcdiv,
clkout pllrcs, pllhextdiv, pllmult, usbdiv and pllrange bits */
CRM->cfg = 0;
/* reset hexten, hextbyps, cfden and pllen bits */
CRM->ctrl &= ~(0x010D0000U);
/* reset clkout[3], usbbufs, hickdiv, clkoutdiv */
CRM->misc1 = 0;

7
bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/system_at32f403a_407.h
View File

@ -1,8 +1,6 @@
/**
**************************************************************************
* @file system_at32f403a_407.h
* @version v2.0.9
* @date 2022-04-25
* @brief cmsis cortex-m4 system header file.
**************************************************************************
* Copyright notice & Disclaimer
@ -45,6 +43,11 @@ extern "C" {
#define HEXT_STABLE_DELAY (5000u)
#define PLL_STABLE_DELAY (500u)
#define SystemCoreClock system_core_clock
#define DUMMY_NOP() {__NOP();__NOP();__NOP();__NOP();__NOP(); \
__NOP();__NOP();__NOP();__NOP();__NOP(); \
__NOP();__NOP();__NOP();__NOP();__NOP(); \
__NOP();__NOP();__NOP();__NOP();__NOP();}
/**
* @}

3
bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_acc.h
View File

@ -1,8 +1,6 @@
/**
**************************************************************************
* @file at32f403a_407_acc.h
* @version v2.0.9
* @date 2022-04-25
* @brief at32f403a_407 acc header file
**************************************************************************
* Copyright notice & Disclaimer
@ -181,6 +179,7 @@ uint16_t acc_read_c1(void);
uint16_t acc_read_c2(void);
uint16_t acc_read_c3(void);
flag_status acc_flag_get(uint16_t acc_flag);
flag_status acc_interrupt_flag_get(uint16_t acc_flag);
void acc_flag_clear(uint16_t acc_flag);
/**

3
bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_adc.h
View File

@ -1,8 +1,6 @@
/**
**************************************************************************
* @file at32f403a_407_adc.h
* @version v2.0.9
* @date 2022-04-25
* @brief at32f403a_407 adc header file
**************************************************************************
* Copyright notice & Disclaimer
@ -621,6 +619,7 @@ uint16_t adc_ordinary_conversion_data_get(adc_type *adc_x);
uint32_t adc_combine_ordinary_conversion_data_get(void);
uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel);
flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag);
flag_status adc_interrupt_flag_get(adc_type *adc_x, uint8_t adc_flag);
void adc_flag_clear(adc_type *adc_x, uint32_t adc_flag);
/**

3
bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_bpr.h
View File

@ -1,8 +1,6 @@
/**
**************************************************************************
* @file at32f403a_407_bpr.h
* @version v2.0.9
* @date 2022-04-25
* @brief at32f403a_407 bpr header file
**************************************************************************
* Copyright notice & Disclaimer
@ -761,6 +759,7 @@ typedef struct
void bpr_reset(void);
flag_status bpr_flag_get(uint32_t flag);
flag_status bpr_interrupt_flag_get(uint32_t flag);
void bpr_flag_clear(uint32_t flag);
void bpr_interrupt_enable(confirm_state new_state);
uint16_t bpr_data_read(bpr_data_type bpr_data);

5
bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_can.h
View File

@ -1,8 +1,6 @@
/**
**************************************************************************
* @file at32f403a_407_can.h
* @version v2.0.9
* @date 2022-04-25
* @brief at32f403a_407 can header file
**************************************************************************
* Copyright notice & Disclaimer
@ -352,7 +350,7 @@ typedef struct
*/
typedef struct
{
uint16_t baudrate_div; /*!< baudrate division,this parameter can be 0x001~0x400.*/
uint16_t baudrate_div; /*!< baudrate division,this parameter can be 0x001~0x1000.*/
can_rsaw_type rsaw_size; /*!< resynchronization adjust width */
@ -964,6 +962,7 @@ can_error_record_type can_error_type_record_get(can_type* can_x);
uint8_t can_receive_error_counter_get(can_type* can_x);
uint8_t can_transmit_error_counter_get(can_type* can_x);
void can_interrupt_enable(can_type* can_x, uint32_t can_int, confirm_state new_state);
flag_status can_interrupt_flag_get(can_type* can_x, uint32_t can_flag);
flag_status can_flag_get(can_type* can_x, uint32_t can_flag);
void can_flag_clear(can_type* can_x, uint32_t can_flag);

34
bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_crc.h
View File

@ -1,8 +1,6 @@
/**
**************************************************************************
* @file at32f403a_407_crc.h
* @version v2.0.9
* @date 2022-04-25
* @brief at32f403a_407 crc header file
**************************************************************************
* Copyright notice & Disclaimer
@ -68,6 +66,17 @@ typedef enum
CRC_REVERSE_OUTPUT_DATA = 0x01 /*!< output data reverse by word */
} crc_reverse_output_type;
/**
* @brief crc polynomial size
*/
typedef enum
{
CRC_POLY_SIZE_32B = 0x00, /*!< polynomial size 32 bits */
CRC_POLY_SIZE_16B = 0x01, /*!< polynomial size 16 bits */
CRC_POLY_SIZE_8B = 0x02, /*!< polynomial size 8 bits */
CRC_POLY_SIZE_7B = 0x03 /*!< polynomial size 7 bits */
} crc_poly_size_type;
/**
* @brief type define crc register all
*/
@ -107,7 +116,8 @@ typedef struct
struct
{
__IO uint32_t rst : 1 ; /* [0] */
__IO uint32_t reserved1 : 4 ; /* [4:1] */
__IO uint32_t reserved1 : 2 ; /* [2:1] */
__IO uint32_t poly_size : 2 ; /* [4:3] */
__IO uint32_t revid : 2 ; /* [6:5] */
__IO uint32_t revod : 1 ; /* [7] */
__IO uint32_t reserved2 : 24 ;/* [31:8] */
@ -131,6 +141,18 @@ typedef struct
} idt_bit;
};
/**
* @brief crc polynomial register, offset:0x14
*/
union
{
__IO uint32_t poly;
struct
{
__IO uint32_t poly : 32; /* [31:0] */
} poly_bit;
};
} crc_type;
/**
@ -148,10 +170,14 @@ uint32_t crc_one_word_calculate(uint32_t data);
uint32_t crc_block_calculate(uint32_t *pbuffer, uint32_t length);
uint32_t crc_data_get(void);
void crc_common_data_set(uint8_t cdt_value);
uint8_t crc_common_date_get(void);
uint8_t crc_common_data_get(void);
void crc_init_data_set(uint32_t value);
void crc_reverse_input_data_set(crc_reverse_input_type value);
void crc_reverse_output_data_set(crc_reverse_output_type value);
void crc_poly_value_set(uint32_t value);
uint32_t crc_poly_value_get(void);
void crc_poly_size_set(crc_poly_size_type size);
crc_poly_size_type crc_poly_size_get(void);
/**
* @}

3
bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_crm.h
View File

@ -1,8 +1,6 @@
/**
**************************************************************************
* @file at32f403a_407_crm.h
* @version v2.0.9
* @date 2022-04-25
* @brief at32f403a_407 crm header file
**************************************************************************
* Copyright notice & Disclaimer
@ -1088,6 +1086,7 @@ void crm_reset(void);
void crm_lext_bypass(confirm_state new_state);
void crm_hext_bypass(confirm_state new_state);
flag_status crm_flag_get(uint32_t flag);
flag_status crm_interrupt_flag_get(uint32_t flag);
error_status crm_hext_stable_wait(void);
void crm_hick_clock_trimming_set(uint8_t trim_value);
void crm_hick_clock_calibration_set(uint8_t cali_value);

2
bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_dac.h
View File

@ -1,8 +1,6 @@
/**
**************************************************************************
* @file at32f403a_407_dac.h
* @version v2.0.9
* @date 2022-04-25
* @brief at32f403a_407 dac header file
**************************************************************************
* Copyright notice & Disclaimer

2
bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_debug.h
View File

@ -1,8 +1,6 @@
/**
**************************************************************************
* @file at32f403a_407_debug.h
* @version v2.0.9
* @date 2022-04-25
* @brief at32f403a_407 debug header file
**************************************************************************
* Copyright notice & Disclaimer

4
bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_def.h
View File

@ -1,8 +1,6 @@
/**
**************************************************************************
* @file at32f403a_407_def.h
* @version v2.0.9
* @date 2022-04-25
* @brief at32f403a_407 macros header file
**************************************************************************
* Copyright notice & Disclaimer
@ -62,6 +60,8 @@ extern "C" {
#endif
#endif
#define UNUSED(x) (void)x /* to avoid gcc/g++ warnings */
#ifdef __cplusplus
}
#endif

3
bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_dma.h
View File

@ -1,8 +1,6 @@
/**
**************************************************************************
* @file at32f403a_407_dma.h
* @version v2.0.9
* @date 2022-04-25
* @brief at32f403a_407 dma header file
**************************************************************************
* Copyright notice & Disclaimer
@ -527,6 +525,7 @@ void dma_interrupt_enable(dma_channel_type* dmax_channely, uint32_t dma_int, con
void dma_channel_enable(dma_channel_type* dmax_channely, confirm_state new_state);
void dma_flexible_config(dma_type* dma_x, uint8_t flex_channelx, dma_flexible_request_type flexible_request);
flag_status dma_flag_get(uint32_t dmax_flag);
flag_status dma_interrupt_flag_get(uint32_t dmax_flag);
void dma_flag_clear(uint32_t dmax_flag);
void dma_default_para_init(dma_init_type* dma_init_struct);
void dma_init(dma_channel_type* dmax_channely, dma_init_type* dma_init_struct);

39
bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_emac.h
View File

@ -1,8 +1,6 @@
/**
**************************************************************************
* @file at32f403a_407_emac.h
* @version v2.0.9
* @date 2022-04-25
* @brief at32f403a_407 emac header file
**************************************************************************
* Copyright notice & Disclaimer
@ -46,6 +44,7 @@ extern "C" {
*/
#define PHY_TIMEOUT (0x000FFFFF) /*!< timeout for phy response */
#define EMAC_USE_ENHANCED_DMA_DESCRIPTOR
/** @defgroup EMAC_smi_clock_border_definition
* @brief emac smi clock border
@ -99,7 +98,7 @@ extern "C" {
* @{
*/
#define EMAC_MAX_PACKET_LENGTH 1520 /*!< emac_header + emac_extra + emac_max_payload + emac_crc */
#define EMAC_MAX_PACKET_LENGTH 1524 /*!< emac_header + emac_extra + emac_max_payload + emac_crc */
#define EMAC_HEADER 14 /*!< 6 byte dest addr, 6 byte src addr, 2 byte length/ept_type */
#define EMAC_CRC 4 /*!< ethernet crc */
#define EMAC_EXTRA 2 /*!< extra bytes in some cases */
@ -271,6 +270,15 @@ extern "C" {
#define EMAC_DMA_AIS_FLAG ((uint32_t)0x00008000) /*!< emac dma abnormal interrupt summary */
#define EMAC_DMA_NIS_FLAG ((uint32_t)0x00010000) /*!< emac dma normal interrupt summary */
/**
* @brief emac ptp time sign
*/
#define EMAC_PTP_POSITIVETIME ((uint32_t)0x00000000) /*!< Positive time value */
#define EMAC_PTP_NEGATIVETIME ((uint32_t)0x80000000) /*!< Negative time value */
#define EMAC_PTP_TI_FLAG ((uint32_t)0x00000004) /*!< Time Stamp Initialized */
#define EMAC_PTP_TU_FLAG ((uint32_t)0x00000008) /*!< Time Stamp Updated */
#define EMAC_PTP_ARU_FLAG ((uint32_t)0x00000020) /*!< Addend Register Updated */
/** @defgroup EMAC_exported_types
* @{
*/
@ -345,9 +353,10 @@ typedef enum
*/
typedef enum
{
EMAC_CONTROL_FRAME_PASSING_NO = 0x00, /*!< don't pass any control frame to application */
EMAC_CONTROL_FRAME_PASSING_ALL = 0x02, /*!< pass all control frames to application */
EMAC_CONTROL_FRAME_PASSING_MATCH = 0x03 /*!< only pass filtered control frames to application */
EMAC_CONTROL_FRAME_PASSING_NO = 0x00, /*!< don't pass any control frame to application */
EMAC_CONTROL_FRAME_PASSING_ALL_EXCEPT_PAUSE = 0x01, /*!< pass all control frames to application except pause frame */
EMAC_CONTROL_FRAME_PASSING_ALL = 0x02, /*!< pass all control frames to application */
EMAC_CONTROL_FRAME_PASSING_MATCH = 0x03 /*!< only pass filtered control frames to application */
} emac_control_frames_filter_type;
/**
@ -633,6 +642,10 @@ typedef struct {
uint32_t controlsize; /*!< control and buffer1, buffer2 lengths */
uint32_t buf1addr; /*!< buffer1 address pointer */
uint32_t buf2nextdescaddr; /*!< buffer2 or next descriptor address pointer */
uint32_t extendedstatus;
uint32_t reserved1;
uint32_t timestamp_l;
uint32_t timestamp_h;
} emac_dma_desc_type;
/**
@ -891,7 +904,7 @@ typedef struct
__IO uint32_t reserved1 : 8; /* [16:23] */
__IO uint32_t mbc : 6; /* [24:29] */
__IO uint32_t sa : 1; /* [30] */
__IO uint32_t ae : 1; /* [31] */
__IO uint32_t ae : 1; /* [31] */
} a1h_bit;
};
@ -1328,7 +1341,7 @@ typedef struct
__IO uint32_t swr : 1; /* [0] */
__IO uint32_t da : 1; /* [1] */
__IO uint32_t dsl : 5; /* [2:6] */
__IO uint32_t reserved1 : 1; /* [7] */
__IO uint32_t atds : 1; /* [7] */
__IO uint32_t pbl : 6; /* [8:13] */
__IO uint32_t pr : 2; /* [14:15] */
__IO uint32_t fb : 1; /* [16] */
@ -1336,7 +1349,7 @@ typedef struct
__IO uint32_t usp : 1; /* [23] */
__IO uint32_t pblx8 : 1; /* [24] */
__IO uint32_t aab : 1; /* [25] */
__IO uint32_t reserved2 : 6; /* [26:31] */
__IO uint32_t reserved : 6; /* [26:31] */
} bm_bit;
};
@ -1628,6 +1641,7 @@ void emac_address_filter_set(emac_address_type mac, emac_address_filter_type fil
uint32_t emac_received_packet_size_get(void);
uint32_t emac_dmarxdesc_frame_length_get(emac_dma_desc_type *dma_rx_desc);
void emac_dma_descriptor_list_address_set(emac_dma_tx_rx_type transfer_type, emac_dma_desc_type *dma_desc_tab, uint8_t *buff, uint32_t buffer_count);
void emac_ptp_dma_descriptor_list_address_set(emac_dma_tx_rx_type transfer_type, emac_dma_desc_type *dma_desc_tab, emac_dma_desc_type *ptp_dma_desc_tab, uint8_t *buff, uint32_t buffer_count);
uint32_t emac_dma_descriptor_list_address_get(emac_dma_tx_rx_type transfer_type);
void emac_dma_rx_desc_interrupt_config(emac_dma_desc_type *dma_rx_desc, confirm_state new_state);
void emac_dma_para_init(emac_dma_config_type *control_para);
@ -1650,6 +1664,7 @@ uint8_t emac_dma_missing_overflow_bit_get(void);
uint16_t emac_dma_application_missing_frame_get(void);
uint8_t emac_dma_fifo_overflow_bit_get(void);
uint32_t emac_dma_tansfer_address_get(emac_dma_transfer_address_type transfer_type);
void emac_dma_alternate_desc_size(confirm_state new_state);
void emac_mmc_counter_reset(void);
void emac_mmc_rollover_stop(confirm_state new_state);
void emac_mmc_reset_on_read_enable(confirm_state new_state);
@ -1676,19 +1691,19 @@ void emac_ptp_snapshot_event_message_enable(confirm_state new_state);
void emac_ptp_snapshot_master_event_enable(confirm_state new_state);
void emac_ptp_clock_node_set(emac_ptp_clock_node_type node);
void emac_ptp_mac_address_filter_enable(confirm_state new_state);
flag_status emac_ptp_flag_get(uint32_t flag);
void emac_ptp_subsecond_increment_set(uint8_t value);
uint32_t emac_ptp_system_second_get(void);
uint32_t emac_ptp_system_subsecond_get(void);
confirm_state emac_ptp_system_time_sign_get(void);
void emac_ptp_system_second_set(uint32_t second);
void emac_ptp_system_subsecond_set(uint32_t subsecond);
void emac_ptp_system_time_sign_set(confirm_state sign);
void emac_ptp_system_time_set(uint32_t sign, uint32_t second, uint32_t subsecond);
void emac_ptp_timestamp_addend_set(uint32_t value);
void emac_ptp_target_second_set(uint32_t value);
void emac_ptp_target_nanosecond_set(uint32_t value);
confirm_state emac_ptp_timestamp_status_get(emac_ptp_timestamp_status_type status);
void emac_ptp_pps_frequency_set(emac_ptp_pps_control_type freq);
flag_status emac_dma_flag_get(uint32_t dma_flag);
flag_status emac_dma_interrupt_flag_get(uint32_t dma_flag);
void emac_dma_flag_clear(uint32_t dma_flag);
/**

3
bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_exint.h
View File

@ -1,8 +1,6 @@
/**
**************************************************************************
* @file at32f403a_407_exint.h
* @version v2.0.9
* @date 2022-04-25
* @brief at32f403a_407 exint header file
**************************************************************************
* Copyright notice & Disclaimer
@ -208,6 +206,7 @@ void exint_default_para_init(exint_init_type *exint_struct);
void exint_init(exint_init_type *exint_struct);
void exint_flag_clear(uint32_t exint_line);
flag_status exint_flag_get(uint32_t exint_line);
flag_status exint_interrupt_flag_get(uint32_t exint_line);
void exint_software_interrupt_event_generate(uint32_t exint_line);
void exint_interrupt_enable(uint32_t exint_line, confirm_state new_state);
void exint_event_enable(uint32_t exint_line, confirm_state new_state);

8
bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_flash.h
View File

@ -1,8 +1,6 @@
/**
**************************************************************************
* @file at32f403a_407_flash.h
* @version v2.0.9
* @date 2022-04-25
* @brief at32f403a_407 flash header file
**************************************************************************
* Copyright notice & Disclaimer
@ -190,7 +188,7 @@ typedef enum
typedef enum
{
FLASH_SPIM_MODEL1 = 0x01, /*!< spim model 1 */
FLASH_SPIM_MODEL2 = 0x02, /*!< spim model 2 */
FLASH_SPIM_MODEL2 = 0x02 /*!< spim model 2 */
} flash_spim_model_type;
/**
@ -700,12 +698,14 @@ uint8_t flash_ssb_status_get(void);
void flash_interrupt_enable(uint32_t flash_int, confirm_state new_state);
void flash_spim_model_select(flash_spim_model_type mode);
void flash_spim_encryption_range_set(uint32_t decode_address);
void flash_spim_dummy_read(void);
flash_status_type flash_spim_mass_program(uint32_t address, uint8_t *buf, uint32_t cnt);
flash_status_type flash_slib_enable(uint32_t pwd, uint16_t start_sector, uint16_t data_start_sector, uint16_t end_sector);
error_status flash_slib_disable(uint32_t pwd);
uint32_t flash_slib_remaining_count_get(void);
flag_status flash_slib_state_get(void);
uint16_t flash_slib_start_sector_get(void);
uint16_t flash_slib_datstart_sector_get(void);
uint16_t flash_slib_datastart_sector_get(void);
uint16_t flash_slib_end_sector_get(void);
uint32_t flash_crc_calibrate(uint32_t start_sector, uint32_t sector_cnt);

8
bsp/at32/libraries/AT32F403A_407_Firmware_Library/drivers/inc/at32f403a_407_gpio.h
View File

@ -1,8 +1,6 @@
/**
**************************************************************************
* @file at32f403a_407_gpio.h
* @version v2.0.9
* @date 2022-04-25
* @brief at32f403a_407 gpio header file
**************************************************************************
* Copyright notice & Disclaimer
@ -215,8 +213,8 @@ extern "C" {
#define SPI3_GMUX_0010 IOMUX_MAKE_VALUE(0x28, 24, 4, 0x02) /*!< spi3_cs/i2s3_ws(pa15), spi3_sck/i2s3_ck(pb3), spi3_miso(pb4), spi3_mosi/i2s3_sd(pb5), i2s3_mck(pb10) */
#define SPI3_GMUX_0011 IOMUX_MAKE_VALUE(0x28, 24, 4, 0x03) /*!< spi3_cs/i2s3_ws(pa4), spi3_sck/i2s3_ck(pc10), spi3_miso(pc11), spi3_mosi/i2s3_sd(pc12), i2s3_mck(pb10) */
#define SPI4_GMUX_0001 IOMUX_MAKE_VALUE(0x28, 28, 4, 0x01) /*!< spi4_cs/i2s4_ws(pe12), spi4_sck/i2s4_ck(pe11), spi4_miso(pe13), spi4_mosi/i2s4_sd(pe14), i2s4_mck(pc8) */
#define SPI4_GMUX_0010 IOMUX_MAKE_VALUE(0x28, 28, 4, 0x02) /*!< spi4_cs/i2s4_ws(pb6), spi4_sck/i2s4_ck(pb7), spi4_miso(pb8), spi4_mosi/i2s4_sd(pb8), i2s4_mck(pc8) */
#define SPI4_GMUX_0011 IOMUX_MAKE_VALUE(0x28, 28, 4, 0x03) /*!< spi4_cs/i2s4_ws(pb6), spi4_sck/i2s4_ck(pb7), spi4_miso(pb8), spi4_mosi/i2s4_sd(pb8), i2s4_mck(pa10) */
#define SPI4_GMUX_0010 IOMUX_MAKE_VALUE(0x28, 28, 4, 0x02) /*!< spi4_cs/i2s4_ws(pb6), spi4_sck/i2s4_ck(pb7), spi4_miso(pb8), spi4_mosi/i2s4_sd(pb9), i2s4_mck(pc8) */
#define SPI4_GMUX_0011 IOMUX_MAKE_VALUE(0x28, 28, 4, 0x03) /*!< spi4_cs/i2s4_ws(pb6), spi4_sck/i2s4_ck(pb7), spi4_miso(pb8), spi4_mosi/i2s4_sd(pb9), i2s4_mck(pa10) */
/**
* @}
@ -914,7 +912,7 @@ uint16_t gpio_output_data_read(gpio_type *gpio_x);
void gpio_bits_set(gpio_type *gpio_x, uint16_t pins);
void gpio_bits_reset(gpio_type *gpio_x, uint16_t pins);
void gpio_bits_write(gpio_type *gpio_x, uint16_t pins, confirm_state bit_state);
void gpio_port_wirte(gpio_type *gpio_x, uint16_t port_value);
void gpio_port_write(gpio_type *gpio_x, uint16_t port_value);
void gpio_pin_wp_config(gpio_type *gpio_x, uint16_t pins);
void gpio_pins_huge_driven_config(gpio_type *gpio_x, uint16_t pins, confirm_state new_state);
void gpio_event_output_config(gpio_port_source_type gpio_port_source, gpio_pins_source_type gpio_pin_source);

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