Merge pull request #4273 from greedyhao/bluetrum
[bsp][bluetrum] add pwm support
This commit is contained in:
Bernard Xiong
GitHub
commit
e210bc7cb6
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@ -107,13 +107,7 @@ CONFIG_FINSH_ARG_MAX=10
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#
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# Device virtual file system
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#
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CONFIG_RT_USING_DFS=y
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CONFIG_DFS_USING_WORKDIR=y
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CONFIG_DFS_FILESYSTEMS_MAX=2
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CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
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CONFIG_DFS_FD_MAX=16
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# CONFIG_RT_USING_DFS_MNTTABLE is not set
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# CONFIG_RT_USING_DFS_ELMFAT is not set
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# CONFIG_RT_USING_DFS is not set
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# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set
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# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
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# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
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@ -122,11 +116,6 @@ CONFIG_DFS_FD_MAX=16
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# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set
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# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set
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# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set
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# CONFIG_RT_USING_DFS_DEVFS is not set
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# CONFIG_RT_USING_DFS_ROMFS is not set
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# CONFIG_RT_USING_DFS_RAMFS is not set
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# CONFIG_RT_USING_DFS_UFFS is not set
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# CONFIG_RT_USING_DFS_JFFS2 is not set
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#
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# Device Drivers
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@ -172,7 +161,6 @@ CONFIG_RT_USING_PIN=y
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#
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CONFIG_RT_USING_LIBC=y
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# CONFIG_RT_USING_PTHREADS is not set
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# CONFIG_RT_USING_POSIX is not set
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# CONFIG_RT_USING_MODULE is not set
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#
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@ -525,6 +513,7 @@ CONFIG_BSP_USING_USB_TO_USART=y
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CONFIG_BSP_USING_UART0=y
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# CONFIG_BSP_USING_SDIO is not set
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# CONFIG_BSP_USING_I2C1 is not set
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# CONFIG_BSP_USING_PWM is not set
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# CONFIG_BSP_USING_WDT is not set
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# CONFIG_BSP_USING_TIM is not set
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@ -31,7 +31,7 @@ ab32vg1-prougen 是 中科蓝讯(Bluetrum) 推出的一款基于 RISC-V 内核
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本 BSP 目前对外设的支持情况如下：
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| **板载外设** | **支持情况** | **备注** |
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| :----------- | :----------: | :---------- |
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| :----------- | :----------: | :---------------------------------------- |
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| USB 转串口 | 支持 | |
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| SD卡 | 支持 | |
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| IRDA | 即将支持 | |
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@ -47,7 +47,7 @@ ab32vg1-prougen 是 中科蓝讯(Bluetrum) 推出的一款基于 RISC-V 内核
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| WDT | 支持 | |
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| FLASH | 即将支持 | |
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| TIMER | 支持 | |
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| PWM | 即将支持 | |
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| PWM | 支持 | LPWM 的 G1 G2 G3 之间是互斥的，只能三选一 |
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| USB Device | 暂不支持 | |
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| USB Host | 暂不支持 | |
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@ -65,6 +65,72 @@ menu "On-chip Peripheral Drivers"
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default 15
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endif
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menuconfig BSP_USING_PWM
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bool "Enable PWM"
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default n
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select RT_USING_PWM
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if BSP_USING_PWM
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menuconfig BSP_USING_T3_PWM
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bool "Enable Timer3 PWM"
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default n
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if BSP_USING_T3_PWM
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config BSP_USING_T3_PWM0
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bool "Enable Timer3 PWM0 (PB0)(Confict with SD card)"
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default n
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endif
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menuconfig BSP_USING_T4_PWM
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bool "Enable Timer4 PWM"
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default n
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if BSP_USING_T4_PWM
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config BSP_USING_T4_PWM1
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bool "Enable Timer4 PWM1 (PA6)(Confit with uart0 rx)"
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default n
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endif
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menuconfig BSP_USING_T5_PWM
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bool "Enable Timer5 PWM"
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default n
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if BSP_USING_T5_PWM
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config BSP_USING_T5_PWM0
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bool "Enable Timer5 PWM2 (PE1)"
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default n
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endif
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menuconfig BSP_USING_LPWM0
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bool "Enable LPWM0"
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default n
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if BSP_USING_LPWM0
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comment "G1, G2 and G3 are mutually exclusive"
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config BSP_USING_LPWM0_G1
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bool "Enable LPWM0 G1 (PE4)"
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default n
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endif
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menuconfig BSP_USING_LPWM1
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bool "Enable LPWM1"
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default n
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if BSP_USING_LPWM1
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comment "G1, G2 and G3 are mutually exclusive"
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config BSP_USING_LPWM1_G3
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bool "Enable LPWM1 G3 (PA1)"
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default n
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endif
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menuconfig BSP_USING_LPWM2
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bool "Enable LPWM2"
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default n
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if BSP_USING_LPWM2
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comment "G1, G2 and G3 are mutually exclusive"
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config BSP_USING_LPWM2_G2
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bool "Enable LPWM2 G2 (PE0)"
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default n
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config BSP_USING_LPWM2_G3
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bool "Enable LPWM2 G3 (PA2)"
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default n
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endif
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endif
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config BSP_USING_WDT
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bool "Enable Watchdog Timer"
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select RT_USING_WDT
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@ -1,9 +1,10 @@
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/*
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* Copyright (c) 2020-2020, BLUETRUM Development Team
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* Copyright (c) 2020-2021, BLUETRUM Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <rtthread.h>
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#include "ab32vg1_hal.h"
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void hal_uart_mspinit(struct uart_handle *huart)
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@ -63,3 +64,60 @@ void hal_sd_mspinit(sd_handle_t hsd)
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hal_gpio_init(GPIOB_BASE, &gpio_init);
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}
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#endif
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void hal_pwm_mspinit(void)
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{
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struct gpio_init gpio_init = {0};
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gpio_init.dir = GPIO_DIR_OUTPUT;
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gpio_init.de = GPIO_DIGITAL;
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#ifdef BSP_USING_T3_PWM0
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gpio_init.pin = GPIO_PIN_0;
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gpio_init.alternate = GPIO_AF_MAP_Gx(TMR3MAP_AF, GPIO_AF_G1);
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gpio_init.af_con = GPIO_AFEN | GPIO_AFCON2;
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hal_gpio_init(GPIOB_BASE, &gpio_init);
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#endif
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#ifdef BSP_USING_T4_PWM1
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gpio_init.pin = GPIO_PIN_6;
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gpio_init.alternate = GPIO_AF_MAP_Gx(TMR4MAP_AF, GPIO_AF_G1);
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gpio_init.af_con = GPIO_AFEN | GPIO_AFCON2;
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hal_gpio_init(GPIOA_BASE, &gpio_init);
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#endif
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#ifdef BSP_USING_T5_PWM0
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gpio_init.pin = GPIO_PIN_1;
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gpio_init.alternate = GPIO_AF_MAP_Gx(TMR5MAP_AF, GPIO_AF_G1);
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gpio_init.af_con = GPIO_AFEN | GPIO_AFCON2;
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hal_gpio_init(GPIOE_BASE, &gpio_init);
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#endif
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#ifdef BSP_USING_LPWM0_G1
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gpio_init.pin = GPIO_PIN_4;
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gpio_init.alternate = GPIO_AF_MAP_Gx(LPWM0MAP_AF, GPIO_AF_G1);
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gpio_init.af_con = GPIO_AFEN | GPIO_AFCON1;
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hal_gpio_init(GPIOE_BASE, &gpio_init);
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#endif
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#ifdef BSP_USING_LPWM1_G3
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gpio_init.pin = GPIO_PIN_1;
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gpio_init.alternate = GPIO_AF_MAP_Gx(LPWM1MAP_AF, GPIO_AF_G3);
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gpio_init.af_con = GPIO_AFEN | GPIO_AFCON1;
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hal_gpio_init(GPIOA_BASE, &gpio_init);
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#endif
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#ifdef BSP_USING_LPWM2_G2
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gpio_init.pin = GPIO_PIN_0;
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gpio_init.alternate = GPIO_AF_MAP_Gx(LPWM2MAP_AF, GPIO_AF_G2);
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gpio_init.af_con = GPIO_AFEN | GPIO_AFCON1;
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hal_gpio_init(GPIOE_BASE, &gpio_init);
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#endif
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#ifdef BSP_USING_LPWM2_G3
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gpio_init.pin = GPIO_PIN_2;
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gpio_init.alternate = GPIO_AF_MAP_Gx(LPWM2MAP_AF, GPIO_AF_G3);
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gpio_init.af_con = GPIO_AFEN | GPIO_AFCON1;
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hal_gpio_init(GPIOA_BASE, &gpio_init);
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#endif
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}
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2006-2020, RT-Thread Development Team
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* Copyright (c) 2020-2021, Bluetrum Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2006-2020, RT-Thread Development Team
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* Copyright (c) 2020-2021, Bluetrum Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2020-2020, Bluetrum Development Team
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* Copyright (c) 2020-2021, Bluetrum Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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@ -61,7 +61,6 @@ SECTIONS
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*components.o (.text*)
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*idle.o (.text*)
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*object.o (.text*)
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*scheduler.o (.text*)
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} > ram1 AT > flash
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.comm __comm_vma : {
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@ -72,11 +72,6 @@
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/* Device virtual file system */
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#define RT_USING_DFS
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#define DFS_USING_WORKDIR
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#define DFS_FILESYSTEMS_MAX 2
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#define DFS_FILESYSTEM_TYPES_MAX 2
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#define DFS_FD_MAX 16
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/* Device Drivers */
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@ -25,6 +25,9 @@ if GetDepend('RT_USING_WDT'):
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if GetDepend('RT_USING_HWTIMER'):
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src += ['drv_hwtimer.c']
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if GetDepend('RT_USING_PWM'):
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src += ['drv_pwm.c']
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group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
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objs = [group]
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@ -5,5 +5,109 @@
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*
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* Change Logs:
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* Date Author Notes
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* 2021/01/18 greedyhao The first version
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* 2021-01-28 greedyhao first version
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*/
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#ifndef __PWM_CONFIG_H__
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#define __PWM_CONFIG_H__
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#include <rtthread.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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enum
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{
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PWMxCON,
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PWMxPR,
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PWMxxDUT,
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PWMyyDUT,
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PWMxCYCNUM,
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PWMxSTEP,
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};
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#define PWM_BASE ((hal_sfr_t)&PWMCON)
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#ifdef BSP_USING_T3_PWM
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#ifndef T3_PWM_CONFIG
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#define T3_PWM_CONFIG \
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{ \
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.pwm_handle = TIM3_BASE, \
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.name = "t3pwm", \
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.channel = 0 \
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}
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#endif /* T3_PWM_CONFIG */
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#endif /* BSP_USING_T3_PWM */
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#ifdef BSP_USING_T4_PWM
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#ifndef T4_PWM_CONFIG
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#define T4_PWM_CONFIG \
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{ \
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.pwm_handle = TIM4_BASE, \
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.name = "t4pwm", \
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.channel = 0 \
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}
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#endif /* T4_PWM_CONFIG */
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#endif /* BSP_USING_T4_PWM */
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#ifdef BSP_USING_T5_PWM
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#ifndef T5_PWM_CONFIG
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#define T5_PWM_CONFIG \
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{ \
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.pwm_handle = TIM5_BASE, \
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.name = "t5pwm", \
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.channel = 0 \
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}
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#endif /* T5_PWM_CONFIG */
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#endif /* BSP_USING_T5_PWM */
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#ifdef BSP_USING_LPWM0
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#ifndef LPWM0_CONFIG
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#define LPWM0_CONFIG \
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{ \
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.pwm_handle = PWM_BASE, \
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.name = "lpwm0", \
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.channel = 0 \
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}
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#endif /* LPWM0_CONFIG */
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#endif /* BSP_USING_LPWM0 */
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#ifdef BSP_USING_LPWM1
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#ifndef LPWM1_CONFIG
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#define LPWM1_CONFIG \
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{ \
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.pwm_handle = PWM_BASE, \
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.name = "lpwm1", \
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.channel = 0 \
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}
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#endif /* LPWM1_CONFIG */
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#endif /* BSP_USING_LPWM1 */
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#ifdef BSP_USING_LPWM2
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#ifndef LPWM2_CONFIG
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#define LPWM2_CONFIG \
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{ \
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.pwm_handle = PWM_BASE, \
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.name = "lpwm2", \
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.channel = 0 \
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}
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#endif /* LPWM2_CONFIG */
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#endif /* BSP_USING_LPWM2 */
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#ifdef BSP_USING_LPWM3
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#ifndef LPWM3_CONFIG
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#define LPWM3_CONFIG \
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{ \
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.pwm_handle = PWM_BASE, \
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.name = "lpwm3", \
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.channel = 0 \
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}
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#endif /* LPWM3_CONFIG */
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#endif /* BSP_USING_LPWM3 */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __PWM_CONFIG_H__ */
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@ -0,0 +1,334 @@
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/*
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* Copyright (c) 2020-2021, Bluetrum Development Team
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*
|
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-01-28 greedyhao first version
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*/
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#include <board.h>
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#ifdef RT_USING_PWM
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#include "pwm_config.h"
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//#define DRV_DEBUG
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#define LOG_TAG "drv.pwm"
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#include <drv_log.h>
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#define MAX_PERIOD 65535
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#define MIN_PERIOD 3
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#define MIN_PULSE 2
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void hal_pwm_mspinit(void);
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enum
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{
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#ifdef BSP_USING_T3_PWM
|
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T3_PWM_INDEX,
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#endif
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#ifdef BSP_USING_T4_PWM
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T4_PWM_INDEX,
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#endif
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#ifdef BSP_USING_T5_PWM
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T5_PWM_INDEX,
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#endif
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#ifdef BSP_USING_LPWM0
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LPWM0_INDEX,
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#endif
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#ifdef BSP_USING_LPWM1
|
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LPWM1_INDEX,
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#endif
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#ifdef BSP_USING_LPWM2
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LPWM2_INDEX,
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#endif
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#ifdef BSP_USING_LPWM3
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LPWM3_INDEX,
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#endif
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};
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struct ab32_pwm
|
||||
{
|
||||
struct rt_device_pwm pwm_device;
|
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hal_sfr_t pwm_handle;
|
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char *name;
|
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rt_uint8_t channel;
|
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rt_uint32_t period;
|
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rt_uint32_t pulse;
|
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};
|
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|
||||
static struct ab32_pwm ab32_pwm_obj[] =
|
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{
|
||||
#ifdef BSP_USING_T3_PWM
|
||||
T3_PWM_CONFIG,
|
||||
#endif
|
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#ifdef BSP_USING_T4_PWM
|
||||
T4_PWM_CONFIG,
|
||||
#endif
|
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#ifdef BSP_USING_T5_PWM
|
||||
T5_PWM_CONFIG,
|
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#endif
|
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#ifdef BSP_USING_LPWM0
|
||||
LPWM0_CONFIG,
|
||||
#endif
|
||||
#ifdef BSP_USING_LPWM1
|
||||
LPWM1_CONFIG,
|
||||
#endif
|
||||
#ifdef BSP_USING_LPWM2
|
||||
LPWM2_CONFIG,
|
||||
#endif
|
||||
#ifdef BSP_USING_LPWM3
|
||||
LPWM3_CONFIG,
|
||||
#endif
|
||||
};
|
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|
||||
static rt_err_t drv_pwm_enable(hal_sfr_t pwm, char *name, struct rt_pwm_configuration *configuration, rt_bool_t enable)
|
||||
{
|
||||
rt_uint8_t channel = configuration->channel;
|
||||
rt_uint8_t pwm_num = 0;
|
||||
|
||||
if (!configuration->complementary) {
|
||||
if (name[0] == 'l') {
|
||||
pwm[PWMxCON] &= ~BIT(5);
|
||||
}
|
||||
} else {
|
||||
if (name[0] == 'l') {
|
||||
pwm[PWMxCON] |= BIT(5);
|
||||
} else {
|
||||
LOG_W("Timer no support complementary PWM output!");
|
||||
}
|
||||
}
|
||||
|
||||
if (!enable) {
|
||||
if (name[0] == 'l') {
|
||||
pwm_num = name[4] - '0';
|
||||
pwm[PWMxCON] &= ~(1 << (pwm_num));
|
||||
} else {
|
||||
if (channel & 0x1) { /* pwm0 */
|
||||
pwm[TMRxCON] &= ~(1 << (9 + 0));
|
||||
}
|
||||
if (channel & 0x2) { /* pwm1 */
|
||||
pwm[TMRxCON] &= ~(1 << (9 + 1));
|
||||
}
|
||||
if (channel & 0x4) { /* pwm2 */
|
||||
pwm[TMRxCON] &= ~(1 << (9 + 2));
|
||||
}
|
||||
}
|
||||
} else {
|
||||
if (name[0] == 'l') {
|
||||
pwm_num = name[4] - '0';
|
||||
pwm[PWMxCON] |= 1 << (pwm_num);
|
||||
} else {
|
||||
if (channel & 0x1) { /* pwm0 */
|
||||
pwm[TMRxCON] |= (1 << (9 + 0));
|
||||
}
|
||||
if (channel & 0x2) { /* pwm1 */
|
||||
pwm[TMRxCON] |= (1 << (9 + 1));
|
||||
}
|
||||
if (channel & 0x4) { /* pwm2 */
|
||||
pwm[TMRxCON] |= (1 << (9 + 2));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg)
|
||||
{
|
||||
struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
|
||||
struct ab32_pwm *pwm_obj = (struct ab32_pwm *)device->parent.user_data;
|
||||
hal_sfr_t pwm = pwm_obj->pwm_handle;
|
||||
char *name = pwm_obj->name;
|
||||
rt_uint8_t channel = configuration->channel;
|
||||
rt_uint32_t period, pulse;
|
||||
rt_uint64_t tim_clock, psc;
|
||||
|
||||
if (name[0] == 'l') {
|
||||
tim_clock = 6500; /* lpwm clock is 6.5MHz */
|
||||
} else {
|
||||
tim_clock = get_sysclk_nhz() / 1000ul;
|
||||
}
|
||||
|
||||
switch (cmd)
|
||||
{
|
||||
case PWMN_CMD_ENABLE:
|
||||
configuration->complementary = RT_TRUE;
|
||||
case PWM_CMD_ENABLE:
|
||||
return drv_pwm_enable(pwm, name, configuration, RT_TRUE);
|
||||
case PWMN_CMD_DISABLE:
|
||||
configuration->complementary = RT_FALSE;
|
||||
case PWM_CMD_DISABLE:
|
||||
return drv_pwm_enable(pwm, name, configuration, RT_FALSE);
|
||||
case PWM_CMD_SET:
|
||||
pwm_obj->pulse = configuration->pulse;
|
||||
pwm_obj->period = configuration->period;
|
||||
|
||||
period = pwm_obj->period * tim_clock / 1000000ul;
|
||||
psc = period / MAX_PERIOD + 1;
|
||||
period = period / psc;
|
||||
|
||||
if (period < MIN_PERIOD)
|
||||
{
|
||||
period = MIN_PERIOD;
|
||||
}
|
||||
|
||||
pulse = pwm_obj->pulse * tim_clock / psc / 1000000ul;
|
||||
if (pulse < MIN_PULSE)
|
||||
{
|
||||
pulse = MIN_PULSE;
|
||||
}
|
||||
else if (pulse > period)
|
||||
{
|
||||
pulse = period;
|
||||
}
|
||||
|
||||
if (name[0] == 'l') {
|
||||
pwm[PWMxPR] = period - 1;
|
||||
switch (name[4] - '0')
|
||||
{
|
||||
case 0: /* lpwm0 */
|
||||
pwm[PWMxxDUT] = pulse - 1;
|
||||
break;
|
||||
case 1: /* lpwm1 */
|
||||
pwm[PWMxxDUT] = (pulse - 1) << 16;
|
||||
break;
|
||||
case 2: /* lpwm2 */
|
||||
pwm[PWMyyDUT] = pulse - 1;
|
||||
break;
|
||||
case 3: /* lpwm3 */
|
||||
pwm[PWMyyDUT] = (pulse - 1) << 16;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
pwm[TMRxPR] = period - 1;
|
||||
if (channel & 0x1) { /* pwm0 */
|
||||
pwm[TMRxDUTY0] = pulse - 1;
|
||||
}
|
||||
if (channel & 0x2) { /* pwm1 */
|
||||
pwm[TMRxDUTY1] = pulse - 1;
|
||||
}
|
||||
if (channel & 0x4) { /* pwm2 */
|
||||
pwm[TMRxDUTY2] = pulse - 1;
|
||||
}
|
||||
}
|
||||
return RT_EOK;
|
||||
case PWM_CMD_GET:
|
||||
configuration->pulse = pwm_obj->pulse;
|
||||
configuration->period = pwm_obj->period;
|
||||
return RT_EOK;
|
||||
default:
|
||||
return -RT_EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
static rt_err_t ab32_hw_pwm_init(struct ab32_pwm *device)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
hal_sfr_t pwm = RT_NULL;
|
||||
char *name = RT_NULL;
|
||||
|
||||
RT_ASSERT(device != RT_NULL);
|
||||
|
||||
pwm = (hal_sfr_t)device->pwm_handle;
|
||||
name = device->name;
|
||||
|
||||
if (name[0] == 'l') {
|
||||
pwm[PWMxCON] = 0;
|
||||
} else {
|
||||
pwm[TMRxCON] &= ~(7 << 9);
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
static void pwm_get_channel(void)
|
||||
{
|
||||
#ifdef BSP_USING_T3_PWM0
|
||||
ab32_pwm_obj[T3_PWM_INDEX].channel |= 1 << 0;
|
||||
#endif
|
||||
#ifdef BSP_USING_T3_PWM1
|
||||
ab32_pwm_obj[T3_PWM_INDEX].channel |= 1 << 1;
|
||||
#endif
|
||||
#ifdef BSP_USING_T3_PWM2
|
||||
ab32_pwm_obj[T3_PWM_INDEX].channel |= 1 << 2;
|
||||
#endif
|
||||
#ifdef BSP_USING_T4_PWM0
|
||||
ab32_pwm_obj[T4_PWM_INDEX].channel |= 1 << 0;
|
||||
#endif
|
||||
#ifdef BSP_USING_T4_PWM1
|
||||
ab32_pwm_obj[T4_PWM_INDEX].channel |= 1 << 1;
|
||||
#endif
|
||||
#ifdef BSP_USING_T4_PWM2
|
||||
ab32_pwm_obj[T4_PWM_INDEX].channel |= 1 << 2;
|
||||
#endif
|
||||
#ifdef BSP_USING_T5_PWM0
|
||||
ab32_pwm_obj[T5_PWM_INDEX].channel |= 1 << 0;
|
||||
#endif
|
||||
#ifdef BSP_USING_T5_PWM1
|
||||
ab32_pwm_obj[T5_PWM_INDEX].channel |= 1 << 1;
|
||||
#endif
|
||||
#ifdef BSP_USING_T5_PWM2
|
||||
ab32_pwm_obj[T5_PWM_INDEX].channel |= 1 << 2;
|
||||
#endif
|
||||
#ifdef BSP_USING_LPWM0
|
||||
ab32_pwm_obj[LPWM0_INDEX].channel |= 1 << 0;
|
||||
#endif
|
||||
#ifdef BSP_USING_LPWM1
|
||||
ab32_pwm_obj[LPWM1_INDEX].channel |= 1 << 0;
|
||||
#endif
|
||||
#ifdef BSP_USING_LPWM2
|
||||
ab32_pwm_obj[LPWM2_INDEX].channel |= 1 << 0;
|
||||
#endif
|
||||
#ifdef BSP_USING_LPWM3
|
||||
ab32_pwm_obj[LPWM3_INDEX].channel |= 1 << 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
static struct rt_pwm_ops drv_ops =
|
||||
{
|
||||
drv_pwm_control
|
||||
};
|
||||
|
||||
static int ab32_pwm_init(void)
|
||||
{
|
||||
int i = 0;
|
||||
int result = RT_EOK;
|
||||
|
||||
pwm_get_channel();
|
||||
hal_pwm_mspinit();
|
||||
|
||||
for (i = 0; i < sizeof(ab32_pwm_obj) / sizeof(ab32_pwm_obj[0]); i++)
|
||||
{
|
||||
/* pwm init */
|
||||
if (ab32_hw_pwm_init(&ab32_pwm_obj[i]) != RT_EOK)
|
||||
{
|
||||
LOG_E("%s init failed", ab32_pwm_obj[i].name);
|
||||
result = -RT_ERROR;
|
||||
goto __exit;
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG_D("%s init success", ab32_pwm_obj[i].name);
|
||||
|
||||
/* register pwm device */
|
||||
if (rt_device_pwm_register(&ab32_pwm_obj[i].pwm_device, ab32_pwm_obj[i].name, &drv_ops, (void *)&ab32_pwm_obj[i]) == RT_EOK)
|
||||
{
|
||||
LOG_D("%s register success", ab32_pwm_obj[i].name);
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG_E("%s register failed", ab32_pwm_obj[i].name);
|
||||
result = -RT_ERROR;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
__exit:
|
||||
return result;
|
||||
}
|
||||
INIT_DEVICE_EXPORT(ab32_pwm_init);
|
||||
#endif /* RT_USING_PWM */
|
||||
|
|
@ -8,6 +8,17 @@
|
|||
#define AB32VG1_HAL_GPIO_EX_H__
|
||||
|
||||
/* Alternate function */
|
||||
#define GPIO_AF_MAP_Gx(AF, Gx) ((uint32_t)((Gx) << (AF)))
|
||||
#define GPIO_AF_MAP_CLR(AF) ((uint32_t)(0xfu << (AF)))
|
||||
|
||||
#define GPIO_AF_G1 (1u)
|
||||
#define GPIO_AF_G2 (2u)
|
||||
#define GPIO_AF_G3 (3u)
|
||||
#define GPIO_AF_G4 (4u)
|
||||
#define GPIO_AF_G5 (5u)
|
||||
#define GPIO_AF_G6 (6u)
|
||||
#define GPIO_AF_G7 (7u)
|
||||
|
||||
/**
|
||||
* UART0:
|
||||
* G1: tx:PA7 rx:PA6
|
||||
|
|
@ -23,16 +34,6 @@
|
|||
* G2: tx:PA4 rx:PA3
|
||||
* G3: tx:PF2 rx:map to tx
|
||||
*/
|
||||
#define GPIO_AF_MAP_Gx(AF, Gx) ((uint32_t)((Gx) << (AF)))
|
||||
#define GPIO_AF_MAP_CLR(AF) ((uint32_t)(0xfu << (AF)))
|
||||
|
||||
#define GPIO_AF_G1 (1u)
|
||||
#define GPIO_AF_G2 (2u)
|
||||
#define GPIO_AF_G3 (3u)
|
||||
#define GPIO_AF_G4 (4u)
|
||||
#define GPIO_AF_G5 (5u)
|
||||
#define GPIO_AF_G6 (6u)
|
||||
#define GPIO_AF_G7 (7u)
|
||||
|
||||
#define UT1RXMAP_AF (28u)
|
||||
#define UT1TXMAP_AF (24u)
|
||||
|
|
@ -46,26 +47,44 @@
|
|||
#define UT1RXMAP_TX ((uint32_t)(0x3u << (UT1RXMAP_AF)))
|
||||
#define UT0RXMAP_TX ((uint32_t)(0x7u << (UT0RXMAP_AF)))
|
||||
|
||||
#define GPIO_HSUART_G1
|
||||
#define GPIO_HSUART_G2
|
||||
#define GPIO_HSUART_G3
|
||||
#define GPIO_HSUART_G4
|
||||
#define GPIO_HSUART_G5
|
||||
#define GPIO_HSUART_G6
|
||||
#define GPIO_HSUART_G7
|
||||
#define GPIO_HSUART_G8
|
||||
#define GPIO_HSUART_G9
|
||||
#define GPIO_HSUART_G10
|
||||
/**
|
||||
* LPWM3:
|
||||
* G1: PE7
|
||||
* G2: PF2
|
||||
* G3: PA3
|
||||
*
|
||||
* LPWM2:
|
||||
* G1: PE6
|
||||
* G2: PE0
|
||||
* G3: PA2
|
||||
*
|
||||
* LPWM1:
|
||||
* G1: PE5
|
||||
* G2: PB4
|
||||
* G3: PA1
|
||||
*
|
||||
* LPWM0:
|
||||
* G1: PE4
|
||||
* G2: PB3
|
||||
* G3: PA0
|
||||
*/
|
||||
#define LPWM3MAP_AF (28u)
|
||||
#define LPWM2MAP_AF (24u)
|
||||
#define LPWM1MAP_AF (20u)
|
||||
#define LPWM0MAP_AF (16u)
|
||||
|
||||
#define GPIO_SPI0_G1
|
||||
#define GPIO_SPI0_G2
|
||||
#define GPIO_SPI0_G3
|
||||
|
||||
#define GPIO_SD0_G1
|
||||
#define GPIO_SD0_G2
|
||||
#define GPIO_SD0_G3
|
||||
#define GPIO_SD0_G4
|
||||
#define GPIO_SD0_G5
|
||||
#define GPIO_SD0_G6
|
||||
/**
|
||||
* TMR5:
|
||||
* G1: PE1 PE2 PE3
|
||||
*
|
||||
* TMR4:
|
||||
* G1: PA5 PA6 PA7
|
||||
*
|
||||
* TMR3:
|
||||
* G1: PB0 PB1 PB2
|
||||
*/
|
||||
#define TMR5MAP_AF (16u)
|
||||
#define TMR4MAP_AF (12u)
|
||||
#define TMR3MAP_AF ( 8u)
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue