Perfect the AT45DB driver
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@332 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
wuyangyong
parent
d088d60152
commit
e1f2525416
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@ -1,51 +1,72 @@
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#include "stm32f10x.h"
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#include "usb_lib.h"
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#include "usb_istr.h"
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#include "hw_config.h"
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#include "usb_pwr.h"
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#include "rtthread.h"
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extern uint32_t Mass_Memory_Size[3];
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extern uint32_t Mass_Block_Size[3];
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extern uint32_t Mass_Block_Count[3];
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extern rt_device_t dev_sdio;
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extern rt_device_t dev_spi_flash;
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#include <finsh.h>
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#include "sdcard.h"
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void USB_cable(void)
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{
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rt_device_t dev = RT_NULL;
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SD_CardInfo * sdio_info = RT_NULL;
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dev = rt_device_find("sd0");
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/* SPI_FLASH */
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dev_spi_flash = rt_device_find("spi0");
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Mass_Block_Size[1] = 512;
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Mass_Block_Count[1] = 4096;
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Mass_Memory_Size[1] = 4096*512;
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if(dev != RT_NULL)
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{
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dev_sdio = dev;
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sdio_info = (SD_CardInfo *)dev->private;
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Mass_Memory_Size[0] = sdio_info->CardCapacity;
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Mass_Block_Size[0] = sdio_info->CardBlockSize;
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Mass_Block_Count[0] = Mass_Memory_Size[0] / Mass_Block_Size[0];
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}
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else
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{
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rt_kprintf("\r\nNo find the device sd0 !!!!");
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}
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/* 3:NAND */
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/* usb msc up*/
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Set_System();
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Set_USBClock();
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USB_Interrupts_Config();
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USB_Init();
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}
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FINSH_FUNCTION_EXPORT(USB_cable, cable_the_usb);
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#include "stm32f10x.h"
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#include "usb_lib.h"
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#include "usb_istr.h"
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#include "hw_config.h"
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#include "usb_pwr.h"
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#include "rtthread.h"
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extern uint32_t Mass_Memory_Size[3];
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extern uint32_t Mass_Block_Size[3];
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extern uint32_t Mass_Block_Count[3];
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extern rt_device_t dev_sdio;
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extern rt_device_t dev_spi_flash;
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#include <finsh.h>
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#include "sdcard.h"
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void USB_cable(void)
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{
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rt_device_t dev = RT_NULL;
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SD_CardInfo * sdio_info = RT_NULL;
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dev = rt_device_find("sd0");
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{
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SPI_InitTypeDef SPI_InitStructure;
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/*------------------------ SPI1 configuration ------------------------*/
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SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;//SPI_Direction_1Line_Tx;
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SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
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SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
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SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
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SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;
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SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
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SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_16;/* 72M/64=1.125M */
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SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
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SPI_InitStructure.SPI_CRCPolynomial = 7;
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SPI_I2S_DeInit(SPI1);
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SPI_Init(SPI1, &SPI_InitStructure);
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/* Enable SPI_MASTER */
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SPI_Cmd(SPI1, ENABLE);
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SPI_CalculateCRC(SPI1, DISABLE);
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}
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/* SPI_FLASH */
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dev_spi_flash = rt_device_find("spi0");
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Mass_Block_Size[1] = 512;
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Mass_Block_Count[1] = 4096;
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Mass_Memory_Size[1] = 4096*512;
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if(dev != RT_NULL)
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{
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dev_sdio = dev;
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sdio_info = (SD_CardInfo *)dev->private;
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Mass_Memory_Size[0] = sdio_info->CardCapacity;
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Mass_Block_Size[0] = sdio_info->CardBlockSize;
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Mass_Block_Count[0] = Mass_Memory_Size[0] / Mass_Block_Size[0];
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}
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else
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{
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rt_kprintf("\r\nNo find the device sd0 !!!!");
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}
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/* 3:NAND */
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/* usb msc up*/
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Set_System();
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Set_USBClock();
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USB_Interrupts_Config();
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USB_Init();
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}
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FINSH_FUNCTION_EXPORT(USB_cable, cable_the_usb);
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@ -1,369 +1,371 @@
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/*
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* File : board.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006 - 2009 RT-Thread Develop Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2006-08-23 Bernard first implementation
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include "stm32f10x.h"
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#include "board.h"
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static void rt_hw_console_init(void);
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/**
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* @addtogroup STM32
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*/
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/*@{*/
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/*******************************************************************************
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* Function Name : RCC_Configuration
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* Description : Configures the different system clocks.
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* Input : None
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* Output : None
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* Return : None
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*******************************************************************************/
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void RCC_Configuration(void)
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{
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ErrorStatus HSEStartUpStatus;
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/* RCC system reset(for debug purpose) */
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RCC_DeInit();
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/* Enable HSE */
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RCC_HSEConfig(RCC_HSE_ON);
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/* Wait till HSE is ready */
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HSEStartUpStatus = RCC_WaitForHSEStartUp();
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if (HSEStartUpStatus == SUCCESS)
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{
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/* HCLK = SYSCLK */
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RCC_HCLKConfig(RCC_SYSCLK_Div1);
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/* PCLK2 = HCLK */
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RCC_PCLK2Config(RCC_HCLK_Div1);
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/* PCLK1 = HCLK/2 */
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RCC_PCLK1Config(RCC_HCLK_Div2);
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/* Flash 2 wait state */
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FLASH_SetLatency(FLASH_Latency_2);
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/* Enable Prefetch Buffer */
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FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
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/* PLLCLK = 8MHz * 9 = 72 MHz */
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RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9);
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/* Enable PLL */
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RCC_PLLCmd(ENABLE);
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/* Wait till PLL is ready */
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while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET) ;
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/* Select PLL as system clock source */
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RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
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/* Wait till PLL is used as system clock source */
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while (RCC_GetSYSCLKSource() != 0x08) ;
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}
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}
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/*******************************************************************************
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* Function Name : NVIC_Configuration
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* Description : Configures Vector Table base location.
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* Input : None
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* Output : None
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* Return : None
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*******************************************************************************/
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void NVIC_Configuration(void)
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{
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#ifdef VECT_TAB_RAM
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/* Set the Vector Table base location at 0x20000000 */
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NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
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#else /* VECT_TAB_FLASH */
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/* Set the Vector Table base location at 0x08000000 */
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NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
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#endif
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/*
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* set priority group:
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* 2 bits for pre-emption priority
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* 2 bits for subpriority
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*/
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NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
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}
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/*******************************************************************************
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* Function Name : SysTick_Configuration
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* Description : Configures the SysTick for OS tick.
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* Input : None
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* Output : None
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* Return : None
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*******************************************************************************/
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void SysTick_Configuration(void)
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{
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RCC_ClocksTypeDef rcc_clocks;
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rt_uint32_t cnts;
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RCC_GetClocksFreq(&rcc_clocks);
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cnts = (rt_uint32_t)rcc_clocks.HCLK_Frequency / RT_TICK_PER_SECOND;
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SysTick_Config(cnts);
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SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK);
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}
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extern void rt_hw_interrupt_thread_switch(void);
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/**
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* This is the timer interrupt service routine.
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*
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*/
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void rt_hw_timer_handler(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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rt_tick_increase();
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/* leave interrupt */
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rt_interrupt_leave();
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}
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/* NAND Flash */
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#include "fsmc_nand.h"
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/**
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* This function will initial STM32 Radio board.
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*/
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extern void FSMC_SRAM_Init(void);
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void rt_hw_board_init()
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{
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NAND_IDTypeDef NAND_ID;
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/* Configure the system clocks */
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RCC_Configuration();
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/* DM9000A */
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{
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GPIO_InitTypeDef GPIO_InitStructure;
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RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOE,ENABLE);
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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GPIO_Init(GPIOE,&GPIO_InitStructure);
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GPIO_SetBits(GPIOE,GPIO_Pin_5);
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}
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/* NVIC Configuration */
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NVIC_Configuration();
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/* Configure the SysTick */
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SysTick_Configuration();
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/* Console Initialization*/
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rt_hw_console_init();
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/* FSMC Initialization */
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FSMC_NAND_Init();
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/* NAND read ID command */
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FSMC_NAND_ReadID(&NAND_ID);
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rt_kprintf("\r\n\r\nRead the NAND ID:%02X%02X%02X%02X",NAND_ID.Maker_ID,NAND_ID.Device_ID,NAND_ID.Third_ID,NAND_ID.Fourth_ID);
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/* SRAM init */
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RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
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FSMC_SRAM_Init();
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/* memtest */
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{
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unsigned char * p_extram = (unsigned char *)0x68000000;
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unsigned int temp;
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rt_kprintf("\r\nmem testing....");
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for(temp=0; temp<0x80000; temp++)
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{
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*p_extram++ = (unsigned char)temp;
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}
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p_extram = (unsigned char *)0x68000000;
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for(temp=0; temp<0x80000; temp++)
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{
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if( *p_extram++ != (unsigned char)temp )
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{
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rt_kprintf("\rmemtest fail @ %08X\r\nsystem halt!!!!!",(unsigned int)p_extram);
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while(1);
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}
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}
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rt_kprintf("\rmem test pass!!\r\n");
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}/* memtest */
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{
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/* PC6 for SDCard Rst */
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GPIO_InitTypeDef GPIO_InitStructure;
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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GPIO_Init(GPIOC,&GPIO_InitStructure);
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GPIO_SetBits(GPIOC,GPIO_Pin_6);
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}
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/* SPI1 config */
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{
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GPIO_InitTypeDef GPIO_InitStructure;
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SPI_InitTypeDef SPI_InitStructure;
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/* Enable SPI1 Periph clock */
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RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA
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| RCC_APB2Periph_AFIO | RCC_APB2Periph_SPI1,
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ENABLE);
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/* Configure SPI1 pins: PA5-SCK, PA6-MISO and PA7-MOSI */
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
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GPIO_Init(GPIOA, &GPIO_InitStructure);
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/*------------------------ SPI1 configuration ------------------------*/
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SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;//SPI_Direction_1Line_Tx;
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SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
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SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
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SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
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SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;
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SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
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SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_64;/* 72M/64=1.125M */
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SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
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SPI_InitStructure.SPI_CRCPolynomial = 7;
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SPI_Init(SPI1, &SPI_InitStructure);
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/* Enable SPI_MASTER */
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SPI_Cmd(SPI1, ENABLE);
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SPI_CalculateCRC(SPI1, DISABLE);
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}
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}/* rt_hw_board_init */
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#if STM32_CONSOLE_USART == 1
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#define CONSOLE_RX_PIN GPIO_Pin_9
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#define CONSOLE_TX_PIN GPIO_Pin_10
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#define CONSOLE_GPIO GPIOA
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#define CONSOLE_USART USART1
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#elif STM32_CONSOLE_USART == 2
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#if defined(STM32_LD) || defined(STM32_MD)
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#define CONSOLE_RX_PIN GPIO_Pin_6
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#define CONSOLE_TX_PIN GPIO_Pin_5
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#define CONSOLE_GPIO GPIOD
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#elif defined(STM32_HD)
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#define CONSOLE_RX_PIN GPIO_Pin_3
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#define CONSOLE_TX_PIN GPIO_Pin_2
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#define CONSOLE_GPIO GPIOA
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#endif
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#define CONSOLE_USART USART2
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#elif STM32_CONSOLE_USART == 2
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#define CONSOLE_RX_PIN GPIO_Pin_11
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#define CONSOLE_TX_PIN GPIO_Pin_10
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#define CONSOLE_GPIO GPIOB
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#define CONSOLE_USART USART3
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#endif
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/* init console to support rt_kprintf */
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static void rt_hw_console_init()
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{
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/* Enable USART1 and GPIOA clocks */
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RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1
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| RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOC
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| RCC_APB2Periph_GPIOF, ENABLE);
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#if STM32_CONSOLE_USART == 0
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#else
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/* GPIO configuration */
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{
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GPIO_InitTypeDef GPIO_InitStructure;
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/* Configure USART1 Tx (PA.09) as alternate function push-pull */
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GPIO_InitStructure.GPIO_Pin = CONSOLE_RX_PIN;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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GPIO_Init(CONSOLE_GPIO, &GPIO_InitStructure);
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/* Configure USART1 Rx (PA.10) as input floating */
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GPIO_InitStructure.GPIO_Pin = CONSOLE_TX_PIN;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
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GPIO_Init(CONSOLE_GPIO, &GPIO_InitStructure);
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}
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/* USART configuration */
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{
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USART_InitTypeDef USART_InitStructure;
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/* USART configured as follow:
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- BaudRate = 115200 baud
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- Word Length = 8 Bits
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- One Stop Bit
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- No parity
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- Hardware flow control disabled (RTS and CTS signals)
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- Receive and transmit enabled
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- USART Clock disabled
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- USART CPOL: Clock is active low
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- USART CPHA: Data is captured on the middle
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- USART LastBit: The clock pulse of the last data bit is not output to
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the SCLK pin
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*/
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USART_InitStructure.USART_BaudRate = 115200;
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USART_InitStructure.USART_WordLength = USART_WordLength_8b;
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USART_InitStructure.USART_StopBits = USART_StopBits_1;
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USART_InitStructure.USART_Parity = USART_Parity_No;
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USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
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USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
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USART_Init(CONSOLE_USART, &USART_InitStructure);
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/* Enable USART1 */
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USART_Cmd(CONSOLE_USART, ENABLE);
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}
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#endif
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}
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/* write one character to serial, must not trigger interrupt */
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static void rt_hw_console_putc(const char c)
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{
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/*
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to be polite with serial console add a line feed
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to the carriage return character
|
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*/
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if (c=='\n')rt_hw_console_putc('\r');
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while (!(CONSOLE_USART->SR & USART_FLAG_TXE));
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CONSOLE_USART->DR = (c & 0x1FF);
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}
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/**
|
||||
* This function is used by rt_kprintf to display a string on console.
|
||||
*
|
||||
* @param str the displayed string
|
||||
*/
|
||||
void rt_hw_console_output(const char* str)
|
||||
{
|
||||
#if STM32_CONSOLE_USART == 0
|
||||
/* no console */
|
||||
#else
|
||||
while (*str)
|
||||
{
|
||||
rt_hw_console_putc (*str++);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
/*
|
||||
* File : board.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006 - 2009 RT-Thread Develop Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rt-thread.org/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2006-08-23 Bernard first implementation
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
|
||||
#include "stm32f10x.h"
|
||||
#include "board.h"
|
||||
|
||||
static void rt_hw_console_init(void);
|
||||
|
||||
/**
|
||||
* @addtogroup STM32
|
||||
*/
|
||||
|
||||
/*@{*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : RCC_Configuration
|
||||
* Description : Configures the different system clocks.
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void RCC_Configuration(void)
|
||||
{
|
||||
ErrorStatus HSEStartUpStatus;
|
||||
|
||||
/* RCC system reset(for debug purpose) */
|
||||
RCC_DeInit();
|
||||
|
||||
/* Enable HSE */
|
||||
RCC_HSEConfig(RCC_HSE_ON);
|
||||
|
||||
/* Wait till HSE is ready */
|
||||
HSEStartUpStatus = RCC_WaitForHSEStartUp();
|
||||
|
||||
if (HSEStartUpStatus == SUCCESS)
|
||||
{
|
||||
/* HCLK = SYSCLK */
|
||||
RCC_HCLKConfig(RCC_SYSCLK_Div1);
|
||||
|
||||
/* PCLK2 = HCLK */
|
||||
RCC_PCLK2Config(RCC_HCLK_Div1);
|
||||
/* PCLK1 = HCLK/2 */
|
||||
RCC_PCLK1Config(RCC_HCLK_Div2);
|
||||
|
||||
/* Flash 2 wait state */
|
||||
FLASH_SetLatency(FLASH_Latency_2);
|
||||
/* Enable Prefetch Buffer */
|
||||
FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
|
||||
|
||||
/* PLLCLK = 8MHz * 9 = 72 MHz */
|
||||
RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC_PLLCmd(ENABLE);
|
||||
|
||||
/* Wait till PLL is ready */
|
||||
while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET) ;
|
||||
|
||||
/* Select PLL as system clock source */
|
||||
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
|
||||
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while (RCC_GetSYSCLKSource() != 0x08) ;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : NVIC_Configuration
|
||||
* Description : Configures Vector Table base location.
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void NVIC_Configuration(void)
|
||||
{
|
||||
#ifdef VECT_TAB_RAM
|
||||
/* Set the Vector Table base location at 0x20000000 */
|
||||
NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
|
||||
#else /* VECT_TAB_FLASH */
|
||||
/* Set the Vector Table base location at 0x08000000 */
|
||||
NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* set priority group:
|
||||
* 2 bits for pre-emption priority
|
||||
* 2 bits for subpriority
|
||||
*/
|
||||
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SysTick_Configuration
|
||||
* Description : Configures the SysTick for OS tick.
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void SysTick_Configuration(void)
|
||||
{
|
||||
RCC_ClocksTypeDef rcc_clocks;
|
||||
rt_uint32_t cnts;
|
||||
|
||||
RCC_GetClocksFreq(&rcc_clocks);
|
||||
|
||||
cnts = (rt_uint32_t)rcc_clocks.HCLK_Frequency / RT_TICK_PER_SECOND;
|
||||
|
||||
SysTick_Config(cnts);
|
||||
SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK);
|
||||
}
|
||||
|
||||
extern void rt_hw_interrupt_thread_switch(void);
|
||||
/**
|
||||
* This is the timer interrupt service routine.
|
||||
*
|
||||
*/
|
||||
void rt_hw_timer_handler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
rt_tick_increase();
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
/* NAND Flash */
|
||||
#include "fsmc_nand.h"
|
||||
|
||||
/**
|
||||
* This function will initial STM32 Radio board.
|
||||
*/
|
||||
extern void FSMC_SRAM_Init(void);
|
||||
void rt_hw_board_init()
|
||||
{
|
||||
NAND_IDTypeDef NAND_ID;
|
||||
|
||||
/* Configure the system clocks */
|
||||
RCC_Configuration();
|
||||
|
||||
/* DM9000A */
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOE,ENABLE);
|
||||
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
GPIO_Init(GPIOE,&GPIO_InitStructure);
|
||||
GPIO_SetBits(GPIOE,GPIO_Pin_5);
|
||||
}
|
||||
|
||||
/* NVIC Configuration */
|
||||
NVIC_Configuration();
|
||||
|
||||
/* Configure the SysTick */
|
||||
SysTick_Configuration();
|
||||
|
||||
/* Console Initialization*/
|
||||
rt_hw_console_init();
|
||||
|
||||
/* FSMC Initialization */
|
||||
FSMC_NAND_Init();
|
||||
|
||||
/* NAND read ID command */
|
||||
FSMC_NAND_ReadID(&NAND_ID);
|
||||
rt_kprintf("\r\n\r\nRead the NAND ID:%02X%02X%02X%02X",NAND_ID.Maker_ID,NAND_ID.Device_ID,NAND_ID.Third_ID,NAND_ID.Fourth_ID);
|
||||
|
||||
/* SRAM init */
|
||||
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
|
||||
FSMC_SRAM_Init();
|
||||
|
||||
/* memtest */
|
||||
{
|
||||
unsigned char * p_extram = (unsigned char *)0x68000000;
|
||||
unsigned int temp;
|
||||
|
||||
rt_kprintf("\r\nmem testing....");
|
||||
for(temp=0; temp<0x80000; temp++)
|
||||
{
|
||||
*p_extram++ = (unsigned char)temp;
|
||||
}
|
||||
|
||||
p_extram = (unsigned char *)0x68000000;
|
||||
for(temp=0; temp<0x80000; temp++)
|
||||
{
|
||||
if( *p_extram++ != (unsigned char)temp )
|
||||
{
|
||||
rt_kprintf("\rmemtest fail @ %08X\r\nsystem halt!!!!!",(unsigned int)p_extram);
|
||||
while(1);
|
||||
}
|
||||
}
|
||||
rt_kprintf("\rmem test pass!!\r\n");
|
||||
}/* memtest */
|
||||
|
||||
{
|
||||
/* PC6 for SDCard Rst */
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
GPIO_Init(GPIOC,&GPIO_InitStructure);
|
||||
GPIO_SetBits(GPIOC,GPIO_Pin_6);
|
||||
}
|
||||
|
||||
/* SPI1 config */
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
SPI_InitTypeDef SPI_InitStructure;
|
||||
|
||||
/* Enable SPI1 Periph clock */
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA
|
||||
| RCC_APB2Periph_AFIO | RCC_APB2Periph_SPI1,
|
||||
ENABLE);
|
||||
|
||||
/* Configure SPI1 pins: PA5-SCK, PA6-MISO and PA7-MOSI */
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
|
||||
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||
|
||||
/*------------------------ SPI1 configuration ------------------------*/
|
||||
SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;//SPI_Direction_1Line_Tx;
|
||||
SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
|
||||
SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
|
||||
SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
|
||||
SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;
|
||||
SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
|
||||
SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_64;/* 72M/64=1.125M */
|
||||
SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
|
||||
SPI_InitStructure.SPI_CRCPolynomial = 7;
|
||||
|
||||
SPI_I2S_DeInit(SPI1);
|
||||
SPI_Init(SPI1, &SPI_InitStructure);
|
||||
|
||||
/* Enable SPI_MASTER */
|
||||
SPI_Cmd(SPI1, ENABLE);
|
||||
SPI_CalculateCRC(SPI1, DISABLE);
|
||||
}
|
||||
|
||||
}/* rt_hw_board_init */
|
||||
|
||||
#if STM32_CONSOLE_USART == 1
|
||||
#define CONSOLE_RX_PIN GPIO_Pin_9
|
||||
#define CONSOLE_TX_PIN GPIO_Pin_10
|
||||
#define CONSOLE_GPIO GPIOA
|
||||
#define CONSOLE_USART USART1
|
||||
#elif STM32_CONSOLE_USART == 2
|
||||
|
||||
#if defined(STM32_LD) || defined(STM32_MD)
|
||||
#define CONSOLE_RX_PIN GPIO_Pin_6
|
||||
#define CONSOLE_TX_PIN GPIO_Pin_5
|
||||
#define CONSOLE_GPIO GPIOD
|
||||
#elif defined(STM32_HD)
|
||||
#define CONSOLE_RX_PIN GPIO_Pin_3
|
||||
#define CONSOLE_TX_PIN GPIO_Pin_2
|
||||
#define CONSOLE_GPIO GPIOA
|
||||
#endif
|
||||
|
||||
#define CONSOLE_USART USART2
|
||||
#elif STM32_CONSOLE_USART == 2
|
||||
#define CONSOLE_RX_PIN GPIO_Pin_11
|
||||
#define CONSOLE_TX_PIN GPIO_Pin_10
|
||||
#define CONSOLE_GPIO GPIOB
|
||||
#define CONSOLE_USART USART3
|
||||
#endif
|
||||
|
||||
/* init console to support rt_kprintf */
|
||||
static void rt_hw_console_init()
|
||||
{
|
||||
/* Enable USART1 and GPIOA clocks */
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1
|
||||
| RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOC
|
||||
| RCC_APB2Periph_GPIOF, ENABLE);
|
||||
|
||||
#if STM32_CONSOLE_USART == 0
|
||||
#else
|
||||
/* GPIO configuration */
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
|
||||
/* Configure USART1 Tx (PA.09) as alternate function push-pull */
|
||||
GPIO_InitStructure.GPIO_Pin = CONSOLE_RX_PIN;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
GPIO_Init(CONSOLE_GPIO, &GPIO_InitStructure);
|
||||
|
||||
/* Configure USART1 Rx (PA.10) as input floating */
|
||||
GPIO_InitStructure.GPIO_Pin = CONSOLE_TX_PIN;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
|
||||
GPIO_Init(CONSOLE_GPIO, &GPIO_InitStructure);
|
||||
}
|
||||
|
||||
/* USART configuration */
|
||||
{
|
||||
USART_InitTypeDef USART_InitStructure;
|
||||
|
||||
/* USART configured as follow:
|
||||
- BaudRate = 115200 baud
|
||||
- Word Length = 8 Bits
|
||||
- One Stop Bit
|
||||
- No parity
|
||||
- Hardware flow control disabled (RTS and CTS signals)
|
||||
- Receive and transmit enabled
|
||||
- USART Clock disabled
|
||||
- USART CPOL: Clock is active low
|
||||
- USART CPHA: Data is captured on the middle
|
||||
- USART LastBit: The clock pulse of the last data bit is not output to
|
||||
the SCLK pin
|
||||
*/
|
||||
USART_InitStructure.USART_BaudRate = 115200;
|
||||
USART_InitStructure.USART_WordLength = USART_WordLength_8b;
|
||||
USART_InitStructure.USART_StopBits = USART_StopBits_1;
|
||||
USART_InitStructure.USART_Parity = USART_Parity_No;
|
||||
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
|
||||
USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
|
||||
USART_Init(CONSOLE_USART, &USART_InitStructure);
|
||||
/* Enable USART1 */
|
||||
USART_Cmd(CONSOLE_USART, ENABLE);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
/* write one character to serial, must not trigger interrupt */
|
||||
static void rt_hw_console_putc(const char c)
|
||||
{
|
||||
/*
|
||||
to be polite with serial console add a line feed
|
||||
to the carriage return character
|
||||
*/
|
||||
if (c=='\n')rt_hw_console_putc('\r');
|
||||
|
||||
while (!(CONSOLE_USART->SR & USART_FLAG_TXE));
|
||||
CONSOLE_USART->DR = (c & 0x1FF);
|
||||
}
|
||||
|
||||
/**
|
||||
* This function is used by rt_kprintf to display a string on console.
|
||||
*
|
||||
* @param str the displayed string
|
||||
*/
|
||||
void rt_hw_console_output(const char* str)
|
||||
{
|
||||
#if STM32_CONSOLE_USART == 0
|
||||
/* no console */
|
||||
#else
|
||||
while (*str)
|
||||
{
|
||||
rt_hw_console_putc (*str++);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
|
|
|
|||
|
|
@ -1,199 +1,190 @@
|
|||
#include <stm32f10x.h>
|
||||
//#include "spi_flash.h"
|
||||
#include <string.h>
|
||||
|
||||
extern unsigned char SPI_WriteByte(unsigned char data);
|
||||
|
||||
/********************** hardware *************************************/
|
||||
/* SPI_FLASH_CS PA4 */
|
||||
/* SPI_FLASH_RST PA3 */
|
||||
#define FLASH_RST_0() GPIO_ResetBits(GPIOA,GPIO_Pin_3)
|
||||
#define FLASH_RST_1() GPIO_SetBits(GPIOA,GPIO_Pin_3)
|
||||
|
||||
#define FLASH_CS_0() GPIO_ResetBits(GPIOA,GPIO_Pin_4)
|
||||
#define FLASH_CS_1() GPIO_SetBits(GPIOA,GPIO_Pin_4)
|
||||
/********************** hardware *************************************/
|
||||
|
||||
static void GPIO_Configuration(void)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA,ENABLE);
|
||||
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_3;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
GPIO_Init(GPIOA,&GPIO_InitStructure);
|
||||
|
||||
FLASH_RST_0(); // RESET
|
||||
FLASH_RST_1();
|
||||
}
|
||||
|
||||
static unsigned char SPI_HostReadByte(void)
|
||||
{
|
||||
return SPI_WriteByte(0x00);
|
||||
}
|
||||
|
||||
static void SPI_HostWriteByte(unsigned char wByte)
|
||||
{
|
||||
SPI_WriteByte(wByte);
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/*Status Register Format: */
|
||||
/* ----------------------------------------------------------------------- */
|
||||
/* | bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 | */
|
||||
/* |--------|--------|--------|--------|--------|--------|--------|--------| */
|
||||
/* |RDY/BUSY| COMP | 0 | 1 | 1 | 1 | X | X | */
|
||||
/* ----------------------------------------------------------------------- */
|
||||
/* bit7 - 忙标记，0为忙1为不忙。 */
|
||||
/* 当Status Register的位0移出之后，接下来的时钟脉冲序列将使SPI器件继续*/
|
||||
/* 将最新的状态字节送出。 */
|
||||
/* bit6 - 标记最近一次Main Memory Page和Buffer的比较结果，0相同，1不同。 */
|
||||
/* bit5 */
|
||||
/* bit4 */
|
||||
/* bit3 */
|
||||
/* bit2 - 这4位用来标记器件密度，对于AT45DB041B，这4位应该是0111，一共能标记 */
|
||||
/* 16种不同密度的器件。 */
|
||||
/* bit1 */
|
||||
/* bit0 - 这2位暂时无效 */
|
||||
/******************************************************************************/
|
||||
static unsigned char AT45DB_StatusRegisterRead(void)
|
||||
{
|
||||
unsigned char i;
|
||||
|
||||
FLASH_CS_0();
|
||||
SPI_HostWriteByte(0xd7);
|
||||
i=SPI_HostReadByte();
|
||||
FLASH_CS_1();
|
||||
|
||||
return i;
|
||||
}
|
||||
|
||||
static void wait_busy(void)
|
||||
{
|
||||
unsigned int i=0;
|
||||
while (i++<2000)
|
||||
{
|
||||
if (AT45DB_StatusRegisterRead()&0x80)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void read_page(unsigned int page,unsigned char * pHeader)
|
||||
{
|
||||
unsigned int i=0;
|
||||
|
||||
wait_busy();
|
||||
|
||||
FLASH_CS_0();
|
||||
SPI_HostWriteByte(0x53);
|
||||
SPI_HostWriteByte((unsigned char)(page >> 6));
|
||||
SPI_HostWriteByte((unsigned char)(page << 2));
|
||||
SPI_HostWriteByte(0x00);
|
||||
FLASH_CS_1();
|
||||
|
||||
wait_busy();
|
||||
|
||||
FLASH_CS_0();
|
||||
SPI_HostWriteByte(0xD4);
|
||||
SPI_HostWriteByte(0x00);
|
||||
SPI_HostWriteByte(0x00);
|
||||
SPI_HostWriteByte(0x00);
|
||||
SPI_HostWriteByte(0x00);
|
||||
for (i=0; i<512; i++)
|
||||
{
|
||||
*pHeader++ = SPI_HostReadByte();
|
||||
}
|
||||
FLASH_CS_1();
|
||||
|
||||
}
|
||||
|
||||
static void write_page(unsigned int page,unsigned char * pHeader)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
wait_busy();
|
||||
|
||||
FLASH_CS_0();
|
||||
SPI_HostWriteByte(0x87);
|
||||
SPI_HostWriteByte(0);
|
||||
SPI_HostWriteByte(0);
|
||||
SPI_HostWriteByte(0);
|
||||
for(i=0; i<512; i++)
|
||||
{
|
||||
SPI_HostWriteByte(*pHeader++);
|
||||
}
|
||||
FLASH_CS_1();
|
||||
|
||||
wait_busy();
|
||||
|
||||
FLASH_CS_0();
|
||||
SPI_HostWriteByte(0x86);
|
||||
SPI_HostWriteByte((unsigned char)(page>>6));
|
||||
SPI_HostWriteByte((unsigned char)(page<<2));
|
||||
SPI_HostWriteByte(0x00);
|
||||
FLASH_CS_1();
|
||||
}
|
||||
|
||||
|
||||
#include <rtthread.h>
|
||||
/* SPI DEVICE */
|
||||
static struct rt_device spi_flash_device;
|
||||
|
||||
/* RT-Thread Device Driver Interface */
|
||||
static rt_err_t rt_spi_flash_init(rt_device_t dev)
|
||||
{
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t rt_spi_flash_open(rt_device_t dev, rt_uint16_t oflag)
|
||||
{
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t rt_spi_flash_close(rt_device_t dev)
|
||||
{
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t rt_spi_flash_control(rt_device_t dev, rt_uint8_t cmd, void *args)
|
||||
{
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_size_t rt_spi_flash_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
|
||||
{
|
||||
/* only supply single block read: block size 512Byte */
|
||||
read_page(pos/512,buffer);
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_size_t rt_spi_flash_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
|
||||
{
|
||||
/* only supply single block write: block size 512Byte */
|
||||
write_page(pos/512,(unsigned char*)buffer);
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
void rt_hw_spi_flash_init(void)
|
||||
{
|
||||
GPIO_Configuration();
|
||||
|
||||
/* register spi_flash device */
|
||||
spi_flash_device.init = rt_spi_flash_init;
|
||||
spi_flash_device.open = rt_spi_flash_open;
|
||||
spi_flash_device.close = rt_spi_flash_close;
|
||||
spi_flash_device.read = rt_spi_flash_read;
|
||||
spi_flash_device.write = rt_spi_flash_write;
|
||||
spi_flash_device.control = rt_spi_flash_control;
|
||||
|
||||
/* no private */
|
||||
spi_flash_device.private = RT_NULL;
|
||||
|
||||
rt_device_register(&spi_flash_device, "spi0",
|
||||
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE);
|
||||
}
|
||||
#include <stm32f10x.h>
|
||||
#include "spi_flash.h"
|
||||
|
||||
extern unsigned char SPI_WriteByte(unsigned char data);
|
||||
|
||||
/********************** hardware *************************************/
|
||||
/* SPI_FLASH_CS PA4 */
|
||||
/* SPI_FLASH_RST PA3 */
|
||||
#define FLASH_RST_0() GPIO_ResetBits(GPIOA,GPIO_Pin_3)
|
||||
#define FLASH_RST_1() GPIO_SetBits(GPIOA,GPIO_Pin_3)
|
||||
|
||||
#define FLASH_CS_0() GPIO_ResetBits(GPIOA,GPIO_Pin_4)
|
||||
#define FLASH_CS_1() GPIO_SetBits(GPIOA,GPIO_Pin_4)
|
||||
/********************** hardware *************************************/
|
||||
|
||||
static void GPIO_Configuration(void)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA,ENABLE);
|
||||
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_3;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
GPIO_Init(GPIOA,&GPIO_InitStructure);
|
||||
|
||||
FLASH_RST_0(); // RESET
|
||||
FLASH_RST_1();
|
||||
}
|
||||
|
||||
static unsigned char SPI_HostReadByte(void)
|
||||
{
|
||||
return SPI_WriteByte(0x00);
|
||||
}
|
||||
|
||||
static void SPI_HostWriteByte(unsigned char wByte)
|
||||
{
|
||||
SPI_WriteByte(wByte);
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/*Status Register Format: */
|
||||
/* ------------------------------------------------------------------------- */
|
||||
/* | bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 | */
|
||||
/* |--------|--------|--------|--------|--------|--------|--------|--------| */
|
||||
/* |RDY/BUSY| COMP | device density | X | X | */
|
||||
/* ------------------------------------------------------------------------- */
|
||||
/* 0:busy | | AT45DB041:0111 | protect|page size */
|
||||
/* 1:ready | | AT45DB161:1011 | */
|
||||
/* --------------------------------------------------------------------------*/
|
||||
/*****************************************************************************/
|
||||
static unsigned char AT45DB_StatusRegisterRead(void)
|
||||
{
|
||||
unsigned char i;
|
||||
|
||||
FLASH_CS_0();
|
||||
SPI_HostWriteByte(AT45DB_READ_STATE_REGISTER);
|
||||
i=SPI_HostReadByte();
|
||||
FLASH_CS_1();
|
||||
|
||||
return i;
|
||||
}
|
||||
|
||||
static void wait_busy(void)
|
||||
{
|
||||
unsigned int i=0;
|
||||
while (i++<2000)
|
||||
{
|
||||
if (AT45DB_StatusRegisterRead()&0x80)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void read_page(unsigned int page,unsigned char * pHeader)
|
||||
{
|
||||
unsigned int i=0;
|
||||
|
||||
wait_busy();
|
||||
|
||||
FLASH_CS_0();
|
||||
SPI_HostWriteByte(AT45DB_MM_PAGE_TO_B1_XFER);
|
||||
SPI_HostWriteByte((unsigned char)(page >> 6));
|
||||
SPI_HostWriteByte((unsigned char)(page << 2));
|
||||
SPI_HostWriteByte(0x00);
|
||||
FLASH_CS_1();
|
||||
|
||||
wait_busy();
|
||||
|
||||
FLASH_CS_0();
|
||||
SPI_HostWriteByte(AT45DB_BUFFER_1_READ);
|
||||
SPI_HostWriteByte(0x00);
|
||||
SPI_HostWriteByte(0x00);
|
||||
SPI_HostWriteByte(0x00);
|
||||
SPI_HostWriteByte(0x00);
|
||||
for (i=0; i<512; i++)
|
||||
{
|
||||
*pHeader++ = SPI_HostReadByte();
|
||||
}
|
||||
FLASH_CS_1();
|
||||
|
||||
}
|
||||
|
||||
static void write_page(unsigned int page,unsigned char * pHeader)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
wait_busy();
|
||||
|
||||
FLASH_CS_0();
|
||||
SPI_HostWriteByte(AT45DB_BUFFER_2_WRITE);
|
||||
SPI_HostWriteByte(0);
|
||||
SPI_HostWriteByte(0);
|
||||
SPI_HostWriteByte(0);
|
||||
for(i=0; i<512; i++)
|
||||
{
|
||||
SPI_HostWriteByte(*pHeader++);
|
||||
}
|
||||
FLASH_CS_1();
|
||||
|
||||
wait_busy();
|
||||
|
||||
FLASH_CS_0();
|
||||
SPI_HostWriteByte(AT45DB_B2_TO_MM_PAGE_PROG_WITH_ERASE);
|
||||
SPI_HostWriteByte((unsigned char)(page>>6));
|
||||
SPI_HostWriteByte((unsigned char)(page<<2));
|
||||
SPI_HostWriteByte(0x00);
|
||||
FLASH_CS_1();
|
||||
}
|
||||
|
||||
|
||||
#include <rtthread.h>
|
||||
/* SPI DEVICE */
|
||||
static struct rt_device spi_flash_device;
|
||||
|
||||
/* RT-Thread Device Driver Interface */
|
||||
static rt_err_t rt_spi_flash_init(rt_device_t dev)
|
||||
{
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t rt_spi_flash_open(rt_device_t dev, rt_uint16_t oflag)
|
||||
{
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t rt_spi_flash_close(rt_device_t dev)
|
||||
{
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t rt_spi_flash_control(rt_device_t dev, rt_uint8_t cmd, void *args)
|
||||
{
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_size_t rt_spi_flash_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
|
||||
{
|
||||
/* only supply single block read: block size 512Byte */
|
||||
read_page(pos/512,buffer);
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_size_t rt_spi_flash_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
|
||||
{
|
||||
/* only supply single block write: block size 512Byte */
|
||||
write_page(pos/512,(unsigned char*)buffer);
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
void rt_hw_spi_flash_init(void)
|
||||
{
|
||||
GPIO_Configuration();
|
||||
|
||||
/* register spi_flash device */
|
||||
spi_flash_device.init = rt_spi_flash_init;
|
||||
spi_flash_device.open = rt_spi_flash_open;
|
||||
spi_flash_device.close = rt_spi_flash_close;
|
||||
spi_flash_device.read = rt_spi_flash_read;
|
||||
spi_flash_device.write = rt_spi_flash_write;
|
||||
spi_flash_device.control = rt_spi_flash_control;
|
||||
|
||||
/* no private */
|
||||
spi_flash_device.private = RT_NULL;
|
||||
|
||||
rt_device_register(&spi_flash_device, "spi0",
|
||||
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,6 +1,25 @@
|
|||
#ifndef SPI_FLASH_H_INCLUDED
|
||||
#define SPI_FLASH_H_INCLUDED
|
||||
|
||||
extern void rt_hw_spi_flash_init(void);
|
||||
|
||||
#endif // SPI_FLASH_H_INCLUDED
|
||||
#ifndef SPI_FLASH_H_INCLUDED
|
||||
#define SPI_FLASH_H_INCLUDED
|
||||
|
||||
/*
|
||||
user for AT45DB161.
|
||||
copy form : http://www.ourdev.cn/bbs/bbs_content.jsp?bbs_sn=737106
|
||||
thanks to gxlujd.
|
||||
*/
|
||||
|
||||
#define AT45DB_BUFFER_1_WRITE 0x84 /* 写入第一缓冲区 */
|
||||
#define AT45DB_BUFFER_2_WRITE 0x87 /* 写入第二缓冲区 */
|
||||
#define AT45DB_BUFFER_1_READ 0xD4 /* 读取第一缓冲区 */
|
||||
#define AT45DB_BUFFER_2_READ 0xD6 /* 读取第二缓冲区 */
|
||||
#define AT45DB_B1_TO_MM_PAGE_PROG_WITH_ERASE 0x83 /* 将第一缓冲区的数据写入主存储器（擦除模式）*/
|
||||
#define AT45DB_B2_TO_MM_PAGE_PROG_WITH_ERASE 0x86 /* 将第二缓冲区的数据写入主存储器（擦除模式）*/
|
||||
#define AT45DB_MM_PAGE_TO_B1_XFER 0x53 /* 将主存储器的指定页数据加载到第一缓冲区 */
|
||||
#define AT45DB_MM_PAGE_TO_B2_XFER 0x55 /* 将主存储器的指定页数据加载到第二缓冲区 */
|
||||
#define AT45DB_PAGE_ERASE 0x81 /* 页删除（每页512/528字节） */
|
||||
#define AT45DB_SECTOR_ERASE 0x7C /* 扇区擦除（每扇区128K字节）*/
|
||||
#define AT45DB_READ_STATE_REGISTER 0xD7 /* 读取状态寄存器 */
|
||||
|
||||
|
||||
extern void rt_hw_spi_flash_init(void);
|
||||
|
||||
#endif /* SPI_FLASH_H_INCLUDED */
|
||||
|
|
|
|||
Loading…
Reference in New Issue