libs/rt-thread
libs
/
rt-thread
4
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

[frdm] format codes

This commit is contained in:
Meco Man 2022-01-03 00:21:39 -05:00 committed by Bernard Xiong
parent 918ee6147c
commit e1a17f0bbc
6 changed files with 11 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
bsp/frdm-k64f/applications/startup.c
View File

@ -1,11 +1,11 @@
/* /*
* Copyright (c) 2006-2018, RT-Thread Development Team * Copyright (c) 2006-2022, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Change Logs: * Change Logs:
* Date Author Notes * Date Author Notes
* *
*/ */
#include <rthw.h> #include <rthw.h>

6
bsp/frdm-k64f/board/board.c
View File

@ -1,11 +1,11 @@
/* /*
* Copyright (c) 2006-2018, RT-Thread Development Team * Copyright (c) 2006-2022, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Change Logs: * Change Logs:
* Date Author Notes * Date Author Notes
* *
*/ */
#include <rthw.h> #include <rthw.h>
@ -69,7 +69,7 @@ void rt_hw_board_init()
{ {
/* NVIC Configuration */ /* NVIC Configuration */
NVIC_Configuration(); NVIC_Configuration();
BOARD_BootClockRUN(); BOARD_BootClockRUN();
/* Configure the SysTick */ /* Configure the SysTick */

2
bsp/frdm-k64f/board/clock_config.c
View File

@ -196,7 +196,7 @@ void BOARD_BootClockRUN(void)
CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockRUN.freq); CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockRUN.freq);
/* Configure the Internal Reference clock (MCGIRCLK). */ /* Configure the Internal Reference clock (MCGIRCLK). */
CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode, CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode,
mcgConfig_BOARD_BootClockRUN.ircs, mcgConfig_BOARD_BootClockRUN.ircs,
mcgConfig_BOARD_BootClockRUN.fcrdiv); mcgConfig_BOARD_BootClockRUN.fcrdiv);
/* Configure FLL external reference divider (FRDIV). */ /* Configure FLL external reference divider (FRDIV). */
CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockRUN.frdiv); CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockRUN.frdiv);

4
bsp/frdm-k64f/board/drv_uart.c
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2018, RT-Thread Development Team * Copyright (c) 2006-2022, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
@ -243,7 +243,7 @@ void rt_hw_uart_init(void)
config.parity = PARITY_NONE; config.parity = PARITY_NONE;
config.stop_bits = STOP_BITS_1; config.stop_bits = STOP_BITS_1;
config.invert = NRZ_NORMAL; config.invert = NRZ_NORMAL;
config.bufsz = RT_SERIAL_RB_BUFSZ; config.bufsz = RT_SERIAL_RB_BUFSZ;
_k64_serial.ops = &_k64_ops; _k64_serial.ops = &_k64_ops;
_k64_serial.config = config; _k64_serial.config = config;

4
bsp/frdm-k64f/board/drv_uart.h
View File

@ -1,11 +1,11 @@
/* /*
* Copyright (c) 2006-2018, RT-Thread Development Team * Copyright (c) 2006-2022, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Change Logs: * Change Logs:
* Date Author Notes * Date Author Notes
* *
*/ */
#ifndef DRV_UART_H #ifndef DRV_UART_H

2
bsp/frdm-k64f/board/fsl_phy.c
View File

@ -80,7 +80,7 @@ status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz)
while ((idReg != PHY_CONTROL_ID1) && (counter != 0)) while ((idReg != PHY_CONTROL_ID1) && (counter != 0))
{ {
PHY_Read(base, phyAddr, PHY_ID1_REG, &idReg); PHY_Read(base, phyAddr, PHY_ID1_REG, &idReg);
counter --; counter --;
} }
if (!counter) if (!counter)