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[frdm] format codes

This commit is contained in:
Meco Man 2022-01-03 00:21:39 -05:00 committed by Bernard Xiong
parent 918ee6147c
commit e1a17f0bbc
6 changed files with 11 additions and 11 deletions
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4
bsp/frdm-k64f/applications/startup.c
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@ -1,11 +1,11 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*
*
*/
#include <rthw.h>

6
bsp/frdm-k64f/board/board.c
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@ -1,11 +1,11 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*
*
*/
#include <rthw.h>
@ -69,7 +69,7 @@ void rt_hw_board_init()
{
/* NVIC Configuration */
NVIC_Configuration();
BOARD_BootClockRUN();
/* Configure the SysTick */

2
bsp/frdm-k64f/board/clock_config.c
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@ -196,7 +196,7 @@ void BOARD_BootClockRUN(void)
CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockRUN.freq);
/* Configure the Internal Reference clock (MCGIRCLK). */
CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode,
mcgConfig_BOARD_BootClockRUN.ircs,
mcgConfig_BOARD_BootClockRUN.ircs,
mcgConfig_BOARD_BootClockRUN.fcrdiv);
/* Configure FLL external reference divider (FRDIV). */
CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockRUN.frdiv);

4
bsp/frdm-k64f/board/drv_uart.c
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -243,7 +243,7 @@ void rt_hw_uart_init(void)
config.parity = PARITY_NONE;
config.stop_bits = STOP_BITS_1;
config.invert = NRZ_NORMAL;
config.bufsz = RT_SERIAL_RB_BUFSZ;
config.bufsz = RT_SERIAL_RB_BUFSZ;
_k64_serial.ops = &_k64_ops;
_k64_serial.config = config;

4
bsp/frdm-k64f/board/drv_uart.h
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@ -1,11 +1,11 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*
*
*/
#ifndef DRV_UART_H

2
bsp/frdm-k64f/board/fsl_phy.c
View File

@ -80,7 +80,7 @@ status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz)
while ((idReg != PHY_CONTROL_ID1) && (counter != 0))
{
PHY_Read(base, phyAddr, PHY_ID1_REG, &idReg);
counter --;
counter --;
}
if (!counter)