[bsp][LPC4088] 增加IAR环境的支持 (#7611)
This commit is contained in:
meng-plus
GitHub
parent
ff8064c02e
commit
dd4a068e76
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@ -57,7 +57,6 @@ CONFIG_RT_USING_MESSAGEQUEUE=y
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#
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# Memory Management
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#
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CONFIG_RT_PAGE_MAX_ORDER=11
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CONFIG_RT_USING_MEMPOOL=y
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# CONFIG_RT_USING_SMALL_MEM is not set
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# CONFIG_RT_USING_SLAB is not set
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@ -84,7 +83,7 @@ CONFIG_RT_USING_DEVICE=y
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CONFIG_RT_USING_CONSOLE=y
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CONFIG_RT_CONSOLEBUF_SIZE=128
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CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
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CONFIG_RT_VER_NUM=0x50000
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CONFIG_RT_VER_NUM=0x50001
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# CONFIG_RT_USING_STDC_ATOMIC is not set
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# CONFIG_RT_USING_CACHE is not set
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CONFIG_RT_USING_HW_ATOMIC=y
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@ -118,13 +117,19 @@ CONFIG_FINSH_USING_DESCRIPTION=y
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# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
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# CONFIG_FINSH_USING_AUTH is not set
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CONFIG_FINSH_ARG_MAX=10
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#
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# DFS: device virtual file system
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#
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CONFIG_RT_USING_DFS=y
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CONFIG_DFS_USING_POSIX=y
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CONFIG_DFS_USING_WORKDIR=y
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# CONFIG_RT_USING_DFS_MNTTABLE is not set
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CONFIG_DFS_FD_MAX=16
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CONFIG_RT_USING_DFS_V1=y
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# CONFIG_RT_USING_DFS_V2 is not set
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CONFIG_DFS_FILESYSTEMS_MAX=2
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CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
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CONFIG_DFS_FD_MAX=16
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# CONFIG_RT_USING_DFS_MNTTABLE is not set
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CONFIG_RT_USING_DFS_ELMFAT=y
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#
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@ -474,6 +479,7 @@ CONFIG_RT_USING_POSIX_DELAY=y
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# CONFIG_PKG_USING_HASH_MATCH is not set
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# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
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# CONFIG_PKG_USING_VOFA_PLUS is not set
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# CONFIG_PKG_USING_RT_TRACE is not set
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#
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# system packages
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@ -545,6 +551,7 @@ CONFIG_RT_USING_POSIX_DELAY=y
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# CONFIG_PKG_USING_QPC is not set
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# CONFIG_PKG_USING_AGILE_UPGRADE is not set
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# CONFIG_PKG_USING_FLASH_BLOB is not set
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# CONFIG_PKG_USING_MLIBC is not set
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#
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# peripheral libraries and drivers
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@ -629,6 +636,7 @@ CONFIG_RT_USING_POSIX_DELAY=y
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# CONFIG_PKG_USING_FT5426 is not set
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# CONFIG_PKG_USING_FT6236 is not set
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# CONFIG_PKG_USING_XPT2046_TOUCH is not set
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# CONFIG_PKG_USING_CST816X is not set
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# CONFIG_PKG_USING_REALTEK_AMEBA is not set
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# CONFIG_PKG_USING_STM32_SDIO is not set
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# CONFIG_PKG_USING_ESP_IDF is not set
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@ -641,7 +649,6 @@ CONFIG_RT_USING_POSIX_DELAY=y
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# CONFIG_PKG_USING_LKDGUI is not set
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# CONFIG_PKG_USING_NRF5X_SDK is not set
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# CONFIG_PKG_USING_NRFX is not set
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# CONFIG_PKG_USING_WM_LIBRARIES is not set
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#
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# Kendryte SDK
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@ -699,14 +706,15 @@ CONFIG_RT_USING_POSIX_DELAY=y
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# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
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# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
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# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
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# CONFIG_PKG_USING_BL_MCU_SDK is not set
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# CONFIG_PKG_USING_SOFT_SERIAL is not set
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# CONFIG_PKG_USING_MB85RS16 is not set
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# CONFIG_PKG_USING_RFM300 is not set
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# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
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# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
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# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
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# CONFIG_PKG_USING_AIP650 is not set
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# CONFIG_PKG_USING_FINGERPRINT is not set
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# CONFIG_PKG_USING_SPI_TOOLS is not set
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#
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# AI packages
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@ -725,7 +733,10 @@ CONFIG_RT_USING_POSIX_DELAY=y
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# Signal Processing and Control Algorithm Packages
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#
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# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
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# CONFIG_PKG_USING_QPID is not set
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# CONFIG_PKG_USING_UKAL is not set
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# CONFIG_PKG_USING_DIGITALCTRL is not set
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# CONFIG_PKG_USING_KISSFFT is not set
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#
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# miscellaneous packages
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@ -772,7 +783,6 @@ CONFIG_RT_USING_POSIX_DELAY=y
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# CONFIG_PKG_USING_DSTR is not set
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# CONFIG_PKG_USING_TINYFRAME is not set
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# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
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# CONFIG_PKG_USING_DIGITALCTRL is not set
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# CONFIG_PKG_USING_UPACKER is not set
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# CONFIG_PKG_USING_UPARAM is not set
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# CONFIG_PKG_USING_HELLO is not set
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@ -799,6 +809,7 @@ CONFIG_RT_USING_POSIX_DELAY=y
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#
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# Projects
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#
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# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set
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# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
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# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
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# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
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@ -945,14 +956,20 @@ CONFIG_RT_USING_POSIX_DELAY=y
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#
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# Display
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#
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# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set
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# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set
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# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
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# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set
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# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set
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# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set
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# CONFIG_PKG_USING_SEEED_TM1637 is not set
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#
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# Timing
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#
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# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
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# CONFIG_PKG_USING_ARDUINO_TICKER is not set
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# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set
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#
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# Data Processing
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@ -1,9 +1,9 @@
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;/*****************************************************************************
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; * @file: startup_LPC177x_8x.s
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; * @purpose: CMSIS Cortex-M3 Core Device Startup File
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; * for the NXP LPC17xx Device Series
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; * @version: V1.03
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; * @date: 09. February 2010
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; * @file: startup_LPC407x_8x.s
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; * @purpose: CMSIS Cortex-M4 Core Device Startup File
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; * for the NXP LPC40xx Device Series
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; * @version: V1.00
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; * @date: September 2012
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; *----------------------------------------------------------------------------
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; *
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; * Copyright (C) 2010 ARM Limited. All rights reserved.
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@ -75,49 +75,47 @@ __vector_table_0x1c
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DCD SysTick_Handler
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; External Interrupts
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DCD WDT_IRQHandler ; 16: Watchdog Timer
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DCD TIMER0_IRQHandler ; 17: Timer0
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DCD TIMER1_IRQHandler ; 18: Timer1
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DCD TIMER2_IRQHandler ; 19: Timer2
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DCD TIMER3_IRQHandler ; 20: Timer3
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DCD UART0_IRQHandler ; 21: UART0
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DCD UART1_IRQHandler ; 22: UART1
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DCD UART2_IRQHandler ; 23: UART2
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DCD UART3_IRQHandler ; 24: UART3
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DCD PWM1_IRQHandler ; 25: PWM1
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DCD I2C0_IRQHandler ; 26: I2C0
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DCD I2C1_IRQHandler ; 27: I2C1
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DCD I2C2_IRQHandler ; 28: I2C2
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DCD 0 ; 29: reserved; not for SPIFI anymore
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DCD SSP0_IRQHandler ; 30: SSP0
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DCD SSP1_IRQHandler ; 31: SSP1
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DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL)
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DCD RTC_IRQHandler ; 33: Real Time Clock
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DCD EINT0_IRQHandler ; 34: External Interrupt 0
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DCD EINT1_IRQHandler ; 35: External Interrupt 1
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DCD EINT2_IRQHandler ; 36: External Interrupt 2
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DCD EINT3_IRQHandler ; 37: External Interrupt 3
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DCD ADC_IRQHandler ; 38: A/D Converter
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DCD BOD_IRQHandler ; 39: Brown-Out Detect
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DCD USB_IRQHandler ; 40: USB
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DCD CAN_IRQHandler ; 41: CAN
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DCD DMA_IRQHandler ; 42: General Purpose DMA
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DCD I2S_IRQHandler ; 43: I2S
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DCD ENET_IRQHandler ; 44: Ethernet
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DCD MCI_IRQHandler ; 45: MCI Card
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DCD MCPWM_IRQHandler ; 46: Motor Control PWM
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DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface
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DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL)
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DCD USBActivity_IRQHandler ; 49: USB Activity Interrupt
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DCD CANActivity_IRQHandler ; 50: CAN Activity Interrupt
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DCD UART4_IRQHandler ; 51: UART4
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DCD SSP2_IRQHandler ; 52: SSP2
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DCD LCD_IRQHandler ; 53: LCD
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DCD GPIO_IRQHandler ; 54: GPIO
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DCD PWM0_IRQHandler ; 55: PWM0
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DCD EEPROM_IRQHandler ; 56: EEPROM
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DCD WDT_IRQHandler ; 16: Watchdog Timer
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DCD TIMER0_IRQHandler ; 17: Timer0
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DCD TIMER1_IRQHandler ; 18: Timer1
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DCD TIMER2_IRQHandler ; 19: Timer2
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DCD TIMER3_IRQHandler ; 20: Timer3
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DCD UART0_IRQHandler ; 21: UART0
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DCD UART1_IRQHandler ; 22: UART1
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DCD UART2_IRQHandler ; 23: UART2
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DCD UART3_IRQHandler ; 24: UART3
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DCD PWM1_IRQHandler ; 25: PWM1
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DCD I2C0_IRQHandler ; 26: I2C0
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DCD I2C1_IRQHandler ; 27: I2C1
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DCD I2C2_IRQHandler ; 28: I2C2
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DCD 0 ; 29: Reserved
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DCD SSP0_IRQHandler ; 30: SSP0
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DCD SSP1_IRQHandler ; 31: SSP1
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DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL)
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DCD RTC_IRQHandler ; 33: Real Time Clock
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DCD EINT0_IRQHandler ; 34: External Interrupt 0
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DCD EINT1_IRQHandler ; 35: External Interrupt 1
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DCD EINT2_IRQHandler ; 36: External Interrupt 2
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DCD EINT3_IRQHandler ; 37: External Interrupt 3
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DCD ADC_IRQHandler ; 38: A/D Converter
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DCD BOD_IRQHandler ; 39: Brown-Out Detect
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DCD USB_IRQHandler ; 40: USB
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DCD CAN_IRQHandler ; 41: CAN
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DCD DMA_IRQHandler ; 42: General Purpose DMA
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DCD I2S_IRQHandler ; 43: I2S
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DCD ENET_IRQHandler ; 44: Ethernet
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DCD MCI_IRQHandler ; 45: MCI Card
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DCD MCPWM_IRQHandler ; 46: Motor Control PWM
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DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface
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DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL)
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DCD USBActivity_IRQHandler ; 49: USB Activity Interrupt
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DCD CANActivity_IRQHandler ; 50: CAN Activity Interrupt
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DCD UART4_IRQHandler ; 51: UART4
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DCD SSP2_IRQHandler ; 52: SSP2
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DCD LCD_IRQHandler ; 53: LCD
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DCD GPIO_IRQHandler ; 54: GPIO
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DCD PWM0_IRQHandler ; 55: PWM0
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DCD EEPROM_IRQHandler ; 56: EEPROM
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__Vectors_End
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@ -125,10 +123,7 @@ __Vectors_End
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__Vectors EQU __vector_table
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__Vectors_Size EQU __Vectors_End - __Vectors
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PUBLIC CRP_Value
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RSEG CRPKEY : CODE(2)
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CRP_Value
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DCD 0xFFFFFFFF
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; Default interrupt handlers.
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@ -136,7 +131,7 @@ CRP_Value
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THUMB
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PUBWEAK Reset_Handler
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SECTION .text:CODE:REORDER(2)
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SECTION .text:CODE:REORDER:NOROOT(2)
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Reset_Handler
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LDR R0, =SystemInit
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BLX R0
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@ -144,253 +139,281 @@ Reset_Handler
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BX R0
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PUBWEAK NMI_Handler
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SECTION .text:CODE:REORDER(1)
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SECTION .text:CODE:REORDER:NOROOT(1)
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NMI_Handler
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B NMI_Handler
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PUBWEAK HardFault_Handler
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SECTION .text:CODE:REORDER(1)
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SECTION .text:CODE:REORDER:NOROOT(1)
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HardFault_Handler
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B HardFault_Handler
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PUBWEAK MemManage_Handler
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SECTION .text:CODE:REORDER(1)
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SECTION .text:CODE:REORDER:NOROOT(1)
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MemManage_Handler
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B MemManage_Handler
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PUBWEAK BusFault_Handler
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SECTION .text:CODE:REORDER(1)
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SECTION .text:CODE:REORDER:NOROOT(1)
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BusFault_Handler
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B BusFault_Handler
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PUBWEAK UsageFault_Handler
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SECTION .text:CODE:REORDER(1)
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SECTION .text:CODE:REORDER:NOROOT(1)
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UsageFault_Handler
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B UsageFault_Handler
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PUBWEAK SVC_Handler
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SECTION .text:CODE:REORDER(1)
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SECTION .text:CODE:REORDER:NOROOT(1)
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SVC_Handler
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B SVC_Handler
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PUBWEAK DebugMon_Handler
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SECTION .text:CODE:REORDER(1)
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SECTION .text:CODE:REORDER:NOROOT(1)
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DebugMon_Handler
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B DebugMon_Handler
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PUBWEAK PendSV_Handler
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SECTION .text:CODE:REORDER(1)
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SECTION .text:CODE:REORDER:NOROOT(1)
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PendSV_Handler
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B PendSV_Handler
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PUBWEAK SysTick_Handler
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SECTION .text:CODE:REORDER(1)
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SECTION .text:CODE:REORDER:NOROOT(1)
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SysTick_Handler
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B SysTick_Handler
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PUBWEAK WDT_IRQHandler
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SECTION .text:CODE:REORDER(1)
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SECTION .text:CODE:REORDER:NOROOT(1)
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WDT_IRQHandler
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B WDT_IRQHandler
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PUBWEAK TIMER0_IRQHandler
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SECTION .text:CODE:REORDER(1)
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SECTION .text:CODE:REORDER:NOROOT(1)
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TIMER0_IRQHandler
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B TIMER0_IRQHandler
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PUBWEAK TIMER1_IRQHandler
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SECTION .text:CODE:REORDER(1)
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SECTION .text:CODE:REORDER:NOROOT(1)
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TIMER1_IRQHandler
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B TIMER1_IRQHandler
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PUBWEAK TIMER2_IRQHandler
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SECTION .text:CODE:REORDER(1)
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SECTION .text:CODE:REORDER:NOROOT(1)
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TIMER2_IRQHandler
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B TIMER2_IRQHandler
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PUBWEAK TIMER3_IRQHandler
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SECTION .text:CODE:REORDER(1)
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SECTION .text:CODE:REORDER:NOROOT(1)
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TIMER3_IRQHandler
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B TIMER3_IRQHandler
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PUBWEAK UART0_IRQHandler
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SECTION .text:CODE:REORDER(1)
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SECTION .text:CODE:REORDER:NOROOT(1)
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UART0_IRQHandler
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B UART0_IRQHandler
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PUBWEAK UART1_IRQHandler
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SECTION .text:CODE:REORDER(1)
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SECTION .text:CODE:REORDER:NOROOT(1)
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UART1_IRQHandler
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B UART1_IRQHandler
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PUBWEAK UART2_IRQHandler
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SECTION .text:CODE:REORDER(1)
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SECTION .text:CODE:REORDER:NOROOT(1)
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UART2_IRQHandler
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B UART2_IRQHandler
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PUBWEAK UART3_IRQHandler
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SECTION .text:CODE:REORDER(1)
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SECTION .text:CODE:REORDER:NOROOT(1)
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UART3_IRQHandler
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B UART3_IRQHandler
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PUBWEAK PWM1_IRQHandler
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SECTION .text:CODE:REORDER(1)
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SECTION .text:CODE:REORDER:NOROOT(1)
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PWM1_IRQHandler
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B PWM1_IRQHandler
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PUBWEAK I2C0_IRQHandler
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SECTION .text:CODE:REORDER(1)
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SECTION .text:CODE:REORDER:NOROOT(1)
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I2C0_IRQHandler
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B I2C0_IRQHandler
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PUBWEAK I2C1_IRQHandler
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SECTION .text:CODE:REORDER(1)
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SECTION .text:CODE:REORDER:NOROOT(1)
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I2C1_IRQHandler
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B I2C1_IRQHandler
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PUBWEAK I2C2_IRQHandler
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SECTION .text:CODE:REORDER(1)
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SECTION .text:CODE:REORDER:NOROOT(1)
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I2C2_IRQHandler
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B I2C2_IRQHandler
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;PUBWEAK SPIFI_IRQHandler
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;SECTION .text:CODE:REORDER(1)
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; PUBWEAK SPIFI_IRQHandler
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; SECTION .text:CODE:REORDER:NOROOT(1)
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;SPIFI_IRQHandler
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;B SPIFI_IRQHandler
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; B SPIFI_IRQHandler
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PUBWEAK SSP0_IRQHandler
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SECTION .text:CODE:REORDER(1)
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SECTION .text:CODE:REORDER:NOROOT(1)
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SSP0_IRQHandler
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B SSP0_IRQHandler
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PUBWEAK SSP1_IRQHandler
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SECTION .text:CODE:REORDER(1)
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SECTION .text:CODE:REORDER:NOROOT(1)
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||||
SSP1_IRQHandler
|
||||
B SSP1_IRQHandler
|
||||
|
||||
PUBWEAK PLL0_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PLL0_IRQHandler
|
||||
B PLL0_IRQHandler
|
||||
|
||||
PUBWEAK RTC_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RTC_IRQHandler
|
||||
B RTC_IRQHandler
|
||||
|
||||
PUBWEAK EINT0_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EINT0_IRQHandler
|
||||
B EINT0_IRQHandler
|
||||
|
||||
PUBWEAK EINT1_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EINT1_IRQHandler
|
||||
B EINT1_IRQHandler
|
||||
|
||||
PUBWEAK EINT2_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EINT2_IRQHandler
|
||||
B EINT2_IRQHandler
|
||||
|
||||
PUBWEAK EINT3_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EINT3_IRQHandler
|
||||
B EINT3_IRQHandler
|
||||
|
||||
PUBWEAK ADC_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
ADC_IRQHandler
|
||||
B ADC_IRQHandler
|
||||
|
||||
PUBWEAK BOD_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
BOD_IRQHandler
|
||||
B BOD_IRQHandler
|
||||
|
||||
PUBWEAK USB_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
USB_IRQHandler
|
||||
B USB_IRQHandler
|
||||
|
||||
PUBWEAK CAN_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
CAN_IRQHandler
|
||||
B CAN_IRQHandler
|
||||
|
||||
PUBWEAK DMA_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA_IRQHandler
|
||||
B DMA_IRQHandler
|
||||
|
||||
PUBWEAK I2S_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
I2S_IRQHandler
|
||||
B I2S_IRQHandler
|
||||
|
||||
PUBWEAK ENET_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
ENET_IRQHandler
|
||||
B ENET_IRQHandler
|
||||
|
||||
PUBWEAK MCI_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
MCI_IRQHandler
|
||||
B MCI_IRQHandler
|
||||
|
||||
PUBWEAK MCPWM_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
MCPWM_IRQHandler
|
||||
B MCPWM_IRQHandler
|
||||
|
||||
PUBWEAK QEI_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
QEI_IRQHandler
|
||||
B QEI_IRQHandler
|
||||
|
||||
PUBWEAK PLL1_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PLL1_IRQHandler
|
||||
B PLL1_IRQHandler
|
||||
|
||||
PUBWEAK USBActivity_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
USBActivity_IRQHandler
|
||||
B USBActivity_IRQHandler
|
||||
|
||||
PUBWEAK CANActivity_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
CANActivity_IRQHandler
|
||||
B CANActivity_IRQHandler
|
||||
|
||||
PUBWEAK UART4_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
UART4_IRQHandler
|
||||
B UART4_IRQHandler
|
||||
|
||||
PUBWEAK SSP2_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SSP2_IRQHandler
|
||||
B SSP2_IRQHandler
|
||||
|
||||
PUBWEAK LCD_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
LCD_IRQHandler
|
||||
B LCD_IRQHandler
|
||||
|
||||
PUBWEAK GPIO_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
GPIO_IRQHandler
|
||||
B GPIO_IRQHandler
|
||||
|
||||
PUBWEAK PWM0_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PWM0_IRQHandler
|
||||
B PWM0_IRQHandler
|
||||
|
||||
PUBWEAK EEPROM_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EEPROM_IRQHandler
|
||||
B EEPROM_IRQHandler
|
||||
|
||||
#ifndef SRAM
|
||||
SECTION .crp:CODE:ROOT(2)
|
||||
DATA
|
||||
|
||||
/* Code Read Protection
|
||||
CRP1 0x12345678 - Write to RAM command can not access RAM below 0x10000200.
|
||||
- Read Memory command: disabled.
|
||||
- Copy RAM to Flash command: cannot write to Sector 0.
|
||||
- "Go" command: disabled.
|
||||
- Erase sector(s) command: can erase any individual sector except
|
||||
sector 0 only, or can erase all sectors at once.
|
||||
- Compare command: disabled
|
||||
CRP2 0x87654321 - Write to RAM command: disabled.
|
||||
- Copy RAM to Flash: disabled.
|
||||
- Erase command: only allows erase of all sectors.
|
||||
CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry
|
||||
by pulling PIO0_1 LOW is disabled if a valid user code is
|
||||
present in flash sector 0.
|
||||
Caution: If CRP3 is selected, no future factory testing can be
|
||||
performed on the device.
|
||||
*/
|
||||
|
||||
#ifndef CRP
|
||||
#define CRP 0xFFFFFFFF
|
||||
#endif
|
||||
|
||||
DCD CRP
|
||||
#endif
|
||||
END
|
||||
|
|
|
|||
|
|
@ -0,0 +1,51 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x10000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x1000FFDF;
|
||||
define symbol __ICFEDIT_region_SDRAM_start__ = 0xA0000000;
|
||||
define symbol __ICFEDIT_region_SDRAM_end__ = 0xA3FFFFFF;
|
||||
|
||||
define symbol _AHB_RAM_start__ = 0x20000000;
|
||||
define symbol _AHB_RAM_end__ = 0x20007FFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x1C00;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define symbol __CRP_start__ = 0x000002FC;
|
||||
define symbol __CRP_end__ = 0x000002FF;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__];
|
||||
define region CRP_region = mem:[from __CRP_start__ to __CRP_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region SDRAM_region = mem:[from __ICFEDIT_region_SDRAM_start__ to __ICFEDIT_region_SDRAM_end__];
|
||||
define region AHB_RAM_region = mem:[from _AHB_RAM_start__ to _AHB_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
do not initialize { section USB_DMA_RAM };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK,
|
||||
block HEAP};
|
||||
place in AHB_RAM_region
|
||||
{ readwrite data section AHB_RAM_MEMORY, section USB_DMA_RAM, section EMAC_DMA_RAM};
|
||||
|
||||
place in SDRAM_region {section SDRAM,section EXFLASH_RAM};
|
||||
|
||||
place in CRP_region { section .crp };
|
||||
|
||||
define exported symbol SDRAM_BASE_ADDR = __ICFEDIT_region_SDRAM_start__;
|
||||
|
|
@ -33,7 +33,6 @@
|
|||
|
||||
/* Memory Management */
|
||||
|
||||
#define RT_PAGE_MAX_ORDER 11
|
||||
#define RT_USING_MEMPOOL
|
||||
#define RT_USING_MEMHEAP
|
||||
#define RT_MEMHEAP_FAST_MODE
|
||||
|
|
@ -47,7 +46,7 @@
|
|||
#define RT_USING_CONSOLE
|
||||
#define RT_CONSOLEBUF_SIZE 128
|
||||
#define RT_CONSOLE_DEVICE_NAME "uart0"
|
||||
#define RT_VER_NUM 0x50000
|
||||
#define RT_VER_NUM 0x50001
|
||||
#define RT_USING_HW_ATOMIC
|
||||
#define RT_USING_CPU_FFS
|
||||
#define ARCH_ARM
|
||||
|
|
@ -73,12 +72,16 @@
|
|||
#define MSH_USING_BUILT_IN_COMMANDS
|
||||
#define FINSH_USING_DESCRIPTION
|
||||
#define FINSH_ARG_MAX 10
|
||||
|
||||
/* DFS: device virtual file system */
|
||||
|
||||
#define RT_USING_DFS
|
||||
#define DFS_USING_POSIX
|
||||
#define DFS_USING_WORKDIR
|
||||
#define DFS_FD_MAX 16
|
||||
#define RT_USING_DFS_V1
|
||||
#define DFS_FILESYSTEMS_MAX 2
|
||||
#define DFS_FILESYSTEM_TYPES_MAX 2
|
||||
#define DFS_FD_MAX 16
|
||||
#define RT_USING_DFS_ELMFAT
|
||||
|
||||
/* elm-chan's FatFs, Generic FAT Filesystem Module */
|
||||
|
|
|
|||
|
|
@ -15,10 +15,8 @@ elif CROSS_TOOL == 'keil':
|
|||
PLATFORM = 'armcc'
|
||||
EXEC_PATH = 'D:/Keil'
|
||||
elif CROSS_TOOL == 'iar':
|
||||
print('================ERROR============================')
|
||||
print('Not support iar yet!')
|
||||
print('=================================================')
|
||||
exit(0)
|
||||
PLATFORM = 'iccarm'
|
||||
EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.4'
|
||||
|
||||
if os.getenv('RTT_EXEC_PATH'):
|
||||
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
|
||||
|
|
@ -43,7 +41,7 @@ if PLATFORM == 'gcc':
|
|||
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
|
||||
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T drivers/linker_scripts/link.lds'
|
||||
CXXFLAGS = CFLAGS
|
||||
|
||||
|
||||
CPATH = ''
|
||||
LPATH = ''
|
||||
|
||||
|
|
@ -82,3 +80,53 @@ elif PLATFORM == 'armcc':
|
|||
CFLAGS += ' -O2'
|
||||
|
||||
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
|
||||
|
||||
elif PLATFORM == 'iccarm':
|
||||
# toolchains
|
||||
CC = 'iccarm'
|
||||
CXX = 'iccarm'
|
||||
AS = 'iasmarm'
|
||||
AR = 'iarchive'
|
||||
LINK = 'ilinkarm'
|
||||
TARGET_EXT = 'out'
|
||||
|
||||
DEVICE = '-Dewarm'
|
||||
|
||||
CFLAGS = DEVICE
|
||||
CFLAGS += ' --diag_suppress Pa050'
|
||||
CFLAGS += ' --no_cse'
|
||||
CFLAGS += ' --no_unroll'
|
||||
CFLAGS += ' --no_inline'
|
||||
CFLAGS += ' --no_code_motion'
|
||||
CFLAGS += ' --no_tbaa'
|
||||
CFLAGS += ' --no_clustering'
|
||||
CFLAGS += ' --no_scheduling'
|
||||
CFLAGS += ' --endian=little'
|
||||
CFLAGS += ' --cpu=Cortex-M4'
|
||||
CFLAGS += ' -e'
|
||||
CFLAGS += ' --fpu=VFPv4_sp'
|
||||
CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
|
||||
CFLAGS += ' --silent'
|
||||
|
||||
AFLAGS = DEVICE
|
||||
AFLAGS += ' -s+'
|
||||
AFLAGS += ' -w+'
|
||||
AFLAGS += ' -r'
|
||||
AFLAGS += ' --cpu Cortex-M4'
|
||||
AFLAGS += ' --fpu VFPv4_sp'
|
||||
AFLAGS += ' -S'
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' --debug'
|
||||
CFLAGS += ' -On'
|
||||
else:
|
||||
CFLAGS += ' -Oh'
|
||||
|
||||
LFLAGS = ' --config "drivers/linker_scripts/link.icf"'
|
||||
LFLAGS += ' --entry __iar_program_start'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
|
||||
EXEC_PATH = EXEC_PATH + '/arm/bin/'
|
||||
POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,10 @@
|
|||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<workspace>
|
||||
<project>
|
||||
<path>$WS_DIR$\template.ewp</path>
|
||||
</project>
|
||||
<batchBuild/>
|
||||
</workspace>
|
||||
|
||||
|
||||
Loading…
Reference in New Issue