1.修改stm32f103-ufun为stm32f103-yf-ufun和其readme。
This commit is contained in:
commit
dae875593f
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@ -29,14 +29,14 @@ extern "C" {
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#endif /* BSP_USING_UART1 */
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#endif /* BSP_USING_UART1 */
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#if defined(BSP_UART1_RX_USING_DMA)
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#if defined(BSP_UART1_RX_USING_DMA)
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#ifndef UART1_DMA_CONFIG
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#ifndef UART1_DMA_RX_CONFIG
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#define UART1_DMA_CONFIG \
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#define UART1_DMA_RX_CONFIG \
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{ \
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{ \
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.Instance = UART1_RX_DMA_INSTANCE, \
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.Instance = UART1_RX_DMA_INSTANCE, \
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.dma_rcc = UART1_RX_DMA_RCC, \
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.dma_rcc = UART1_RX_DMA_RCC, \
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.dma_irq = UART1_RX_DMA_IRQ, \
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.dma_irq = UART1_RX_DMA_IRQ, \
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}
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}
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#endif /* UART1_DMA_CONFIG */
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#endif /* UART1_DMA_RX_CONFIG */
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#endif /* BSP_UART1_RX_USING_DMA */
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#endif /* BSP_UART1_RX_USING_DMA */
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#if defined(BSP_USING_UART2)
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#if defined(BSP_USING_UART2)
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@ -51,14 +51,14 @@ extern "C" {
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#endif /* BSP_USING_UART2 */
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#endif /* BSP_USING_UART2 */
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#if defined(BSP_UART2_RX_USING_DMA)
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#if defined(BSP_UART2_RX_USING_DMA)
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#ifndef UART2_DMA_CONFIG
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#ifndef UART2_DMA_RX_CONFIG
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#define UART2_DMA_CONFIG \
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#define UART2_DMA_RX_CONFIG \
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{ \
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{ \
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.Instance = UART2_RX_DMA_INSTANCE, \
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.Instance = UART2_RX_DMA_INSTANCE, \
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.dma_rcc = UART2_RX_DMA_RCC, \
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.dma_rcc = UART2_RX_DMA_RCC, \
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.dma_irq = UART2_RX_DMA_IRQ, \
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.dma_irq = UART2_RX_DMA_IRQ, \
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}
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}
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#endif /* UART2_DMA_CONFIG */
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#endif /* UART2_DMA_RX_CONFIG */
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#endif /* BSP_UART2_RX_USING_DMA */
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#endif /* BSP_UART2_RX_USING_DMA */
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#ifdef __cplusplus
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#ifdef __cplusplus
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@ -25,6 +25,11 @@ extern "C" {
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#define SPI1_RX_DMA_RCC RCC_AHBENR_DMA1EN
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#define SPI1_RX_DMA_RCC RCC_AHBENR_DMA1EN
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#define SPI1_RX_DMA_INSTANCE DMA1_Channel2
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#define SPI1_RX_DMA_INSTANCE DMA1_Channel2
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#define SPI1_RX_DMA_IRQ DMA1_Channel2_IRQn
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#define SPI1_RX_DMA_IRQ DMA1_Channel2_IRQn
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#elif defined(BSP_UART3_TX_USING_DMA) && !defined(UART3_TX_DMA_INSTANCE)
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#define UART3_DMA_TX_IRQHandler DMA1_Channel2_IRQHandler
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#define UART3_TX_DMA_RCC RCC_AHBENR_DMA1EN
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#define UART3_TX_DMA_INSTANCE DMA1_Channel2
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#define UART3_TX_DMA_IRQ DMA1_Channel2_IRQn
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#endif
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#endif
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/* DMA1 channel3 */
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/* DMA1 channel3 */
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@ -46,6 +51,11 @@ extern "C" {
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#define SPI2_RX_DMA_RCC RCC_AHBENR_DMA1EN
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#define SPI2_RX_DMA_RCC RCC_AHBENR_DMA1EN
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#define SPI2_RX_DMA_INSTANCE DMA1_Channel4
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#define SPI2_RX_DMA_INSTANCE DMA1_Channel4
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#define SPI2_RX_DMA_IRQ DMA1_Channel4_IRQn
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#define SPI2_RX_DMA_IRQ DMA1_Channel4_IRQn
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#elif defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
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#define UART1_DMA_TX_IRQHandler DMA1_Channel4_IRQHandler
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#define UART1_TX_DMA_RCC RCC_AHBENR_DMA1EN
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#define UART1_TX_DMA_INSTANCE DMA1_Channel4
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#define UART1_TX_DMA_IRQ DMA1_Channel4_IRQn
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#endif
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#endif
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/* DMA1 channel5 */
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/* DMA1 channel5 */
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@ -71,6 +81,12 @@ extern "C" {
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#endif
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#endif
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/* DMA1 channel7 */
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/* DMA1 channel7 */
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#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
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#define UART2_DMA_TX_IRQHandler DMA1_Channel7_IRQHandler
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#define UART2_TX_DMA_RCC RCC_AHBENR_DMA1EN
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#define UART2_TX_DMA_INSTANCE DMA1_Channel7
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#define UART2_TX_DMA_IRQ DMA1_Channel7_IRQn
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#endif
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/* DMA2 channel1 */
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/* DMA2 channel1 */
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#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
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#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
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@ -89,8 +105,20 @@ extern "C" {
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#endif
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#endif
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/* DMA2 channel3 */
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/* DMA2 channel3 */
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#if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
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#define UART4_DMA_RX_IRQHandler DMA2_Channel3_IRQHandler
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#define UART4_RX_DMA_RCC RCC_AHBENR_DMA2EN
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#define UART4_RX_DMA_INSTANCE DMA2_Channel3
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#define UART4_RX_DMA_IRQ DMA2_Channel3_IRQn
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#endif
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/* DMA2 channel4 */
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/* DMA2 channel4 */
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/* DMA2 channel5 */
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/* DMA2 channel5 */
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#if defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE)
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#define UART4_DMA_TX_IRQHandler DMA2_Channel4_5_IRQHandler
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#define UART4_TX_DMA_RCC RCC_AHBENR_DMA2EN
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#define UART4_TX_DMA_INSTANCE DMA2_Channel5
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#define UART4_TX_DMA_IRQ DMA2_Channel4_5_IRQn
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#endif
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#ifdef __cplusplus
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#ifdef __cplusplus
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}
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}
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@ -28,19 +28,30 @@ extern "C" {
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.irq_type = USART1_IRQn, \
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.irq_type = USART1_IRQn, \
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}
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}
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#endif /* UART1_CONFIG */
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#endif /* UART1_CONFIG */
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#endif /* BSP_USING_UART1 */
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#if defined(BSP_UART1_RX_USING_DMA)
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#if defined(BSP_UART1_RX_USING_DMA)
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#ifndef UART1_DMA_CONFIG
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#ifndef UART1_DMA_RX_CONFIG
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#define UART1_DMA_CONFIG \
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#define UART1_DMA_RX_CONFIG \
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{ \
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{ \
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.Instance = UART1_RX_DMA_INSTANCE, \
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.Instance = UART1_RX_DMA_INSTANCE, \
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.dma_rcc = UART1_RX_DMA_RCC, \
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.dma_rcc = UART1_RX_DMA_RCC, \
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.dma_irq = UART1_RX_DMA_IRQ, \
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.dma_irq = UART1_RX_DMA_IRQ, \
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}
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}
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#endif /* UART1_DMA_CONFIG */
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#endif /* UART1_DMA_RX_CONFIG */
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#endif /* BSP_UART1_RX_USING_DMA */
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#endif /* BSP_UART1_RX_USING_DMA */
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#if defined(BSP_UART1_TX_USING_DMA)
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#ifndef UART1_DMA_TX_CONFIG
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#define UART1_DMA_TX_CONFIG \
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{ \
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.Instance = UART1_TX_DMA_INSTANCE, \
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.dma_rcc = UART1_TX_DMA_RCC, \
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.dma_irq = UART1_TX_DMA_IRQ, \
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}
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#endif /* UART1_DMA_TX_CONFIG */
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#endif /* BSP_UART1_TX_USING_DMA */
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#endif /* BSP_USING_UART1 */
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#if defined(BSP_USING_UART2)
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#if defined(BSP_USING_UART2)
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#ifndef UART2_CONFIG
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#ifndef UART2_CONFIG
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#define UART2_CONFIG \
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#define UART2_CONFIG \
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@ -50,19 +61,30 @@ extern "C" {
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.irq_type = USART2_IRQn, \
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.irq_type = USART2_IRQn, \
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}
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}
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#endif /* UART2_CONFIG */
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#endif /* UART2_CONFIG */
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#endif /* BSP_USING_UART2 */
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#if defined(BSP_UART2_RX_USING_DMA)
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#if defined(BSP_UART2_RX_USING_DMA)
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#ifndef UART2_DMA_CONFIG
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#ifndef UART2_DMA_RX_CONFIG
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#define UART2_DMA_CONFIG \
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#define UART2_DMA_RX_CONFIG \
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{ \
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{ \
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.Instance = UART2_RX_DMA_INSTANCE, \
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.Instance = UART2_RX_DMA_INSTANCE, \
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.dma_rcc = UART2_RX_DMA_RCC, \
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.dma_rcc = UART2_RX_DMA_RCC, \
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.dma_irq = UART2_RX_DMA_IRQ, \
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.dma_irq = UART2_RX_DMA_IRQ, \
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}
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}
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#endif /* UART2_DMA_CONFIG */
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#endif /* UART2_DMA_RX_CONFIG */
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#endif /* BSP_UART2_RX_USING_DMA */
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#endif /* BSP_UART2_RX_USING_DMA */
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#if defined(BSP_UART2_TX_USING_DMA)
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#ifndef UART2_DMA_TX_CONFIG
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#define UART2_DMA_TX_CONFIG \
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{ \
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.Instance = UART2_TX_DMA_INSTANCE, \
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.dma_rcc = UART2_TX_DMA_RCC, \
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.dma_irq = UART2_TX_DMA_IRQ, \
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}
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#endif /* UART2_DMA_TX_CONFIG */
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#endif /* BSP_UART2_TX_USING_DMA */
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#endif /* BSP_USING_UART2 */
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#if defined(BSP_USING_UART3)
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#if defined(BSP_USING_UART3)
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#ifndef UART3_CONFIG
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#ifndef UART3_CONFIG
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#define UART3_CONFIG \
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#define UART3_CONFIG \
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@ -72,19 +94,30 @@ extern "C" {
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.irq_type = USART3_IRQn, \
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.irq_type = USART3_IRQn, \
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}
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}
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#endif /* UART3_CONFIG */
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#endif /* UART3_CONFIG */
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#endif /* BSP_USING_UART3 */
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#if defined(BSP_UART3_RX_USING_DMA)
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#if defined(BSP_UART3_RX_USING_DMA)
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#ifndef UART3_DMA_CONFIG
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#ifndef UART3_DMA_RX_CONFIG
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#define UART3_DMA_CONFIG \
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#define UART3_DMA_RX_CONFIG \
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{ \
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{ \
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.Instance = UART3_RX_DMA_INSTANCE, \
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.Instance = UART3_RX_DMA_INSTANCE, \
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.dma_rcc = UART3_RX_DMA_RCC, \
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.dma_rcc = UART3_RX_DMA_RCC, \
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.dma_irq = UART3_RX_DMA_IRQ, \
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.dma_irq = UART3_RX_DMA_IRQ, \
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}
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}
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#endif /* UART3_DMA_CONFIG */
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#endif /* UART3_DMA_RX_CONFIG */
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#endif /* BSP_UART3_RX_USING_DMA */
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#endif /* BSP_UART3_RX_USING_DMA */
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#if defined(BSP_UART3_TX_USING_DMA)
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#ifndef UART3_DMA_TX_CONFIG
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#define UART3_DMA_TX_CONFIG \
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{ \
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.Instance = UART3_TX_DMA_INSTANCE, \
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.dma_rcc = UART3_TX_DMA_RCC, \
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.dma_irq = UART3_TX_DMA_IRQ, \
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}
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#endif /* UART3_DMA_TX_CONFIG */
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#endif /* BSP_UART3_TX_USING_DMA */
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#endif /* BSP_USING_UART3 */
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#if defined(BSP_USING_UART4)
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#if defined(BSP_USING_UART4)
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#ifndef UART4_CONFIG
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#ifndef UART4_CONFIG
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#define UART4_CONFIG \
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#define UART4_CONFIG \
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@ -94,19 +127,30 @@ extern "C" {
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.irq_type = UART4_IRQn, \
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.irq_type = UART4_IRQn, \
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}
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}
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#endif /* UART4_CONFIG */
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#endif /* UART4_CONFIG */
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#endif /* BSP_USING_UART4 */
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#if defined(BSP_UART4_RX_USING_DMA)
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#if defined(BSP_UART4_RX_USING_DMA)
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#ifndef UART4_DMA_CONFIG
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#ifndef UART4_DMA_RX_CONFIG
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#define UART4_DMA_CONFIG \
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#define UART4_DMA_RX_CONFIG \
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{ \
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{ \
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.Instance = UART4_RX_DMA_INSTANCE, \
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.Instance = UART4_RX_DMA_INSTANCE, \
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.dma_rcc = UART4_RX_DMA_RCC, \
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.dma_rcc = UART4_RX_DMA_RCC, \
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.dma_irq = UART4_RX_DMA_IRQ, \
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.dma_irq = UART4_RX_DMA_IRQ, \
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}
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}
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#endif /* UART4_DMA_CONFIG */
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#endif /* UART4_DMA_RX_CONFIG */
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#endif /* BSP_UART4_RX_USING_DMA */
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#endif /* BSP_UART4_RX_USING_DMA */
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#if defined(BSP_UART4_TX_USING_DMA)
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#ifndef UART4_DMA_TX_CONFIG
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#define UART4_DMA_TX_CONFIG \
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{ \
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.Instance = UART4_TX_DMA_INSTANCE, \
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.dma_rcc = UART4_TX_DMA_RCC, \
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.dma_irq = UART4_TX_DMA_IRQ, \
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}
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#endif /* UART4_DMA_TX_CONFIG */
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#endif /* BSP_UART4_TX_USING_DMA */
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#endif /* BSP_USING_UART4 */
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#if defined(BSP_USING_UART5)
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#if defined(BSP_USING_UART5)
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#ifndef UART5_CONFIG
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#ifndef UART5_CONFIG
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#define UART5_CONFIG \
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#define UART5_CONFIG \
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@ -119,12 +163,12 @@ extern "C" {
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#endif /* BSP_USING_UART5 */
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#endif /* BSP_USING_UART5 */
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#if defined(BSP_UART5_RX_USING_DMA)
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#if defined(BSP_UART5_RX_USING_DMA)
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#ifndef UART5_DMA_CONFIG
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#ifndef UART5_DMA_RX_CONFIG
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#define UART5_DMA_CONFIG \
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#define UART5_DMA_RX_CONFIG \
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{ \
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{ \
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.Instance = DMA_NOT_AVAILABLE, \
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.Instance = DMA_NOT_AVAILABLE, \
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}
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}
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#endif /* UART5_DMA_CONFIG */
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#endif /* UART5_DMA_RX_CONFIG */
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#endif /* BSP_UART5_RX_USING_DMA */
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#endif /* BSP_UART5_RX_USING_DMA */
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#ifdef __cplusplus
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#ifdef __cplusplus
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@ -64,6 +64,12 @@ extern "C" {
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#define SPI2_RX_DMA_INSTANCE DMA1_Stream3
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#define SPI2_RX_DMA_INSTANCE DMA1_Stream3
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#define SPI2_RX_DMA_CHANNEL DMA_CHANNEL_0
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#define SPI2_RX_DMA_CHANNEL DMA_CHANNEL_0
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#define SPI2_RX_DMA_IRQ DMA1_Stream3_IRQn
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#define SPI2_RX_DMA_IRQ DMA1_Stream3_IRQn
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#elif defined(BSP_UART3_TX_USING_DMA) && !defined(UART3_TX_DMA_INSTANCE)
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#define UART3_DMA_TX_IRQHandler DMA1_Stream3_IRQHandler
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#define UART3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define UART3_TX_DMA_INSTANCE DMA1_Stream3
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#define UART3_TX_DMA_CHANNEL DMA_CHANNEL_4
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#define UART3_TX_DMA_IRQ DMA1_Stream3_IRQn
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#endif
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#endif
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/* DMA1 stream4 */
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/* DMA1 stream4 */
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@ -73,6 +79,12 @@ extern "C" {
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#define SPI2_TX_DMA_INSTANCE DMA1_Stream4
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#define SPI2_TX_DMA_INSTANCE DMA1_Stream4
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#define SPI2_TX_DMA_CHANNEL DMA_CHANNEL_0
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#define SPI2_TX_DMA_CHANNEL DMA_CHANNEL_0
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#define SPI2_TX_DMA_IRQ DMA1_Stream4_IRQn
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#define SPI2_TX_DMA_IRQ DMA1_Stream4_IRQn
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#elif defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE)
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#define UART4_DMA_TX_IRQHandler DMA1_Stream4_IRQHandler
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#define UART4_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define UART4_TX_DMA_INSTANCE DMA1_Stream4
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#define UART4_TX_DMA_CHANNEL DMA_CHANNEL_4
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#define UART4_TX_DMA_IRQ DMA1_Stream4_IRQn
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#endif
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#endif
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/* DMA1 stream5 */
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/* DMA1 stream5 */
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@ -91,6 +103,13 @@ extern "C" {
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#endif
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#endif
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/* DMA1 stream6 */
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/* DMA1 stream6 */
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#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
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#define UART2_DMA_TX_IRQHandler DMA1_Stream6_IRQHandler
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#define UART2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define UART2_TX_DMA_INSTANCE DMA1_Stream6
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#define UART2_TX_DMA_CHANNEL DMA_CHANNEL_4
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#define UART2_TX_DMA_IRQ DMA1_Stream6_IRQn
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#endif
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/* DMA1 stream7 */
|
/* DMA1 stream7 */
|
||||||
#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
|
#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
|
||||||
|
@ -99,6 +118,12 @@ extern "C" {
|
||||||
#define SPI3_TX_DMA_INSTANCE DMA1_Stream7
|
#define SPI3_TX_DMA_INSTANCE DMA1_Stream7
|
||||||
#define SPI3_TX_DMA_CHANNEL DMA_CHANNEL_0
|
#define SPI3_TX_DMA_CHANNEL DMA_CHANNEL_0
|
||||||
#define SPI3_TX_DMA_IRQ DMA1_Stream7_IRQn
|
#define SPI3_TX_DMA_IRQ DMA1_Stream7_IRQn
|
||||||
|
#elif defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE)
|
||||||
|
#define UART5_DMA_TX_IRQHandler DMA1_Stream7_IRQHandler
|
||||||
|
#define UART5_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
|
||||||
|
#define UART5_TX_DMA_INSTANCE DMA1_Stream7
|
||||||
|
#define UART5_TX_DMA_CHANNEL DMA_CHANNEL_4
|
||||||
|
#define UART5_TX_DMA_IRQ DMA1_Stream7_IRQn
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* DMA2 stream0 */
|
/* DMA2 stream0 */
|
||||||
|
@ -148,7 +173,6 @@ extern "C" {
|
||||||
|
|
||||||
/* DMA2 stream3 */
|
/* DMA2 stream3 */
|
||||||
#if defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
|
#if defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
|
||||||
|
|
||||||
#define SPI5_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler
|
#define SPI5_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler
|
||||||
#define SPI5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
|
#define SPI5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
|
||||||
#define SPI5_RX_DMA_INSTANCE DMA2_Stream3
|
#define SPI5_RX_DMA_INSTANCE DMA2_Stream3
|
||||||
|
@ -211,9 +235,22 @@ extern "C" {
|
||||||
#define SPI5_TX_DMA_INSTANCE DMA2_Stream6
|
#define SPI5_TX_DMA_INSTANCE DMA2_Stream6
|
||||||
#define SPI5_TX_DMA_CHANNEL DMA_CHANNEL_7
|
#define SPI5_TX_DMA_CHANNEL DMA_CHANNEL_7
|
||||||
#define SPI5_TX_DMA_IRQ DMA2_Stream6_IRQn
|
#define SPI5_TX_DMA_IRQ DMA2_Stream6_IRQn
|
||||||
|
#elif defined(BSP_UART6_TX_USING_DMA) && !defined(UART6_TX_DMA_INSTANCE)
|
||||||
|
#define UART6_DMA_TX_IRQHandler DMA2_Stream6_IRQHandler
|
||||||
|
#define UART6_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
|
||||||
|
#define UART6_TX_DMA_INSTANCE DMA2_Stream6
|
||||||
|
#define UART6_TX_DMA_CHANNEL DMA_CHANNEL_5
|
||||||
|
#define UART6_TX_DMA_IRQ DMA2_Stream6_IRQn
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* DMA2 stream7 */
|
/* DMA2 stream7 */
|
||||||
|
#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
|
||||||
|
#define UART1_DMA_TX_IRQHandler DMA2_Stream7_IRQHandler
|
||||||
|
#define UART1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
|
||||||
|
#define UART1_TX_DMA_INSTANCE DMA2_Stream7
|
||||||
|
#define UART1_TX_DMA_CHANNEL DMA_CHANNEL_4
|
||||||
|
#define UART1_TX_DMA_IRQ DMA2_Stream7_IRQn
|
||||||
|
#endif
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
}
|
}
|
||||||
|
|
|
@ -27,20 +27,32 @@ extern "C" {
|
||||||
.irq_type = USART1_IRQn, \
|
.irq_type = USART1_IRQn, \
|
||||||
}
|
}
|
||||||
#endif /* UART1_CONFIG */
|
#endif /* UART1_CONFIG */
|
||||||
#endif /* BSP_USING_UART1 */
|
|
||||||
|
|
||||||
#if defined(BSP_UART1_RX_USING_DMA)
|
#if defined(BSP_UART1_RX_USING_DMA)
|
||||||
#ifndef UART1_DMA_CONFIG
|
#ifndef UART1_DMA_RX_CONFIG
|
||||||
#define UART1_DMA_CONFIG \
|
#define UART1_DMA_RX_CONFIG \
|
||||||
{ \
|
{ \
|
||||||
.Instance = UART1_RX_DMA_INSTANCE, \
|
.Instance = UART1_RX_DMA_INSTANCE, \
|
||||||
.channel = UART1_RX_DMA_CHANNEL, \
|
.channel = UART1_RX_DMA_CHANNEL, \
|
||||||
.dma_rcc = UART1_RX_DMA_RCC, \
|
.dma_rcc = UART1_RX_DMA_RCC, \
|
||||||
.dma_irq = UART1_RX_DMA_IRQ, \
|
.dma_irq = UART1_RX_DMA_IRQ, \
|
||||||
}
|
}
|
||||||
#endif /* UART1_DMA_CONFIG */
|
#endif /* UART1_DMA_RX_CONFIG */
|
||||||
#endif /* BSP_UART1_RX_USING_DMA */
|
#endif /* BSP_UART1_RX_USING_DMA */
|
||||||
|
|
||||||
|
#if defined(BSP_UART1_TX_USING_DMA)
|
||||||
|
#ifndef UART1_DMA_TX_CONFIG
|
||||||
|
#define UART1_DMA_TX_CONFIG \
|
||||||
|
{ \
|
||||||
|
.Instance = UART1_TX_DMA_INSTANCE, \
|
||||||
|
.channel = UART1_TX_DMA_CHANNEL, \
|
||||||
|
.dma_rcc = UART1_TX_DMA_RCC, \
|
||||||
|
.dma_irq = UART1_TX_DMA_IRQ, \
|
||||||
|
}
|
||||||
|
#endif /* UART1_DMA_TX_CONFIG */
|
||||||
|
#endif /* BSP_UART1_TX_USING_DMA */
|
||||||
|
#endif /* BSP_USING_UART1 */
|
||||||
|
|
||||||
#if defined(BSP_USING_UART2)
|
#if defined(BSP_USING_UART2)
|
||||||
#ifndef UART2_CONFIG
|
#ifndef UART2_CONFIG
|
||||||
#define UART2_CONFIG \
|
#define UART2_CONFIG \
|
||||||
|
@ -50,20 +62,32 @@ extern "C" {
|
||||||
.irq_type = USART2_IRQn, \
|
.irq_type = USART2_IRQn, \
|
||||||
}
|
}
|
||||||
#endif /* UART2_CONFIG */
|
#endif /* UART2_CONFIG */
|
||||||
#endif /* BSP_USING_UART2 */
|
|
||||||
|
|
||||||
#if defined(BSP_UART2_RX_USING_DMA)
|
#if defined(BSP_UART2_RX_USING_DMA)
|
||||||
#ifndef UART2_DMA_CONFIG
|
#ifndef UART2_DMA_RX_CONFIG
|
||||||
#define UART2_DMA_CONFIG \
|
#define UART2_DMA_RX_CONFIG \
|
||||||
{ \
|
{ \
|
||||||
.Instance = UART2_RX_DMA_INSTANCE, \
|
.Instance = UART2_RX_DMA_INSTANCE, \
|
||||||
.channel = UART2_RX_DMA_CHANNEL, \
|
.channel = UART2_RX_DMA_CHANNEL, \
|
||||||
.dma_rcc = UART2_RX_DMA_RCC, \
|
.dma_rcc = UART2_RX_DMA_RCC, \
|
||||||
.dma_irq = UART2_RX_DMA_IRQ, \
|
.dma_irq = UART2_RX_DMA_IRQ, \
|
||||||
}
|
}
|
||||||
#endif /* UART2_DMA_CONFIG */
|
#endif /* UART2_DMA_RX_CONFIG */
|
||||||
#endif /* BSP_UART2_RX_USING_DMA */
|
#endif /* BSP_UART2_RX_USING_DMA */
|
||||||
|
|
||||||
|
#if defined(BSP_UART2_TX_USING_DMA)
|
||||||
|
#ifndef UART2_DMA_TX_CONFIG
|
||||||
|
#define UART2_DMA_TX_CONFIG \
|
||||||
|
{ \
|
||||||
|
.Instance = UART2_TX_DMA_INSTANCE, \
|
||||||
|
.channel = UART2_TX_DMA_CHANNEL, \
|
||||||
|
.dma_rcc = UART2_TX_DMA_RCC, \
|
||||||
|
.dma_irq = UART2_TX_DMA_IRQ, \
|
||||||
|
}
|
||||||
|
#endif /* UART2_DMA_TX_CONFIG */
|
||||||
|
#endif /* BSP_UART2_TX_USING_DMA */
|
||||||
|
#endif /* BSP_USING_UART2 */
|
||||||
|
|
||||||
#if defined(BSP_USING_UART3)
|
#if defined(BSP_USING_UART3)
|
||||||
#ifndef UART3_CONFIG
|
#ifndef UART3_CONFIG
|
||||||
#define UART3_CONFIG \
|
#define UART3_CONFIG \
|
||||||
|
@ -73,20 +97,32 @@ extern "C" {
|
||||||
.irq_type = USART3_IRQn, \
|
.irq_type = USART3_IRQn, \
|
||||||
}
|
}
|
||||||
#endif /* UART3_CONFIG */
|
#endif /* UART3_CONFIG */
|
||||||
#endif /* BSP_USING_UART3 */
|
|
||||||
|
|
||||||
#if defined(BSP_UART3_RX_USING_DMA)
|
#if defined(BSP_UART3_RX_USING_DMA)
|
||||||
#ifndef UART3_DMA_CONFIG
|
#ifndef UART3_DMA_RX_CONFIG
|
||||||
#define UART3_DMA_CONFIG \
|
#define UART3_DMA_RX_CONFIG \
|
||||||
{ \
|
{ \
|
||||||
.Instance = UART3_RX_DMA_INSTANCE, \
|
.Instance = UART3_RX_DMA_INSTANCE, \
|
||||||
.channel = UART3_RX_DMA_CHANNEL, \
|
.channel = UART3_RX_DMA_CHANNEL, \
|
||||||
.dma_rcc = UART3_RX_DMA_RCC, \
|
.dma_rcc = UART3_RX_DMA_RCC, \
|
||||||
.dma_irq = UART3_RX_DMA_IRQ, \
|
.dma_irq = UART3_RX_DMA_IRQ, \
|
||||||
}
|
}
|
||||||
#endif /* UART3_DMA_CONFIG */
|
#endif /* UART3_DMA_RX_CONFIG */
|
||||||
#endif /* BSP_UART3_RX_USING_DMA */
|
#endif /* BSP_UART3_RX_USING_DMA */
|
||||||
|
|
||||||
|
#if defined(BSP_UART3_TX_USING_DMA)
|
||||||
|
#ifndef UART3_DMA_TX_CONFIG
|
||||||
|
#define UART3_DMA_TX_CONFIG \
|
||||||
|
{ \
|
||||||
|
.Instance = UART3_TX_DMA_INSTANCE, \
|
||||||
|
.channel = UART3_TX_DMA_CHANNEL, \
|
||||||
|
.dma_rcc = UART3_TX_DMA_RCC, \
|
||||||
|
.dma_irq = UART3_TX_DMA_IRQ, \
|
||||||
|
}
|
||||||
|
#endif /* UART3_DMA_TX_CONFIG */
|
||||||
|
#endif /* BSP_UART3_TX_USING_DMA */
|
||||||
|
#endif /* BSP_USING_UART3 */
|
||||||
|
|
||||||
#if defined(BSP_USING_UART4)
|
#if defined(BSP_USING_UART4)
|
||||||
#ifndef UART4_CONFIG
|
#ifndef UART4_CONFIG
|
||||||
#define UART4_CONFIG \
|
#define UART4_CONFIG \
|
||||||
|
@ -96,20 +132,32 @@ extern "C" {
|
||||||
.irq_type = UART4_IRQn, \
|
.irq_type = UART4_IRQn, \
|
||||||
}
|
}
|
||||||
#endif /* UART4_CONFIG */
|
#endif /* UART4_CONFIG */
|
||||||
#endif /* BSP_USING_UART4 */
|
|
||||||
|
|
||||||
#if defined(BSP_UART4_RX_USING_DMA)
|
#if defined(BSP_UART4_RX_USING_DMA)
|
||||||
#ifndef UART4_DMA_CONFIG
|
#ifndef UART4_DMA_RX_CONFIG
|
||||||
#define UART4_DMA_CONFIG \
|
#define UART4_DMA_RX_CONFIG \
|
||||||
{ \
|
{ \
|
||||||
.Instance = UART4_RX_DMA_INSTANCE, \
|
.Instance = UART4_RX_DMA_INSTANCE, \
|
||||||
.channel = UART4_RX_DMA_CHANNEL, \
|
.channel = UART4_RX_DMA_CHANNEL, \
|
||||||
.dma_rcc = UART4_RX_DMA_RCC, \
|
.dma_rcc = UART4_RX_DMA_RCC, \
|
||||||
.dma_irq = UART4_RX_DMA_IRQ, \
|
.dma_irq = UART4_RX_DMA_IRQ, \
|
||||||
}
|
}
|
||||||
#endif /* UART4_DMA_CONFIG */
|
#endif /* UART4_DMA_RX_CONFIG */
|
||||||
#endif /* BSP_UART4_RX_USING_DMA */
|
#endif /* BSP_UART4_RX_USING_DMA */
|
||||||
|
|
||||||
|
#if defined(BSP_UART4_TX_USING_DMA)
|
||||||
|
#ifndef UART4_DMA_TX_CONFIG
|
||||||
|
#define UART4_DMA_TX_CONFIG \
|
||||||
|
{ \
|
||||||
|
.Instance = UART4_TX_DMA_INSTANCE, \
|
||||||
|
.channel = UART4_TX_DMA_CHANNEL, \
|
||||||
|
.dma_rcc = UART4_TX_DMA_RCC, \
|
||||||
|
.dma_irq = UART4_TX_DMA_IRQ, \
|
||||||
|
}
|
||||||
|
#endif /* UART4_DMA_TX_CONFIG */
|
||||||
|
#endif /* BSP_UART4_RX_USING_DMA */
|
||||||
|
#endif /* BSP_USING_UART4 */
|
||||||
|
|
||||||
#if defined(BSP_USING_UART5)
|
#if defined(BSP_USING_UART5)
|
||||||
#ifndef UART5_CONFIG
|
#ifndef UART5_CONFIG
|
||||||
#define UART5_CONFIG \
|
#define UART5_CONFIG \
|
||||||
|
@ -119,20 +167,32 @@ extern "C" {
|
||||||
.irq_type = UART5_IRQn, \
|
.irq_type = UART5_IRQn, \
|
||||||
}
|
}
|
||||||
#endif /* UART5_CONFIG */
|
#endif /* UART5_CONFIG */
|
||||||
#endif /* BSP_USING_UART5 */
|
|
||||||
|
|
||||||
#if defined(BSP_UART5_RX_USING_DMA)
|
#if defined(BSP_UART5_RX_USING_DMA)
|
||||||
#ifndef UART5_DMA_CONFIG
|
#ifndef UART5_DMA_RX_CONFIG
|
||||||
#define UART5_DMA_CONFIG \
|
#define UART5_DMA_RX_CONFIG \
|
||||||
{ \
|
{ \
|
||||||
.Instance = UART5_RX_DMA_INSTANCE, \
|
.Instance = UART5_RX_DMA_INSTANCE, \
|
||||||
.channel = UART5_RX_DMA_CHANNEL, \
|
.channel = UART5_RX_DMA_CHANNEL, \
|
||||||
.dma_rcc = UART5_RX_DMA_RCC, \
|
.dma_rcc = UART5_RX_DMA_RCC, \
|
||||||
.dma_irq = UART5_RX_DMA_IRQ, \
|
.dma_irq = UART5_RX_DMA_IRQ, \
|
||||||
}
|
}
|
||||||
#endif /* UART5_DMA_CONFIG */
|
#endif /* UART5_DMA_RX_CONFIG */
|
||||||
#endif /* BSP_UART5_RX_USING_DMA */
|
#endif /* BSP_UART5_RX_USING_DMA */
|
||||||
|
|
||||||
|
#if defined(BSP_UART5_TX_USING_DMA)
|
||||||
|
#ifndef UART5_DMA_TX_CONFIG
|
||||||
|
#define UART5_DMA_TX_CONFIG \
|
||||||
|
{ \
|
||||||
|
.Instance = UART5_TX_DMA_INSTANCE, \
|
||||||
|
.channel = UART5_TX_DMA_CHANNEL, \
|
||||||
|
.dma_rcc = UART5_TX_DMA_RCC, \
|
||||||
|
.dma_irq = UART5_TX_DMA_IRQ, \
|
||||||
|
}
|
||||||
|
#endif /* UART5_DMA_TX_CONFIG */
|
||||||
|
#endif /* BSP_UART5_TX_USING_DMA */
|
||||||
|
#endif /* BSP_USING_UART5 */
|
||||||
|
|
||||||
#if defined(BSP_USING_UART6)
|
#if defined(BSP_USING_UART6)
|
||||||
#ifndef UART6_CONFIG
|
#ifndef UART6_CONFIG
|
||||||
#define UART6_CONFIG \
|
#define UART6_CONFIG \
|
||||||
|
@ -142,20 +202,32 @@ extern "C" {
|
||||||
.irq_type = USART6_IRQn, \
|
.irq_type = USART6_IRQn, \
|
||||||
}
|
}
|
||||||
#endif /* UART6_CONFIG */
|
#endif /* UART6_CONFIG */
|
||||||
#endif /* BSP_USING_UART6 */
|
|
||||||
|
|
||||||
#if defined(BSP_UART6_RX_USING_DMA)
|
#if defined(BSP_UART6_RX_USING_DMA)
|
||||||
#ifndef UART6_DMA_CONFIG
|
#ifndef UART6_DMA_RX_CONFIG
|
||||||
#define UART6_DMA_CONFIG \
|
#define UART6_DMA_RX_CONFIG \
|
||||||
{ \
|
{ \
|
||||||
.Instance = UART6_RX_DMA_INSTANCE, \
|
.Instance = UART6_RX_DMA_INSTANCE, \
|
||||||
.channel = UART6_RX_DMA_CHANNEL, \
|
.channel = UART6_RX_DMA_CHANNEL, \
|
||||||
.dma_rcc = UART6_RX_DMA_RCC, \
|
.dma_rcc = UART6_RX_DMA_RCC, \
|
||||||
.dma_irq = UART6_RX_DMA_IRQ, \
|
.dma_irq = UART6_RX_DMA_IRQ, \
|
||||||
}
|
}
|
||||||
#endif /* UART6_DMA_CONFIG */
|
#endif /* UART6_DMA_RX_CONFIG */
|
||||||
#endif /* BSP_UART6_RX_USING_DMA */
|
#endif /* BSP_UART6_RX_USING_DMA */
|
||||||
|
|
||||||
|
#if defined(BSP_UART6_TX_USING_DMA)
|
||||||
|
#ifndef UART6_DMA_TX_CONFIG
|
||||||
|
#define UART6_DMA_TX_CONFIG \
|
||||||
|
{ \
|
||||||
|
.Instance = UART6_TX_DMA_INSTANCE, \
|
||||||
|
.channel = UART6_TX_DMA_CHANNEL, \
|
||||||
|
.dma_rcc = UART6_TX_DMA_RCC, \
|
||||||
|
.dma_irq = UART6_TX_DMA_IRQ, \
|
||||||
|
}
|
||||||
|
#endif /* UART6_DMA_TX_CONFIG */
|
||||||
|
#endif /* BSP_UART6_TX_USING_DMA */
|
||||||
|
#endif /* BSP_USING_UART6 */
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -30,15 +30,15 @@ extern "C" {
|
||||||
#endif /* BSP_USING_UART1 */
|
#endif /* BSP_USING_UART1 */
|
||||||
|
|
||||||
#if defined(BSP_UART1_RX_USING_DMA)
|
#if defined(BSP_UART1_RX_USING_DMA)
|
||||||
#ifndef UART1_DMA_CONFIG
|
#ifndef UART1_DMA_RX_CONFIG
|
||||||
#define UART1_DMA_CONFIG \
|
#define UART1_DMA_RX_CONFIG \
|
||||||
{ \
|
{ \
|
||||||
.Instance = UART1_RX_DMA_INSTANCE, \
|
.Instance = UART1_RX_DMA_INSTANCE, \
|
||||||
.channel = UART1_RX_DMA_CHANNEL, \
|
.channel = UART1_RX_DMA_CHANNEL, \
|
||||||
.dma_rcc = UART1_RX_DMA_RCC, \
|
.dma_rcc = UART1_RX_DMA_RCC, \
|
||||||
.dma_irq = UART1_RX_DMA_IRQ, \
|
.dma_irq = UART1_RX_DMA_IRQ, \
|
||||||
}
|
}
|
||||||
#endif /* UART1_DMA_CONFIG */
|
#endif /* UART1_DMA_RX_CONFIG */
|
||||||
#endif /* BSP_UART1_RX_USING_DMA */
|
#endif /* BSP_UART1_RX_USING_DMA */
|
||||||
|
|
||||||
#if defined(BSP_USING_UART2)
|
#if defined(BSP_USING_UART2)
|
||||||
|
@ -53,15 +53,15 @@ extern "C" {
|
||||||
#endif /* BSP_USING_UART2 */
|
#endif /* BSP_USING_UART2 */
|
||||||
|
|
||||||
#if defined(BSP_UART2_RX_USING_DMA)
|
#if defined(BSP_UART2_RX_USING_DMA)
|
||||||
#ifndef UART2_DMA_CONFIG
|
#ifndef UART2_DMA_RX_CONFIG
|
||||||
#define UART2_DMA_CONFIG \
|
#define UART2_DMA_RX_CONFIG \
|
||||||
{ \
|
{ \
|
||||||
.Instance = UART2_RX_DMA_INSTANCE, \
|
.Instance = UART2_RX_DMA_INSTANCE, \
|
||||||
.channel = UART2_RX_DMA_CHANNEL, \
|
.channel = UART2_RX_DMA_CHANNEL, \
|
||||||
.dma_rcc = UART2_RX_DMA_RCC, \
|
.dma_rcc = UART2_RX_DMA_RCC, \
|
||||||
.dma_irq = UART2_RX_DMA_IRQ, \
|
.dma_irq = UART2_RX_DMA_IRQ, \
|
||||||
}
|
}
|
||||||
#endif /* UART2_DMA_CONFIG */
|
#endif /* UART2_DMA_RX_CONFIG */
|
||||||
#endif /* BSP_UART2_RX_USING_DMA */
|
#endif /* BSP_UART2_RX_USING_DMA */
|
||||||
|
|
||||||
#if defined(BSP_USING_UART3)
|
#if defined(BSP_USING_UART3)
|
||||||
|
@ -76,15 +76,15 @@ extern "C" {
|
||||||
#endif /* BSP_USING_UART3 */
|
#endif /* BSP_USING_UART3 */
|
||||||
|
|
||||||
#if defined(BSP_UART3_RX_USING_DMA)
|
#if defined(BSP_UART3_RX_USING_DMA)
|
||||||
#ifndef UART3_DMA_CONFIG
|
#ifndef UART3_DMA_RX_CONFIG
|
||||||
#define UART3_DMA_CONFIG \
|
#define UART3_DMA_RX_CONFIG \
|
||||||
{ \
|
{ \
|
||||||
.Instance = UART3_RX_DMA_INSTANCE, \
|
.Instance = UART3_RX_DMA_INSTANCE, \
|
||||||
.channel = UART3_RX_DMA_CHANNEL, \
|
.channel = UART3_RX_DMA_CHANNEL, \
|
||||||
.dma_rcc = UART3_RX_DMA_RCC, \
|
.dma_rcc = UART3_RX_DMA_RCC, \
|
||||||
.dma_irq = UART3_RX_DMA_IRQ, \
|
.dma_irq = UART3_RX_DMA_IRQ, \
|
||||||
}
|
}
|
||||||
#endif /* UART3_DMA_CONFIG */
|
#endif /* UART3_DMA_RX_CONFIG */
|
||||||
#endif /* BSP_UART3_RX_USING_DMA */
|
#endif /* BSP_UART3_RX_USING_DMA */
|
||||||
|
|
||||||
#if defined(BSP_USING_UART4)
|
#if defined(BSP_USING_UART4)
|
||||||
|
@ -99,15 +99,15 @@ extern "C" {
|
||||||
#endif /* BSP_USING_UART4 */
|
#endif /* BSP_USING_UART4 */
|
||||||
|
|
||||||
#if defined(BSP_UART4_RX_USING_DMA)
|
#if defined(BSP_UART4_RX_USING_DMA)
|
||||||
#ifndef UART4_DMA_CONFIG
|
#ifndef UART4_DMA_RX_CONFIG
|
||||||
#define UART4_DMA_CONFIG \
|
#define UART4_DMA_RX_CONFIG \
|
||||||
{ \
|
{ \
|
||||||
.Instance = UART4_RX_DMA_INSTANCE, \
|
.Instance = UART4_RX_DMA_INSTANCE, \
|
||||||
.channel = UART4_RX_DMA_CHANNEL, \
|
.channel = UART4_RX_DMA_CHANNEL, \
|
||||||
.dma_rcc = UART4_RX_DMA_RCC, \
|
.dma_rcc = UART4_RX_DMA_RCC, \
|
||||||
.dma_irq = UART4_RX_DMA_IRQ, \
|
.dma_irq = UART4_RX_DMA_IRQ, \
|
||||||
}
|
}
|
||||||
#endif /* UART4_DMA_CONFIG */
|
#endif /* UART4_DMA_RX_CONFIG */
|
||||||
#endif /* BSP_UART4_RX_USING_DMA */
|
#endif /* BSP_UART4_RX_USING_DMA */
|
||||||
|
|
||||||
#if defined(BSP_USING_UART5)
|
#if defined(BSP_USING_UART5)
|
||||||
|
@ -122,15 +122,15 @@ extern "C" {
|
||||||
#endif /* BSP_USING_UART5 */
|
#endif /* BSP_USING_UART5 */
|
||||||
|
|
||||||
#if defined(BSP_UART5_RX_USING_DMA)
|
#if defined(BSP_UART5_RX_USING_DMA)
|
||||||
#ifndef UART5_DMA_CONFIG
|
#ifndef UART5_DMA_RX_CONFIG
|
||||||
#define UART5_DMA_CONFIG \
|
#define UART5_DMA_RX_CONFIG \
|
||||||
{ \
|
{ \
|
||||||
.Instance = UART5_RX_DMA_INSTANCE, \
|
.Instance = UART5_RX_DMA_INSTANCE, \
|
||||||
.channel = UART5_RX_DMA_CHANNEL, \
|
.channel = UART5_RX_DMA_CHANNEL, \
|
||||||
.dma_rcc = UART5_RX_DMA_RCC, \
|
.dma_rcc = UART5_RX_DMA_RCC, \
|
||||||
.dma_irq = UART5_RX_DMA_IRQ, \
|
.dma_irq = UART5_RX_DMA_IRQ, \
|
||||||
}
|
}
|
||||||
#endif /* UART5_DMA_CONFIG */
|
#endif /* UART5_DMA_RX_CONFIG */
|
||||||
#endif /* BSP_UART5_RX_USING_DMA */
|
#endif /* BSP_UART5_RX_USING_DMA */
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
|
|
|
@ -48,15 +48,15 @@
|
||||||
#endif /* BSP_USING_UART1 */
|
#endif /* BSP_USING_UART1 */
|
||||||
|
|
||||||
#if defined(BSP_UART1_RX_USING_DMA)
|
#if defined(BSP_UART1_RX_USING_DMA)
|
||||||
#ifndef UART1_DMA_CONFIG
|
#ifndef UART1_DMA_RX_CONFIG
|
||||||
#define UART1_DMA_CONFIG \
|
#define UART1_DMA_RX_CONFIG \
|
||||||
{ \
|
{ \
|
||||||
.Instance = UART1_RX_DMA_INSTANCE, \
|
.Instance = UART1_RX_DMA_INSTANCE, \
|
||||||
.request = UART1_RX_DMA_REQUEST, \
|
.request = UART1_RX_DMA_REQUEST, \
|
||||||
.dma_rcc = UART1_RX_DMA_RCC, \
|
.dma_rcc = UART1_RX_DMA_RCC, \
|
||||||
.dma_irq = UART1_RX_DMA_IRQ, \
|
.dma_irq = UART1_RX_DMA_IRQ, \
|
||||||
}
|
}
|
||||||
#endif /* UART1_DMA_CONFIG */
|
#endif /* UART1_DMA_RX_CONFIG */
|
||||||
#endif /* BSP_UART1_RX_USING_DMA */
|
#endif /* BSP_UART1_RX_USING_DMA */
|
||||||
|
|
||||||
#if defined(BSP_USING_UART2)
|
#if defined(BSP_USING_UART2)
|
||||||
|
@ -71,15 +71,15 @@
|
||||||
#endif /* BSP_USING_UART2 */
|
#endif /* BSP_USING_UART2 */
|
||||||
|
|
||||||
#if defined(BSP_UART2_RX_USING_DMA)
|
#if defined(BSP_UART2_RX_USING_DMA)
|
||||||
#ifndef UART2_DMA_CONFIG
|
#ifndef UART2_DMA_RX_CONFIG
|
||||||
#define UART2_DMA_CONFIG \
|
#define UART2_DMA_RX_CONFIG \
|
||||||
{ \
|
{ \
|
||||||
.Instance = UART2_RX_DMA_INSTANCE, \
|
.Instance = UART2_RX_DMA_INSTANCE, \
|
||||||
.request = UART2_RX_DMA_REQUEST, \
|
.request = UART2_RX_DMA_REQUEST, \
|
||||||
.dma_rcc = UART2_RX_DMA_RCC, \
|
.dma_rcc = UART2_RX_DMA_RCC, \
|
||||||
.dma_irq = UART2_RX_DMA_IRQ, \
|
.dma_irq = UART2_RX_DMA_IRQ, \
|
||||||
}
|
}
|
||||||
#endif /* UART2_DMA_CONFIG */
|
#endif /* UART2_DMA_RX_CONFIG */
|
||||||
#endif /* BSP_UART2_RX_USING_DMA */
|
#endif /* BSP_UART2_RX_USING_DMA */
|
||||||
|
|
||||||
#if defined(BSP_USING_UART3)
|
#if defined(BSP_USING_UART3)
|
||||||
|
@ -103,15 +103,15 @@
|
||||||
#endif /* BSP_USING_UART3 */
|
#endif /* BSP_USING_UART3 */
|
||||||
|
|
||||||
#if defined(BSP_UART3_RX_USING_DMA)
|
#if defined(BSP_UART3_RX_USING_DMA)
|
||||||
#ifndef UART3_DMA_CONFIG
|
#ifndef UART3_DMA_RX_CONFIG
|
||||||
#define UART3_DMA_CONFIG \
|
#define UART3_DMA_RX_CONFIG \
|
||||||
{ \
|
{ \
|
||||||
.Instance = UART3_RX_DMA_INSTANCE, \
|
.Instance = UART3_RX_DMA_INSTANCE, \
|
||||||
.request = UART3_RX_DMA_REQUEST, \
|
.request = UART3_RX_DMA_REQUEST, \
|
||||||
.dma_rcc = UART3_RX_DMA_RCC, \
|
.dma_rcc = UART3_RX_DMA_RCC, \
|
||||||
.dma_irq = UART3_RX_DMA_IRQ, \
|
.dma_irq = UART3_RX_DMA_IRQ, \
|
||||||
}
|
}
|
||||||
#endif /* UART3_DMA_CONFIG */
|
#endif /* UART3_DMA_RX_CONFIG */
|
||||||
#endif /* BSP_UART3_RX_USING_DMA */
|
#endif /* BSP_UART3_RX_USING_DMA */
|
||||||
|
|
||||||
#if defined(BSP_USING_UART4)
|
#if defined(BSP_USING_UART4)
|
||||||
|
@ -135,15 +135,15 @@
|
||||||
#endif /* BSP_USING_UART4 */
|
#endif /* BSP_USING_UART4 */
|
||||||
|
|
||||||
#if defined(BSP_UART4_RX_USING_DMA)
|
#if defined(BSP_UART4_RX_USING_DMA)
|
||||||
#ifndef UART4_DMA_CONFIG
|
#ifndef UART4_DMA_RX_CONFIG
|
||||||
#define UART4_DMA_CONFIG \
|
#define UART4_DMA_RX_CONFIG \
|
||||||
{ \
|
{ \
|
||||||
.Instance = UART4_RX_DMA_INSTANCE, \
|
.Instance = UART4_RX_DMA_INSTANCE, \
|
||||||
.request = UART4_RX_DMA_REQUEST, \
|
.request = UART4_RX_DMA_REQUEST, \
|
||||||
.dma_rcc = UART4_RX_DMA_RCC, \
|
.dma_rcc = UART4_RX_DMA_RCC, \
|
||||||
.dma_irq = UART4_RX_DMA_IRQ, \
|
.dma_irq = UART4_RX_DMA_IRQ, \
|
||||||
}
|
}
|
||||||
#endif /* UART4_DMA_CONFIG */
|
#endif /* UART4_DMA_RX_CONFIG */
|
||||||
#endif /* BSP_UART4_RX_USING_DMA */
|
#endif /* BSP_UART4_RX_USING_DMA */
|
||||||
|
|
||||||
#if defined(BSP_USING_UART5)
|
#if defined(BSP_USING_UART5)
|
||||||
|
@ -158,12 +158,12 @@
|
||||||
#endif /* BSP_USING_UART5 */
|
#endif /* BSP_USING_UART5 */
|
||||||
|
|
||||||
#if defined(BSP_UART5_RX_USING_DMA)
|
#if defined(BSP_UART5_RX_USING_DMA)
|
||||||
#ifndef UART5_DMA_CONFIG
|
#ifndef UART5_DMA_RX_CONFIG
|
||||||
#define UART5_DMA_CONFIG \
|
#define UART5_DMA_RX_CONFIG \
|
||||||
{ \
|
{ \
|
||||||
.Instance = DMA_NOT_AVAILABLE, \
|
.Instance = DMA_NOT_AVAILABLE, \
|
||||||
}
|
}
|
||||||
#endif /* UART5_DMA_CONFIG */
|
#endif /* UART5_DMA_RX_CONFIG */
|
||||||
#endif /* BSP_UART5_RX_USING_DMA */
|
#endif /* BSP_UART5_RX_USING_DMA */
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
|
|
|
@ -30,15 +30,15 @@ extern "C" {
|
||||||
#endif /* BSP_USING_UART1 */
|
#endif /* BSP_USING_UART1 */
|
||||||
|
|
||||||
#if defined(BSP_UART1_RX_USING_DMA)
|
#if defined(BSP_UART1_RX_USING_DMA)
|
||||||
#ifndef UART1_DMA_CONFIG
|
#ifndef UART1_DMA_RX_CONFIG
|
||||||
#define UART1_DMA_CONFIG \
|
#define UART1_DMA_RX_CONFIG \
|
||||||
{ \
|
{ \
|
||||||
.Instance = UART1_RX_DMA_INSTANCE, \
|
.Instance = UART1_RX_DMA_INSTANCE, \
|
||||||
.channel = UART1_RX_DMA_CHANNEL, \
|
.channel = UART1_RX_DMA_CHANNEL, \
|
||||||
.dma_rcc = UART1_RX_DMA_RCC, \
|
.dma_rcc = UART1_RX_DMA_RCC, \
|
||||||
.dma_irq = UART1_RX_DMA_IRQ, \
|
.dma_irq = UART1_RX_DMA_IRQ, \
|
||||||
}
|
}
|
||||||
#endif /* UART1_DMA_CONFIG */
|
#endif /* UART1_DMA_RX_CONFIG */
|
||||||
#endif /* BSP_UART1_RX_USING_DMA */
|
#endif /* BSP_UART1_RX_USING_DMA */
|
||||||
|
|
||||||
#if defined(BSP_USING_UART2)
|
#if defined(BSP_USING_UART2)
|
||||||
|
@ -53,15 +53,15 @@ extern "C" {
|
||||||
#endif /* BSP_USING_UART2 */
|
#endif /* BSP_USING_UART2 */
|
||||||
|
|
||||||
#if defined(BSP_UART2_RX_USING_DMA)
|
#if defined(BSP_UART2_RX_USING_DMA)
|
||||||
#ifndef UART2_DMA_CONFIG
|
#ifndef UART2_DMA_RX_CONFIG
|
||||||
#define UART2_DMA_CONFIG \
|
#define UART2_DMA_RX_CONFIG \
|
||||||
{ \
|
{ \
|
||||||
.Instance = UART2_RX_DMA_INSTANCE, \
|
.Instance = UART2_RX_DMA_INSTANCE, \
|
||||||
.channel = UART2_RX_DMA_CHANNEL, \
|
.channel = UART2_RX_DMA_CHANNEL, \
|
||||||
.dma_rcc = UART2_RX_DMA_RCC, \
|
.dma_rcc = UART2_RX_DMA_RCC, \
|
||||||
.dma_irq = UART2_RX_DMA_IRQ, \
|
.dma_irq = UART2_RX_DMA_IRQ, \
|
||||||
}
|
}
|
||||||
#endif /* UART2_DMA_CONFIG */
|
#endif /* UART2_DMA_RX_CONFIG */
|
||||||
#endif /* BSP_UART2_RX_USING_DMA */
|
#endif /* BSP_UART2_RX_USING_DMA */
|
||||||
|
|
||||||
#if defined(BSP_USING_UART3)
|
#if defined(BSP_USING_UART3)
|
||||||
|
@ -76,15 +76,15 @@ extern "C" {
|
||||||
#endif /* BSP_USING_UART3 */
|
#endif /* BSP_USING_UART3 */
|
||||||
|
|
||||||
#if defined(BSP_UART3_RX_USING_DMA)
|
#if defined(BSP_UART3_RX_USING_DMA)
|
||||||
#ifndef UART3_DMA_CONFIG
|
#ifndef UART3_DMA_RX_CONFIG
|
||||||
#define UART3_DMA_CONFIG \
|
#define UART3_DMA_RX_CONFIG \
|
||||||
{ \
|
{ \
|
||||||
.Instance = UART3_RX_DMA_INSTANCE, \
|
.Instance = UART3_RX_DMA_INSTANCE, \
|
||||||
.channel = UART3_RX_DMA_CHANNEL, \
|
.channel = UART3_RX_DMA_CHANNEL, \
|
||||||
.dma_rcc = UART3_RX_DMA_RCC, \
|
.dma_rcc = UART3_RX_DMA_RCC, \
|
||||||
.dma_irq = UART3_RX_DMA_IRQ, \
|
.dma_irq = UART3_RX_DMA_IRQ, \
|
||||||
}
|
}
|
||||||
#endif /* UART3_DMA_CONFIG */
|
#endif /* UART3_DMA_RX_CONFIG */
|
||||||
#endif /* BSP_UART3_RX_USING_DMA */
|
#endif /* BSP_UART3_RX_USING_DMA */
|
||||||
|
|
||||||
#if defined(BSP_USING_UART4)
|
#if defined(BSP_USING_UART4)
|
||||||
|
@ -99,15 +99,15 @@ extern "C" {
|
||||||
#endif /* BSP_USING_UART4 */
|
#endif /* BSP_USING_UART4 */
|
||||||
|
|
||||||
#if defined(BSP_UART4_RX_USING_DMA)
|
#if defined(BSP_UART4_RX_USING_DMA)
|
||||||
#ifndef UART4_DMA_CONFIG
|
#ifndef UART4_DMA_RX_CONFIG
|
||||||
#define UART4_DMA_CONFIG \
|
#define UART4_DMA_RX_CONFIG \
|
||||||
{ \
|
{ \
|
||||||
.Instance = UART4_RX_DMA_INSTANCE, \
|
.Instance = UART4_RX_DMA_INSTANCE, \
|
||||||
.channel = UART4_RX_DMA_CHANNEL, \
|
.channel = UART4_RX_DMA_CHANNEL, \
|
||||||
.dma_rcc = UART4_RX_DMA_RCC, \
|
.dma_rcc = UART4_RX_DMA_RCC, \
|
||||||
.dma_irq = UART4_RX_DMA_IRQ, \
|
.dma_irq = UART4_RX_DMA_IRQ, \
|
||||||
}
|
}
|
||||||
#endif /* UART4_DMA_CONFIG */
|
#endif /* UART4_DMA_RX_CONFIG */
|
||||||
#endif /* BSP_UART4_RX_USING_DMA */
|
#endif /* BSP_UART4_RX_USING_DMA */
|
||||||
|
|
||||||
#if defined(BSP_USING_UART5)
|
#if defined(BSP_USING_UART5)
|
||||||
|
@ -122,15 +122,15 @@ extern "C" {
|
||||||
#endif /* BSP_USING_UART5 */
|
#endif /* BSP_USING_UART5 */
|
||||||
|
|
||||||
#if defined(BSP_UART5_RX_USING_DMA)
|
#if defined(BSP_UART5_RX_USING_DMA)
|
||||||
#ifndef UART5_DMA_CONFIG
|
#ifndef UART5_DMA_RX_CONFIG
|
||||||
#define UART5_DMA_CONFIG \
|
#define UART5_DMA_RX_CONFIG \
|
||||||
{ \
|
{ \
|
||||||
.Instance = UART5_RX_DMA_INSTANCE, \
|
.Instance = UART5_RX_DMA_INSTANCE, \
|
||||||
.channel = UART5_RX_DMA_CHANNEL, \
|
.channel = UART5_RX_DMA_CHANNEL, \
|
||||||
.dma_rcc = UART5_RX_DMA_RCC, \
|
.dma_rcc = UART5_RX_DMA_RCC, \
|
||||||
.dma_irq = UART5_RX_DMA_IRQ, \
|
.dma_irq = UART5_RX_DMA_IRQ, \
|
||||||
}
|
}
|
||||||
#endif /* UART5_DMA_CONFIG */
|
#endif /* UART5_DMA_RX_CONFIG */
|
||||||
#endif /* BSP_UART5_RX_USING_DMA */
|
#endif /* BSP_UART5_RX_USING_DMA */
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
|
|
|
@ -29,14 +29,14 @@ extern "C" {
|
||||||
#endif /* BSP_USING_UART1 */
|
#endif /* BSP_USING_UART1 */
|
||||||
|
|
||||||
#if defined(BSP_UART1_RX_USING_DMA)
|
#if defined(BSP_UART1_RX_USING_DMA)
|
||||||
#ifndef UART1_DMA_CONFIG
|
#ifndef UART1_DMA_RX_CONFIG
|
||||||
#define UART1_DMA_CONFIG \
|
#define UART1_DMA_RX_CONFIG \
|
||||||
{ \
|
{ \
|
||||||
.Instance = UART1_RX_DMA_INSTANCE, \
|
.Instance = UART1_RX_DMA_INSTANCE, \
|
||||||
.dma_rcc = UART1_RX_DMA_RCC, \
|
.dma_rcc = UART1_RX_DMA_RCC, \
|
||||||
.dma_irq = UART1_RX_DMA_IRQ, \
|
.dma_irq = UART1_RX_DMA_IRQ, \
|
||||||
}
|
}
|
||||||
#endif /* UART1_DMA_CONFIG */
|
#endif /* UART1_DMA_RX_CONFIG */
|
||||||
#endif /* BSP_UART1_RX_USING_DMA */
|
#endif /* BSP_UART1_RX_USING_DMA */
|
||||||
|
|
||||||
#if defined(BSP_USING_UART2)
|
#if defined(BSP_USING_UART2)
|
||||||
|
@ -51,14 +51,14 @@ extern "C" {
|
||||||
#endif /* BSP_USING_UART2 */
|
#endif /* BSP_USING_UART2 */
|
||||||
|
|
||||||
#if defined(BSP_UART2_RX_USING_DMA)
|
#if defined(BSP_UART2_RX_USING_DMA)
|
||||||
#ifndef UART2_DMA_CONFIG
|
#ifndef UART2_DMA_RX_CONFIG
|
||||||
#define UART2_DMA_CONFIG \
|
#define UART2_DMA_RX_CONFIG \
|
||||||
{ \
|
{ \
|
||||||
.Instance = UART2_RX_DMA_INSTANCE, \
|
.Instance = UART2_RX_DMA_INSTANCE, \
|
||||||
.dma_rcc = UART2_RX_DMA_RCC, \
|
.dma_rcc = UART2_RX_DMA_RCC, \
|
||||||
.dma_irq = UART2_RX_DMA_IRQ, \
|
.dma_irq = UART2_RX_DMA_IRQ, \
|
||||||
}
|
}
|
||||||
#endif /* UART2_DMA_CONFIG */
|
#endif /* UART2_DMA_RX_CONFIG */
|
||||||
#endif /* BSP_UART2_RX_USING_DMA */
|
#endif /* BSP_UART2_RX_USING_DMA */
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
|
|
|
@ -51,15 +51,15 @@ extern "C" {
|
||||||
#endif /* BSP_USING_UART1 */
|
#endif /* BSP_USING_UART1 */
|
||||||
|
|
||||||
#if defined(BSP_UART1_RX_USING_DMA)
|
#if defined(BSP_UART1_RX_USING_DMA)
|
||||||
#ifndef UART1_DMA_CONFIG
|
#ifndef UART1_DMA_RX_CONFIG
|
||||||
#define UART1_DMA_CONFIG \
|
#define UART1_DMA_RX_CONFIG \
|
||||||
{ \
|
{ \
|
||||||
.Instance = UART1_RX_DMA_INSTANCE, \
|
.Instance = UART1_RX_DMA_INSTANCE, \
|
||||||
.request = UART1_RX_DMA_REQUEST, \
|
.request = UART1_RX_DMA_REQUEST, \
|
||||||
.dma_rcc = UART1_RX_DMA_RCC, \
|
.dma_rcc = UART1_RX_DMA_RCC, \
|
||||||
.dma_irq = UART1_RX_DMA_IRQ, \
|
.dma_irq = UART1_RX_DMA_IRQ, \
|
||||||
}
|
}
|
||||||
#endif /* UART1_DMA_CONFIG */
|
#endif /* UART1_DMA_RX_CONFIG */
|
||||||
#endif /* BSP_UART1_RX_USING_DMA */
|
#endif /* BSP_UART1_RX_USING_DMA */
|
||||||
|
|
||||||
#if defined(BSP_USING_UART2)
|
#if defined(BSP_USING_UART2)
|
||||||
|
@ -74,15 +74,15 @@ extern "C" {
|
||||||
#endif /* BSP_USING_UART2 */
|
#endif /* BSP_USING_UART2 */
|
||||||
|
|
||||||
#if defined(BSP_UART2_RX_USING_DMA)
|
#if defined(BSP_UART2_RX_USING_DMA)
|
||||||
#ifndef UART2_DMA_CONFIG
|
#ifndef UART2_DMA_RX_CONFIG
|
||||||
#define UART2_DMA_CONFIG \
|
#define UART2_DMA_RX_CONFIG \
|
||||||
{ \
|
{ \
|
||||||
.Instance = UART2_RX_DMA_INSTANCE, \
|
.Instance = UART2_RX_DMA_INSTANCE, \
|
||||||
.request = UART2_RX_DMA_REQUEST, \
|
.request = UART2_RX_DMA_REQUEST, \
|
||||||
.dma_rcc = UART2_RX_DMA_RCC, \
|
.dma_rcc = UART2_RX_DMA_RCC, \
|
||||||
.dma_irq = UART2_RX_DMA_IRQ, \
|
.dma_irq = UART2_RX_DMA_IRQ, \
|
||||||
}
|
}
|
||||||
#endif /* UART2_DMA_CONFIG */
|
#endif /* UART2_DMA_RX_CONFIG */
|
||||||
#endif /* BSP_UART2_RX_USING_DMA */
|
#endif /* BSP_UART2_RX_USING_DMA */
|
||||||
|
|
||||||
#if defined(BSP_USING_UART3)
|
#if defined(BSP_USING_UART3)
|
||||||
|
@ -97,15 +97,15 @@ extern "C" {
|
||||||
#endif /* BSP_USING_UART3 */
|
#endif /* BSP_USING_UART3 */
|
||||||
|
|
||||||
#if defined(BSP_UART3_RX_USING_DMA)
|
#if defined(BSP_UART3_RX_USING_DMA)
|
||||||
#ifndef UART3_DMA_CONFIG
|
#ifndef UART3_DMA_RX_CONFIG
|
||||||
#define UART3_DMA_CONFIG \
|
#define UART3_DMA_RX_CONFIG \
|
||||||
{ \
|
{ \
|
||||||
.Instance = UART3_RX_DMA_INSTANCE, \
|
.Instance = UART3_RX_DMA_INSTANCE, \
|
||||||
.request = UART3_RX_DMA_REQUEST, \
|
.request = UART3_RX_DMA_REQUEST, \
|
||||||
.dma_rcc = UART3_RX_DMA_RCC, \
|
.dma_rcc = UART3_RX_DMA_RCC, \
|
||||||
.dma_irq = UART3_RX_DMA_IRQ, \
|
.dma_irq = UART3_RX_DMA_IRQ, \
|
||||||
}
|
}
|
||||||
#endif /* UART3_DMA_CONFIG */
|
#endif /* UART3_DMA_RX_CONFIG */
|
||||||
#endif /* BSP_UART3_RX_USING_DMA */
|
#endif /* BSP_UART3_RX_USING_DMA */
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
|
|
|
@ -25,7 +25,7 @@
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef RT_SERIAL_USING_DMA
|
#ifdef RT_SERIAL_USING_DMA
|
||||||
static void stm32_dma_config(struct rt_serial_device *serial);
|
static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag);
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
enum
|
enum
|
||||||
|
@ -171,10 +171,7 @@ static rt_err_t stm32_control(struct rt_serial_device *serial, int cmd, void *ar
|
||||||
|
|
||||||
#ifdef RT_SERIAL_USING_DMA
|
#ifdef RT_SERIAL_USING_DMA
|
||||||
case RT_DEVICE_CTRL_CONFIG:
|
case RT_DEVICE_CTRL_CONFIG:
|
||||||
if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX)
|
stm32_dma_config(serial, ctrl_arg);
|
||||||
{
|
|
||||||
stm32_dma_config(serial);
|
|
||||||
}
|
|
||||||
break;
|
break;
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
@ -219,12 +216,39 @@ static int stm32_getc(struct rt_serial_device *serial)
|
||||||
return ch;
|
return ch;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static rt_size_t stm32_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction)
|
||||||
|
{
|
||||||
|
struct stm32_uart *uart;
|
||||||
|
RT_ASSERT(serial != RT_NULL);
|
||||||
|
uart = (struct stm32_uart *)(serial->parent.user_data);
|
||||||
|
RT_ASSERT(uart != RT_NULL);
|
||||||
|
|
||||||
|
if (size == 0)
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (RT_SERIAL_DMA_TX == direction)
|
||||||
|
{
|
||||||
|
if (HAL_UART_Transmit_DMA(&uart->handle, buf, size) == HAL_OK)
|
||||||
|
{
|
||||||
|
return size;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
static const struct rt_uart_ops stm32_uart_ops =
|
static const struct rt_uart_ops stm32_uart_ops =
|
||||||
{
|
{
|
||||||
.configure = stm32_configure,
|
.configure = stm32_configure,
|
||||||
.control = stm32_control,
|
.control = stm32_control,
|
||||||
.putc = stm32_putc,
|
.putc = stm32_putc,
|
||||||
.getc = stm32_getc,
|
.getc = stm32_getc,
|
||||||
|
.dma_transmit = stm32_dma_transmit
|
||||||
};
|
};
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -252,13 +276,13 @@ static void uart_isr(struct rt_serial_device *serial)
|
||||||
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
|
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
|
||||||
}
|
}
|
||||||
#ifdef RT_SERIAL_USING_DMA
|
#ifdef RT_SERIAL_USING_DMA
|
||||||
else if ((uart->uart_dma_flag) && (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_IDLE) != RESET) &&
|
else if ((uart->uart_dma_flag) && (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_IDLE) != RESET)
|
||||||
(__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_IDLE) != RESET))
|
&& (__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_IDLE) != RESET))
|
||||||
{
|
{
|
||||||
level = rt_hw_interrupt_disable();
|
level = rt_hw_interrupt_disable();
|
||||||
recv_total_index = serial->config.bufsz - __HAL_DMA_GET_COUNTER(&(uart->dma.handle));
|
recv_total_index = serial->config.bufsz - __HAL_DMA_GET_COUNTER(&(uart->dma_rx.handle));
|
||||||
recv_len = recv_total_index - uart->dma.last_index;
|
recv_len = recv_total_index - uart->dma_rx.last_index;
|
||||||
uart->dma.last_index = recv_total_index;
|
uart->dma_rx.last_index = recv_total_index;
|
||||||
rt_hw_interrupt_enable(level);
|
rt_hw_interrupt_enable(level);
|
||||||
|
|
||||||
if (recv_len)
|
if (recv_len)
|
||||||
|
@ -267,6 +291,17 @@ static void uart_isr(struct rt_serial_device *serial)
|
||||||
}
|
}
|
||||||
__HAL_UART_CLEAR_IDLEFLAG(&uart->handle);
|
__HAL_UART_CLEAR_IDLEFLAG(&uart->handle);
|
||||||
}
|
}
|
||||||
|
else if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TC) != RESET)
|
||||||
|
{
|
||||||
|
if ((serial->parent.open_flag & RT_DEVICE_FLAG_DMA_TX) != 0)
|
||||||
|
{
|
||||||
|
HAL_UART_IRQHandler(&(uart->handle));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC);
|
||||||
|
}
|
||||||
|
}
|
||||||
#endif
|
#endif
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
|
@ -324,20 +359,20 @@ static void dma_isr(struct rt_serial_device *serial)
|
||||||
uart = (struct stm32_uart *) serial->parent.user_data;
|
uart = (struct stm32_uart *) serial->parent.user_data;
|
||||||
RT_ASSERT(uart != RT_NULL);
|
RT_ASSERT(uart != RT_NULL);
|
||||||
|
|
||||||
if ((__HAL_DMA_GET_IT_SOURCE(&(uart->dma.handle), DMA_IT_TC) != RESET) ||
|
if ((__HAL_DMA_GET_IT_SOURCE(&(uart->dma_rx.handle), DMA_IT_TC) != RESET) ||
|
||||||
(__HAL_DMA_GET_IT_SOURCE(&(uart->dma.handle), DMA_IT_HT) != RESET))
|
(__HAL_DMA_GET_IT_SOURCE(&(uart->dma_rx.handle), DMA_IT_HT) != RESET))
|
||||||
{
|
{
|
||||||
level = rt_hw_interrupt_disable();
|
level = rt_hw_interrupt_disable();
|
||||||
recv_total_index = serial->config.bufsz - __HAL_DMA_GET_COUNTER(&(uart->dma.handle));
|
recv_total_index = serial->config.bufsz - __HAL_DMA_GET_COUNTER(&(uart->dma_rx.handle));
|
||||||
if (recv_total_index == 0)
|
if (recv_total_index == 0)
|
||||||
{
|
{
|
||||||
recv_len = serial->config.bufsz - uart->dma.last_index;
|
recv_len = serial->config.bufsz - uart->dma_rx.last_index;
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
recv_len = recv_total_index - uart->dma.last_index;
|
recv_len = recv_total_index - uart->dma_rx.last_index;
|
||||||
}
|
}
|
||||||
uart->dma.last_index = recv_total_index;
|
uart->dma_rx.last_index = recv_total_index;
|
||||||
rt_hw_interrupt_enable(level);
|
rt_hw_interrupt_enable(level);
|
||||||
|
|
||||||
if (recv_len)
|
if (recv_len)
|
||||||
|
@ -365,12 +400,24 @@ void UART1_DMA_RX_IRQHandler(void)
|
||||||
/* enter interrupt */
|
/* enter interrupt */
|
||||||
rt_interrupt_enter();
|
rt_interrupt_enter();
|
||||||
|
|
||||||
HAL_DMA_IRQHandler(&uart_obj[UART1_INDEX].dma.handle);
|
HAL_DMA_IRQHandler(&uart_obj[UART1_INDEX].dma_rx.handle);
|
||||||
|
|
||||||
/* leave interrupt */
|
/* leave interrupt */
|
||||||
rt_interrupt_leave();
|
rt_interrupt_leave();
|
||||||
}
|
}
|
||||||
#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA) */
|
#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA) */
|
||||||
|
#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA)
|
||||||
|
void UART1_DMA_TX_IRQHandler(void)
|
||||||
|
{
|
||||||
|
/* enter interrupt */
|
||||||
|
rt_interrupt_enter();
|
||||||
|
|
||||||
|
HAL_DMA_IRQHandler(&uart_obj[UART1_INDEX].dma_tx.handle);
|
||||||
|
|
||||||
|
/* leave interrupt */
|
||||||
|
rt_interrupt_leave();
|
||||||
|
}
|
||||||
|
#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA) */
|
||||||
#endif /* BSP_USING_UART1 */
|
#endif /* BSP_USING_UART1 */
|
||||||
|
|
||||||
#if defined(BSP_USING_UART2)
|
#if defined(BSP_USING_UART2)
|
||||||
|
@ -390,12 +437,24 @@ void UART2_DMA_RX_IRQHandler(void)
|
||||||
/* enter interrupt */
|
/* enter interrupt */
|
||||||
rt_interrupt_enter();
|
rt_interrupt_enter();
|
||||||
|
|
||||||
HAL_DMA_IRQHandler(&uart_obj[UART2_INDEX].dma.handle);
|
HAL_DMA_IRQHandler(&uart_obj[UART2_INDEX].dma_rx.handle);
|
||||||
|
|
||||||
/* leave interrupt */
|
/* leave interrupt */
|
||||||
rt_interrupt_leave();
|
rt_interrupt_leave();
|
||||||
}
|
}
|
||||||
#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA) */
|
#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA) */
|
||||||
|
#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA)
|
||||||
|
void UART2_DMA_TX_IRQHandler(void)
|
||||||
|
{
|
||||||
|
/* enter interrupt */
|
||||||
|
rt_interrupt_enter();
|
||||||
|
|
||||||
|
HAL_DMA_IRQHandler(&uart_obj[UART2_INDEX].dma_tx.handle);
|
||||||
|
|
||||||
|
/* leave interrupt */
|
||||||
|
rt_interrupt_leave();
|
||||||
|
}
|
||||||
|
#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA) */
|
||||||
#endif /* BSP_USING_UART2 */
|
#endif /* BSP_USING_UART2 */
|
||||||
|
|
||||||
#if defined(BSP_USING_UART3)
|
#if defined(BSP_USING_UART3)
|
||||||
|
@ -415,12 +474,24 @@ void UART3_DMA_RX_IRQHandler(void)
|
||||||
/* enter interrupt */
|
/* enter interrupt */
|
||||||
rt_interrupt_enter();
|
rt_interrupt_enter();
|
||||||
|
|
||||||
HAL_DMA_IRQHandler(&uart_obj[UART3_INDEX].dma.handle);
|
HAL_DMA_IRQHandler(&uart_obj[UART3_INDEX].dma_rx.handle);
|
||||||
|
|
||||||
/* leave interrupt */
|
/* leave interrupt */
|
||||||
rt_interrupt_leave();
|
rt_interrupt_leave();
|
||||||
}
|
}
|
||||||
#endif /* defined(BSP_UART_USING_DMA_RX) && defined(BSP_UART3_RX_USING_DMA) */
|
#endif /* defined(BSP_UART_USING_DMA_RX) && defined(BSP_UART3_RX_USING_DMA) */
|
||||||
|
#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_TX_USING_DMA)
|
||||||
|
void UART3_DMA_TX_IRQHandler(void)
|
||||||
|
{
|
||||||
|
/* enter interrupt */
|
||||||
|
rt_interrupt_enter();
|
||||||
|
|
||||||
|
HAL_DMA_IRQHandler(&uart_obj[UART3_INDEX].dma_tx.handle);
|
||||||
|
|
||||||
|
/* leave interrupt */
|
||||||
|
rt_interrupt_leave();
|
||||||
|
}
|
||||||
|
#endif /* defined(BSP_UART_USING_DMA_TX) && defined(BSP_UART3_TX_USING_DMA) */
|
||||||
#endif /* BSP_USING_UART3*/
|
#endif /* BSP_USING_UART3*/
|
||||||
|
|
||||||
#if defined(BSP_USING_UART4)
|
#if defined(BSP_USING_UART4)
|
||||||
|
@ -440,12 +511,25 @@ void UART4_DMA_RX_IRQHandler(void)
|
||||||
/* enter interrupt */
|
/* enter interrupt */
|
||||||
rt_interrupt_enter();
|
rt_interrupt_enter();
|
||||||
|
|
||||||
HAL_DMA_IRQHandler(&uart_obj[UART4_INDEX].dma.handle);
|
HAL_DMA_IRQHandler(&uart_obj[UART4_INDEX].dma_rx.handle);
|
||||||
|
|
||||||
/* leave interrupt */
|
/* leave interrupt */
|
||||||
rt_interrupt_leave();
|
rt_interrupt_leave();
|
||||||
}
|
}
|
||||||
#endif /* defined(BSP_UART_USING_DMA_RX) && defined(BSP_UART4_RX_USING_DMA) */
|
#endif /* defined(BSP_UART_USING_DMA_RX) && defined(BSP_UART4_RX_USING_DMA) */
|
||||||
|
|
||||||
|
#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART4_TX_USING_DMA)
|
||||||
|
void UART4_DMA_TX_IRQHandler(void)
|
||||||
|
{
|
||||||
|
/* enter interrupt */
|
||||||
|
rt_interrupt_enter();
|
||||||
|
|
||||||
|
HAL_DMA_IRQHandler(&uart_obj[UART4_INDEX].dma_tx.handle);
|
||||||
|
|
||||||
|
/* leave interrupt */
|
||||||
|
rt_interrupt_leave();
|
||||||
|
}
|
||||||
|
#endif /* defined(BSP_UART_USING_DMA_TX) && defined(BSP_UART4_TX_USING_DMA) */
|
||||||
#endif /* BSP_USING_UART4*/
|
#endif /* BSP_USING_UART4*/
|
||||||
|
|
||||||
#if defined(BSP_USING_UART5)
|
#if defined(BSP_USING_UART5)
|
||||||
|
@ -465,12 +549,24 @@ void UART5_DMA_RX_IRQHandler(void)
|
||||||
/* enter interrupt */
|
/* enter interrupt */
|
||||||
rt_interrupt_enter();
|
rt_interrupt_enter();
|
||||||
|
|
||||||
HAL_DMA_IRQHandler(&uart_obj[UART5_INDEX].dma.handle);
|
HAL_DMA_IRQHandler(&uart_obj[UART5_INDEX].dma_rx.handle);
|
||||||
|
|
||||||
/* leave interrupt */
|
/* leave interrupt */
|
||||||
rt_interrupt_leave();
|
rt_interrupt_leave();
|
||||||
}
|
}
|
||||||
#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_RX_USING_DMA) */
|
#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_RX_USING_DMA) */
|
||||||
|
#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_TX_USING_DMA)
|
||||||
|
void UART5_DMA_TX_IRQHandler(void)
|
||||||
|
{
|
||||||
|
/* enter interrupt */
|
||||||
|
rt_interrupt_enter();
|
||||||
|
|
||||||
|
HAL_DMA_IRQHandler(&uart_obj[UART5_INDEX].dma_tx.handle);
|
||||||
|
|
||||||
|
/* leave interrupt */
|
||||||
|
rt_interrupt_leave();
|
||||||
|
}
|
||||||
|
#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_TX_USING_DMA) */
|
||||||
#endif /* BSP_USING_UART5*/
|
#endif /* BSP_USING_UART5*/
|
||||||
|
|
||||||
#if defined(BSP_USING_UART6)
|
#if defined(BSP_USING_UART6)
|
||||||
|
@ -490,12 +586,24 @@ void UART6_DMA_RX_IRQHandler(void)
|
||||||
/* enter interrupt */
|
/* enter interrupt */
|
||||||
rt_interrupt_enter();
|
rt_interrupt_enter();
|
||||||
|
|
||||||
HAL_DMA_IRQHandler(&uart_obj[UART6_INDEX].dma.handle);
|
HAL_DMA_IRQHandler(&uart_obj[UART6_INDEX].dma_rx.handle);
|
||||||
|
|
||||||
/* leave interrupt */
|
/* leave interrupt */
|
||||||
rt_interrupt_leave();
|
rt_interrupt_leave();
|
||||||
}
|
}
|
||||||
#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_RX_USING_DMA) */
|
#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_RX_USING_DMA) */
|
||||||
|
#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_TX_USING_DMA)
|
||||||
|
void UART6_DMA_TX_IRQHandler(void)
|
||||||
|
{
|
||||||
|
/* enter interrupt */
|
||||||
|
rt_interrupt_enter();
|
||||||
|
|
||||||
|
HAL_DMA_IRQHandler(&uart_obj[UART6_INDEX].dma_tx.handle);
|
||||||
|
|
||||||
|
/* leave interrupt */
|
||||||
|
rt_interrupt_leave();
|
||||||
|
}
|
||||||
|
#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_TX_USING_DMA) */
|
||||||
#endif /* BSP_USING_UART6*/
|
#endif /* BSP_USING_UART6*/
|
||||||
|
|
||||||
#if defined(BSP_USING_LPUART1)
|
#if defined(BSP_USING_LPUART1)
|
||||||
|
@ -515,7 +623,7 @@ void LPUART1_DMA_RX_IRQHandler(void)
|
||||||
/* enter interrupt */
|
/* enter interrupt */
|
||||||
rt_interrupt_enter();
|
rt_interrupt_enter();
|
||||||
|
|
||||||
HAL_DMA_IRQHandler(&uart_obj[LPUART1_INDEX].dma.handle);
|
HAL_DMA_IRQHandler(&uart_obj[LPUART1_INDEX].dma_rx.handle);
|
||||||
|
|
||||||
/* leave interrupt */
|
/* leave interrupt */
|
||||||
rt_interrupt_leave();
|
rt_interrupt_leave();
|
||||||
|
@ -524,13 +632,27 @@ void LPUART1_DMA_RX_IRQHandler(void)
|
||||||
#endif /* BSP_USING_LPUART1*/
|
#endif /* BSP_USING_LPUART1*/
|
||||||
|
|
||||||
#ifdef RT_SERIAL_USING_DMA
|
#ifdef RT_SERIAL_USING_DMA
|
||||||
static void stm32_dma_config(struct rt_serial_device *serial)
|
static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
|
||||||
{
|
{
|
||||||
RT_ASSERT(serial != RT_NULL);
|
|
||||||
struct stm32_uart *uart = (struct stm32_uart *)serial->parent.user_data;
|
|
||||||
RT_ASSERT(uart != RT_NULL);
|
|
||||||
struct rt_serial_rx_fifo *rx_fifo;
|
struct rt_serial_rx_fifo *rx_fifo;
|
||||||
|
DMA_HandleTypeDef *DMA_Handle;
|
||||||
|
struct dma_config *dma_config;
|
||||||
|
struct stm32_uart *uart;
|
||||||
|
|
||||||
|
RT_ASSERT(serial != RT_NULL);
|
||||||
|
uart = (struct stm32_uart *)serial->parent.user_data;
|
||||||
|
RT_ASSERT(uart != RT_NULL);
|
||||||
|
|
||||||
|
if (RT_DEVICE_FLAG_DMA_RX == flag)
|
||||||
|
{
|
||||||
|
DMA_Handle = &uart->dma_rx.handle;
|
||||||
|
dma_config = uart->config->dma_rx;
|
||||||
|
}
|
||||||
|
else if (RT_DEVICE_FLAG_DMA_TX == flag)
|
||||||
|
{
|
||||||
|
DMA_Handle = &uart->dma_tx.handle;
|
||||||
|
dma_config = uart->config->dma_tx;
|
||||||
|
}
|
||||||
LOG_D("%s dma config start", uart->config->name);
|
LOG_D("%s dma config start", uart->config->name);
|
||||||
|
|
||||||
{
|
{
|
||||||
|
@ -538,67 +660,86 @@ static void stm32_dma_config(struct rt_serial_device *serial)
|
||||||
#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0) \
|
#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0) \
|
||||||
|| defined(SOC_SERIES_STM32L0)
|
|| defined(SOC_SERIES_STM32L0)
|
||||||
/* enable DMA clock && Delay after an RCC peripheral clock enabling*/
|
/* enable DMA clock && Delay after an RCC peripheral clock enabling*/
|
||||||
SET_BIT(RCC->AHBENR, uart->config->dma_rx->dma_rcc);
|
SET_BIT(RCC->AHBENR, dma_config->dma_rcc);
|
||||||
tmpreg = READ_BIT(RCC->AHBENR, uart->config->dma_rx->dma_rcc);
|
tmpreg = READ_BIT(RCC->AHBENR, dma_config->dma_rcc);
|
||||||
#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4)
|
#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4)
|
||||||
/* enable DMA clock && Delay after an RCC peripheral clock enabling*/
|
/* enable DMA clock && Delay after an RCC peripheral clock enabling*/
|
||||||
SET_BIT(RCC->AHB1ENR, uart->config->dma_rx->dma_rcc);
|
SET_BIT(RCC->AHB1ENR, dma_config->dma_rcc);
|
||||||
tmpreg = READ_BIT(RCC->AHB1ENR, uart->config->dma_rx->dma_rcc);
|
tmpreg = READ_BIT(RCC->AHB1ENR, dma_config->dma_rcc);
|
||||||
#endif
|
#endif
|
||||||
UNUSED(tmpreg); /* To avoid compiler warnings */
|
UNUSED(tmpreg); /* To avoid compiler warnings */
|
||||||
}
|
}
|
||||||
|
|
||||||
__HAL_LINKDMA(&(uart->handle), hdmarx, uart->dma.handle);
|
if (RT_DEVICE_FLAG_DMA_RX == flag)
|
||||||
|
{
|
||||||
|
__HAL_LINKDMA(&(uart->handle), hdmarx, uart->dma_rx.handle);
|
||||||
|
}
|
||||||
|
else if (RT_DEVICE_FLAG_DMA_TX == flag)
|
||||||
|
{
|
||||||
|
__HAL_LINKDMA(&(uart->handle), hdmatx, uart->dma_tx.handle);
|
||||||
|
}
|
||||||
|
|
||||||
#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32L0)
|
#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32L0)
|
||||||
uart->dma.handle.Instance = uart->config->dma_rx->Instance;
|
DMA_Handle->Instance = dma_config->Instance;
|
||||||
#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
|
#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
|
||||||
uart->dma.handle.Instance = uart->config->dma_rx->Instance;
|
DMA_Handle->Instance = dma_config->Instance;
|
||||||
uart->dma.handle.Init.Channel = uart->config->dma_rx->channel;
|
DMA_Handle->Init.Channel = dma_config->channel;
|
||||||
#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0)
|
#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0)
|
||||||
uart->dma.handle.Instance = uart->config->dma_rx->Instance;
|
DMA_Handle->Instance = dma_config->Instance;
|
||||||
uart->dma.handle.Init.Request = uart->config->dma_rx->request;
|
DMA_Handle->Init.Request = dma_config->request;
|
||||||
#endif
|
#endif
|
||||||
uart->dma.handle.Init.Direction = DMA_PERIPH_TO_MEMORY;
|
DMA_Handle->Init.PeriphInc = DMA_PINC_DISABLE;
|
||||||
uart->dma.handle.Init.PeriphInc = DMA_PINC_DISABLE;
|
DMA_Handle->Init.MemInc = DMA_MINC_ENABLE;
|
||||||
uart->dma.handle.Init.MemInc = DMA_MINC_ENABLE;
|
DMA_Handle->Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
|
||||||
uart->dma.handle.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
|
DMA_Handle->Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
|
||||||
uart->dma.handle.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
|
|
||||||
uart->dma.handle.Init.Mode = DMA_CIRCULAR;
|
if (RT_DEVICE_FLAG_DMA_RX == flag)
|
||||||
uart->dma.handle.Init.Priority = DMA_PRIORITY_MEDIUM;
|
{
|
||||||
|
DMA_Handle->Init.Direction = DMA_PERIPH_TO_MEMORY;
|
||||||
|
DMA_Handle->Init.Mode = DMA_CIRCULAR;
|
||||||
|
}
|
||||||
|
else if (RT_DEVICE_FLAG_DMA_TX == flag)
|
||||||
|
{
|
||||||
|
DMA_Handle->Init.Direction = DMA_MEMORY_TO_PERIPH;
|
||||||
|
DMA_Handle->Init.Mode = DMA_NORMAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
DMA_Handle->Init.Priority = DMA_PRIORITY_MEDIUM;
|
||||||
#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
|
#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
|
||||||
uart->dma.handle.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
|
DMA_Handle->Init.FIFOMode = DMA_FIFOMODE_DISABLE;
|
||||||
#endif
|
#endif
|
||||||
if (HAL_DMA_DeInit(&(uart->dma.handle)) != HAL_OK)
|
if (HAL_DMA_DeInit(DMA_Handle) != HAL_OK)
|
||||||
{
|
{
|
||||||
RT_ASSERT(0);
|
RT_ASSERT(0);
|
||||||
}
|
}
|
||||||
|
|
||||||
if (HAL_DMA_Init(&(uart->dma.handle)) != HAL_OK)
|
if (HAL_DMA_Init(DMA_Handle) != HAL_OK)
|
||||||
{
|
{
|
||||||
RT_ASSERT(0);
|
RT_ASSERT(0);
|
||||||
}
|
}
|
||||||
|
|
||||||
rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
|
|
||||||
|
|
||||||
/* Start DMA transfer */
|
|
||||||
if (HAL_UART_Receive_DMA(&(uart->handle), rx_fifo->buffer, serial->config.bufsz) != HAL_OK)
|
|
||||||
{
|
|
||||||
/* Transfer error in reception process */
|
|
||||||
RT_ASSERT(0);
|
|
||||||
}
|
|
||||||
|
|
||||||
/* enable interrupt */
|
/* enable interrupt */
|
||||||
__HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_IDLE);
|
if (flag == RT_DEVICE_FLAG_DMA_RX)
|
||||||
|
{
|
||||||
|
rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
|
||||||
|
/* Start DMA transfer */
|
||||||
|
if (HAL_UART_Receive_DMA(&(uart->handle), rx_fifo->buffer, serial->config.bufsz) != HAL_OK)
|
||||||
|
{
|
||||||
|
/* Transfer error in reception process */
|
||||||
|
RT_ASSERT(0);
|
||||||
|
}
|
||||||
|
CLEAR_BIT(uart->handle.Instance->CR3, USART_CR3_EIE);
|
||||||
|
__HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_IDLE);
|
||||||
|
}
|
||||||
|
|
||||||
/* enable rx irq */
|
/* enable irq */
|
||||||
HAL_NVIC_SetPriority(uart->config->dma_rx->dma_irq, 0, 0);
|
HAL_NVIC_SetPriority(dma_config->dma_irq, 0, 0);
|
||||||
HAL_NVIC_EnableIRQ(uart->config->dma_rx->dma_irq);
|
HAL_NVIC_EnableIRQ(dma_config->dma_irq);
|
||||||
|
|
||||||
HAL_NVIC_SetPriority(uart->config->irq_type, 1, 0);
|
HAL_NVIC_SetPriority(uart->config->irq_type, 1, 0);
|
||||||
HAL_NVIC_EnableIRQ(uart->config->irq_type);
|
HAL_NVIC_EnableIRQ(uart->config->irq_type);
|
||||||
|
|
||||||
LOG_D("%s dma RX instance: %x", uart->config->name, uart->dma.handle.Instance);
|
LOG_D("%s dma %s instance: %x", uart->config->name, flag == RT_DEVICE_FLAG_DMA_RX ? "RX" : "TX", DMA_Handle->Instance);
|
||||||
LOG_D("%s dma config done", uart->config->name);
|
LOG_D("%s dma config done", uart->config->name);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -646,44 +787,99 @@ void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
|
||||||
uart = (struct stm32_uart *)huart;
|
uart = (struct stm32_uart *)huart;
|
||||||
dma_isr(&uart->serial);
|
dma_isr(&uart->serial);
|
||||||
}
|
}
|
||||||
|
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
|
||||||
|
{
|
||||||
|
struct stm32_uart *uart;
|
||||||
|
RT_ASSERT(huart != NULL);
|
||||||
|
uart = (struct stm32_uart *)huart;
|
||||||
|
rt_hw_serial_isr(&uart->serial, RT_SERIAL_EVENT_TX_DMADONE);
|
||||||
|
}
|
||||||
#endif /* RT_SERIAL_USING_DMA */
|
#endif /* RT_SERIAL_USING_DMA */
|
||||||
|
|
||||||
static void stm32_uart_get_dma_config(void)
|
static void stm32_uart_get_dma_config(void)
|
||||||
{
|
{
|
||||||
|
#ifdef BSP_USING_UART1
|
||||||
|
uart_obj[UART1_INDEX].uart_dma_flag = 0;
|
||||||
#ifdef BSP_UART1_RX_USING_DMA
|
#ifdef BSP_UART1_RX_USING_DMA
|
||||||
uart_obj[UART1_INDEX].uart_dma_flag = 1;
|
uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
|
||||||
static struct dma_config uart1_dma_rx = UART1_DMA_CONFIG;
|
static struct dma_config uart1_dma_rx = UART1_DMA_RX_CONFIG;
|
||||||
uart_config[UART1_INDEX].dma_rx = &uart1_dma_rx;
|
uart_config[UART1_INDEX].dma_rx = &uart1_dma_rx;
|
||||||
#endif
|
#endif
|
||||||
|
#ifdef BSP_UART1_TX_USING_DMA
|
||||||
|
uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
|
||||||
|
static struct dma_config uart1_dma_tx = UART1_DMA_TX_CONFIG;
|
||||||
|
uart_config[UART1_INDEX].dma_tx = &uart1_dma_tx;
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef BSP_USING_UART2
|
||||||
|
uart_obj[UART2_INDEX].uart_dma_flag = 0;
|
||||||
#ifdef BSP_UART2_RX_USING_DMA
|
#ifdef BSP_UART2_RX_USING_DMA
|
||||||
uart_obj[UART2_INDEX].uart_dma_flag = 1;
|
uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
|
||||||
static struct dma_config uart2_dma_rx = UART2_DMA_CONFIG;
|
static struct dma_config uart2_dma_rx = UART2_DMA_RX_CONFIG;
|
||||||
uart_config[UART2_INDEX].dma_rx = &uart2_dma_rx;
|
uart_config[UART2_INDEX].dma_rx = &uart2_dma_rx;
|
||||||
#endif
|
#endif
|
||||||
|
#ifdef BSP_UART2_TX_USING_DMA
|
||||||
|
uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
|
||||||
|
static struct dma_config uart2_dma_tx = UART2_DMA_TX_CONFIG;
|
||||||
|
uart_config[UART2_INDEX].dma_tx = &uart2_dma_tx;
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef BSP_USING_UART3
|
||||||
|
uart_obj[UART3_INDEX].uart_dma_flag = 0;
|
||||||
#ifdef BSP_UART3_RX_USING_DMA
|
#ifdef BSP_UART3_RX_USING_DMA
|
||||||
uart_obj[UART3_INDEX].uart_dma_flag = 1;
|
uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
|
||||||
static struct dma_config uart3_dma_rx = UART3_DMA_CONFIG;
|
static struct dma_config uart3_dma_rx = UART3_DMA_RX_CONFIG;
|
||||||
uart_config[UART3_INDEX].dma_rx = &uart3_dma_rx;
|
uart_config[UART3_INDEX].dma_rx = &uart3_dma_rx;
|
||||||
#endif
|
#endif
|
||||||
|
#ifdef BSP_UART3_TX_USING_DMA
|
||||||
|
uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
|
||||||
|
static struct dma_config uart3_dma_tx = UART3_DMA_TX_CONFIG;
|
||||||
|
uart_config[UART3_INDEX].dma_tx = &uart3_dma_tx;
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef BSP_USING_UART4
|
||||||
|
uart_obj[UART4_INDEX].uart_dma_flag = 0;
|
||||||
#ifdef BSP_UART4_RX_USING_DMA
|
#ifdef BSP_UART4_RX_USING_DMA
|
||||||
uart_obj[UART4_INDEX].uart_dma_flag = 1;
|
uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
|
||||||
static struct dma_config uart4_dma_rx = UART4_DMA_CONFIG;
|
static struct dma_config uart4_dma_rx = UART4_DMA_RX_CONFIG;
|
||||||
uart_config[UART4_INDEX].dma_rx = &uart4_dma_rx;
|
uart_config[UART4_INDEX].dma_rx = &uart4_dma_rx;
|
||||||
#endif
|
#endif
|
||||||
|
#ifdef BSP_UART4_TX_USING_DMA
|
||||||
|
uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
|
||||||
|
static struct dma_config uart4_dma_tx = UART4_DMA_TX_CONFIG;
|
||||||
|
uart_config[UART4_INDEX].dma_tx = &uart4_dma_tx;
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef BSP_USING_UART5
|
||||||
|
uart_obj[UART5_INDEX].uart_dma_flag = 0;
|
||||||
#ifdef BSP_UART5_RX_USING_DMA
|
#ifdef BSP_UART5_RX_USING_DMA
|
||||||
uart_obj[UART5_INDEX].uart_dma_flag = 1;
|
uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
|
||||||
static struct dma_config uart5_dma_rx = UART5_DMA_CONFIG;
|
static struct dma_config uart5_dma_rx = UART5_DMA_RX_CONFIG;
|
||||||
uart_config[UART5_INDEX].dma_rx = &uart5_dma_rx;
|
uart_config[UART5_INDEX].dma_rx = &uart5_dma_rx;
|
||||||
#endif
|
#endif
|
||||||
|
#ifdef BSP_UART5_TX_USING_DMA
|
||||||
|
uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
|
||||||
|
static struct dma_config uart5_dma_tx = UART5_DMA_TX_CONFIG;
|
||||||
|
uart_config[UART5_INDEX].dma_tx = &uart5_dma_tx;
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef BSP_USING_UART6
|
||||||
|
uart_obj[UART6_INDEX].uart_dma_flag = 0;
|
||||||
#ifdef BSP_UART6_RX_USING_DMA
|
#ifdef BSP_UART6_RX_USING_DMA
|
||||||
uart_obj[UART6_INDEX].uart_dma_flag = 1;
|
uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
|
||||||
static struct dma_config uart6_dma_rx = UART6_DMA_CONFIG;
|
static struct dma_config uart6_dma_rx = UART6_DMA_RX_CONFIG;
|
||||||
uart_config[UART6_INDEX].dma_rx = &uart6_dma_rx;
|
uart_config[UART6_INDEX].dma_rx = &uart6_dma_rx;
|
||||||
#endif
|
#endif
|
||||||
#ifdef BSP_LPUART1_RX_USING_DMA
|
#ifdef BSP_UART6_TX_USING_DMA
|
||||||
uart_obj[LPUART1_INDEX].uart_dma_flag = 1;
|
uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
|
||||||
static struct dma_config lpuart1_dma_rx = LPUART1_DMA_CONFIG;
|
static struct dma_config uart6_dma_tx = UART6_DMA_TX_CONFIG;
|
||||||
uart_config[LPUART1_INDEX].dma_rx = &lpuart1_dma_rx;
|
uart_config[UART6_INDEX].dma_tx = &uart6_dma_tx;
|
||||||
|
#endif
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -700,23 +896,13 @@ int rt_hw_usart_init(void)
|
||||||
uart_obj[i].config = &uart_config[i];
|
uart_obj[i].config = &uart_config[i];
|
||||||
uart_obj[i].serial.ops = &stm32_uart_ops;
|
uart_obj[i].serial.ops = &stm32_uart_ops;
|
||||||
uart_obj[i].serial.config = config;
|
uart_obj[i].serial.config = config;
|
||||||
|
/* register UART device */
|
||||||
#if defined(RT_SERIAL_USING_DMA)
|
result = rt_hw_serial_register(&uart_obj[i].serial, uart_obj[i].config->name,
|
||||||
if (uart_obj[i].uart_dma_flag)
|
RT_DEVICE_FLAG_RDWR
|
||||||
{
|
| RT_DEVICE_FLAG_INT_RX
|
||||||
/* register UART device */
|
| RT_DEVICE_FLAG_INT_TX
|
||||||
result = rt_hw_serial_register(&uart_obj[i].serial, uart_obj[i].config->name,
|
| uart_obj[i].uart_dma_flag
|
||||||
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_DMA_RX
|
, &uart_obj[i]);
|
||||||
, &uart_obj[i]);
|
|
||||||
}
|
|
||||||
else
|
|
||||||
#endif
|
|
||||||
{
|
|
||||||
/* register UART device */
|
|
||||||
result = rt_hw_serial_register(&uart_obj[i].serial, uart_obj[i].config->name,
|
|
||||||
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX
|
|
||||||
, &uart_obj[i]);
|
|
||||||
}
|
|
||||||
RT_ASSERT(result == RT_EOK);
|
RT_ASSERT(result == RT_EOK);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -41,6 +41,7 @@ struct stm32_uart_config
|
||||||
USART_TypeDef *Instance;
|
USART_TypeDef *Instance;
|
||||||
IRQn_Type irq_type;
|
IRQn_Type irq_type;
|
||||||
struct dma_config *dma_rx;
|
struct dma_config *dma_rx;
|
||||||
|
struct dma_config *dma_tx;
|
||||||
};
|
};
|
||||||
|
|
||||||
/* stm32 uart dirver class */
|
/* stm32 uart dirver class */
|
||||||
|
@ -54,9 +55,13 @@ struct stm32_uart
|
||||||
{
|
{
|
||||||
DMA_HandleTypeDef handle;
|
DMA_HandleTypeDef handle;
|
||||||
rt_size_t last_index;
|
rt_size_t last_index;
|
||||||
} dma;
|
} dma_rx;
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
DMA_HandleTypeDef handle;
|
||||||
|
} dma_tx;
|
||||||
#endif
|
#endif
|
||||||
rt_uint8_t uart_dma_flag;
|
rt_uint16_t uart_dma_flag;
|
||||||
struct rt_serial_device serial;
|
struct rt_serial_device serial;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
@ -40,8 +40,8 @@ if GetDepend(['RT_USING_I2C']):
|
||||||
src += ['STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c']
|
src += ['STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c']
|
||||||
|
|
||||||
if GetDepend(['RT_USING_SPI']):
|
if GetDepend(['RT_USING_SPI']):
|
||||||
src += ['STM32F7xx_HAL_Driver/Src/stm32h7xx_hal_spi.c']
|
src += ['STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi.c']
|
||||||
src += ['STM32F7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c']
|
src += ['STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c']
|
||||||
|
|
||||||
if GetDepend(['RT_USING_USB_HOST']) or GetDepend(['RT_USING_USB_DEVICE']):
|
if GetDepend(['RT_USING_USB_HOST']) or GetDepend(['RT_USING_USB_DEVICE']):
|
||||||
src += ['STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pccard.c']
|
src += ['STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pccard.c']
|
||||||
|
|
|
@ -1,8 +1,8 @@
|
||||||
# BSP README 模板
|
# STM32F103 yf-ufun 开发板 BSP 说明
|
||||||
|
|
||||||
## 简介
|
## 简介
|
||||||
|
|
||||||
本文档为 ufun 开发板的 BSP (板级支持包) 说明。
|
本文档为刘恒为 STM32F103 yf-ufun 开发板提供的 BSP (板级支持包) 说明。
|
||||||
|
|
||||||
主要内容如下:
|
主要内容如下:
|
||||||
|
|
||||||
|
@ -14,11 +14,7 @@
|
||||||
|
|
||||||
## 开发板介绍
|
## 开发板介绍
|
||||||
|
|
||||||
板载资源比较丰富。
|
yf-ufun STM32F103 是优凡(天津)科技有限公司推出的一款基于 ARM Cortex-M3 内核的开发板,最高主频为 72Mhz,该开发板具有丰富的板载资源,可以充分发挥 STM32F103 的芯片性能。正面有 Micro SD 卡槽,usb 接口(供电、ISP 下载、USB 转串口),LED,触摸按键控制芯片 TTP224N-BSB,CH340 USB 转串口芯片。背面有电源开关,BOOT 配置拨码开关,蜂鸣器,RGB LED,RTC 超级电容,复位按键,触摸按键,SWD 调试接口。通过 miniPCIe 连接扩展板。
|
||||||
正面有Micro SD 卡槽,usb接口(供电、ISP下载、USB转串口),LED3,触摸按键控制芯片(TTP224N-BSB),CH340 USB 转串口芯片。
|
|
||||||
背面有电源开关,BOOT配置拨码开关,蜂鸣器,RGB LED,RTC超级电容,复位按键,触摸按键,SWD调试接口。
|
|
||||||
主控MCU STM32F103RCT6,LQFP64封装。
|
|
||||||
扩展板, 通过 miniPCIe 来进行连接。
|
|
||||||
|
|
||||||
开发板外观如下图所示:
|
开发板外观如下图所示:
|
||||||
|
|
||||||
|
@ -27,15 +23,13 @@
|
||||||
该开发板常用 **板载资源** 如下:
|
该开发板常用 **板载资源** 如下:
|
||||||
|
|
||||||
- MCU:STM32F103RCT6,主频 72MHz,256KB FLASH ,48KB RAM
|
- MCU:STM32F103RCT6,主频 72MHz,256KB FLASH ,48KB RAM
|
||||||
- 外部 RAM:无
|
|
||||||
- 外部 FLASH:无
|
|
||||||
- 常用外设
|
- 常用外设
|
||||||
- LED:2个,LED3(红色,PA3),LED1(RGB,PA1,PA2,PA0)
|
- LED:2个,LED3(R,PA3),LED1(RGB,PA1,PA2,PA0)
|
||||||
- 按键:5个,K1(复位),上下左右4个触摸按键
|
- 按键:5个,K1 复位,上下左右4个触摸按键
|
||||||
- 常用接口:USB 转串口、SD 卡接口等
|
- 常用接口:USB 转串口、SD 卡接口,miniPCIe 扩展接口等
|
||||||
- 调试接口,标准 SWD
|
- 调试接口,标准 SWD 调试下载接口
|
||||||
|
|
||||||
开发板更多详细信息请参考【ufun】 [ufun开发板介绍]链接https://forum.mianbaoban.cn/topic/70846_1_1.html。
|
开发板更多详细信息请参考优凡 [ufun 资料] 链接: https://pan.baidu.com/s/12WzPnuGVufoiKUtzhdXNeg 提取码: mp4h
|
||||||
|
|
||||||
## 外设支持
|
## 外设支持
|
||||||
|
|
||||||
|
@ -44,12 +38,12 @@
|
||||||
| **板载外设** | **支持情况** | **备注** |
|
| **板载外设** | **支持情况** | **备注** |
|
||||||
| :----------------- | :----------: | :------------------------------------|
|
| :----------------- | :----------: | :------------------------------------|
|
||||||
| USB 转串口 | 支持 | |
|
| USB 转串口 | 支持 | |
|
||||||
| SPI Flash | 暂不支持 | |
|
| 蜂鸣器 | 暂不支持 | |
|
||||||
| 以太网 | 暂不支持 | |
|
| LED | 支持 | |
|
||||||
| SD卡 | 暂不支持 | |
|
| RGB LED | 暂不支持 | |
|
||||||
| CAN | 暂不支持 | |
|
| 触摸按键 | 暂不支持 | |
|
||||||
| **片上外设** | **支持情况** | **备注** |
|
| **片上外设** | **支持情况** | **备注** |
|
||||||
| GPIO | 支持 | PA0, PA1... PK15 ---> PIN: 0, 1...64 |
|
| GPIO | 支持 | PA0-PA14,PB0-PB15,PC0-PC5,PC7-PC12 |
|
||||||
| UART | 支持 | UART1 |
|
| UART | 支持 | UART1 |
|
||||||
| SPI | 暂不支持 | |
|
| SPI | 暂不支持 | |
|
||||||
| I2C | 暂不支持 | |
|
| I2C | 暂不支持 | |
|
||||||
|
@ -59,8 +53,7 @@
|
||||||
| USB Device | 暂不支持 | |
|
| USB Device | 暂不支持 | |
|
||||||
| USB Host | 暂不支持 | |
|
| USB Host | 暂不支持 | |
|
||||||
| IWG | 暂不支持 | |
|
| IWG | 暂不支持 | |
|
||||||
| **扩展模块** | **支持情况** | **备注** |
|
| **扩展模块** | **支持情况** | **备注** |
|
||||||
| xxx 模块 | 支持 | |
|
|
||||||
|
|
||||||
## 使用说明
|
## 使用说明
|
||||||
|
|
||||||
|
@ -74,7 +67,6 @@
|
||||||
|
|
||||||
本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置,可以开启更多板载资源,实现更多高级功能。
|
本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置,可以开启更多板载资源,实现更多高级功能。
|
||||||
|
|
||||||
|
|
||||||
### 快速上手
|
### 快速上手
|
||||||
|
|
||||||
本 BSP 为开发者提供 MDK4、MDK5 和 IAR 工程,并且支持 GCC 开发环境。下面以 MDK5 开发环境为例,介绍如何将系统运行起来。
|
本 BSP 为开发者提供 MDK4、MDK5 和 IAR 工程,并且支持 GCC 开发环境。下面以 MDK5 开发环境为例,介绍如何将系统运行起来。
|
||||||
|
@ -87,15 +79,14 @@
|
||||||
|
|
||||||
双击 project.uvprojx 文件,打开 MDK5 工程,编译并下载程序到开发板。
|
双击 project.uvprojx 文件,打开 MDK5 工程,编译并下载程序到开发板。
|
||||||
|
|
||||||
> 工程默认配置使用 xxx 仿真器下载程序,在通过 xxx 连接开发板的基础上,点击下载按钮即可下载程序到开发板
|
> 工程默认配置使用 Jlink 仿真器下载程序,在通过 Jlink 连接开发板的基础上,点击下载按钮即可下载程序到开发板
|
||||||
|
|
||||||
#### 运行结果
|
#### 运行结果
|
||||||
|
|
||||||
下载程序成功之后,系统会自动运行,【这里写开发板运行起来之后的现象,如:LED 闪烁等】。
|
下载程序成功之后,系统会自动运行,LED3 闪烁。
|
||||||
|
|
||||||
连接开发板对应串口到 PC , 在终端工具里打开相应的串口(115200-8-1-N),复位设备后,可以看到 RT-Thread 的输出信息:
|
连接开发板对应串口到 PC , 在终端工具里打开相应的串口(115200-8-1-N),复位设备后,可以看到 RT-Thread 的输出信息:
|
||||||
|
|
||||||
|
|
||||||
\ | /
|
\ | /
|
||||||
- RT - Thread Operating System
|
- RT - Thread Operating System
|
||||||
/ | \ 4.0.2 build May 23 2019
|
/ | \ 4.0.2 build May 23 2019
|
||||||
|
@ -104,7 +95,7 @@ msh >
|
||||||
|
|
||||||
### 进阶使用
|
### 进阶使用
|
||||||
|
|
||||||
此 BSP 默认只开启了 GPIO 和 串口1 的功能,如果需使用 SD 卡、Flash 等更多高级功能,需要利用 ENV 工具对BSP 进行配置,步骤如下:
|
此 BSP 默认只开启了 GPIO 和 串口1 的功能,如果需使用 Flash 等更多高级功能,需要利用 ENV 工具对BSP 进行配置,步骤如下:
|
||||||
|
|
||||||
1. 在 bsp 下打开 env 工具。
|
1. 在 bsp 下打开 env 工具。
|
||||||
|
|
||||||
|
@ -118,10 +109,8 @@ msh >
|
||||||
|
|
||||||
## 注意事项
|
## 注意事项
|
||||||
|
|
||||||
- xxx
|
|
||||||
|
|
||||||
## 联系人信息
|
## 联系人信息
|
||||||
|
|
||||||
维护人:
|
维护人:
|
||||||
|
|
||||||
- [rfq](https://github.com/lhxzui), 邮箱:<iuzxhl@qq.com>
|
- [刘恒](https://github.com/lhxzui), 邮箱:<iuzxhl@qq.com>
|
Before Width: | Height: | Size: 163 KiB After Width: | Height: | Size: 163 KiB |
|
@ -83,6 +83,25 @@ menu "On-chip Peripheral Drivers"
|
||||||
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
|
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
|
||||||
default n
|
default n
|
||||||
|
|
||||||
|
config BSP_UART1_TX_USING_DMA
|
||||||
|
bool "Enable UART1 TX DMA"
|
||||||
|
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
|
||||||
|
default n
|
||||||
|
|
||||||
|
config BSP_USING_UART2
|
||||||
|
bool "Enable UART2"
|
||||||
|
default n
|
||||||
|
|
||||||
|
config BSP_UART2_RX_USING_DMA
|
||||||
|
bool "Enable UART2 RX DMA"
|
||||||
|
depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
|
||||||
|
default n
|
||||||
|
|
||||||
|
config BSP_UART2_TX_USING_DMA
|
||||||
|
bool "Enable UART2 TX DMA"
|
||||||
|
depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
|
||||||
|
default n
|
||||||
|
|
||||||
config BSP_USING_UART3
|
config BSP_USING_UART3
|
||||||
bool "Enable UART3"
|
bool "Enable UART3"
|
||||||
default n
|
default n
|
||||||
|
@ -91,6 +110,53 @@ menu "On-chip Peripheral Drivers"
|
||||||
bool "Enable UART3 RX DMA"
|
bool "Enable UART3 RX DMA"
|
||||||
depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA
|
depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA
|
||||||
default n
|
default n
|
||||||
|
|
||||||
|
config BSP_UART3_TX_USING_DMA
|
||||||
|
bool "Enable UART3 TX DMA"
|
||||||
|
depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA
|
||||||
|
default n
|
||||||
|
|
||||||
|
config BSP_USING_UART4
|
||||||
|
bool "Enable UART4"
|
||||||
|
default n
|
||||||
|
|
||||||
|
config BSP_UART4_RX_USING_DMA
|
||||||
|
bool "Enable UART4 RX DMA"
|
||||||
|
depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA
|
||||||
|
default n
|
||||||
|
|
||||||
|
config BSP_UART4_TX_USING_DMA
|
||||||
|
bool "Enable UART4 TX DMA"
|
||||||
|
depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA
|
||||||
|
default n
|
||||||
|
|
||||||
|
config BSP_USING_UART5
|
||||||
|
bool "Enable UART5"
|
||||||
|
default n
|
||||||
|
|
||||||
|
config BSP_UART5_RX_USING_DMA
|
||||||
|
bool "Enable UART5 RX DMA"
|
||||||
|
depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA
|
||||||
|
default n
|
||||||
|
|
||||||
|
config BSP_UART5_TX_USING_DMA
|
||||||
|
bool "Enable UART5 TX DMA"
|
||||||
|
depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA
|
||||||
|
default n
|
||||||
|
|
||||||
|
config BSP_USING_UART6
|
||||||
|
bool "Enable UART6"
|
||||||
|
default n
|
||||||
|
|
||||||
|
config BSP_UART6_RX_USING_DMA
|
||||||
|
bool "Enable UART6 RX DMA"
|
||||||
|
depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA
|
||||||
|
default n
|
||||||
|
|
||||||
|
config BSP_UART6_TX_USING_DMA
|
||||||
|
bool "Enable UART6 TX DMA"
|
||||||
|
depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA
|
||||||
|
default n
|
||||||
endif
|
endif
|
||||||
|
|
||||||
menuconfig BSP_USING_TIM
|
menuconfig BSP_USING_TIM
|
||||||
|
|
|
@ -71,37 +71,35 @@ Mcu.Pin43=PG7
|
||||||
Mcu.Pin44=PG8
|
Mcu.Pin44=PG8
|
||||||
Mcu.Pin45=PA9
|
Mcu.Pin45=PA9
|
||||||
Mcu.Pin46=PA10
|
Mcu.Pin46=PA10
|
||||||
Mcu.Pin47=PA13 (JTMS/SWDIO)
|
Mcu.Pin47=PH13
|
||||||
Mcu.Pin48=PH13
|
Mcu.Pin48=PH14
|
||||||
Mcu.Pin49=PH14
|
Mcu.Pin49=PH15
|
||||||
Mcu.Pin5=PF3
|
Mcu.Pin5=PF3
|
||||||
Mcu.Pin50=PH15
|
Mcu.Pin50=PI0
|
||||||
Mcu.Pin51=PI0
|
Mcu.Pin51=PI1
|
||||||
Mcu.Pin52=PI1
|
Mcu.Pin52=PI2
|
||||||
Mcu.Pin53=PI2
|
Mcu.Pin53=PD0
|
||||||
Mcu.Pin54=PA14 (JTCK/SWCLK)
|
Mcu.Pin54=PD1
|
||||||
Mcu.Pin55=PD0
|
Mcu.Pin55=PG11
|
||||||
Mcu.Pin56=PD1
|
Mcu.Pin56=PG15
|
||||||
Mcu.Pin57=PG11
|
Mcu.Pin57=PE0
|
||||||
Mcu.Pin58=PG15
|
Mcu.Pin58=PE1
|
||||||
Mcu.Pin59=PE0
|
Mcu.Pin59=PI4
|
||||||
Mcu.Pin6=PF4
|
Mcu.Pin6=PF4
|
||||||
Mcu.Pin60=PE1
|
Mcu.Pin60=PI5
|
||||||
Mcu.Pin61=PI4
|
Mcu.Pin61=PI6
|
||||||
Mcu.Pin62=PI5
|
Mcu.Pin62=PI7
|
||||||
Mcu.Pin63=PI6
|
Mcu.Pin63=VP_DMA2D_VS_DMA2D
|
||||||
Mcu.Pin64=PI7
|
Mcu.Pin64=VP_SYS_VS_Systick
|
||||||
Mcu.Pin65=VP_DMA2D_VS_DMA2D
|
|
||||||
Mcu.Pin66=VP_SYS_VS_Systick
|
|
||||||
Mcu.Pin7=PF5
|
Mcu.Pin7=PF5
|
||||||
Mcu.Pin8=PF10
|
Mcu.Pin8=PF10
|
||||||
Mcu.Pin9=PH0-OSC_IN (PH0)
|
Mcu.Pin9=PH0-OSC_IN (PH0)
|
||||||
Mcu.PinsNb=67
|
Mcu.PinsNb=65
|
||||||
Mcu.ThirdPartyNb=0
|
Mcu.ThirdPartyNb=0
|
||||||
Mcu.UserConstants=
|
Mcu.UserConstants=
|
||||||
Mcu.UserName=STM32H743IITx
|
Mcu.UserName=STM32H743IITx
|
||||||
MxCube.Version=5.0.1
|
MxCube.Version=5.2.0
|
||||||
MxDb.Version=DB.5.0.1
|
MxDb.Version=DB.5.0.20
|
||||||
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
|
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
|
||||||
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
|
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
|
||||||
NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
|
NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
|
||||||
|
@ -116,10 +114,6 @@ NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
|
||||||
PA10.Locked=true
|
PA10.Locked=true
|
||||||
PA10.Mode=Asynchronous
|
PA10.Mode=Asynchronous
|
||||||
PA10.Signal=USART1_RX
|
PA10.Signal=USART1_RX
|
||||||
PA13\ (JTMS/SWDIO).Mode=Serial_Wire
|
|
||||||
PA13\ (JTMS/SWDIO).Signal=SYS_JTMS-SWDIO
|
|
||||||
PA14\ (JTCK/SWCLK).Mode=Serial_Wire
|
|
||||||
PA14\ (JTCK/SWCLK).Signal=SYS_JTCK-SWCLK
|
|
||||||
PA9.Locked=true
|
PA9.Locked=true
|
||||||
PA9.Mode=Asynchronous
|
PA9.Mode=Asynchronous
|
||||||
PA9.Signal=USART1_TX
|
PA9.Signal=USART1_TX
|
||||||
|
@ -128,7 +122,7 @@ PC2_C.Mode=SdramChipSelect1_1
|
||||||
PC2_C.Signal=FMC_SDNE0
|
PC2_C.Signal=FMC_SDNE0
|
||||||
PC3_C.Mode=SdramChipSelect1_1
|
PC3_C.Mode=SdramChipSelect1_1
|
||||||
PC3_C.Signal=FMC_SDCKE0
|
PC3_C.Signal=FMC_SDCKE0
|
||||||
PCC.Checker=false
|
PCC.Checker=true
|
||||||
PCC.Line=STM32H743/753
|
PCC.Line=STM32H743/753
|
||||||
PCC.MCU=STM32H743IITx
|
PCC.MCU=STM32H743IITx
|
||||||
PCC.PartNumber=STM32H743IITx
|
PCC.PartNumber=STM32H743IITx
|
||||||
|
@ -232,7 +226,7 @@ PI7.Signal=LTDC_B7
|
||||||
PI9.Mode=RGB565
|
PI9.Mode=RGB565
|
||||||
PI9.Signal=LTDC_VSYNC
|
PI9.Signal=LTDC_VSYNC
|
||||||
PinOutPanel.RotationAngle=0
|
PinOutPanel.RotationAngle=0
|
||||||
ProjectManager.AskForMigrate=false
|
ProjectManager.AskForMigrate=true
|
||||||
ProjectManager.BackupPrevious=false
|
ProjectManager.BackupPrevious=false
|
||||||
ProjectManager.CompilerOptimize=6
|
ProjectManager.CompilerOptimize=6
|
||||||
ProjectManager.ComputerToolchain=false
|
ProjectManager.ComputerToolchain=false
|
||||||
|
@ -241,7 +235,7 @@ ProjectManager.CustomerFirmwarePackage=
|
||||||
ProjectManager.DefaultFWLocation=true
|
ProjectManager.DefaultFWLocation=true
|
||||||
ProjectManager.DeletePrevious=true
|
ProjectManager.DeletePrevious=true
|
||||||
ProjectManager.DeviceId=STM32H743IITx
|
ProjectManager.DeviceId=STM32H743IITx
|
||||||
ProjectManager.FirmwarePackage=STM32Cube FW_H7 V1.3.2
|
ProjectManager.FirmwarePackage=STM32Cube FW_H7 V1.4.0
|
||||||
ProjectManager.FreePins=false
|
ProjectManager.FreePins=false
|
||||||
ProjectManager.HalAssertFull=false
|
ProjectManager.HalAssertFull=false
|
||||||
ProjectManager.HeapSize=0x200
|
ProjectManager.HeapSize=0x200
|
||||||
|
@ -304,7 +298,7 @@ RCC.HRTIMFreq_Value=200000000
|
||||||
RCC.HSE_VALUE=25000000
|
RCC.HSE_VALUE=25000000
|
||||||
RCC.I2C123Freq_Value=100000000
|
RCC.I2C123Freq_Value=100000000
|
||||||
RCC.I2C4Freq_Value=100000000
|
RCC.I2C4Freq_Value=100000000
|
||||||
RCC.IPParameters=ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CECFreq_Value,CKPERFreq_Value,CPU2Freq_Value,CPU2SystikFreq_Value,CortexFreq_Value,CpuClockFreq_Value,D1CPREFreq_Value,D1PPRE,D2PPRE1,D2PPRE2,D3PPRE,DFSDMACLkFreq_Value,DFSDMFreq_Value,DIVM1,DIVM3,DIVN1,DIVN3,DIVP1Freq_Value,DIVP2Freq_Value,DIVP3Freq_Value,DIVQ1Freq_Value,DIVQ2Freq_Value,DIVQ3Freq_Value,DIVR1Freq_Value,DIVR2Freq_Value,DIVR3,DIVR3Freq_Value,FDCANFreq_Value,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,HPRE,HRTIMFreq_Value,HSE_VALUE,I2C123Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM345Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,PLLSourceVirtual,QSPIFreq_Value,RNGFreq_Value,RTCFreq_Value,SAI1Freq_Value,SAI23Freq_Value,SAI4AFreq_Value,SAI4BFreq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI123Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16Freq_Value,USART234578Freq_Value,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value
|
RCC.IPParameters=ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CECFreq_Value,CKPERFreq_Value,CPU2Freq_Value,CPU2SystikFreq_Value,CortexFreq_Value,CpuClockFreq_Value,D1CPREFreq_Value,D1PPRE,D2PPRE1,D2PPRE2,D3PPRE,DFSDMACLkFreq_Value,DFSDMFreq_Value,DIVM1,DIVM3,DIVN1,DIVN3,DIVP1Freq_Value,DIVP2Freq_Value,DIVP3Freq_Value,DIVQ1Freq_Value,DIVQ2Freq_Value,DIVQ3Freq_Value,DIVR1Freq_Value,DIVR2Freq_Value,DIVR3,DIVR3Freq_Value,FDCANFreq_Value,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,HPRE,HRTIMFreq_Value,HSE_VALUE,I2C123Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM345Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,PLLSourceVirtual,PWR_Regulator_Voltage_Scale,QSPIFreq_Value,RNGFreq_Value,RTCFreq_Value,SAI1Freq_Value,SAI23Freq_Value,SAI4AFreq_Value,SAI4BFreq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI123Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16Freq_Value,USART234578Freq_Value,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value
|
||||||
RCC.LPTIM1Freq_Value=100000000
|
RCC.LPTIM1Freq_Value=100000000
|
||||||
RCC.LPTIM2Freq_Value=100000000
|
RCC.LPTIM2Freq_Value=100000000
|
||||||
RCC.LPTIM345Freq_Value=100000000
|
RCC.LPTIM345Freq_Value=100000000
|
||||||
|
@ -313,6 +307,7 @@ RCC.LTDCFreq_Value=9090909.090909092
|
||||||
RCC.MCO1PinFreq_Value=64000000
|
RCC.MCO1PinFreq_Value=64000000
|
||||||
RCC.MCO2PinFreq_Value=400000000
|
RCC.MCO2PinFreq_Value=400000000
|
||||||
RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
|
RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
|
||||||
|
RCC.PWR_Regulator_Voltage_Scale=PWR_REGULATOR_VOLTAGE_SCALE1
|
||||||
RCC.QSPIFreq_Value=200000000
|
RCC.QSPIFreq_Value=200000000
|
||||||
RCC.RNGFreq_Value=48000000
|
RCC.RNGFreq_Value=48000000
|
||||||
RCC.RTCFreq_Value=32000
|
RCC.RTCFreq_Value=32000
|
||||||
|
@ -330,7 +325,7 @@ RCC.SYSCLKFreq_VALUE=400000000
|
||||||
RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
|
RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
|
||||||
RCC.Tim1OutputFreq_Value=200000000
|
RCC.Tim1OutputFreq_Value=200000000
|
||||||
RCC.Tim2OutputFreq_Value=200000000
|
RCC.Tim2OutputFreq_Value=200000000
|
||||||
RCC.TraceFreq_Value=400000000
|
RCC.TraceFreq_Value=64000000
|
||||||
RCC.USART16Freq_Value=100000000
|
RCC.USART16Freq_Value=100000000
|
||||||
RCC.USART234578Freq_Value=100000000
|
RCC.USART234578Freq_Value=100000000
|
||||||
RCC.USBFreq_Value=400000000
|
RCC.USBFreq_Value=400000000
|
||||||
|
|
Loading…
Reference in New Issue