Bernard Xiong
GitHub
commit
d8dcd4d7ab
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@ -22,6 +22,12 @@ CONFIG_RT_USING_IDLE_HOOK=y
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CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
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CONFIG_IDLE_THREAD_STACK_SIZE=256
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# CONFIG_RT_USING_TIMER_SOFT is not set
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#
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# kservice optimization
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#
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# CONFIG_RT_KSERVICE_USING_STDLIB is not set
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# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
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CONFIG_RT_DEBUG=y
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# CONFIG_RT_DEBUG_COLOR is not set
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# CONFIG_RT_DEBUG_INIT_CONFIG is not set
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@ -53,6 +59,7 @@ CONFIG_RT_USING_MEMPOOL=y
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# CONFIG_RT_USING_NOHEAP is not set
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CONFIG_RT_USING_SMALL_MEM=y
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# CONFIG_RT_USING_SLAB is not set
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# CONFIG_RT_USING_USERHEAP is not set
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# CONFIG_RT_USING_MEMTRACE is not set
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CONFIG_RT_USING_HEAP=y
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@ -65,10 +72,14 @@ CONFIG_RT_USING_DEVICE=y
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CONFIG_RT_USING_CONSOLE=y
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CONFIG_RT_CONSOLEBUF_SIZE=128
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CONFIG_RT_CONSOLE_DEVICE_NAME="uart"
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CONFIG_RT_VER_NUM=0x40002
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CONFIG_RT_VER_NUM=0x40003
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CONFIG_ARCH_ARM=y
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# CONFIG_RT_USING_CPU_FFS is not set
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CONFIG_ARCH_ARM_CORTEX_A=y
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# CONFIG_RT_SMP_AUTO_BOOT is not set
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CONFIG_RT_USING_GIC_V2=y
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# CONFIG_RT_USING_GIC_V3 is not set
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# CONFIG_RT_NO_USING_GIC is not set
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CONFIG_ARCH_ARM_CORTEX_A7=y
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# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
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@ -115,8 +126,6 @@ CONFIG_DFS_FD_MAX=16
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CONFIG_RT_USING_DFS_DEVFS=y
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# CONFIG_RT_USING_DFS_ROMFS is not set
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# CONFIG_RT_USING_DFS_RAMFS is not set
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# CONFIG_RT_USING_DFS_UFFS is not set
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# CONFIG_RT_USING_DFS_JFFS2 is not set
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#
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# Device Drivers
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@ -131,8 +140,10 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
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# CONFIG_RT_USING_HWTIMER is not set
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# CONFIG_RT_USING_CPUTIME is not set
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# CONFIG_RT_USING_I2C is not set
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# CONFIG_RT_USING_PHY is not set
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CONFIG_RT_USING_PIN=y
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# CONFIG_RT_USING_ADC is not set
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# CONFIG_RT_USING_DAC is not set
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# CONFIG_RT_USING_PWM is not set
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# CONFIG_RT_USING_MTD_NOR is not set
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# CONFIG_RT_USING_MTD_NAND is not set
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@ -163,6 +174,7 @@ CONFIG_RT_USING_LIBC=y
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CONFIG_RT_USING_POSIX=y
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# CONFIG_RT_USING_POSIX_MMAP is not set
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# CONFIG_RT_USING_POSIX_TERMIOS is not set
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# CONFIG_RT_USING_POSIX_GETLINE is not set
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# CONFIG_RT_USING_POSIX_AIO is not set
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# CONFIG_RT_USING_MODULE is not set
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@ -210,10 +222,15 @@ CONFIG_RT_USING_POSIX=y
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#
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# IoT - internet of things
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#
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# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
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# CONFIG_PKG_USING_PAHOMQTT is not set
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# CONFIG_PKG_USING_UMQTT is not set
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# CONFIG_PKG_USING_WEBCLIENT is not set
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# CONFIG_PKG_USING_WEBNET is not set
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# CONFIG_PKG_USING_MONGOOSE is not set
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# CONFIG_PKG_USING_MYMQTT is not set
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# CONFIG_PKG_USING_KAWAII_MQTT is not set
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# CONFIG_PKG_USING_BC28_MQTT is not set
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# CONFIG_PKG_USING_WEBTERMINAL is not set
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# CONFIG_PKG_USING_CJSON is not set
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# CONFIG_PKG_USING_JSMN is not set
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@ -240,6 +257,8 @@ CONFIG_RT_USING_POSIX=y
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# CONFIG_PKG_USING_COAP is not set
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# CONFIG_PKG_USING_NOPOLL is not set
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# CONFIG_PKG_USING_NETUTILS is not set
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# CONFIG_PKG_USING_CMUX is not set
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# CONFIG_PKG_USING_PPP_DEVICE is not set
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# CONFIG_PKG_USING_AT_DEVICE is not set
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# CONFIG_PKG_USING_ATSRV_SOCKET is not set
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# CONFIG_PKG_USING_WIZNET is not set
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@ -251,8 +270,10 @@ CONFIG_RT_USING_POSIX=y
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# CONFIG_PKG_USING_GAGENT_CLOUD is not set
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# CONFIG_PKG_USING_ALI_IOTKIT is not set
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# CONFIG_PKG_USING_AZURE is not set
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# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
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# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
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# CONFIG_PKG_USING_JIOT-C-SDK is not set
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# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
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# CONFIG_PKG_USING_JOYLINK is not set
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# CONFIG_PKG_USING_NIMBLE is not set
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# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
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# CONFIG_PKG_USING_IPMSG is not set
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@ -263,6 +284,19 @@ CONFIG_RT_USING_POSIX=y
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# CONFIG_PKG_USING_PROTOBUF_C is not set
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# CONFIG_PKG_USING_ONNX_PARSER is not set
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# CONFIG_PKG_USING_ONNX_BACKEND is not set
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# CONFIG_PKG_USING_DLT645 is not set
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# CONFIG_PKG_USING_QXWZ is not set
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# CONFIG_PKG_USING_SMTP_CLIENT is not set
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# CONFIG_PKG_USING_ABUP_FOTA is not set
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# CONFIG_PKG_USING_LIBCURL2RTT is not set
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# CONFIG_PKG_USING_CAPNP is not set
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# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
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# CONFIG_PKG_USING_AGILE_TELNET is not set
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# CONFIG_PKG_USING_NMEALIB is not set
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# CONFIG_PKG_USING_AGILE_JSMN is not set
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# CONFIG_PKG_USING_PDULIB is not set
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# CONFIG_PKG_USING_BTSTACK is not set
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# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
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#
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# security packages
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@ -270,6 +304,8 @@ CONFIG_RT_USING_POSIX=y
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# CONFIG_PKG_USING_MBEDTLS is not set
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# CONFIG_PKG_USING_libsodium is not set
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# CONFIG_PKG_USING_TINYCRYPT is not set
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# CONFIG_PKG_USING_TFM is not set
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# CONFIG_PKG_USING_YD_CRYPTO is not set
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#
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# language packages
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@ -286,6 +322,7 @@ CONFIG_RT_USING_POSIX=y
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# CONFIG_PKG_USING_STEMWIN is not set
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# CONFIG_PKG_USING_WAVPLAYER is not set
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# CONFIG_PKG_USING_TJPGD is not set
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# CONFIG_PKG_USING_HELIX is not set
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#
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# tools packages
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@ -298,6 +335,15 @@ CONFIG_RT_USING_POSIX=y
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# CONFIG_PKG_USING_QRCODE is not set
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# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
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# CONFIG_PKG_USING_ADBD is not set
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# CONFIG_PKG_USING_COREMARK is not set
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# CONFIG_PKG_USING_DHRYSTONE is not set
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# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
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# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
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# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
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# CONFIG_PKG_USING_BS8116A is not set
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# CONFIG_PKG_USING_GPS_RMC is not set
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# CONFIG_PKG_USING_URLENCODE is not set
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# CONFIG_PKG_USING_UMCN is not set
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#
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# system packages
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@ -309,6 +355,7 @@ CONFIG_RT_USING_POSIX=y
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# CONFIG_PKG_USING_LWEXT4 is not set
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# CONFIG_PKG_USING_PARTITION is not set
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# CONFIG_PKG_USING_FAL is not set
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# CONFIG_PKG_USING_FLASHDB is not set
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# CONFIG_PKG_USING_SQLITE is not set
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# CONFIG_PKG_USING_RTI is not set
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# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
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@ -317,6 +364,14 @@ CONFIG_RT_USING_POSIX=y
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# CONFIG_PKG_USING_LITTLEFS is not set
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# CONFIG_PKG_USING_THREAD_POOL is not set
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# CONFIG_PKG_USING_ROBOTS is not set
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# CONFIG_PKG_USING_EV is not set
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# CONFIG_PKG_USING_SYSWATCH is not set
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# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
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# CONFIG_PKG_USING_PLCCORE is not set
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# CONFIG_PKG_USING_RAMDISK is not set
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# CONFIG_PKG_USING_MININI is not set
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# CONFIG_PKG_USING_QBOOT is not set
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# CONFIG_PKG_USING_PPOOL is not set
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#
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# peripheral libraries and drivers
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@ -324,6 +379,7 @@ CONFIG_RT_USING_POSIX=y
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# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
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# CONFIG_PKG_USING_REALTEK_AMEBA is not set
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# CONFIG_PKG_USING_SHT2X is not set
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# CONFIG_PKG_USING_SHT3X is not set
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# CONFIG_PKG_USING_STM32_SDIO is not set
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# CONFIG_PKG_USING_ICM20608 is not set
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# CONFIG_PKG_USING_U8G2 is not set
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@ -332,10 +388,16 @@ CONFIG_RT_USING_POSIX=y
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# CONFIG_PKG_USING_SX12XX is not set
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# CONFIG_PKG_USING_SIGNAL_LED is not set
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# CONFIG_PKG_USING_LEDBLINK is not set
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# CONFIG_PKG_USING_LITTLED is not set
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# CONFIG_PKG_USING_LKDGUI is not set
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# CONFIG_PKG_USING_NRF5X_SDK is not set
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# CONFIG_PKG_USING_NRFX is not set
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# CONFIG_PKG_USING_WM_LIBRARIES is not set
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# CONFIG_PKG_USING_KENDRYTE_SDK is not set
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# CONFIG_PKG_USING_INFRARED is not set
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# CONFIG_PKG_USING_ROSSERIAL is not set
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# CONFIG_PKG_USING_AGILE_BUTTON is not set
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# CONFIG_PKG_USING_AGILE_LED is not set
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# CONFIG_PKG_USING_AT24CXX is not set
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# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
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# CONFIG_PKG_USING_AD7746 is not set
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@ -343,8 +405,28 @@ CONFIG_RT_USING_POSIX=y
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# CONFIG_PKG_USING_I2C_TOOLS is not set
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# CONFIG_PKG_USING_NRF24L01 is not set
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# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
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# CONFIG_PKG_USING_LCD_DRIVERS is not set
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# CONFIG_PKG_USING_MAX17048 is not set
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# CONFIG_PKG_USING_RPLIDAR is not set
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# CONFIG_PKG_USING_AS608 is not set
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# CONFIG_PKG_USING_RC522 is not set
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# CONFIG_PKG_USING_WS2812B is not set
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# CONFIG_PKG_USING_EMBARC_BSP is not set
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# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
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# CONFIG_PKG_USING_MULTI_RTIMER is not set
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# CONFIG_PKG_USING_MAX7219 is not set
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# CONFIG_PKG_USING_BEEP is not set
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# CONFIG_PKG_USING_EASYBLINK is not set
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# CONFIG_PKG_USING_PMS_SERIES is not set
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# CONFIG_PKG_USING_CAN_YMODEM is not set
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# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
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# CONFIG_PKG_USING_QLED is not set
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# CONFIG_PKG_USING_PAJ7620 is not set
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# CONFIG_PKG_USING_AGILE_CONSOLE is not set
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# CONFIG_PKG_USING_LD3320 is not set
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# CONFIG_PKG_USING_WK2124 is not set
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# CONFIG_PKG_USING_LY68L6400 is not set
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# CONFIG_PKG_USING_DM9051 is not set
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# CONFIG_PKG_USING_SSD1306 is not set
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#
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# miscellaneous packages
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@ -379,4 +461,12 @@ CONFIG_RT_USING_POSIX=y
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# CONFIG_PKG_USING_ELAPACK is not set
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# CONFIG_PKG_USING_ARMv7M_DWT is not set
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# CONFIG_PKG_USING_VT100 is not set
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# CONFIG_PKG_USING_TETRIS is not set
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# CONFIG_PKG_USING_ULAPACK is not set
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# CONFIG_PKG_USING_UKAL is not set
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# CONFIG_PKG_USING_CRCLIB is not set
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# CONFIG_PKG_USING_THREES is not set
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# CONFIG_PKG_USING_2048 is not set
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# CONFIG_PKG_USING_LWGPS is not set
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# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
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CONFIG_SOC_MCIMX6X4=y
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@ -9,12 +9,8 @@
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/* RT-Thread Kernel */
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#define RT_NAME_MAX 8
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/* RT_USING_ARCH_DATA_TYPE is not set */
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/* RT_USING_SMP is not set */
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#define RT_ALIGN_SIZE 4
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/* RT_THREAD_PRIORITY_8 is not set */
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#define RT_THREAD_PRIORITY_32
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/* RT_THREAD_PRIORITY_256 is not set */
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#define RT_THREAD_PRIORITY_MAX 32
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#define RT_TICK_PER_SECOND 100
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#define RT_USING_OVERFLOW_CHECK
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@ -22,19 +18,10 @@
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#define RT_USING_IDLE_HOOK
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#define RT_IDLE_HOOK_LIST_SIZE 4
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#define IDLE_THREAD_STACK_SIZE 256
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/* RT_USING_TIMER_SOFT is not set */
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/* kservice optimization */
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#define RT_DEBUG
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/* RT_DEBUG_COLOR is not set */
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/* RT_DEBUG_INIT_CONFIG is not set */
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/* RT_DEBUG_THREAD_CONFIG is not set */
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/* RT_DEBUG_SCHEDULER_CONFIG is not set */
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/* RT_DEBUG_IPC_CONFIG is not set */
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/* RT_DEBUG_TIMER_CONFIG is not set */
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/* RT_DEBUG_IRQ_CONFIG is not set */
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/* RT_DEBUG_MEM_CONFIG is not set */
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/* RT_DEBUG_SLAB_CONFIG is not set */
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/* RT_DEBUG_MEMHEAP_CONFIG is not set */
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/* RT_DEBUG_MODULE_CONFIG is not set */
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/* Inter-Thread communication */
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@ -43,41 +30,31 @@
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#define RT_USING_EVENT
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#define RT_USING_MAILBOX
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#define RT_USING_MESSAGEQUEUE
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/* RT_USING_SIGNALS is not set */
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/* Memory Management */
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#define RT_USING_MEMPOOL
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/* RT_USING_MEMHEAP is not set */
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/* RT_USING_NOHEAP is not set */
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#define RT_USING_SMALL_MEM
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/* RT_USING_SLAB is not set */
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/* RT_USING_MEMTRACE is not set */
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#define RT_USING_HEAP
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/* Kernel Device Object */
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#define RT_USING_DEVICE
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/* RT_USING_DEVICE_OPS is not set */
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/* RT_USING_INTERRUPT_INFO is not set */
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#define RT_USING_CONSOLE
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#define RT_CONSOLEBUF_SIZE 128
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#define RT_CONSOLE_DEVICE_NAME "uart"
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#define RT_VER_NUM 0x40002
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#define RT_VER_NUM 0x40003
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#define ARCH_ARM
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/* RT_USING_CPU_FFS is not set */
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#define ARCH_ARM_CORTEX_A
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#define RT_USING_GIC_V2
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#define ARCH_ARM_CORTEX_A7
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/* ARCH_CPU_STACK_GROWS_UPWARD is not set */
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/* RT-Thread Components */
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#define RT_USING_COMPONENTS_INIT
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/* RT_USING_USER_MAIN is not set */
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/* C++ features */
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/* RT_USING_CPLUSPLUS is not set */
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/* Command shell */
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@ -87,14 +64,11 @@
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#define FINSH_HISTORY_LINES 5
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#define FINSH_USING_SYMTAB
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#define FINSH_USING_DESCRIPTION
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/* FINSH_ECHO_DISABLE_DEFAULT is not set */
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#define FINSH_THREAD_PRIORITY 20
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#define FINSH_THREAD_STACK_SIZE 4096
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#define FINSH_CMD_SIZE 80
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/* FINSH_USING_AUTH is not set */
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#define FINSH_USING_MSH
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#define FINSH_USING_MSH_DEFAULT
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/* FINSH_USING_MSH_ONLY is not set */
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#define FINSH_ARG_MAX 10
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/* Device virtual file system */
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@ -104,248 +78,84 @@
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#define DFS_FILESYSTEMS_MAX 2
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#define DFS_FILESYSTEM_TYPES_MAX 2
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#define DFS_FD_MAX 16
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/* RT_USING_DFS_MNTTABLE is not set */
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/* RT_USING_DFS_ELMFAT is not set */
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#define RT_USING_DFS_DEVFS
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/* RT_USING_DFS_ROMFS is not set */
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/* RT_USING_DFS_RAMFS is not set */
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/* RT_USING_DFS_UFFS is not set */
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/* RT_USING_DFS_JFFS2 is not set */
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/* Device Drivers */
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#define RT_USING_DEVICE_IPC
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#define RT_PIPE_BUFSZ 512
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/* RT_USING_SYSTEM_WORKQUEUE is not set */
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#define RT_USING_SERIAL
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#define RT_SERIAL_USING_DMA
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#define RT_SERIAL_RB_BUFSZ 64
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/* RT_USING_CAN is not set */
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/* RT_USING_HWTIMER is not set */
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/* RT_USING_CPUTIME is not set */
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/* RT_USING_I2C is not set */
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#define RT_USING_PIN
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/* RT_USING_ADC is not set */
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/* RT_USING_PWM is not set */
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/* RT_USING_MTD_NOR is not set */
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/* RT_USING_MTD_NAND is not set */
|
||||
/* RT_USING_PM is not set */
|
||||
/* RT_USING_RTC is not set */
|
||||
/* RT_USING_SDIO is not set */
|
||||
/* RT_USING_SPI is not set */
|
||||
/* RT_USING_WDT is not set */
|
||||
/* RT_USING_AUDIO is not set */
|
||||
/* RT_USING_SENSOR is not set */
|
||||
/* RT_USING_TOUCH is not set */
|
||||
/* RT_USING_HWCRYPTO is not set */
|
||||
/* RT_USING_PULSE_ENCODER is not set */
|
||||
/* RT_USING_INPUT_CAPTURE is not set */
|
||||
/* RT_USING_WIFI is not set */
|
||||
|
||||
/* Using USB */
|
||||
|
||||
/* RT_USING_USB_HOST is not set */
|
||||
/* RT_USING_USB_DEVICE is not set */
|
||||
|
||||
/* POSIX layer and C standard library */
|
||||
|
||||
#define RT_USING_LIBC
|
||||
/* RT_USING_PTHREADS is not set */
|
||||
#define RT_USING_POSIX
|
||||
/* RT_USING_POSIX_MMAP is not set */
|
||||
/* RT_USING_POSIX_TERMIOS is not set */
|
||||
/* RT_USING_POSIX_AIO is not set */
|
||||
/* RT_USING_MODULE is not set */
|
||||
|
||||
/* Network */
|
||||
|
||||
/* Socket abstraction layer */
|
||||
|
||||
/* RT_USING_SAL is not set */
|
||||
|
||||
/* Network interface device */
|
||||
|
||||
/* RT_USING_NETDEV is not set */
|
||||
|
||||
/* light weight TCP/IP stack */
|
||||
|
||||
/* RT_USING_LWIP is not set */
|
||||
|
||||
/* AT commands */
|
||||
|
||||
/* RT_USING_AT is not set */
|
||||
|
||||
/* VBUS(Virtual Software BUS) */
|
||||
|
||||
/* RT_USING_VBUS is not set */
|
||||
|
||||
/* Utilities */
|
||||
|
||||
/* RT_USING_RYM is not set */
|
||||
/* RT_USING_ULOG is not set */
|
||||
/* RT_USING_UTEST is not set */
|
||||
/* RT_USING_LWP is not set */
|
||||
|
||||
/* RT-Thread online packages */
|
||||
|
||||
/* IoT - internet of things */
|
||||
|
||||
/* PKG_USING_PAHOMQTT is not set */
|
||||
/* PKG_USING_WEBCLIENT is not set */
|
||||
/* PKG_USING_WEBNET is not set */
|
||||
/* PKG_USING_MONGOOSE is not set */
|
||||
/* PKG_USING_WEBTERMINAL is not set */
|
||||
/* PKG_USING_CJSON is not set */
|
||||
/* PKG_USING_JSMN is not set */
|
||||
/* PKG_USING_LIBMODBUS is not set */
|
||||
/* PKG_USING_FREEMODBUS is not set */
|
||||
/* PKG_USING_LJSON is not set */
|
||||
/* PKG_USING_EZXML is not set */
|
||||
/* PKG_USING_NANOPB is not set */
|
||||
|
||||
/* Wi-Fi */
|
||||
|
||||
/* Marvell WiFi */
|
||||
|
||||
/* PKG_USING_WLANMARVELL is not set */
|
||||
|
||||
/* Wiced WiFi */
|
||||
|
||||
/* PKG_USING_WLAN_WICED is not set */
|
||||
/* PKG_USING_RW007 is not set */
|
||||
/* PKG_USING_COAP is not set */
|
||||
/* PKG_USING_NOPOLL is not set */
|
||||
/* PKG_USING_NETUTILS is not set */
|
||||
/* PKG_USING_AT_DEVICE is not set */
|
||||
/* PKG_USING_ATSRV_SOCKET is not set */
|
||||
/* PKG_USING_WIZNET is not set */
|
||||
|
||||
/* IoT Cloud */
|
||||
|
||||
/* PKG_USING_ONENET is not set */
|
||||
/* PKG_USING_GAGENT_CLOUD is not set */
|
||||
/* PKG_USING_ALI_IOTKIT is not set */
|
||||
/* PKG_USING_AZURE is not set */
|
||||
/* PKG_USING_TENCENT_IOTHUB is not set */
|
||||
/* PKG_USING_JIOT-C-SDK is not set */
|
||||
/* PKG_USING_NIMBLE is not set */
|
||||
/* PKG_USING_OTA_DOWNLOADER is not set */
|
||||
/* PKG_USING_IPMSG is not set */
|
||||
/* PKG_USING_LSSDP is not set */
|
||||
/* PKG_USING_AIRKISS_OPEN is not set */
|
||||
/* PKG_USING_LIBRWS is not set */
|
||||
/* PKG_USING_TCPSERVER is not set */
|
||||
/* PKG_USING_PROTOBUF_C is not set */
|
||||
/* PKG_USING_ONNX_PARSER is not set */
|
||||
/* PKG_USING_ONNX_BACKEND is not set */
|
||||
|
||||
/* security packages */
|
||||
|
||||
/* PKG_USING_MBEDTLS is not set */
|
||||
/* PKG_USING_libsodium is not set */
|
||||
/* PKG_USING_TINYCRYPT is not set */
|
||||
|
||||
/* language packages */
|
||||
|
||||
/* PKG_USING_LUA is not set */
|
||||
/* PKG_USING_JERRYSCRIPT is not set */
|
||||
/* PKG_USING_MICROPYTHON is not set */
|
||||
|
||||
/* multimedia packages */
|
||||
|
||||
/* PKG_USING_OPENMV is not set */
|
||||
/* PKG_USING_MUPDF is not set */
|
||||
/* PKG_USING_STEMWIN is not set */
|
||||
/* PKG_USING_WAVPLAYER is not set */
|
||||
/* PKG_USING_TJPGD is not set */
|
||||
|
||||
/* tools packages */
|
||||
|
||||
/* PKG_USING_CMBACKTRACE is not set */
|
||||
/* PKG_USING_EASYFLASH is not set */
|
||||
/* PKG_USING_EASYLOGGER is not set */
|
||||
/* PKG_USING_SYSTEMVIEW is not set */
|
||||
/* PKG_USING_RDB is not set */
|
||||
/* PKG_USING_QRCODE is not set */
|
||||
/* PKG_USING_ULOG_EASYFLASH is not set */
|
||||
/* PKG_USING_ADBD is not set */
|
||||
|
||||
/* system packages */
|
||||
|
||||
/* PKG_USING_GUIENGINE is not set */
|
||||
/* PKG_USING_PERSIMMON is not set */
|
||||
/* PKG_USING_CAIRO is not set */
|
||||
/* PKG_USING_PIXMAN is not set */
|
||||
/* PKG_USING_LWEXT4 is not set */
|
||||
/* PKG_USING_PARTITION is not set */
|
||||
/* PKG_USING_FAL is not set */
|
||||
/* PKG_USING_SQLITE is not set */
|
||||
/* PKG_USING_RTI is not set */
|
||||
/* PKG_USING_LITTLEVGL2RTT is not set */
|
||||
/* PKG_USING_CMSIS is not set */
|
||||
/* PKG_USING_DFS_YAFFS is not set */
|
||||
/* PKG_USING_LITTLEFS is not set */
|
||||
/* PKG_USING_THREAD_POOL is not set */
|
||||
/* PKG_USING_ROBOTS is not set */
|
||||
|
||||
/* peripheral libraries and drivers */
|
||||
|
||||
/* PKG_USING_SENSORS_DRIVERS is not set */
|
||||
/* PKG_USING_REALTEK_AMEBA is not set */
|
||||
/* PKG_USING_SHT2X is not set */
|
||||
/* PKG_USING_STM32_SDIO is not set */
|
||||
/* PKG_USING_ICM20608 is not set */
|
||||
/* PKG_USING_U8G2 is not set */
|
||||
/* PKG_USING_BUTTON is not set */
|
||||
/* PKG_USING_PCF8574 is not set */
|
||||
/* PKG_USING_SX12XX is not set */
|
||||
/* PKG_USING_SIGNAL_LED is not set */
|
||||
/* PKG_USING_LEDBLINK is not set */
|
||||
/* PKG_USING_WM_LIBRARIES is not set */
|
||||
/* PKG_USING_KENDRYTE_SDK is not set */
|
||||
/* PKG_USING_INFRARED is not set */
|
||||
/* PKG_USING_ROSSERIAL is not set */
|
||||
/* PKG_USING_AT24CXX is not set */
|
||||
/* PKG_USING_MOTIONDRIVER2RTT is not set */
|
||||
/* PKG_USING_AD7746 is not set */
|
||||
/* PKG_USING_PCA9685 is not set */
|
||||
/* PKG_USING_I2C_TOOLS is not set */
|
||||
/* PKG_USING_NRF24L01 is not set */
|
||||
/* PKG_USING_TOUCH_DRIVERS is not set */
|
||||
/* PKG_USING_LCD_DRIVERS is not set */
|
||||
/* PKG_USING_MAX17048 is not set */
|
||||
|
||||
/* miscellaneous packages */
|
||||
|
||||
/* PKG_USING_LIBCSV is not set */
|
||||
/* PKG_USING_OPTPARSE is not set */
|
||||
/* PKG_USING_FASTLZ is not set */
|
||||
/* PKG_USING_MINILZO is not set */
|
||||
/* PKG_USING_QUICKLZ is not set */
|
||||
/* PKG_USING_MULTIBUTTON is not set */
|
||||
/* PKG_USING_FLEXIBLE_BUTTON is not set */
|
||||
/* PKG_USING_CANFESTIVAL is not set */
|
||||
/* PKG_USING_ZLIB is not set */
|
||||
/* PKG_USING_DSTR is not set */
|
||||
/* PKG_USING_TINYFRAME is not set */
|
||||
/* PKG_USING_KENDRYTE_DEMO is not set */
|
||||
/* PKG_USING_DIGITALCTRL is not set */
|
||||
/* PKG_USING_UPACKER is not set */
|
||||
/* PKG_USING_UPARAM is not set */
|
||||
|
||||
/* samples: kernel and components samples */
|
||||
|
||||
/* PKG_USING_KERNEL_SAMPLES is not set */
|
||||
/* PKG_USING_FILESYSTEM_SAMPLES is not set */
|
||||
/* PKG_USING_NETWORK_SAMPLES is not set */
|
||||
/* PKG_USING_PERIPHERAL_SAMPLES is not set */
|
||||
/* PKG_USING_HELLO is not set */
|
||||
/* PKG_USING_VI is not set */
|
||||
/* PKG_USING_NNOM is not set */
|
||||
/* PKG_USING_LIBANN is not set */
|
||||
/* PKG_USING_ELAPACK is not set */
|
||||
/* PKG_USING_ARMv7M_DWT is not set */
|
||||
/* PKG_USING_VT100 is not set */
|
||||
#define SOC_MCIMX6X4
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -79,6 +79,10 @@ CONFIG_RT_VER_NUM=0x40004
|
|||
CONFIG_ARCH_ARM=y
|
||||
# CONFIG_RT_USING_CPU_FFS is not set
|
||||
CONFIG_ARCH_ARM_CORTEX_A=y
|
||||
# CONFIG_RT_SMP_AUTO_BOOT is not set
|
||||
CONFIG_RT_USING_GIC_V2=y
|
||||
# CONFIG_RT_USING_GIC_V3 is not set
|
||||
# CONFIG_RT_NO_USING_GIC is not set
|
||||
CONFIG_ARCH_ARM_CORTEX_A9=y
|
||||
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
|
||||
|
||||
|
|
|
|||
|
|
@ -26,10 +26,16 @@ static void rt_hw_timer2_isr(int vector, void *param)
|
|||
timer_clear_pending(0);
|
||||
}
|
||||
|
||||
void set_secondary_cpu_boot_address(void)
|
||||
{
|
||||
extern void secondary_cpu_start(void);
|
||||
uint32_t *boot_address = (uint32_t *)0x10000030;
|
||||
*(boot_address + 1) = ~0ul;
|
||||
*boot_address = (uint32_t )&secondary_cpu_start;
|
||||
}
|
||||
|
||||
void rt_hw_secondary_cpu_up(void)
|
||||
{
|
||||
extern void set_secondary_cpu_boot_address(void);
|
||||
|
||||
set_secondary_cpu_boot_address();
|
||||
__asm__ volatile ("dsb":::"memory");
|
||||
rt_hw_ipi_send(0, 1 << 1);
|
||||
|
|
|
|||
|
|
@ -55,6 +55,7 @@
|
|||
#define RT_VER_NUM 0x40004
|
||||
#define ARCH_ARM
|
||||
#define ARCH_ARM_CORTEX_A
|
||||
#define RT_USING_GIC_V2
|
||||
#define ARCH_ARM_CORTEX_A9
|
||||
|
||||
/* RT-Thread Components */
|
||||
|
|
|
|||
|
|
@ -55,6 +55,7 @@
|
|||
#define RT_VER_NUM 0x40004
|
||||
#define ARCH_ARM
|
||||
#define ARCH_ARM_CORTEX_A
|
||||
#define RT_USING_GIC_V2
|
||||
#define ARCH_ARM_CORTEX_A9
|
||||
|
||||
/* RT-Thread Components */
|
||||
|
|
|
|||
|
|
@ -58,6 +58,26 @@ config ARCH_ARM_CORTEX_A
|
|||
bool
|
||||
select ARCH_ARM
|
||||
|
||||
if ARCH_ARM_CORTEX_A
|
||||
config RT_SMP_AUTO_BOOT
|
||||
bool
|
||||
default n
|
||||
|
||||
choice
|
||||
prompt "GIC controller selection"
|
||||
default RT_USING_GIC_V2
|
||||
|
||||
config RT_USING_GIC_V2
|
||||
bool " Gic version 2 "
|
||||
|
||||
config RT_USING_GIC_V3
|
||||
bool " Gic version 3 "
|
||||
|
||||
config RT_NO_USING_GIC
|
||||
bool " GIC controller is not used "
|
||||
endchoice
|
||||
endif
|
||||
|
||||
config ARCH_ARM_CORTEX_A5
|
||||
bool
|
||||
select ARCH_ARM_CORTEX_A
|
||||
|
|
|
|||
|
|
@ -5,9 +5,27 @@ from building import *
|
|||
Import('rtconfig')
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src = Glob('*.c') + Glob('*.cpp')
|
||||
src = Split('''
|
||||
cache.c
|
||||
cpu.c
|
||||
gtimer.c
|
||||
mmu.c
|
||||
pmu.c
|
||||
stack.c
|
||||
|
||||
''')
|
||||
CPPPATH = [cwd]
|
||||
|
||||
if GetDepend('RT_USING_GIC_V2'):
|
||||
src += ['interrupt.c']
|
||||
src += ['gic.c']
|
||||
src += ['trap.c']
|
||||
|
||||
if GetDepend('RT_USING_GIC_V3'):
|
||||
src += ['interrupt.c']
|
||||
src += ['gicv3.c']
|
||||
src += ['trap.c']
|
||||
|
||||
if rtconfig.PLATFORM == 'armcc':
|
||||
src += Glob('*_rvds.S')
|
||||
|
||||
|
|
@ -18,6 +36,9 @@ if rtconfig.PLATFORM == 'gcc':
|
|||
if rtconfig.PLATFORM == 'iar':
|
||||
src += Glob('*_iar.S')
|
||||
|
||||
if rtconfig.PLATFORM == 'iar':
|
||||
src += Glob('*_iar.S')
|
||||
|
||||
group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
Return('group')
|
||||
|
|
|
|||
|
|
@ -15,8 +15,7 @@
|
|||
#define __get_cp64(cp, op1, Rt, CRm) __asm__ volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
|
||||
#define __set_cp64(cp, op1, Rt, CRm) __asm__ volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
|
||||
|
||||
unsigned long rt_cpu_get_smp_id(void);
|
||||
|
||||
int rt_hw_cpu_id(void);
|
||||
void rt_cpu_mmu_disable(void);
|
||||
void rt_cpu_mmu_enable(void);
|
||||
void rt_cpu_tlb_set(volatile unsigned long*);
|
||||
|
|
|
|||
|
|
@ -8,9 +8,11 @@
|
|||
* 2013-07-05 Bernard the first version
|
||||
*/
|
||||
|
||||
.globl rt_cpu_get_smp_id
|
||||
rt_cpu_get_smp_id:
|
||||
mrc p15, #0, r0, c0, c0, #5
|
||||
.weak rt_hw_cpu_id
|
||||
rt_hw_cpu_id:
|
||||
mrc p15, #0, r0, c0, c0, #5 @ read multiprocessor affinity register
|
||||
ldr r1, =0xFFFF03 @ Affinity mask off, leaving CPU ID field, [0:1]CPU ID, [8:15]Cluster ID Aff1, [16:23]Cluster ID Aff2
|
||||
and r0, r0, r1
|
||||
bx lr
|
||||
|
||||
.globl rt_cpu_vector_set_base
|
||||
|
|
|
|||
|
|
@ -15,17 +15,6 @@
|
|||
|
||||
#ifdef RT_USING_SMP
|
||||
|
||||
int rt_hw_cpu_id(void)
|
||||
{
|
||||
int cpu_id;
|
||||
__asm__ volatile (
|
||||
"mrc p15, 0, %0, c0, c0, 5"
|
||||
:"=r"(cpu_id)
|
||||
);
|
||||
cpu_id &= 0xf;
|
||||
return cpu_id;
|
||||
};
|
||||
|
||||
void rt_hw_spin_lock_init(rt_hw_spinlock_t *lock)
|
||||
{
|
||||
lock->slock = 0;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,708 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2013-07-20 Bernard first version
|
||||
* 2014-04-03 Grissiom many enhancements
|
||||
* 2018-11-22 Jesven add rt_hw_ipi_send()
|
||||
* add rt_hw_ipi_handler_install()
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
|
||||
#include "gicv3.h"
|
||||
#include "cp15.h"
|
||||
|
||||
#ifndef RT_CPUS_NR
|
||||
#define RT_CPUS_NR 1
|
||||
#endif
|
||||
|
||||
struct arm_gic_v3
|
||||
{
|
||||
rt_uint32_t offset; /* the first interrupt index in the vector table */
|
||||
rt_uint32_t redist_hw_base[RT_CPUS_NR]; /* the pointer of the gic redistributor */
|
||||
rt_uint32_t dist_hw_base; /* the base address of the gic distributor */
|
||||
rt_uint32_t cpu_hw_base[RT_CPUS_NR]; /* the base addrees of the gic cpu interface */
|
||||
};
|
||||
|
||||
/* 'ARM_GIC_MAX_NR' is the number of cores */
|
||||
static struct arm_gic_v3 _gic_table[ARM_GIC_MAX_NR];
|
||||
static unsigned int _gic_max_irq;
|
||||
|
||||
/**
|
||||
* @name: arm_gic_cpumask_to_affval
|
||||
* @msg:
|
||||
* @in param cpu_mask:
|
||||
* @out param cluster_id: aff1 [0:7],aff2 [8:15],aff3 [16:23]
|
||||
* @out param target_list: Target List. The set of PEs for which SGI interrupts will be generated. Each bit corresponds to the
|
||||
* PE within a cluster with an Affinity 0 value equal to the bit number.
|
||||
* @return {rt_uint32_t} 0 is finish , 1 is data valid
|
||||
*/
|
||||
RT_WEAK rt_uint32_t arm_gic_cpumask_to_affval(rt_uint32_t *cpu_mask, rt_uint32_t *cluster_id, rt_uint32_t *target_list)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
RT_WEAK rt_uint64_t get_main_cpu_affval(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int arm_gic_get_active_irq(rt_uint32_t index)
|
||||
{
|
||||
int irq;
|
||||
|
||||
RT_ASSERT(index < ARM_GIC_MAX_NR);
|
||||
|
||||
__get_gicv3_reg(ICC_IAR1, irq);
|
||||
|
||||
irq = (irq & 0x1FFFFFF) + _gic_table[index].offset;
|
||||
return irq;
|
||||
}
|
||||
|
||||
void arm_gic_ack(rt_uint32_t index, int irq)
|
||||
{
|
||||
RT_ASSERT(index < ARM_GIC_MAX_NR);
|
||||
RT_ASSERT(irq >= 0U);
|
||||
|
||||
__asm__ volatile("dsb 0xF" ::
|
||||
: "memory");
|
||||
__set_gicv3_reg(ICC_EOIR1, irq);
|
||||
}
|
||||
|
||||
void arm_gic_mask(rt_uint32_t index, int irq)
|
||||
{
|
||||
rt_uint32_t mask = 1U << (irq % 32U);
|
||||
|
||||
RT_ASSERT(index < ARM_GIC_MAX_NR);
|
||||
|
||||
irq = irq - _gic_table[index].offset;
|
||||
RT_ASSERT(irq >= 0U);
|
||||
|
||||
if (irq < 32U)
|
||||
{
|
||||
rt_int32_t cpu_id = rt_hw_cpu_id();
|
||||
RT_ASSERT((cpu_id) < RT_CPUS_NR);
|
||||
GIC_RDISTSGI_ICENABLER0(_gic_table[index].redist_hw_base[cpu_id]) = mask;
|
||||
}
|
||||
else
|
||||
{
|
||||
GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
|
||||
}
|
||||
}
|
||||
|
||||
void arm_gic_umask(rt_uint32_t index, int irq)
|
||||
{
|
||||
rt_uint32_t mask = 1U << (irq % 32U);
|
||||
|
||||
RT_ASSERT(index < ARM_GIC_MAX_NR);
|
||||
|
||||
irq = irq - _gic_table[index].offset;
|
||||
RT_ASSERT(irq >= 0U);
|
||||
|
||||
if (irq < 32U)
|
||||
{
|
||||
rt_int32_t cpu_id = rt_hw_cpu_id();
|
||||
RT_ASSERT((cpu_id) < RT_CPUS_NR);
|
||||
GIC_RDISTSGI_ISENABLER0(_gic_table[index].redist_hw_base[cpu_id]) = mask;
|
||||
}
|
||||
else
|
||||
{
|
||||
GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask;
|
||||
}
|
||||
}
|
||||
|
||||
rt_uint32_t arm_gic_get_pending_irq(rt_uint32_t index, int irq)
|
||||
{
|
||||
rt_uint32_t pend;
|
||||
|
||||
RT_ASSERT(index < ARM_GIC_MAX_NR);
|
||||
|
||||
irq = irq - _gic_table[index].offset;
|
||||
RT_ASSERT(irq >= 0U);
|
||||
|
||||
if (irq >= 16U)
|
||||
{
|
||||
pend = (GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* INTID 0-15 Software Generated Interrupt */
|
||||
pend = (GIC_DIST_SPENDSGI(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL;
|
||||
/* No CPU identification offered */
|
||||
if (pend != 0U)
|
||||
{
|
||||
pend = 1U;
|
||||
}
|
||||
else
|
||||
{
|
||||
pend = 0U;
|
||||
}
|
||||
}
|
||||
|
||||
return (pend);
|
||||
}
|
||||
|
||||
void arm_gic_set_pending_irq(rt_uint32_t index, int irq)
|
||||
{
|
||||
RT_ASSERT(index < ARM_GIC_MAX_NR);
|
||||
|
||||
irq = irq - _gic_table[index].offset;
|
||||
RT_ASSERT(irq >= 0U);
|
||||
|
||||
if (irq >= 16U)
|
||||
{
|
||||
GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) = 1U << (irq % 32U);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* INTID 0-15 Software Generated Interrupt */
|
||||
/* Forward the interrupt to the CPU interface that requested it */
|
||||
GIC_DIST_SOFTINT(_gic_table[index].dist_hw_base) = (irq | 0x02000000U);
|
||||
}
|
||||
}
|
||||
|
||||
void arm_gic_clear_pending_irq(rt_uint32_t index, int irq)
|
||||
{
|
||||
rt_uint32_t mask;
|
||||
|
||||
RT_ASSERT(index < ARM_GIC_MAX_NR);
|
||||
|
||||
irq = irq - _gic_table[index].offset;
|
||||
RT_ASSERT(irq >= 0U);
|
||||
|
||||
if (irq >= 16U)
|
||||
{
|
||||
mask = 1U << (irq % 32U);
|
||||
GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
|
||||
}
|
||||
else
|
||||
{
|
||||
mask = 1U << ((irq % 4U) * 8U);
|
||||
GIC_DIST_CPENDSGI(_gic_table[index].dist_hw_base, irq) = mask;
|
||||
}
|
||||
}
|
||||
|
||||
void arm_gic_set_configuration(rt_uint32_t index, int irq, uint32_t config)
|
||||
{
|
||||
rt_uint32_t icfgr;
|
||||
rt_uint32_t shift;
|
||||
|
||||
RT_ASSERT(index < ARM_GIC_MAX_NR);
|
||||
|
||||
irq = irq - _gic_table[index].offset;
|
||||
RT_ASSERT(irq >= 0U);
|
||||
|
||||
icfgr = GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq);
|
||||
shift = (irq % 16U) << 1U;
|
||||
|
||||
icfgr &= (~(3U << shift));
|
||||
icfgr |= (config << shift);
|
||||
|
||||
GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) = icfgr;
|
||||
}
|
||||
|
||||
rt_uint32_t arm_gic_get_configuration(rt_uint32_t index, int irq)
|
||||
{
|
||||
RT_ASSERT(index < ARM_GIC_MAX_NR);
|
||||
|
||||
irq = irq - _gic_table[index].offset;
|
||||
RT_ASSERT(irq >= 0U);
|
||||
|
||||
return (GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) >> ((irq % 16U) >> 1U));
|
||||
}
|
||||
|
||||
void arm_gic_clear_active(rt_uint32_t index, int irq)
|
||||
{
|
||||
rt_uint32_t mask = 1U << (irq % 32U);
|
||||
|
||||
RT_ASSERT(index < ARM_GIC_MAX_NR);
|
||||
|
||||
irq = irq - _gic_table[index].offset;
|
||||
RT_ASSERT(irq >= 0U);
|
||||
|
||||
GIC_DIST_ACTIVE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
|
||||
}
|
||||
|
||||
/* Set up the cpu mask for the specific interrupt */
|
||||
void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask)
|
||||
{
|
||||
rt_uint32_t old_tgt;
|
||||
|
||||
RT_ASSERT(index < ARM_GIC_MAX_NR);
|
||||
|
||||
irq = irq - _gic_table[index].offset;
|
||||
RT_ASSERT(irq >= 0U);
|
||||
|
||||
old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq);
|
||||
|
||||
old_tgt &= ~(0x0FFUL << ((irq % 4U) * 8U));
|
||||
old_tgt |= cpumask << ((irq % 4U) * 8U);
|
||||
|
||||
GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt;
|
||||
}
|
||||
|
||||
rt_uint32_t arm_gic_get_target_cpu(rt_uint32_t index, int irq)
|
||||
{
|
||||
RT_ASSERT(index < ARM_GIC_MAX_NR);
|
||||
|
||||
irq = irq - _gic_table[index].offset;
|
||||
RT_ASSERT(irq >= 0U);
|
||||
|
||||
return (GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL;
|
||||
}
|
||||
|
||||
void arm_gic_set_priority(rt_uint32_t index, int irq, rt_uint32_t priority)
|
||||
{
|
||||
rt_uint32_t mask;
|
||||
|
||||
RT_ASSERT(index < ARM_GIC_MAX_NR);
|
||||
|
||||
irq = irq - _gic_table[index].offset;
|
||||
RT_ASSERT(irq >= 0U);
|
||||
|
||||
if (irq < 32U)
|
||||
{
|
||||
rt_int32_t cpu_id = rt_hw_cpu_id();
|
||||
RT_ASSERT((cpu_id) < RT_CPUS_NR);
|
||||
|
||||
mask = GIC_RDISTSGI_IPRIORITYR(_gic_table[index].redist_hw_base[cpu_id], irq);
|
||||
mask &= ~(0xFFUL << ((irq % 4U) * 8U));
|
||||
mask |= ((priority & 0xFFUL) << ((irq % 4U) * 8U));
|
||||
GIC_RDISTSGI_IPRIORITYR(_gic_table[index].redist_hw_base[cpu_id], irq) = mask;
|
||||
}
|
||||
else
|
||||
{
|
||||
mask = GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq);
|
||||
mask &= ~(0xFFUL << ((irq % 4U) * 8U));
|
||||
mask |= ((priority & 0xFFUL) << ((irq % 4U) * 8U));
|
||||
GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) = mask;
|
||||
}
|
||||
}
|
||||
|
||||
rt_uint32_t arm_gic_get_priority(rt_uint32_t index, int irq)
|
||||
{
|
||||
RT_ASSERT(index < ARM_GIC_MAX_NR);
|
||||
|
||||
irq = irq - _gic_table[index].offset;
|
||||
RT_ASSERT(irq >= 0U);
|
||||
|
||||
if (irq < 32U)
|
||||
{
|
||||
rt_int32_t cpu_id = rt_hw_cpu_id();
|
||||
|
||||
RT_ASSERT((cpu_id) < RT_CPUS_NR);
|
||||
return (GIC_RDISTSGI_IPRIORITYR(_gic_table[index].redist_hw_base[cpu_id], irq) >> ((irq % 4U) * 8U)) & 0xFFUL;
|
||||
}
|
||||
else
|
||||
{
|
||||
return (GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL;
|
||||
}
|
||||
}
|
||||
|
||||
void arm_gic_set_system_register_enable_mask(rt_uint32_t index, rt_uint32_t value)
|
||||
{
|
||||
RT_ASSERT(index < ARM_GIC_MAX_NR);
|
||||
|
||||
value &= 0xFFUL;
|
||||
/* set priority mask */
|
||||
__set_gicv3_reg(ICC_SRE, value);
|
||||
__asm__ volatile ("isb 0xF"::
|
||||
:"memory");
|
||||
}
|
||||
|
||||
rt_uint32_t arm_gic_get_system_register_enable_mask(rt_uint32_t index)
|
||||
{
|
||||
RT_ASSERT(index < ARM_GIC_MAX_NR);
|
||||
rt_uint32_t value;
|
||||
|
||||
__get_gicv3_reg(ICC_SRE, value);
|
||||
return value;
|
||||
}
|
||||
|
||||
void arm_gic_set_interface_prior_mask(rt_uint32_t index, rt_uint32_t priority)
|
||||
{
|
||||
RT_ASSERT(index < ARM_GIC_MAX_NR);
|
||||
|
||||
priority &= 0xFFUL;
|
||||
/* set priority mask */
|
||||
__set_gicv3_reg(ICC_PMR, priority);
|
||||
}
|
||||
|
||||
rt_uint32_t arm_gic_get_interface_prior_mask(rt_uint32_t index)
|
||||
{
|
||||
RT_ASSERT(index < ARM_GIC_MAX_NR);
|
||||
rt_uint32_t priority;
|
||||
|
||||
__get_gicv3_reg(ICC_PMR, priority);
|
||||
return priority;
|
||||
}
|
||||
|
||||
void arm_gic_set_binary_point(rt_uint32_t index, rt_uint32_t binary_point)
|
||||
{
|
||||
index = index;
|
||||
binary_point &= 0x7U;
|
||||
|
||||
__set_gicv3_reg(ICC_BPR1, binary_point);
|
||||
}
|
||||
|
||||
rt_uint32_t arm_gic_get_binary_point(rt_uint32_t index)
|
||||
{
|
||||
rt_uint32_t binary_point;
|
||||
|
||||
index = index;
|
||||
__get_gicv3_reg(ICC_BPR1, binary_point);
|
||||
return binary_point;
|
||||
}
|
||||
|
||||
rt_uint32_t arm_gic_get_irq_status(rt_uint32_t index, int irq)
|
||||
{
|
||||
rt_uint32_t pending;
|
||||
rt_uint32_t active;
|
||||
|
||||
RT_ASSERT(index < ARM_GIC_MAX_NR);
|
||||
|
||||
irq = irq - _gic_table[index].offset;
|
||||
RT_ASSERT(irq >= 0U);
|
||||
|
||||
active = (GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL;
|
||||
pending = (GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL;
|
||||
|
||||
return ((active << 1U) | pending);
|
||||
}
|
||||
|
||||
void arm_gic_send_affinity_sgi(rt_uint32_t index, int irq, rt_uint32_t cpu_mask, rt_uint32_t routing_mode)
|
||||
{
|
||||
rt_uint64_t sgi_val;
|
||||
|
||||
if (routing_mode)
|
||||
{
|
||||
sgi_val = (1ULL << 40) | ((irq & 0x0FULL) << 24); //Interrupts routed to all PEs in the system, excluding "self".
|
||||
/* Write the ICC_SGI1R registers */
|
||||
__asm__ volatile("dsb 0xF" ::
|
||||
: "memory");
|
||||
__set_cp64(15, 0, sgi_val, 12);
|
||||
__asm__ volatile("isb 0xF" ::
|
||||
: "memory");
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_uint32_t cluster_id, target_list;
|
||||
while (arm_gic_cpumask_to_affval(&cpu_mask, &cluster_id, &target_list))
|
||||
{
|
||||
sgi_val = ((irq & 0x0FULL) << 24 |
|
||||
target_list |
|
||||
((cluster_id >> 8) & 0xFFULL) << GIC_RSGI_AFF1_OFFSET |
|
||||
((cluster_id >> 16) & 0xFFULL) << GIC_RSGI_AFF2_OFFSET |
|
||||
((cluster_id >> 24) & 0xFFull) << GIC_RSGI_AFF3_OFFSET);
|
||||
|
||||
__asm__ volatile("dsb 0xF" ::
|
||||
: "memory");
|
||||
__set_cp64(15, 0, sgi_val, 12);
|
||||
__asm__ volatile("isb 0xF" ::
|
||||
: "memory");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
rt_uint32_t arm_gic_get_high_pending_irq(rt_uint32_t index)
|
||||
{
|
||||
rt_uint32_t irq;
|
||||
RT_ASSERT(index < ARM_GIC_MAX_NR);
|
||||
|
||||
index = index;
|
||||
__get_gicv3_reg(ICC_HPPIR1, irq);
|
||||
return irq;
|
||||
}
|
||||
|
||||
rt_uint32_t arm_gic_get_interface_id(rt_uint32_t index)
|
||||
{
|
||||
RT_ASSERT(index < ARM_GIC_MAX_NR);
|
||||
|
||||
return GIC_CPU_IIDR(_gic_table[index].cpu_hw_base);
|
||||
}
|
||||
|
||||
void arm_gic_set_group(rt_uint32_t index, int irq, rt_uint32_t group)
|
||||
{
|
||||
uint32_t igroupr;
|
||||
uint32_t shift;
|
||||
|
||||
RT_ASSERT(index < ARM_GIC_MAX_NR);
|
||||
RT_ASSERT(group <= 1U);
|
||||
|
||||
irq = irq - _gic_table[index].offset;
|
||||
RT_ASSERT(irq >= 0U);
|
||||
|
||||
igroupr = GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq);
|
||||
shift = (irq % 32U);
|
||||
igroupr &= (~(1U << shift));
|
||||
igroupr |= ((group & 0x1U) << shift);
|
||||
|
||||
GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) = igroupr;
|
||||
}
|
||||
|
||||
rt_uint32_t arm_gic_get_group(rt_uint32_t index, int irq)
|
||||
{
|
||||
RT_ASSERT(index < ARM_GIC_MAX_NR);
|
||||
|
||||
irq = irq - _gic_table[index].offset;
|
||||
RT_ASSERT(irq >= 0U);
|
||||
|
||||
return (GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL;
|
||||
}
|
||||
|
||||
static int arm_gicv3_wait_rwp(rt_uint32_t index, rt_uint32_t irq)
|
||||
{
|
||||
rt_uint32_t rwp_bit;
|
||||
rt_uint32_t base;
|
||||
|
||||
RT_ASSERT(index < ARM_GIC_MAX_NR);
|
||||
|
||||
if (irq < 32u)
|
||||
{
|
||||
rt_int32_t cpu_id = rt_hw_cpu_id();
|
||||
|
||||
RT_ASSERT((cpu_id) < RT_CPUS_NR);
|
||||
base = _gic_table[index].redist_hw_base[cpu_id];
|
||||
rwp_bit = GICR_CTLR_RWP;
|
||||
}
|
||||
else
|
||||
{
|
||||
base = _gic_table[index].dist_hw_base;
|
||||
rwp_bit = GICD_CTLR_RWP;
|
||||
}
|
||||
|
||||
while (__REG32(base) & rwp_bit)
|
||||
{
|
||||
;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start)
|
||||
{
|
||||
rt_uint64_t cpu0_affval;
|
||||
unsigned int gic_type, i;
|
||||
|
||||
RT_ASSERT(index < ARM_GIC_MAX_NR);
|
||||
|
||||
_gic_table[index].dist_hw_base = dist_base;
|
||||
_gic_table[index].offset = irq_start;
|
||||
|
||||
/* Find out how many interrupts are supported. */
|
||||
gic_type = GIC_DIST_TYPE(dist_base);
|
||||
_gic_max_irq = ((gic_type & 0x1fU) + 1U) * 32U;
|
||||
|
||||
/*
|
||||
* The GIC only supports up to 1020 interrupt sources.
|
||||
* Limit this to either the architected maximum, or the
|
||||
* platform maximum.
|
||||
*/
|
||||
if (_gic_max_irq > 1020U)
|
||||
_gic_max_irq = 1020U;
|
||||
if (_gic_max_irq > ARM_GIC_NR_IRQS) /* the platform maximum interrupts */
|
||||
_gic_max_irq = ARM_GIC_NR_IRQS;
|
||||
|
||||
GIC_DIST_CTRL(dist_base) = 0x0U;
|
||||
/* Wait for register write pending */
|
||||
arm_gicv3_wait_rwp(0, 32);
|
||||
|
||||
/* Set all global interrupts to be level triggered, active low. */
|
||||
for (i = 32U; i < _gic_max_irq; i += 16U)
|
||||
GIC_DIST_CONFIG(dist_base, i) = 0x0U;
|
||||
|
||||
arm_gicv3_wait_rwp(0, 32);
|
||||
|
||||
cpu0_affval = get_main_cpu_affval();
|
||||
/* Set all global interrupts to this CPU only. */
|
||||
for (i = 32U; i < _gic_max_irq; i++)
|
||||
{
|
||||
GIC_DIST_IROUTER_LOW(dist_base, i) = cpu0_affval;
|
||||
GIC_DIST_IROUTER_HIGH(dist_base, i) = cpu0_affval >> 32;
|
||||
}
|
||||
|
||||
arm_gicv3_wait_rwp(0, 32);
|
||||
|
||||
/* Set priority on spi interrupts. */
|
||||
for (i = 32U; i < _gic_max_irq; i += 4U)
|
||||
GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0U;
|
||||
|
||||
arm_gicv3_wait_rwp(0, 32);
|
||||
/* Disable all interrupts. */
|
||||
for (i = 0U; i < _gic_max_irq; i += 32U)
|
||||
{
|
||||
GIC_DIST_PENDING_CLEAR(dist_base, i) = 0xffffffffU;
|
||||
GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffffU;
|
||||
}
|
||||
|
||||
arm_gicv3_wait_rwp(0, 32);
|
||||
/* All interrupts defaults to IGROUP1(IRQ). */
|
||||
for (i = 0U; i < _gic_max_irq; i += 32U)
|
||||
GIC_DIST_IGROUP(dist_base, i) = 0xffffffffU;
|
||||
|
||||
arm_gicv3_wait_rwp(0, 32);
|
||||
|
||||
/*
|
||||
The Distributor control register (GICD_CTLR) must be configured to enable the interrupt groups and to set the routing mode.
|
||||
Enable Affinity routing (ARE bits) The ARE bits in GICD_CTLR control whether affinity routing is enabled.
|
||||
If affinity routing is not enabled, GICv3 can be configured for legacy operation.
|
||||
Whether affinity routing is enabled or not can be controlled separately for Secure and Non-secure state.
|
||||
Enables GICD_CTLR contains separate enable bits for Group 0, Secure Group 1 and Non-secure Group 1:
|
||||
GICD_CTLR.EnableGrp1S enables distribution of Secure Group 1 interrupts.
|
||||
GICD_CTLR.EnableGrp1NS enables distribution of Non-secure Group 1 interrupts.
|
||||
GICD_CTLR.EnableGrp0 enables distribution of Group 0 interrupts.
|
||||
*/
|
||||
GIC_DIST_CTRL(dist_base) = GICD_CTLR_ARE_NS | GICD_CTLR_ENGRP1NS;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int arm_gic_redist_address_set(rt_uint32_t index, rt_uint32_t redist_addr, rt_uint32_t cpu_id)
|
||||
{
|
||||
RT_ASSERT(index < ARM_GIC_MAX_NR);
|
||||
RT_ASSERT((cpu_id) < RT_CPUS_NR);
|
||||
_gic_table[index].redist_hw_base[cpu_id] = redist_addr;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int arm_gic_cpu_interface_address_set(rt_uint32_t index, rt_uint32_t interface_addr, rt_uint32_t cpu_id)
|
||||
{
|
||||
RT_ASSERT(index < ARM_GIC_MAX_NR);
|
||||
RT_ASSERT((cpu_id) < RT_CPUS_NR);
|
||||
_gic_table[index].cpu_hw_base[cpu_id] = interface_addr;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int arm_gic_redist_init(rt_uint32_t index)
|
||||
{
|
||||
unsigned int i;
|
||||
rt_uint32_t base;
|
||||
rt_int32_t cpu_id = rt_hw_cpu_id();
|
||||
|
||||
RT_ASSERT(index < ARM_GIC_MAX_NR);
|
||||
RT_ASSERT((cpu_id) < RT_CPUS_NR);
|
||||
|
||||
base = _gic_table[index].redist_hw_base[cpu_id];
|
||||
/* redistributor enable */
|
||||
GIC_RDIST_WAKER(base) &= ~(1U << 1);
|
||||
while (GIC_RDIST_WAKER(base) & (1 << 2))
|
||||
{
|
||||
;
|
||||
}
|
||||
|
||||
/* Disable all sgi and ppi interrupt */
|
||||
GIC_RDISTSGI_ICENABLER0(base) = 0xFFFFFFFF;
|
||||
arm_gicv3_wait_rwp(0, 0);
|
||||
|
||||
/* Clear all inetrrupt pending */
|
||||
GIC_RDISTSGI_ICPENDR0(base) = 0xFFFFFFFF;
|
||||
|
||||
/* the corresponding interrupt is Group 1 or Non-secure Group 1. */
|
||||
GIC_RDISTSGI_IGROUPR0(base, 0) = 0xFFFFFFFF;
|
||||
GIC_RDISTSGI_IGRPMODR0(base, 0) = 0xFFFFFFFF;
|
||||
|
||||
/* Configure default priorities for SGI 0:15 and PPI 16:31. */
|
||||
for (i = 0; i < 32; i += 4)
|
||||
{
|
||||
GIC_RDISTSGI_IPRIORITYR(base, i) = 0xa0a0a0a0U;
|
||||
}
|
||||
|
||||
/* Trigger level for PPI interrupts*/
|
||||
GIC_RDISTSGI_ICFGR1(base) = 0x0U; // PPI is level-sensitive.
|
||||
return 0;
|
||||
}
|
||||
|
||||
int arm_gic_cpu_init(rt_uint32_t index)
|
||||
{
|
||||
rt_uint32_t value;
|
||||
RT_ASSERT(index < ARM_GIC_MAX_NR);
|
||||
|
||||
value = arm_gic_get_system_register_enable_mask(index);
|
||||
value |= (1U << 0);
|
||||
arm_gic_set_system_register_enable_mask(index, value);
|
||||
__set_gicv3_reg(ICC_CTLR, 0);
|
||||
|
||||
arm_gic_set_interface_prior_mask(index, 0xFFU);
|
||||
|
||||
/* Enable group1 interrupt */
|
||||
value = 0x1U;
|
||||
__set_gicv3_reg(ICC_IGRPEN1, value);
|
||||
|
||||
arm_gic_set_binary_point(0, 0);
|
||||
|
||||
/* ICC_BPR0_EL1 determines the preemption group for both
|
||||
Group 0 and Group 1 interrupts.
|
||||
*/
|
||||
value = 0x1U;
|
||||
__set_gicv3_reg(ICC_CTLR, value);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef RT_USING_SMP
|
||||
void arm_gic_secondary_cpu_init(void)
|
||||
{
|
||||
arm_gic_redist_init(0);
|
||||
|
||||
arm_gic_cpu_init(0);
|
||||
}
|
||||
#endif
|
||||
|
||||
void arm_gic_dump_type(rt_uint32_t index)
|
||||
{
|
||||
unsigned int gic_type;
|
||||
|
||||
gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base);
|
||||
rt_kprintf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\n",
|
||||
(GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4U) & 0xfUL,
|
||||
_gic_table[index].dist_hw_base,
|
||||
_gic_max_irq,
|
||||
gic_type & (1U << 10U) ? "has" : "no",
|
||||
gic_type);
|
||||
}
|
||||
|
||||
void arm_gic_dump(rt_uint32_t index)
|
||||
{
|
||||
unsigned int i, k;
|
||||
|
||||
k = arm_gic_get_high_pending_irq(0);
|
||||
rt_kprintf("--- high pending priority: %d(%08x)\n", k, k);
|
||||
rt_kprintf("--- hw mask ---\n");
|
||||
for (i = 0U; i < _gic_max_irq / 32U; i++)
|
||||
{
|
||||
rt_kprintf("0x%08x, ",
|
||||
GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base,
|
||||
i * 32U));
|
||||
}
|
||||
rt_kprintf("\n--- hw pending ---\n");
|
||||
for (i = 0U; i < _gic_max_irq / 32U; i++)
|
||||
{
|
||||
rt_kprintf("0x%08x, ",
|
||||
GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base,
|
||||
i * 32U));
|
||||
}
|
||||
rt_kprintf("\n--- hw active ---\n");
|
||||
for (i = 0U; i < _gic_max_irq / 32U; i++)
|
||||
{
|
||||
rt_kprintf("0x%08x, ",
|
||||
GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base,
|
||||
i * 32U));
|
||||
}
|
||||
rt_kprintf("\n");
|
||||
}
|
||||
|
||||
long gic_dump(void)
|
||||
{
|
||||
arm_gic_dump_type(0);
|
||||
arm_gic_dump(0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
MSH_CMD_EXPORT(gic_dump, show gic status);
|
||||
|
|
@ -0,0 +1,194 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2013-07-20 Bernard first version
|
||||
*/
|
||||
|
||||
#ifndef __GIC_V3_H__
|
||||
#define __GIC_V3_H__
|
||||
|
||||
#include <rthw.h>
|
||||
#include <board.h>
|
||||
|
||||
#define __get_gicv3_reg(CR, Rt) __asm__ volatile("MRC " CR \
|
||||
: "=r"(Rt) \
|
||||
: \
|
||||
: "memory")
|
||||
#define __set_gicv3_reg(CR, Rt) __asm__ volatile("MCR " CR \
|
||||
: \
|
||||
: "r"(Rt) \
|
||||
: "memory")
|
||||
|
||||
|
||||
/* AArch32 System register interface to GICv3 */
|
||||
#define ICC_IAR0 "p15, 0, %0, c12, c8, 0"
|
||||
#define ICC_IAR1 "p15, 0, %0, c12, c12, 0"
|
||||
#define ICC_EOIR0 "p15, 0, %0, c12, c8, 1"
|
||||
#define ICC_EOIR1 "p15, 0, %0, c12, c12, 1"
|
||||
#define ICC_HPPIR0 "p15, 0, %0, c12, c8, 2"
|
||||
#define ICC_HPPIR1 "p15, 0, %0, c12, c12, 2"
|
||||
#define ICC_BPR0 "p15, 0, %0, c12, c8, 3"
|
||||
#define ICC_BPR1 "p15, 0, %0, c12, c12, 3"
|
||||
#define ICC_DIR "p15, 0, %0, c12, c11, 1"
|
||||
#define ICC_PMR "p15, 0, %0, c4, c6, 0"
|
||||
#define ICC_RPR "p15, 0, %0, c12, c11, 3"
|
||||
#define ICC_CTLR "p15, 0, %0, c12, c12, 4"
|
||||
#define ICC_MCTLR "p15, 6, %0, c12, c12, 4"
|
||||
#define ICC_SRE "p15, 0, %0, c12, c12, 5"
|
||||
#define ICC_HSRE "p15, 4, %0, c12, c9, 5"
|
||||
#define ICC_MSRE "p15, 6, %0, c12, c12, 5"
|
||||
#define ICC_IGRPEN0 "p15, 0, %0, c12, c12, 6"
|
||||
#define ICC_IGRPEN1 "p15, 0, %0, c12, c12, 7"
|
||||
#define ICC_MGRPEN1 "p15, 6, %0, c12, c12, 7"
|
||||
|
||||
#define __REG32(x) (*((volatile unsigned int*)((rt_uint32_t)x)))
|
||||
|
||||
#define ROUTED_TO_ALL (1)
|
||||
#define ROUTED_TO_SPEC (0)
|
||||
|
||||
/** Macro to access the Distributor Control Register (GICD_CTLR)
|
||||
*/
|
||||
#define GICD_CTLR_RWP (1<<31)
|
||||
#define GICD_CTLR_E1NWF (1<<7)
|
||||
#define GICD_CTLR_DS (1<<6)
|
||||
#define GICD_CTLR_ARE_NS (1<<5)
|
||||
#define GICD_CTLR_ARE_S (1<<4)
|
||||
#define GICD_CTLR_ENGRP1S (1<<2)
|
||||
#define GICD_CTLR_ENGRP1NS (1<<1)
|
||||
#define GICD_CTLR_ENGRP0 (1<<0)
|
||||
|
||||
/** Macro to access the Redistributor Control Register (GICR_CTLR)
|
||||
*/
|
||||
#define GICR_CTLR_UWP (1<<31)
|
||||
#define GICR_CTLR_DPG1S (1<<26)
|
||||
#define GICR_CTLR_DPG1NS (1<<25)
|
||||
#define GICR_CTLR_DPG0 (1<<24)
|
||||
#define GICR_CTLR_RWP (1<<3)
|
||||
#define GICR_CTLR_IR (1<<2)
|
||||
#define GICR_CTLR_CES (1<<1)
|
||||
#define GICR_CTLR_EnableLPI (1<<0)
|
||||
|
||||
/** Macro to access the Generic Interrupt Controller Interface (GICC)
|
||||
*/
|
||||
#define GIC_CPU_CTRL(hw_base) __REG32((hw_base) + 0x00U)
|
||||
#define GIC_CPU_PRIMASK(hw_base) __REG32((hw_base) + 0x04U)
|
||||
#define GIC_CPU_BINPOINT(hw_base) __REG32((hw_base) + 0x08U)
|
||||
#define GIC_CPU_INTACK(hw_base) __REG32((hw_base) + 0x0cU)
|
||||
#define GIC_CPU_EOI(hw_base) __REG32((hw_base) + 0x10U)
|
||||
#define GIC_CPU_RUNNINGPRI(hw_base) __REG32((hw_base) + 0x14U)
|
||||
#define GIC_CPU_HIGHPRI(hw_base) __REG32((hw_base) + 0x18U)
|
||||
#define GIC_CPU_IIDR(hw_base) __REG32((hw_base) + 0xFCU)
|
||||
|
||||
/** Macro to access the Generic Interrupt Controller Distributor (GICD)
|
||||
*/
|
||||
#define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000U)
|
||||
#define GIC_DIST_TYPE(hw_base) __REG32((hw_base) + 0x004U)
|
||||
#define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080U + ((n)/32U) * 4U)
|
||||
#define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100U + ((n)/32U) * 4U)
|
||||
#define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180U + ((n)/32U) * 4U)
|
||||
#define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200U + ((n)/32U) * 4U)
|
||||
#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280U + ((n)/32U) * 4U)
|
||||
#define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300U + ((n)/32U) * 4U)
|
||||
#define GIC_DIST_ACTIVE_CLEAR(hw_base, n) __REG32((hw_base) + 0x380U + ((n)/32U) * 4U)
|
||||
#define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400U + ((n)/4U) * 4U)
|
||||
#define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800U + ((n)/4U) * 4U)
|
||||
#define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00U + ((n)/16U) * 4U)
|
||||
#define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00U)
|
||||
#define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10U + ((n)/4U) * 4U)
|
||||
#define GIC_DIST_SPENDSGI(hw_base, n) __REG32((hw_base) + 0xf20U + ((n)/4U) * 4U)
|
||||
#define GIC_DIST_ICPIDR2(hw_base) __REG32((hw_base) + 0xfe8U)
|
||||
#define GIC_DIST_IROUTER_LOW(hw_base, n) __REG32((hw_base) + 0x6000U + (n)*8U)
|
||||
#define GIC_DIST_IROUTER_HIGH(hw_base, n) __REG32((hw_base) + 0x6000U + (n)*8U + 4)
|
||||
|
||||
/* SGI base address is at 64K offset from Redistributor base address */
|
||||
#define GIC_RSGI_OFFSET 0x10000
|
||||
|
||||
/** Macro to access the Generic Interrupt Controller Redistributor (GICD)
|
||||
*/
|
||||
#define GIC_RDIST_CTRL(hw_base) __REG32((hw_base) + 0x000U)
|
||||
#define GIC_RDIST_IIDR(hw_base) __REG32((hw_base) + 0x004U)
|
||||
#define GIC_RDIST_TYPER(hw_base) __REG32((hw_base) + 0x008U)
|
||||
#define GIC_RDIST_TSTATUSR(hw_base) __REG32((hw_base) + 0x010U)
|
||||
#define GIC_RDIST_WAKER(hw_base) __REG32((hw_base) + 0x014U)
|
||||
#define GIC_RDIST_SETLPIR(hw_base) __REG32((hw_base) + 0x040U)
|
||||
#define GIC_RDIST_CLRLPIR(hw_base) __REG32((hw_base) + 0x048U)
|
||||
#define GIC_RDIST_PROPBASER(hw_base) __REG32((hw_base) + 0x070U)
|
||||
#define GIC_RDIST_PENDBASER(hw_base) __REG32((hw_base) + 0x078U)
|
||||
#define GIC_RDIST_INVLPIR(hw_base) __REG32((hw_base) + 0x0A0U)
|
||||
#define GIC_RDIST_INVALLR(hw_base) __REG32((hw_base) + 0x0B0U)
|
||||
#define GIC_RDIST_SYNCR(hw_base) __REG32((hw_base) + 0x0C0U)
|
||||
|
||||
#define GIC_RDISTSGI_IGROUPR0(hw_base, n) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x080U + (n)*4U)
|
||||
#define GIC_RDISTSGI_ISENABLER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x100U)
|
||||
#define GIC_RDISTSGI_ICENABLER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x180U)
|
||||
#define GIC_RDISTSGI_ISPENDR0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x200U)
|
||||
#define GIC_RDISTSGI_ICPENDR0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x280U)
|
||||
#define GIC_RDISTSGI_ISACTIVER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x300U)
|
||||
#define GIC_RDISTSGI_ICACTIVER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x380U)
|
||||
#define GIC_RDISTSGI_IPRIORITYR(hw_base, n) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x400U + ((n) / 4U) * 4U)
|
||||
#define GIC_RDISTSGI_ICFGR0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xC00U)
|
||||
#define GIC_RDISTSGI_ICFGR1(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xC04U)
|
||||
#define GIC_RDISTSGI_IGRPMODR0(hw_base, n) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xD00U + (n)*4)
|
||||
#define GIC_RDISTSGI_NSACR(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xE00U)
|
||||
|
||||
#define GIC_RSGI_AFF1_OFFSET 16
|
||||
#define GIC_RSGI_AFF2_OFFSET 32
|
||||
#define GIC_RSGI_AFF3_OFFSET 48
|
||||
|
||||
rt_uint32_t arm_gic_cpumask_to_affval(rt_uint32_t *cpu_mask, rt_uint32_t *cluster_id, rt_uint32_t *target_list);
|
||||
rt_uint64_t get_main_cpu_affval(void);
|
||||
int arm_gic_get_active_irq(rt_uint32_t index);
|
||||
void arm_gic_ack(rt_uint32_t index, int irq);
|
||||
|
||||
void arm_gic_mask(rt_uint32_t index, int irq);
|
||||
void arm_gic_umask(rt_uint32_t index, int irq);
|
||||
|
||||
rt_uint32_t arm_gic_get_pending_irq(rt_uint32_t index, int irq);
|
||||
void arm_gic_set_pending_irq(rt_uint32_t index, int irq);
|
||||
void arm_gic_clear_pending_irq(rt_uint32_t index, int irq);
|
||||
|
||||
void arm_gic_set_configuration(rt_uint32_t index, int irq, uint32_t config);
|
||||
rt_uint32_t arm_gic_get_configuration(rt_uint32_t index, int irq);
|
||||
|
||||
void arm_gic_clear_active(rt_uint32_t index, int irq);
|
||||
|
||||
void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask);
|
||||
rt_uint32_t arm_gic_get_target_cpu(rt_uint32_t index, int irq);
|
||||
|
||||
void arm_gic_set_priority(rt_uint32_t index, int irq, rt_uint32_t priority);
|
||||
rt_uint32_t arm_gic_get_priority(rt_uint32_t index, int irq);
|
||||
|
||||
void arm_gic_set_interface_prior_mask(rt_uint32_t index, rt_uint32_t priority);
|
||||
rt_uint32_t arm_gic_get_interface_prior_mask(rt_uint32_t index);
|
||||
|
||||
void arm_gic_set_binary_point(rt_uint32_t index, rt_uint32_t binary_point);
|
||||
rt_uint32_t arm_gic_get_binary_point(rt_uint32_t index);
|
||||
|
||||
rt_uint32_t arm_gic_get_irq_status(rt_uint32_t index, int irq);
|
||||
|
||||
void arm_gic_send_affinity_sgi(rt_uint32_t index, int irq, rt_uint32_t cpu_mask, rt_uint32_t routing_mode);
|
||||
rt_uint32_t arm_gic_get_high_pending_irq(rt_uint32_t index);
|
||||
|
||||
rt_uint32_t arm_gic_get_interface_id(rt_uint32_t index);
|
||||
|
||||
void arm_gic_set_group(rt_uint32_t index, int irq, rt_uint32_t group);
|
||||
rt_uint32_t arm_gic_get_group(rt_uint32_t index, int irq);
|
||||
|
||||
int arm_gic_redist_address_set(rt_uint32_t index, rt_uint32_t redist_addr, rt_uint32_t cpu_id);
|
||||
int arm_gic_cpu_interface_address_set(rt_uint32_t index, rt_uint32_t interface_addr, rt_uint32_t cpu_id);
|
||||
int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start);
|
||||
int arm_gic_cpu_init(rt_uint32_t index);
|
||||
int arm_gic_redist_init(rt_uint32_t index);
|
||||
|
||||
void arm_gic_dump_type(rt_uint32_t index);
|
||||
void arm_gic_dump(rt_uint32_t index);
|
||||
|
||||
void arm_gic_set_system_register_enable_mask(rt_uint32_t index, rt_uint32_t value);
|
||||
rt_uint32_t arm_gic_get_system_register_enable_mask(rt_uint32_t index);
|
||||
void arm_gic_secondary_cpu_init(void);
|
||||
#endif
|
||||
|
||||
|
|
@ -110,6 +110,14 @@ void gtimer_set_counter_frequency(rt_uint32_t value)
|
|||
__asm__ volatile ("isb 0xF":::"memory");
|
||||
}
|
||||
|
||||
/** Get the frequency the timer shall run at.
|
||||
* return timer frequency in Hz.
|
||||
*/
|
||||
rt_uint32_t gtimer_get_counter_frequency(void)
|
||||
{
|
||||
return(__get_cntfrq());
|
||||
}
|
||||
|
||||
/** Sets the reset value of the timer.
|
||||
* param value: The value the timer is loaded with.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -14,6 +14,7 @@
|
|||
#include <rtdef.h>
|
||||
|
||||
void gtimer_set_counter_frequency(rt_uint32_t value);
|
||||
rt_uint32_t gtimer_get_counter_frequency(void);
|
||||
void gtimer_set_load_value(rt_uint32_t value);
|
||||
rt_uint32_t gtimer_get_current_value(void);
|
||||
rt_uint64_t gtimer_get_current_physical_value(void);
|
||||
|
|
|
|||
|
|
@ -12,8 +12,12 @@
|
|||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include "interrupt.h"
|
||||
#include "gic.h"
|
||||
|
||||
#ifdef RT_USING_GIC_V2
|
||||
#include "gic.h"
|
||||
#else
|
||||
#include "gicv3.h"
|
||||
#endif
|
||||
|
||||
/* exception and interrupt handler table */
|
||||
struct rt_irq_desc isr_table[MAX_HANDLERS];
|
||||
|
|
@ -34,6 +38,7 @@ void rt_hw_vector_init(void)
|
|||
rt_cpu_vector_set_base((unsigned int)&system_vectors);
|
||||
}
|
||||
|
||||
#ifdef RT_USING_GIC_V2
|
||||
/**
|
||||
* This function will initialize hardware interrupt
|
||||
*/
|
||||
|
|
@ -58,6 +63,33 @@ void rt_hw_interrupt_init(void)
|
|||
arm_gic_dist_init(0, gic_dist_base, gic_irq_start);
|
||||
arm_gic_cpu_init(0, gic_cpu_base);
|
||||
}
|
||||
#else
|
||||
/**
|
||||
* This function will initialize hardware interrupt
|
||||
* Called by the primary cpu(cpu0)
|
||||
*/
|
||||
void rt_hw_interrupt_init(void)
|
||||
{
|
||||
rt_uint32_t gic_dist_base;
|
||||
rt_uint32_t gic_irq_start;
|
||||
|
||||
/* initialize vector table */
|
||||
rt_hw_vector_init();
|
||||
|
||||
/* initialize exceptions table */
|
||||
rt_memset(isr_table, 0x00, sizeof(isr_table));
|
||||
|
||||
/* initialize ARM GIC */
|
||||
gic_dist_base = platform_get_gic_dist_base();
|
||||
gic_irq_start = GIC_IRQ_START;
|
||||
|
||||
arm_gic_dist_init(0, gic_dist_base, gic_irq_start);
|
||||
|
||||
arm_gic_cpu_init(0);
|
||||
arm_gic_redist_init(0);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* This function will mask a interrupt.
|
||||
|
|
@ -245,7 +277,7 @@ unsigned int rt_hw_interrupt_get_prior_group_bits(void)
|
|||
* @param old_handler the old interrupt service routine
|
||||
*/
|
||||
rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
|
||||
void *param, const char *name)
|
||||
void *param, const char *name)
|
||||
{
|
||||
rt_isr_handler_t old_handler = RT_NULL;
|
||||
|
||||
|
|
@ -269,7 +301,11 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
|
|||
#ifdef RT_USING_SMP
|
||||
void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask)
|
||||
{
|
||||
#ifdef RT_USING_GIC_V2
|
||||
arm_gic_send_sgi(0, ipi_vector, cpu_mask, 0);
|
||||
#else
|
||||
arm_gic_send_affinity_sgi(0, ipi_vector, cpu_mask, ROUTED_TO_SPEC);
|
||||
#endif
|
||||
}
|
||||
|
||||
void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler)
|
||||
|
|
|
|||
|
|
@ -22,20 +22,26 @@
|
|||
.equ I_Bit, 0x80 @ when I bit is set, IRQ is disabled
|
||||
.equ F_Bit, 0x40 @ when F bit is set, FIQ is disabled
|
||||
|
||||
#ifdef RT_USING_FPU
|
||||
.equ UND_Stack_Size, 0x00000400
|
||||
#else
|
||||
.equ UND_Stack_Size, 0x00000000
|
||||
#endif
|
||||
.equ SVC_Stack_Size, 0x00000400
|
||||
.equ ABT_Stack_Size, 0x00000000
|
||||
.equ ABT_Stack_Size, 0x00000400
|
||||
.equ RT_FIQ_STACK_PGSZ, 0x00000000
|
||||
.equ RT_IRQ_STACK_PGSZ, 0x00000800
|
||||
.equ USR_Stack_Size, 0x00000400
|
||||
|
||||
.equ SUB_UND_Stack_Size, 0x00000400
|
||||
.equ SUB_SVC_Stack_Size, 0x00000400
|
||||
.equ SUB_ABT_Stack_Size, 0x00000400
|
||||
.equ SUB_RT_FIQ_STACK_PGSZ, 0x00000000
|
||||
.equ SUB_RT_IRQ_STACK_PGSZ, 0x00000400
|
||||
.equ SUB_USR_Stack_Size, 0x00000400
|
||||
|
||||
#define ISR_Stack_Size (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
|
||||
RT_FIQ_STACK_PGSZ + RT_IRQ_STACK_PGSZ)
|
||||
|
||||
#define SUB_ISR_Stack_Size (SUB_UND_Stack_Size + SUB_SVC_Stack_Size + SUB_ABT_Stack_Size + \
|
||||
SUB_RT_FIQ_STACK_PGSZ + SUB_RT_IRQ_STACK_PGSZ)
|
||||
|
||||
.section .data.share.isr
|
||||
/* stack */
|
||||
.globl stack_start
|
||||
|
|
@ -82,9 +88,40 @@ continue:
|
|||
|
||||
/* disable the data alignment check */
|
||||
mrc p15, 0, r1, c1, c0, 0
|
||||
bic r1, #(1<<1)
|
||||
bic r1, #(1<<0) /* Disable MMU */
|
||||
bic r1, #(1<<1) /* Disable Alignment fault checking */
|
||||
bic r1, #(1<<2) /* Disable data cache */
|
||||
bic r1, #(1<<11) /* Disable program flow prediction */
|
||||
bic r1, #(1<<12) /* Disable instruction cache */
|
||||
bic r1, #(3<<19) /* bit[20:19] must be zero */
|
||||
mcr p15, 0, r1, c1, c0, 0
|
||||
|
||||
@ get cpu id, and subtract the offset from the stacks base address
|
||||
bl rt_hw_cpu_id
|
||||
mov r5, r0
|
||||
|
||||
cmp r5, #0 @ cpu id == 0
|
||||
beq normal_setup
|
||||
|
||||
@ cpu id > 0, stop or wait
|
||||
#ifdef RT_SMP_AUTO_BOOT
|
||||
ldr r0, =secondary_cpu_entry
|
||||
mov r1, #0
|
||||
str r1, [r0] /* clean secondary_cpu_entry */
|
||||
#endif /* RT_SMP_AUTO_BOOT */
|
||||
|
||||
secondary_loop:
|
||||
@ cpu core 1 goes into sleep until core 0 wakeup it
|
||||
wfe
|
||||
#ifdef RT_SMP_AUTO_BOOT
|
||||
ldr r1, =secondary_cpu_entry
|
||||
ldr r0, [r1]
|
||||
cmp r0, #0
|
||||
blxne r0 /* if(secondary_cpu_entry) secondary_cpu_entry(); */
|
||||
#endif /* RT_SMP_AUTO_BOOT */
|
||||
b secondary_loop
|
||||
|
||||
normal_setup:
|
||||
/* setup stack */
|
||||
bl stack_setup
|
||||
|
||||
|
|
@ -105,6 +142,11 @@ bss_loop:
|
|||
mcr p15, 0, r1, c1, c0, 1 //enable smp
|
||||
#endif
|
||||
|
||||
/* enable branch prediction */
|
||||
mrc p15, 0, r0, c1, c0, 0
|
||||
orr r0, r0, #(1<<11)
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
|
||||
/* initialize the mmu table and enable mmu */
|
||||
ldr r0, =platform_mem_desc
|
||||
ldr r1, =platform_mem_desc_size
|
||||
|
|
@ -137,6 +179,7 @@ stack_setup:
|
|||
|
||||
@ Set the startup stack for svc
|
||||
mov sp, r0
|
||||
sub r0, r0, #SVC_Stack_Size
|
||||
|
||||
@ Enter Undefined Instruction Mode and set its Stack Pointer
|
||||
msr cpsr_c, #Mode_UND|I_Bit|F_Bit
|
||||
|
|
@ -378,16 +421,6 @@ vector_resv:
|
|||
b .
|
||||
|
||||
#ifdef RT_USING_SMP
|
||||
.global set_secondary_cpu_boot_address
|
||||
set_secondary_cpu_boot_address:
|
||||
ldr r0, =secondary_cpu_start
|
||||
|
||||
mvn r1, #0 //0xffffffff
|
||||
ldr r2, =0x10000034
|
||||
str r1, [r2]
|
||||
str r0, [r2, #-4]
|
||||
mov pc, lr
|
||||
|
||||
.global secondary_cpu_start
|
||||
secondary_cpu_start:
|
||||
|
||||
|
|
@ -405,38 +438,52 @@ secondary_cpu_start:
|
|||
bic r0, #(1<<13)
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
|
||||
#ifdef RT_USING_FPU
|
||||
cps #Mode_UND
|
||||
ldr sp, =und_stack_2_limit
|
||||
#endif
|
||||
/* enable branch prediction */
|
||||
mrc p15, 0, r0, c1, c0, 0
|
||||
orr r0, r0, #(1<<11)
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
|
||||
cps #Mode_IRQ
|
||||
ldr sp, =irq_stack_2_limit
|
||||
@ get cpu id, and subtract the offset from the stacks base address
|
||||
bl rt_hw_cpu_id
|
||||
sub r5, r0, #1
|
||||
|
||||
cps #Mode_FIQ
|
||||
ldr sp, =irq_stack_2_limit
|
||||
ldr r0, =SUB_ISR_Stack_Size
|
||||
mul r0, r0, r5 @r0 = SUB_ISR_Stack_Size * (cpuid - 1)
|
||||
ldr r1, =sub_stack_top
|
||||
sub r0, r1, r0 @r0 = sub_stack_top - (SUB_ISR_Stack_Size * (cpuid - 1))
|
||||
|
||||
cps #Mode_SVC
|
||||
mov sp, r0
|
||||
sub r0, r0, #SUB_SVC_Stack_Size
|
||||
|
||||
cps #Mode_UND
|
||||
mov sp, r0
|
||||
sub r0, r0, #SUB_UND_Stack_Size
|
||||
|
||||
cps #Mode_ABT
|
||||
mov sp, r0
|
||||
sub r0, r0, #SUB_ABT_Stack_Size
|
||||
|
||||
cps #Mode_FIQ
|
||||
mov sp, r0
|
||||
sub r0, r0, #SUB_RT_FIQ_STACK_PGSZ
|
||||
|
||||
cps #Mode_IRQ
|
||||
mov sp, r0
|
||||
sub r0, r0, #SUB_RT_IRQ_STACK_PGSZ
|
||||
|
||||
cps #Mode_SVC
|
||||
ldr sp, =svc_stack_2_limit
|
||||
|
||||
/* initialize the mmu table and enable mmu */
|
||||
bl rt_hw_mmu_init
|
||||
|
||||
b secondary_cpu_c_start
|
||||
#endif
|
||||
|
||||
.bss
|
||||
.align 2 //align to 2~2=4
|
||||
svc_stack_2:
|
||||
.space (1 << 10)
|
||||
svc_stack_2_limit:
|
||||
|
||||
irq_stack_2:
|
||||
.space (1 << 10)
|
||||
irq_stack_2_limit:
|
||||
sub_stack_start:
|
||||
.space (SUB_ISR_Stack_Size * (RT_CPUS_NR-1))
|
||||
sub_stack_top:
|
||||
|
||||
#ifdef RT_USING_FPU
|
||||
und_stack_2:
|
||||
.space (1 << 10)
|
||||
und_stack_2_limit:
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue