From d6f5fbcd5b4418c9762b957e9489b5dadb7bd13b Mon Sep 17 00:00:00 2001
From: bigmagic123 <57786250+bigmagic123@users.noreply.github.com>
Date: Fri, 21 May 2021 18:39:41 +0800
Subject: [PATCH] format code
---
bsp/qemu-riscv-virt64/driver/board.c | 4 +-
bsp/qemu-riscv-virt64/driver/board.h | 2 +-
bsp/qemu-riscv-virt64/driver/drv_uart.c | 6 +--
bsp/qemu-riscv-virt64/driver/io.h | 2 +-
bsp/qemu-riscv-virt64/driver/plic.c | 36 +++++++++---------
bsp/qemu-riscv-virt64/driver/plic.h | 4 +-
libcpu/risc-v/virt64/context_gcc.S | 1 -
libcpu/risc-v/virt64/cpuport.c | 6 +--
libcpu/risc-v/virt64/cpuport.h | 2 +-
libcpu/risc-v/virt64/interrupt.c | 4 +-
libcpu/risc-v/virt64/interrupt.h | 2 +-
libcpu/risc-v/virt64/riscv.h | 2 +-
libcpu/risc-v/virt64/riscv_io.h | 50 ++++++++++++-------------
libcpu/risc-v/virt64/stackframe.h | 2 +-
libcpu/risc-v/virt64/tick.c | 10 ++---
libcpu/risc-v/virt64/tick.h | 2 +-
16 files changed, 65 insertions(+), 70 deletions(-)
diff --git a/bsp/qemu-riscv-virt64/driver/board.c b/bsp/qemu-riscv-virt64/driver/board.c
index 1e567ea151..91e8f25982 100644
--- a/bsp/qemu-riscv-virt64/driver/board.c
+++ b/bsp/qemu-riscv-virt64/driver/board.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -55,7 +55,7 @@ void rt_hw_board_init(void)
#endif /* RT_USING_CONSOLE */
rt_hw_tick_init();
rt_kprintf("heap: [0x%08x - 0x%08x]\n", (rt_ubase_t) RT_HW_HEAP_BEGIN, (rt_ubase_t) RT_HW_HEAP_END);
-
+
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
diff --git a/bsp/qemu-riscv-virt64/driver/board.h b/bsp/qemu-riscv-virt64/driver/board.h
index 3193346508..3445852e40 100644
--- a/bsp/qemu-riscv-virt64/driver/board.h
+++ b/bsp/qemu-riscv-virt64/driver/board.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/bsp/qemu-riscv-virt64/driver/drv_uart.c b/bsp/qemu-riscv-virt64/driver/drv_uart.c
index f6ee2e1c7f..c84ae6df7d 100644
--- a/bsp/qemu-riscv-virt64/driver/drv_uart.c
+++ b/bsp/qemu-riscv-virt64/driver/drv_uart.c
@@ -84,7 +84,7 @@ static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg
}
static int drv_uart_putc(struct rt_serial_device *serial, char c)
-{
+{
while ((uart_read_reg(LSR) & LSR_TX_IDLE) == 0);
return uart_write_reg(THR, c);
}
@@ -143,9 +143,9 @@ int rt_hw_uart_init(void)
RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
uart);
rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, serial, "uart");
-
+
rt_hw_interrupt_umask(uart->irqno);
}
-
+
return 0;
}
diff --git a/bsp/qemu-riscv-virt64/driver/io.h b/bsp/qemu-riscv-virt64/driver/io.h
index 8915b55306..1285d5955b 100644
--- a/bsp/qemu-riscv-virt64/driver/io.h
+++ b/bsp/qemu-riscv-virt64/driver/io.h
@@ -49,4 +49,4 @@ static inline uint32_t read_reg(
return readl(addr + offset);
}
-#endif // ARCH_IO_H
\ No newline at end of file
+#endif // ARCH_IO_H
diff --git a/bsp/qemu-riscv-virt64/driver/plic.c b/bsp/qemu-riscv-virt64/driver/plic.c
index afd186933d..f502bc9da0 100644
--- a/bsp/qemu-riscv-virt64/driver/plic.c
+++ b/bsp/qemu-riscv-virt64/driver/plic.c
@@ -13,14 +13,14 @@
#include "encoding.h"
/*
-* Each PLIC interrupt source can be assigned a priority by writing
+* Each PLIC interrupt source can be assigned a priority by writing
* to its 32-bit memory-mapped priority register.
-* The QEMU-virt (the same as FU540-C000) supports 7 levels of priority.
-* A priority value of 0 is reserved to mean "never interrupt" and
-* effectively disables the interrupt.
-* Priority 1 is the lowest active priority, and priority 7 is the highest.
-* Ties between global interrupts of the same priority are broken by
-* the Interrupt ID; interrupts with the lowest ID have the highest
+* The QEMU-virt (the same as FU540-C000) supports 7 levels of priority.
+* A priority value of 0 is reserved to mean "never interrupt" and
+* effectively disables the interrupt.
+* Priority 1 is the lowest active priority, and priority 7 is the highest.
+* Ties between global interrupts of the same priority are broken by
+* the Interrupt ID; interrupts with the lowest ID have the highest
* effective priority.
*/
void plic_set_priority(int irq, int priority)
@@ -29,7 +29,7 @@ void plic_set_priority(int irq, int priority)
}
/*
-* Each global interrupt can be enabled by setting the corresponding
+* Each global interrupt can be enabled by setting the corresponding
* bit in the enables registers.
*/
void plic_irq_enable(int irq)
@@ -49,7 +49,7 @@ void plic_irq_disable(int irq)
*(uint32_t*)PLIC_ENABLE(hart) = (((*(uint32_t*)PLIC_ENABLE(hart)) & (~(1 << irq))));
}
-/*
+/*
* PLIC will mask all interrupts of a priority less than or equal to threshold.
* Maximum threshold is 7.
* For example, a threshold value of zero permits all interrupts with
@@ -62,16 +62,16 @@ void plic_set_threshold(int threshold)
*(uint32_t*)PLIC_THRESHOLD(hart) = threshold;
}
-/*
+/*
* DESCRIPTION:
* Query the PLIC what interrupt we should serve.
* Perform an interrupt claim by reading the claim register, which
- * returns the ID of the highest-priority pending interrupt or zero if there
- * is no pending interrupt.
+ * returns the ID of the highest-priority pending interrupt or zero if there
+ * is no pending interrupt.
* A successful claim also atomically clears the corresponding pending bit
* on the interrupt source.
* RETURN VALUE:
- * the ID of the highest-priority pending interrupt or zero if there
+ * the ID of the highest-priority pending interrupt or zero if there
* is no pending interrupt.
*/
int plic_claim(void)
@@ -81,12 +81,12 @@ int plic_claim(void)
return irq;
}
-/*
+/*
* DESCRIPTION:
- * Writing the interrupt ID it received from the claim (irq) to the
- * complete register would signal the PLIC we've served this IRQ.
- * The PLIC does not check whether the completion ID is the same as the
- * last claim ID for that target. If the completion ID does not match an
+ * Writing the interrupt ID it received from the claim (irq) to the
+ * complete register would signal the PLIC we've served this IRQ.
+ * The PLIC does not check whether the completion ID is the same as the
+ * last claim ID for that target. If the completion ID does not match an
* interrupt source that is currently enabled for the target, the completion
* is silently ignored.
* RETURN VALUE: none
diff --git a/bsp/qemu-riscv-virt64/driver/plic.h b/bsp/qemu-riscv-virt64/driver/plic.h
index 79af90cbfb..5d0fea6eb2 100644
--- a/bsp/qemu-riscv-virt64/driver/plic.h
+++ b/bsp/qemu-riscv-virt64/driver/plic.h
@@ -15,7 +15,7 @@
/*
* This machine puts platform-level interrupt controller (PLIC) here.
* Here only list PLIC registers in Machine mode.
- *
+ *
*/
#define VIRT_PLIC_BASE 0x0c000000L
@@ -49,8 +49,6 @@
#define PLIC_PRIORITY(id) (VIRT_PLIC_BASE + PLIC_PRIORITY_OFFSET + (id) * 4)
#define PLIC_PENDING(id) (VIRT_PLIC_BASE + PLIC_PENDING_OFFSET + ((id) / 32))
-
-
void plic_set_priority(int irq, int priority);
void plic_irq_enable(int irq);
void plic_irq_disable(int irq);
diff --git a/libcpu/risc-v/virt64/context_gcc.S b/libcpu/risc-v/virt64/context_gcc.S
index 620559a8d0..40803148df 100644
--- a/libcpu/risc-v/virt64/context_gcc.S
+++ b/libcpu/risc-v/virt64/context_gcc.S
@@ -28,7 +28,6 @@ rt_hw_interrupt_disable:
#endif
ret
-
/*
* void rt_hw_interrupt_enable(rt_base_t level);
*/
diff --git a/libcpu/risc-v/virt64/cpuport.c b/libcpu/risc-v/virt64/cpuport.c
index df98bfe1eb..33cab19488 100644
--- a/libcpu/risc-v/virt64/cpuport.c
+++ b/libcpu/risc-v/virt64/cpuport.c
@@ -18,17 +18,17 @@
/**
* @brief from thread used interrupt context switch
- *
+ *
*/
volatile rt_ubase_t rt_interrupt_from_thread = 0;
/**
* @brief to thread used interrupt context switch
- *
+ *
*/
volatile rt_ubase_t rt_interrupt_to_thread = 0;
/**
* @brief flag to indicate context switch in interrupt or not
- *
+ *
*/
volatile rt_ubase_t rt_thread_switch_interrupt_flag = 0;
diff --git a/libcpu/risc-v/virt64/cpuport.h b/libcpu/risc-v/virt64/cpuport.h
index 378d8085bd..fa0776b509 100644
--- a/libcpu/risc-v/virt64/cpuport.h
+++ b/libcpu/risc-v/virt64/cpuport.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/libcpu/risc-v/virt64/interrupt.c b/libcpu/risc-v/virt64/interrupt.c
index 4280446198..7916be8f6f 100644
--- a/libcpu/risc-v/virt64/interrupt.c
+++ b/libcpu/risc-v/virt64/interrupt.c
@@ -158,7 +158,7 @@ void dump_regs(struct rt_hw_stack_frame *regs)
rt_size_t satp_v = read_csr(satp);
rt_kprintf("satp = 0x%p\n",satp_v);
const char *mode_str = "Unknown Address Translation/Protection Mode";
-
+
switch(__MASKVALUE(satp_v >> 60,__MASK(4)))
{
case 0:
@@ -188,7 +188,7 @@ void handle_trap(rt_size_t xcause,rt_size_t xtval,rt_size_t xepc,struct rt_hw_st
{
case IRQ_M_SOFT:
{
-
+
}
break;
case IRQ_M_TIMER:
diff --git a/libcpu/risc-v/virt64/interrupt.h b/libcpu/risc-v/virt64/interrupt.h
index 01b26c78c8..e49f0215bf 100644
--- a/libcpu/risc-v/virt64/interrupt.h
+++ b/libcpu/risc-v/virt64/interrupt.h
@@ -24,4 +24,4 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
void *param, const char *name);
void handle_trap(rt_size_t xcause,rt_size_t xtval,rt_size_t xepc,struct rt_hw_stack_frame *sp);
-#endif
\ No newline at end of file
+#endif
diff --git a/libcpu/risc-v/virt64/riscv.h b/libcpu/risc-v/virt64/riscv.h
index 04ac4fea74..d0c0cc4b38 100644
--- a/libcpu/risc-v/virt64/riscv.h
+++ b/libcpu/risc-v/virt64/riscv.h
@@ -26,4 +26,4 @@
#define __ALIGNUP(value,bit) (((value) + __MASK(bit)) & __UMASK(bit))
#define __ALIGNDOWN(value,bit) ((value) & __UMASK(bit))
-#endif
\ No newline at end of file
+#endif
diff --git a/libcpu/risc-v/virt64/riscv_io.h b/libcpu/risc-v/virt64/riscv_io.h
index 109f7297e5..391d7f5a41 100644
--- a/libcpu/risc-v/virt64/riscv_io.h
+++ b/libcpu/risc-v/virt64/riscv_io.h
@@ -98,40 +98,40 @@ static inline rt_uint64_t __raw_readq(const volatile void *addr)
/* clang-format off */
-#define __io_rbr() do {} while (0)
-#define __io_rar() do {} while (0)
-#define __io_rbw() do {} while (0)
-#define __io_raw() do {} while (0)
+#define __io_rbr() do {} while (0)
+#define __io_rar() do {} while (0)
+#define __io_rbw() do {} while (0)
+#define __io_raw() do {} while (0)
-#define readb_relaxed(c) ({ rt_uint8_t __v; __io_rbr(); __v = __raw_readb(c); __io_rar(); __v; })
-#define readw_relaxed(c) ({ rt_uint16_t __v; __io_rbr(); __v = __raw_readw(c); __io_rar(); __v; })
-#define readl_relaxed(c) ({ rt_uint32_t __v; __io_rbr(); __v = __raw_readl(c); __io_rar(); __v; })
+#define readb_relaxed(c) ({ rt_uint8_t __v; __io_rbr(); __v = __raw_readb(c); __io_rar(); __v; })
+#define readw_relaxed(c) ({ rt_uint16_t __v; __io_rbr(); __v = __raw_readw(c); __io_rar(); __v; })
+#define readl_relaxed(c) ({ rt_uint32_t __v; __io_rbr(); __v = __raw_readl(c); __io_rar(); __v; })
-#define writeb_relaxed(v,c) ({ __io_rbw(); __raw_writeb((v),(c)); __io_raw(); })
-#define writew_relaxed(v,c) ({ __io_rbw(); __raw_writew((v),(c)); __io_raw(); })
-#define writel_relaxed(v,c) ({ __io_rbw(); __raw_writel((v),(c)); __io_raw(); })
+#define writeb_relaxed(v,c) ({ __io_rbw(); __raw_writeb((v),(c)); __io_raw(); })
+#define writew_relaxed(v,c) ({ __io_rbw(); __raw_writew((v),(c)); __io_raw(); })
+#define writel_relaxed(v,c) ({ __io_rbw(); __raw_writel((v),(c)); __io_raw(); })
#if __riscv_xlen != 32
-#define readq_relaxed(c) ({ rt_uint64_t __v; __io_rbr(); __v = __raw_readq(c); __io_rar(); __v; })
-#define writeq_relaxed(v,c) ({ __io_rbw(); __raw_writeq((v),(c)); __io_raw(); })
+#define readq_relaxed(c) ({ rt_uint64_t __v; __io_rbr(); __v = __raw_readq(c); __io_rar(); __v; })
+#define writeq_relaxed(v,c) ({ __io_rbw(); __raw_writeq((v),(c)); __io_raw(); })
#endif
-#define __io_br() do {} while (0)
-#define __io_ar() __asm__ __volatile__ ("fence i,r" : : : "memory");
-#define __io_bw() __asm__ __volatile__ ("fence w,o" : : : "memory");
-#define __io_aw() do {} while (0)
+#define __io_br() do {} while (0)
+#define __io_ar() __asm__ __volatile__ ("fence i,r" : : : "memory");
+#define __io_bw() __asm__ __volatile__ ("fence w,o" : : : "memory");
+#define __io_aw() do {} while (0)
-#define readb(c) ({ rt_uint8_t __v; __io_br(); __v = __raw_readb(c); __io_ar(); __v; })
-#define readw(c) ({ rt_uint16_t __v; __io_br(); __v = __raw_readw(c); __io_ar(); __v; })
-#define readl(c) ({ rt_uint32_t __v; __io_br(); __v = __raw_readl(c); __io_ar(); __v; })
+#define readb(c) ({ rt_uint8_t __v; __io_br(); __v = __raw_readb(c); __io_ar(); __v; })
+#define readw(c) ({ rt_uint16_t __v; __io_br(); __v = __raw_readw(c); __io_ar(); __v; })
+#define readl(c) ({ rt_uint32_t __v; __io_br(); __v = __raw_readl(c); __io_ar(); __v; })
-#define writeb(v,c) ({ __io_bw(); __raw_writeb((v),(c)); __io_aw(); })
-#define writew(v,c) ({ __io_bw(); __raw_writew((v),(c)); __io_aw(); })
-#define writel(v,c) ({ __io_bw(); __raw_writel((v),(c)); __io_aw(); })
+#define writeb(v,c) ({ __io_bw(); __raw_writeb((v),(c)); __io_aw(); })
+#define writew(v,c) ({ __io_bw(); __raw_writew((v),(c)); __io_aw(); })
+#define writel(v,c) ({ __io_bw(); __raw_writel((v),(c)); __io_aw(); })
#if __riscv_xlen != 32
-#define readq(c) ({ rt_uint64_t __v; __io_br(); __v = __raw_readq(c); __io_ar(); __v; })
-#define writeq(v,c) ({ __io_bw(); __raw_writeq((v),(c)); __io_aw(); })
+#define readq(c) ({ rt_uint64_t __v; __io_br(); __v = __raw_readq(c); __io_ar(); __v; })
+#define writeq(v,c) ({ __io_bw(); __raw_writeq((v),(c)); __io_aw(); })
#endif
-#endif
\ No newline at end of file
+#endif
diff --git a/libcpu/risc-v/virt64/stackframe.h b/libcpu/risc-v/virt64/stackframe.h
index 835f03ee3a..eb4e4f9d86 100644
--- a/libcpu/risc-v/virt64/stackframe.h
+++ b/libcpu/risc-v/virt64/stackframe.h
@@ -152,4 +152,4 @@
.option pop
.endm
-#endif
\ No newline at end of file
+#endif
diff --git a/libcpu/risc-v/virt64/tick.c b/libcpu/risc-v/virt64/tick.c
index 9647751b46..d6970ec417 100644
--- a/libcpu/risc-v/virt64/tick.c
+++ b/libcpu/risc-v/virt64/tick.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -36,8 +36,7 @@ int tick_isr(void)
#ifdef RISCV_S_MODE
sbi_set_timer(get_ticks() + tick_cycles);
#else
- int id = r_mhartid();
- *(uint64_t*)CLINT_MTIMECMP(id) = *(uint64_t*)CLINT_MTIME + tick_cycles;
+ *(uint64_t*)CLINT_MTIMECMP(r_mhartid()) = *(uint64_t*)CLINT_MTIME + tick_cycles;
#endif
return 0;
@@ -57,14 +56,13 @@ int rt_hw_tick_init(void)
tick_cycles = 40000;
/* Set timer */
sbi_set_timer(get_ticks() + tick_cycles);
-
+
/* Enable the Supervisor-Timer bit in SIE */
set_csr(sie, SIP_STIP);
#else
clear_csr(mie, MIP_MTIP);
clear_csr(mip, MIP_MTIP);
- int id = r_mhartid();
- *(uint64_t*)CLINT_MTIMECMP(id) = *(uint64_t*)CLINT_MTIME + interval;
+ *(uint64_t*)CLINT_MTIMECMP(r_mhartid()) = *(uint64_t*)CLINT_MTIME + interval;
set_csr(mie, MIP_MTIP);
#endif
return 0;
diff --git a/libcpu/risc-v/virt64/tick.h b/libcpu/risc-v/virt64/tick.h
index 1168e611e6..c5a55cf16f 100644
--- a/libcpu/risc-v/virt64/tick.h
+++ b/libcpu/risc-v/virt64/tick.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*