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[BSP][STM32][469-DISCO]Add flash sdram usb drivers

This commit is contained in:
ZYH 2019-04-11 10:24:43 +08:00
parent 2a41e3257f
commit d212787bbb
20 changed files with 2325 additions and 68 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

80
bsp/stm32/stm32f469-st-disco/.config
View File

@ -48,11 +48,11 @@ CONFIG_RT_USING_MESSAGEQUEUE=y
# Memory Management
#
CONFIG_RT_USING_MEMPOOL=y
# CONFIG_RT_USING_MEMHEAP is not set
CONFIG_RT_USING_MEMHEAP=y
# CONFIG_RT_USING_NOHEAP is not set
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SMALL_MEM is not set
# CONFIG_RT_USING_SLAB is not set
# CONFIG_RT_USING_MEMTRACE is not set
CONFIG_RT_USING_MEMHEAP_AS_HEAP=y
CONFIG_RT_USING_HEAP=y
#
@ -105,7 +105,34 @@ CONFIG_FINSH_ARG_MAX=10
#
# Device virtual file system
#
# CONFIG_RT_USING_DFS is not set
CONFIG_RT_USING_DFS=y
CONFIG_DFS_USING_WORKDIR=y
CONFIG_DFS_FILESYSTEMS_MAX=8
CONFIG_DFS_FILESYSTEM_TYPES_MAX=8
CONFIG_DFS_FD_MAX=64
# CONFIG_RT_USING_DFS_MNTTABLE is not set
CONFIG_RT_USING_DFS_ELMFAT=y
#
# elm-chan's FatFs, Generic FAT Filesystem Module
#
CONFIG_RT_DFS_ELM_CODE_PAGE=437
CONFIG_RT_DFS_ELM_WORD_ACCESS=y
# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
CONFIG_RT_DFS_ELM_USE_LFN_3=y
CONFIG_RT_DFS_ELM_USE_LFN=3
CONFIG_RT_DFS_ELM_MAX_LFN=255
CONFIG_RT_DFS_ELM_DRIVES=2
CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512
# CONFIG_RT_DFS_ELM_USE_ERASE is not set
CONFIG_RT_DFS_ELM_REENTRANT=y
CONFIG_RT_USING_DFS_DEVFS=y
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_RAMFS is not set
# CONFIG_RT_USING_DFS_UFFS is not set
# CONFIG_RT_USING_DFS_JFFS2 is not set
#
# Device Drivers
@ -144,12 +171,22 @@ CONFIG_RT_USING_PIN=y
#
# CONFIG_RT_USING_USB_HOST is not set
# CONFIG_RT_USING_USB_DEVICE is not set
# CONFIG__RT_USB_DEVICE_NONE is not set
# CONFIG__RT_USB_DEVICE_CDC is not set
# CONFIG__RT_USB_DEVICE_MSTORAGE is not set
# CONFIG__RT_USB_DEVICE_HID is not set
# CONFIG__RT_USB_DEVICE_WINUSB is not set
#
# POSIX layer and C standard library
#
# CONFIG_RT_USING_LIBC is not set
CONFIG_RT_USING_LIBC=y
# CONFIG_RT_USING_PTHREADS is not set
CONFIG_RT_USING_POSIX=y
# CONFIG_RT_USING_POSIX_MMAP is not set
# CONFIG_RT_USING_POSIX_TERMIOS is not set
# CONFIG_RT_USING_POSIX_AIO is not set
# CONFIG_RT_USING_MODULE is not set
#
# Network
@ -258,6 +295,7 @@ CONFIG_RT_USING_PIN=y
#
# CONFIG_PKG_USING_OPENMV is not set
# CONFIG_PKG_USING_MUPDF is not set
# CONFIG_PKG_USING_STEMWIN is not set
#
# tools packages
@ -281,28 +319,25 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_FAL is not set
# CONFIG_PKG_USING_FAL_LATEST_VERSION is not set
# CONFIG_PKG_USING_FAL_V00300 is not set
# CONFIG_PKG_USING_FAL_V00200 is not set
# CONFIG_PKG_USING_FAL_V00100 is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
# CONFIG_PKG_USING_CMSIS is not set
# CONFIG_PKG_USING_DFS_YAFFS is not set
# CONFIG_PKG_USING_LITTLEFS is not set
# CONFIG_PKG_USING_LITTLEFS_V090 is not set
# CONFIG_PKG_USING_LITTLEFS_V170 is not set
# CONFIG_PKG_USING_LITTLEFS_LATEST_VERSION is not set
# CONFIG_PKG_USING_THREAD_POOL is not set
#
# peripheral libraries and drivers
#
#
# sensors drivers
#
# CONFIG_PKG_USING_LSM6DSL is not set
# CONFIG_PKG_USING_LPS22HB is not set
# CONFIG_PKG_USING_HTS221 is not set
# CONFIG_PKG_USING_LSM303AGR is not set
# CONFIG_PKG_USING_BME280 is not set
# CONFIG_PKG_USING_BMA400 is not set
# CONFIG_PKG_USING_BMI160_BMX160 is not set
# CONFIG_PKG_USING_SPL0601 is not set
# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_AHT10 is not set
@ -315,7 +350,10 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_SX12XX is not set
# CONFIG_PKG_USING_SIGNAL_LED is not set
# CONFIG_PKG_USING_WM_LIBRARIES is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
# CONFIG_PKG_USING_INFRARED is not set
# CONFIG_PKG_USING_ROSSERIAL is not set
#
# miscellaneous packages
@ -341,6 +379,7 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
# CONFIG_PKG_USING_HELLO is not set
# CONFIG_PKG_USING_VI is not set
# CONFIG_PKG_USING_NNOM is not set
#
# Privated Packages of RealThread
@ -380,6 +419,8 @@ CONFIG_SOC_STM32F469NI=y
#
# Onboard Peripheral Drivers
#
CONFIG_BSP_USING_SDRAM=y
# CONFIG_BSP_USING_QSPI_FLASH is not set
#
# On-chip Peripheral Drivers
@ -387,6 +428,11 @@ CONFIG_SOC_STM32F469NI=y
CONFIG_BSP_USING_GPIO=y
CONFIG_BSP_USING_UART=y
CONFIG_BSP_USING_UART3=y
# CONFIG_BSP_UART3_RX_USING_DMA is not set
# CONFIG_BSP_USING_QSPI is not set
# CONFIG_BSP_USING_ON_CHIP_FLASH is not set
CONFIG_BSP_USING_FMC=y
# CONFIG_BSP_USING_USBD_FS is not set
#
# Board extended module Drivers

14
bsp/stm32/stm32f469-st-disco/board/CubeMX_Config/.mxproject
View File

File diff suppressed because one or more lines are too long

408
bsp/stm32/stm32f469-st-disco/board/CubeMX_Config/CubeMX_Config.ioc
View File

@ -1,49 +1,185 @@
#MicroXplorer Configuration settings - do not modify
Dma.Request0=SPI3_RX
Dma.RequestsNb=1
Dma.SPI3_RX.0.Direction=DMA_PERIPH_TO_MEMORY
Dma.SPI3_RX.0.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.SPI3_RX.0.Instance=DMA1_Stream0
Dma.SPI3_RX.0.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.SPI3_RX.0.MemInc=DMA_MINC_ENABLE
Dma.SPI3_RX.0.Mode=DMA_NORMAL
Dma.SPI3_RX.0.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.SPI3_RX.0.PeriphInc=DMA_PINC_DISABLE
Dma.SPI3_RX.0.Priority=DMA_PRIORITY_LOW
Dma.SPI3_RX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
FMC.CASLatency1=FMC_SDRAM_CAS_LATENCY_3
FMC.ExitSelfRefreshDelay1=7
FMC.IPParameters=CASLatency1,ReadBurst1,ReadBurst2,SDClockPeriod1,SDClockPeriod2,LoadToActiveDelay1,ExitSelfRefreshDelay1,SelfRefreshTime1,RowCycleDelay1,RowCycleDelay2,WriteRecoveryTime1,RPDelay1,RPDelay2,RCDDelay1
FMC.LoadToActiveDelay1=2
FMC.RCDDelay1=2
FMC.RPDelay1=2
FMC.RPDelay2=2
FMC.ReadBurst1=FMC_SDRAM_RBURST_ENABLE
FMC.ReadBurst2=FMC_SDRAM_RBURST_ENABLE
FMC.RowCycleDelay1=7
FMC.RowCycleDelay2=7
FMC.SDClockPeriod1=FMC_SDRAM_CLOCK_PERIOD_2
FMC.SDClockPeriod2=FMC_SDRAM_CLOCK_PERIOD_2
FMC.SelfRefreshTime1=4
FMC.WriteRecoveryTime1=3
File.Version=6
I2S3.AudioFreq=I2S_AUDIOFREQ_16K
I2S3.ErrorAudioFreq=0.0 %
I2S3.FullDuplexMode=I2S_FULLDUPLEXMODE_DISABLE
I2S3.IPParameters=Instance,VirtualMode,FullDuplexMode,RealAudioFreq,ErrorAudioFreq,AudioFreq,Standard,Mode
I2S3.Instance=SPI$Index
I2S3.Mode=I2S_MODE_MASTER_RX
I2S3.RealAudioFreq=16.0 KHz
I2S3.Standard=I2S_STANDARD_LSB
I2S3.VirtualMode=I2S_MODE_MASTER
KeepUserPlacement=false
Mcu.Family=STM32F4
Mcu.IP0=NVIC
Mcu.IP1=RCC
Mcu.IP2=SYS
Mcu.IP3=USART3
Mcu.IPNb=4
Mcu.IP0=CRC
Mcu.IP1=DMA
Mcu.IP10=TIM4
Mcu.IP11=USART3
Mcu.IP12=USB_OTG_FS
Mcu.IP2=FMC
Mcu.IP3=GFXSIMULATOR
Mcu.IP4=I2S3
Mcu.IP5=NVIC
Mcu.IP6=PDM2PCM
Mcu.IP7=QUADSPI
Mcu.IP8=RCC
Mcu.IP9=SYS
Mcu.IPNb=13
Mcu.Name=STM32F469NIHx
Mcu.Package=TFBGA216
Mcu.Pin0=PA14
Mcu.Pin1=PA13
Mcu.Pin2=PC14/OSC32_IN
Mcu.Pin3=PC15/OSC32_OUT
Mcu.Pin4=PH0/OSC_IN
Mcu.Pin5=PH1/OSC_OUT
Mcu.Pin6=PB10
Mcu.Pin7=PB11
Mcu.Pin8=VP_SYS_VS_Systick
Mcu.PinsNb=9
Mcu.Pin0=PE1
Mcu.Pin1=PE0
Mcu.Pin10=PA12
Mcu.Pin11=PI4
Mcu.Pin12=PD1
Mcu.Pin13=PI3
Mcu.Pin14=PI2
Mcu.Pin15=PA11
Mcu.Pin16=PF0
Mcu.Pin17=PI5
Mcu.Pin18=PI7
Mcu.Pin19=PI10
Mcu.Pin2=PB3
Mcu.Pin20=PI6
Mcu.Pin21=PH15
Mcu.Pin22=PI1
Mcu.Pin23=PC14/OSC32_IN
Mcu.Pin24=PF1
Mcu.Pin25=PI9
Mcu.Pin26=PH13
Mcu.Pin27=PH14
Mcu.Pin28=PI0
Mcu.Pin29=PC15/OSC32_OUT
Mcu.Pin3=PA15
Mcu.Pin30=PH0/OSC_IN
Mcu.Pin31=PF2
Mcu.Pin32=PH1/OSC_OUT
Mcu.Pin33=PF3
Mcu.Pin34=PG8
Mcu.Pin35=PF4
Mcu.Pin36=PH3
Mcu.Pin37=PF7
Mcu.Pin38=PF6
Mcu.Pin39=PF5
Mcu.Pin4=PA14
Mcu.Pin40=PH2
Mcu.Pin41=PD15
Mcu.Pin42=PD10
Mcu.Pin43=PF10
Mcu.Pin44=PF9
Mcu.Pin45=PF8
Mcu.Pin46=PD14
Mcu.Pin47=PD9
Mcu.Pin48=PD8
Mcu.Pin49=PC0
Mcu.Pin5=PA13
Mcu.Pin50=PF12
Mcu.Pin51=PG1
Mcu.Pin52=PF15
Mcu.Pin53=PD12
Mcu.Pin54=PD13
Mcu.Pin55=PH12
Mcu.Pin56=PF13
Mcu.Pin57=PG0
Mcu.Pin58=PE8
Mcu.Pin59=PG5
Mcu.Pin6=PB6
Mcu.Pin60=PG4
Mcu.Pin61=PH9
Mcu.Pin62=PH11
Mcu.Pin63=PF14
Mcu.Pin64=PF11
Mcu.Pin65=PE9
Mcu.Pin66=PE11
Mcu.Pin67=PE14
Mcu.Pin68=PB10
Mcu.Pin69=PH8
Mcu.Pin7=PG15
Mcu.Pin70=PH10
Mcu.Pin71=PE7
Mcu.Pin72=PE10
Mcu.Pin73=PE12
Mcu.Pin74=PE15
Mcu.Pin75=PE13
Mcu.Pin76=PB11
Mcu.Pin77=VP_CRC_VS_CRC
Mcu.Pin78=VP_PDM2PCM_VS_PDM2PCM
Mcu.Pin79=VP_SYS_VS_Systick
Mcu.Pin8=PD6
Mcu.Pin80=VP_TIM4_VS_ControllerModeClock
Mcu.Pin9=PD0
Mcu.PinsNb=81
Mcu.ThirdPartyNb=0
Mcu.UserConstants=
Mcu.UserName=STM32F469NIHx
MxCube.Version=5.1.0
MxDb.Version=DB.5.0.10
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.DMA1_Stream0_IRQn=true\:0\:0\:false\:false\:true\:false\:true
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.OTG_FS_IRQn=true\:0\:0\:false\:false\:true\:true\:true
NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
NVIC.SPI3_IRQn=true\:0\:0\:false\:false\:true\:true\:true
NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
PA11.Mode=Device_Only
PA11.Signal=USB_OTG_FS_DM
PA12.Mode=Device_Only
PA12.Signal=USB_OTG_FS_DP
PA13.Mode=Serial_Wire
PA13.Signal=SYS_JTMS-SWDIO
PA14.Mode=Serial_Wire
PA14.Signal=SYS_JTCK-SWCLK
PA15.GPIOParameters=GPIO_Speed
PA15.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
PA15.Mode=Half_Duplex_Master
PA15.Signal=I2S3_WS
PB10.Locked=true
PB10.Mode=Asynchronous
PB10.Signal=USART3_TX
PB11.Locked=true
PB11.Mode=Asynchronous
PB11.Signal=USART3_RX
PB3.GPIOParameters=GPIO_Speed
PB3.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
PB3.Mode=Half_Duplex_Master
PB3.Signal=I2S3_CK
PB6.Mode=Single Bank 1
PB6.Signal=QUADSPI_BK1_NCS
PC0.Locked=true
PC0.Signal=FMC_SDNWE
PC14/OSC32_IN.Mode=LSE-External-Oscillator
PC14/OSC32_IN.Signal=RCC_OSC32_IN
PC15/OSC32_OUT.Mode=LSE-External-Oscillator
@ -56,10 +192,92 @@ PCC.Seq0=0
PCC.Series=STM32F4
PCC.Temperature=25
PCC.Vdd=3.3
PD0.Signal=FMC_D2_DA2
PD1.Signal=FMC_D3_DA3
PD10.Signal=FMC_D15_DA15
PD12.Locked=true
PD12.Signal=S_TIM4_CH1
PD13.Locked=true
PD13.Signal=S_TIM4_CH2
PD14.Signal=FMC_D0_DA0
PD15.Signal=FMC_D1_DA1
PD6.GPIOParameters=GPIO_Speed
PD6.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
PD6.Locked=true
PD6.Mode=Half_Duplex_Master
PD6.Signal=I2S3_SD
PD8.Signal=FMC_D13_DA13
PD9.Signal=FMC_D14_DA14
PDM2PCM.IPParameters=NbCHANNEL
PDM2PCM.NbCHANNEL=2
PE0.Locked=true
PE0.Signal=FMC_NBL0
PE1.Signal=FMC_NBL1
PE10.Signal=FMC_D7_DA7
PE11.Signal=FMC_D8_DA8
PE12.Signal=FMC_D9_DA9
PE13.Signal=FMC_D10_DA10
PE14.Signal=FMC_D11_DA11
PE15.Signal=FMC_D12_DA12
PE7.Signal=FMC_D4_DA4
PE8.Signal=FMC_D5_DA5
PE9.Signal=FMC_D6_DA6
PF0.Signal=FMC_A0
PF1.Signal=FMC_A1
PF10.Mode=Single Bank 1
PF10.Signal=QUADSPI_CLK
PF11.Signal=FMC_SDNRAS
PF12.Signal=FMC_A6
PF13.Signal=FMC_A7
PF14.Signal=FMC_A8
PF15.Signal=FMC_A9
PF2.Signal=FMC_A2
PF3.Signal=FMC_A3
PF4.Signal=FMC_A4
PF5.Signal=FMC_A5
PF6.Mode=Single Bank 1
PF6.Signal=QUADSPI_BK1_IO3
PF7.Locked=true
PF7.Mode=Single Bank 1
PF7.Signal=QUADSPI_BK1_IO2
PF8.Locked=true
PF8.Mode=Single Bank 1
PF8.Signal=QUADSPI_BK1_IO0
PF9.Locked=true
PF9.Mode=Single Bank 1
PF9.Signal=QUADSPI_BK1_IO1
PG0.Signal=FMC_A10
PG1.Signal=FMC_A11
PG15.Signal=FMC_SDNCAS
PG4.Signal=FMC_A14_BA0
PG5.Signal=FMC_A15_BA1
PG8.Signal=FMC_SDCLK
PH0/OSC_IN.Mode=HSE-External-Oscillator
PH0/OSC_IN.Signal=RCC_OSC_IN
PH1/OSC_OUT.Mode=HSE-External-Oscillator
PH1/OSC_OUT.Signal=RCC_OSC_OUT
PH10.Signal=FMC_D18
PH11.Signal=FMC_D19
PH12.Signal=FMC_D20
PH13.Signal=FMC_D21
PH14.Signal=FMC_D22
PH15.Signal=FMC_D23
PH2.Mode=SdramChipSelect1_1
PH2.Signal=FMC_SDCKE0
PH3.Mode=SdramChipSelect1_1
PH3.Signal=FMC_SDNE0
PH8.Signal=FMC_D16
PH9.Signal=FMC_D17
PI0.Signal=FMC_D24
PI1.Signal=FMC_D25
PI10.Signal=FMC_D31
PI2.Signal=FMC_D26
PI3.Signal=FMC_D27
PI4.Signal=FMC_NBL2
PI5.Signal=FMC_NBL3
PI6.Signal=FMC_D28
PI7.Signal=FMC_D29
PI9.Signal=FMC_D30
PinOutPanel.CurrentBGAView=Top
PinOutPanel.RotationAngle=0
ProjectManager.AskForMigrate=true
@ -88,7 +306,13 @@ ProjectManager.StackSize=0x400
ProjectManager.TargetToolchain=MDK-ARM V5
ProjectManager.ToolChainLocation=
ProjectManager.UnderRoot=false
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART3_UART_Init-USART3-false-HAL-true
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-MX_DMA_Init-DMA-false-HAL-true,3-MX_USART3_UART_Init-USART3-false-HAL-true,4-MX_FMC_Init-FMC-false-HAL-true,5-MX_QUADSPI_Init-QUADSPI-false-HAL-true,6-MX_GFXSIMULATOR_Init-GFXSIMULATOR-false-HAL-true,7-MX_CRC_Init-CRC-false-HAL-true,8-MX_I2S3_Init-I2S3-false-HAL-true,9-MX_TIM4_Init-TIM4-false-HAL-true,10-MX_PDM2PCM_Init-PDM2PCM-false-HAL-true,11-MX_USB_OTG_FS_PCD_Init-USB_OTG_FS-false-HAL-true,12-SystemClock_Config-RCC-false-HAL-false
QUADSPI.ChipSelectHighTime=QSPI_CS_HIGH_TIME_5_CYCLE
QUADSPI.ClockPrescaler=1
QUADSPI.FifoThreshold=4
QUADSPI.FlashSize=24
QUADSPI.IPParameters=ClockPrescaler,FifoThreshold,SampleShifting,FlashSize,ChipSelectHighTime
QUADSPI.SampleShifting=QSPI_SAMPLE_SHIFTING_HALFCYCLE
RCC.AHBFreq_Value=180000000
RCC.APB1CLKDivider=RCC_HCLK_DIV4
RCC.APB1Freq_Value=45000000
@ -105,8 +329,8 @@ RCC.FamilyName=M
RCC.HCLKFreq_Value=180000000
RCC.HSE_VALUE=8000000
RCC.I2SFreq_Value=192000000
RCC.IPParameters=AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,DSIFreq_Value,DSITXEscFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,I2SFreq_Value,LCDTFTFreq_Value,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLDSIFreq_Value,PLLDSIVCOFreq_Value,PLLI2SQCLKFreq_Value,PLLI2SRCLKFreq_Value,PLLM,PLLN,PLLQCLKFreq_Value,PLLRCLKFreq_Value,PLLRFreq_Value,PLLSAIPCLKFreq_Value,PLLSAIQCLKFreq_Value,PLLSAIRCLKFreq_Value,PLLSourceVirtual,RTCFreq_Value,RTCHSEDivFreq_Value,SAIAFreq_Value,SAIBFreq_Value,SDIOFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USBFreq_Value,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAIOutputFreq_Value
RCC.LCDTFTFreq_Value=96000000
RCC.IPParameters=AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,DSIFreq_Value,DSITXEscFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,I2SFreq_Value,LCDTFTFreq_Value,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLDSIFreq_Value,PLLDSIVCOFreq_Value,PLLI2SQCLKFreq_Value,PLLI2SRCLKFreq_Value,PLLM,PLLN,PLLQ,PLLQCLKFreq_Value,PLLRCLKFreq_Value,PLLRFreq_Value,PLLSAIN,PLLSAIP,PLLSAIPCLKFreq_Value,PLLSAIQCLKFreq_Value,PLLSAIRCLKFreq_Value,PLLSourceVirtual,RTCFreq_Value,RTCHSEDivFreq_Value,SAIAFreq_Value,SAIBFreq_Value,SDIOFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USBCLockSelection,USBFreq_Value,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAIOutputFreq_Value
RCC.LCDTFTFreq_Value=48000000
RCC.MCO2PinFreq_Value=180000000
RCC.PLLCLKFreq_Value=180000000
RCC.PLLDSIFreq_Value=160000000
@ -115,27 +339,157 @@ RCC.PLLI2SQCLKFreq_Value=96000000
RCC.PLLI2SRCLKFreq_Value=192000000
RCC.PLLM=4
RCC.PLLN=180
RCC.PLLQCLKFreq_Value=90000000
RCC.PLLQ=3
RCC.PLLQCLKFreq_Value=120000000
RCC.PLLRCLKFreq_Value=180000000
RCC.PLLRFreq_Value=180000000
RCC.PLLSAIPCLKFreq_Value=192000000
RCC.PLLSAIQCLKFreq_Value=96000000
RCC.PLLSAIRCLKFreq_Value=192000000
RCC.PLLSAIN=96
RCC.PLLSAIP=RCC_PLLSAIP_DIV4
RCC.PLLSAIPCLKFreq_Value=48000000
RCC.PLLSAIQCLKFreq_Value=48000000
RCC.PLLSAIRCLKFreq_Value=96000000
RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
RCC.RTCFreq_Value=32000
RCC.RTCHSEDivFreq_Value=4000000
RCC.SAIAFreq_Value=96000000
RCC.SAIBFreq_Value=96000000
RCC.SDIOFreq_Value=90000000
RCC.SAIAFreq_Value=48000000
RCC.SAIBFreq_Value=48000000
RCC.SDIOFreq_Value=48000000
RCC.SYSCLKFreq_VALUE=180000000
RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
RCC.USBFreq_Value=90000000
RCC.USBCLockSelection=RCC_CLK48CLKSOURCE_PLLSAIP
RCC.USBFreq_Value=48000000
RCC.VCOI2SOutputFreq_Value=384000000
RCC.VCOInputFreq_Value=2000000
RCC.VCOOutputFreq_Value=360000000
RCC.VCOSAIOutputFreq_Value=384000000
RCC.VCOSAIOutputFreq_Value=192000000
SH.FMC_A0.0=FMC_A0,12b-sda1
SH.FMC_A0.ConfNb=1
SH.FMC_A1.0=FMC_A1,12b-sda1
SH.FMC_A1.ConfNb=1
SH.FMC_A10.0=FMC_A10,12b-sda1
SH.FMC_A10.ConfNb=1
SH.FMC_A11.0=FMC_A11,12b-sda1
SH.FMC_A11.ConfNb=1
SH.FMC_A14_BA0.0=FMC_BA0,FourSdramBanks1
SH.FMC_A14_BA0.ConfNb=1
SH.FMC_A15_BA1.0=FMC_BA1,FourSdramBanks1
SH.FMC_A15_BA1.ConfNb=1
SH.FMC_A2.0=FMC_A2,12b-sda1
SH.FMC_A2.ConfNb=1
SH.FMC_A3.0=FMC_A3,12b-sda1
SH.FMC_A3.ConfNb=1
SH.FMC_A4.0=FMC_A4,12b-sda1
SH.FMC_A4.ConfNb=1
SH.FMC_A5.0=FMC_A5,12b-sda1
SH.FMC_A5.ConfNb=1
SH.FMC_A6.0=FMC_A6,12b-sda1
SH.FMC_A6.ConfNb=1
SH.FMC_A7.0=FMC_A7,12b-sda1
SH.FMC_A7.ConfNb=1
SH.FMC_A8.0=FMC_A8,12b-sda1
SH.FMC_A8.ConfNb=1
SH.FMC_A9.0=FMC_A9,12b-sda1
SH.FMC_A9.ConfNb=1
SH.FMC_D0_DA0.0=FMC_D0,sd-32b-d1
SH.FMC_D0_DA0.ConfNb=1
SH.FMC_D10_DA10.0=FMC_D10,sd-32b-d1
SH.FMC_D10_DA10.ConfNb=1
SH.FMC_D11_DA11.0=FMC_D11,sd-32b-d1
SH.FMC_D11_DA11.ConfNb=1
SH.FMC_D12_DA12.0=FMC_D12,sd-32b-d1
SH.FMC_D12_DA12.ConfNb=1
SH.FMC_D13_DA13.0=FMC_D13,sd-32b-d1
SH.FMC_D13_DA13.ConfNb=1
SH.FMC_D14_DA14.0=FMC_D14,sd-32b-d1
SH.FMC_D14_DA14.ConfNb=1
SH.FMC_D15_DA15.0=FMC_D15,sd-32b-d1
SH.FMC_D15_DA15.ConfNb=1
SH.FMC_D16.0=FMC_D16,sd-32b-d1
SH.FMC_D16.ConfNb=1
SH.FMC_D17.0=FMC_D17,sd-32b-d1
SH.FMC_D17.ConfNb=1
SH.FMC_D18.0=FMC_D18,sd-32b-d1
SH.FMC_D18.ConfNb=1
SH.FMC_D19.0=FMC_D19,sd-32b-d1
SH.FMC_D19.ConfNb=1
SH.FMC_D1_DA1.0=FMC_D1,sd-32b-d1
SH.FMC_D1_DA1.ConfNb=1
SH.FMC_D20.0=FMC_D20,sd-32b-d1
SH.FMC_D20.ConfNb=1
SH.FMC_D21.0=FMC_D21,sd-32b-d1
SH.FMC_D21.ConfNb=1
SH.FMC_D22.0=FMC_D22,sd-32b-d1
SH.FMC_D22.ConfNb=1
SH.FMC_D23.0=FMC_D23,sd-32b-d1
SH.FMC_D23.ConfNb=1
SH.FMC_D24.0=FMC_D24,sd-32b-d1
SH.FMC_D24.ConfNb=1
SH.FMC_D25.0=FMC_D25,sd-32b-d1
SH.FMC_D25.ConfNb=1
SH.FMC_D26.0=FMC_D26,sd-32b-d1
SH.FMC_D26.ConfNb=1
SH.FMC_D27.0=FMC_D27,sd-32b-d1
SH.FMC_D27.ConfNb=1
SH.FMC_D28.0=FMC_D28,sd-32b-d1
SH.FMC_D28.ConfNb=1
SH.FMC_D29.0=FMC_D29,sd-32b-d1
SH.FMC_D29.ConfNb=1
SH.FMC_D2_DA2.0=FMC_D2,sd-32b-d1
SH.FMC_D2_DA2.ConfNb=1
SH.FMC_D30.0=FMC_D30,sd-32b-d1
SH.FMC_D30.ConfNb=1
SH.FMC_D31.0=FMC_D31,sd-32b-d1
SH.FMC_D31.ConfNb=1
SH.FMC_D3_DA3.0=FMC_D3,sd-32b-d1
SH.FMC_D3_DA3.ConfNb=1
SH.FMC_D4_DA4.0=FMC_D4,sd-32b-d1
SH.FMC_D4_DA4.ConfNb=1
SH.FMC_D5_DA5.0=FMC_D5,sd-32b-d1
SH.FMC_D5_DA5.ConfNb=1
SH.FMC_D6_DA6.0=FMC_D6,sd-32b-d1
SH.FMC_D6_DA6.ConfNb=1
SH.FMC_D7_DA7.0=FMC_D7,sd-32b-d1
SH.FMC_D7_DA7.ConfNb=1
SH.FMC_D8_DA8.0=FMC_D8,sd-32b-d1
SH.FMC_D8_DA8.ConfNb=1
SH.FMC_D9_DA9.0=FMC_D9,sd-32b-d1
SH.FMC_D9_DA9.ConfNb=1
SH.FMC_NBL0.0=FMC_NBL0,Sd4ByteEnable1
SH.FMC_NBL0.ConfNb=1
SH.FMC_NBL1.0=FMC_NBL1,Sd4ByteEnable1
SH.FMC_NBL1.ConfNb=1
SH.FMC_NBL2.0=FMC_NBL2,Sd4ByteEnable1
SH.FMC_NBL2.ConfNb=1
SH.FMC_NBL3.0=FMC_NBL3,Sd4ByteEnable1
SH.FMC_NBL3.ConfNb=1
SH.FMC_SDCLK.0=FMC_SDCLK,12b-sda1
SH.FMC_SDCLK.ConfNb=1
SH.FMC_SDNCAS.0=FMC_SDNCAS,12b-sda1
SH.FMC_SDNCAS.ConfNb=1
SH.FMC_SDNRAS.0=FMC_SDNRAS,12b-sda1
SH.FMC_SDNRAS.ConfNb=1
SH.FMC_SDNWE.0=FMC_SDNWE,12b-sda1
SH.FMC_SDNWE.ConfNb=1
SH.S_TIM4_CH1.0=TIM4_CH1,TriggerSource_TI1FP1
SH.S_TIM4_CH1.ConfNb=1
SH.S_TIM4_CH2.0=TIM4_CH2,PWM Generation2 CH2
SH.S_TIM4_CH2.ConfNb=1
TIM4.Channel-PWM\ Generation2\ CH2=TIM_CHANNEL_2
TIM4.IPParameters=Channel-PWM Generation2 CH2,Prescaler,Period,Slave_TriggerPolarity,Pulse-PWM Generation2 CH2
TIM4.Period=1
TIM4.Prescaler=0
TIM4.Pulse-PWM\ Generation2\ CH2=1
TIM4.Slave_TriggerPolarity=TIM_TRIGGERPOLARITY_FALLING
USART3.IPParameters=VirtualMode
USART3.VirtualMode=VM_ASYNC
USB_OTG_FS.IPParameters=VirtualMode
USB_OTG_FS.VirtualMode=Device_Only
VP_CRC_VS_CRC.Mode=CRC_Activate
VP_CRC_VS_CRC.Signal=CRC_VS_CRC
VP_PDM2PCM_VS_PDM2PCM.Mode=PDM2PCM_Channel
VP_PDM2PCM_VS_PDM2PCM.Signal=PDM2PCM_VS_PDM2PCM
VP_SYS_VS_Systick.Mode=SysTick
VP_SYS_VS_Systick.Signal=SYS_VS_Systick
VP_TIM4_VS_ControllerModeClock.Mode=Clock Mode
VP_TIM4_VS_ControllerModeClock.Signal=TIM4_VS_ControllerModeClock
board=custom

2
bsp/stm32/stm32f469-st-disco/board/CubeMX_Config/Inc/main.h
View File

@ -50,6 +50,8 @@ extern "C" {
/* USER CODE END EM */
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
/* Exported functions prototypes ---------------------------------------------*/
void Error_Handler(void);

67
bsp/stm32/stm32f469-st-disco/board/CubeMX_Config/Inc/pdm2pcm.h Normal file
View File

@ -0,0 +1,67 @@
/* USER CODE BEGIN Header */
/**
******************************************************************************
* File Name : pdm2pcm.h
* Description : This file provides code for the configuration
* of the pdm2pcm instances.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __pdm2pcm_H
#define __pdm2pcm_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "main.h"
#include "pdm2pcm_glo.h"
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/* Global variables ---------------------------------------------------------*/
extern PDM_Filter_Handler_t PDM1_filter_handler;
extern PDM_Filter_Config_t PDM1_filter_config;
extern PDM_Filter_Handler_t PDM2_filter_handler;
extern PDM_Filter_Config_t PDM2_filter_config;
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/* PDM2PCM init function */
void MX_PDM2PCM_Init(void);
/* USER CODE BEGIN 2 */
/* PDM2PCM process function */
uint8_t MX_PDM2PCM_Process(uint16_t *PDMBuf, uint16_t *PCMBuf);
/* USER CODE END 2 */
/* USER CODE BEGIN 3 */
/* USER CODE END 3 */
#ifdef __cplusplus
}
#endif
#endif /*__pdm2pcm_H */
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

12
bsp/stm32/stm32f469-st-disco/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h
View File

@ -52,7 +52,7 @@
/* #define HAL_ADC_MODULE_ENABLED */
/* #define HAL_CRYP_MODULE_ENABLED */
/* #define HAL_CAN_MODULE_ENABLED */
/* #define HAL_CRC_MODULE_ENABLED */
#define HAL_CRC_MODULE_ENABLED
/* #define HAL_CRYP_MODULE_ENABLED */
/* #define HAL_DAC_MODULE_ENABLED */
/* #define HAL_DCMI_MODULE_ENABLED */
@ -62,10 +62,10 @@
/* #define HAL_NOR_MODULE_ENABLED */
/* #define HAL_PCCARD_MODULE_ENABLED */
/* #define HAL_SRAM_MODULE_ENABLED */
/* #define HAL_SDRAM_MODULE_ENABLED */
#define HAL_SDRAM_MODULE_ENABLED
/* #define HAL_HASH_MODULE_ENABLED */
/* #define HAL_I2C_MODULE_ENABLED */
/* #define HAL_I2S_MODULE_ENABLED */
#define HAL_I2S_MODULE_ENABLED
/* #define HAL_IWDG_MODULE_ENABLED */
/* #define HAL_LTDC_MODULE_ENABLED */
/* #define HAL_RNG_MODULE_ENABLED */
@ -74,17 +74,17 @@
/* #define HAL_SD_MODULE_ENABLED */
/* #define HAL_MMC_MODULE_ENABLED */
/* #define HAL_SPI_MODULE_ENABLED */
/* #define HAL_TIM_MODULE_ENABLED */
#define HAL_TIM_MODULE_ENABLED
#define HAL_UART_MODULE_ENABLED
/* #define HAL_USART_MODULE_ENABLED */
/* #define HAL_IRDA_MODULE_ENABLED */
/* #define HAL_SMARTCARD_MODULE_ENABLED */
/* #define HAL_WWDG_MODULE_ENABLED */
/* #define HAL_PCD_MODULE_ENABLED */
#define HAL_PCD_MODULE_ENABLED
/* #define HAL_HCD_MODULE_ENABLED */
/* #define HAL_DSI_MODULE_ENABLED */
/* #define HAL_QSPI_MODULE_ENABLED */
/* #define HAL_QSPI_MODULE_ENABLED */
#define HAL_QSPI_MODULE_ENABLED
/* #define HAL_CEC_MODULE_ENABLED */
/* #define HAL_FMPI2C_MODULE_ENABLED */
/* #define HAL_SPDIFRX_MODULE_ENABLED */

3
bsp/stm32/stm32f469-st-disco/board/CubeMX_Config/Inc/stm32f4xx_it.h
View File

@ -56,6 +56,9 @@ void SVC_Handler(void);
void DebugMon_Handler(void);
void PendSV_Handler(void);
void SysTick_Handler(void);
void DMA1_Stream0_IRQHandler(void);
void SPI3_IRQHandler(void);
void OTG_FS_IRQHandler(void);
/* USER CODE BEGIN EFP */
/* USER CODE END EFP */

97
bsp/stm32/stm32f469-st-disco/board/CubeMX_Config/Middlewares/ST/STM32_Audio/Addons/PDM/Inc/pdm2pcm_glo.h Normal file
View File

@ -0,0 +1,97 @@
/**
******************************************************************************
* @file pdm2pcm_glo.h
* @author MCD Application Team
* @version V3.0.0
* @date 28-February-2017
* @brief Global header for PDM2PCM conversion code
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Image SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_image_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __PDM2PCM_FILTER_H
#define __PDM2PCM_FILTER_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include <stdint.h>
/* Exported constants --------------------------------------------------------*/
#define PDM_FILTER_ENDIANNESS_LE ((uint16_t)0x0000)
#define PDM_FILTER_ENDIANNESS_BE ((uint16_t)0x0001)
#define PDM_FILTER_BIT_ORDER_LSB ((uint16_t)0x0000)
#define PDM_FILTER_BIT_ORDER_MSB ((uint16_t)0x0001)
#define PDM_FILTER_DEC_FACTOR_48 ((uint16_t)0x0001)
#define PDM_FILTER_DEC_FACTOR_64 ((uint16_t)0x0002)
#define PDM_FILTER_DEC_FACTOR_80 ((uint16_t)0x0003)
#define PDM_FILTER_DEC_FACTOR_128 ((uint16_t)0x0004)
#define PDM_FILTER_DEC_FACTOR_16 ((uint16_t)0x0005)
#define PDM_FILTER_DEC_FACTOR_24 ((uint16_t)0x0006)
#define PDM_FILTER_DEC_FACTOR_32 ((uint16_t)0x0007)
#define PDM_FILTER_INIT_ERROR ((uint16_t)0x0010)
#define PDM_FILTER_CONFIG_ERROR ((uint16_t)0x0020)
#define PDM_FILTER_ENDIANNESS_ERROR ((uint16_t)0x0001)
#define PDM_FILTER_BIT_ORDER_ERROR ((uint16_t)0x0002)
#define PDM_FILTER_CRC_LOCK_ERROR ((uint16_t)0x0004)
#define PDM_FILTER_DECIMATION_ERROR ((uint16_t)0x0008)
#define PDM_FILTER_GAIN_ERROR ((uint16_t)0x0040)
#define PDM_FILTER_SAMPLES_NUMBER_ERROR ((uint16_t)0x0080)
#define PDM2PCM_INTERNAL_MEMORY_SIZE 16
/* Exported types ------------------------------------------------------------*/
typedef struct{
uint16_t bit_order;
uint16_t endianness;
uint32_t high_pass_tap;
uint16_t in_ptr_channels;
uint16_t out_ptr_channels;
uint32_t pInternalMemory[PDM2PCM_INTERNAL_MEMORY_SIZE];
}PDM_Filter_Handler_t;
typedef struct{
uint16_t decimation_factor;
uint16_t output_samples_number;
int16_t mic_gain;
}PDM_Filter_Config_t;
/* Exported macros -----------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
uint32_t PDM_Filter_Init(PDM_Filter_Handler_t *pHandler);
uint32_t PDM_Filter_setConfig(PDM_Filter_Handler_t *pHandler, PDM_Filter_Config_t *pConfig);
uint32_t PDM_Filter_getConfig(PDM_Filter_Handler_t *pHandler, PDM_Filter_Config_t *pConfig);
uint32_t PDM_Filter_deInterleave(void *pDataIn, void *pDataOut, PDM_Filter_Handler_t * pHandler);
uint32_t PDM_Filter(void *pDataIn, void *pDataOut, PDM_Filter_Handler_t *pHandler);
#ifdef __cplusplus
}
#endif
#endif /* __PDM2PCM_FILTER_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

318
bsp/stm32/stm32f469-st-disco/board/CubeMX_Config/Src/main.c
View File

@ -20,6 +20,7 @@
/* Includes ------------------------------------------------------------------*/
#include "main.h"
#include "pdm2pcm.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
@ -42,8 +43,21 @@
/* USER CODE END PM */
/* Private variables ---------------------------------------------------------*/
CRC_HandleTypeDef hcrc;
I2S_HandleTypeDef hi2s3;
DMA_HandleTypeDef hdma_spi3_rx;
QSPI_HandleTypeDef hqspi;
TIM_HandleTypeDef htim4;
UART_HandleTypeDef huart3;
PCD_HandleTypeDef hpcd_USB_OTG_FS;
SDRAM_HandleTypeDef hsdram1;
/* USER CODE BEGIN PV */
/* USER CODE END PV */
@ -51,7 +65,15 @@ UART_HandleTypeDef huart3;
/* Private function prototypes -----------------------------------------------*/
void SystemClock_Config(void);
static void MX_GPIO_Init(void);
static void MX_DMA_Init(void);
static void MX_USART3_UART_Init(void);
static void MX_FMC_Init(void);
static void MX_QUADSPI_Init(void);
static void MX_GFXSIMULATOR_Init(void);
static void MX_CRC_Init(void);
static void MX_I2S3_Init(void);
static void MX_TIM4_Init(void);
static void MX_USB_OTG_FS_PCD_Init(void);
/* USER CODE BEGIN PFP */
/* USER CODE END PFP */
@ -89,7 +111,16 @@ int main(void)
/* Initialize all configured peripherals */
MX_GPIO_Init();
MX_DMA_Init();
MX_USART3_UART_Init();
MX_FMC_Init();
MX_QUADSPI_Init();
MX_GFXSIMULATOR_Init();
MX_CRC_Init();
MX_I2S3_Init();
MX_TIM4_Init();
MX_PDM2PCM_Init();
MX_USB_OTG_FS_PCD_Init();
/* USER CODE BEGIN 2 */
/* USER CODE END 2 */
@ -115,6 +146,7 @@ void SystemClock_Config(void)
{
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
/** Configure the main internal regulator output voltage
*/
@ -129,7 +161,7 @@ void SystemClock_Config(void)
RCC_OscInitStruct.PLL.PLLM = 4;
RCC_OscInitStruct.PLL.PLLN = 180;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
RCC_OscInitStruct.PLL.PLLQ = 4;
RCC_OscInitStruct.PLL.PLLQ = 3;
RCC_OscInitStruct.PLL.PLLR = 2;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
@ -154,6 +186,195 @@ void SystemClock_Config(void)
{
Error_Handler();
}
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2S|RCC_PERIPHCLK_CLK48;
PeriphClkInitStruct.PLLI2S.PLLI2SN = 192;
PeriphClkInitStruct.PLLI2S.PLLI2SR = 2;
PeriphClkInitStruct.PLLSAI.PLLSAIN = 96;
PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV4;
PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLSAIP;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
Error_Handler();
}
}
/**
* @brief CRC Initialization Function
* @param None
* @retval None
*/
static void MX_CRC_Init(void)
{
/* USER CODE BEGIN CRC_Init 0 */
/* USER CODE END CRC_Init 0 */
/* USER CODE BEGIN CRC_Init 1 */
/* USER CODE END CRC_Init 1 */
hcrc.Instance = CRC;
if (HAL_CRC_Init(&hcrc) != HAL_OK)
{
Error_Handler();
}
__HAL_CRC_DR_RESET(&hcrc);
/* USER CODE BEGIN CRC_Init 2 */
/* USER CODE END CRC_Init 2 */
}
/**
* @brief GFXSIMULATOR Initialization Function
* @param None
* @retval None
*/
static void MX_GFXSIMULATOR_Init(void)
{
/* USER CODE BEGIN GFXSIMULATOR_Init 0 */
/* USER CODE END GFXSIMULATOR_Init 0 */
/* USER CODE BEGIN GFXSIMULATOR_Init 1 */
/* USER CODE END GFXSIMULATOR_Init 1 */
/* USER CODE BEGIN GFXSIMULATOR_Init 2 */
/* USER CODE END GFXSIMULATOR_Init 2 */
}
/**
* @brief I2S3 Initialization Function
* @param None
* @retval None
*/
static void MX_I2S3_Init(void)
{
/* USER CODE BEGIN I2S3_Init 0 */
/* USER CODE END I2S3_Init 0 */
/* USER CODE BEGIN I2S3_Init 1 */
/* USER CODE END I2S3_Init 1 */
hi2s3.Instance = SPI3;
hi2s3.Init.Mode = I2S_MODE_MASTER_RX;
hi2s3.Init.Standard = I2S_STANDARD_LSB;
hi2s3.Init.DataFormat = I2S_DATAFORMAT_16B;
hi2s3.Init.MCLKOutput = I2S_MCLKOUTPUT_DISABLE;
hi2s3.Init.AudioFreq = I2S_AUDIOFREQ_16K;
hi2s3.Init.CPOL = I2S_CPOL_LOW;
hi2s3.Init.ClockSource = I2S_CLOCK_PLL;
hi2s3.Init.FullDuplexMode = I2S_FULLDUPLEXMODE_DISABLE;
if (HAL_I2S_Init(&hi2s3) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN I2S3_Init 2 */
/* USER CODE END I2S3_Init 2 */
}
/**
* @brief QUADSPI Initialization Function
* @param None
* @retval None
*/
static void MX_QUADSPI_Init(void)
{
/* USER CODE BEGIN QUADSPI_Init 0 */
/* USER CODE END QUADSPI_Init 0 */
/* USER CODE BEGIN QUADSPI_Init 1 */
/* USER CODE END QUADSPI_Init 1 */
/* QUADSPI parameter configuration*/
hqspi.Instance = QUADSPI;
hqspi.Init.ClockPrescaler = 1;
hqspi.Init.FifoThreshold = 4;
hqspi.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE;
hqspi.Init.FlashSize = 24;
hqspi.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_5_CYCLE;
hqspi.Init.ClockMode = QSPI_CLOCK_MODE_0;
hqspi.Init.FlashID = QSPI_FLASH_ID_1;
hqspi.Init.DualFlash = QSPI_DUALFLASH_DISABLE;
if (HAL_QSPI_Init(&hqspi) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN QUADSPI_Init 2 */
/* USER CODE END QUADSPI_Init 2 */
}
/**
* @brief TIM4 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM4_Init(void)
{
/* USER CODE BEGIN TIM4_Init 0 */
/* USER CODE END TIM4_Init 0 */
TIM_SlaveConfigTypeDef sSlaveConfig = {0};
TIM_MasterConfigTypeDef sMasterConfig = {0};
TIM_OC_InitTypeDef sConfigOC = {0};
/* USER CODE BEGIN TIM4_Init 1 */
/* USER CODE END TIM4_Init 1 */
htim4.Instance = TIM4;
htim4.Init.Prescaler = 0;
htim4.Init.CounterMode = TIM_COUNTERMODE_UP;
htim4.Init.Period = 1;
htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
if (HAL_TIM_Base_Init(&htim4) != HAL_OK)
{
Error_Handler();
}
if (HAL_TIM_PWM_Init(&htim4) != HAL_OK)
{
Error_Handler();
}
sSlaveConfig.SlaveMode = TIM_SLAVEMODE_EXTERNAL1;
sSlaveConfig.InputTrigger = TIM_TS_TI1FP1;
sSlaveConfig.TriggerPolarity = TIM_TRIGGERPOLARITY_FALLING;
sSlaveConfig.TriggerFilter = 0;
if (HAL_TIM_SlaveConfigSynchro(&htim4, &sSlaveConfig) != HAL_OK)
{
Error_Handler();
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK)
{
Error_Handler();
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
sConfigOC.Pulse = 1;
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN TIM4_Init 2 */
/* USER CODE END TIM4_Init 2 */
HAL_TIM_MspPostInit(&htim4);
}
/**
@ -189,6 +410,90 @@ static void MX_USART3_UART_Init(void)
}
/**
* @brief USB_OTG_FS Initialization Function
* @param None
* @retval None
*/
static void MX_USB_OTG_FS_PCD_Init(void)
{
/* USER CODE BEGIN USB_OTG_FS_Init 0 */
/* USER CODE END USB_OTG_FS_Init 0 */
/* USER CODE BEGIN USB_OTG_FS_Init 1 */
/* USER CODE END USB_OTG_FS_Init 1 */
hpcd_USB_OTG_FS.Instance = USB_OTG_FS;
hpcd_USB_OTG_FS.Init.dev_endpoints = 6;
hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL;
hpcd_USB_OTG_FS.Init.dma_enable = DISABLE;
hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED;
hpcd_USB_OTG_FS.Init.Sof_enable = DISABLE;
hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE;
hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE;
hpcd_USB_OTG_FS.Init.vbus_sensing_enable = DISABLE;
hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE;
if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN USB_OTG_FS_Init 2 */
/* USER CODE END USB_OTG_FS_Init 2 */
}
/**
* Enable DMA controller clock
*/
static void MX_DMA_Init(void)
{
/* DMA controller clock enable */
__HAL_RCC_DMA1_CLK_ENABLE();
/* DMA interrupt init */
/* DMA1_Stream0_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn);
}
/* FMC initialization function */
static void MX_FMC_Init(void)
{
FMC_SDRAM_TimingTypeDef SdramTiming;
/** Perform the SDRAM1 memory initialization sequence
*/
hsdram1.Instance = FMC_SDRAM_DEVICE;
/* hsdram1.Init */
hsdram1.Init.SDBank = FMC_SDRAM_BANK1;
hsdram1.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8;
hsdram1.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12;
hsdram1.Init.MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_32;
hsdram1.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
hsdram1.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_3;
hsdram1.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
hsdram1.Init.SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2;
hsdram1.Init.ReadBurst = FMC_SDRAM_RBURST_ENABLE;
hsdram1.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0;
/* SdramTiming */
SdramTiming.LoadToActiveDelay = 2;
SdramTiming.ExitSelfRefreshDelay = 7;
SdramTiming.SelfRefreshTime = 4;
SdramTiming.RowCycleDelay = 7;
SdramTiming.WriteRecoveryTime = 3;
SdramTiming.RPDelay = 2;
SdramTiming.RCDDelay = 2;
if (HAL_SDRAM_Init(&hsdram1, &SdramTiming) != HAL_OK)
{
Error_Handler( );
}
}
/**
* @brief GPIO Initialization Function
* @param None
@ -198,10 +503,15 @@ static void MX_GPIO_Init(void)
{
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOH_CLK_ENABLE();
__HAL_RCC_GPIOE_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOG_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
__HAL_RCC_GPIOI_CLK_ENABLE();
__HAL_RCC_GPIOF_CLK_ENABLE();
__HAL_RCC_GPIOH_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
}

111
bsp/stm32/stm32f469-st-disco/board/CubeMX_Config/Src/pdm2pcm.c Normal file
View File

@ -0,0 +1,111 @@
/* USER CODE BEGIN Header */
/**
******************************************************************************
* File Name : pdm2pcm.c
* Description : This file provides code for the configuration
* of the pdm2pcm instances.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "pdm2pcm.h"
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/* Global variables ---------------------------------------------------------*/
PDM_Filter_Handler_t PDM1_filter_handler;
PDM_Filter_Config_t PDM1_filter_config;
PDM_Filter_Handler_t PDM2_filter_handler;
PDM_Filter_Config_t PDM2_filter_config;
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/* PDM2PCM init function */
void MX_PDM2PCM_Init(void)
{
/* USER CODE BEGIN 2 */
/* USER CODE END 2 */
/**
*/
PDM1_filter_handler.bit_order = PDM_FILTER_BIT_ORDER_LSB;
PDM1_filter_handler.endianness = PDM_FILTER_ENDIANNESS_BE;
PDM1_filter_handler.high_pass_tap = 2104533974;
PDM1_filter_handler.in_ptr_channels = 2;
PDM1_filter_handler.out_ptr_channels = 2;
PDM_Filter_Init(&PDM1_filter_handler);
PDM1_filter_config.decimation_factor = PDM_FILTER_DEC_FACTOR_64;
PDM1_filter_config.output_samples_number = 16;
PDM1_filter_config.mic_gain = 0;
PDM_Filter_setConfig(&PDM1_filter_handler, &PDM1_filter_config);
PDM2_filter_handler.bit_order = PDM_FILTER_BIT_ORDER_LSB;
PDM2_filter_handler.endianness = PDM_FILTER_ENDIANNESS_BE;
PDM2_filter_handler.high_pass_tap = 2104533974;
PDM2_filter_handler.in_ptr_channels = 2;
PDM2_filter_handler.out_ptr_channels = 2;
PDM_Filter_Init(&PDM2_filter_handler);
PDM2_filter_config.decimation_factor = PDM_FILTER_DEC_FACTOR_64;
PDM2_filter_config.output_samples_number = 16;
PDM2_filter_config.mic_gain = 0;
PDM_Filter_setConfig(&PDM2_filter_handler, &PDM2_filter_config);
PDM2_filter_handler.bit_order = PDM_FILTER_BIT_ORDER_LSB;
PDM2_filter_handler.endianness = PDM_FILTER_ENDIANNESS_BE;
PDM2_filter_handler.high_pass_tap = 2104533974;
PDM2_filter_handler.in_ptr_channels = 2;
PDM2_filter_handler.out_ptr_channels = 2;
PDM_Filter_Init(&PDM2_filter_handler);
PDM2_filter_config.decimation_factor = PDM_FILTER_DEC_FACTOR_64;
PDM2_filter_config.output_samples_number = 16;
PDM2_filter_config.mic_gain = 0;
PDM_Filter_setConfig(&PDM2_filter_handler, &PDM2_filter_config);
/* USER CODE BEGIN 3 */
/* USER CODE END 3 */
}
/* USER CODE BEGIN 4 */
/* process function */
uint8_t MX_PDM2PCM_Process(uint16_t *PDMBuf, uint16_t *PCMBuf)
{
/*
uint8_t BSP_AUDIO_IN_PDMToPCM(uint16_t * PDMBuf, uint16_t * PCMBuf)
Converts audio format from PDM to PCM.
Parameters:
PDMBuf : Pointer to PDM buffer data
PCMBuf : Pointer to PCM buffer data
Return values:
AUDIO_OK in case of success, AUDIO_ERROR otherwise
*/
/* this example return the default status AUDIO_ERROR */
return (uint8_t) 1;
}
/* USER CODE END 4 */
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

668
bsp/stm32/stm32f469-st-disco/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c
View File

@ -24,6 +24,7 @@
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
extern DMA_HandleTypeDef hdma_spi3_rx;
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN TD */
@ -58,6 +59,8 @@
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
/**
* Initializes the Global MSP.
*/
@ -77,6 +80,345 @@ void HAL_MspInit(void)
/* USER CODE END MspInit 1 */
}
/**
* @brief CRC MSP Initialization
* This function configures the hardware resources used in this example
* @param hcrc: CRC handle pointer
* @retval None
*/
void HAL_CRC_MspInit(CRC_HandleTypeDef* hcrc)
{
if(hcrc->Instance==CRC)
{
/* USER CODE BEGIN CRC_MspInit 0 */
/* USER CODE END CRC_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_CRC_CLK_ENABLE();
/* USER CODE BEGIN CRC_MspInit 1 */
/* USER CODE END CRC_MspInit 1 */
}
}
/**
* @brief CRC MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hcrc: CRC handle pointer
* @retval None
*/
void HAL_CRC_MspDeInit(CRC_HandleTypeDef* hcrc)
{
if(hcrc->Instance==CRC)
{
/* USER CODE BEGIN CRC_MspDeInit 0 */
/* USER CODE END CRC_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_CRC_CLK_DISABLE();
/* USER CODE BEGIN CRC_MspDeInit 1 */
/* USER CODE END CRC_MspDeInit 1 */
}
}
/**
* @brief I2S MSP Initialization
* This function configures the hardware resources used in this example
* @param hi2s: I2S handle pointer
* @retval None
*/
void HAL_I2S_MspInit(I2S_HandleTypeDef* hi2s)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
if(hi2s->Instance==SPI3)
{
/* USER CODE BEGIN SPI3_MspInit 0 */
/* USER CODE END SPI3_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_SPI3_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
/**I2S3 GPIO Configuration
PB3 ------> I2S3_CK
PA15 ------> I2S3_WS
PD6 ------> I2S3_SD
*/
GPIO_InitStruct.Pin = GPIO_PIN_3;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF6_SPI3;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_15;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF6_SPI3;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_6;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF5_I2S3ext;
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
/* I2S3 DMA Init */
/* SPI3_RX Init */
hdma_spi3_rx.Instance = DMA1_Stream0;
hdma_spi3_rx.Init.Channel = DMA_CHANNEL_0;
hdma_spi3_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
hdma_spi3_rx.Init.PeriphInc = DMA_PINC_DISABLE;
hdma_spi3_rx.Init.MemInc = DMA_MINC_ENABLE;
hdma_spi3_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
hdma_spi3_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
hdma_spi3_rx.Init.Mode = DMA_NORMAL;
hdma_spi3_rx.Init.Priority = DMA_PRIORITY_LOW;
hdma_spi3_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
if (HAL_DMA_Init(&hdma_spi3_rx) != HAL_OK)
{
Error_Handler();
}
__HAL_LINKDMA(hi2s,hdmarx,hdma_spi3_rx);
/* I2S3 interrupt Init */
HAL_NVIC_SetPriority(SPI3_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(SPI3_IRQn);
/* USER CODE BEGIN SPI3_MspInit 1 */
/* USER CODE END SPI3_MspInit 1 */
}
}
/**
* @brief I2S MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hi2s: I2S handle pointer
* @retval None
*/
void HAL_I2S_MspDeInit(I2S_HandleTypeDef* hi2s)
{
if(hi2s->Instance==SPI3)
{
/* USER CODE BEGIN SPI3_MspDeInit 0 */
/* USER CODE END SPI3_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_SPI3_CLK_DISABLE();
/**I2S3 GPIO Configuration
PB3 ------> I2S3_CK
PA15 ------> I2S3_WS
PD6 ------> I2S3_SD
*/
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_3);
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_15);
HAL_GPIO_DeInit(GPIOD, GPIO_PIN_6);
/* I2S3 DMA DeInit */
HAL_DMA_DeInit(hi2s->hdmarx);
/* I2S3 interrupt DeInit */
HAL_NVIC_DisableIRQ(SPI3_IRQn);
/* USER CODE BEGIN SPI3_MspDeInit 1 */
/* USER CODE END SPI3_MspDeInit 1 */
}
}
/**
* @brief QSPI MSP Initialization
* This function configures the hardware resources used in this example
* @param hqspi: QSPI handle pointer
* @retval None
*/
void HAL_QSPI_MspInit(QSPI_HandleTypeDef* hqspi)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
if(hqspi->Instance==QUADSPI)
{
/* USER CODE BEGIN QUADSPI_MspInit 0 */
/* USER CODE END QUADSPI_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_QSPI_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOF_CLK_ENABLE();
/**QUADSPI GPIO Configuration
PB6 ------> QUADSPI_BK1_NCS
PF7 ------> QUADSPI_BK1_IO2
PF6 ------> QUADSPI_BK1_IO3
PF10 ------> QUADSPI_CLK
PF9 ------> QUADSPI_BK1_IO1
PF8 ------> QUADSPI_BK1_IO0
*/
GPIO_InitStruct.Pin = GPIO_PIN_6;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF10_QSPI;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_6|GPIO_PIN_10;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF9_QSPI;
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_8;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF10_QSPI;
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
/* USER CODE BEGIN QUADSPI_MspInit 1 */
/* USER CODE END QUADSPI_MspInit 1 */
}
}
/**
* @brief QSPI MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hqspi: QSPI handle pointer
* @retval None
*/
void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef* hqspi)
{
if(hqspi->Instance==QUADSPI)
{
/* USER CODE BEGIN QUADSPI_MspDeInit 0 */
/* USER CODE END QUADSPI_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_QSPI_CLK_DISABLE();
/**QUADSPI GPIO Configuration
PB6 ------> QUADSPI_BK1_NCS
PF7 ------> QUADSPI_BK1_IO2
PF6 ------> QUADSPI_BK1_IO3
PF10 ------> QUADSPI_CLK
PF9 ------> QUADSPI_BK1_IO1
PF8 ------> QUADSPI_BK1_IO0
*/
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6);
HAL_GPIO_DeInit(GPIOF, GPIO_PIN_7|GPIO_PIN_6|GPIO_PIN_10|GPIO_PIN_9
|GPIO_PIN_8);
/* USER CODE BEGIN QUADSPI_MspDeInit 1 */
/* USER CODE END QUADSPI_MspDeInit 1 */
}
}
/**
* @brief TIM_Base MSP Initialization
* This function configures the hardware resources used in this example
* @param htim_base: TIM_Base handle pointer
* @retval None
*/
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
if(htim_base->Instance==TIM4)
{
/* USER CODE BEGIN TIM4_MspInit 0 */
/* USER CODE END TIM4_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_TIM4_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
/**TIM4 GPIO Configuration
PD12 ------> TIM4_CH1
*/
GPIO_InitStruct.Pin = GPIO_PIN_12;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF2_TIM4;
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
/* USER CODE BEGIN TIM4_MspInit 1 */
/* USER CODE END TIM4_MspInit 1 */
}
}
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
if(htim->Instance==TIM4)
{
/* USER CODE BEGIN TIM4_MspPostInit 0 */
/* USER CODE END TIM4_MspPostInit 0 */
__HAL_RCC_GPIOD_CLK_ENABLE();
/**TIM4 GPIO Configuration
PD13 ------> TIM4_CH2
*/
GPIO_InitStruct.Pin = GPIO_PIN_13;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF2_TIM4;
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
/* USER CODE BEGIN TIM4_MspPostInit 1 */
/* USER CODE END TIM4_MspPostInit 1 */
}
}
/**
* @brief TIM_Base MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param htim_base: TIM_Base handle pointer
* @retval None
*/
void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base)
{
if(htim_base->Instance==TIM4)
{
/* USER CODE BEGIN TIM4_MspDeInit 0 */
/* USER CODE END TIM4_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_TIM4_CLK_DISABLE();
/**TIM4 GPIO Configuration
PD12 ------> TIM4_CH1
PD13 ------> TIM4_CH2
*/
HAL_GPIO_DeInit(GPIOD, GPIO_PIN_12|GPIO_PIN_13);
/* USER CODE BEGIN TIM4_MspDeInit 1 */
/* USER CODE END TIM4_MspDeInit 1 */
}
}
/**
* @brief UART MSP Initialization
* This function configures the hardware resources used in this example
@ -142,6 +484,332 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
}
/**
* @brief PCD MSP Initialization
* This function configures the hardware resources used in this example
* @param hpcd: PCD handle pointer
* @retval None
*/
void HAL_PCD_MspInit(PCD_HandleTypeDef* hpcd)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
if(hpcd->Instance==USB_OTG_FS)
{
/* USER CODE BEGIN USB_OTG_FS_MspInit 0 */
/* USER CODE END USB_OTG_FS_MspInit 0 */
__HAL_RCC_GPIOA_CLK_ENABLE();
/**USB_OTG_FS GPIO Configuration
PA12 ------> USB_OTG_FS_DP
PA11 ------> USB_OTG_FS_DM
*/
GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_11;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/* Peripheral clock enable */
__HAL_RCC_USB_OTG_FS_CLK_ENABLE();
/* USB_OTG_FS interrupt Init */
HAL_NVIC_SetPriority(OTG_FS_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(OTG_FS_IRQn);
/* USER CODE BEGIN USB_OTG_FS_MspInit 1 */
/* USER CODE END USB_OTG_FS_MspInit 1 */
}
}
/**
* @brief PCD MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hpcd: PCD handle pointer
* @retval None
*/
void HAL_PCD_MspDeInit(PCD_HandleTypeDef* hpcd)
{
if(hpcd->Instance==USB_OTG_FS)
{
/* USER CODE BEGIN USB_OTG_FS_MspDeInit 0 */
/* USER CODE END USB_OTG_FS_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_USB_OTG_FS_CLK_DISABLE();
/**USB_OTG_FS GPIO Configuration
PA12 ------> USB_OTG_FS_DP
PA11 ------> USB_OTG_FS_DM
*/
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_12|GPIO_PIN_11);
/* USB_OTG_FS interrupt DeInit */
HAL_NVIC_DisableIRQ(OTG_FS_IRQn);
/* USER CODE BEGIN USB_OTG_FS_MspDeInit 1 */
/* USER CODE END USB_OTG_FS_MspDeInit 1 */
}
}
static uint32_t FMC_Initialized = 0;
static void HAL_FMC_MspInit(void){
/* USER CODE BEGIN FMC_MspInit 0 */
/* USER CODE END FMC_MspInit 0 */
GPIO_InitTypeDef GPIO_InitStruct;
if (FMC_Initialized) {
return;
}
FMC_Initialized = 1;
/* Peripheral clock enable */
__HAL_RCC_FMC_CLK_ENABLE();
/** FMC GPIO Configuration
PE1 ------> FMC_NBL1
PE0 ------> FMC_NBL0
PG15 ------> FMC_SDNCAS
PD0 ------> FMC_D2
PI4 ------> FMC_NBL2
PD1 ------> FMC_D3
PI3 ------> FMC_D27
PI2 ------> FMC_D26
PF0 ------> FMC_A0
PI5 ------> FMC_NBL3
PI7 ------> FMC_D29
PI10 ------> FMC_D31
PI6 ------> FMC_D28
PH15 ------> FMC_D23
PI1 ------> FMC_D25
PF1 ------> FMC_A1
PI9 ------> FMC_D30
PH13 ------> FMC_D21
PH14 ------> FMC_D22
PI0 ------> FMC_D24
PF2 ------> FMC_A2
PF3 ------> FMC_A3
PG8 ------> FMC_SDCLK
PF4 ------> FMC_A4
PH3 ------> FMC_SDNE0
PF5 ------> FMC_A5
PH2 ------> FMC_SDCKE0
PD15 ------> FMC_D1
PD10 ------> FMC_D15
PD14 ------> FMC_D0
PD9 ------> FMC_D14
PD8 ------> FMC_D13
PC0 ------> FMC_SDNWE
PF12 ------> FMC_A6
PG1 ------> FMC_A11
PF15 ------> FMC_A9
PH12 ------> FMC_D20
PF13 ------> FMC_A7
PG0 ------> FMC_A10
PE8 ------> FMC_D5
PG5 ------> FMC_BA1
PG4 ------> FMC_BA0
PH9 ------> FMC_D17
PH11 ------> FMC_D19
PF14 ------> FMC_A8
PF11 ------> FMC_SDNRAS
PE9 ------> FMC_D6
PE11 ------> FMC_D8
PE14 ------> FMC_D11
PH8 ------> FMC_D16
PH10 ------> FMC_D18
PE7 ------> FMC_D4
PE10 ------> FMC_D7
PE12 ------> FMC_D9
PE15 ------> FMC_D12
PE13 ------> FMC_D10
*/
GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_0|GPIO_PIN_8|GPIO_PIN_9
|GPIO_PIN_11|GPIO_PIN_14|GPIO_PIN_7|GPIO_PIN_10
|GPIO_PIN_12|GPIO_PIN_15|GPIO_PIN_13;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_15|GPIO_PIN_8|GPIO_PIN_1|GPIO_PIN_0
|GPIO_PIN_5|GPIO_PIN_4;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_15|GPIO_PIN_10
|GPIO_PIN_14|GPIO_PIN_9|GPIO_PIN_8;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_3|GPIO_PIN_2|GPIO_PIN_5
|GPIO_PIN_7|GPIO_PIN_10|GPIO_PIN_6|GPIO_PIN_1
|GPIO_PIN_9|GPIO_PIN_0;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3
|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_12|GPIO_PIN_15
|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_11;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_15|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_3
|GPIO_PIN_2|GPIO_PIN_12|GPIO_PIN_9|GPIO_PIN_11
|GPIO_PIN_8|GPIO_PIN_10;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_0;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
/* USER CODE BEGIN FMC_MspInit 1 */
/* USER CODE END FMC_MspInit 1 */
}
void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef* hsdram){
/* USER CODE BEGIN SDRAM_MspInit 0 */
/* USER CODE END SDRAM_MspInit 0 */
HAL_FMC_MspInit();
/* USER CODE BEGIN SDRAM_MspInit 1 */
/* USER CODE END SDRAM_MspInit 1 */
}
static uint32_t FMC_DeInitialized = 0;
static void HAL_FMC_MspDeInit(void){
/* USER CODE BEGIN FMC_MspDeInit 0 */
/* USER CODE END FMC_MspDeInit 0 */
if (FMC_DeInitialized) {
return;
}
FMC_DeInitialized = 1;
/* Peripheral clock enable */
__HAL_RCC_FMC_CLK_DISABLE();
/** FMC GPIO Configuration
PE1 ------> FMC_NBL1
PE0 ------> FMC_NBL0
PG15 ------> FMC_SDNCAS
PD0 ------> FMC_D2
PI4 ------> FMC_NBL2
PD1 ------> FMC_D3
PI3 ------> FMC_D27
PI2 ------> FMC_D26
PF0 ------> FMC_A0
PI5 ------> FMC_NBL3
PI7 ------> FMC_D29
PI10 ------> FMC_D31
PI6 ------> FMC_D28
PH15 ------> FMC_D23
PI1 ------> FMC_D25
PF1 ------> FMC_A1
PI9 ------> FMC_D30
PH13 ------> FMC_D21
PH14 ------> FMC_D22
PI0 ------> FMC_D24
PF2 ------> FMC_A2
PF3 ------> FMC_A3
PG8 ------> FMC_SDCLK
PF4 ------> FMC_A4
PH3 ------> FMC_SDNE0
PF5 ------> FMC_A5
PH2 ------> FMC_SDCKE0
PD15 ------> FMC_D1
PD10 ------> FMC_D15
PD14 ------> FMC_D0
PD9 ------> FMC_D14
PD8 ------> FMC_D13
PC0 ------> FMC_SDNWE
PF12 ------> FMC_A6
PG1 ------> FMC_A11
PF15 ------> FMC_A9
PH12 ------> FMC_D20
PF13 ------> FMC_A7
PG0 ------> FMC_A10
PE8 ------> FMC_D5
PG5 ------> FMC_BA1
PG4 ------> FMC_BA0
PH9 ------> FMC_D17
PH11 ------> FMC_D19
PF14 ------> FMC_A8
PF11 ------> FMC_SDNRAS
PE9 ------> FMC_D6
PE11 ------> FMC_D8
PE14 ------> FMC_D11
PH8 ------> FMC_D16
PH10 ------> FMC_D18
PE7 ------> FMC_D4
PE10 ------> FMC_D7
PE12 ------> FMC_D9
PE15 ------> FMC_D12
PE13 ------> FMC_D10
*/
HAL_GPIO_DeInit(GPIOE, GPIO_PIN_1|GPIO_PIN_0|GPIO_PIN_8|GPIO_PIN_9
|GPIO_PIN_11|GPIO_PIN_14|GPIO_PIN_7|GPIO_PIN_10
|GPIO_PIN_12|GPIO_PIN_15|GPIO_PIN_13);
HAL_GPIO_DeInit(GPIOG, GPIO_PIN_15|GPIO_PIN_8|GPIO_PIN_1|GPIO_PIN_0
|GPIO_PIN_5|GPIO_PIN_4);
HAL_GPIO_DeInit(GPIOD, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_15|GPIO_PIN_10
|GPIO_PIN_14|GPIO_PIN_9|GPIO_PIN_8);
HAL_GPIO_DeInit(GPIOI, GPIO_PIN_4|GPIO_PIN_3|GPIO_PIN_2|GPIO_PIN_5
|GPIO_PIN_7|GPIO_PIN_10|GPIO_PIN_6|GPIO_PIN_1
|GPIO_PIN_9|GPIO_PIN_0);
HAL_GPIO_DeInit(GPIOF, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3
|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_12|GPIO_PIN_15
|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_11);
HAL_GPIO_DeInit(GPIOH, GPIO_PIN_15|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_3
|GPIO_PIN_2|GPIO_PIN_12|GPIO_PIN_9|GPIO_PIN_11
|GPIO_PIN_8|GPIO_PIN_10);
HAL_GPIO_DeInit(GPIOC, GPIO_PIN_0);
/* USER CODE BEGIN FMC_MspDeInit 1 */
/* USER CODE END FMC_MspDeInit 1 */
}
void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef* hsdram){
/* USER CODE BEGIN SDRAM_MspDeInit 0 */
/* USER CODE END SDRAM_MspDeInit 0 */
HAL_FMC_MspDeInit();
/* USER CODE BEGIN SDRAM_MspDeInit 1 */
/* USER CODE END SDRAM_MspDeInit 1 */
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */

46
bsp/stm32/stm32f469-st-disco/board/CubeMX_Config/Src/stm32f4xx_it.c
View File

@ -56,7 +56,9 @@
/* USER CODE END 0 */
/* External variables --------------------------------------------------------*/
extern DMA_HandleTypeDef hdma_spi3_rx;
extern I2S_HandleTypeDef hi2s3;
extern PCD_HandleTypeDef hpcd_USB_OTG_FS;
/* USER CODE BEGIN EV */
/* USER CODE END EV */
@ -197,6 +199,48 @@ void SysTick_Handler(void)
/* please refer to the startup file (startup_stm32f4xx.s). */
/******************************************************************************/
/**
* @brief This function handles DMA1 stream0 global interrupt.
*/
void DMA1_Stream0_IRQHandler(void)
{
/* USER CODE BEGIN DMA1_Stream0_IRQn 0 */
/* USER CODE END DMA1_Stream0_IRQn 0 */
HAL_DMA_IRQHandler(&hdma_spi3_rx);
/* USER CODE BEGIN DMA1_Stream0_IRQn 1 */
/* USER CODE END DMA1_Stream0_IRQn 1 */
}
/**
* @brief This function handles SPI3 global interrupt.
*/
void SPI3_IRQHandler(void)
{
/* USER CODE BEGIN SPI3_IRQn 0 */
/* USER CODE END SPI3_IRQn 0 */
HAL_I2S_IRQHandler(&hi2s3);
/* USER CODE BEGIN SPI3_IRQn 1 */
/* USER CODE END SPI3_IRQn 1 */
}
/**
* @brief This function handles USB On The Go FS global interrupt.
*/
void OTG_FS_IRQHandler(void)
{
/* USER CODE BEGIN OTG_FS_IRQn 0 */
/* USER CODE END OTG_FS_IRQn 0 */
HAL_PCD_IRQHandler(&hpcd_USB_OTG_FS);
/* USER CODE BEGIN OTG_FS_IRQn 1 */
/* USER CODE END OTG_FS_IRQn 1 */
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */

42
bsp/stm32/stm32f469-st-disco/board/Kconfig
View File

@ -6,7 +6,25 @@ config SOC_STM32F469NI
default y
menu "Onboard Peripheral Drivers"
config BSP_USING_SDRAM
bool "Enable SDRAM"
select BSP_USING_FMC
default n
config BSP_USING_QSPI_FLASH
bool "Enable QSPI FLASH (N25Q128A qspi1)"
select BSP_USING_QSPI
select RT_USING_SFUD
select RT_SFUD_USING_QSPI
select PKG_USING_FAL
select FAL_USING_SFUD_PORT
default n
config BSP_MOUNT_QSPI_WITH_LFS
bool "Mount QSPI flash to / with little fs"
depends on BSP_USING_QSPI_FLASH
select PKG_USING_LITTLEFS
select RT_USING_MTD_NOR
select RT_USING_DFS
default y
endmenu
menu "On-chip Peripheral Drivers"
@ -25,8 +43,30 @@ menu "On-chip Peripheral Drivers"
bool "Enable UART3"
default y
config BSP_UART3_RX_USING_DMA
bool "Enable UART3 RX DMA"
depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA
default n
endif
config BSP_USING_QSPI
bool "Enable QSPI BUS"
select RT_USING_QSPI
select RT_USING_SPI
default n
config BSP_USING_ON_CHIP_FLASH
bool "Enable on-chip FLASH"
default n
config BSP_USING_FMC
bool
default n
config BSP_USING_USBD_FS
bool "Enable OTGFS as USB device"
select RT_USING_USB_DEVICE
default n
endmenu
menu "Board extended module Drivers"

3
bsp/stm32/stm32f469-st-disco/board/SConscript
View File

@ -10,10 +10,13 @@ cwd = GetCurrentDir()
src = Split('''
board.c
CubeMX_Config/Src/stm32f4xx_hal_msp.c
ports/drv_qspi_flash.c
ports/qspi_mnt.c
''')
path = [cwd]
path += [cwd + '/CubeMX_Config/Inc']
path += [cwd + '/ports']
startup_path_prefix = SDK_LIB

13
bsp/stm32/stm32f469-st-disco/board/board.c
View File

@ -15,6 +15,7 @@ void SystemClock_Config(void)
{
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
/** Configure the main internal regulator output voltage
*/
@ -29,7 +30,7 @@ void SystemClock_Config(void)
RCC_OscInitStruct.PLL.PLLM = 4;
RCC_OscInitStruct.PLL.PLLN = 180;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
RCC_OscInitStruct.PLL.PLLQ = 4;
RCC_OscInitStruct.PLL.PLLQ = 3;
RCC_OscInitStruct.PLL.PLLR = 2;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
@ -54,4 +55,14 @@ void SystemClock_Config(void)
{
Error_Handler();
}
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2S|RCC_PERIPHCLK_CLK48;
PeriphClkInitStruct.PLLI2S.PLLI2SN = 192;
PeriphClkInitStruct.PLLI2S.PLLI2SR = 2;
PeriphClkInitStruct.PLLSAI.PLLSAIN = 96;
PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV4;
PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLSAIP;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
Error_Handler();
}
}

78
bsp/stm32/stm32f469-st-disco/board/ports/drv_qspi_flash.c Normal file
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@ -0,0 +1,78 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-11-27 zylx first version
* 2019-04-11 ZYH port from stm32f7serial
*/
#include <board.h>
#include <drv_qspi.h>
#include <rtdevice.h>
#include <rthw.h>
#include <finsh.h>
#ifdef BSP_USING_QSPI_FLASH
#include "spi_flash.h"
#include "spi_flash_sfud.h"
char n25qxxa_read_status_register2(struct rt_qspi_device *device)
{
/* 0x35 read status register2 */
char instruction = 0x35, status;
rt_qspi_send_then_recv(device, &instruction, 1, &status, 1);
return status;
}
void n25qxxa_write_enable(struct rt_qspi_device *device)
{
/* 0x06 write enable */
char instruction = 0x06;
rt_qspi_send(device, &instruction, 1);
}
void n25qxxa_enter_qspi_mode(struct rt_qspi_device *device)
{
char status = 0;
/* 0x38 enter qspi mode */
char instruction = 0x38;
char write_status2_buf[2] = {0};
/* 0x31 write status register2 */
write_status2_buf[0] = 0x31;
status = n25qxxa_read_status_register2(device);
if (!(status & 0x02))
{
status |= 1 << 1;
n25qxxa_write_enable(device);
write_status2_buf[1] = status;
rt_qspi_send(device, &write_status2_buf, 2);
rt_qspi_send(device, &instruction, 1);
rt_kprintf("flash already enter qspi mode\n");
rt_thread_mdelay(10);
}
}
static int rt_hw_qspi_flash_with_sfud_init(void)
{
stm32_qspi_bus_attach_device("qspi1", "qspi10", RT_NULL, 4, n25qxxa_enter_qspi_mode, RT_NULL);
/* init n25qxx */
if (RT_NULL == rt_sfud_flash_probe(FAL_USING_NOR_FLASH_DEV_NAME, "qspi10"))
{
return -RT_ERROR;
}
return RT_EOK;
}
INIT_COMPONENT_EXPORT(rt_hw_qspi_flash_with_sfud_init);
#endif/* BSP_USING_QSPI_FLASH */

96
bsp/stm32/stm32f469-st-disco/board/ports/fal_cfg.h Normal file
View File

@ -0,0 +1,96 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-04-10 ZYH first version
*/
#ifndef _FAL_CFG_H_
#define _FAL_CFG_H_
#include <rtthread.h>
#include <board.h>
#if defined(BSP_USING_ON_CHIP_FLASH)
#define FLASH_SIZE_GRANULARITY_16K (4 * 16 * 1024)
#define FLASH_SIZE_GRANULARITY_64K (64 * 1024)
#define FLASH_SIZE_GRANULARITY_128K (15 * 128 * 1024)
#define STM32_FLASH_START_ADRESS_16K STM32_FLASH_START_ADRESS
#define STM32_FLASH_START_ADRESS_64K (STM32_FLASH_START_ADRESS_16K + FLASH_SIZE_GRANULARITY_16K)
#define STM32_FLASH_START_ADRESS_128K (STM32_FLASH_START_ADRESS_64K + FLASH_SIZE_GRANULARITY_64K)
extern const struct fal_flash_dev stm32_onchip_flash_16k;
extern const struct fal_flash_dev stm32_onchip_flash_64k;
extern const struct fal_flash_dev stm32_onchip_flash_128k;
#endif
#if defined(BSP_USING_QSPI_FLASH)
extern struct fal_flash_dev nor_flash0;
#endif
/* flash device table */
#if defined(BSP_USING_QSPI_FLASH) && defined(BSP_USING_ON_CHIP_FLASH)
#define FAL_FLASH_DEV_TABLE \
{ \
&stm32_onchip_flash_16k, \
&stm32_onchip_flash_64k, \
&stm32_onchip_flash_128k, \
&nor_flash0, \
}
#ifdef FAL_PART_HAS_TABLE_CFG
/* partition table */
#define FAL_PART_TABLE \
{ \
{FAL_PART_MAGIC_WROD, "bootloader", "onchip_flash_16k", 0 , FLASH_SIZE_GRANULARITY_16K , 0}, \
{FAL_PART_MAGIC_WROD, "param", "onchip_flash_64k", 0 , FLASH_SIZE_GRANULARITY_64K , 0}, \
{FAL_PART_MAGIC_WROD, "app", "onchip_flash_128k", 0 , FLASH_SIZE_GRANULARITY_128K, 0}, \
{FAL_PART_MAGIC_WROD, "qspiflash", FAL_USING_NOR_FLASH_DEV_NAME, 0 , (16 * 1024 * 1024), 0}, \
}
#endif /* FAL_PART_HAS_TABLE_CFG */
#elif defined(BSP_USING_QSPI_FLASH)
#define FAL_FLASH_DEV_TABLE \
{ \
&nor_flash0, \
}
#ifdef FAL_PART_HAS_TABLE_CFG
/* partition table */
#define FAL_PART_TABLE \
{ \
{FAL_PART_MAGIC_WROD, "qspiflash", FAL_USING_NOR_FLASH_DEV_NAME, 0 , (16 * 1024 * 1024), 0}, \
}
#endif /* FAL_PART_HAS_TABLE_CFG */
#elif defined(BSP_USING_ON_CHIP_FLASH)
#define FAL_FLASH_DEV_TABLE \
{ \
&stm32_onchip_flash_16k, \
&stm32_onchip_flash_64k, \
&stm32_onchip_flash_128k, \
}
#ifdef FAL_PART_HAS_TABLE_CFG
/* partition table */
#define FAL_PART_TABLE \
{ \
{FAL_PART_MAGIC_WROD, "bootloader", "onchip_flash_16k", 0 , FLASH_SIZE_GRANULARITY_16K , 0}, \
{FAL_PART_MAGIC_WROD, "param", "onchip_flash_64k", 0 , FLASH_SIZE_GRANULARITY_64K , 0}, \
{FAL_PART_MAGIC_WROD, "app", "onchip_flash_128k", 0 , FLASH_SIZE_GRANULARITY_128K, 0}, \
}
#endif /* FAL_PART_HAS_TABLE_CFG */
#else
#define FAL_FLASH_DEV_TABLE { 0 }
#define FAL_PART_TABLE { 0 }
#endif
#endif /* _FAL_CFG_H_ */

41
bsp/stm32/stm32f469-st-disco/board/ports/qspi_mnt.c Normal file
View File

@ -0,0 +1,41 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-04-11 ZYH first version
*/
#include <rtthread.h>
#if defined(PKG_USING_FAL)
#include <fal.h>
#include <dfs_fs.h>
int mnt_init(void)
{
fal_init();
#if defined(BSP_MOUNT_QSPI_WITH_LFS)
fal_mtd_nor_device_create("qspiflash");
if (dfs_mount("qspiflash", "/", "lfs", 0, 0) == 0)
{
rt_kprintf("Mount \"qspiflash\" on \"/\" success\n");
}
else
{
dfs_mkfs("lfs","qspiflash");
if (dfs_mount("qspiflash", "/", "lfs", 0, 0) == 0)
{
rt_kprintf("Mount \"qspiflash\" on \"/\" success\n");
}
else
{
rt_kprintf("Mount \"qspiflash\" on \"/\" fail\n");
return -1;
}
}
#endif
return 0;
}
INIT_ENV_EXPORT(mnt_init);
#endif

66
bsp/stm32/stm32f469-st-disco/board/ports/sdram_port.h Normal file
View File

@ -0,0 +1,66 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-04-09 ZYH first version
*/
#ifndef __SDRAM_PORT_H__
#define __SDRAM_PORT_H__
/* parameters for sdram peripheral */
/* Bank1 or Bank2 */
#define SDRAM_TARGET_BANK 1
/* stm32f4 Bank1:0XC0000000 Bank2:0XD0000000 */
#define SDRAM_BANK_ADDR ((uint32_t)0XC0000000)
/* data width: 8, 16, 32 */
#define SDRAM_DATA_WIDTH 32
/* column bit numbers: 8, 9, 10, 11 */
#define SDRAM_COLUMN_BITS 8
/* row bit numbers: 11, 12, 13 */
#define SDRAM_ROW_BITS 12
/* cas latency clock number: 1, 2, 3 */
#define SDRAM_CAS_LATENCY 3
/* read pipe delay: 0, 1, 2 */
#define SDRAM_RPIPE_DELAY 0
/* clock divid: 2, 3 */
#define SDCLOCK_PERIOD 2
/* refresh rate counter */
#define SDRAM_REFRESH_COUNT ((uint32_t)0x0569)
#define SDRAM_SIZE ((uint32_t)0x1000000)
/* Timing configuration for W9825G6KH-6 */
/* 90 MHz of SD clock frequency (180MHz/2) */
/* TMRD: 2 Clock cycles */
#define LOADTOACTIVEDELAY 2
/* TXSR: 7x11.90ns */
#define EXITSELFREFRESHDELAY 7
/* TRAS: 4x11.90ns */
#define SELFREFRESHTIME 4
/* TRC: 7x11.90ns */
#define ROWCYCLEDELAY 7
/* TWR: 3 Clock cycles */
#define WRITERECOVERYTIME 2
/* TRP: 2x11.90ns */
#define RPDELAY 2
/* TRCD: 2x11.90ns */
#define RCDDELAY 2
/* memory mode register */
#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0003)
#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
#define SDRAM_MODEREG_CAS_LATENCY_1 ((uint16_t)0x0010)
#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
#endif

226
bsp/stm32/stm32f469-st-disco/rtconfig.h
View File

@ -7,8 +7,12 @@
/* RT-Thread Kernel */
#define RT_NAME_MAX 8
/* RT_USING_ARCH_DATA_TYPE is not set */
/* RT_USING_SMP is not set */
#define RT_ALIGN_SIZE 4
/* RT_THREAD_PRIORITY_8 is not set */
#define RT_THREAD_PRIORITY_32
/* RT_THREAD_PRIORITY_256 is not set */
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
@ -16,8 +20,19 @@
#define RT_USING_IDLE_HOOK
#define RT_IDEL_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 256
/* RT_USING_TIMER_SOFT is not set */
#define RT_DEBUG
#define RT_DEBUG_COLOR
/* RT_DEBUG_INIT_CONFIG is not set */
/* RT_DEBUG_THREAD_CONFIG is not set */
/* RT_DEBUG_SCHEDULER_CONFIG is not set */
/* RT_DEBUG_IPC_CONFIG is not set */
/* RT_DEBUG_TIMER_CONFIG is not set */
/* RT_DEBUG_IRQ_CONFIG is not set */
/* RT_DEBUG_MEM_CONFIG is not set */
/* RT_DEBUG_SLAB_CONFIG is not set */
/* RT_DEBUG_MEMHEAP_CONFIG is not set */
/* RT_DEBUG_MODULE_CONFIG is not set */
/* Inter-Thread communication */
@ -26,16 +41,23 @@
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* RT_USING_SIGNALS is not set */
/* Memory Management */
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_USING_MEMHEAP
/* RT_USING_NOHEAP is not set */
/* RT_USING_SMALL_MEM is not set */
/* RT_USING_SLAB is not set */
#define RT_USING_MEMHEAP_AS_HEAP
#define RT_USING_HEAP
/* Kernel Device Object */
#define RT_USING_DEVICE
/* RT_USING_DEVICE_OPS is not set */
/* RT_USING_INTERRUPT_INFO is not set */
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart3"
@ -43,6 +65,7 @@
#define ARCH_ARM
#define ARCH_ARM_CORTEX_M
#define ARCH_ARM_CORTEX_M4
/* ARCH_CPU_STACK_GROWS_UPWARD is not set */
/* RT-Thread Components */
@ -53,6 +76,7 @@
/* C++ features */
/* RT_USING_CPLUSPLUS is not set */
/* Command shell */
@ -62,9 +86,11 @@
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_USING_DESCRIPTION
/* FINSH_ECHO_DISABLE_DEFAULT is not set */
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_CMD_SIZE 80
/* FINSH_USING_AUTH is not set */
#define FINSH_USING_MSH
#define FINSH_USING_MSH_DEFAULT
#define FINSH_USING_MSH_ONLY
@ -72,92 +98,278 @@
/* Device virtual file system */
#define RT_USING_DFS
#define DFS_USING_WORKDIR
#define DFS_FILESYSTEMS_MAX 8
#define DFS_FILESYSTEM_TYPES_MAX 8
#define DFS_FD_MAX 64
/* RT_USING_DFS_MNTTABLE is not set */
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
/* RT_DFS_ELM_USE_LFN_0 is not set */
/* RT_DFS_ELM_USE_LFN_1 is not set */
/* RT_DFS_ELM_USE_LFN_2 is not set */
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
/* RT_DFS_ELM_USE_ERASE is not set */
#define RT_DFS_ELM_REENTRANT
#define RT_USING_DFS_DEVFS
/* RT_USING_DFS_ROMFS is not set */
/* RT_USING_DFS_RAMFS is not set */
/* RT_USING_DFS_UFFS is not set */
/* RT_USING_DFS_JFFS2 is not set */
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_PIPE_BUFSZ 512
/* RT_USING_SYSTEM_WORKQUEUE is not set */
#define RT_USING_SERIAL
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
/* RT_USING_CAN is not set */
/* RT_USING_HWTIMER is not set */
/* RT_USING_CPUTIME is not set */
/* RT_USING_I2C is not set */
#define RT_USING_PIN
/* RT_USING_ADC is not set */
/* RT_USING_PWM is not set */
/* RT_USING_MTD_NOR is not set */
/* RT_USING_MTD_NAND is not set */
/* RT_USING_MTD is not set */
/* RT_USING_PM is not set */
/* RT_USING_RTC is not set */
/* RT_USING_SDIO is not set */
/* RT_USING_SPI is not set */
/* RT_USING_WDT is not set */
/* RT_USING_AUDIO is not set */
/* RT_USING_SENSOR is not set */
/* Using WiFi */
/* RT_USING_WIFI is not set */
/* Using USB */
/* RT_USING_USB_HOST is not set */
/* RT_USING_USB_DEVICE is not set */
/* _RT_USB_DEVICE_NONE is not set */
/* _RT_USB_DEVICE_CDC is not set */
/* _RT_USB_DEVICE_MSTORAGE is not set */
/* _RT_USB_DEVICE_HID is not set */
/* _RT_USB_DEVICE_WINUSB is not set */
/* POSIX layer and C standard library */
#define RT_USING_LIBC
/* RT_USING_PTHREADS is not set */
#define RT_USING_POSIX
/* RT_USING_POSIX_MMAP is not set */
/* RT_USING_POSIX_TERMIOS is not set */
/* RT_USING_POSIX_AIO is not set */
/* RT_USING_MODULE is not set */
/* Network */
/* Socket abstraction layer */
/* RT_USING_SAL is not set */
/* light weight TCP/IP stack */
/* RT_USING_LWIP is not set */
/* Modbus master and slave stack */
/* RT_USING_MODBUS is not set */
/* AT commands */
/* RT_USING_AT is not set */
/* VBUS(Virtual Software BUS) */
/* RT_USING_VBUS is not set */
/* Utilities */
/* RT_USING_LOGTRACE is not set */
/* RT_USING_RYM is not set */
/* RT_USING_ULOG is not set */
/* RT_USING_UTEST is not set */
/* RT_USING_LWP is not set */
/* RT-Thread online packages */
/* IoT - internet of things */
/* PKG_USING_PAHOMQTT is not set */
/* PKG_USING_WEBCLIENT is not set */
/* PKG_USING_WEBNET is not set */
/* PKG_USING_MONGOOSE is not set */
/* PKG_USING_WEBTERMINAL is not set */
/* PKG_USING_CJSON is not set */
/* PKG_USING_JSMN is not set */
/* PKG_USING_LIBMODBUS is not set */
/* PKG_USING_LJSON is not set */
/* PKG_USING_EZXML is not set */
/* PKG_USING_NANOPB is not set */
/* Wi-Fi */
/* Marvell WiFi */
/* PKG_USING_WLANMARVELL is not set */
/* Wiced WiFi */
/* PKG_USING_WLAN_WICED is not set */
/* PKG_USING_RW007 is not set */
/* PKG_USING_COAP is not set */
/* PKG_USING_NOPOLL is not set */
/* PKG_USING_NETUTILS is not set */
/* PKG_USING_AT_DEVICE is not set */
/* PKG_USING_WIZNET is not set */
/* IoT Cloud */
/* PKG_USING_ONENET is not set */
/* PKG_USING_GAGENT_CLOUD is not set */
/* PKG_USING_ALI_IOTKIT is not set */
/* PKG_USING_AZURE is not set */
/* PKG_USING_TENCENT_IOTKIT is not set */
/* PKG_USING_NIMBLE is not set */
/* PKG_USING_OTA_DOWNLOADER is not set */
/* security packages */
/* PKG_USING_MBEDTLS is not set */
/* PKG_USING_libsodium is not set */
/* PKG_USING_TINYCRYPT is not set */
/* language packages */
/* PKG_USING_LUA is not set */
/* PKG_USING_JERRYSCRIPT is not set */
/* PKG_USING_MICROPYTHON is not set */
/* multimedia packages */
/* PKG_USING_OPENMV is not set */
/* PKG_USING_MUPDF is not set */
/* PKG_USING_STEMWIN is not set */
/* tools packages */
/* PKG_USING_CMBACKTRACE is not set */
/* PKG_USING_EASYFLASH is not set */
/* PKG_USING_EASYLOGGER is not set */
/* PKG_USING_SYSTEMVIEW is not set */
/* PKG_USING_RDB is not set */
/* PKG_USING_QRCODE is not set */
/* PKG_USING_ULOG_EASYFLASH is not set */
/* PKG_USING_ADBD is not set */
/* system packages */
/* PKG_USING_GUIENGINE is not set */
/* PKG_USING_PERSIMMON is not set */
/* PKG_USING_CAIRO is not set */
/* PKG_USING_PIXMAN is not set */
/* PKG_USING_LWEXT4 is not set */
/* PKG_USING_PARTITION is not set */
/* PKG_USING_FAL is not set */
/* PKG_USING_FAL_LATEST_VERSION is not set */
/* PKG_USING_FAL_V00300 is not set */
/* PKG_USING_FAL_V00200 is not set */
/* PKG_USING_FAL_V00100 is not set */
/* PKG_USING_SQLITE is not set */
/* PKG_USING_RTI is not set */
/* PKG_USING_LITTLEVGL2RTT is not set */
/* PKG_USING_CMSIS is not set */
/* PKG_USING_DFS_YAFFS is not set */
/* PKG_USING_LITTLEFS is not set */
/* PKG_USING_LITTLEFS_V090 is not set */
/* PKG_USING_LITTLEFS_V170 is not set */
/* PKG_USING_LITTLEFS_LATEST_VERSION is not set */
/* PKG_USING_THREAD_POOL is not set */
/* peripheral libraries and drivers */
/* sensors drivers */
/* PKG_USING_SENSORS_DRIVERS is not set */
/* PKG_USING_REALTEK_AMEBA is not set */
/* PKG_USING_SHT2X is not set */
/* PKG_USING_AHT10 is not set */
/* PKG_USING_AP3216C is not set */
/* PKG_USING_STM32_SDIO is not set */
/* PKG_USING_ICM20608 is not set */
/* PKG_USING_U8G2 is not set */
/* PKG_USING_BUTTON is not set */
/* PKG_USING_MPU6XXX is not set */
/* PKG_USING_PCF8574 is not set */
/* PKG_USING_SX12XX is not set */
/* PKG_USING_SIGNAL_LED is not set */
/* PKG_USING_WM_LIBRARIES is not set */
/* PKG_USING_KENDRYTE_SDK is not set */
/* PKG_USING_INFRARED is not set */
/* PKG_USING_ROSSERIAL is not set */
/* miscellaneous packages */
/* PKG_USING_LIBCSV is not set */
/* PKG_USING_OPTPARSE is not set */
/* PKG_USING_FASTLZ is not set */
/* PKG_USING_MINILZO is not set */
/* PKG_USING_QUICKLZ is not set */
/* PKG_USING_MULTIBUTTON is not set */
/* PKG_USING_CANFESTIVAL is not set */
/* PKG_USING_ZLIB is not set */
/* PKG_USING_DSTR is not set */
/* PKG_USING_TINYFRAME is not set */
/* PKG_USING_KENDRYTE_DEMO is not set */
/* samples: kernel and components samples */
/* PKG_USING_KERNEL_SAMPLES is not set */
/* PKG_USING_FILESYSTEM_SAMPLES is not set */
/* PKG_USING_NETWORK_SAMPLES is not set */
/* PKG_USING_PERIPHERAL_SAMPLES is not set */
/* PKG_USING_HELLO is not set */
/* PKG_USING_VI is not set */
/* PKG_USING_NNOM is not set */
/* Privated Packages of RealThread */
/* PKG_USING_CODEC is not set */
/* PKG_USING_PLAYER is not set */
/* PKG_USING_MPLAYER is not set */
/* PKG_USING_PERSIMMON_SRC is not set */
/* PKG_USING_JS_PERSIMMON is not set */
/* PKG_USING_JERRYSCRIPT_WIN32 is not set */
/* Network Utilities */
/* PKG_USING_WICED is not set */
/* PKG_USING_CLOUDSDK is not set */
/* PKG_USING_COREMARK is not set */
/* PKG_USING_POWER_MANAGER is not set */
/* PKG_USING_RT_OTA is not set */
/* PKG_USING_RDBD_SRC is not set */
/* PKG_USING_RTINSIGHT is not set */
/* PKG_USING_SMARTCONFIG is not set */
/* PKG_USING_RTX is not set */
/* RT_USING_TESTCASE is not set */
/* PKG_USING_NGHTTP2 is not set */
/* PKG_USING_AVS is not set */
/* PKG_USING_STS is not set */
/* PKG_USING_DLMS is not set */
#define SOC_FAMILY_STM32
#define SOC_SERIES_STM32F4
@ -167,11 +379,19 @@
/* Onboard Peripheral Drivers */
#define BSP_USING_SDRAM
/* BSP_USING_QSPI_FLASH is not set */
/* On-chip Peripheral Drivers */
#define BSP_USING_GPIO
#define BSP_USING_UART
#define BSP_USING_UART3
/* BSP_UART3_RX_USING_DMA is not set */
/* BSP_USING_QSPI is not set */
/* BSP_USING_ON_CHIP_FLASH is not set */
#define BSP_USING_FMC
/* BSP_USING_USBD_FS is not set */
/* Board extended module Drivers */