[bsp/at32] 1.add support hwi2c driver, 2.update all firmware libraries. (#9241)
* 1.add support hwi2c driver, 2.update all firmware libraries * update some files and fixed errors * add support a423 at hwi2c driver * add .ignore_format.yml
This commit is contained in:
sheltonyu
GitHub
parent
c8914c7f2b
commit
d1c7712bfb
@ -41,6 +41,7 @@ AT32A403A-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以
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| UART | 支持 | USART1/2/3 |
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| GPIO | 支持 | PA0...PF7 |
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| IIC | 支持 | GPIO模拟I2C |
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| HWIIC | 支持 | I2C1/2/3 |
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| SPI | 支持 | SPI1/2 |
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| ADC | 支持 | ADC1/2 |
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| DAC | 支持 | DAC1 |
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@ -265,6 +265,57 @@ menu "On-chip Peripheral Drivers"
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endif
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endif
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menuconfig BSP_USING_HARD_I2C
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bool "Enable I2C BUS (hardware driver)"
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default n
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select RT_USING_I2C
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if BSP_USING_HARD_I2C
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config BSP_USING_HARD_I2C1
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bool "Enable I2C1 BUS"
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default n
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config BSP_I2C1_TX_USING_DMA
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bool "Enable I2C1 TX DMA"
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depends on BSP_USING_HARD_I2C1
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default n
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config BSP_I2C1_RX_USING_DMA
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bool "Enable I2C1 RX DMA"
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depends on BSP_USING_HARD_I2C1
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select BSP_I2C1_TX_USING_DMA
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default n
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config BSP_USING_HARD_I2C2
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bool "Enable I2C2 BUS"
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default n
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config BSP_I2C2_TX_USING_DMA
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bool "Enable I2C2 TX DMA"
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depends on BSP_USING_HARD_I2C2
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default n
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config BSP_I2C2_RX_USING_DMA
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bool "Enable I2C2 RX DMA"
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depends on BSP_USING_HARD_I2C2
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select BSP_I2C2_TX_USING_DMA
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default n
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config BSP_USING_HARD_I2C3
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bool "Enable I2C3 BUS"
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default n
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config BSP_I2C3_TX_USING_DMA
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bool "Enable I2C3 TX DMA"
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depends on BSP_USING_HARD_I2C3
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default n
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config BSP_I2C3_RX_USING_DMA
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bool "Enable I2C3 RX DMA"
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depends on BSP_USING_HARD_I2C3
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select BSP_I2C3_TX_USING_DMA
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default n
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endif
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menuconfig BSP_USING_ADC
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bool "Enable ADC"
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default n
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@ -129,6 +129,60 @@ void at32_msp_spi_init(void *instance)
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}
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#endif /* BSP_USING_SPI */
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#ifdef BSP_USING_HARD_I2C
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void at32_msp_i2c_init(void *instance)
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{
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gpio_init_type gpio_init_struct;
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i2c_type *i2c_x = (i2c_type *)instance;
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gpio_default_para_init(&gpio_init_struct);
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gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
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#ifdef BSP_USING_HARD_I2C1
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if(I2C1 == i2c_x)
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{
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crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE);
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crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
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gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
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gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
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gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
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gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7;
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gpio_init(GPIOB, &gpio_init_struct);
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}
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#endif
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#ifdef BSP_USING_HARD_I2C2
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if(I2C2 == i2c_x)
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{
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crm_periph_clock_enable(CRM_I2C2_PERIPH_CLOCK, TRUE);
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crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
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gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
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gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
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gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
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gpio_init_struct.gpio_pins = GPIO_PINS_10 | GPIO_PINS_11;
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gpio_init(GPIOB, &gpio_init_struct);
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}
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#endif
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#ifdef BSP_USING_HARD_I2C3
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if(I2C3 == i2c_x)
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{
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crm_periph_clock_enable(CRM_I2C3_PERIPH_CLOCK, TRUE);
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crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE);
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crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE);
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gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
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gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
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gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
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gpio_init_struct.gpio_pins = GPIO_PINS_8;
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gpio_init(GPIOA, &gpio_init_struct);
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gpio_init_struct.gpio_pins = GPIO_PINS_9;
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gpio_init(GPIOC, &gpio_init_struct);
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}
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#endif
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/* add others */
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}
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#endif /* BSP_USING_HARD_I2C */
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#ifdef BSP_USING_SDIO
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void at32_msp_sdio_init(void *instance)
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{
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@ -41,6 +41,7 @@ AT32A423-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以
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| UART | 支持 | USART1/2/3 |
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| GPIO | 支持 | PA0...PF10 |
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| IIC | 支持 | GPIO模拟I2C |
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| HWIIC | 支持 | I2C1/2/3 |
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| SPI | 支持 | SPI1/2 |
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| ADC | 支持 | ADC1 |
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| DAC | 支持 | DAC1 |
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@ -277,6 +277,57 @@ menu "On-chip Peripheral Drivers"
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endif
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endif
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menuconfig BSP_USING_HARD_I2C
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bool "Enable I2C BUS (hardware driver)"
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default n
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select RT_USING_I2C
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if BSP_USING_HARD_I2C
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config BSP_USING_HARD_I2C1
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bool "Enable I2C1 BUS"
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default n
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config BSP_I2C1_TX_USING_DMA
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bool "Enable I2C1 TX DMA"
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depends on BSP_USING_HARD_I2C1
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default n
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config BSP_I2C1_RX_USING_DMA
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bool "Enable I2C1 RX DMA"
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depends on BSP_USING_HARD_I2C1
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select BSP_I2C1_TX_USING_DMA
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default n
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config BSP_USING_HARD_I2C2
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bool "Enable I2C2 BUS"
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default n
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config BSP_I2C2_TX_USING_DMA
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bool "Enable I2C2 TX DMA"
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depends on BSP_USING_HARD_I2C2
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default n
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config BSP_I2C2_RX_USING_DMA
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bool "Enable I2C2 RX DMA"
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depends on BSP_USING_HARD_I2C2
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select BSP_I2C2_TX_USING_DMA
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default n
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config BSP_USING_HARD_I2C3
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bool "Enable I2C3 BUS"
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default n
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config BSP_I2C3_TX_USING_DMA
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bool "Enable I2C3 TX DMA"
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depends on BSP_USING_HARD_I2C3
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default n
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config BSP_I2C3_RX_USING_DMA
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bool "Enable I2C3 RX DMA"
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depends on BSP_USING_HARD_I2C3
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select BSP_I2C3_TX_USING_DMA
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default n
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endif
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menuconfig BSP_USING_ADC
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bool "Enable ADC"
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default n
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@ -19,5 +19,6 @@ void at32_msp_hwtmr_init(void *instance);
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void at32_msp_can_init(void *instance);
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void at32_msp_usb_init(void *instance);
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void at32_msp_dac_init(void *instance);
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void at32_msp_i2c_init(void *instance);
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#endif /* __AT32_MSP_H__ */
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@ -134,6 +134,68 @@ void at32_msp_spi_init(void *instance)
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/* add others */
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}
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#endif /* BSP_USING_SPI */
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#ifdef BSP_USING_HARD_I2C
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void at32_msp_i2c_init(void *instance)
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{
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gpio_init_type gpio_init_struct;
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i2c_type *i2c_x = (i2c_type *)instance;
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gpio_default_para_init(&gpio_init_struct);
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gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
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#ifdef BSP_USING_HARD_I2C1
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if(I2C1 == i2c_x)
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{
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crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE);
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crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
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gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
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gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
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gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
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gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7;
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gpio_init(GPIOB, &gpio_init_struct);
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gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE6, GPIO_MUX_4);
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gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE7, GPIO_MUX_4);
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}
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#endif
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#ifdef BSP_USING_HARD_I2C2
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if(I2C2 == i2c_x)
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{
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crm_periph_clock_enable(CRM_I2C2_PERIPH_CLOCK, TRUE);
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crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
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gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
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gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
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gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
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gpio_init_struct.gpio_pins = GPIO_PINS_10 | GPIO_PINS_11;
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gpio_init(GPIOB, &gpio_init_struct);
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gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE10, GPIO_MUX_4);
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gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE11, GPIO_MUX_4);
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}
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#endif
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#ifdef BSP_USING_HARD_I2C3
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if(I2C3 == i2c_x)
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{
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crm_periph_clock_enable(CRM_I2C3_PERIPH_CLOCK, TRUE);
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crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE);
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crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE);
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gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
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gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
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gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
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gpio_init_struct.gpio_pins = GPIO_PINS_8;
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gpio_init(GPIOA, &gpio_init_struct);
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gpio_init_struct.gpio_pins = GPIO_PINS_9;
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gpio_init(GPIOC, &gpio_init_struct);
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gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE8, GPIO_MUX_4);
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gpio_pin_mux_config(GPIOC, GPIO_PINS_SOURCE9, GPIO_MUX_4);
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}
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#endif
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/* add others */
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}
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#endif /* BSP_USING_HARD_I2C */
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#ifdef BSP_USING_PWM
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void at32_msp_tmr_init(void *instance)
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@ -41,6 +41,7 @@ AT32F402-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以
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| UART | 支持 | USART1/2/3 |
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| GPIO | 支持 | PA0...PF7 |
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| IIC | 支持 | GPIO模拟I2C |
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| HWIIC | 支持 | I2C1/2/3 |
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| SPI | 支持 | SPI1/2 |
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| ADC | 支持 | ADC1 |
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| PWM | 支持 | TMR1/2 |
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@ -288,6 +288,57 @@ menu "On-chip Peripheral Drivers"
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endif
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endif
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menuconfig BSP_USING_HARD_I2C
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bool "Enable I2C BUS (hardware driver)"
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default n
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select RT_USING_I2C
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if BSP_USING_HARD_I2C
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config BSP_USING_HARD_I2C1
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bool "Enable I2C1 BUS"
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default n
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config BSP_I2C1_TX_USING_DMA
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bool "Enable I2C1 TX DMA"
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depends on BSP_USING_HARD_I2C1
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default n
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config BSP_I2C1_RX_USING_DMA
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bool "Enable I2C1 RX DMA"
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depends on BSP_USING_HARD_I2C1
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select BSP_I2C1_TX_USING_DMA
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default n
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config BSP_USING_HARD_I2C2
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bool "Enable I2C2 BUS"
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default n
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config BSP_I2C2_TX_USING_DMA
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bool "Enable I2C2 TX DMA"
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depends on BSP_USING_HARD_I2C2
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default n
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config BSP_I2C2_RX_USING_DMA
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bool "Enable I2C2 RX DMA"
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depends on BSP_USING_HARD_I2C2
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select BSP_I2C2_TX_USING_DMA
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default n
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config BSP_USING_HARD_I2C3
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bool "Enable I2C3 BUS"
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default n
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config BSP_I2C3_TX_USING_DMA
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bool "Enable I2C3 TX DMA"
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depends on BSP_USING_HARD_I2C3
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default n
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config BSP_I2C3_RX_USING_DMA
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bool "Enable I2C3 RX DMA"
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depends on BSP_USING_HARD_I2C3
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select BSP_I2C3_TX_USING_DMA
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default n
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endif
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menuconfig BSP_USING_ADC
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bool "Enable ADC"
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default n
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@ -127,6 +127,69 @@ void at32_msp_spi_init(void *instance)
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}
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#endif /* BSP_USING_SPI */
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#ifdef BSP_USING_HARD_I2C
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void at32_msp_i2c_init(void *instance)
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{
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gpio_init_type gpio_init_struct;
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i2c_type *i2c_x = (i2c_type *)instance;
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gpio_default_para_init(&gpio_init_struct);
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gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
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#ifdef BSP_USING_HARD_I2C1
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if(I2C1 == i2c_x)
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{
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crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE);
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crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
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gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
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gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
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gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
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gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7;
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gpio_init(GPIOB, &gpio_init_struct);
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gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE6, GPIO_MUX_4);
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gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE7, GPIO_MUX_4);
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}
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#endif
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#ifdef BSP_USING_HARD_I2C2
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if(I2C2 == i2c_x)
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{
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crm_periph_clock_enable(CRM_I2C2_PERIPH_CLOCK, TRUE);
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crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
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gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
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gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
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gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
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gpio_init_struct.gpio_pins = GPIO_PINS_3 | GPIO_PINS_10;
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gpio_init(GPIOB, &gpio_init_struct);
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gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE3, GPIO_MUX_4);
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gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE10, GPIO_MUX_4);
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}
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#endif
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#ifdef BSP_USING_HARD_I2C3
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if(I2C3 == i2c_x)
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{
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crm_periph_clock_enable(CRM_I2C3_PERIPH_CLOCK, TRUE);
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crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE);
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crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE);
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gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
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gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
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gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
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gpio_init_struct.gpio_pins = GPIO_PINS_8;
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gpio_init(GPIOA, &gpio_init_struct);
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gpio_init_struct.gpio_pins = GPIO_PINS_9;
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gpio_init(GPIOC, &gpio_init_struct);
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gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE8, GPIO_MUX_4);
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gpio_pin_mux_config(GPIOC, GPIO_PINS_SOURCE9, GPIO_MUX_4);
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}
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#endif
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/* add others */
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||||
}
|
||||
#endif /* BSP_USING_HARD_I2C */
|
||||
|
||||
#ifdef BSP_USING_PWM
|
||||
void at32_msp_tmr_init(void *instance)
|
||||
{
|
||||
|
||||
@ -41,6 +41,7 @@ AT32F403A-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以
|
||||
| UART | 支持 | USART1/2/3 |
|
||||
| GPIO | 支持 | PA0...PF7 |
|
||||
| IIC | 支持 | GPIO模拟I2C |
|
||||
| HWIIC | 支持 | I2C1/2/3 |
|
||||
| SPI | 支持 | SPI1/2 |
|
||||
| ADC | 支持 | ADC1/2 |
|
||||
| DAC | 支持 | DAC1 |
|
||||
|
||||
@ -265,6 +265,57 @@ menu "On-chip Peripheral Drivers"
|
||||
endif
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_HARD_I2C
|
||||
bool "Enable I2C BUS (hardware driver)"
|
||||
default n
|
||||
select RT_USING_I2C
|
||||
if BSP_USING_HARD_I2C
|
||||
config BSP_USING_HARD_I2C1
|
||||
bool "Enable I2C1 BUS"
|
||||
default n
|
||||
|
||||
config BSP_I2C1_TX_USING_DMA
|
||||
bool "Enable I2C1 TX DMA"
|
||||
depends on BSP_USING_HARD_I2C1
|
||||
default n
|
||||
|
||||
config BSP_I2C1_RX_USING_DMA
|
||||
bool "Enable I2C1 RX DMA"
|
||||
depends on BSP_USING_HARD_I2C1
|
||||
select BSP_I2C1_TX_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_USING_HARD_I2C2
|
||||
bool "Enable I2C2 BUS"
|
||||
default n
|
||||
|
||||
config BSP_I2C2_TX_USING_DMA
|
||||
bool "Enable I2C2 TX DMA"
|
||||
depends on BSP_USING_HARD_I2C2
|
||||
default n
|
||||
|
||||
config BSP_I2C2_RX_USING_DMA
|
||||
bool "Enable I2C2 RX DMA"
|
||||
depends on BSP_USING_HARD_I2C2
|
||||
select BSP_I2C2_TX_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_USING_HARD_I2C3
|
||||
bool "Enable I2C3 BUS"
|
||||
default n
|
||||
|
||||
config BSP_I2C3_TX_USING_DMA
|
||||
bool "Enable I2C3 TX DMA"
|
||||
depends on BSP_USING_HARD_I2C3
|
||||
default n
|
||||
|
||||
config BSP_I2C3_RX_USING_DMA
|
||||
bool "Enable I2C3 RX DMA"
|
||||
depends on BSP_USING_HARD_I2C3
|
||||
select BSP_I2C3_TX_USING_DMA
|
||||
default n
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_ADC
|
||||
bool "Enable ADC"
|
||||
default n
|
||||
|
||||
@ -129,6 +129,60 @@ void at32_msp_spi_init(void *instance)
|
||||
}
|
||||
#endif /* BSP_USING_SPI */
|
||||
|
||||
#ifdef BSP_USING_HARD_I2C
|
||||
void at32_msp_i2c_init(void *instance)
|
||||
{
|
||||
gpio_init_type gpio_init_struct;
|
||||
i2c_type *i2c_x = (i2c_type *)instance;
|
||||
|
||||
gpio_default_para_init(&gpio_init_struct);
|
||||
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
|
||||
#ifdef BSP_USING_HARD_I2C1
|
||||
if(I2C1 == i2c_x)
|
||||
{
|
||||
crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE);
|
||||
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
|
||||
|
||||
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
|
||||
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
|
||||
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
|
||||
gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7;
|
||||
gpio_init(GPIOB, &gpio_init_struct);
|
||||
}
|
||||
#endif
|
||||
#ifdef BSP_USING_HARD_I2C2
|
||||
if(I2C2 == i2c_x)
|
||||
{
|
||||
crm_periph_clock_enable(CRM_I2C2_PERIPH_CLOCK, TRUE);
|
||||
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
|
||||
|
||||
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
|
||||
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
|
||||
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
|
||||
gpio_init_struct.gpio_pins = GPIO_PINS_10 | GPIO_PINS_11;
|
||||
gpio_init(GPIOB, &gpio_init_struct);
|
||||
}
|
||||
#endif
|
||||
#ifdef BSP_USING_HARD_I2C3
|
||||
if(I2C3 == i2c_x)
|
||||
{
|
||||
crm_periph_clock_enable(CRM_I2C3_PERIPH_CLOCK, TRUE);
|
||||
crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE);
|
||||
crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE);
|
||||
|
||||
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
|
||||
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
|
||||
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
|
||||
gpio_init_struct.gpio_pins = GPIO_PINS_8;
|
||||
gpio_init(GPIOA, &gpio_init_struct);
|
||||
gpio_init_struct.gpio_pins = GPIO_PINS_9;
|
||||
gpio_init(GPIOC, &gpio_init_struct);
|
||||
}
|
||||
#endif
|
||||
/* add others */
|
||||
}
|
||||
#endif /* BSP_USING_HARD_I2C */
|
||||
|
||||
#ifdef BSP_USING_SDIO
|
||||
void at32_msp_sdio_init(void *instance)
|
||||
{
|
||||
|
||||
@ -41,6 +41,7 @@ AT32F405-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以
|
||||
| UART | 支持 | USART1/2/3 |
|
||||
| GPIO | 支持 | PA0...PF7 |
|
||||
| IIC | 支持 | GPIO模拟I2C |
|
||||
| HWIIC | 支持 | I2C1/2/3 |
|
||||
| SPI | 支持 | SPI1/2 |
|
||||
| ADC | 支持 | ADC1 |
|
||||
| PWM | 支持 | TMR1/2 |
|
||||
|
||||
@ -307,6 +307,57 @@ menu "On-chip Peripheral Drivers"
|
||||
endif
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_HARD_I2C
|
||||
bool "Enable I2C BUS (hardware driver)"
|
||||
default n
|
||||
select RT_USING_I2C
|
||||
if BSP_USING_HARD_I2C
|
||||
config BSP_USING_HARD_I2C1
|
||||
bool "Enable I2C1 BUS"
|
||||
default n
|
||||
|
||||
config BSP_I2C1_TX_USING_DMA
|
||||
bool "Enable I2C1 TX DMA"
|
||||
depends on BSP_USING_HARD_I2C1
|
||||
default n
|
||||
|
||||
config BSP_I2C1_RX_USING_DMA
|
||||
bool "Enable I2C1 RX DMA"
|
||||
depends on BSP_USING_HARD_I2C1
|
||||
select BSP_I2C1_TX_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_USING_HARD_I2C2
|
||||
bool "Enable I2C2 BUS"
|
||||
default n
|
||||
|
||||
config BSP_I2C2_TX_USING_DMA
|
||||
bool "Enable I2C2 TX DMA"
|
||||
depends on BSP_USING_HARD_I2C2
|
||||
default n
|
||||
|
||||
config BSP_I2C2_RX_USING_DMA
|
||||
bool "Enable I2C2 RX DMA"
|
||||
depends on BSP_USING_HARD_I2C2
|
||||
select BSP_I2C2_TX_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_USING_HARD_I2C3
|
||||
bool "Enable I2C3 BUS"
|
||||
default n
|
||||
|
||||
config BSP_I2C3_TX_USING_DMA
|
||||
bool "Enable I2C3 TX DMA"
|
||||
depends on BSP_USING_HARD_I2C3
|
||||
default n
|
||||
|
||||
config BSP_I2C3_RX_USING_DMA
|
||||
bool "Enable I2C3 RX DMA"
|
||||
depends on BSP_USING_HARD_I2C3
|
||||
select BSP_I2C3_TX_USING_DMA
|
||||
default n
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_ADC
|
||||
bool "Enable ADC"
|
||||
default n
|
||||
|
||||
@ -127,6 +127,69 @@ void at32_msp_spi_init(void *instance)
|
||||
}
|
||||
#endif /* BSP_USING_SPI */
|
||||
|
||||
#ifdef BSP_USING_HARD_I2C
|
||||
void at32_msp_i2c_init(void *instance)
|
||||
{
|
||||
gpio_init_type gpio_init_struct;
|
||||
i2c_type *i2c_x = (i2c_type *)instance;
|
||||
|
||||
gpio_default_para_init(&gpio_init_struct);
|
||||
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
|
||||
#ifdef BSP_USING_HARD_I2C1
|
||||
if(I2C1 == i2c_x)
|
||||
{
|
||||
crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE);
|
||||
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
|
||||
|
||||
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
|
||||
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
|
||||
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
|
||||
gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7;
|
||||
gpio_init(GPIOB, &gpio_init_struct);
|
||||
|
||||
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE6, GPIO_MUX_4);
|
||||
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE7, GPIO_MUX_4);
|
||||
}
|
||||
#endif
|
||||
#ifdef BSP_USING_HARD_I2C2
|
||||
if(I2C2 == i2c_x)
|
||||
{
|
||||
crm_periph_clock_enable(CRM_I2C2_PERIPH_CLOCK, TRUE);
|
||||
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
|
||||
|
||||
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
|
||||
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
|
||||
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
|
||||
gpio_init_struct.gpio_pins = GPIO_PINS_3 | GPIO_PINS_10;
|
||||
gpio_init(GPIOB, &gpio_init_struct);
|
||||
|
||||
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE3, GPIO_MUX_4);
|
||||
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE10, GPIO_MUX_4);
|
||||
}
|
||||
#endif
|
||||
#ifdef BSP_USING_HARD_I2C3
|
||||
if(I2C3 == i2c_x)
|
||||
{
|
||||
crm_periph_clock_enable(CRM_I2C3_PERIPH_CLOCK, TRUE);
|
||||
crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE);
|
||||
crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE);
|
||||
|
||||
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
|
||||
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
|
||||
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
|
||||
gpio_init_struct.gpio_pins = GPIO_PINS_8;
|
||||
gpio_init(GPIOA, &gpio_init_struct);
|
||||
gpio_init_struct.gpio_pins = GPIO_PINS_9;
|
||||
gpio_init(GPIOC, &gpio_init_struct);
|
||||
|
||||
gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE8, GPIO_MUX_4);
|
||||
gpio_pin_mux_config(GPIOC, GPIO_PINS_SOURCE9, GPIO_MUX_4);
|
||||
}
|
||||
#endif
|
||||
/* add others */
|
||||
}
|
||||
#endif /* BSP_USING_HARD_I2C */
|
||||
|
||||
#ifdef BSP_USING_PWM
|
||||
void at32_msp_tmr_init(void *instance)
|
||||
{
|
||||
|
||||
@ -41,6 +41,7 @@ AT32F407-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以
|
||||
| UART | 支持 | USART1/2/3 |
|
||||
| GPIO | 支持 | PA0...PF7 |
|
||||
| IIC | 支持 | GPIO模拟I2C |
|
||||
| HWIIC | 支持 | I2C1/2/3 |
|
||||
| SPI | 支持 | SPI1/2 |
|
||||
| ADC | 支持 | ADC1/2 |
|
||||
| DAC | 支持 | DAC1 |
|
||||
|
||||
@ -282,6 +282,57 @@ menu "On-chip Peripheral Drivers"
|
||||
endif
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_HARD_I2C
|
||||
bool "Enable I2C BUS (hardware driver)"
|
||||
default n
|
||||
select RT_USING_I2C
|
||||
if BSP_USING_HARD_I2C
|
||||
config BSP_USING_HARD_I2C1
|
||||
bool "Enable I2C1 BUS"
|
||||
default n
|
||||
|
||||
config BSP_I2C1_TX_USING_DMA
|
||||
bool "Enable I2C1 TX DMA"
|
||||
depends on BSP_USING_HARD_I2C1
|
||||
default n
|
||||
|
||||
config BSP_I2C1_RX_USING_DMA
|
||||
bool "Enable I2C1 RX DMA"
|
||||
depends on BSP_USING_HARD_I2C1
|
||||
select BSP_I2C1_TX_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_USING_HARD_I2C2
|
||||
bool "Enable I2C2 BUS"
|
||||
default n
|
||||
|
||||
config BSP_I2C2_TX_USING_DMA
|
||||
bool "Enable I2C2 TX DMA"
|
||||
depends on BSP_USING_HARD_I2C2
|
||||
default n
|
||||
|
||||
config BSP_I2C2_RX_USING_DMA
|
||||
bool "Enable I2C2 RX DMA"
|
||||
depends on BSP_USING_HARD_I2C2
|
||||
select BSP_I2C2_TX_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_USING_HARD_I2C3
|
||||
bool "Enable I2C3 BUS"
|
||||
default n
|
||||
|
||||
config BSP_I2C3_TX_USING_DMA
|
||||
bool "Enable I2C3 TX DMA"
|
||||
depends on BSP_USING_HARD_I2C3
|
||||
default n
|
||||
|
||||
config BSP_I2C3_RX_USING_DMA
|
||||
bool "Enable I2C3 RX DMA"
|
||||
depends on BSP_USING_HARD_I2C3
|
||||
select BSP_I2C3_TX_USING_DMA
|
||||
default n
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_ADC
|
||||
bool "Enable ADC"
|
||||
default n
|
||||
|
||||
@ -131,6 +131,60 @@ void at32_msp_spi_init(void *instance)
|
||||
}
|
||||
#endif /* BSP_USING_SPI */
|
||||
|
||||
#ifdef BSP_USING_HARD_I2C
|
||||
void at32_msp_i2c_init(void *instance)
|
||||
{
|
||||
gpio_init_type gpio_init_struct;
|
||||
i2c_type *i2c_x = (i2c_type *)instance;
|
||||
|
||||
gpio_default_para_init(&gpio_init_struct);
|
||||
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
|
||||
#ifdef BSP_USING_HARD_I2C1
|
||||
if(I2C1 == i2c_x)
|
||||
{
|
||||
crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE);
|
||||
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
|
||||
|
||||
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
|
||||
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
|
||||
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
|
||||
gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7;
|
||||
gpio_init(GPIOB, &gpio_init_struct);
|
||||
}
|
||||
#endif
|
||||
#ifdef BSP_USING_HARD_I2C2
|
||||
if(I2C2 == i2c_x)
|
||||
{
|
||||
crm_periph_clock_enable(CRM_I2C2_PERIPH_CLOCK, TRUE);
|
||||
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
|
||||
|
||||
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
|
||||
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
|
||||
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
|
||||
gpio_init_struct.gpio_pins = GPIO_PINS_10 | GPIO_PINS_11;
|
||||
gpio_init(GPIOB, &gpio_init_struct);
|
||||
}
|
||||
#endif
|
||||
#ifdef BSP_USING_HARD_I2C3
|
||||
if(I2C3 == i2c_x)
|
||||
{
|
||||
crm_periph_clock_enable(CRM_I2C3_PERIPH_CLOCK, TRUE);
|
||||
crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE);
|
||||
crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE);
|
||||
|
||||
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
|
||||
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
|
||||
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
|
||||
gpio_init_struct.gpio_pins = GPIO_PINS_8;
|
||||
gpio_init(GPIOA, &gpio_init_struct);
|
||||
gpio_init_struct.gpio_pins = GPIO_PINS_9;
|
||||
gpio_init(GPIOC, &gpio_init_struct);
|
||||
}
|
||||
#endif
|
||||
/* add others */
|
||||
}
|
||||
#endif /* BSP_USING_HARD_I2C */
|
||||
|
||||
#ifdef BSP_USING_SDIO
|
||||
void at32_msp_sdio_init(void *instance)
|
||||
{
|
||||
|
||||
@ -41,6 +41,7 @@ AT32F413-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以
|
||||
| UART | 支持 | USART1/2/3 |
|
||||
| GPIO | 支持 | PA0...PF5 |
|
||||
| IIC | 支持 | GPIO模拟I2C |
|
||||
| HWIIC | 支持 | I2C1/2 |
|
||||
| SPI | 支持 | SPI1/2 |
|
||||
| ADC | 支持 | ADC1/2 |
|
||||
| PWM | 支持 | TMR1/2 |
|
||||
|
||||
@ -253,6 +253,42 @@ menu "On-chip Peripheral Drivers"
|
||||
endif
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_HARD_I2C
|
||||
bool "Enable I2C BUS (hardware driver)"
|
||||
default n
|
||||
select RT_USING_I2C
|
||||
if BSP_USING_HARD_I2C
|
||||
config BSP_USING_HARD_I2C1
|
||||
bool "Enable I2C1 BUS"
|
||||
default n
|
||||
|
||||
config BSP_I2C1_TX_USING_DMA
|
||||
bool "Enable I2C1 TX DMA"
|
||||
depends on BSP_USING_HARD_I2C1
|
||||
default n
|
||||
|
||||
config BSP_I2C1_RX_USING_DMA
|
||||
bool "Enable I2C1 RX DMA"
|
||||
depends on BSP_USING_HARD_I2C1
|
||||
select BSP_I2C1_TX_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_USING_HARD_I2C2
|
||||
bool "Enable I2C2 BUS"
|
||||
default n
|
||||
|
||||
config BSP_I2C2_TX_USING_DMA
|
||||
bool "Enable I2C2 TX DMA"
|
||||
depends on BSP_USING_HARD_I2C2
|
||||
default n
|
||||
|
||||
config BSP_I2C2_RX_USING_DMA
|
||||
bool "Enable I2C2 RX DMA"
|
||||
depends on BSP_USING_HARD_I2C2
|
||||
select BSP_I2C2_TX_USING_DMA
|
||||
default n
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_ADC
|
||||
bool "Enable ADC"
|
||||
default n
|
||||
|
||||
@ -129,6 +129,44 @@ void at32_msp_spi_init(void *instance)
|
||||
}
|
||||
#endif /* BSP_USING_SPI */
|
||||
|
||||
#ifdef BSP_USING_HARD_I2C
|
||||
void at32_msp_i2c_init(void *instance)
|
||||
{
|
||||
gpio_init_type gpio_init_struct;
|
||||
i2c_type *i2c_x = (i2c_type *)instance;
|
||||
|
||||
gpio_default_para_init(&gpio_init_struct);
|
||||
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
|
||||
#ifdef BSP_USING_HARD_I2C1
|
||||
if(I2C1 == i2c_x)
|
||||
{
|
||||
crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE);
|
||||
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
|
||||
|
||||
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
|
||||
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
|
||||
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
|
||||
gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7;
|
||||
gpio_init(GPIOB, &gpio_init_struct);
|
||||
}
|
||||
#endif
|
||||
#ifdef BSP_USING_HARD_I2C2
|
||||
if(I2C2 == i2c_x)
|
||||
{
|
||||
crm_periph_clock_enable(CRM_I2C2_PERIPH_CLOCK, TRUE);
|
||||
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
|
||||
|
||||
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
|
||||
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
|
||||
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
|
||||
gpio_init_struct.gpio_pins = GPIO_PINS_10 | GPIO_PINS_11;
|
||||
gpio_init(GPIOB, &gpio_init_struct);
|
||||
}
|
||||
#endif
|
||||
/* add others */
|
||||
}
|
||||
#endif /* BSP_USING_HARD_I2C */
|
||||
|
||||
#ifdef BSP_USING_SDIO
|
||||
void at32_msp_sdio_init(void *instance)
|
||||
{
|
||||
|
||||
@ -41,6 +41,7 @@ AT32F415-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以
|
||||
| UART | 支持 | USART1/2/3 |
|
||||
| GPIO | 支持 | PA0...PF5 |
|
||||
| IIC | 支持 | GPIO模拟I2C |
|
||||
| HWIIC | 支持 | I2C1/2 |
|
||||
| SPI | 支持 | SPI1/2 |
|
||||
| ADC | 支持 | ADC1 |
|
||||
| PWM | 支持 | TMR1/2 |
|
||||
|
||||
@ -268,6 +268,42 @@ menu "On-chip Peripheral Drivers"
|
||||
endif
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_HARD_I2C
|
||||
bool "Enable I2C BUS (hardware driver)"
|
||||
default n
|
||||
select RT_USING_I2C
|
||||
if BSP_USING_HARD_I2C
|
||||
config BSP_USING_HARD_I2C1
|
||||
bool "Enable I2C1 BUS"
|
||||
default n
|
||||
|
||||
config BSP_I2C1_TX_USING_DMA
|
||||
bool "Enable I2C1 TX DMA"
|
||||
depends on BSP_USING_HARD_I2C1
|
||||
default n
|
||||
|
||||
config BSP_I2C1_RX_USING_DMA
|
||||
bool "Enable I2C1 RX DMA"
|
||||
depends on BSP_USING_HARD_I2C1
|
||||
select BSP_I2C1_TX_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_USING_HARD_I2C2
|
||||
bool "Enable I2C2 BUS"
|
||||
default n
|
||||
|
||||
config BSP_I2C2_TX_USING_DMA
|
||||
bool "Enable I2C2 TX DMA"
|
||||
depends on BSP_USING_HARD_I2C2
|
||||
default n
|
||||
|
||||
config BSP_I2C2_RX_USING_DMA
|
||||
bool "Enable I2C2 RX DMA"
|
||||
depends on BSP_USING_HARD_I2C2
|
||||
select BSP_I2C2_TX_USING_DMA
|
||||
default n
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_ADC
|
||||
bool "Enable ADC"
|
||||
default n
|
||||
|
||||
@ -129,6 +129,44 @@ void at32_msp_spi_init(void *instance)
|
||||
}
|
||||
#endif /* BSP_USING_SPI */
|
||||
|
||||
#ifdef BSP_USING_HARD_I2C
|
||||
void at32_msp_i2c_init(void *instance)
|
||||
{
|
||||
gpio_init_type gpio_init_struct;
|
||||
i2c_type *i2c_x = (i2c_type *)instance;
|
||||
|
||||
gpio_default_para_init(&gpio_init_struct);
|
||||
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
|
||||
#ifdef BSP_USING_HARD_I2C1
|
||||
if(I2C1 == i2c_x)
|
||||
{
|
||||
crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE);
|
||||
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
|
||||
|
||||
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
|
||||
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
|
||||
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
|
||||
gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7;
|
||||
gpio_init(GPIOB, &gpio_init_struct);
|
||||
}
|
||||
#endif
|
||||
#ifdef BSP_USING_HARD_I2C2
|
||||
if(I2C2 == i2c_x)
|
||||
{
|
||||
crm_periph_clock_enable(CRM_I2C2_PERIPH_CLOCK, TRUE);
|
||||
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
|
||||
|
||||
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
|
||||
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
|
||||
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
|
||||
gpio_init_struct.gpio_pins = GPIO_PINS_10 | GPIO_PINS_11;
|
||||
gpio_init(GPIOB, &gpio_init_struct);
|
||||
}
|
||||
#endif
|
||||
/* add others */
|
||||
}
|
||||
#endif /* BSP_USING_HARD_I2C */
|
||||
|
||||
#ifdef BSP_USING_SDIO
|
||||
void at32_msp_sdio_init(void *instance)
|
||||
{
|
||||
|
||||
@ -41,6 +41,7 @@ AT32F421-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以
|
||||
| UART | 支持 | USART1/2 |
|
||||
| GPIO | 支持 | PA0...PF7 |
|
||||
| IIC | 支持 | GPIO模拟I2C |
|
||||
| HWIIC | 支持 | I2C1/2 |
|
||||
| SPI | 支持 | SPI1/2 |
|
||||
| ADC | 支持 | ADC1 |
|
||||
| PWM | 支持 | TMR1 |
|
||||
|
||||
@ -203,6 +203,42 @@ menu "On-chip Peripheral Drivers"
|
||||
endif
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_HARD_I2C
|
||||
bool "Enable I2C BUS (hardware driver)"
|
||||
default n
|
||||
select RT_USING_I2C
|
||||
if BSP_USING_HARD_I2C
|
||||
config BSP_USING_HARD_I2C1
|
||||
bool "Enable I2C1 BUS"
|
||||
default n
|
||||
|
||||
config BSP_I2C1_TX_USING_DMA
|
||||
bool "Enable I2C1 TX DMA"
|
||||
depends on BSP_USING_HARD_I2C1
|
||||
default n
|
||||
|
||||
config BSP_I2C1_RX_USING_DMA
|
||||
bool "Enable I2C1 RX DMA"
|
||||
depends on BSP_USING_HARD_I2C1
|
||||
select BSP_I2C1_TX_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_USING_HARD_I2C2
|
||||
bool "Enable I2C2 BUS"
|
||||
default n
|
||||
|
||||
config BSP_I2C2_TX_USING_DMA
|
||||
bool "Enable I2C2 TX DMA"
|
||||
depends on BSP_USING_HARD_I2C2
|
||||
default n
|
||||
|
||||
config BSP_I2C2_RX_USING_DMA
|
||||
bool "Enable I2C2 RX DMA"
|
||||
depends on BSP_USING_HARD_I2C2
|
||||
select BSP_I2C2_TX_USING_DMA
|
||||
default n
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_ADC
|
||||
bool "Enable ADC"
|
||||
default n
|
||||
|
||||
@ -16,5 +16,6 @@ void at32_msp_spi_init(void *instance);
|
||||
void at32_msp_tmr_init(void *instance);
|
||||
void at32_msp_adc_init(void *instance);
|
||||
void at32_msp_hwtmr_init(void *instance);
|
||||
void at32_msp_i2c_init(void *instance);
|
||||
|
||||
#endif /* __AT32_MSP_H__ */
|
||||
|
||||
@ -116,6 +116,50 @@ void at32_msp_spi_init(void *instance)
|
||||
}
|
||||
#endif /* BSP_USING_SPI */
|
||||
|
||||
#ifdef BSP_USING_HARD_I2C
|
||||
void at32_msp_i2c_init(void *instance)
|
||||
{
|
||||
gpio_init_type gpio_init_struct;
|
||||
i2c_type *i2c_x = (i2c_type *)instance;
|
||||
|
||||
gpio_default_para_init(&gpio_init_struct);
|
||||
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
|
||||
#ifdef BSP_USING_HARD_I2C1
|
||||
if(I2C1 == i2c_x)
|
||||
{
|
||||
crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE);
|
||||
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
|
||||
|
||||
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
|
||||
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
|
||||
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
|
||||
gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7;
|
||||
gpio_init(GPIOB, &gpio_init_struct);
|
||||
|
||||
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE6, GPIO_MUX_1);
|
||||
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE7, GPIO_MUX_1);
|
||||
}
|
||||
#endif
|
||||
#ifdef BSP_USING_HARD_I2C2
|
||||
if(I2C2 == i2c_x)
|
||||
{
|
||||
crm_periph_clock_enable(CRM_I2C2_PERIPH_CLOCK, TRUE);
|
||||
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
|
||||
|
||||
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
|
||||
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
|
||||
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
|
||||
gpio_init_struct.gpio_pins = GPIO_PINS_10 | GPIO_PINS_11;
|
||||
gpio_init(GPIOB, &gpio_init_struct);
|
||||
|
||||
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE10, GPIO_MUX_1);
|
||||
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE11, GPIO_MUX_1);
|
||||
}
|
||||
#endif
|
||||
/* add others */
|
||||
}
|
||||
#endif /* BSP_USING_HARD_I2C */
|
||||
|
||||
#ifdef BSP_USING_PWM
|
||||
void at32_msp_tmr_init(void *instance)
|
||||
{
|
||||
|
||||
@ -41,6 +41,7 @@ AT32F423-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以
|
||||
| UART | 支持 | USART1/2/3 |
|
||||
| GPIO | 支持 | PA0...PF10 |
|
||||
| IIC | 支持 | GPIO模拟I2C |
|
||||
| HWIIC | 支持 | I2C1/2/3 |
|
||||
| SPI | 支持 | SPI1/2 |
|
||||
| ADC | 支持 | ADC1 |
|
||||
| DAC | 支持 | DAC1 |
|
||||
|
||||
@ -277,6 +277,57 @@ menu "On-chip Peripheral Drivers"
|
||||
endif
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_HARD_I2C
|
||||
bool "Enable I2C BUS (hardware driver)"
|
||||
default n
|
||||
select RT_USING_I2C
|
||||
if BSP_USING_HARD_I2C
|
||||
config BSP_USING_HARD_I2C1
|
||||
bool "Enable I2C1 BUS"
|
||||
default n
|
||||
|
||||
config BSP_I2C1_TX_USING_DMA
|
||||
bool "Enable I2C1 TX DMA"
|
||||
depends on BSP_USING_HARD_I2C1
|
||||
default n
|
||||
|
||||
config BSP_I2C1_RX_USING_DMA
|
||||
bool "Enable I2C1 RX DMA"
|
||||
depends on BSP_USING_HARD_I2C1
|
||||
select BSP_I2C1_TX_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_USING_HARD_I2C2
|
||||
bool "Enable I2C2 BUS"
|
||||
default n
|
||||
|
||||
config BSP_I2C2_TX_USING_DMA
|
||||
bool "Enable I2C2 TX DMA"
|
||||
depends on BSP_USING_HARD_I2C2
|
||||
default n
|
||||
|
||||
config BSP_I2C2_RX_USING_DMA
|
||||
bool "Enable I2C2 RX DMA"
|
||||
depends on BSP_USING_HARD_I2C2
|
||||
select BSP_I2C2_TX_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_USING_HARD_I2C3
|
||||
bool "Enable I2C3 BUS"
|
||||
default n
|
||||
|
||||
config BSP_I2C3_TX_USING_DMA
|
||||
bool "Enable I2C3 TX DMA"
|
||||
depends on BSP_USING_HARD_I2C3
|
||||
default n
|
||||
|
||||
config BSP_I2C3_RX_USING_DMA
|
||||
bool "Enable I2C3 RX DMA"
|
||||
depends on BSP_USING_HARD_I2C3
|
||||
select BSP_I2C3_TX_USING_DMA
|
||||
default n
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_ADC
|
||||
bool "Enable ADC"
|
||||
default n
|
||||
|
||||
@ -19,5 +19,6 @@ void at32_msp_hwtmr_init(void *instance);
|
||||
void at32_msp_can_init(void *instance);
|
||||
void at32_msp_usb_init(void *instance);
|
||||
void at32_msp_dac_init(void *instance);
|
||||
void at32_msp_i2c_init(void *instance);
|
||||
|
||||
#endif /* __AT32_MSP_H__ */
|
||||
|
||||
@ -135,6 +135,69 @@ void at32_msp_spi_init(void *instance)
|
||||
}
|
||||
#endif /* BSP_USING_SPI */
|
||||
|
||||
#ifdef BSP_USING_HARD_I2C
|
||||
void at32_msp_i2c_init(void *instance)
|
||||
{
|
||||
gpio_init_type gpio_init_struct;
|
||||
i2c_type *i2c_x = (i2c_type *)instance;
|
||||
|
||||
gpio_default_para_init(&gpio_init_struct);
|
||||
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
|
||||
#ifdef BSP_USING_HARD_I2C1
|
||||
if(I2C1 == i2c_x)
|
||||
{
|
||||
crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE);
|
||||
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
|
||||
|
||||
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
|
||||
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
|
||||
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
|
||||
gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7;
|
||||
gpio_init(GPIOB, &gpio_init_struct);
|
||||
|
||||
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE6, GPIO_MUX_4);
|
||||
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE7, GPIO_MUX_4);
|
||||
}
|
||||
#endif
|
||||
#ifdef BSP_USING_HARD_I2C2
|
||||
if(I2C2 == i2c_x)
|
||||
{
|
||||
crm_periph_clock_enable(CRM_I2C2_PERIPH_CLOCK, TRUE);
|
||||
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
|
||||
|
||||
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
|
||||
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
|
||||
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
|
||||
gpio_init_struct.gpio_pins = GPIO_PINS_10 | GPIO_PINS_11;
|
||||
gpio_init(GPIOB, &gpio_init_struct);
|
||||
|
||||
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE10, GPIO_MUX_4);
|
||||
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE11, GPIO_MUX_4);
|
||||
}
|
||||
#endif
|
||||
#ifdef BSP_USING_HARD_I2C3
|
||||
if(I2C3 == i2c_x)
|
||||
{
|
||||
crm_periph_clock_enable(CRM_I2C3_PERIPH_CLOCK, TRUE);
|
||||
crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE);
|
||||
crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE);
|
||||
|
||||
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
|
||||
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
|
||||
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
|
||||
gpio_init_struct.gpio_pins = GPIO_PINS_8;
|
||||
gpio_init(GPIOA, &gpio_init_struct);
|
||||
gpio_init_struct.gpio_pins = GPIO_PINS_9;
|
||||
gpio_init(GPIOC, &gpio_init_struct);
|
||||
|
||||
gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE8, GPIO_MUX_4);
|
||||
gpio_pin_mux_config(GPIOC, GPIO_PINS_SOURCE9, GPIO_MUX_4);
|
||||
}
|
||||
#endif
|
||||
/* add others */
|
||||
}
|
||||
#endif /* BSP_USING_HARD_I2C */
|
||||
|
||||
#ifdef BSP_USING_PWM
|
||||
void at32_msp_tmr_init(void *instance)
|
||||
{
|
||||
|
||||
@ -41,6 +41,7 @@ AT32F425-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以
|
||||
| UART | 支持 | USART1/2/3 |
|
||||
| GPIO | 支持 | PA0...PF7 |
|
||||
| IIC | 支持 | GPIO模拟I2C |
|
||||
| HWIIC | 支持 | I2C1/2 |
|
||||
| SPI | 支持 | SPI1/2 |
|
||||
| ADC | 支持 | ADC1 |
|
||||
| PWM | 支持 | TMR1/2 |
|
||||
|
||||
@ -277,6 +277,42 @@ menu "On-chip Peripheral Drivers"
|
||||
endif
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_HARD_I2C
|
||||
bool "Enable I2C BUS (hardware driver)"
|
||||
default n
|
||||
select RT_USING_I2C
|
||||
if BSP_USING_HARD_I2C
|
||||
config BSP_USING_HARD_I2C1
|
||||
bool "Enable I2C1 BUS"
|
||||
default n
|
||||
|
||||
config BSP_I2C1_TX_USING_DMA
|
||||
bool "Enable I2C1 TX DMA"
|
||||
depends on BSP_USING_HARD_I2C1
|
||||
default n
|
||||
|
||||
config BSP_I2C1_RX_USING_DMA
|
||||
bool "Enable I2C1 RX DMA"
|
||||
depends on BSP_USING_HARD_I2C1
|
||||
select BSP_I2C1_TX_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_USING_HARD_I2C2
|
||||
bool "Enable I2C2 BUS"
|
||||
default n
|
||||
|
||||
config BSP_I2C2_TX_USING_DMA
|
||||
bool "Enable I2C2 TX DMA"
|
||||
depends on BSP_USING_HARD_I2C2
|
||||
default n
|
||||
|
||||
config BSP_I2C2_RX_USING_DMA
|
||||
bool "Enable I2C2 RX DMA"
|
||||
depends on BSP_USING_HARD_I2C2
|
||||
select BSP_I2C2_TX_USING_DMA
|
||||
default n
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_ADC
|
||||
bool "Enable ADC"
|
||||
default n
|
||||
|
||||
@ -18,5 +18,6 @@ void at32_msp_adc_init(void *instance);
|
||||
void at32_msp_hwtmr_init(void *instance);
|
||||
void at32_msp_can_init(void *instance);
|
||||
void at32_msp_usb_init(void *instance);
|
||||
void at32_msp_i2c_init(void *instance);
|
||||
|
||||
#endif /* __AT32_MSP_H__ */
|
||||
|
||||
@ -135,6 +135,50 @@ void at32_msp_spi_init(void *instance)
|
||||
}
|
||||
#endif /* BSP_USING_SPI */
|
||||
|
||||
#ifdef BSP_USING_HARD_I2C
|
||||
void at32_msp_i2c_init(void *instance)
|
||||
{
|
||||
gpio_init_type gpio_init_struct;
|
||||
i2c_type *i2c_x = (i2c_type *)instance;
|
||||
|
||||
gpio_default_para_init(&gpio_init_struct);
|
||||
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
|
||||
#ifdef BSP_USING_HARD_I2C1
|
||||
if(I2C1 == i2c_x)
|
||||
{
|
||||
crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE);
|
||||
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
|
||||
|
||||
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
|
||||
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
|
||||
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
|
||||
gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7;
|
||||
gpio_init(GPIOB, &gpio_init_struct);
|
||||
|
||||
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE6, GPIO_MUX_1);
|
||||
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE7, GPIO_MUX_1);
|
||||
}
|
||||
#endif
|
||||
#ifdef BSP_USING_HARD_I2C2
|
||||
if(I2C2 == i2c_x)
|
||||
{
|
||||
crm_periph_clock_enable(CRM_I2C2_PERIPH_CLOCK, TRUE);
|
||||
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
|
||||
|
||||
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
|
||||
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
|
||||
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
|
||||
gpio_init_struct.gpio_pins = GPIO_PINS_10 | GPIO_PINS_11;
|
||||
gpio_init(GPIOB, &gpio_init_struct);
|
||||
|
||||
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE10, GPIO_MUX_1);
|
||||
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE11, GPIO_MUX_1);
|
||||
}
|
||||
#endif
|
||||
/* add others */
|
||||
}
|
||||
#endif /* BSP_USING_HARD_I2C */
|
||||
|
||||
#ifdef BSP_USING_PWM
|
||||
void at32_msp_tmr_init(void *instance)
|
||||
{
|
||||
|
||||
@ -41,6 +41,7 @@ AT32F437-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以
|
||||
| UART | 支持 | USART1/2/3 |
|
||||
| GPIO | 支持 | PA0...PH7 |
|
||||
| IIC | 支持 | GPIO模拟I2C |
|
||||
| HWIIC | 支持 | I2C1/2/3 |
|
||||
| SPI | 支持 | SPI1/2 |
|
||||
| ADC | 支持 | ADC1/2 |
|
||||
| DAC | 支持 | DAC1 |
|
||||
|
||||
@ -314,6 +314,57 @@ menu "On-chip Peripheral Drivers"
|
||||
endif
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_HARD_I2C
|
||||
bool "Enable I2C BUS (hardware driver)"
|
||||
default n
|
||||
select RT_USING_I2C
|
||||
if BSP_USING_HARD_I2C
|
||||
config BSP_USING_HARD_I2C1
|
||||
bool "Enable I2C1 BUS"
|
||||
default n
|
||||
|
||||
config BSP_I2C1_TX_USING_DMA
|
||||
bool "Enable I2C1 TX DMA"
|
||||
depends on BSP_USING_HARD_I2C1
|
||||
default n
|
||||
|
||||
config BSP_I2C1_RX_USING_DMA
|
||||
bool "Enable I2C1 RX DMA"
|
||||
depends on BSP_USING_HARD_I2C1
|
||||
select BSP_I2C1_TX_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_USING_HARD_I2C2
|
||||
bool "Enable I2C2 BUS"
|
||||
default n
|
||||
|
||||
config BSP_I2C2_TX_USING_DMA
|
||||
bool "Enable I2C2 TX DMA"
|
||||
depends on BSP_USING_HARD_I2C2
|
||||
default n
|
||||
|
||||
config BSP_I2C2_RX_USING_DMA
|
||||
bool "Enable I2C2 RX DMA"
|
||||
depends on BSP_USING_HARD_I2C2
|
||||
select BSP_I2C2_TX_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_USING_HARD_I2C3
|
||||
bool "Enable I2C3 BUS"
|
||||
default n
|
||||
|
||||
config BSP_I2C3_TX_USING_DMA
|
||||
bool "Enable I2C3 TX DMA"
|
||||
depends on BSP_USING_HARD_I2C3
|
||||
default n
|
||||
|
||||
config BSP_I2C3_RX_USING_DMA
|
||||
bool "Enable I2C3 RX DMA"
|
||||
depends on BSP_USING_HARD_I2C3
|
||||
select BSP_I2C3_TX_USING_DMA
|
||||
default n
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_ADC
|
||||
bool "Enable ADC"
|
||||
default n
|
||||
|
||||
@ -126,6 +126,69 @@ void at32_msp_spi_init(void *instance)
|
||||
}
|
||||
#endif /* BSP_USING_SPI */
|
||||
|
||||
#ifdef BSP_USING_HARD_I2C
|
||||
void at32_msp_i2c_init(void *instance)
|
||||
{
|
||||
gpio_init_type gpio_init_struct;
|
||||
i2c_type *i2c_x = (i2c_type *)instance;
|
||||
|
||||
gpio_default_para_init(&gpio_init_struct);
|
||||
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
|
||||
#ifdef BSP_USING_HARD_I2C1
|
||||
if(I2C1 == i2c_x)
|
||||
{
|
||||
crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE);
|
||||
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
|
||||
|
||||
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
|
||||
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
|
||||
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
|
||||
gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7;
|
||||
gpio_init(GPIOB, &gpio_init_struct);
|
||||
|
||||
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE6, GPIO_MUX_4);
|
||||
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE7, GPIO_MUX_4);
|
||||
}
|
||||
#endif
|
||||
#ifdef BSP_USING_HARD_I2C2
|
||||
if(I2C2 == i2c_x)
|
||||
{
|
||||
crm_periph_clock_enable(CRM_I2C2_PERIPH_CLOCK, TRUE);
|
||||
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
|
||||
|
||||
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
|
||||
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
|
||||
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
|
||||
gpio_init_struct.gpio_pins = GPIO_PINS_10 | GPIO_PINS_11;
|
||||
gpio_init(GPIOB, &gpio_init_struct);
|
||||
|
||||
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE10, GPIO_MUX_4);
|
||||
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE11, GPIO_MUX_4);
|
||||
}
|
||||
#endif
|
||||
#ifdef BSP_USING_HARD_I2C3
|
||||
if(I2C3 == i2c_x)
|
||||
{
|
||||
crm_periph_clock_enable(CRM_I2C3_PERIPH_CLOCK, TRUE);
|
||||
crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE);
|
||||
crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE);
|
||||
|
||||
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
|
||||
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
|
||||
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
|
||||
gpio_init_struct.gpio_pins = GPIO_PINS_8;
|
||||
gpio_init(GPIOA, &gpio_init_struct);
|
||||
gpio_init_struct.gpio_pins = GPIO_PINS_9;
|
||||
gpio_init(GPIOC, &gpio_init_struct);
|
||||
|
||||
gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE8, GPIO_MUX_4);
|
||||
gpio_pin_mux_config(GPIOC, GPIO_PINS_SOURCE9, GPIO_MUX_4);
|
||||
}
|
||||
#endif
|
||||
/* add others */
|
||||
}
|
||||
#endif /* BSP_USING_HARD_I2C */
|
||||
|
||||
#ifdef BSP_USING_SDIO
|
||||
void at32_msp_sdio_init(void *instance)
|
||||
{
|
||||
|
||||
@ -41,6 +41,7 @@ AT32F437-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以
|
||||
| UART | 支持 | USART1/2/3 |
|
||||
| GPIO | 支持 | PA0...PH7 |
|
||||
| IIC | 支持 | GPIO模拟I2C |
|
||||
| HWIIC | 支持 | I2C1/2/3 |
|
||||
| SPI | 支持 | SPI1/2 |
|
||||
| ADC | 支持 | ADC1/2 |
|
||||
| DAC | 支持 | DAC1 |
|
||||
|
||||
@ -331,6 +331,57 @@ menu "On-chip Peripheral Drivers"
|
||||
endif
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_HARD_I2C
|
||||
bool "Enable I2C BUS (hardware driver)"
|
||||
default n
|
||||
select RT_USING_I2C
|
||||
if BSP_USING_HARD_I2C
|
||||
config BSP_USING_HARD_I2C1
|
||||
bool "Enable I2C1 BUS"
|
||||
default n
|
||||
|
||||
config BSP_I2C1_TX_USING_DMA
|
||||
bool "Enable I2C1 TX DMA"
|
||||
depends on BSP_USING_HARD_I2C1
|
||||
default n
|
||||
|
||||
config BSP_I2C1_RX_USING_DMA
|
||||
bool "Enable I2C1 RX DMA"
|
||||
depends on BSP_USING_HARD_I2C1
|
||||
select BSP_I2C1_TX_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_USING_HARD_I2C2
|
||||
bool "Enable I2C2 BUS"
|
||||
default n
|
||||
|
||||
config BSP_I2C2_TX_USING_DMA
|
||||
bool "Enable I2C2 TX DMA"
|
||||
depends on BSP_USING_HARD_I2C2
|
||||
default n
|
||||
|
||||
config BSP_I2C2_RX_USING_DMA
|
||||
bool "Enable I2C2 RX DMA"
|
||||
depends on BSP_USING_HARD_I2C2
|
||||
select BSP_I2C2_TX_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_USING_HARD_I2C3
|
||||
bool "Enable I2C3 BUS"
|
||||
default n
|
||||
|
||||
config BSP_I2C3_TX_USING_DMA
|
||||
bool "Enable I2C3 TX DMA"
|
||||
depends on BSP_USING_HARD_I2C3
|
||||
default n
|
||||
|
||||
config BSP_I2C3_RX_USING_DMA
|
||||
bool "Enable I2C3 RX DMA"
|
||||
depends on BSP_USING_HARD_I2C3
|
||||
select BSP_I2C3_TX_USING_DMA
|
||||
default n
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_ADC
|
||||
bool "Enable ADC"
|
||||
default n
|
||||
|
||||
@ -127,6 +127,69 @@ void at32_msp_spi_init(void *instance)
|
||||
}
|
||||
#endif /* BSP_USING_SPI */
|
||||
|
||||
#ifdef BSP_USING_HARD_I2C
|
||||
void at32_msp_i2c_init(void *instance)
|
||||
{
|
||||
gpio_init_type gpio_init_struct;
|
||||
i2c_type *i2c_x = (i2c_type *)instance;
|
||||
|
||||
gpio_default_para_init(&gpio_init_struct);
|
||||
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
|
||||
#ifdef BSP_USING_HARD_I2C1
|
||||
if(I2C1 == i2c_x)
|
||||
{
|
||||
crm_periph_clock_enable(CRM_I2C1_PERIPH_CLOCK, TRUE);
|
||||
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
|
||||
|
||||
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
|
||||
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
|
||||
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
|
||||
gpio_init_struct.gpio_pins = GPIO_PINS_6 | GPIO_PINS_7;
|
||||
gpio_init(GPIOB, &gpio_init_struct);
|
||||
|
||||
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE6, GPIO_MUX_4);
|
||||
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE7, GPIO_MUX_4);
|
||||
}
|
||||
#endif
|
||||
#ifdef BSP_USING_HARD_I2C2
|
||||
if(I2C2 == i2c_x)
|
||||
{
|
||||
crm_periph_clock_enable(CRM_I2C2_PERIPH_CLOCK, TRUE);
|
||||
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
|
||||
|
||||
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
|
||||
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
|
||||
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
|
||||
gpio_init_struct.gpio_pins = GPIO_PINS_10 | GPIO_PINS_11;
|
||||
gpio_init(GPIOB, &gpio_init_struct);
|
||||
|
||||
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE10, GPIO_MUX_4);
|
||||
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE11, GPIO_MUX_4);
|
||||
}
|
||||
#endif
|
||||
#ifdef BSP_USING_HARD_I2C3
|
||||
if(I2C3 == i2c_x)
|
||||
{
|
||||
crm_periph_clock_enable(CRM_I2C3_PERIPH_CLOCK, TRUE);
|
||||
crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE);
|
||||
crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE);
|
||||
|
||||
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
|
||||
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_OPEN_DRAIN;
|
||||
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
|
||||
gpio_init_struct.gpio_pins = GPIO_PINS_8;
|
||||
gpio_init(GPIOA, &gpio_init_struct);
|
||||
gpio_init_struct.gpio_pins = GPIO_PINS_9;
|
||||
gpio_init(GPIOC, &gpio_init_struct);
|
||||
|
||||
gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE8, GPIO_MUX_4);
|
||||
gpio_pin_mux_config(GPIOC, GPIO_PINS_SOURCE9, GPIO_MUX_4);
|
||||
}
|
||||
#endif
|
||||
/* add others */
|
||||
}
|
||||
#endif /* BSP_USING_HARD_I2C */
|
||||
|
||||
#ifdef BSP_USING_SDIO
|
||||
void at32_msp_sdio_init(void *instance)
|
||||
{
|
||||
|
||||
15
bsp/at32/libraries/.ignore_format.yml
Normal file
15
bsp/at32/libraries/.ignore_format.yml
Normal file
@ -0,0 +1,15 @@
|
||||
# files format check exclude path, please follow the instructions below to modify;
|
||||
# If you need to exclude an entire folder, add the folder path in dir_path;
|
||||
# If you need to exclude a file, add the path to the file in file_path.
|
||||
|
||||
dir_path:
|
||||
- AT32A403A_Firmware_Library
|
||||
- AT32A423_Firmware_Library
|
||||
- AT32F402_405_Firmware_Library
|
||||
- AT32F403A_407_Firmware_Library
|
||||
- AT32F413_Firmware_Library
|
||||
- AT32F415_Firmware_Library
|
||||
- AT32F421_Firmware_Library
|
||||
- AT32F423_Firmware_Library
|
||||
- AT32F425_Firmware_Library
|
||||
- AT32F435_437_Firmware_Library
|
||||
@ -179,6 +179,50 @@ void system_core_clock_update(void)
|
||||
system_core_clock = system_core_clock >> div_value;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief reduce power consumption initialize
|
||||
* If OTGHS is not used, call this function to reduce power consumption.
|
||||
* PLL or HEXT should be enabled when calling this function.
|
||||
*
|
||||
* If OTGHS is required, initialize OTGHS to reduce power consumption,
|
||||
* without the need to call this function.
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void reduce_power_consumption(void)
|
||||
{
|
||||
volatile uint32_t delay = 0x34BC0;
|
||||
if(CRM->ctrl_bit.hextstbl)
|
||||
{
|
||||
*(__IO uint32_t *)0x40023878 = 0x00;
|
||||
}
|
||||
else if(CRM->ctrl_bit.pllstbl == SET)
|
||||
{
|
||||
CRM->pllcfg_bit.plluen = TRUE;
|
||||
while(CRM->ctrl_bit.pllstbl != SET || CRM->ctrl_bit.pllustbl != SET);
|
||||
*(__IO uint32_t *)0x40023878 = 0x10;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* the pll or hext need to be enable */
|
||||
return;
|
||||
}
|
||||
CRM->ahben1 |= 1 << 29;
|
||||
*(__IO uint32_t *)0x40040038 = 0x210000;
|
||||
*(__IO uint32_t *)0x4004000C |= 0x40000000;
|
||||
*(__IO uint32_t *)0x40040804 &= ~0x2;
|
||||
while(delay --)
|
||||
{
|
||||
if(*(__IO uint32_t *)0x40040808 & 0x1)
|
||||
break;
|
||||
}
|
||||
*(__IO uint32_t *)0x40040038 |= 0x400000;
|
||||
*(__IO uint32_t *)0x40040E00 |= 0x1;
|
||||
*(__IO uint32_t *)0x40040038 &= ~0x10000;
|
||||
*(__IO uint32_t *)0x40023878 = 0x0;
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@ -52,6 +52,7 @@ extern unsigned int system_core_clock; /*!< system clock frequency (core clock)
|
||||
|
||||
extern void SystemInit(void);
|
||||
extern void system_core_clock_update(void);
|
||||
extern void reduce_power_consumption(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
||||
@ -178,6 +178,7 @@ uint16_t acc_read_c1(void);
|
||||
uint16_t acc_read_c2(void);
|
||||
uint16_t acc_read_c3(void);
|
||||
flag_status acc_flag_get(uint16_t acc_flag);
|
||||
flag_status acc_interrupt_flag_get(uint16_t acc_flag);
|
||||
void acc_flag_clear(uint16_t acc_flag);
|
||||
|
||||
/**
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f425_adc.h
|
||||
* @brief at32f425 adc header file
|
||||
* @file at32f402_405_adc.h
|
||||
* @brief at32f402_405 adc header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
@ -34,7 +34,7 @@ extern "C" {
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "at32f402_405.h"
|
||||
|
||||
/** @addtogroup AT32F425_periph_driver
|
||||
/** @addtogroup AT32F402_405_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
@ -688,6 +688,7 @@ flag_status adc_preempt_software_trigger_status_get(adc_type *adc_x);
|
||||
uint16_t adc_ordinary_conversion_data_get(adc_type *adc_x);
|
||||
uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel);
|
||||
flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag);
|
||||
flag_status adc_interrupt_flag_get(adc_type *adc_x, uint8_t adc_flag);
|
||||
void adc_flag_clear(adc_type *adc_x, uint32_t adc_flag);
|
||||
void adc_ordinary_oversample_enable(adc_type *adc_x, confirm_state new_state);
|
||||
void adc_preempt_oversample_enable(adc_type *adc_x, confirm_state new_state);
|
||||
|
||||
@ -1018,6 +1018,7 @@ can_error_record_type can_error_type_record_get(can_type* can_x);
|
||||
uint8_t can_receive_error_counter_get(can_type* can_x);
|
||||
uint8_t can_transmit_error_counter_get(can_type* can_x);
|
||||
void can_interrupt_enable(can_type* can_x, uint32_t can_int, confirm_state new_state);
|
||||
flag_status can_interrupt_flag_get(can_type* can_x, uint32_t can_flag);
|
||||
flag_status can_flag_get(can_type* can_x, uint32_t can_flag);
|
||||
void can_flag_clear(can_type* can_x, uint32_t can_flag);
|
||||
|
||||
|
||||
@ -461,8 +461,7 @@ typedef enum
|
||||
CRM_CLKOUT_ADC = 0x11, /*!< output adcclk to clkout pin */
|
||||
CRM_CLKOUT_HICK = 0x12, /*!< output high speed internal clock to clkout pin */
|
||||
CRM_CLKOUT_LICK = 0x13, /*!< output low speed internal clock to clkout pin */
|
||||
CRM_CLKOUT_LEXT = 0x14, /*!< output low speed external crystal to clkout pin */
|
||||
CRM_CLKOUT_USBHS = 0x15 /*!< output usbhsclk to clkout pin */
|
||||
CRM_CLKOUT_LEXT = 0x14 /*!< output low speed external crystal to clkout pin */
|
||||
} crm_clkout_select_type;
|
||||
|
||||
/**
|
||||
@ -1179,6 +1178,7 @@ void crm_reset(void);
|
||||
void crm_lext_bypass(confirm_state new_state);
|
||||
void crm_hext_bypass(confirm_state new_state);
|
||||
flag_status crm_flag_get(uint32_t flag);
|
||||
flag_status crm_interrupt_flag_get(uint32_t flag);
|
||||
error_status crm_hext_stable_wait(void);
|
||||
void crm_hick_clock_trimming_set(uint8_t trim_value);
|
||||
void crm_hick_clock_calibration_set(uint8_t cali_value);
|
||||
|
||||
@ -113,6 +113,7 @@ typedef struct
|
||||
__IO uint32_t reserved1 : 29;/* [31:3] */
|
||||
} ctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief debug apb1 frz register, offset:0x08
|
||||
*/
|
||||
@ -145,8 +146,9 @@ typedef struct
|
||||
__IO uint32_t reserved6 : 3;/* [31:29] */
|
||||
} apb1_frz_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief debug apb2 frz register, offset:0x0c
|
||||
* @brief debug apb2 frz register, offset:0x0C
|
||||
*/
|
||||
union
|
||||
{
|
||||
@ -163,6 +165,26 @@ typedef struct
|
||||
} apb2_frz_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief debug reserved1 register, offset:0x10~0x1C
|
||||
*/
|
||||
__IO uint32_t reserved1[4];
|
||||
|
||||
/**
|
||||
* @brief debug ser id register, offset:0x20
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ser_id;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t rev_id : 3;/* [2:0] */
|
||||
__IO uint32_t reserved1 : 5;/* [7:3] */
|
||||
__IO uint32_t ser_id : 8;/* [15:8] */
|
||||
__IO uint32_t reserved2 : 16;/* [31:16] */
|
||||
} ser_id_bit;
|
||||
};
|
||||
|
||||
} debug_type;
|
||||
|
||||
/**
|
||||
|
||||
@ -727,6 +727,7 @@ uint16_t dma_data_number_get(dma_channel_type *dmax_channely);
|
||||
void dma_interrupt_enable(dma_channel_type *dmax_channely, uint32_t dma_int, confirm_state new_state);
|
||||
void dma_channel_enable(dma_channel_type *dmax_channely, confirm_state new_state);
|
||||
flag_status dma_flag_get(uint32_t dmax_flag);
|
||||
flag_status dma_interrupt_flag_get(uint32_t dmax_flag);
|
||||
void dma_flag_clear(uint32_t dmax_flag);
|
||||
void dma_default_para_init(dma_init_type *dma_init_struct);
|
||||
void dma_init(dma_channel_type *dmax_channely, dma_init_type *dma_init_struct);
|
||||
@ -742,8 +743,10 @@ void dmamux_generator_config(dmamux_generator_type *dmamux_gen_x, dmamux_gen_ini
|
||||
void dmamux_sync_interrupt_enable(dmamux_channel_type *dmamux_channelx, confirm_state new_state);
|
||||
void dmamux_generator_interrupt_enable(dmamux_generator_type *dmamux_gen_x, confirm_state new_state);
|
||||
flag_status dmamux_sync_flag_get(dma_type *dma_x, uint32_t flag);
|
||||
flag_status dmamux_sync_interrupt_flag_get(dma_type *dma_x, uint32_t flag);
|
||||
void dmamux_sync_flag_clear(dma_type *dma_x, uint32_t flag);
|
||||
flag_status dmamux_generator_flag_get(dma_type *dma_x, uint32_t flag);
|
||||
flag_status dmamux_generator_interrupt_flag_get(dma_type *dma_x, uint32_t flag);
|
||||
void dmamux_generator_flag_clear(dma_type *dma_x, uint32_t flag);
|
||||
|
||||
/**
|
||||
|
||||
@ -1174,6 +1174,7 @@ void ertc_tamper_enable(ertc_tamper_select_type tamper_x, confirm_state new_stat
|
||||
void ertc_interrupt_enable(uint32_t source, confirm_state new_state);
|
||||
flag_status ertc_interrupt_get(uint32_t source);
|
||||
flag_status ertc_flag_get(uint32_t flag);
|
||||
flag_status ertc_interrupt_flag_get(uint32_t flag);
|
||||
void ertc_flag_clear(uint32_t flag);
|
||||
void ertc_bpr_data_write(ertc_dt_type dt, uint32_t data);
|
||||
uint32_t ertc_bpr_data_read(ertc_dt_type dt);
|
||||
|
||||
@ -209,6 +209,7 @@ void exint_default_para_init(exint_init_type *exint_struct);
|
||||
void exint_init(exint_init_type *exint_struct);
|
||||
void exint_flag_clear(uint32_t exint_line);
|
||||
flag_status exint_flag_get(uint32_t exint_line);
|
||||
flag_status exint_interrupt_flag_get(uint32_t exint_line);
|
||||
void exint_software_interrupt_event_generate(uint32_t exint_line);
|
||||
void exint_interrupt_enable(uint32_t exint_line, confirm_state new_state);
|
||||
void exint_event_enable(uint32_t exint_line, confirm_state new_state);
|
||||
|
||||
@ -155,12 +155,12 @@ typedef enum
|
||||
{
|
||||
I2C_ADDR2_NOMASK = 0x00, /*!< compare bit [7:1] */
|
||||
I2C_ADDR2_MASK01 = 0x01, /*!< only compare bit [7:2] */
|
||||
I2C_ADDR2_MASK02 = 0x02, /*!< only compare bit [7:2] */
|
||||
I2C_ADDR2_MASK03 = 0x03, /*!< only compare bit [7:3] */
|
||||
I2C_ADDR2_MASK04 = 0x04, /*!< only compare bit [7:4] */
|
||||
I2C_ADDR2_MASK05 = 0x05, /*!< only compare bit [7:5] */
|
||||
I2C_ADDR2_MASK06 = 0x06, /*!< only compare bit [7:6] */
|
||||
I2C_ADDR2_MASK07 = 0x07 /*!< only compare bit [7] */
|
||||
I2C_ADDR2_MASK02 = 0x02, /*!< only compare bit [7:3] */
|
||||
I2C_ADDR2_MASK03 = 0x03, /*!< only compare bit [7:4] */
|
||||
I2C_ADDR2_MASK04 = 0x04, /*!< only compare bit [7:5] */
|
||||
I2C_ADDR2_MASK05 = 0x05, /*!< only compare bit [7:6] */
|
||||
I2C_ADDR2_MASK06 = 0x06, /*!< only compare bit [7] */
|
||||
I2C_ADDR2_MASK07 = 0x07 /*!< response all addresses other than those reserved for i2c */
|
||||
} i2c_addr2_mask_type;
|
||||
|
||||
/**
|
||||
@ -456,6 +456,7 @@ void i2c_stop_generate(i2c_type *i2c_x);
|
||||
void i2c_data_send(i2c_type *i2c_x, uint8_t data);
|
||||
uint8_t i2c_data_receive(i2c_type *i2c_x);
|
||||
flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag);
|
||||
flag_status i2c_interrupt_flag_get(i2c_type *i2c_x, uint32_t flag);
|
||||
void i2c_flag_clear(i2c_type *i2c_x, uint32_t flag);
|
||||
|
||||
/**
|
||||
|
||||
@ -126,8 +126,7 @@ typedef enum
|
||||
typedef enum
|
||||
{
|
||||
PWC_REGULATOR_ON = 0x00, /*!< voltage regulator state on when deepsleep mode */
|
||||
PWC_REGULATOR_LOW_POWER = 0x01, /*!< voltage regulator state low power when deepsleep mode */
|
||||
PWC_REGULATOR_EXTRA_LOW_POWER = 0x02 /*!< voltage regulator state extra low power when deepsleep mode */
|
||||
PWC_REGULATOR_EXTRA_LOW_POWER = 0x01 /*!< voltage regulator state extra low power when deepsleep mode */
|
||||
} pwc_regulator_type ;
|
||||
|
||||
/**
|
||||
|
||||
@ -121,11 +121,11 @@ typedef enum
|
||||
typedef enum
|
||||
{
|
||||
QSPI_CLK_DIV_2 = 0x00, /*!< qspi clk divide by 2 */
|
||||
QSPI_CLK_DIV_3 = 0x04, /*!< qspi clk divide by 3 */
|
||||
QSPI_CLK_DIV_4 = 0x01, /*!< qspi clk divide by 4 */
|
||||
QSPI_CLK_DIV_5 = 0x05, /*!< qspi clk divide by 5 */
|
||||
QSPI_CLK_DIV_6 = 0x02, /*!< qspi clk divide by 6 */
|
||||
QSPI_CLK_DIV_8 = 0x03, /*!< qspi clk divide by 8 */
|
||||
QSPI_CLK_DIV_3 = 0x04, /*!< qspi clk divide by 3 */
|
||||
QSPI_CLK_DIV_5 = 0x05, /*!< qspi clk divide by 5 */
|
||||
QSPI_CLK_DIV_10 = 0x06, /*!< qspi clk divide by 10 */
|
||||
QSPI_CLK_DIV_12 = 0x07 /*!< qspi clk divide by 12 */
|
||||
} qspi_clk_div_type;
|
||||
@ -177,7 +177,7 @@ typedef enum
|
||||
{
|
||||
QSPI_DMA_FIFO_THOD_WORD08 = 0x00, /*!< qspi dma fifo threshold 8 words */
|
||||
QSPI_DMA_FIFO_THOD_WORD16 = 0x01, /*!< qspi dma fifo threshold 16 words */
|
||||
QSPI_DMA_FIFO_THOD_WORD32 = 0x02 /*!< qspi dma fifo threshold 32 words */
|
||||
QSPI_DMA_FIFO_THOD_WORD24 = 0x02 /*!< qspi dma fifo threshold 24 words */
|
||||
} qspi_dma_fifo_thod_type;
|
||||
|
||||
/**
|
||||
@ -185,7 +185,7 @@ typedef enum
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
confirm_state pe_mode_enable; /*!< perfornance enhance mode enable */
|
||||
confirm_state pe_mode_enable; /*!< performance enhance mode enable */
|
||||
uint8_t pe_mode_operate_code; /*!< performance enhance mode operate code */
|
||||
uint8_t instruction_code; /*!< instruction code */
|
||||
qspi_cmd_inslen_type instruction_length; /*!< instruction code length */
|
||||
@ -458,9 +458,23 @@ typedef struct
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief qspi reserved register, offset:0x40~4C
|
||||
* @brief qspi ctrl3 register, offset:0x40
|
||||
*/
|
||||
__IO uint32_t reserved2[4];
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl3;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t reserved1 : 8; /* [7:0] */
|
||||
__IO uint32_t ispc : 1; /* [8] */
|
||||
__IO uint32_t reserved2 : 23;/* [31:9] */
|
||||
} ctrl3_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief qspi reserved register, offset:0x44~4C
|
||||
*/
|
||||
__IO uint32_t reserved2[3];
|
||||
|
||||
/**
|
||||
* @brief qspi rev register, offset:0x50
|
||||
@ -505,13 +519,15 @@ typedef struct
|
||||
* @{
|
||||
*/
|
||||
|
||||
void qspi_reset(qspi_type* qspi_x);
|
||||
void qspi_encryption_enable(qspi_type* qspi_x, confirm_state new_state);
|
||||
void qspi_sck_mode_set( qspi_type* qspi_x, qspi_clk_mode_type new_mode);
|
||||
void qspi_sck_mode_set(qspi_type* qspi_x, qspi_clk_mode_type new_mode);
|
||||
void qspi_clk_division_set(qspi_type* qspi_x, qspi_clk_div_type new_clkdiv);
|
||||
void qspi_xip_cache_bypass_set(qspi_type* qspi_x, confirm_state new_state);
|
||||
void qspi_interrupt_enable(qspi_type* qspi_x, confirm_state new_state);
|
||||
flag_status qspi_flag_get(qspi_type* qspi_x, uint32_t flag);
|
||||
void qspi_flag_clear( qspi_type* qspi_x, uint32_t flag);
|
||||
flag_status qspi_interrupt_flag_get(qspi_type* qspi_x, uint32_t flag);
|
||||
void qspi_flag_clear(qspi_type* qspi_x, uint32_t flag);
|
||||
void qspi_dma_rx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_threshold);
|
||||
void qspi_dma_tx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_threshold);
|
||||
void qspi_dma_enable(qspi_type* qspi_x, confirm_state new_state);
|
||||
@ -525,6 +541,7 @@ uint32_t qspi_word_read(qspi_type* qspi_x);
|
||||
void qspi_word_write(qspi_type* qspi_x, uint32_t value);
|
||||
void qspi_half_word_write(qspi_type* qspi_x, uint16_t value);
|
||||
void qspi_byte_write(qspi_type* qspi_x, uint8_t value);
|
||||
void qspi_auto_ispc_enable(qspi_type* qspi_x);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@ -55,8 +55,6 @@ extern "C" {
|
||||
typedef enum
|
||||
{
|
||||
SCFG_IR_SOURCE_TMR10 = 0x00, /* infrared signal source select tmr10 */
|
||||
SCFG_IR_SOURCE_USART1 = 0x01, /* infrared signal source select usart1 */
|
||||
SCFG_IR_SOURCE_USART2 = 0x02 /* infrared signal source select usart2 */
|
||||
} scfg_ir_source_type;
|
||||
|
||||
/**
|
||||
@ -277,7 +275,7 @@ void scfg_infrared_config(scfg_ir_source_type source, scfg_ir_polarity_type pola
|
||||
scfg_mem_map_type scfg_mem_map_get(void);
|
||||
void scfg_i2s_full_duplex_config(scfg_i2s_type i2s_full_duplex);
|
||||
void scfg_pvm_lock_enable(confirm_state new_state);
|
||||
error_status scfg_sram_operr_status_get(void);
|
||||
flag_status scfg_sram_operr_status_get(void);
|
||||
void scfg_sram_operr_lock_enable(confirm_state new_state);
|
||||
void scfg_lockup_enable(confirm_state new_state);
|
||||
void scfg_exint_line_config(scfg_port_source_type port_source, scfg_pins_source_type pin_source);
|
||||
|
||||
@ -508,6 +508,7 @@ void spi_i2s_dma_receiver_enable(spi_type* spi_x, confirm_state new_state);
|
||||
void spi_i2s_data_transmit(spi_type* spi_x, uint16_t tx_data);
|
||||
uint16_t spi_i2s_data_receive(spi_type* spi_x);
|
||||
flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag);
|
||||
flag_status spi_i2s_interrupt_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag);
|
||||
void spi_i2s_flag_clear(spi_type* spi_x, uint32_t spi_i2s_flag);
|
||||
void i2sf_full_duplex_mode_enable(spi_type* spi_x, confirm_state new_state);
|
||||
void i2sf_pcm_sample_clock_set(spi_type* spi_x, i2s_pcm_sample_clock_type pcm_sample_clock);
|
||||
|
||||
@ -444,7 +444,6 @@ typedef struct
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t brk_filter_value; /*!< tmr brake filter value */
|
||||
uint8_t deadtime; /*!< dead-time generator setup */
|
||||
tmr_brk_polarity_type brk_polarity; /*!< tmr brake polarity */
|
||||
tmr_wp_level_type wp_level; /*!< write protect configuration */
|
||||
@ -972,6 +971,7 @@ void tmr_trigger_input_select(tmr_type *tmr_x, sub_tmr_input_sel_type trigger_se
|
||||
void tmr_sub_sync_mode_set(tmr_type *tmr_x, confirm_state new_state);
|
||||
void tmr_dma_request_enable(tmr_type *tmr_x, tmr_dma_request_type dma_request, confirm_state new_state);
|
||||
void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state new_state);
|
||||
flag_status tmr_interrupt_flag_get(tmr_type *tmr_x, uint32_t tmr_flag);
|
||||
flag_status tmr_flag_get(tmr_type *tmr_x, uint32_t tmr_flag);
|
||||
void tmr_flag_clear(tmr_type *tmr_x, uint32_t tmr_flag);
|
||||
void tmr_event_sw_trigger(tmr_type *tmr_x, tmr_event_trigger_type tmr_event);
|
||||
@ -993,6 +993,7 @@ void tmr_force_output_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel,
|
||||
void tmr_dma_control_config(tmr_type *tmr_x, tmr_dma_transfer_length_type dma_length, \
|
||||
tmr_dma_address_type dma_base_address);
|
||||
void tmr_brkdt_config(tmr_type *tmr_x, tmr_brkdt_config_type *brkdt_struct);
|
||||
void tmr_brk_filter_value_set(tmr_type *tmr_x, uint8_t filter_value);
|
||||
void tmr_iremap_config(tmr_type *tmr_x, tmr_input_remap_type input_remap);
|
||||
|
||||
/**
|
||||
|
||||
@ -184,6 +184,15 @@ typedef enum
|
||||
USART_ID_RELATED_DATA_BIT = 0x01 /*!< usart id bit num related data bits */
|
||||
} usart_identification_bit_num_type;
|
||||
|
||||
/**
|
||||
* @brief usart de polarity type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_DE_POLARITY_HIGH = 0x00, /*!< usart de polarity high */
|
||||
USART_DE_POLARITY_LOW = 0x01 /*!< usart de polarity low */
|
||||
} usart_de_polarity_type;
|
||||
|
||||
/**
|
||||
* @brief type define usart register all
|
||||
*/
|
||||
@ -418,11 +427,12 @@ void usart_irda_mode_enable(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_irda_low_power_enable(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_hardware_flow_control_set(usart_type* usart_x,usart_hardware_flow_control_type flow_state);
|
||||
flag_status usart_flag_get(usart_type* usart_x, uint32_t flag);
|
||||
flag_status usart_interrupt_flag_get(usart_type* usart_x, uint32_t flag);
|
||||
void usart_flag_clear(usart_type* usart_x, uint32_t flag);
|
||||
void usart_rs485_delay_time_config(usart_type* usart_x, uint8_t start_delay_time, uint8_t complete_delay_time);
|
||||
void usart_transmit_receive_pin_swap(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_id_bit_num_set(usart_type* usart_x, usart_identification_bit_num_type id_bit_num);
|
||||
void usart_de_polarity_reverse(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_de_polarity_set(usart_type* usart_x, usart_de_polarity_type de_polarity);
|
||||
void usart_rs485_mode_enable(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_msb_transmit_first_enable(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_dt_polarity_reverse(usart_type* usart_x, confirm_state new_state);
|
||||
|
||||
@ -134,6 +134,7 @@ void wwdt_flag_clear(void);
|
||||
void wwdt_enable(uint8_t wwdt_cnt);
|
||||
void wwdt_interrupt_enable(void);
|
||||
flag_status wwdt_flag_get(void);
|
||||
flag_status wwdt_interrupt_flag_get(void);
|
||||
void wwdt_counter_set(uint8_t wwdt_cnt);
|
||||
void wwdt_window_counter_set(uint8_t window_cnt);
|
||||
|
||||
|
||||
@ -188,6 +188,22 @@ flag_status acc_flag_get(uint16_t acc_flag)
|
||||
return (flag_status)(ACC->sts_bit.rslost);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief check whether the specified acc interrupt flag is set or not.
|
||||
* @param acc_flag: specifies the flag to check.
|
||||
* this parameter can be one of the following values:
|
||||
* - ACC_RSLOST_FLAG
|
||||
* - ACC_CALRDY_FLAG
|
||||
* @retval flag_status (SET or RESET)
|
||||
*/
|
||||
flag_status acc_interrupt_flag_get(uint16_t acc_flag)
|
||||
{
|
||||
if(acc_flag == ACC_CALRDY_FLAG)
|
||||
return (flag_status)(ACC->sts_bit.calrdy && ACC->ctrl1_bit.calrdyien);
|
||||
else
|
||||
return (flag_status)(ACC->sts_bit.rslost && ACC->ctrl1_bit.eien);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief clear the specified acc flag is set or not.
|
||||
* @param acc_flag: specifies the flag to check.
|
||||
|
||||
@ -799,10 +799,10 @@ uint16_t adc_ordinary_conversion_data_get(adc_type *adc_x)
|
||||
* ADC1.
|
||||
* @param adc_preempt_channel: select the preempt channel.
|
||||
* this parameter can be one of the following values:
|
||||
* - ADC_PREEMPTED_CHANNEL_1
|
||||
* - ADC_PREEMPTED_CHANNEL_2
|
||||
* - ADC_PREEMPTED_CHANNEL_3
|
||||
* - ADC_PREEMPTED_CHANNEL_4
|
||||
* - ADC_PREEMPT_CHANNEL_1
|
||||
* - ADC_PREEMPT_CHANNEL_2
|
||||
* - ADC_PREEMPT_CHANNEL_3
|
||||
* - ADC_PREEMPT_CHANNEL_4
|
||||
* @retval the conversion data for selection preempt channel.
|
||||
*/
|
||||
uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel)
|
||||
@ -857,6 +857,47 @@ flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag)
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief get interrupt flag of the specified adc peripheral.
|
||||
* @param adc_x: select the adc peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* ADC1.
|
||||
* @param adc_flag: select the adc flag.
|
||||
* this parameter can be one of the following values:
|
||||
* - ADC_VMOR_FLAG
|
||||
* - ADC_CCE_FLAG
|
||||
* - ADC_PCCE_FLAG
|
||||
* @retval the new state of adc flag status(SET or RESET).
|
||||
*/
|
||||
flag_status adc_interrupt_flag_get(adc_type *adc_x, uint8_t adc_flag)
|
||||
{
|
||||
flag_status status = RESET;
|
||||
switch(adc_flag)
|
||||
{
|
||||
case ADC_VMOR_FLAG:
|
||||
if(adc_x->sts_bit.vmor && adc_x->ctrl1_bit.vmorien)
|
||||
{
|
||||
status = SET;
|
||||
}
|
||||
break;
|
||||
case ADC_CCE_FLAG:
|
||||
if(adc_x->sts_bit.cce && adc_x->ctrl1_bit.cceien)
|
||||
{
|
||||
status = SET;
|
||||
}
|
||||
break;
|
||||
case ADC_PCCE_FLAG:
|
||||
if(adc_x->sts_bit.pcce && adc_x->ctrl1_bit.pcceien)
|
||||
{
|
||||
status = SET;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief clear flag of the specified adc peripheral.
|
||||
* @param adc_x: select the adc peripheral.
|
||||
|
||||
@ -928,6 +928,102 @@ void can_interrupt_enable(can_type* can_x, uint32_t can_int, confirm_state new_s
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief get interrupt flag of the specified can peripheral.
|
||||
* @param can_x: select the can peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* CAN1,CAN2.
|
||||
* @param can_flag: select the flag.
|
||||
* this parameter can be one of the following flags:
|
||||
* - CAN_EAF_FLAG
|
||||
* - CAN_EPF_FLAG
|
||||
* - CAN_BOF_FLAG
|
||||
* - CAN_ETR_FLAG
|
||||
* - CAN_EOIF_FLAG
|
||||
* - CAN_TM0TCF_FLAG
|
||||
* - CAN_TM1TCF_FLAG
|
||||
* - CAN_TM2TCF_FLAG
|
||||
* - CAN_RF0MN_FLAG
|
||||
* - CAN_RF0FF_FLAG
|
||||
* - CAN_RF0OF_FLAG
|
||||
* - CAN_RF1MN_FLAG
|
||||
* - CAN_RF1FF_FLAG
|
||||
* - CAN_RF1OF_FLAG
|
||||
* - CAN_QDZIF_FLAG
|
||||
* - CAN_EDZC_FLAG
|
||||
* - CAN_TMEF_FLAG
|
||||
* note:the state of CAN_EDZC_FLAG need to check dzc and edzif bit
|
||||
* note:the state of CAN_TMEF_FLAG need to check rqc0,rqc1 and rqc2 bit
|
||||
* @retval status of can_flag, the returned value can be:SET or RESET.
|
||||
*/
|
||||
flag_status can_interrupt_flag_get(can_type* can_x, uint32_t can_flag)
|
||||
{
|
||||
flag_status bit_status = RESET;
|
||||
flag_status int_status = RESET;
|
||||
|
||||
switch(can_flag)
|
||||
{
|
||||
case CAN_EAF_FLAG:
|
||||
int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.eaien);
|
||||
break;
|
||||
case CAN_EPF_FLAG:
|
||||
int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.epien);
|
||||
break;
|
||||
case CAN_BOF_FLAG:
|
||||
int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.boien);
|
||||
break;
|
||||
case CAN_ETR_FLAG:
|
||||
int_status = (flag_status)(can_x->inten_bit.eoien && can_x->inten_bit.etrien);
|
||||
break;
|
||||
case CAN_EOIF_FLAG:
|
||||
int_status = (flag_status)can_x->inten_bit.eoien;
|
||||
break;
|
||||
case CAN_TM0TCF_FLAG:
|
||||
case CAN_TM1TCF_FLAG:
|
||||
case CAN_TM2TCF_FLAG:
|
||||
int_status = (flag_status)can_x->inten_bit.tcien;
|
||||
break;
|
||||
case CAN_RF0MN_FLAG:
|
||||
int_status = (flag_status)can_x->inten_bit.rf0mien;
|
||||
break;
|
||||
case CAN_RF0FF_FLAG:
|
||||
int_status = (flag_status)can_x->inten_bit.rf0fien;
|
||||
break;
|
||||
case CAN_RF0OF_FLAG:
|
||||
int_status = (flag_status)can_x->inten_bit.rf0oien;
|
||||
break;
|
||||
case CAN_RF1MN_FLAG:
|
||||
int_status = (flag_status)can_x->inten_bit.rf1mien;
|
||||
break;
|
||||
case CAN_RF1FF_FLAG:
|
||||
int_status = (flag_status)can_x->inten_bit.rf1fien;
|
||||
break;
|
||||
case CAN_RF1OF_FLAG:
|
||||
int_status = (flag_status)can_x->inten_bit.rf1oien;
|
||||
break;
|
||||
case CAN_QDZIF_FLAG:
|
||||
int_status = (flag_status)can_x->inten_bit.qdzien;
|
||||
break;
|
||||
case CAN_EDZC_FLAG:
|
||||
int_status = (flag_status)can_x->inten_bit.edzien;
|
||||
break;
|
||||
case CAN_TMEF_FLAG:
|
||||
int_status = (flag_status)can_x->inten_bit.tcien;
|
||||
break;
|
||||
default:
|
||||
int_status = RESET;
|
||||
break;
|
||||
}
|
||||
|
||||
if(int_status != SET)
|
||||
{
|
||||
return RESET;
|
||||
}
|
||||
bit_status = can_flag_get(can_x, can_flag);
|
||||
|
||||
return bit_status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief get flag of the specified can peripheral.
|
||||
* @param can_x: select the can peripheral.
|
||||
|
||||
@ -141,6 +141,64 @@ flag_status crm_flag_get(uint32_t flag)
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief get crm interrupt flag status
|
||||
* @param flag
|
||||
* this parameter can be one of the following values:
|
||||
* - CRM_LICK_READY_INT_FLAG
|
||||
* - CRM_LEXT_READY_INT_FLAG
|
||||
* - CRM_HICK_READY_INT_FLAG
|
||||
* - CRM_HEXT_READY_INT_FLAG
|
||||
* - CRM_PLL_READY_INT_FLAG
|
||||
* - CRM_CLOCK_FAILURE_INT_FLAG
|
||||
* @retval flag_status (SET or RESET)
|
||||
*/
|
||||
flag_status crm_interrupt_flag_get(uint32_t flag)
|
||||
{
|
||||
flag_status status = RESET;
|
||||
switch(flag)
|
||||
{
|
||||
case CRM_LICK_READY_INT_FLAG:
|
||||
if(CRM->clkint_bit.lickstblf && CRM->clkint_bit.lickstblien)
|
||||
{
|
||||
status = SET;
|
||||
}
|
||||
break;
|
||||
case CRM_LEXT_READY_INT_FLAG:
|
||||
if(CRM->clkint_bit.lextstblf && CRM->clkint_bit.lextstblien)
|
||||
{
|
||||
status = SET;
|
||||
}
|
||||
break;
|
||||
case CRM_HICK_READY_INT_FLAG:
|
||||
if(CRM->clkint_bit.hickstblf && CRM->clkint_bit.hickstblien)
|
||||
{
|
||||
status = SET;
|
||||
}
|
||||
break;
|
||||
case CRM_HEXT_READY_INT_FLAG:
|
||||
if(CRM->clkint_bit.hextstblf && CRM->clkint_bit.hextstblien)
|
||||
{
|
||||
status = SET;
|
||||
}
|
||||
break;
|
||||
case CRM_PLL_READY_INT_FLAG:
|
||||
if(CRM->clkint_bit.pllstblf && CRM->clkint_bit.pllstblien)
|
||||
{
|
||||
status = SET;
|
||||
}
|
||||
break;
|
||||
case CRM_CLOCK_FAILURE_INT_FLAG:
|
||||
if(CRM->clkint_bit.cfdf && CRM->ctrl_bit.cfden)
|
||||
{
|
||||
status = SET;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief wait for hext stable
|
||||
* @param none
|
||||
@ -871,7 +929,7 @@ void crm_clocks_freq_get(crm_clocks_freq_type *clocks_struct)
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief set crm clkout2
|
||||
* @brief set crm clkout
|
||||
* @param clkout
|
||||
* this parameter can be one of the following values:
|
||||
* - CRM_CLKOUT_SCLK
|
||||
@ -882,7 +940,6 @@ void crm_clocks_freq_get(crm_clocks_freq_type *clocks_struct)
|
||||
* - CRM_CLKOUT_HICK
|
||||
* - CRM_CLKOUT_LICK
|
||||
* - CRM_CLKOUT_LEXT
|
||||
* - CRM_CLKOUT_USBHS
|
||||
* @retval none
|
||||
*/
|
||||
void crm_clock_out_set(crm_clkout_select_type clkout)
|
||||
@ -899,7 +956,7 @@ void crm_clock_out_set(crm_clkout_select_type clkout)
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief set crm clkout1 division1
|
||||
* @brief set crm clkout division1
|
||||
* @param div1
|
||||
* this parameter can be one of the following values:
|
||||
* - CRM_CLKOUT_DIV1_1
|
||||
|
||||
@ -197,6 +197,52 @@ void dma_channel_enable(dma_channel_type *dmax_channely, confirm_state new_state
|
||||
dmax_channely->ctrl_bit.chen = new_state;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief get dma interrupt flag
|
||||
* @param dmax_flag
|
||||
* this parameter can be one of the following values:
|
||||
* - DMA1_FDT1_FLAG - DMA1_HDT1_FLAG - DMA1_DTERR1_FLAG
|
||||
* - DMA1_FDT2_FLAG - DMA1_HDT2_FLAG - DMA1_DTERR2_FLAG
|
||||
* - DMA1_FDT3_FLAG - DMA1_HDT3_FLAG - DMA1_DTERR3_FLAG
|
||||
* - DMA1_FDT4_FLAG - DMA1_HDT4_FLAG - DMA1_DTERR4_FLAG
|
||||
* - DMA1_FDT5_FLAG - DMA1_HDT5_FLAG - DMA1_DTERR5_FLAG
|
||||
* - DMA1_FDT6_FLAG - DMA1_HDT6_FLAG - DMA1_DTERR6_FLAG
|
||||
* - DMA1_FDT7_FLAG - DMA1_HDT7_FLAG - DMA1_DTERR7_FLAG
|
||||
* - DMA2_FDT1_FLAG - DMA2_HDT1_FLAG - DMA2_DTERR1_FLAG
|
||||
* - DMA2_FDT2_FLAG - DMA2_HDT2_FLAG - DMA2_DTERR2_FLAG
|
||||
* - DMA2_FDT3_FLAG - DMA2_HDT3_FLAG - DMA2_DTERR3_FLAG
|
||||
* - DMA2_FDT4_FLAG - DMA2_HDT4_FLAG - DMA2_DTERR4_FLAG
|
||||
* - DMA2_FDT5_FLAG - DMA2_HDT5_FLAG - DMA2_DTERR5_FLAG
|
||||
* - DMA2_FDT6_FLAG - DMA2_HDT6_FLAG - DMA2_DTERR6_FLAG
|
||||
* - DMA2_FDT7_FLAG - DMA2_HDT7_FLAG - DMA2_DTERR7_FLAG
|
||||
* @retval state of dma flag
|
||||
*/
|
||||
flag_status dma_interrupt_flag_get(uint32_t dmax_flag)
|
||||
{
|
||||
flag_status status = RESET;
|
||||
uint32_t temp = 0;
|
||||
|
||||
if(dmax_flag > 0x10000000)
|
||||
{
|
||||
temp = DMA2->sts;
|
||||
}
|
||||
else
|
||||
{
|
||||
temp = DMA1->sts;
|
||||
}
|
||||
|
||||
if ((temp & dmax_flag) != (uint16_t)RESET)
|
||||
{
|
||||
status = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
status = RESET;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief dma flag get.
|
||||
* @param dma_flag
|
||||
@ -599,6 +645,78 @@ flag_status dmamux_sync_flag_get(dma_type *dma_x, uint32_t flag)
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief dmamux sync interrupt flag get.
|
||||
* @param dma_x : pointer to a dma_type structure, can be DMA1 or DMA2.
|
||||
* @param flag
|
||||
* this parameter can be any combination of the following values:
|
||||
* - DMAMUX_SYNC_OV1_FLAG
|
||||
* - DMAMUX_SYNC_OV2_FLAG
|
||||
* - DMAMUX_SYNC_OV3_FLAG
|
||||
* - DMAMUX_SYNC_OV4_FLAG
|
||||
* - DMAMUX_SYNC_OV5_FLAG
|
||||
* - DMAMUX_SYNC_OV6_FLAG
|
||||
* - DMAMUX_SYNC_OV7_FLAG
|
||||
* @retval state of dmamux sync flag.
|
||||
*/
|
||||
flag_status dmamux_sync_interrupt_flag_get(dma_type *dma_x, uint32_t flag)
|
||||
{
|
||||
|
||||
flag_status bitstatus = RESET;
|
||||
uint32_t sync_int_temp = flag;
|
||||
uint32_t index = 0;
|
||||
uint32_t tmpreg = 0, enablestatus = 0;
|
||||
uint32_t regoffset = 0x4;
|
||||
|
||||
while((sync_int_temp & 0x00000001) == RESET)
|
||||
{
|
||||
sync_int_temp = sync_int_temp >> 1;
|
||||
index++;
|
||||
}
|
||||
|
||||
if(dma_x == DMA1)
|
||||
{
|
||||
tmpreg = *(uint32_t*)(DMA1MUX_BASE + (index * regoffset));
|
||||
}
|
||||
else
|
||||
{
|
||||
tmpreg = *(uint32_t*)(DMA2MUX_BASE + (index * regoffset));
|
||||
}
|
||||
|
||||
if((tmpreg & (uint32_t)0x00000100) != (uint32_t)RESET)
|
||||
{
|
||||
enablestatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
enablestatus = RESET;
|
||||
}
|
||||
|
||||
if(dma_x == DMA1)
|
||||
{
|
||||
if(((DMA1->muxsyncsts & flag) != (uint32_t)RESET) && (enablestatus != RESET))
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if(((DMA2->muxsyncsts & flag) != (uint32_t)RESET) && (enablestatus != RESET))
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief dmamux sync flag clear.
|
||||
* @param dma_x : pointer to a dma_type structure, can be DMA1 or DMA2.
|
||||
@ -641,6 +759,70 @@ flag_status dmamux_generator_flag_get(dma_type *dma_x, uint32_t flag)
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief dmamux request generator interrupt flag get.
|
||||
* @param dma_x : pointer to a dma_type structure, can be DMA1 or DMA2.
|
||||
* @param flag
|
||||
* this parameter can be any combination of the following values:
|
||||
* - DMAMUX_GEN_TRIG_OV1_FLAG
|
||||
* - DMAMUX_GEN_TRIG_OV2_FLAG
|
||||
* - DMAMUX_GEN_TRIG_OV3_FLAG
|
||||
* - DMAMUX_GEN_TRIG_OV4_FLAG
|
||||
* @retval state of dmamux sync flag.
|
||||
*/
|
||||
flag_status dmamux_generator_interrupt_flag_get(dma_type *dma_x, uint32_t flag)
|
||||
{
|
||||
flag_status bitstatus = RESET;
|
||||
uint32_t sync_int_temp = flag;
|
||||
uint32_t index = 0;
|
||||
uint32_t tmpreg = 0, enablestatus = 0;
|
||||
uint32_t regoffset = 0x4;
|
||||
|
||||
while((sync_int_temp & 0x00000001) == RESET)
|
||||
{
|
||||
sync_int_temp = sync_int_temp >> 1;
|
||||
index++;
|
||||
}
|
||||
|
||||
if(dma_x == DMA1)
|
||||
tmpreg = *(uint32_t*)(DMA1MUX_GENERATOR1_BASE + (index * regoffset));
|
||||
else
|
||||
tmpreg = *(uint32_t*)(DMA2MUX_GENERATOR1_BASE + (index * regoffset));
|
||||
|
||||
if((tmpreg & (uint32_t)0x00000100) != (uint32_t)RESET)
|
||||
{
|
||||
enablestatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
enablestatus = RESET;
|
||||
}
|
||||
if(dma_x == DMA1)
|
||||
{
|
||||
if(((DMA1->muxgsts & flag) != (uint32_t)RESET) && (enablestatus != RESET))
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if(((DMA2->muxgsts & flag) != (uint32_t)RESET) && (enablestatus != RESET))
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
}
|
||||
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief dmamux request generator flag clear.
|
||||
* @param dma_x : pointer to a dma_type structure, can be DMA1 or DMA2.
|
||||
|
||||
@ -1482,6 +1482,55 @@ flag_status ertc_flag_get(uint32_t flag)
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief get interrupt flag status.
|
||||
* @param flag: specifies the flag to check.
|
||||
* this parameter can be one of the following values:
|
||||
* - ERTC_ALAF_FLAG: alarm clock a flag.
|
||||
* - ERTC_ALBF_FLAG: alarm clock b flag.
|
||||
* - ERTC_WATF_FLAG: wakeup timer flag.
|
||||
* - ERTC_TSF_FLAG: timestamp flag.
|
||||
* - ERTC_TP1F_FLAG: tamper detection 1 flag.
|
||||
* - ERTC_TP2F_FLAG: tamper detection 2 flag.
|
||||
* @retval the new state of flag (SET or RESET).
|
||||
*/
|
||||
flag_status ertc_interrupt_flag_get(uint32_t flag)
|
||||
{
|
||||
__IO uint32_t iten = 0;
|
||||
|
||||
switch(flag)
|
||||
{
|
||||
case ERTC_ALAF_FLAG:
|
||||
iten = ERTC->ctrl_bit.alaien;
|
||||
break;
|
||||
case ERTC_ALBF_FLAG:
|
||||
iten = ERTC->ctrl_bit.albien;
|
||||
break;
|
||||
case ERTC_WATF_FLAG:
|
||||
iten = ERTC->ctrl_bit.watien;
|
||||
break;
|
||||
case ERTC_TSF_FLAG:
|
||||
iten = ERTC->ctrl_bit.tsien;
|
||||
break;
|
||||
case ERTC_TP1F_FLAG:
|
||||
case ERTC_TP2F_FLAG:
|
||||
iten = ERTC->tamp_bit.tpien;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
if(((ERTC->sts & flag) != (uint32_t)RESET) && (iten))
|
||||
{
|
||||
return SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
return RESET;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief clear flag status
|
||||
* @param flag: specifies the flag to clear.
|
||||
|
||||
@ -153,6 +153,36 @@ flag_status exint_flag_get(uint32_t exint_line)
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief get exint interrupt flag
|
||||
* @param exint_line
|
||||
* this parameter can be one of the following values:
|
||||
* - EXINT_LINE_0
|
||||
* - EXINT_LINE_1
|
||||
* ...
|
||||
* - EXINT_LINE_21
|
||||
* - EXINT_LINE_22
|
||||
* @retval the new state of exint flag(SET or RESET).
|
||||
*/
|
||||
flag_status exint_interrupt_flag_get(uint32_t exint_line)
|
||||
{
|
||||
flag_status status = RESET;
|
||||
uint32_t exint_flag = 0;
|
||||
exint_flag = EXINT->intsts & exint_line;
|
||||
exint_flag = exint_flag & EXINT->inten;
|
||||
|
||||
if((exint_flag != (uint16_t)RESET))
|
||||
{
|
||||
status = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
status = RESET;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief generate exint software interrupt event
|
||||
* @param exint_line
|
||||
|
||||
@ -536,7 +536,7 @@ flag_status flash_fap_high_level_status_get(void)
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief program the flash system setting byte in usd: wdt_ato_en / depslp_rst / stdby_rst / boot1 / depslp_wdt / stdby_wdt.
|
||||
* @brief program the flash system setting byte in usd: wdt_ato_en / depslp_rst / stdby_rst / boot1 / depslp_wdt / stdby_wdt / ram_prt_chk.
|
||||
* @param usd_ssb: the system setting byte
|
||||
* @note this parameter usd_ssb must contain a combination of all the following 6 types of data
|
||||
* type 1: wdt_ato_en, select the wdt auto start
|
||||
@ -563,6 +563,10 @@ flag_status flash_fap_high_level_status_get(void)
|
||||
* this data can be one of the following values:
|
||||
* - USD_STDBY_WDT_CONTINUE: wdt continue count when entering in standby
|
||||
* - USD_STDBY_WDT_STOP: wdt stop count when entering in standby
|
||||
* type 7: ram_prt_chk, ram parity check disable or enable.
|
||||
* this data can be one of the following values:
|
||||
* - USD_RAM_PRT_CHK_DISABLE: ram parity check disabled
|
||||
* - USD_RAM_PRT_CHK_ENABLE: ram parity check enabled
|
||||
* @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
|
||||
* FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
|
||||
*/
|
||||
@ -593,7 +597,7 @@ flash_status_type flash_ssb_set(uint8_t usd_ssb)
|
||||
* @brief return the flash system setting byte status.
|
||||
* @param none
|
||||
* @retval values from flash_usd register: wdt_ato_en(bit0), depslp_rst(bit1),
|
||||
* stdby_rst(bit2), boot1(bit4), depslp_wdt(bit5) and stdby_wdt(bit6).
|
||||
* stdby_rst(bit2), boot1(bit4), depslp_wdt(bit5), stdby_wdt(bit6) and ram_prt_chk(bit7).
|
||||
*/
|
||||
uint8_t flash_ssb_status_get(void)
|
||||
{
|
||||
|
||||
@ -120,12 +120,12 @@ void i2c_own_address1_set(i2c_type *i2c_x, i2c_address_mode_type mode, uint16_t
|
||||
* this parameter can be one of the following values:
|
||||
* - I2C_ADDR2_NOMASK: compare bit [7:1].
|
||||
* - I2C_ADDR2_MASK01: only compare bit [7:2].
|
||||
* - I2C_ADDR2_MASK02: only compare bit [7:2].
|
||||
* - I2C_ADDR2_MASK03: only compare bit [7:3].
|
||||
* - I2C_ADDR2_MASK04: only compare bit [7:4].
|
||||
* - I2C_ADDR2_MASK05: only compare bit [7:5].
|
||||
* - I2C_ADDR2_MASK06: only compare bit [7:6].
|
||||
* - I2C_ADDR2_MASK07: only compare bit [7].
|
||||
* - I2C_ADDR2_MASK02: only compare bit [7:3].
|
||||
* - I2C_ADDR2_MASK03: only compare bit [7:4].
|
||||
* - I2C_ADDR2_MASK04: only compare bit [7:5].
|
||||
* - I2C_ADDR2_MASK05: only compare bit [7:6].
|
||||
* - I2C_ADDR2_MASK06: only compare bit [7].
|
||||
* - I2C_ADDR2_MASK07: response all addresses other than those reserved for i2c.
|
||||
* @retval none
|
||||
*/
|
||||
void i2c_own_address2_set(i2c_type *i2c_x, uint8_t address, i2c_addr2_mask_type mask)
|
||||
@ -706,6 +706,77 @@ flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag)
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief get interrupt flag status.
|
||||
* @param i2c_x: to select the i2c peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* I2C1, I2C2, I2C3.
|
||||
* @param flag: specifies the flag to check.
|
||||
* this parameter can be one of the following values:
|
||||
* - I2C_TDBE_FLAG: transmit data buffer empty flag.
|
||||
* - I2C_TDIS_FLAG: send interrupt status.
|
||||
* - I2C_RDBF_FLAG: receive data buffer full flag.
|
||||
* - I2C_ADDRF_FLAG: 0~7 bit address match flag.
|
||||
* - I2C_ACKFAIL_FLAG: acknowledge failure flag.
|
||||
* - I2C_STOPF_FLAG: stop condition generation complete flag.
|
||||
* - I2C_TDC_FLAG: transmit data complete flag.
|
||||
* - I2C_TCRLD_FLAG: transmission is complete, waiting to load data.
|
||||
* - I2C_BUSERR_FLAG: bus error flag.
|
||||
* - I2C_ARLOST_FLAG: arbitration lost flag.
|
||||
* - I2C_OUF_FLAG: overflow or underflow flag.
|
||||
* - I2C_PECERR_FLAG: pec receive error flag.
|
||||
* - I2C_TMOUT_FLAG: smbus timeout flag.
|
||||
* - I2C_ALERTF_FLAG: smbus alert flag.
|
||||
* @retval the new state of flag (SET or RESET).
|
||||
*/
|
||||
flag_status i2c_interrupt_flag_get(i2c_type *i2c_x, uint32_t flag)
|
||||
{
|
||||
__IO uint32_t iten = 0;
|
||||
|
||||
switch(flag)
|
||||
{
|
||||
case I2C_TDIS_FLAG:
|
||||
iten = i2c_x->ctrl1_bit.tdien;
|
||||
break;
|
||||
case I2C_RDBF_FLAG:
|
||||
iten = i2c_x->ctrl1_bit.rdien;
|
||||
break;
|
||||
case I2C_ADDRF_FLAG:
|
||||
iten = i2c_x->ctrl1_bit.addrien;
|
||||
break;
|
||||
case I2C_ACKFAIL_FLAG:
|
||||
iten = i2c_x->ctrl1_bit.ackfailien;
|
||||
break;
|
||||
case I2C_STOPF_FLAG:
|
||||
iten = i2c_x->ctrl1_bit.stopien;
|
||||
break;
|
||||
case I2C_TDC_FLAG:
|
||||
case I2C_TCRLD_FLAG:
|
||||
iten = i2c_x->ctrl1_bit.tdcien;
|
||||
break;
|
||||
case I2C_BUSERR_FLAG:
|
||||
case I2C_ARLOST_FLAG:
|
||||
case I2C_OUF_FLAG:
|
||||
case I2C_PECERR_FLAG:
|
||||
case I2C_TMOUT_FLAG:
|
||||
case I2C_ALERTF_FLAG:
|
||||
iten = i2c_x->ctrl1_bit.errien;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
if(((i2c_x->sts & flag) != RESET) && (iten))
|
||||
{
|
||||
return SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
return RESET;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief clear flag status
|
||||
* @param i2c_x: to select the i2c peripheral.
|
||||
|
||||
@ -207,7 +207,6 @@ void pwc_deep_sleep_mode_enter(pwc_deep_sleep_enter_type pwc_deep_sleep_enter)
|
||||
* @param pwc_regulator: set the regulator state.
|
||||
* this parameter can be one of the following values:
|
||||
* - PWC_REGULATOR_ON
|
||||
* - PWC_REGULATOR_LOW_POWER
|
||||
* - PWC_REGULATOR_EXTRA_LOW_POWER
|
||||
* @retval none
|
||||
*/
|
||||
@ -215,15 +214,11 @@ void pwc_voltage_regulate_set(pwc_regulator_type pwc_regulator)
|
||||
{
|
||||
switch(pwc_regulator)
|
||||
{
|
||||
case 0:
|
||||
case PWC_REGULATOR_ON:
|
||||
PWC->ldoov_bit.vrexlpen = 0;
|
||||
PWC->ctrl_bit.vrsel = 0;
|
||||
break;
|
||||
case 1:
|
||||
PWC->ldoov_bit.vrexlpen = 0;
|
||||
PWC->ctrl_bit.vrsel = 1;
|
||||
break;
|
||||
case 2:
|
||||
case PWC_REGULATOR_EXTRA_LOW_POWER:
|
||||
PWC->ldoov_bit.vrexlpen = 1;
|
||||
PWC->ctrl_bit.vrsel = 1;
|
||||
break;
|
||||
@ -242,7 +237,7 @@ void pwc_standby_mode_enter(void)
|
||||
PWC->ctrl_bit.clswef = TRUE;
|
||||
PWC->ctrl_bit.lpsel = TRUE;
|
||||
SCB->SCR |= 0x04;
|
||||
#if defined (__CC_ARM)
|
||||
#if defined (__ARMCC_VERSION)
|
||||
__force_stores();
|
||||
#endif
|
||||
while(1)
|
||||
|
||||
@ -39,6 +39,21 @@
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief deinitialize the qspi peripheral registers to their default reset values.
|
||||
* @param qspi_x: select the qspi peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* QSPI1.
|
||||
* @retval none
|
||||
*/
|
||||
void qspi_reset(qspi_type* qspi_x)
|
||||
{
|
||||
{
|
||||
crm_periph_reset(CRM_QSPI1_PERIPH_RESET, TRUE);
|
||||
crm_periph_reset(CRM_QSPI1_PERIPH_RESET, FALSE);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief enable/disable encryption for qspi.
|
||||
* @note the function must be configured only when qspi in command-port mode!!!
|
||||
@ -131,7 +146,7 @@ void qspi_interrupt_enable(qspi_type* qspi_x, confirm_state new_state)
|
||||
* - QSPI_RXFIFORDY_FLAG
|
||||
* - QSPI_TXFIFORDY_FLAG
|
||||
* - QSPI_CMDSTS_FLAG
|
||||
* @retval the new state of usart_flag (SET or RESET).
|
||||
* @retval the new state of the flag (SET or RESET).
|
||||
*/
|
||||
flag_status qspi_flag_get(qspi_type* qspi_x, uint32_t flag)
|
||||
{
|
||||
@ -153,6 +168,24 @@ flag_status qspi_flag_get(qspi_type* qspi_x, uint32_t flag)
|
||||
return bit_status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief get interrupt flags.
|
||||
* @param qspi_x: select the qspi peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* QSPI1.
|
||||
* @param flag: only QSPI_CMDSTS_FLAG valid.
|
||||
* @retval the new state of the flag (SET or RESET).
|
||||
*/
|
||||
flag_status qspi_interrupt_flag_get(qspi_type* qspi_x, uint32_t flag)
|
||||
{
|
||||
if(QSPI_CMDSTS_FLAG != flag)
|
||||
return RESET;
|
||||
if(qspi_x->cmdsts_bit.cmdsts && qspi_x->ctrl2_bit.cmdie)
|
||||
return SET;
|
||||
else
|
||||
return RESET;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief clear flags
|
||||
* @param qspi_x: select the qspi peripheral.
|
||||
@ -163,7 +196,7 @@ flag_status qspi_flag_get(qspi_type* qspi_x, uint32_t flag)
|
||||
* - QSPI_CMDSTS_FLAG
|
||||
* @retval none
|
||||
*/
|
||||
void qspi_flag_clear( qspi_type* qspi_x, uint32_t flag)
|
||||
void qspi_flag_clear(qspi_type* qspi_x, uint32_t flag)
|
||||
{
|
||||
qspi_x->cmdsts = QSPI_CMDSTS_FLAG;
|
||||
}
|
||||
@ -178,7 +211,7 @@ void qspi_flag_clear( qspi_type* qspi_x, uint32_t flag)
|
||||
* this parameter can be one of the following values:
|
||||
* - QSPI_DMA_FIFO_THOD_WORD08
|
||||
* - QSPI_DMA_FIFO_THOD_WORD16
|
||||
* - QSPI_DMA_FIFO_THOD_WORD32
|
||||
* - QSPI_DMA_FIFO_THOD_WORD24
|
||||
* @retval none
|
||||
*/
|
||||
void qspi_dma_rx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_threshold)
|
||||
@ -196,7 +229,7 @@ void qspi_dma_rx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_th
|
||||
* this parameter can be one of the following values:
|
||||
* - QSPI_DMA_FIFO_THOD_WORD08
|
||||
* - QSPI_DMA_FIFO_THOD_WORD16
|
||||
* - QSPI_DMA_FIFO_THOD_WORD32
|
||||
* - QSPI_DMA_FIFO_THOD_WORD24
|
||||
* @retval none
|
||||
*/
|
||||
void qspi_dma_tx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_threshold)
|
||||
@ -267,6 +300,7 @@ void qspi_xip_enable(qspi_type* qspi_x, confirm_state new_state)
|
||||
{
|
||||
__NOP();
|
||||
}
|
||||
|
||||
/* flush and reset qspi state */
|
||||
qspi_x->ctrl_bit.xiprcmdf = 1;
|
||||
|
||||
@ -425,6 +459,16 @@ void qspi_word_write(qspi_type* qspi_x, uint32_t value)
|
||||
qspi_x->dt = value;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief enable auto input sampling phase correction
|
||||
* @param qspi_x: select the qspi peripheral.
|
||||
* @retval none.
|
||||
*/
|
||||
void qspi_auto_ispc_enable(qspi_type* qspi_x)
|
||||
{
|
||||
qspi_x->ctrl3_bit.ispc = TRUE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@ -55,8 +55,6 @@ void scfg_reset(void)
|
||||
* @param source
|
||||
* this parameter can be one of the following values:
|
||||
* - SCFG_IR_SOURCE_TMR10
|
||||
* - SCFG_IR_SOURCE_USART1
|
||||
* - SCFG_IR_SOURCE_USART2
|
||||
* @param polarity
|
||||
* this parameter can be one of the following values:
|
||||
* - SCFG_IR_POLARITY_NO_AFFECTE
|
||||
@ -116,18 +114,11 @@ void scfg_pvm_lock_enable(confirm_state new_state)
|
||||
/**
|
||||
* @brief scfg sram odd parity error status get
|
||||
* @param none
|
||||
* @retval return sram odd parity error status (ERROR or SUCCESS)
|
||||
* @retval return sram odd parity error status(SET or RESET)
|
||||
*/
|
||||
error_status scfg_sram_operr_status_get(void)
|
||||
flag_status scfg_sram_operr_status_get(void)
|
||||
{
|
||||
error_status status = SUCCESS;
|
||||
|
||||
if(SCFG->cfg2_bit.sram_operr_sts)
|
||||
status = ERROR;
|
||||
else
|
||||
status = SUCCESS;
|
||||
|
||||
return status ;
|
||||
return (flag_status)SCFG->cfg2_bit.sram_operr_sts;
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
@ -674,6 +674,76 @@ flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag)
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief get interrupt flag of the specified spi/i2s peripheral.
|
||||
* @param spi_x: select the spi/i2s peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* SPI1, SPI2, SPI3, I2SF5
|
||||
* @param spi_i2s_flag: select the spi/i2s flag
|
||||
* this parameter can be one of the following values:
|
||||
* - SPI_I2S_RDBF_FLAG
|
||||
* - SPI_I2S_TDBE_FLAG
|
||||
* - I2S_TUERR_FLAG (this flag only use in i2s mode)
|
||||
* - SPI_CCERR_FLAG (this flag only use in spi mode)
|
||||
* - SPI_MMERR_FLAG (this flag only use in spi mode)
|
||||
* - SPI_I2S_ROERR_FLAG
|
||||
* - SPI_I2S_CSPAS_FLAG
|
||||
* @retval the new state of spi/i2s flag
|
||||
*/
|
||||
flag_status spi_i2s_interrupt_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag)
|
||||
{
|
||||
flag_status status = RESET;
|
||||
|
||||
switch(spi_i2s_flag)
|
||||
{
|
||||
case SPI_I2S_RDBF_FLAG:
|
||||
if(spi_x->sts_bit.rdbf && spi_x->ctrl2_bit.rdbfie)
|
||||
{
|
||||
status = SET;
|
||||
}
|
||||
break;
|
||||
case SPI_I2S_TDBE_FLAG:
|
||||
if(spi_x->sts_bit.tdbe && spi_x->ctrl2_bit.tdbeie)
|
||||
{
|
||||
status = SET;
|
||||
}
|
||||
break;
|
||||
case I2S_TUERR_FLAG:
|
||||
if(spi_x->sts_bit.tuerr && spi_x->ctrl2_bit.errie)
|
||||
{
|
||||
status = SET;
|
||||
}
|
||||
break;
|
||||
case SPI_CCERR_FLAG:
|
||||
if(spi_x->sts_bit.ccerr && spi_x->ctrl2_bit.errie)
|
||||
{
|
||||
status = SET;
|
||||
}
|
||||
break;
|
||||
case SPI_MMERR_FLAG:
|
||||
if(spi_x->sts_bit.mmerr && spi_x->ctrl2_bit.errie)
|
||||
{
|
||||
status = SET;
|
||||
}
|
||||
break;
|
||||
case SPI_I2S_ROERR_FLAG:
|
||||
if(spi_x->sts_bit.roerr && spi_x->ctrl2_bit.errie)
|
||||
{
|
||||
status = SET;
|
||||
}
|
||||
break;
|
||||
case SPI_I2S_CSPAS_FLAG:
|
||||
if(spi_x->sts_bit.cspas && spi_x->ctrl2_bit.errie)
|
||||
{
|
||||
status = SET;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
};
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief clear flag of the specified spi/i2s peripheral.
|
||||
* @param spi_x: select the spi/i2s peripheral.
|
||||
|
||||
@ -160,7 +160,6 @@ void tmr_input_default_para_init(tmr_input_config_type *tmr_input_struct)
|
||||
*/
|
||||
void tmr_brkdt_default_para_init(tmr_brkdt_config_type *tmr_brkdt_struct)
|
||||
{
|
||||
tmr_brkdt_struct->brk_filter_value = 0x0;
|
||||
tmr_brkdt_struct->deadtime = 0x0;
|
||||
tmr_brkdt_struct->brk_polarity = TMR_BRK_INPUT_ACTIVE_LOW;
|
||||
tmr_brkdt_struct->wp_level = TMR_WP_OFF;
|
||||
@ -1346,6 +1345,40 @@ void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief get tmr interrupt flag
|
||||
* @param tmr_x: select the tmr peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* TMR1, TMR2, TMR3, TMR4, TMR6, TMR7, TMR9, TMR10,
|
||||
* TMR11, TMR13, TMR14
|
||||
* @param tmr_flag
|
||||
* this parameter can be one of the following values:
|
||||
* - TMR_OVF_FLAG
|
||||
* - TMR_C1_FLAG
|
||||
* - TMR_C2_FLAG
|
||||
* - TMR_C3_FLAG
|
||||
* - TMR_C4_FLAG
|
||||
* - TMR_HALL_FLAG
|
||||
* - TMR_TRIGGER_FLAG
|
||||
* - TMR_BRK_FLAG
|
||||
* @retval state of tmr interrupt flag
|
||||
*/
|
||||
flag_status tmr_interrupt_flag_get(tmr_type *tmr_x, uint32_t tmr_flag)
|
||||
{
|
||||
flag_status status = RESET;
|
||||
|
||||
if((tmr_x->ists & tmr_flag) && (tmr_x->iden & tmr_flag))
|
||||
{
|
||||
status = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
status = RESET;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief get tmr flag
|
||||
* @param tmr_x: select the tmr peripheral.
|
||||
@ -1766,7 +1799,6 @@ void tmr_dma_control_config(tmr_type *tmr_x, tmr_dma_transfer_length_type dma_le
|
||||
*/
|
||||
void tmr_brkdt_config(tmr_type *tmr_x, tmr_brkdt_config_type *brkdt_struct)
|
||||
{
|
||||
tmr_x->brk_bit.bkf = brkdt_struct->brk_filter_value;
|
||||
tmr_x->brk_bit.brken = brkdt_struct->brk_enable;
|
||||
tmr_x->brk_bit.dtc = brkdt_struct->deadtime;
|
||||
tmr_x->brk_bit.fcsodis = brkdt_struct->fcsodis_state;
|
||||
@ -1776,6 +1808,19 @@ void tmr_brkdt_config(tmr_type *tmr_x, tmr_brkdt_config_type *brkdt_struct)
|
||||
tmr_x->brk_bit.wpc = brkdt_struct->wp_level;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief set tmr break input filter value
|
||||
* @param tmr_x: select the tmr peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* TMR1, TMR9, TMR10, TMR11, TMR13, TRM14
|
||||
* @param filter_value (0x0~0xf)
|
||||
* @retval none
|
||||
*/
|
||||
void tmr_brk_filter_value_set(tmr_type *tmr_x, uint8_t filter_value)
|
||||
{
|
||||
tmr_x->brk_bit.bkf = filter_value;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief set tmr2 and tmr14 input channel remap
|
||||
* @param tmr_x: select the tmr peripheral.
|
||||
|
||||
@ -607,6 +607,88 @@ flag_status usart_flag_get(usart_type* usart_x, uint32_t flag)
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief check whether the specified usart interrupt flag is set or not.
|
||||
* @param usart_x: select the usart or the uart peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* USART1, USART2, USART3, USART4, USART5, USART6, UART7 or UART8.
|
||||
* @param flag: specifies the flag to check.
|
||||
* this parameter can be one of the following values:
|
||||
* - USART_RTODF_FLAG: receiver time out detection flag
|
||||
* - USART_CMDF_FLAG: character match detection flag
|
||||
* - USART_CTSCF_FLAG: cts change flag
|
||||
* - USART_BFF_FLAG: break frame flag
|
||||
* - USART_TDBE_FLAG: transmit data buffer empty flag
|
||||
* - USART_TDC_FLAG: transmit data complete flag
|
||||
* - USART_RDBF_FLAG: receive data buffer full flag
|
||||
* - USART_IDLEF_FLAG: idle flag
|
||||
* - USART_ROERR_FLAG: receiver overflow error flag
|
||||
* - USART_NERR_FLAG: noise error flag
|
||||
* - USART_FERR_FLAG: framing error flag
|
||||
* - USART_PERR_FLAG: parity error flag
|
||||
* @retval the new state of usart_flag (SET or RESET).
|
||||
*/
|
||||
flag_status usart_interrupt_flag_get(usart_type* usart_x, uint32_t flag)
|
||||
{
|
||||
flag_status int_status = RESET;
|
||||
|
||||
switch(flag)
|
||||
{
|
||||
case USART_CTSCF_FLAG:
|
||||
int_status = (flag_status)usart_x->ctrl3_bit.ctscfien;
|
||||
break;
|
||||
case USART_BFF_FLAG:
|
||||
int_status = (flag_status)usart_x->ctrl2_bit.bfien;
|
||||
break;
|
||||
case USART_TDBE_FLAG:
|
||||
int_status = (flag_status)usart_x->ctrl1_bit.tdbeien;
|
||||
break;
|
||||
case USART_TDC_FLAG:
|
||||
int_status = (flag_status)usart_x->ctrl1_bit.tdcien;
|
||||
break;
|
||||
case USART_RDBF_FLAG:
|
||||
int_status = (flag_status)usart_x->ctrl1_bit.rdbfien;
|
||||
break;
|
||||
case USART_ROERR_FLAG:
|
||||
int_status = (flag_status)(usart_x->ctrl1_bit.rdbfien || usart_x->ctrl3_bit.errien);
|
||||
break;
|
||||
case USART_IDLEF_FLAG:
|
||||
int_status = (flag_status)usart_x->ctrl1_bit.idleien;
|
||||
break;
|
||||
case USART_NERR_FLAG:
|
||||
case USART_FERR_FLAG:
|
||||
int_status = (flag_status)usart_x->ctrl3_bit.errien;
|
||||
break;
|
||||
case USART_PERR_FLAG:
|
||||
int_status = (flag_status)usart_x->ctrl1_bit.perrien;
|
||||
break;
|
||||
case USART_RTODF_FLAG:
|
||||
int_status = (flag_status)usart_x->ctrl1_bit.retodie;
|
||||
break;
|
||||
case USART_CMDF_FLAG:
|
||||
int_status = (flag_status)usart_x->ctrl1_bit.cmdie;
|
||||
break;
|
||||
default:
|
||||
int_status = RESET;
|
||||
break;
|
||||
}
|
||||
|
||||
if(int_status != SET)
|
||||
{
|
||||
return RESET;
|
||||
}
|
||||
|
||||
if(usart_x->sts & flag)
|
||||
{
|
||||
return SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
return RESET;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief clear the usart's pending flags.
|
||||
* @param usart_x: select the usart or the uart peripheral.
|
||||
@ -700,17 +782,17 @@ void usart_id_bit_num_set(usart_type* usart_x, usart_identification_bit_num_type
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief enable or disable the usart's de polarity reverse.
|
||||
* @brief set the usart's de polarity.
|
||||
* @param usart_x: select the usart or the uart peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* USART1, USART2, USART3
|
||||
* @param new_state: new state of the irda mode.
|
||||
* this parameter can be: TRUE or FALSE.
|
||||
* @param de_polarity: the usart de polarity selection.
|
||||
* this parameter can be: USART_DE_POLARITY_HIGH or USART_DE_POLARITY_LOW.
|
||||
* @retval none
|
||||
*/
|
||||
void usart_de_polarity_reverse(usart_type* usart_x, confirm_state new_state)
|
||||
void usart_de_polarity_set(usart_type* usart_x, usart_de_polarity_type de_polarity)
|
||||
{
|
||||
usart_x->ctrl3_bit.dep = new_state;
|
||||
usart_x->ctrl3_bit.dep = (uint8_t)de_polarity;
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
@ -1063,7 +1063,6 @@ void usb_hch_halt(otg_global_type *usbx, uint8_t chn)
|
||||
{
|
||||
usb_chh->hcchar_bit.chena = TRUE;
|
||||
}
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
|
||||
@ -104,6 +104,16 @@ flag_status wwdt_flag_get(void)
|
||||
return (flag_status)WWDT->sts_bit.rldf;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief wwdt reload counter interrupt flag get
|
||||
* @param none
|
||||
* @retval state of reload counter interrupt flag
|
||||
*/
|
||||
flag_status wwdt_interrupt_flag_get(void)
|
||||
{
|
||||
return (flag_status)(WWDT->sts_bit.rldf && WWDT->cfg_bit.rldien);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief wwdt counter value set
|
||||
* @param wwdt_cnt (0x40~0x7f)
|
||||
|
||||
@ -1,8 +1,6 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file system_at32f403a_407.c
|
||||
* @version v2.0.9
|
||||
* @date 2022-04-25
|
||||
* @brief contains all the functions for cmsis cortex-m4 system source file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
@ -81,13 +79,13 @@ void SystemInit (void)
|
||||
/* wait sclk switch status */
|
||||
while(CRM->cfg_bit.sclksts != CRM_SCLK_HICK);
|
||||
|
||||
/* reset hexten, hextbyps, cfden and pllen bits */
|
||||
CRM->ctrl &= ~(0x010D0000U);
|
||||
|
||||
/* reset cfg register, include sclk switch, ahbdiv, apb1div, apb2div, adcdiv,
|
||||
clkout pllrcs, pllhextdiv, pllmult, usbdiv and pllrange bits */
|
||||
CRM->cfg = 0;
|
||||
|
||||
/* reset hexten, hextbyps, cfden and pllen bits */
|
||||
CRM->ctrl &= ~(0x010D0000U);
|
||||
|
||||
/* reset clkout[3], usbbufs, hickdiv, clkoutdiv */
|
||||
CRM->misc1 = 0;
|
||||
|
||||
|
||||
@ -1,8 +1,6 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file system_at32f403a_407.h
|
||||
* @version v2.0.9
|
||||
* @date 2022-04-25
|
||||
* @brief cmsis cortex-m4 system header file.
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
@ -45,6 +43,11 @@ extern "C" {
|
||||
|
||||
#define HEXT_STABLE_DELAY (5000u)
|
||||
#define PLL_STABLE_DELAY (500u)
|
||||
#define SystemCoreClock system_core_clock
|
||||
#define DUMMY_NOP() {__NOP();__NOP();__NOP();__NOP();__NOP(); \
|
||||
__NOP();__NOP();__NOP();__NOP();__NOP(); \
|
||||
__NOP();__NOP();__NOP();__NOP();__NOP(); \
|
||||
__NOP();__NOP();__NOP();__NOP();__NOP();}
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
||||
@ -1,8 +1,6 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f403a_407_acc.h
|
||||
* @version v2.0.9
|
||||
* @date 2022-04-25
|
||||
* @brief at32f403a_407 acc header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
@ -181,6 +179,7 @@ uint16_t acc_read_c1(void);
|
||||
uint16_t acc_read_c2(void);
|
||||
uint16_t acc_read_c3(void);
|
||||
flag_status acc_flag_get(uint16_t acc_flag);
|
||||
flag_status acc_interrupt_flag_get(uint16_t acc_flag);
|
||||
void acc_flag_clear(uint16_t acc_flag);
|
||||
|
||||
/**
|
||||
|
||||
@ -1,8 +1,6 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f403a_407_adc.h
|
||||
* @version v2.0.9
|
||||
* @date 2022-04-25
|
||||
* @brief at32f403a_407 adc header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
@ -621,6 +619,7 @@ uint16_t adc_ordinary_conversion_data_get(adc_type *adc_x);
|
||||
uint32_t adc_combine_ordinary_conversion_data_get(void);
|
||||
uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel);
|
||||
flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag);
|
||||
flag_status adc_interrupt_flag_get(adc_type *adc_x, uint8_t adc_flag);
|
||||
void adc_flag_clear(adc_type *adc_x, uint32_t adc_flag);
|
||||
|
||||
/**
|
||||
|
||||
@ -1,8 +1,6 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f403a_407_bpr.h
|
||||
* @version v2.0.9
|
||||
* @date 2022-04-25
|
||||
* @brief at32f403a_407 bpr header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
@ -761,6 +759,7 @@ typedef struct
|
||||
|
||||
void bpr_reset(void);
|
||||
flag_status bpr_flag_get(uint32_t flag);
|
||||
flag_status bpr_interrupt_flag_get(uint32_t flag);
|
||||
void bpr_flag_clear(uint32_t flag);
|
||||
void bpr_interrupt_enable(confirm_state new_state);
|
||||
uint16_t bpr_data_read(bpr_data_type bpr_data);
|
||||
|
||||
@ -1,8 +1,6 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f403a_407_can.h
|
||||
* @version v2.0.9
|
||||
* @date 2022-04-25
|
||||
* @brief at32f403a_407 can header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
@ -352,7 +350,7 @@ typedef struct
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t baudrate_div; /*!< baudrate division,this parameter can be 0x001~0x400.*/
|
||||
uint16_t baudrate_div; /*!< baudrate division,this parameter can be 0x001~0x1000.*/
|
||||
|
||||
can_rsaw_type rsaw_size; /*!< resynchronization adjust width */
|
||||
|
||||
@ -964,6 +962,7 @@ can_error_record_type can_error_type_record_get(can_type* can_x);
|
||||
uint8_t can_receive_error_counter_get(can_type* can_x);
|
||||
uint8_t can_transmit_error_counter_get(can_type* can_x);
|
||||
void can_interrupt_enable(can_type* can_x, uint32_t can_int, confirm_state new_state);
|
||||
flag_status can_interrupt_flag_get(can_type* can_x, uint32_t can_flag);
|
||||
flag_status can_flag_get(can_type* can_x, uint32_t can_flag);
|
||||
void can_flag_clear(can_type* can_x, uint32_t can_flag);
|
||||
|
||||
|
||||
@ -1,8 +1,6 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f403a_407_crc.h
|
||||
* @version v2.0.9
|
||||
* @date 2022-04-25
|
||||
* @brief at32f403a_407 crc header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
@ -68,6 +66,17 @@ typedef enum
|
||||
CRC_REVERSE_OUTPUT_DATA = 0x01 /*!< output data reverse by word */
|
||||
} crc_reverse_output_type;
|
||||
|
||||
/**
|
||||
* @brief crc polynomial size
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CRC_POLY_SIZE_32B = 0x00, /*!< polynomial size 32 bits */
|
||||
CRC_POLY_SIZE_16B = 0x01, /*!< polynomial size 16 bits */
|
||||
CRC_POLY_SIZE_8B = 0x02, /*!< polynomial size 8 bits */
|
||||
CRC_POLY_SIZE_7B = 0x03 /*!< polynomial size 7 bits */
|
||||
} crc_poly_size_type;
|
||||
|
||||
/**
|
||||
* @brief type define crc register all
|
||||
*/
|
||||
@ -107,7 +116,8 @@ typedef struct
|
||||
struct
|
||||
{
|
||||
__IO uint32_t rst : 1 ; /* [0] */
|
||||
__IO uint32_t reserved1 : 4 ; /* [4:1] */
|
||||
__IO uint32_t reserved1 : 2 ; /* [2:1] */
|
||||
__IO uint32_t poly_size : 2 ; /* [4:3] */
|
||||
__IO uint32_t revid : 2 ; /* [6:5] */
|
||||
__IO uint32_t revod : 1 ; /* [7] */
|
||||
__IO uint32_t reserved2 : 24 ;/* [31:8] */
|
||||
@ -131,6 +141,18 @@ typedef struct
|
||||
} idt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief crc polynomial register, offset:0x14
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t poly;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t poly : 32; /* [31:0] */
|
||||
} poly_bit;
|
||||
};
|
||||
|
||||
} crc_type;
|
||||
|
||||
/**
|
||||
@ -148,10 +170,14 @@ uint32_t crc_one_word_calculate(uint32_t data);
|
||||
uint32_t crc_block_calculate(uint32_t *pbuffer, uint32_t length);
|
||||
uint32_t crc_data_get(void);
|
||||
void crc_common_data_set(uint8_t cdt_value);
|
||||
uint8_t crc_common_date_get(void);
|
||||
uint8_t crc_common_data_get(void);
|
||||
void crc_init_data_set(uint32_t value);
|
||||
void crc_reverse_input_data_set(crc_reverse_input_type value);
|
||||
void crc_reverse_output_data_set(crc_reverse_output_type value);
|
||||
void crc_poly_value_set(uint32_t value);
|
||||
uint32_t crc_poly_value_get(void);
|
||||
void crc_poly_size_set(crc_poly_size_type size);
|
||||
crc_poly_size_type crc_poly_size_get(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
||||
@ -1,8 +1,6 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f403a_407_crm.h
|
||||
* @version v2.0.9
|
||||
* @date 2022-04-25
|
||||
* @brief at32f403a_407 crm header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
@ -1088,6 +1086,7 @@ void crm_reset(void);
|
||||
void crm_lext_bypass(confirm_state new_state);
|
||||
void crm_hext_bypass(confirm_state new_state);
|
||||
flag_status crm_flag_get(uint32_t flag);
|
||||
flag_status crm_interrupt_flag_get(uint32_t flag);
|
||||
error_status crm_hext_stable_wait(void);
|
||||
void crm_hick_clock_trimming_set(uint8_t trim_value);
|
||||
void crm_hick_clock_calibration_set(uint8_t cali_value);
|
||||
|
||||
@ -1,8 +1,6 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f403a_407_dac.h
|
||||
* @version v2.0.9
|
||||
* @date 2022-04-25
|
||||
* @brief at32f403a_407 dac header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
|
||||
@ -1,8 +1,6 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f403a_407_debug.h
|
||||
* @version v2.0.9
|
||||
* @date 2022-04-25
|
||||
* @brief at32f403a_407 debug header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
|
||||
@ -1,8 +1,6 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f403a_407_def.h
|
||||
* @version v2.0.9
|
||||
* @date 2022-04-25
|
||||
* @brief at32f403a_407 macros header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
@ -62,6 +60,8 @@ extern "C" {
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define UNUSED(x) (void)x /* to avoid gcc/g++ warnings */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -1,8 +1,6 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f403a_407_dma.h
|
||||
* @version v2.0.9
|
||||
* @date 2022-04-25
|
||||
* @brief at32f403a_407 dma header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
@ -527,6 +525,7 @@ void dma_interrupt_enable(dma_channel_type* dmax_channely, uint32_t dma_int, con
|
||||
void dma_channel_enable(dma_channel_type* dmax_channely, confirm_state new_state);
|
||||
void dma_flexible_config(dma_type* dma_x, uint8_t flex_channelx, dma_flexible_request_type flexible_request);
|
||||
flag_status dma_flag_get(uint32_t dmax_flag);
|
||||
flag_status dma_interrupt_flag_get(uint32_t dmax_flag);
|
||||
void dma_flag_clear(uint32_t dmax_flag);
|
||||
void dma_default_para_init(dma_init_type* dma_init_struct);
|
||||
void dma_init(dma_channel_type* dmax_channely, dma_init_type* dma_init_struct);
|
||||
|
||||
@ -1,8 +1,6 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f403a_407_emac.h
|
||||
* @version v2.0.9
|
||||
* @date 2022-04-25
|
||||
* @brief at32f403a_407 emac header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
@ -46,6 +44,7 @@ extern "C" {
|
||||
*/
|
||||
|
||||
#define PHY_TIMEOUT (0x000FFFFF) /*!< timeout for phy response */
|
||||
#define EMAC_USE_ENHANCED_DMA_DESCRIPTOR
|
||||
|
||||
/** @defgroup EMAC_smi_clock_border_definition
|
||||
* @brief emac smi clock border
|
||||
@ -99,7 +98,7 @@ extern "C" {
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define EMAC_MAX_PACKET_LENGTH 1520 /*!< emac_header + emac_extra + emac_max_payload + emac_crc */
|
||||
#define EMAC_MAX_PACKET_LENGTH 1524 /*!< emac_header + emac_extra + emac_max_payload + emac_crc */
|
||||
#define EMAC_HEADER 14 /*!< 6 byte dest addr, 6 byte src addr, 2 byte length/ept_type */
|
||||
#define EMAC_CRC 4 /*!< ethernet crc */
|
||||
#define EMAC_EXTRA 2 /*!< extra bytes in some cases */
|
||||
@ -271,6 +270,15 @@ extern "C" {
|
||||
#define EMAC_DMA_AIS_FLAG ((uint32_t)0x00008000) /*!< emac dma abnormal interrupt summary */
|
||||
#define EMAC_DMA_NIS_FLAG ((uint32_t)0x00010000) /*!< emac dma normal interrupt summary */
|
||||
|
||||
/**
|
||||
* @brief emac ptp time sign
|
||||
*/
|
||||
#define EMAC_PTP_POSITIVETIME ((uint32_t)0x00000000) /*!< Positive time value */
|
||||
#define EMAC_PTP_NEGATIVETIME ((uint32_t)0x80000000) /*!< Negative time value */
|
||||
|
||||
#define EMAC_PTP_TI_FLAG ((uint32_t)0x00000004) /*!< Time Stamp Initialized */
|
||||
#define EMAC_PTP_TU_FLAG ((uint32_t)0x00000008) /*!< Time Stamp Updated */
|
||||
#define EMAC_PTP_ARU_FLAG ((uint32_t)0x00000020) /*!< Addend Register Updated */
|
||||
/** @defgroup EMAC_exported_types
|
||||
* @{
|
||||
*/
|
||||
@ -345,9 +353,10 @@ typedef enum
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
EMAC_CONTROL_FRAME_PASSING_NO = 0x00, /*!< don't pass any control frame to application */
|
||||
EMAC_CONTROL_FRAME_PASSING_ALL = 0x02, /*!< pass all control frames to application */
|
||||
EMAC_CONTROL_FRAME_PASSING_MATCH = 0x03 /*!< only pass filtered control frames to application */
|
||||
EMAC_CONTROL_FRAME_PASSING_NO = 0x00, /*!< don't pass any control frame to application */
|
||||
EMAC_CONTROL_FRAME_PASSING_ALL_EXCEPT_PAUSE = 0x01, /*!< pass all control frames to application except pause frame */
|
||||
EMAC_CONTROL_FRAME_PASSING_ALL = 0x02, /*!< pass all control frames to application */
|
||||
EMAC_CONTROL_FRAME_PASSING_MATCH = 0x03 /*!< only pass filtered control frames to application */
|
||||
} emac_control_frames_filter_type;
|
||||
|
||||
/**
|
||||
@ -633,6 +642,10 @@ typedef struct {
|
||||
uint32_t controlsize; /*!< control and buffer1, buffer2 lengths */
|
||||
uint32_t buf1addr; /*!< buffer1 address pointer */
|
||||
uint32_t buf2nextdescaddr; /*!< buffer2 or next descriptor address pointer */
|
||||
uint32_t extendedstatus;
|
||||
uint32_t reserved1;
|
||||
uint32_t timestamp_l;
|
||||
uint32_t timestamp_h;
|
||||
} emac_dma_desc_type;
|
||||
|
||||
/**
|
||||
@ -891,7 +904,7 @@ typedef struct
|
||||
__IO uint32_t reserved1 : 8; /* [16:23] */
|
||||
__IO uint32_t mbc : 6; /* [24:29] */
|
||||
__IO uint32_t sa : 1; /* [30] */
|
||||
__IO uint32_t ae : 1; /* [31] */
|
||||
__IO uint32_t ae : 1; /* [31] */
|
||||
} a1h_bit;
|
||||
};
|
||||
|
||||
@ -1328,7 +1341,7 @@ typedef struct
|
||||
__IO uint32_t swr : 1; /* [0] */
|
||||
__IO uint32_t da : 1; /* [1] */
|
||||
__IO uint32_t dsl : 5; /* [2:6] */
|
||||
__IO uint32_t reserved1 : 1; /* [7] */
|
||||
__IO uint32_t atds : 1; /* [7] */
|
||||
__IO uint32_t pbl : 6; /* [8:13] */
|
||||
__IO uint32_t pr : 2; /* [14:15] */
|
||||
__IO uint32_t fb : 1; /* [16] */
|
||||
@ -1336,7 +1349,7 @@ typedef struct
|
||||
__IO uint32_t usp : 1; /* [23] */
|
||||
__IO uint32_t pblx8 : 1; /* [24] */
|
||||
__IO uint32_t aab : 1; /* [25] */
|
||||
__IO uint32_t reserved2 : 6; /* [26:31] */
|
||||
__IO uint32_t reserved : 6; /* [26:31] */
|
||||
} bm_bit;
|
||||
};
|
||||
|
||||
@ -1628,6 +1641,7 @@ void emac_address_filter_set(emac_address_type mac, emac_address_filter_type fil
|
||||
uint32_t emac_received_packet_size_get(void);
|
||||
uint32_t emac_dmarxdesc_frame_length_get(emac_dma_desc_type *dma_rx_desc);
|
||||
void emac_dma_descriptor_list_address_set(emac_dma_tx_rx_type transfer_type, emac_dma_desc_type *dma_desc_tab, uint8_t *buff, uint32_t buffer_count);
|
||||
void emac_ptp_dma_descriptor_list_address_set(emac_dma_tx_rx_type transfer_type, emac_dma_desc_type *dma_desc_tab, emac_dma_desc_type *ptp_dma_desc_tab, uint8_t *buff, uint32_t buffer_count);
|
||||
uint32_t emac_dma_descriptor_list_address_get(emac_dma_tx_rx_type transfer_type);
|
||||
void emac_dma_rx_desc_interrupt_config(emac_dma_desc_type *dma_rx_desc, confirm_state new_state);
|
||||
void emac_dma_para_init(emac_dma_config_type *control_para);
|
||||
@ -1650,6 +1664,7 @@ uint8_t emac_dma_missing_overflow_bit_get(void);
|
||||
uint16_t emac_dma_application_missing_frame_get(void);
|
||||
uint8_t emac_dma_fifo_overflow_bit_get(void);
|
||||
uint32_t emac_dma_tansfer_address_get(emac_dma_transfer_address_type transfer_type);
|
||||
void emac_dma_alternate_desc_size(confirm_state new_state);
|
||||
void emac_mmc_counter_reset(void);
|
||||
void emac_mmc_rollover_stop(confirm_state new_state);
|
||||
void emac_mmc_reset_on_read_enable(confirm_state new_state);
|
||||
@ -1676,19 +1691,19 @@ void emac_ptp_snapshot_event_message_enable(confirm_state new_state);
|
||||
void emac_ptp_snapshot_master_event_enable(confirm_state new_state);
|
||||
void emac_ptp_clock_node_set(emac_ptp_clock_node_type node);
|
||||
void emac_ptp_mac_address_filter_enable(confirm_state new_state);
|
||||
flag_status emac_ptp_flag_get(uint32_t flag);
|
||||
void emac_ptp_subsecond_increment_set(uint8_t value);
|
||||
uint32_t emac_ptp_system_second_get(void);
|
||||
uint32_t emac_ptp_system_subsecond_get(void);
|
||||
confirm_state emac_ptp_system_time_sign_get(void);
|
||||
void emac_ptp_system_second_set(uint32_t second);
|
||||
void emac_ptp_system_subsecond_set(uint32_t subsecond);
|
||||
void emac_ptp_system_time_sign_set(confirm_state sign);
|
||||
void emac_ptp_system_time_set(uint32_t sign, uint32_t second, uint32_t subsecond);
|
||||
void emac_ptp_timestamp_addend_set(uint32_t value);
|
||||
void emac_ptp_target_second_set(uint32_t value);
|
||||
void emac_ptp_target_nanosecond_set(uint32_t value);
|
||||
confirm_state emac_ptp_timestamp_status_get(emac_ptp_timestamp_status_type status);
|
||||
void emac_ptp_pps_frequency_set(emac_ptp_pps_control_type freq);
|
||||
flag_status emac_dma_flag_get(uint32_t dma_flag);
|
||||
flag_status emac_dma_interrupt_flag_get(uint32_t dma_flag);
|
||||
void emac_dma_flag_clear(uint32_t dma_flag);
|
||||
|
||||
/**
|
||||
|
||||
@ -1,8 +1,6 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f403a_407_exint.h
|
||||
* @version v2.0.9
|
||||
* @date 2022-04-25
|
||||
* @brief at32f403a_407 exint header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
@ -208,6 +206,7 @@ void exint_default_para_init(exint_init_type *exint_struct);
|
||||
void exint_init(exint_init_type *exint_struct);
|
||||
void exint_flag_clear(uint32_t exint_line);
|
||||
flag_status exint_flag_get(uint32_t exint_line);
|
||||
flag_status exint_interrupt_flag_get(uint32_t exint_line);
|
||||
void exint_software_interrupt_event_generate(uint32_t exint_line);
|
||||
void exint_interrupt_enable(uint32_t exint_line, confirm_state new_state);
|
||||
void exint_event_enable(uint32_t exint_line, confirm_state new_state);
|
||||
|
||||
@ -1,8 +1,6 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f403a_407_flash.h
|
||||
* @version v2.0.9
|
||||
* @date 2022-04-25
|
||||
* @brief at32f403a_407 flash header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
@ -190,7 +188,7 @@ typedef enum
|
||||
typedef enum
|
||||
{
|
||||
FLASH_SPIM_MODEL1 = 0x01, /*!< spim model 1 */
|
||||
FLASH_SPIM_MODEL2 = 0x02, /*!< spim model 2 */
|
||||
FLASH_SPIM_MODEL2 = 0x02 /*!< spim model 2 */
|
||||
} flash_spim_model_type;
|
||||
|
||||
/**
|
||||
@ -700,12 +698,14 @@ uint8_t flash_ssb_status_get(void);
|
||||
void flash_interrupt_enable(uint32_t flash_int, confirm_state new_state);
|
||||
void flash_spim_model_select(flash_spim_model_type mode);
|
||||
void flash_spim_encryption_range_set(uint32_t decode_address);
|
||||
void flash_spim_dummy_read(void);
|
||||
flash_status_type flash_spim_mass_program(uint32_t address, uint8_t *buf, uint32_t cnt);
|
||||
flash_status_type flash_slib_enable(uint32_t pwd, uint16_t start_sector, uint16_t data_start_sector, uint16_t end_sector);
|
||||
error_status flash_slib_disable(uint32_t pwd);
|
||||
uint32_t flash_slib_remaining_count_get(void);
|
||||
flag_status flash_slib_state_get(void);
|
||||
uint16_t flash_slib_start_sector_get(void);
|
||||
uint16_t flash_slib_datstart_sector_get(void);
|
||||
uint16_t flash_slib_datastart_sector_get(void);
|
||||
uint16_t flash_slib_end_sector_get(void);
|
||||
uint32_t flash_crc_calibrate(uint32_t start_sector, uint32_t sector_cnt);
|
||||
|
||||
|
||||
@ -1,8 +1,6 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f403a_407_gpio.h
|
||||
* @version v2.0.9
|
||||
* @date 2022-04-25
|
||||
* @brief at32f403a_407 gpio header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
@ -215,8 +213,8 @@ extern "C" {
|
||||
#define SPI3_GMUX_0010 IOMUX_MAKE_VALUE(0x28, 24, 4, 0x02) /*!< spi3_cs/i2s3_ws(pa15), spi3_sck/i2s3_ck(pb3), spi3_miso(pb4), spi3_mosi/i2s3_sd(pb5), i2s3_mck(pb10) */
|
||||
#define SPI3_GMUX_0011 IOMUX_MAKE_VALUE(0x28, 24, 4, 0x03) /*!< spi3_cs/i2s3_ws(pa4), spi3_sck/i2s3_ck(pc10), spi3_miso(pc11), spi3_mosi/i2s3_sd(pc12), i2s3_mck(pb10) */
|
||||
#define SPI4_GMUX_0001 IOMUX_MAKE_VALUE(0x28, 28, 4, 0x01) /*!< spi4_cs/i2s4_ws(pe12), spi4_sck/i2s4_ck(pe11), spi4_miso(pe13), spi4_mosi/i2s4_sd(pe14), i2s4_mck(pc8) */
|
||||
#define SPI4_GMUX_0010 IOMUX_MAKE_VALUE(0x28, 28, 4, 0x02) /*!< spi4_cs/i2s4_ws(pb6), spi4_sck/i2s4_ck(pb7), spi4_miso(pb8), spi4_mosi/i2s4_sd(pb8), i2s4_mck(pc8) */
|
||||
#define SPI4_GMUX_0011 IOMUX_MAKE_VALUE(0x28, 28, 4, 0x03) /*!< spi4_cs/i2s4_ws(pb6), spi4_sck/i2s4_ck(pb7), spi4_miso(pb8), spi4_mosi/i2s4_sd(pb8), i2s4_mck(pa10) */
|
||||
#define SPI4_GMUX_0010 IOMUX_MAKE_VALUE(0x28, 28, 4, 0x02) /*!< spi4_cs/i2s4_ws(pb6), spi4_sck/i2s4_ck(pb7), spi4_miso(pb8), spi4_mosi/i2s4_sd(pb9), i2s4_mck(pc8) */
|
||||
#define SPI4_GMUX_0011 IOMUX_MAKE_VALUE(0x28, 28, 4, 0x03) /*!< spi4_cs/i2s4_ws(pb6), spi4_sck/i2s4_ck(pb7), spi4_miso(pb8), spi4_mosi/i2s4_sd(pb9), i2s4_mck(pa10) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
@ -914,7 +912,7 @@ uint16_t gpio_output_data_read(gpio_type *gpio_x);
|
||||
void gpio_bits_set(gpio_type *gpio_x, uint16_t pins);
|
||||
void gpio_bits_reset(gpio_type *gpio_x, uint16_t pins);
|
||||
void gpio_bits_write(gpio_type *gpio_x, uint16_t pins, confirm_state bit_state);
|
||||
void gpio_port_wirte(gpio_type *gpio_x, uint16_t port_value);
|
||||
void gpio_port_write(gpio_type *gpio_x, uint16_t port_value);
|
||||
void gpio_pin_wp_config(gpio_type *gpio_x, uint16_t pins);
|
||||
void gpio_pins_huge_driven_config(gpio_type *gpio_x, uint16_t pins, confirm_state new_state);
|
||||
void gpio_event_output_config(gpio_port_source_type gpio_port_source, gpio_pins_source_type gpio_pin_source);
|
||||
|
||||
@ -1,8 +1,6 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f403a_407_i2c.h
|
||||
* @version v2.0.9
|
||||
* @date 2022-04-25
|
||||
* @brief at32f403a_407 i2c header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
@ -381,6 +379,7 @@ void i2c_7bit_address_send(i2c_type *i2c_x, uint8_t address, i2c_direction_type
|
||||
void i2c_data_send(i2c_type *i2c_x, uint8_t data);
|
||||
uint8_t i2c_data_receive(i2c_type *i2c_x);
|
||||
flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag);
|
||||
flag_status i2c_interrupt_flag_get(i2c_type *i2c_x, uint32_t flag);
|
||||
void i2c_flag_clear(i2c_type *i2c_x, uint32_t flag);
|
||||
|
||||
/**
|
||||
|
||||
@ -1,8 +1,6 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f403a_407_misc.h
|
||||
* @version v2.0.9
|
||||
* @date 2022-04-25
|
||||
* @brief at32f403a_407 misc header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
@ -76,9 +74,9 @@ typedef enum
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NVIC_LP_SLEEPONEXIT = 0x02, /*!< send event on pending */
|
||||
NVIC_LP_SLEEPONEXIT = 0x02, /*!< enable sleep-on-exit feature */
|
||||
NVIC_LP_SLEEPDEEP = 0x04, /*!< enable sleep-deep output signal when entering sleep mode */
|
||||
NVIC_LP_SEVONPEND = 0x10 /*!< enable sleep-on-exit feature */
|
||||
NVIC_LP_SEVONPEND = 0x10 /*!< send event on pending */
|
||||
} nvic_lowpower_mode_type;
|
||||
|
||||
/**
|
||||
|
||||
@ -1,8 +1,6 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f403a_407_pwc.h
|
||||
* @version v2.0.9
|
||||
* @date 2022-04-25
|
||||
* @brief at32f403a_407 pwc header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
@ -60,7 +58,7 @@ extern "C" {
|
||||
/**
|
||||
* @brief pwc wakeup pin num definition
|
||||
*/
|
||||
#define PWC_WAKEUP_PIN_1 ((uint32_t)0x00000100) /*!< standby wake-up pin1 */
|
||||
#define PWC_WAKEUP_PIN_1 ((uint32_t)0x00000100) /*!< standby wake-up pin1(pa0) */
|
||||
|
||||
/** @defgroup PWC_exported_types
|
||||
* @{
|
||||
|
||||
@ -1,8 +1,6 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f403a_407_rtc.h
|
||||
* @version v2.0.9
|
||||
* @date 2022-04-25
|
||||
* @brief at32f403a_407 rtc header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
@ -238,6 +236,7 @@ uint32_t rtc_divider_get(void);
|
||||
void rtc_alarm_set(uint32_t alarm_value);
|
||||
void rtc_interrupt_enable(uint16_t source, confirm_state new_state);
|
||||
flag_status rtc_flag_get(uint16_t flag);
|
||||
flag_status rtc_interrupt_flag_get(uint16_t flag);
|
||||
void rtc_flag_clear(uint16_t flag);
|
||||
void rtc_wait_config_finish(void);
|
||||
void rtc_wait_update_finish(void);
|
||||
|
||||
@ -1,8 +1,6 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f403a_407_sdio.h
|
||||
* @version v2.0.9
|
||||
* @date 2022-04-25
|
||||
* @brief at32f403a_407 sdio header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
@ -569,7 +567,10 @@ typedef struct
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined (AT32F403ARx) || defined (AT32F403AVx) || defined (AT32F407Rx) || \
|
||||
defined (AT32F407Vx)
|
||||
#define SDIO1 ((sdio_type *) SDIO1_BASE)
|
||||
#endif
|
||||
#define SDIO2 ((sdio_type *) SDIO2_BASE)
|
||||
|
||||
/** @defgroup SDIO_exported_functions
|
||||
@ -578,7 +579,7 @@ typedef struct
|
||||
|
||||
void sdio_reset(sdio_type *sdio_x);
|
||||
void sdio_power_set(sdio_type *sdio_x, sdio_power_state_type power_state);
|
||||
flag_status sdio_power_status_get(sdio_type *sdio_x);
|
||||
sdio_power_state_type sdio_power_status_get(sdio_type *sdio_x);
|
||||
void sdio_clock_config(sdio_type *sdio_x, uint16_t clk_div, sdio_edge_phase_type clk_edg);
|
||||
void sdio_bus_width_config(sdio_type *sdio_x, sdio_bus_width_type width);
|
||||
void sdio_clock_bypass(sdio_type *sdio_x, confirm_state new_state);
|
||||
@ -588,6 +589,7 @@ void sdio_clock_enable(sdio_type *sdio_x, confirm_state new_state);
|
||||
void sdio_dma_enable(sdio_type *sdio_x, confirm_state new_state);
|
||||
void sdio_interrupt_enable(sdio_type *sdio_x, uint32_t int_opt, confirm_state new_state);
|
||||
flag_status sdio_flag_get(sdio_type *sdio_x, uint32_t flag);
|
||||
flag_status sdio_interrupt_flag_get(sdio_type *sdio_x, uint32_t flag);
|
||||
void sdio_flag_clear(sdio_type *sdio_x, uint32_t flag);
|
||||
void sdio_command_config(sdio_type *sdio_x, sdio_command_struct_type *command_struct);
|
||||
void sdio_command_state_machine_enable(sdio_type *sdio_x, confirm_state new_state);
|
||||
|
||||
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Reference in New Issue
Block a user