libs/rt-thread
libs/rt-thread
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fix compiling error.

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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1339 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
bernard.xiong 2011-03-21 07:40:54 +00:00
parent 8dbcab1c4a
commit ced8915d64
3 changed files with 61 additions and 59 deletions
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7
libcpu/arm/lpc24xx/interrupt.c
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@ -77,8 +77,11 @@ void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_ha
if(vector < MAX_HANDLERS) if(vector < MAX_HANDLERS)
{ {
/* find first un-assigned VIC address for the handler */ /* find first un-assigned VIC address for the handler */
vect_addr = (rt_uint32_t *)(VIC_BASE_ADDR + 0x100 + vector*4); vect_addr = (rt_uint32_t *)(VIC_BASE_ADDR + 0x100 + vector*4);
if (old_handler != RT_NULL) *old_handler = *vect_addr; /* get old handler */
/* get old handler */
if (old_handler != RT_NULL) *old_handler = (rt_isr_handler_t)*vect_addr;
*vect_addr = (rt_uint32_t)new_handler; /* set interrupt vector */ *vect_addr = (rt_uint32_t)new_handler; /* set interrupt vector */
} }
} }

1
libcpu/arm/lpc24xx/start_gcc.S
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@ -13,7 +13,6 @@
* 2011-03-17 Bernard update to 0.4.x * 2011-03-17 Bernard update to 0.4.x
*/ */
#define CONFIG_STACKSIZE 512
#define WDMOD (0xE0000000 + 0x00) #define WDMOD (0xE0000000 + 0x00)
#define VICIntEnClr (0xFFFFF000 + 0x014) #define VICIntEnClr (0xFFFFF000 + 0x014)
#define VICVectAddr (0xFFFFF000 + 0xF00) #define VICVectAddr (0xFFFFF000 + 0xF00)

112
libcpu/arm/lpc24xx/start_rvds.S
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@ -1056,7 +1056,7 @@ Vectors LDR PC, Reset_Addr
LDR PC, PAbt_Addr LDR PC, PAbt_Addr
LDR PC, DAbt_Addr LDR PC, DAbt_Addr
NOP ; Reserved Vector NOP ; Reserved Vector
LDR PC, IRQ_Addr LDR PC, IRQ_Addr
LDR PC, FIQ_Addr LDR PC, FIQ_Addr
Reset_Addr DCD Reset_Handler Reset_Addr DCD Reset_Handler
@ -1328,7 +1328,7 @@ Wait_2 SUBS R6, R6, #1 ; Delay
Wait_3 SUBS R6, R6, #1 ; Delay ~1 ms @ proc clk 57.6 MHz Wait_3 SUBS R6, R6, #1 ; Delay ~1 ms @ proc clk 57.6 MHz
BNE Wait_3 BNE Wait_3
ENDIF ; EMC_DYNAMIC_SETUP ENDIF ; EMC_DYNAMIC_SETUP
; Setup Static Memory Interface ; Setup Static Memory Interface
IF (EMC_STATIC_SETUP != 0) IF (EMC_STATIC_SETUP != 0)
@ -1487,75 +1487,75 @@ MEMMAP EQU 0xE01FC040 ; Memory Mapping Control
LDR R0, =__main LDR R0, =__main
BX R0 BX R0
IMPORT rt_interrupt_enter IMPORT rt_interrupt_enter
IMPORT rt_interrupt_leave IMPORT rt_interrupt_leave
IMPORT rt_thread_switch_interrput_flag IMPORT rt_thread_switch_interrput_flag
IMPORT rt_interrupt_from_thread IMPORT rt_interrupt_from_thread
IMPORT rt_interrupt_to_thread IMPORT rt_interrupt_to_thread
IMPORT rt_hw_trap_irq IMPORT rt_hw_trap_irq
IRQ_Handler PROC IRQ_Handler PROC
EXPORT IRQ_Handler EXPORT IRQ_Handler
STMFD sp!, {r0-r12,lr} STMFD sp!, {r0-r12,lr}
BL rt_interrupt_enter BL rt_interrupt_enter
BL rt_hw_trap_irq BL rt_hw_trap_irq
BL rt_interrupt_leave BL rt_interrupt_leave
; if rt_thread_switch_interrput_flag set, jump to ; if rt_thread_switch_interrput_flag set, jump to
; rt_hw_context_switch_interrupt_do and don't return ; rt_hw_context_switch_interrupt_do and don't return
LDR r0, =rt_thread_switch_interrput_flag LDR r0, =rt_thread_switch_interrput_flag
LDR r1, [r0] LDR r1, [r0]
CMP r1, #1 CMP r1, #1
BEQ rt_hw_context_switch_interrupt_do BEQ rt_hw_context_switch_interrupt_do
LDMFD sp!, {r0-r12,lr} LDMFD sp!, {r0-r12,lr}
SUBS pc, lr, #4 SUBS pc, lr, #4
ENDP ENDP
; /* ; /*
; * void rt_hw_context_switch_interrupt_do(rt_base_t flag) ; * void rt_hw_context_switch_interrupt_do(rt_base_t flag)
; */ ; */
rt_hw_context_switch_interrupt_do PROC rt_hw_context_switch_interrupt_do PROC
EXPORT rt_hw_context_switch_interrupt_do EXPORT rt_hw_context_switch_interrupt_do
MOV r1, #0 ; clear flag MOV r1, #0 ; clear flag
STR r1, [r0] STR r1, [r0]
LDMFD sp!, {r0-r12,lr}; reload saved registers LDMFD sp!, {r0-r12,lr}; reload saved registers
STMFD sp!, {r0-r3} ; save r0-r3 STMFD sp!, {r0-r3} ; save r0-r3
MOV r1, sp MOV r1, sp
ADD sp, sp, #16 ; restore sp ADD sp, sp, #16 ; restore sp
SUB r2, lr, #4 ; save old task's pc to r2 SUB r2, lr, #4 ; save old task's pc to r2
MRS r3, spsr ; get cpsr of interrupt thread MRS r3, spsr ; get cpsr of interrupt thread
; switch to SVC mode and no interrupt ; switch to SVC mode and no interrupt
MSR cpsr_c, #I_Bit|F_Bit|Mode_SVC MSR cpsr_c, #I_Bit|F_Bit|Mode_SVC
STMFD sp!, {r2} ; push old task's pc STMFD sp!, {r2} ; push old task's pc
STMFD sp!, {r4-r12,lr}; push old task's lr,r12-r4 STMFD sp!, {r4-r12,lr}; push old task's lr,r12-r4
MOV r4, r1 ; Special optimised code below MOV r4, r1 ; Special optimised code below
MOV r5, r3 MOV r5, r3
LDMFD r4!, {r0-r3} LDMFD r4!, {r0-r3}
STMFD sp!, {r0-r3} ; push old task's r3-r0 STMFD sp!, {r0-r3} ; push old task's r3-r0
STMFD sp!, {r5} ; push old task's cpsr STMFD sp!, {r5} ; push old task's cpsr
MRS r4, spsr MRS r4, spsr
STMFD sp!, {r4} ; push old task's spsr STMFD sp!, {r4} ; push old task's spsr
LDR r4, =rt_interrupt_from_thread LDR r4, =rt_interrupt_from_thread
LDR r5, [r4] LDR r5, [r4]
STR sp, [r5] ; store sp in preempted tasks's TCB STR sp, [r5] ; store sp in preempted tasks's TCB
LDR r6, =rt_interrupt_to_thread LDR r6, =rt_interrupt_to_thread
LDR r6, [r6] LDR r6, [r6]
LDR sp, [r6] ; get new task's stack pointer LDR sp, [r6] ; get new task's stack pointer
LDMFD sp!, {r4} ; pop new task's spsr LDMFD sp!, {r4} ; pop new task's spsr
MSR spsr_cxsf, r4 MSR spsr_cxsf, r4
LDMFD sp!, {r4} ; pop new task's psr LDMFD sp!, {r4} ; pop new task's psr
MSR cpsr_cxsf, r4 MSR cpsr_cxsf, r4
LDMFD sp!, {r0-r12,lr,pc} ; pop new task's r0-r12,lr & pc LDMFD sp!, {r0-r12,lr,pc} ; pop new task's r0-r12,lr & pc
ENDP ENDP
IF :DEF:__MICROLIB IF :DEF:__MICROLIB