Merge pull request #3548 from bigmagic123/fix_waring
Fix aarch64 waring
This commit is contained in:
Bernard Xiong
GitHub
commit
cd249bfcb1
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@ -31,6 +31,16 @@ EXEC_PATH = r'E:/env_released_1.1.2/env/tools/gnu_gcc/arm_gcc/gcc-arm-8.3-2019.0
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然后在`bsp\raspberry-pi\raspi3-64\`下输入scons编译即可。
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**window环境搭建注意**
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下载完成`gcc-arm-8.3-2019.03-i686-mingw32-aarch64-elf.tar.xz`交叉编译工具链后，最好采用7-zip解压工具进行两次解压。
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确保解压目录下的`/bin/aarch64-elf-ld.exe`文件的size不为0。
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否则编译会出现如下错误:
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```
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collect2.exe:fatal error:CreateProcess:No such file or directory
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```
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### 2.2 Linux上的环境搭建
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Linux下推荐使用[gcc工具][2]。Linux版本下gcc版本可采用`gcc-arm-8.3-2019.03-x86_64-aarch64-elf`。
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@ -18,10 +18,6 @@
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#include "mmu.h"
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static rt_uint64_t timerStep;
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// 0x40, 0x44, 0x48, 0x4c: Core 0~3 Timers interrupt control
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#define CORE0_TIMER_IRQ_CTRL HWREG32(0xFF800040)
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#define TIMER_IRQ 30
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#define NON_SECURE_TIMER_IRQ (1 << 1)
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int rt_hw_get_gtimer_frq(void);
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void rt_hw_set_gtimer_val(rt_uint64_t value);
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@ -29,7 +25,7 @@ int rt_hw_get_gtimer_val(void);
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int rt_hw_get_cntpct_val(void);
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void rt_hw_gtimer_enable(void);
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void core0_timer_enable_interrupt_controller()
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void core0_timer_enable_interrupt_controller(void)
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{
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CORE0_TIMER_IRQ_CTRL |= NON_SECURE_TIMER_IRQ;
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}
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@ -94,4 +90,4 @@ void rt_hw_board_init(void)
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#ifdef RT_USING_COMPONENTS_INIT
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rt_components_board_init();
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#endif
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}
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}
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@ -12,6 +12,7 @@
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#define BOARD_H__
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#include <stdint.h>
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#include "iomap.h"
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extern unsigned char __bss_start;
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extern unsigned char __bss_end;
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@ -22,4 +23,3 @@ extern unsigned char __bss_end;
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void rt_hw_board_init(void);
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#endif
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@ -17,8 +17,6 @@
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#include "board.h"
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#include "interrupt.h"
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#define GPIO_BASE (0xFE000000 + 0x00200000)
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#define GPIO_REG_GPFSEL0(BASE) HWREG32(BASE + 0x00)
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#define GPIO_REG_GPFSEL1(BASE) HWREG32(BASE + 0x04)
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#define GPIO_REG_GPFSEL2(BASE) HWREG32(BASE + 0x08)
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@ -16,12 +16,6 @@
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#include "drv_uart.h"
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#include "drv_gpio.h"
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#define UART0_BASE (0xFE000000 + 0x00201000)
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#define PL011_BASE UART0_BASE
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#define IRQ_PL011 (121 + 32)
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#define UART_REFERENCE_CLOCK 48000000
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struct hw_uart_device
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{
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rt_ubase_t hw_base;
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@ -81,4 +81,3 @@
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int rt_hw_uart_init(void);
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#endif /* DRV_UART_H__ */
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@ -1,8 +1,23 @@
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#ifndef __RASPI4_H__
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#define __RASPI4_H__
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#define ARM_GIC_NR_IRQS 512
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#define INTC_BASE 0xff800000
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//gpio
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#define GPIO_BASE (0xFE000000 + 0x00200000)
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//uart
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#define UART0_BASE (0xFE000000 + 0x00201000)
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#define PL011_BASE UART0_BASE
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#define IRQ_PL011 (121 + 32)
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#define UART_REFERENCE_CLOCK (48000000)
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// 0x40, 0x44, 0x48, 0x4c: Core 0~3 Timers interrupt control
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#define CORE0_TIMER_IRQ_CTRL HWREG32(0xFF800040)
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#define TIMER_IRQ 30
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#define NON_SECURE_TIMER_IRQ (1 << 1)
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//gic max
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#define ARM_GIC_NR_IRQS (512)
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#define INTC_BASE (0xff800000)
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#define GIC_V2_DISTRIBUTOR_BASE (INTC_BASE + 0x00041000)
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#define GIC_V2_CPU_INTERFACE_BASE (INTC_BASE + 0x00042000)
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#define GIC_V2_HYPERVISOR_BASE (INTC_BASE + 0x00044000)
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@ -11,4 +26,4 @@
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#define GIC_PL400_DISTRIBUTOR_PPTR GIC_V2_DISTRIBUTOR_BASE
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#define GIC_PL400_CONTROLLER_PPTR GIC_V2_CPU_INTERFACE_BASE
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#endif
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#endif
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@ -27,8 +27,8 @@
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#define HEAP_ALIGNMENT 4 /* heap alignment */
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#define FINSH_GET16(x) (*(x)) | (*((x)+1) << 8)
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#define FINSH_GET32(x) (rt_uint32_t)(*(x)) | ((rt_uint32_t)*((x)+1) << 8) | \
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((rt_uint32_t)*((x)+2) << 16) | ((rt_uint32_t)*((x)+3) << 24)
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#define FINSH_GET32(x) (rt_ubase_t)(*(x)) | ((rt_ubase_t)*((x)+1) << 8) | \
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((rt_ubase_t)*((x)+2) << 16) | ((rt_ubase_t)*((x)+3) << 24)
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#define FINSH_SET16(x, v) \
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do \
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@ -191,7 +191,7 @@ static int finsh_compile(struct finsh_node* node)
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case FINSH_NODE_VALUE_NULL:
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case FINSH_NODE_VALUE_STRING:
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finsh_code_byte(FINSH_OP_LD_DWORD);
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finsh_code_dword((uint32_t)node->value.ptr);
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finsh_code_dword((rt_ubase_t)node->value.ptr);
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break;
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/* arithmetic operation */
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