Follow coding-style and formatting.
This commit is contained in:
Wayne Lin
parent
4ae3a3a7f0
commit
cc32e7aa4d
File diff suppressed because it is too large
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@ -31,21 +31,21 @@
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* ARM Compiler 4/5
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*/
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#if defined ( __CC_ARM )
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#include "cmsis_armcc.h"
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#include "cmsis_armcc.h"
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/*
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* ARM Compiler 6 (armclang)
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*/
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#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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#include "cmsis_armclang.h"
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#include "cmsis_armclang.h"
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/*
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* GNU Compiler
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*/
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#elif defined ( __GNUC__ )
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#include "cmsis_gcc.h"
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#include "cmsis_gcc.h"
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/*
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@ -54,88 +54,94 @@
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#elif defined ( __ICCARM__ )
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#ifndef __ASM
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#ifndef __ASM
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#define __ASM __asm
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#endif
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#ifndef __INLINE
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#endif
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#ifndef __INLINE
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#define __INLINE inline
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#endif
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#ifndef __STATIC_INLINE
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#endif
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#ifndef __STATIC_INLINE
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#define __STATIC_INLINE static inline
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#endif
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#endif
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#include <cmsis_iar.h>
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#include <cmsis_iar.h>
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/* CMSIS compiler control architecture macros */
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#if (__CORE__ == __ARM6M__) || (__CORE__ == __ARM6SM__)
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/* CMSIS compiler control architecture macros */
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#if (__CORE__ == __ARM6M__) || (__CORE__ == __ARM6SM__)
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#ifndef __ARM_ARCH_6M__
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#define __ARM_ARCH_6M__ 1
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#endif
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#elif (__CORE__ == __ARM7M__)
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#elif (__CORE__ == __ARM7M__)
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#ifndef __ARM_ARCH_7M__
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#define __ARM_ARCH_7M__ 1
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#endif
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#elif (__CORE__ == __ARM7EM__)
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#elif (__CORE__ == __ARM7EM__)
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#ifndef __ARM_ARCH_7EM__
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#define __ARM_ARCH_7EM__ 1
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#endif
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#endif
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#endif
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#ifndef __NO_RETURN
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#ifndef __NO_RETURN
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#define __NO_RETURN __noreturn
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#endif
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#ifndef __USED
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#endif
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#ifndef __USED
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#define __USED __root
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#endif
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#ifndef __WEAK
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#endif
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#ifndef __WEAK
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#define __WEAK __weak
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#endif
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#ifndef __PACKED
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#endif
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#ifndef __PACKED
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#define __PACKED __packed
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#endif
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#ifndef __PACKED_STRUCT
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#endif
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#ifndef __PACKED_STRUCT
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#define __PACKED_STRUCT __packed struct
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#endif
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#ifndef __PACKED_UNION
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#endif
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#ifndef __PACKED_UNION
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#define __PACKED_UNION __packed union
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#endif
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#ifndef __UNALIGNED_UINT32 /* deprecated */
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__packed struct T_UINT32 { uint32_t v; };
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#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
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#endif
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#ifndef __UNALIGNED_UINT16_WRITE
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__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
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#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
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#endif
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#ifndef __UNALIGNED_UINT16_READ
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__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
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#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
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#endif
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#ifndef __UNALIGNED_UINT32_WRITE
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__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
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#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
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#endif
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#ifndef __UNALIGNED_UINT32_READ
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__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
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#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
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#endif
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#ifndef __ALIGNED
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#endif
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#ifndef __UNALIGNED_UINT32 /* deprecated */
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__packed struct T_UINT32
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{
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uint32_t v;
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};
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#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
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#endif
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#ifndef __UNALIGNED_UINT16_WRITE
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__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
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#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
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#endif
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#ifndef __UNALIGNED_UINT16_READ
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__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
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#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
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#endif
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#ifndef __UNALIGNED_UINT32_WRITE
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__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
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#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
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#endif
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#ifndef __UNALIGNED_UINT32_READ
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__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
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#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
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#endif
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#ifndef __ALIGNED
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//#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
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#define __ALIGNED(x)
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#endif
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#ifndef __RESTRICT
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#endif
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#ifndef __RESTRICT
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//#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
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#define __RESTRICT
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#endif
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#endif
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// Workaround for missing __CLZ intrinsic in
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// various versions of the IAR compilers.
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// __IAR_FEATURE_CLZ__ should be defined by
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// the compiler that supports __CLZ internally.
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#if (defined (__ARM_ARCH_6M__)) && (__ARM_ARCH_6M__ == 1) && (!defined (__IAR_FEATURE_CLZ__))
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__STATIC_INLINE uint32_t __CLZ(uint32_t data)
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// Workaround for missing __CLZ intrinsic in
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// various versions of the IAR compilers.
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// __IAR_FEATURE_CLZ__ should be defined by
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// the compiler that supports __CLZ internally.
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#if (defined (__ARM_ARCH_6M__)) && (__ARM_ARCH_6M__ == 1) && (!defined (__IAR_FEATURE_CLZ__))
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__STATIC_INLINE uint32_t __CLZ(uint32_t data)
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{
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if (data == 0u)
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{
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if (data == 0u) { return 32u; }
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return 32u;
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}
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uint32_t count = 0;
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uint32_t mask = 0x80000000;
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@ -147,205 +153,214 @@
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}
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return (count);
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}
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#endif
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}
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#endif
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/*
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* TI ARM Compiler
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*/
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#elif defined ( __TI_ARM__ )
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#include <cmsis_ccs.h>
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#include <cmsis_ccs.h>
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#ifndef __ASM
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#ifndef __ASM
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#define __ASM __asm
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#endif
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#ifndef __INLINE
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#endif
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#ifndef __INLINE
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#define __INLINE inline
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#endif
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#ifndef __STATIC_INLINE
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#endif
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#ifndef __STATIC_INLINE
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#define __STATIC_INLINE static inline
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#endif
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#ifndef __NO_RETURN
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#endif
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#ifndef __NO_RETURN
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#define __NO_RETURN __attribute__((noreturn))
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#endif
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#ifndef __USED
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#endif
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#ifndef __USED
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#define __USED __attribute__((used))
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#endif
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#ifndef __WEAK
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#endif
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#ifndef __WEAK
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#define __WEAK __attribute__((weak))
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#endif
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#ifndef __PACKED
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#endif
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#ifndef __PACKED
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#define __PACKED __attribute__((packed))
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#endif
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#ifndef __PACKED_STRUCT
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#endif
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#ifndef __PACKED_STRUCT
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#define __PACKED_STRUCT struct __attribute__((packed))
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#endif
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#ifndef __PACKED_UNION
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#endif
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#ifndef __PACKED_UNION
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#define __PACKED_UNION union __attribute__((packed))
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#endif
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#ifndef __UNALIGNED_UINT32 /* deprecated */
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struct __attribute__((packed)) T_UINT32 { uint32_t v; };
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#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
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#endif
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#ifndef __UNALIGNED_UINT16_WRITE
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__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
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#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
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#endif
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#ifndef __UNALIGNED_UINT16_READ
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__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
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#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
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#endif
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#ifndef __UNALIGNED_UINT32_WRITE
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__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
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#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
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#endif
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#ifndef __UNALIGNED_UINT32_READ
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__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
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#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
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#endif
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#ifndef __ALIGNED
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#endif
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#ifndef __UNALIGNED_UINT32 /* deprecated */
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struct __attribute__((packed)) T_UINT32
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{
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uint32_t v;
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};
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#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
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#endif
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#ifndef __UNALIGNED_UINT16_WRITE
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__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
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#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
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#endif
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#ifndef __UNALIGNED_UINT16_READ
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__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
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#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
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#endif
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#ifndef __UNALIGNED_UINT32_WRITE
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__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
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#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
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#endif
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#ifndef __UNALIGNED_UINT32_READ
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__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
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#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
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#endif
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#ifndef __ALIGNED
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#define __ALIGNED(x) __attribute__((aligned(x)))
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#endif
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#ifndef __RESTRICT
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#endif
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#ifndef __RESTRICT
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#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
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#define __RESTRICT
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#endif
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#endif
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/*
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* TASKING Compiler
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*/
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#elif defined ( __TASKING__ )
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/*
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/*
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* The CMSIS functions have been implemented as intrinsics in the compiler.
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* Please use "carm -?i" to get an up to date list of all intrinsics,
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* Including the CMSIS ones.
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*/
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#ifndef __ASM
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#ifndef __ASM
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#define __ASM __asm
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#endif
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#ifndef __INLINE
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#endif
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#ifndef __INLINE
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#define __INLINE inline
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#endif
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#ifndef __STATIC_INLINE
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#endif
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#ifndef __STATIC_INLINE
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#define __STATIC_INLINE static inline
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#endif
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#ifndef __NO_RETURN
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#endif
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#ifndef __NO_RETURN
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#define __NO_RETURN __attribute__((noreturn))
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#endif
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#ifndef __USED
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#endif
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#ifndef __USED
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#define __USED __attribute__((used))
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#endif
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#ifndef __WEAK
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#endif
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#ifndef __WEAK
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#define __WEAK __attribute__((weak))
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#endif
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#ifndef __PACKED
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#endif
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#ifndef __PACKED
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#define __PACKED __packed__
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#endif
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#ifndef __PACKED_STRUCT
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#endif
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#ifndef __PACKED_STRUCT
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#define __PACKED_STRUCT struct __packed__
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#endif
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#ifndef __PACKED_UNION
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#endif
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#ifndef __PACKED_UNION
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#define __PACKED_UNION union __packed__
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#endif
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#ifndef __UNALIGNED_UINT32 /* deprecated */
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struct __packed__ T_UINT32 { uint32_t v; };
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#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
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#endif
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#ifndef __UNALIGNED_UINT16_WRITE
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__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
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#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
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#endif
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#ifndef __UNALIGNED_UINT16_READ
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__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
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#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
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#endif
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#ifndef __UNALIGNED_UINT32_WRITE
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__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
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#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
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#endif
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#ifndef __UNALIGNED_UINT32_READ
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__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
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#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
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#endif
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#ifndef __ALIGNED
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#endif
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#ifndef __UNALIGNED_UINT32 /* deprecated */
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struct __packed__ T_UINT32
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{
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uint32_t v;
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};
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#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
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#endif
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#ifndef __UNALIGNED_UINT16_WRITE
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__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
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#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
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#endif
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#ifndef __UNALIGNED_UINT16_READ
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__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
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#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
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#endif
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#ifndef __UNALIGNED_UINT32_WRITE
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__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
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#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
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#endif
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#ifndef __UNALIGNED_UINT32_READ
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__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
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#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
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#endif
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#ifndef __ALIGNED
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#define __ALIGNED(x) __align(x)
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||||
#endif
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||||
#ifndef __RESTRICT
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||||
#endif
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||||
#ifndef __RESTRICT
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||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
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#define __RESTRICT
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||||
#endif
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||||
#endif
|
||||
|
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|
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/*
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* COSMIC Compiler
|
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*/
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||||
#elif defined ( __CSMC__ )
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#include <cmsis_csm.h>
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#include <cmsis_csm.h>
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|
||||
#ifndef __ASM
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||||
#ifndef __ASM
|
||||
#define __ASM _asm
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||||
#endif
|
||||
#ifndef __INLINE
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||||
#endif
|
||||
#ifndef __INLINE
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||||
#define __INLINE inline
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||||
#endif
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||||
#ifndef __STATIC_INLINE
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||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
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||||
#endif
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||||
#ifndef __NO_RETURN
|
||||
#endif
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||||
#ifndef __NO_RETURN
|
||||
// NO RETURN is automatically detected hence no warning here
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||||
#define __NO_RETURN
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||||
#endif
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||||
#ifndef __USED
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||||
#endif
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||||
#ifndef __USED
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||||
#warning No compiler specific solution for __USED. __USED is ignored.
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||||
#define __USED
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||||
#endif
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||||
#ifndef __WEAK
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||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __weak
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED @packed
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT @packed struct
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION @packed union
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
@packed struct T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
@packed struct T_UINT32
|
||||
{
|
||||
uint32_t v;
|
||||
};
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
|
||||
#define __ALIGNED(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
#else
|
||||
#error Unknown compiler.
|
||||
#error Unknown compiler.
|
||||
#endif
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@
|
|||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
|
|
@ -76,39 +76,39 @@
|
|||
#define __FPU_USED 0U
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#if defined __TARGET_FPU_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
#if defined __TARGET_FPU_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#if defined __ARM_PCS_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
#if defined __ARM_PCS_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#if defined __ARMVFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
#if defined __ARMVFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#if defined __TI_VFP_SUPPORT__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
#if defined __TI_VFP_SUPPORT__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#if defined __FPU_VFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
#if defined __FPU_VFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
#if ( __CSMC__ & 0x400U)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
#if ( __CSMC__ & 0x400U)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -127,55 +127,55 @@
|
|||
#define __CORE_ARMV8MBL_H_DEPENDANT
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* check device defines and use defaults */
|
||||
#if defined __CHECK_DEVICE_DEFINES
|
||||
#ifndef __ARMv8MBL_REV
|
||||
#define __ARMv8MBL_REV 0x0000U
|
||||
#warning "__ARMv8MBL_REV not defined in device header file; using default!"
|
||||
#endif
|
||||
#ifndef __ARMv8MBL_REV
|
||||
#define __ARMv8MBL_REV 0x0000U
|
||||
#warning "__ARMv8MBL_REV not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __FPU_PRESENT
|
||||
#define __FPU_PRESENT 0U
|
||||
#warning "__FPU_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
#ifndef __FPU_PRESENT
|
||||
#define __FPU_PRESENT 0U
|
||||
#warning "__FPU_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __MPU_PRESENT
|
||||
#define __MPU_PRESENT 0U
|
||||
#warning "__MPU_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
#ifndef __MPU_PRESENT
|
||||
#define __MPU_PRESENT 0U
|
||||
#warning "__MPU_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __SAUREGION_PRESENT
|
||||
#define __SAUREGION_PRESENT 0U
|
||||
#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
#ifndef __SAUREGION_PRESENT
|
||||
#define __SAUREGION_PRESENT 0U
|
||||
#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __VTOR_PRESENT
|
||||
#define __VTOR_PRESENT 0U
|
||||
#warning "__VTOR_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
#ifndef __VTOR_PRESENT
|
||||
#define __VTOR_PRESENT 0U
|
||||
#warning "__VTOR_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __NVIC_PRIO_BITS
|
||||
#define __NVIC_PRIO_BITS 2U
|
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||
#endif
|
||||
#ifndef __NVIC_PRIO_BITS
|
||||
#define __NVIC_PRIO_BITS 2U
|
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __Vendor_SysTickConfig
|
||||
#define __Vendor_SysTickConfig 0U
|
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||
#endif
|
||||
#ifndef __Vendor_SysTickConfig
|
||||
#define __Vendor_SysTickConfig 0U
|
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __ETM_PRESENT
|
||||
#define __ETM_PRESENT 0U
|
||||
#warning "__ETM_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
#ifndef __ETM_PRESENT
|
||||
#define __ETM_PRESENT 0U
|
||||
#warning "__ETM_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __MTB_PRESENT
|
||||
#define __MTB_PRESENT 0U
|
||||
#warning "__MTB_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
#ifndef __MTB_PRESENT
|
||||
#define __MTB_PRESENT 0U
|
||||
#warning "__MTB_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -188,9 +188,9 @@
|
|||
\li for automatic generation of peripheral register debug information.
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
#define __I volatile /*!< Defines 'read only' permissions */
|
||||
#define __I volatile /*!< Defines 'read only' permissions */
|
||||
#else
|
||||
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||
#endif
|
||||
#define __O volatile /*!< Defines 'write only' permissions */
|
||||
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||
|
|
@ -234,11 +234,11 @@ typedef union
|
|||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
uint32_t _reserved0: 28; /*!< bit: 0..27 Reserved */
|
||||
uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} APSR_Type;
|
||||
|
|
@ -264,8 +264,8 @@ typedef union
|
|||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
|
||||
uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} IPSR_Type;
|
||||
|
|
@ -282,14 +282,14 @@ typedef union
|
|||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
|
||||
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
||||
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */
|
||||
uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */
|
||||
uint32_t _reserved1: 3; /*!< bit: 25..27 Reserved */
|
||||
uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} xPSR_Type;
|
||||
|
|
@ -321,9 +321,9 @@ typedef union
|
|||
{
|
||||
struct
|
||||
{
|
||||
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
|
||||
uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
|
||||
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
|
||||
uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */
|
||||
uint32_t SPSEL: 1; /*!< bit: 1 Stack-pointer select */
|
||||
uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} CONTROL_Type;
|
||||
|
|
@ -1157,48 +1157,48 @@ typedef struct
|
|||
*/
|
||||
|
||||
/* Memory mapping of Core Hardware */
|
||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||
#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
|
||||
#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
|
||||
#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
|
||||
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||
#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
|
||||
#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
|
||||
#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
|
||||
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
||||
|
||||
|
||||
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
||||
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
||||
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
||||
#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
|
||||
#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
|
||||
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
|
||||
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
||||
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
||||
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
||||
#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
|
||||
#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
|
||||
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
|
||||
|
||||
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
|
||||
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
|
||||
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
|
||||
#endif
|
||||
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
#define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
|
||||
#define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
|
||||
#endif
|
||||
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
|
||||
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
|
||||
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
|
||||
#endif
|
||||
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
#define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
|
||||
#define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
|
||||
#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
|
||||
#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
|
||||
#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
|
||||
#define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
|
||||
#define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
|
||||
#endif
|
||||
|
||||
#define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
|
||||
#define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
|
||||
#define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
|
||||
#define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
#define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
|
||||
#define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
|
||||
#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
|
||||
#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
|
||||
#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
|
||||
|
||||
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
|
||||
#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
|
||||
#define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
|
||||
#endif
|
||||
#define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
|
||||
#define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
|
||||
#define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
|
||||
#define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
|
||||
|
||||
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
|
||||
#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
|
||||
#define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
|
||||
#endif
|
||||
|
||||
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
|
||||
/*@} */
|
||||
|
|
@ -1227,33 +1227,33 @@ typedef struct
|
|||
*/
|
||||
|
||||
#ifdef CMSIS_NVIC_VIRTUAL
|
||||
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#else
|
||||
/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for ARMv8-M Baseline */
|
||||
/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for ARMv8-M Baseline */
|
||||
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
||||
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
||||
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
||||
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||
#define NVIC_GetActive __NVIC_GetActive
|
||||
#define NVIC_SetPriority __NVIC_SetPriority
|
||||
#define NVIC_GetPriority __NVIC_GetPriority
|
||||
#define NVIC_SystemReset __NVIC_SystemReset
|
||||
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
||||
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
||||
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
||||
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||
#define NVIC_GetActive __NVIC_GetActive
|
||||
#define NVIC_SetPriority __NVIC_SetPriority
|
||||
#define NVIC_GetPriority __NVIC_GetPriority
|
||||
#define NVIC_SystemReset __NVIC_SystemReset
|
||||
#endif /* CMSIS_NVIC_VIRTUAL */
|
||||
|
||||
#ifdef CMSIS_VECTAB_VIRTUAL
|
||||
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#else
|
||||
#define NVIC_SetVector __NVIC_SetVector
|
||||
#define NVIC_GetVector __NVIC_GetVector
|
||||
#define NVIC_SetVector __NVIC_SetVector
|
||||
#define NVIC_GetVector __NVIC_GetVector
|
||||
#endif /* (CMSIS_VECTAB_VIRTUAL) */
|
||||
|
||||
#define NVIC_USER_IRQ_OFFSET 16
|
||||
|
|
@ -1293,11 +1293,11 @@ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
|
|||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
return ((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
return (0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1331,11 +1331,11 @@ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
|||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
return ((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
return (0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1382,11 +1382,11 @@ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
|
|||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
return ((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
return (0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1404,11 +1404,11 @@ __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
|
|||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
return ((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
return (0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1426,11 +1426,11 @@ __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
|
|||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
|
||||
return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
return ((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
return (0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1448,11 +1448,11 @@ __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
|
|||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
|
||||
return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
return ((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
return (0U);
|
||||
}
|
||||
}
|
||||
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
|
||||
|
|
@ -1496,11 +1496,11 @@ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
|||
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
return ((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
else
|
||||
{
|
||||
return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
return ((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1557,7 +1557,7 @@ __STATIC_INLINE void __NVIC_SystemReset(void)
|
|||
SCB_AIRCR_SYSRESETREQ_Msk);
|
||||
__DSB(); /* Ensure completion of memory access */
|
||||
|
||||
for(;;) /* wait until reset */
|
||||
for (;;) /* wait until reset */
|
||||
{
|
||||
__NOP();
|
||||
}
|
||||
|
|
@ -1591,11 +1591,11 @@ __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
|
|||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
return ((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
return (0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1627,7 +1627,7 @@ __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
|
|||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
return ((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1674,11 +1674,11 @@ __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
|
|||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
return ((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
return (0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1720,11 +1720,11 @@ __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
|
|||
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
return ((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
else
|
||||
{
|
||||
return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
return ((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
}
|
||||
#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
|
||||
|
|
@ -1824,7 +1824,7 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
|||
}
|
||||
|
||||
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
||||
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||
NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
SysTick_CTRL_TICKINT_Msk |
|
||||
|
|
@ -1853,7 +1853,7 @@ __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
|
|||
}
|
||||
|
||||
SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
||||
TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||
TZ_NVIC_SetPriority_NS(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||
SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||
SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
SysTick_CTRL_TICKINT_Msk |
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@
|
|||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
|
|
@ -74,88 +74,88 @@
|
|||
For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
|
||||
*/
|
||||
#if defined ( __CC_ARM )
|
||||
#if defined __TARGET_FPU_VFP
|
||||
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||
#define __FPU_USED 1U
|
||||
#else
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#else
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#if defined __TARGET_FPU_VFP
|
||||
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||
#define __FPU_USED 1U
|
||||
#else
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#else
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#if defined __ARM_PCS_VFP
|
||||
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||
#define __FPU_USED 1U
|
||||
#else
|
||||
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#else
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#if defined __ARM_PCS_VFP
|
||||
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||
#define __FPU_USED 1U
|
||||
#else
|
||||
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#else
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||
#define __FPU_USED 1U
|
||||
#else
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#else
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||
#define __FPU_USED 1U
|
||||
#else
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#else
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#if defined __ARMVFP__
|
||||
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||
#define __FPU_USED 1U
|
||||
#else
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#else
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#if defined __ARMVFP__
|
||||
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||
#define __FPU_USED 1U
|
||||
#else
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#else
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#if defined __TI_VFP_SUPPORT__
|
||||
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||
#define __FPU_USED 1U
|
||||
#else
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#else
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#if defined __TI_VFP_SUPPORT__
|
||||
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||
#define __FPU_USED 1U
|
||||
#else
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#else
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#if defined __FPU_VFP__
|
||||
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||
#define __FPU_USED 1U
|
||||
#else
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#else
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#if defined __FPU_VFP__
|
||||
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||
#define __FPU_USED 1U
|
||||
#else
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#else
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
#if ( __CSMC__ & 0x400U)
|
||||
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||
#define __FPU_USED 1U
|
||||
#else
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#else
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#if ( __CSMC__ & 0x400U)
|
||||
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||
#define __FPU_USED 1U
|
||||
#else
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#else
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -174,45 +174,45 @@
|
|||
#define __CORE_ARMV8MML_H_DEPENDANT
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* check device defines and use defaults */
|
||||
#if defined __CHECK_DEVICE_DEFINES
|
||||
#ifndef __ARMv8MML_REV
|
||||
#define __ARMv8MML_REV 0x0000U
|
||||
#warning "__ARMv8MML_REV not defined in device header file; using default!"
|
||||
#endif
|
||||
#ifndef __ARMv8MML_REV
|
||||
#define __ARMv8MML_REV 0x0000U
|
||||
#warning "__ARMv8MML_REV not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __FPU_PRESENT
|
||||
#define __FPU_PRESENT 0U
|
||||
#warning "__FPU_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
#ifndef __FPU_PRESENT
|
||||
#define __FPU_PRESENT 0U
|
||||
#warning "__FPU_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __MPU_PRESENT
|
||||
#define __MPU_PRESENT 0U
|
||||
#warning "__MPU_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
#ifndef __MPU_PRESENT
|
||||
#define __MPU_PRESENT 0U
|
||||
#warning "__MPU_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __SAUREGION_PRESENT
|
||||
#define __SAUREGION_PRESENT 0U
|
||||
#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
#ifndef __SAUREGION_PRESENT
|
||||
#define __SAUREGION_PRESENT 0U
|
||||
#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __DSP_PRESENT
|
||||
#define __DSP_PRESENT 0U
|
||||
#warning "__DSP_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
#ifndef __DSP_PRESENT
|
||||
#define __DSP_PRESENT 0U
|
||||
#warning "__DSP_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __NVIC_PRIO_BITS
|
||||
#define __NVIC_PRIO_BITS 3U
|
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||
#endif
|
||||
#ifndef __NVIC_PRIO_BITS
|
||||
#define __NVIC_PRIO_BITS 3U
|
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __Vendor_SysTickConfig
|
||||
#define __Vendor_SysTickConfig 0U
|
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||
#endif
|
||||
#ifndef __Vendor_SysTickConfig
|
||||
#define __Vendor_SysTickConfig 0U
|
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* IO definitions (access restrictions to peripheral registers) */
|
||||
|
|
@ -224,9 +224,9 @@
|
|||
\li for automatic generation of peripheral register debug information.
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
#define __I volatile /*!< Defines 'read only' permissions */
|
||||
#define __I volatile /*!< Defines 'read only' permissions */
|
||||
#else
|
||||
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||
#endif
|
||||
#define __O volatile /*!< Defines 'write only' permissions */
|
||||
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||
|
|
@ -271,14 +271,14 @@ typedef union
|
|||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
|
||||
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
|
||||
uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
|
||||
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
uint32_t _reserved0: 16; /*!< bit: 0..15 Reserved */
|
||||
uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */
|
||||
uint32_t _reserved1: 7; /*!< bit: 20..26 Reserved */
|
||||
uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */
|
||||
uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} APSR_Type;
|
||||
|
|
@ -310,8 +310,8 @@ typedef union
|
|||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
|
||||
uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} IPSR_Type;
|
||||
|
|
@ -328,17 +328,17 @@ typedef union
|
|||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
|
||||
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
|
||||
uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
|
||||
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
||||
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
|
||||
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0: 7; /*!< bit: 9..15 Reserved */
|
||||
uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */
|
||||
uint32_t _reserved1: 4; /*!< bit: 20..23 Reserved */
|
||||
uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */
|
||||
uint32_t IT: 2; /*!< bit: 25..26 saved IT state (read 0) */
|
||||
uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */
|
||||
uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} xPSR_Type;
|
||||
|
|
@ -379,11 +379,11 @@ typedef union
|
|||
{
|
||||
struct
|
||||
{
|
||||
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
|
||||
uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
|
||||
uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
|
||||
uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
|
||||
uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
|
||||
uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */
|
||||
uint32_t SPSEL: 1; /*!< bit: 1 Stack-pointer select */
|
||||
uint32_t FPCA: 1; /*!< bit: 2 Floating-point context active */
|
||||
uint32_t SFPA: 1; /*!< bit: 3 Secure floating-point active */
|
||||
uint32_t _reserved1: 28; /*!< bit: 4..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} CONTROL_Type;
|
||||
|
|
@ -1973,57 +1973,57 @@ typedef struct
|
|||
*/
|
||||
|
||||
/* Memory mapping of Core Hardware */
|
||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||
#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
|
||||
#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
|
||||
#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
|
||||
#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
|
||||
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||
#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
|
||||
#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
|
||||
#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
|
||||
#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
|
||||
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
||||
|
||||
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
|
||||
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
||||
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
||||
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
||||
#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
|
||||
#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
|
||||
#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
|
||||
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
|
||||
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
|
||||
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
||||
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
||||
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
||||
#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
|
||||
#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
|
||||
#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
|
||||
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
|
||||
|
||||
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
|
||||
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
|
||||
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
|
||||
#endif
|
||||
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
#define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
|
||||
#define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
|
||||
#endif
|
||||
|
||||
#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
|
||||
#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
|
||||
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
|
||||
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
|
||||
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
|
||||
#endif
|
||||
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
#define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
|
||||
#define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
|
||||
#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
|
||||
#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
|
||||
#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
|
||||
#define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
|
||||
#define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
|
||||
#endif
|
||||
|
||||
#define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
|
||||
#define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
|
||||
#define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
|
||||
#define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
|
||||
#define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
|
||||
#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
|
||||
#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
|
||||
|
||||
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
|
||||
#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
|
||||
#define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
|
||||
#endif
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
#define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
|
||||
#define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
|
||||
#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
|
||||
#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
|
||||
#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
|
||||
|
||||
#define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
|
||||
#define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
|
||||
#define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
|
||||
#define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
|
||||
#define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
|
||||
#define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
|
||||
#define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
|
||||
|
||||
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
|
||||
#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
|
||||
#define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
|
||||
#endif
|
||||
|
||||
#define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
|
||||
#define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
|
||||
|
||||
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
|
||||
/*@} */
|
||||
|
|
@ -2053,33 +2053,33 @@ typedef struct
|
|||
*/
|
||||
|
||||
#ifdef CMSIS_NVIC_VIRTUAL
|
||||
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#else
|
||||
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
|
||||
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
|
||||
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
||||
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
||||
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
||||
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||
#define NVIC_GetActive __NVIC_GetActive
|
||||
#define NVIC_SetPriority __NVIC_SetPriority
|
||||
#define NVIC_GetPriority __NVIC_GetPriority
|
||||
#define NVIC_SystemReset __NVIC_SystemReset
|
||||
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
|
||||
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
|
||||
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
||||
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
||||
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
||||
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||
#define NVIC_GetActive __NVIC_GetActive
|
||||
#define NVIC_SetPriority __NVIC_SetPriority
|
||||
#define NVIC_GetPriority __NVIC_GetPriority
|
||||
#define NVIC_SystemReset __NVIC_SystemReset
|
||||
#endif /* CMSIS_NVIC_VIRTUAL */
|
||||
|
||||
#ifdef CMSIS_VECTAB_VIRTUAL
|
||||
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#else
|
||||
#define NVIC_SetVector __NVIC_SetVector
|
||||
#define NVIC_GetVector __NVIC_GetVector
|
||||
#define NVIC_SetVector __NVIC_SetVector
|
||||
#define NVIC_GetVector __NVIC_GetVector
|
||||
#endif /* (CMSIS_VECTAB_VIRTUAL) */
|
||||
|
||||
#define NVIC_USER_IRQ_OFFSET 16
|
||||
|
|
@ -2104,7 +2104,7 @@ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|||
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
|
||||
reg_value = (reg_value |
|
||||
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||||
(PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
|
||||
(PriorityGroupTmp << 8U)); /* Insert write key and priorty group */
|
||||
SCB->AIRCR = reg_value;
|
||||
}
|
||||
|
||||
|
|
@ -2147,11 +2147,11 @@ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
|
|||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
return ((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
return (0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -2185,11 +2185,11 @@ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
|||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
return ((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
return (0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -2236,11 +2236,11 @@ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
|
|||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
return ((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
return (0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -2258,11 +2258,11 @@ __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
|
|||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
return ((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
return (0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -2280,11 +2280,11 @@ __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
|
|||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
|
||||
return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
return ((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
return (0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -2302,11 +2302,11 @@ __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
|
|||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
|
||||
return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
return ((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
return (0U);
|
||||
}
|
||||
}
|
||||
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
|
||||
|
|
@ -2329,7 +2329,7 @@ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
|||
}
|
||||
else
|
||||
{
|
||||
SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
||||
SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -2348,11 +2348,11 @@ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
|||
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
|
||||
return (((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
|
||||
return (((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -2368,7 +2368,7 @@ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
|||
\param [in] SubPriority Subpriority value (starting from 0).
|
||||
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
||||
*/
|
||||
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
||||
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
||||
{
|
||||
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||
uint32_t PreemptPriorityBits;
|
||||
|
|
@ -2379,7 +2379,7 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
|
|||
|
||||
return (
|
||||
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
||||
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
||||
((SubPriority & (uint32_t)((1UL << (SubPriorityBits)) - 1UL)))
|
||||
);
|
||||
}
|
||||
|
||||
|
|
@ -2395,7 +2395,7 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
|
|||
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
|
||||
\param [out] pSubPriority Subpriority value (starting from 0).
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
|
||||
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
|
||||
{
|
||||
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||
uint32_t PreemptPriorityBits;
|
||||
|
|
@ -2405,7 +2405,7 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
|
|||
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||
|
||||
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
|
||||
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
|
||||
*pSubPriority = (Priority) & (uint32_t)((1UL << (SubPriorityBits)) - 1UL);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -2450,10 +2450,10 @@ __STATIC_INLINE void __NVIC_SystemReset(void)
|
|||
buffered write are completed before reset */
|
||||
SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||||
(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
|
||||
SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
|
||||
SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
|
||||
__DSB(); /* Ensure completion of memory access */
|
||||
|
||||
for(;;) /* wait until reset */
|
||||
for (;;) /* wait until reset */
|
||||
{
|
||||
__NOP();
|
||||
}
|
||||
|
|
@ -2478,7 +2478,7 @@ __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
|
|||
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
|
||||
reg_value = (reg_value |
|
||||
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||||
(PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
|
||||
(PriorityGroupTmp << 8U)); /* Insert write key and priorty group */
|
||||
SCB_NS->AIRCR = reg_value;
|
||||
}
|
||||
|
||||
|
|
@ -2521,11 +2521,11 @@ __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
|
|||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
return ((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
return (0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -2557,11 +2557,11 @@ __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
|
|||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
return ((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
return (0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -2608,11 +2608,11 @@ __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
|
|||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
return ((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
return (0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -2634,7 +2634,7 @@ __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
|
|||
}
|
||||
else
|
||||
{
|
||||
SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
||||
SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -2652,11 +2652,11 @@ __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
|
|||
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
|
||||
return (((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
|
||||
return (((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
}
|
||||
#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
|
||||
|
|
@ -2770,7 +2770,7 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
|||
}
|
||||
|
||||
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
||||
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||
NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
SysTick_CTRL_TICKINT_Msk |
|
||||
|
|
@ -2799,7 +2799,7 @@ __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
|
|||
}
|
||||
|
||||
SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
||||
TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||
TZ_NVIC_SetPriority_NS(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||
SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||
SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
SysTick_CTRL_TICKINT_Msk |
|
||||
|
|
@ -2834,10 +2834,10 @@ extern volatile int32_t ITM_RxBuffer; /*!< External
|
|||
\param [in] ch Character to transmit.
|
||||
\returns Character to transmit.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
|
||||
__STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch)
|
||||
{
|
||||
if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
|
||||
((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
|
||||
((ITM->TER & 1UL) != 0UL)) /* ITM Port #0 enabled */
|
||||
{
|
||||
while (ITM->PORT[0U].u32 == 0UL)
|
||||
{
|
||||
|
|
@ -2855,7 +2855,7 @@ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
|
|||
\return Received character.
|
||||
\return -1 No character pending.
|
||||
*/
|
||||
__STATIC_INLINE int32_t ITM_ReceiveChar (void)
|
||||
__STATIC_INLINE int32_t ITM_ReceiveChar(void)
|
||||
{
|
||||
int32_t ch = -1; /* no character available */
|
||||
|
||||
|
|
@ -2875,7 +2875,7 @@ __STATIC_INLINE int32_t ITM_ReceiveChar (void)
|
|||
\return 0 No character available.
|
||||
\return 1 Character available.
|
||||
*/
|
||||
__STATIC_INLINE int32_t ITM_CheckChar (void)
|
||||
__STATIC_INLINE int32_t ITM_CheckChar(void)
|
||||
{
|
||||
|
||||
if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@
|
|||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
|
|
@ -76,39 +76,39 @@
|
|||
#define __FPU_USED 0U
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#if defined __TARGET_FPU_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
#if defined __TARGET_FPU_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#if defined __ARM_PCS_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
#if defined __ARM_PCS_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#if defined __ARMVFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
#if defined __ARMVFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#if defined __TI_VFP_SUPPORT__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
#if defined __TI_VFP_SUPPORT__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#if defined __FPU_VFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
#if defined __FPU_VFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
#if ( __CSMC__ & 0x400U)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
#if ( __CSMC__ & 0x400U)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -127,25 +127,25 @@
|
|||
#define __CORE_CM0_H_DEPENDANT
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* check device defines and use defaults */
|
||||
#if defined __CHECK_DEVICE_DEFINES
|
||||
#ifndef __CM0_REV
|
||||
#define __CM0_REV 0x0000U
|
||||
#warning "__CM0_REV not defined in device header file; using default!"
|
||||
#endif
|
||||
#ifndef __CM0_REV
|
||||
#define __CM0_REV 0x0000U
|
||||
#warning "__CM0_REV not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __NVIC_PRIO_BITS
|
||||
#define __NVIC_PRIO_BITS 2U
|
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||
#endif
|
||||
#ifndef __NVIC_PRIO_BITS
|
||||
#define __NVIC_PRIO_BITS 2U
|
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __Vendor_SysTickConfig
|
||||
#define __Vendor_SysTickConfig 0U
|
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||
#endif
|
||||
#ifndef __Vendor_SysTickConfig
|
||||
#define __Vendor_SysTickConfig 0U
|
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* IO definitions (access restrictions to peripheral registers) */
|
||||
|
|
@ -157,9 +157,9 @@
|
|||
\li for automatic generation of peripheral register debug information.
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
#define __I volatile /*!< Defines 'read only' permissions */
|
||||
#define __I volatile /*!< Defines 'read only' permissions */
|
||||
#else
|
||||
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||
#endif
|
||||
#define __O volatile /*!< Defines 'write only' permissions */
|
||||
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||
|
|
@ -200,11 +200,11 @@ typedef union
|
|||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
uint32_t _reserved0: 28; /*!< bit: 0..27 Reserved */
|
||||
uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} APSR_Type;
|
||||
|
|
@ -230,8 +230,8 @@ typedef union
|
|||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
|
||||
uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} IPSR_Type;
|
||||
|
|
@ -248,14 +248,14 @@ typedef union
|
|||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
|
||||
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
||||
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */
|
||||
uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */
|
||||
uint32_t _reserved1: 3; /*!< bit: 25..27 Reserved */
|
||||
uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} xPSR_Type;
|
||||
|
|
@ -287,9 +287,9 @@ typedef union
|
|||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
|
||||
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
|
||||
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
|
||||
uint32_t _reserved0: 1; /*!< bit: 0 Reserved */
|
||||
uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */
|
||||
uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} CONTROL_Type;
|
||||
|
|
@ -567,33 +567,33 @@ typedef struct
|
|||
*/
|
||||
|
||||
#ifdef CMSIS_NVIC_VIRTUAL
|
||||
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#else
|
||||
/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0 */
|
||||
/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0 */
|
||||
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
||||
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
||||
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
||||
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
||||
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
||||
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
||||
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
|
||||
#define NVIC_SetPriority __NVIC_SetPriority
|
||||
#define NVIC_GetPriority __NVIC_GetPriority
|
||||
#define NVIC_SystemReset __NVIC_SystemReset
|
||||
#define NVIC_SetPriority __NVIC_SetPriority
|
||||
#define NVIC_GetPriority __NVIC_GetPriority
|
||||
#define NVIC_SystemReset __NVIC_SystemReset
|
||||
#endif /* CMSIS_NVIC_VIRTUAL */
|
||||
|
||||
#ifdef CMSIS_VECTAB_VIRTUAL
|
||||
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#else
|
||||
#define NVIC_SetVector __NVIC_SetVector
|
||||
#define NVIC_GetVector __NVIC_GetVector
|
||||
#define NVIC_SetVector __NVIC_SetVector
|
||||
#define NVIC_GetVector __NVIC_GetVector
|
||||
#endif /* (CMSIS_VECTAB_VIRTUAL) */
|
||||
|
||||
#define NVIC_USER_IRQ_OFFSET 16
|
||||
|
|
@ -633,11 +633,11 @@ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
|
|||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
return ((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
return (0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -671,11 +671,11 @@ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
|||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
return ((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
return (0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -748,11 +748,11 @@ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
|||
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
return ((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
else
|
||||
{
|
||||
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
return ((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -800,7 +800,7 @@ __STATIC_INLINE void __NVIC_SystemReset(void)
|
|||
SCB_AIRCR_SYSRESETREQ_Msk);
|
||||
__DSB(); /* Ensure completion of memory access */
|
||||
|
||||
for(;;) /* wait until reset */
|
||||
for (;;) /* wait until reset */
|
||||
{
|
||||
__NOP();
|
||||
}
|
||||
|
|
@ -864,7 +864,7 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
|||
}
|
||||
|
||||
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
||||
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||
NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
SysTick_CTRL_TICKINT_Msk |
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@
|
|||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
|
|
@ -76,39 +76,39 @@
|
|||
#define __FPU_USED 0U
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#if defined __TARGET_FPU_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
#if defined __TARGET_FPU_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#if defined __ARM_PCS_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
#if defined __ARM_PCS_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#if defined __ARMVFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
#if defined __ARMVFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#if defined __TI_VFP_SUPPORT__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
#if defined __TI_VFP_SUPPORT__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#if defined __FPU_VFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
#if defined __FPU_VFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
#if ( __CSMC__ & 0x400U)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
#if ( __CSMC__ & 0x400U)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -127,35 +127,35 @@
|
|||
#define __CORE_CM0PLUS_H_DEPENDANT
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* check device defines and use defaults */
|
||||
#if defined __CHECK_DEVICE_DEFINES
|
||||
#ifndef __CM0PLUS_REV
|
||||
#define __CM0PLUS_REV 0x0000U
|
||||
#warning "__CM0PLUS_REV not defined in device header file; using default!"
|
||||
#endif
|
||||
#ifndef __CM0PLUS_REV
|
||||
#define __CM0PLUS_REV 0x0000U
|
||||
#warning "__CM0PLUS_REV not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __MPU_PRESENT
|
||||
#define __MPU_PRESENT 0U
|
||||
#warning "__MPU_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
#ifndef __MPU_PRESENT
|
||||
#define __MPU_PRESENT 0U
|
||||
#warning "__MPU_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __VTOR_PRESENT
|
||||
#define __VTOR_PRESENT 0U
|
||||
#warning "__VTOR_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
#ifndef __VTOR_PRESENT
|
||||
#define __VTOR_PRESENT 0U
|
||||
#warning "__VTOR_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __NVIC_PRIO_BITS
|
||||
#define __NVIC_PRIO_BITS 2U
|
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||
#endif
|
||||
#ifndef __NVIC_PRIO_BITS
|
||||
#define __NVIC_PRIO_BITS 2U
|
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __Vendor_SysTickConfig
|
||||
#define __Vendor_SysTickConfig 0U
|
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||
#endif
|
||||
#ifndef __Vendor_SysTickConfig
|
||||
#define __Vendor_SysTickConfig 0U
|
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* IO definitions (access restrictions to peripheral registers) */
|
||||
|
|
@ -167,9 +167,9 @@
|
|||
\li for automatic generation of peripheral register debug information.
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
#define __I volatile /*!< Defines 'read only' permissions */
|
||||
#define __I volatile /*!< Defines 'read only' permissions */
|
||||
#else
|
||||
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||
#endif
|
||||
#define __O volatile /*!< Defines 'write only' permissions */
|
||||
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||
|
|
@ -211,11 +211,11 @@ typedef union
|
|||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
uint32_t _reserved0: 28; /*!< bit: 0..27 Reserved */
|
||||
uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} APSR_Type;
|
||||
|
|
@ -241,8 +241,8 @@ typedef union
|
|||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
|
||||
uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} IPSR_Type;
|
||||
|
|
@ -259,14 +259,14 @@ typedef union
|
|||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
|
||||
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
||||
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */
|
||||
uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */
|
||||
uint32_t _reserved1: 3; /*!< bit: 25..27 Reserved */
|
||||
uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} xPSR_Type;
|
||||
|
|
@ -298,9 +298,9 @@ typedef union
|
|||
{
|
||||
struct
|
||||
{
|
||||
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
|
||||
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
|
||||
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
|
||||
uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */
|
||||
uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */
|
||||
uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} CONTROL_Type;
|
||||
|
|
@ -653,8 +653,8 @@ typedef struct
|
|||
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
||||
|
||||
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
|
||||
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
|
||||
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
|
||||
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
|
||||
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
|
||||
#endif
|
||||
|
||||
/*@} */
|
||||
|
|
@ -683,33 +683,33 @@ typedef struct
|
|||
*/
|
||||
|
||||
#ifdef CMSIS_NVIC_VIRTUAL
|
||||
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#else
|
||||
/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0+ */
|
||||
/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0+ */
|
||||
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
||||
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
||||
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
||||
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
||||
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
||||
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
||||
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */
|
||||
#define NVIC_SetPriority __NVIC_SetPriority
|
||||
#define NVIC_GetPriority __NVIC_GetPriority
|
||||
#define NVIC_SystemReset __NVIC_SystemReset
|
||||
#define NVIC_SetPriority __NVIC_SetPriority
|
||||
#define NVIC_GetPriority __NVIC_GetPriority
|
||||
#define NVIC_SystemReset __NVIC_SystemReset
|
||||
#endif /* CMSIS_NVIC_VIRTUAL */
|
||||
|
||||
#ifdef CMSIS_VECTAB_VIRTUAL
|
||||
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#else
|
||||
#define NVIC_SetVector __NVIC_SetVector
|
||||
#define NVIC_GetVector __NVIC_GetVector
|
||||
#define NVIC_SetVector __NVIC_SetVector
|
||||
#define NVIC_GetVector __NVIC_GetVector
|
||||
#endif /* (CMSIS_VECTAB_VIRTUAL) */
|
||||
|
||||
#define NVIC_USER_IRQ_OFFSET 16
|
||||
|
|
@ -749,11 +749,11 @@ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
|
|||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
return ((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
return (0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -787,11 +787,11 @@ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
|||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
return ((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
return (0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -864,11 +864,11 @@ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
|||
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
return ((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
else
|
||||
{
|
||||
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
return ((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -926,7 +926,7 @@ __STATIC_INLINE void __NVIC_SystemReset(void)
|
|||
SCB_AIRCR_SYSRESETREQ_Msk);
|
||||
__DSB(); /* Ensure completion of memory access */
|
||||
|
||||
for(;;) /* wait until reset */
|
||||
for (;;) /* wait until reset */
|
||||
{
|
||||
__NOP();
|
||||
}
|
||||
|
|
@ -997,7 +997,7 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
|||
}
|
||||
|
||||
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
||||
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||
NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
SysTick_CTRL_TICKINT_Msk |
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@
|
|||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
|
|
@ -76,39 +76,39 @@
|
|||
#define __FPU_USED 0U
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#if defined __TARGET_FPU_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
#if defined __TARGET_FPU_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#if defined __ARM_PCS_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
#if defined __ARM_PCS_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#if defined __ARMVFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
#if defined __ARMVFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#if defined __TI_VFP_SUPPORT__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
#if defined __TI_VFP_SUPPORT__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#if defined __FPU_VFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
#if defined __FPU_VFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
#if ( __CSMC__ & 0x400U)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
#if ( __CSMC__ & 0x400U)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -127,30 +127,30 @@
|
|||
#define __CORE_CM3_H_DEPENDANT
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* check device defines and use defaults */
|
||||
#if defined __CHECK_DEVICE_DEFINES
|
||||
#ifndef __CM3_REV
|
||||
#define __CM3_REV 0x0200U
|
||||
#warning "__CM3_REV not defined in device header file; using default!"
|
||||
#endif
|
||||
#ifndef __CM3_REV
|
||||
#define __CM3_REV 0x0200U
|
||||
#warning "__CM3_REV not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __MPU_PRESENT
|
||||
#define __MPU_PRESENT 0U
|
||||
#warning "__MPU_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
#ifndef __MPU_PRESENT
|
||||
#define __MPU_PRESENT 0U
|
||||
#warning "__MPU_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __NVIC_PRIO_BITS
|
||||
#define __NVIC_PRIO_BITS 3U
|
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||
#endif
|
||||
#ifndef __NVIC_PRIO_BITS
|
||||
#define __NVIC_PRIO_BITS 3U
|
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __Vendor_SysTickConfig
|
||||
#define __Vendor_SysTickConfig 0U
|
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||
#endif
|
||||
#ifndef __Vendor_SysTickConfig
|
||||
#define __Vendor_SysTickConfig 0U
|
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* IO definitions (access restrictions to peripheral registers) */
|
||||
|
|
@ -162,9 +162,9 @@
|
|||
\li for automatic generation of peripheral register debug information.
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
#define __I volatile /*!< Defines 'read only' permissions */
|
||||
#define __I volatile /*!< Defines 'read only' permissions */
|
||||
#else
|
||||
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||
#endif
|
||||
#define __O volatile /*!< Defines 'write only' permissions */
|
||||
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||
|
|
@ -207,12 +207,12 @@ typedef union
|
|||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
|
||||
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
uint32_t _reserved0: 27; /*!< bit: 0..26 Reserved */
|
||||
uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */
|
||||
uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} APSR_Type;
|
||||
|
|
@ -241,8 +241,8 @@ typedef union
|
|||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
|
||||
uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} IPSR_Type;
|
||||
|
|
@ -259,17 +259,17 @@ typedef union
|
|||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:1; /*!< bit: 9 Reserved */
|
||||
uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
|
||||
uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */
|
||||
uint32_t T:1; /*!< bit: 24 Thumb bit */
|
||||
uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
|
||||
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0: 1; /*!< bit: 9 Reserved */
|
||||
uint32_t ICI_IT_1: 6; /*!< bit: 10..15 ICI/IT part 1 */
|
||||
uint32_t _reserved1: 8; /*!< bit: 16..23 Reserved */
|
||||
uint32_t T: 1; /*!< bit: 24 Thumb bit */
|
||||
uint32_t ICI_IT_2: 2; /*!< bit: 25..26 ICI/IT part 2 */
|
||||
uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */
|
||||
uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} xPSR_Type;
|
||||
|
|
@ -310,9 +310,9 @@ typedef union
|
|||
{
|
||||
struct
|
||||
{
|
||||
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
|
||||
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
|
||||
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
|
||||
uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */
|
||||
uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */
|
||||
uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} CONTROL_Type;
|
||||
|
|
@ -1391,8 +1391,8 @@ typedef struct
|
|||
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
|
||||
|
||||
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
|
||||
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
|
||||
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
|
||||
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
|
||||
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
|
||||
#endif
|
||||
|
||||
/*@} */
|
||||
|
|
@ -1422,33 +1422,33 @@ typedef struct
|
|||
*/
|
||||
|
||||
#ifdef CMSIS_NVIC_VIRTUAL
|
||||
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#else
|
||||
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
|
||||
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
|
||||
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
||||
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
||||
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
||||
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||
#define NVIC_GetActive __NVIC_GetActive
|
||||
#define NVIC_SetPriority __NVIC_SetPriority
|
||||
#define NVIC_GetPriority __NVIC_GetPriority
|
||||
#define NVIC_SystemReset __NVIC_SystemReset
|
||||
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
|
||||
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
|
||||
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
||||
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
||||
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
||||
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||
#define NVIC_GetActive __NVIC_GetActive
|
||||
#define NVIC_SetPriority __NVIC_SetPriority
|
||||
#define NVIC_GetPriority __NVIC_GetPriority
|
||||
#define NVIC_SystemReset __NVIC_SystemReset
|
||||
#endif /* CMSIS_NVIC_VIRTUAL */
|
||||
|
||||
#ifdef CMSIS_VECTAB_VIRTUAL
|
||||
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#else
|
||||
#define NVIC_SetVector __NVIC_SetVector
|
||||
#define NVIC_GetVector __NVIC_GetVector
|
||||
#define NVIC_SetVector __NVIC_SetVector
|
||||
#define NVIC_GetVector __NVIC_GetVector
|
||||
#endif /* (CMSIS_VECTAB_VIRTUAL) */
|
||||
|
||||
#define NVIC_USER_IRQ_OFFSET 16
|
||||
|
|
@ -1473,7 +1473,7 @@ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|||
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
|
||||
reg_value = (reg_value |
|
||||
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||||
(PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
|
||||
(PriorityGroupTmp << 8U)); /* Insert write key and priorty group */
|
||||
SCB->AIRCR = reg_value;
|
||||
}
|
||||
|
||||
|
|
@ -1516,11 +1516,11 @@ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
|
|||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
return ((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
return (0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1554,11 +1554,11 @@ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
|||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
return ((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
return (0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1605,11 +1605,11 @@ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
|
|||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
return ((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
return (0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1631,7 +1631,7 @@ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
|||
}
|
||||
else
|
||||
{
|
||||
SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
||||
SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1650,11 +1650,11 @@ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
|||
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
|
||||
return (((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
|
||||
return (((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1670,7 +1670,7 @@ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
|||
\param [in] SubPriority Subpriority value (starting from 0).
|
||||
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
||||
*/
|
||||
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
||||
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
||||
{
|
||||
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||
uint32_t PreemptPriorityBits;
|
||||
|
|
@ -1681,7 +1681,7 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
|
|||
|
||||
return (
|
||||
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
||||
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
||||
((SubPriority & (uint32_t)((1UL << (SubPriorityBits)) - 1UL)))
|
||||
);
|
||||
}
|
||||
|
||||
|
|
@ -1697,7 +1697,7 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
|
|||
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
|
||||
\param [out] pSubPriority Subpriority value (starting from 0).
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
|
||||
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
|
||||
{
|
||||
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||
uint32_t PreemptPriorityBits;
|
||||
|
|
@ -1707,7 +1707,7 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
|
|||
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||
|
||||
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
|
||||
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
|
||||
*pSubPriority = (Priority) & (uint32_t)((1UL << (SubPriorityBits)) - 1UL);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -1752,10 +1752,10 @@ __STATIC_INLINE void __NVIC_SystemReset(void)
|
|||
buffered write are completed before reset */
|
||||
SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||||
(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
|
||||
SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
|
||||
SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
|
||||
__DSB(); /* Ensure completion of memory access */
|
||||
|
||||
for(;;) /* wait until reset */
|
||||
for (;;) /* wait until reset */
|
||||
{
|
||||
__NOP();
|
||||
}
|
||||
|
|
@ -1826,7 +1826,7 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
|||
}
|
||||
|
||||
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
||||
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||
NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
SysTick_CTRL_TICKINT_Msk |
|
||||
|
|
@ -1860,10 +1860,10 @@ extern volatile int32_t ITM_RxBuffer; /*!< External
|
|||
\param [in] ch Character to transmit.
|
||||
\returns Character to transmit.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
|
||||
__STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch)
|
||||
{
|
||||
if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
|
||||
((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
|
||||
((ITM->TER & 1UL) != 0UL)) /* ITM Port #0 enabled */
|
||||
{
|
||||
while (ITM->PORT[0U].u32 == 0UL)
|
||||
{
|
||||
|
|
@ -1881,7 +1881,7 @@ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
|
|||
\return Received character.
|
||||
\return -1 No character pending.
|
||||
*/
|
||||
__STATIC_INLINE int32_t ITM_ReceiveChar (void)
|
||||
__STATIC_INLINE int32_t ITM_ReceiveChar(void)
|
||||
{
|
||||
int32_t ch = -1; /* no character available */
|
||||
|
||||
|
|
@ -1901,7 +1901,7 @@ __STATIC_INLINE int32_t ITM_ReceiveChar (void)
|
|||
\return 0 No character available.
|
||||
\return 1 Character available.
|
||||
*/
|
||||
__STATIC_INLINE int32_t ITM_CheckChar (void)
|
||||
__STATIC_INLINE int32_t ITM_CheckChar(void)
|
||||
{
|
||||
|
||||
if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@
|
|||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
|
|
@ -74,88 +74,88 @@
|
|||
For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
|
||||
*/
|
||||
#if defined ( __CC_ARM )
|
||||
#if defined __TARGET_FPU_VFP
|
||||
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||
#define __FPU_USED 1U
|
||||
#else
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#else
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#if defined __TARGET_FPU_VFP
|
||||
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||
#define __FPU_USED 1U
|
||||
#else
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#else
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#if defined __ARM_PCS_VFP
|
||||
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||
#define __FPU_USED 1U
|
||||
#else
|
||||
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#else
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#if defined __ARM_PCS_VFP
|
||||
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||
#define __FPU_USED 1U
|
||||
#else
|
||||
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#else
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||
#define __FPU_USED 1U
|
||||
#else
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#else
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||
#define __FPU_USED 1U
|
||||
#else
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#else
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#if defined __ARMVFP__
|
||||
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||
#define __FPU_USED 1U
|
||||
#else
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#else
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#if defined __ARMVFP__
|
||||
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||
#define __FPU_USED 1U
|
||||
#else
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#else
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#if defined __TI_VFP_SUPPORT__
|
||||
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||
#define __FPU_USED 1U
|
||||
#else
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#else
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#if defined __TI_VFP_SUPPORT__
|
||||
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||
#define __FPU_USED 1U
|
||||
#else
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#else
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#if defined __FPU_VFP__
|
||||
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||
#define __FPU_USED 1U
|
||||
#else
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#else
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#if defined __FPU_VFP__
|
||||
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||
#define __FPU_USED 1U
|
||||
#else
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#else
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
#if ( __CSMC__ & 0x400U)
|
||||
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||
#define __FPU_USED 1U
|
||||
#else
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#else
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#if ( __CSMC__ & 0x400U)
|
||||
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||
#define __FPU_USED 1U
|
||||
#else
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#else
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -174,45 +174,45 @@
|
|||
#define __CORE_CM33_H_DEPENDANT
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* check device defines and use defaults */
|
||||
#if defined __CHECK_DEVICE_DEFINES
|
||||
#ifndef __CM33_REV
|
||||
#define __CM33_REV 0x0000U
|
||||
#warning "__CM33_REV not defined in device header file; using default!"
|
||||
#endif
|
||||
#ifndef __CM33_REV
|
||||
#define __CM33_REV 0x0000U
|
||||
#warning "__CM33_REV not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __FPU_PRESENT
|
||||
#define __FPU_PRESENT 0U
|
||||
#warning "__FPU_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
#ifndef __FPU_PRESENT
|
||||
#define __FPU_PRESENT 0U
|
||||
#warning "__FPU_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __MPU_PRESENT
|
||||
#define __MPU_PRESENT 0U
|
||||
#warning "__MPU_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
#ifndef __MPU_PRESENT
|
||||
#define __MPU_PRESENT 0U
|
||||
#warning "__MPU_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __SAUREGION_PRESENT
|
||||
#define __SAUREGION_PRESENT 0U
|
||||
#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
#ifndef __SAUREGION_PRESENT
|
||||
#define __SAUREGION_PRESENT 0U
|
||||
#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __DSP_PRESENT
|
||||
#define __DSP_PRESENT 0U
|
||||
#warning "__DSP_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
#ifndef __DSP_PRESENT
|
||||
#define __DSP_PRESENT 0U
|
||||
#warning "__DSP_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __NVIC_PRIO_BITS
|
||||
#define __NVIC_PRIO_BITS 3U
|
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||
#endif
|
||||
#ifndef __NVIC_PRIO_BITS
|
||||
#define __NVIC_PRIO_BITS 3U
|
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __Vendor_SysTickConfig
|
||||
#define __Vendor_SysTickConfig 0U
|
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||
#endif
|
||||
#ifndef __Vendor_SysTickConfig
|
||||
#define __Vendor_SysTickConfig 0U
|
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* IO definitions (access restrictions to peripheral registers) */
|
||||
|
|
@ -224,9 +224,9 @@
|
|||
\li for automatic generation of peripheral register debug information.
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
#define __I volatile /*!< Defines 'read only' permissions */
|
||||
#define __I volatile /*!< Defines 'read only' permissions */
|
||||
#else
|
||||
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||
#endif
|
||||
#define __O volatile /*!< Defines 'write only' permissions */
|
||||
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||
|
|
@ -271,14 +271,14 @@ typedef union
|
|||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
|
||||
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
|
||||
uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
|
||||
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
uint32_t _reserved0: 16; /*!< bit: 0..15 Reserved */
|
||||
uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */
|
||||
uint32_t _reserved1: 7; /*!< bit: 20..26 Reserved */
|
||||
uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */
|
||||
uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} APSR_Type;
|
||||
|
|
@ -310,8 +310,8 @@ typedef union
|
|||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
|
||||
uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} IPSR_Type;
|
||||
|
|
@ -328,17 +328,17 @@ typedef union
|
|||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
|
||||
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
|
||||
uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
|
||||
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
||||
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
|
||||
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0: 7; /*!< bit: 9..15 Reserved */
|
||||
uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */
|
||||
uint32_t _reserved1: 4; /*!< bit: 20..23 Reserved */
|
||||
uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */
|
||||
uint32_t IT: 2; /*!< bit: 25..26 saved IT state (read 0) */
|
||||
uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */
|
||||
uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} xPSR_Type;
|
||||
|
|
@ -379,11 +379,11 @@ typedef union
|
|||
{
|
||||
struct
|
||||
{
|
||||
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
|
||||
uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
|
||||
uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
|
||||
uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
|
||||
uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
|
||||
uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */
|
||||
uint32_t SPSEL: 1; /*!< bit: 1 Stack-pointer select */
|
||||
uint32_t FPCA: 1; /*!< bit: 2 Floating-point context active */
|
||||
uint32_t SFPA: 1; /*!< bit: 3 Secure floating-point active */
|
||||
uint32_t _reserved1: 28; /*!< bit: 4..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} CONTROL_Type;
|
||||
|
|
@ -1973,57 +1973,57 @@ typedef struct
|
|||
*/
|
||||
|
||||
/* Memory mapping of Core Hardware */
|
||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||
#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
|
||||
#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
|
||||
#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
|
||||
#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
|
||||
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||
#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
|
||||
#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
|
||||
#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
|
||||
#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
|
||||
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
||||
|
||||
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
|
||||
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
||||
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
||||
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
||||
#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
|
||||
#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
|
||||
#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
|
||||
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
|
||||
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
|
||||
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
||||
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
||||
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
||||
#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
|
||||
#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
|
||||
#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
|
||||
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
|
||||
|
||||
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
|
||||
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
|
||||
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
|
||||
#endif
|
||||
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
#define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
|
||||
#define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
|
||||
#endif
|
||||
|
||||
#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
|
||||
#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
|
||||
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
|
||||
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
|
||||
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
|
||||
#endif
|
||||
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
#define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
|
||||
#define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
|
||||
#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
|
||||
#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
|
||||
#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
|
||||
#define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
|
||||
#define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
|
||||
#endif
|
||||
|
||||
#define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
|
||||
#define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
|
||||
#define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
|
||||
#define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
|
||||
#define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
|
||||
#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
|
||||
#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
|
||||
|
||||
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
|
||||
#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
|
||||
#define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
|
||||
#endif
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
#define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
|
||||
#define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
|
||||
#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
|
||||
#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
|
||||
#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
|
||||
|
||||
#define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
|
||||
#define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
|
||||
#define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
|
||||
#define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
|
||||
#define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
|
||||
#define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
|
||||
#define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
|
||||
|
||||
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
|
||||
#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
|
||||
#define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
|
||||
#endif
|
||||
|
||||
#define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
|
||||
#define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
|
||||
|
||||
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
|
||||
/*@} */
|
||||
|
|
@ -2053,33 +2053,33 @@ typedef struct
|
|||
*/
|
||||
|
||||
#ifdef CMSIS_NVIC_VIRTUAL
|
||||
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#else
|
||||
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
|
||||
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
|
||||
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
||||
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
||||
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
||||
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||
#define NVIC_GetActive __NVIC_GetActive
|
||||
#define NVIC_SetPriority __NVIC_SetPriority
|
||||
#define NVIC_GetPriority __NVIC_GetPriority
|
||||
#define NVIC_SystemReset __NVIC_SystemReset
|
||||
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
|
||||
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
|
||||
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
||||
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
||||
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
||||
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||
#define NVIC_GetActive __NVIC_GetActive
|
||||
#define NVIC_SetPriority __NVIC_SetPriority
|
||||
#define NVIC_GetPriority __NVIC_GetPriority
|
||||
#define NVIC_SystemReset __NVIC_SystemReset
|
||||
#endif /* CMSIS_NVIC_VIRTUAL */
|
||||
|
||||
#ifdef CMSIS_VECTAB_VIRTUAL
|
||||
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#else
|
||||
#define NVIC_SetVector __NVIC_SetVector
|
||||
#define NVIC_GetVector __NVIC_GetVector
|
||||
#define NVIC_SetVector __NVIC_SetVector
|
||||
#define NVIC_GetVector __NVIC_GetVector
|
||||
#endif /* (CMSIS_VECTAB_VIRTUAL) */
|
||||
|
||||
#define NVIC_USER_IRQ_OFFSET 16
|
||||
|
|
@ -2104,7 +2104,7 @@ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|||
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
|
||||
reg_value = (reg_value |
|
||||
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||||
(PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
|
||||
(PriorityGroupTmp << 8U)); /* Insert write key and priorty group */
|
||||
SCB->AIRCR = reg_value;
|
||||
}
|
||||
|
||||
|
|
@ -2147,11 +2147,11 @@ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
|
|||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
return ((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
return (0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -2185,11 +2185,11 @@ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
|||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
return ((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
return (0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -2236,11 +2236,11 @@ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
|
|||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
return ((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
return (0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -2258,11 +2258,11 @@ __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
|
|||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
return ((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
return (0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -2280,11 +2280,11 @@ __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
|
|||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
|
||||
return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
return ((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
return (0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -2302,11 +2302,11 @@ __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
|
|||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
|
||||
return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
return ((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
return (0U);
|
||||
}
|
||||
}
|
||||
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
|
||||
|
|
@ -2329,7 +2329,7 @@ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
|||
}
|
||||
else
|
||||
{
|
||||
SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
||||
SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -2348,11 +2348,11 @@ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
|||
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
|
||||
return (((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
|
||||
return (((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -2368,7 +2368,7 @@ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
|||
\param [in] SubPriority Subpriority value (starting from 0).
|
||||
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
||||
*/
|
||||
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
||||
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
||||
{
|
||||
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||
uint32_t PreemptPriorityBits;
|
||||
|
|
@ -2379,7 +2379,7 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
|
|||
|
||||
return (
|
||||
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
||||
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
||||
((SubPriority & (uint32_t)((1UL << (SubPriorityBits)) - 1UL)))
|
||||
);
|
||||
}
|
||||
|
||||
|
|
@ -2395,7 +2395,7 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
|
|||
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
|
||||
\param [out] pSubPriority Subpriority value (starting from 0).
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
|
||||
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
|
||||
{
|
||||
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||
uint32_t PreemptPriorityBits;
|
||||
|
|
@ -2405,7 +2405,7 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
|
|||
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||
|
||||
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
|
||||
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
|
||||
*pSubPriority = (Priority) & (uint32_t)((1UL << (SubPriorityBits)) - 1UL);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -2450,10 +2450,10 @@ __STATIC_INLINE void __NVIC_SystemReset(void)
|
|||
buffered write are completed before reset */
|
||||
SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||||
(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
|
||||
SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
|
||||
SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
|
||||
__DSB(); /* Ensure completion of memory access */
|
||||
|
||||
for(;;) /* wait until reset */
|
||||
for (;;) /* wait until reset */
|
||||
{
|
||||
__NOP();
|
||||
}
|
||||
|
|
@ -2478,7 +2478,7 @@ __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
|
|||
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
|
||||
reg_value = (reg_value |
|
||||
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||||
(PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
|
||||
(PriorityGroupTmp << 8U)); /* Insert write key and priorty group */
|
||||
SCB_NS->AIRCR = reg_value;
|
||||
}
|
||||
|
||||
|
|
@ -2521,11 +2521,11 @@ __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
|
|||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
return ((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
return (0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -2557,7 +2557,7 @@ __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
|
|||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
return ((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -2604,11 +2604,11 @@ __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
|
|||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
return ((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
return (0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -2630,7 +2630,7 @@ __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
|
|||
}
|
||||
else
|
||||
{
|
||||
SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
||||
SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -2648,11 +2648,11 @@ __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
|
|||
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
|
||||
return (((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
|
||||
return (((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
}
|
||||
#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
|
||||
|
|
@ -2766,7 +2766,7 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
|||
}
|
||||
|
||||
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
||||
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||
NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
SysTick_CTRL_TICKINT_Msk |
|
||||
|
|
@ -2795,7 +2795,7 @@ __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
|
|||
}
|
||||
|
||||
SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
||||
TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||
TZ_NVIC_SetPriority_NS(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||
SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||
SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
SysTick_CTRL_TICKINT_Msk |
|
||||
|
|
@ -2830,10 +2830,10 @@ extern volatile int32_t ITM_RxBuffer; /*!< External
|
|||
\param [in] ch Character to transmit.
|
||||
\returns Character to transmit.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
|
||||
__STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch)
|
||||
{
|
||||
if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
|
||||
((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
|
||||
((ITM->TER & 1UL) != 0UL)) /* ITM Port #0 enabled */
|
||||
{
|
||||
while (ITM->PORT[0U].u32 == 0UL)
|
||||
{
|
||||
|
|
@ -2851,7 +2851,7 @@ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
|
|||
\return Received character.
|
||||
\return -1 No character pending.
|
||||
*/
|
||||
__STATIC_INLINE int32_t ITM_ReceiveChar (void)
|
||||
__STATIC_INLINE int32_t ITM_ReceiveChar(void)
|
||||
{
|
||||
int32_t ch = -1; /* no character available */
|
||||
|
||||
|
|
@ -2871,7 +2871,7 @@ __STATIC_INLINE int32_t ITM_ReceiveChar (void)
|
|||
\return 0 No character available.
|
||||
\return 1 Character available.
|
||||
*/
|
||||
__STATIC_INLINE int32_t ITM_CheckChar (void)
|
||||
__STATIC_INLINE int32_t ITM_CheckChar(void)
|
||||
{
|
||||
|
||||
if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@
|
|||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
|
|
@ -74,88 +74,88 @@
|
|||
For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
|
||||
*/
|
||||
#if defined ( __CC_ARM )
|
||||
#if defined __TARGET_FPU_VFP
|
||||
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||
#define __FPU_USED 1U
|
||||
#else
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#else
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#if defined __TARGET_FPU_VFP
|
||||
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||
#define __FPU_USED 1U
|
||||
#else
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#else
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#if defined __ARM_PCS_VFP
|
||||
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||
#define __FPU_USED 1U
|
||||
#else
|
||||
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#else
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#if defined __ARM_PCS_VFP
|
||||
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||
#define __FPU_USED 1U
|
||||
#else
|
||||
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#else
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||
#define __FPU_USED 1U
|
||||
#else
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#else
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||
#define __FPU_USED 1U
|
||||
#else
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#else
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#if defined __ARMVFP__
|
||||
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||
#define __FPU_USED 1U
|
||||
#else
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#else
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#if defined __ARMVFP__
|
||||
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||
#define __FPU_USED 1U
|
||||
#else
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#else
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#if defined __TI_VFP_SUPPORT__
|
||||
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||
#define __FPU_USED 1U
|
||||
#else
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#else
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#if defined __TI_VFP_SUPPORT__
|
||||
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||
#define __FPU_USED 1U
|
||||
#else
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#else
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#if defined __FPU_VFP__
|
||||
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||
#define __FPU_USED 1U
|
||||
#else
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#else
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#if defined __FPU_VFP__
|
||||
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||
#define __FPU_USED 1U
|
||||
#else
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#else
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
#if ( __CSMC__ & 0x400U)
|
||||
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||
#define __FPU_USED 1U
|
||||
#else
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#else
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#if ( __CSMC__ & 0x400U)
|
||||
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||
#define __FPU_USED 1U
|
||||
#else
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
#else
|
||||
#define __FPU_USED 0U
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -174,35 +174,35 @@
|
|||
#define __CORE_CM4_H_DEPENDANT
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* check device defines and use defaults */
|
||||
#if defined __CHECK_DEVICE_DEFINES
|
||||
#ifndef __CM4_REV
|
||||
#define __CM4_REV 0x0000U
|
||||
#warning "__CM4_REV not defined in device header file; using default!"
|
||||
#endif
|
||||
#ifndef __CM4_REV
|
||||
#define __CM4_REV 0x0000U
|
||||
#warning "__CM4_REV not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __FPU_PRESENT
|
||||
#define __FPU_PRESENT 0U
|
||||
#warning "__FPU_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
#ifndef __FPU_PRESENT
|
||||
#define __FPU_PRESENT 0U
|
||||
#warning "__FPU_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __MPU_PRESENT
|
||||
#define __MPU_PRESENT 0U
|
||||
#warning "__MPU_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
#ifndef __MPU_PRESENT
|
||||
#define __MPU_PRESENT 0U
|
||||
#warning "__MPU_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __NVIC_PRIO_BITS
|
||||
#define __NVIC_PRIO_BITS 3U
|
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||
#endif
|
||||
#ifndef __NVIC_PRIO_BITS
|
||||
#define __NVIC_PRIO_BITS 3U
|
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __Vendor_SysTickConfig
|
||||
#define __Vendor_SysTickConfig 0U
|
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||
#endif
|
||||
#ifndef __Vendor_SysTickConfig
|
||||
#define __Vendor_SysTickConfig 0U
|
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* IO definitions (access restrictions to peripheral registers) */
|
||||
|
|
@ -214,9 +214,9 @@
|
|||
\li for automatic generation of peripheral register debug information.
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
#define __I volatile /*!< Defines 'read only' permissions */
|
||||
#define __I volatile /*!< Defines 'read only' permissions */
|
||||
#else
|
||||
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||
#endif
|
||||
#define __O volatile /*!< Defines 'write only' permissions */
|
||||
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||
|
|
@ -260,14 +260,14 @@ typedef union
|
|||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
|
||||
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
|
||||
uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
|
||||
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
uint32_t _reserved0: 16; /*!< bit: 0..15 Reserved */
|
||||
uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */
|
||||
uint32_t _reserved1: 7; /*!< bit: 20..26 Reserved */
|
||||
uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */
|
||||
uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} APSR_Type;
|
||||
|
|
@ -299,8 +299,8 @@ typedef union
|
|||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
|
||||
uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} IPSR_Type;
|
||||
|
|
@ -317,18 +317,18 @@ typedef union
|
|||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:1; /*!< bit: 9 Reserved */
|
||||
uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
|
||||
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
|
||||
uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
|
||||
uint32_t T:1; /*!< bit: 24 Thumb bit */
|
||||
uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
|
||||
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0: 1; /*!< bit: 9 Reserved */
|
||||
uint32_t ICI_IT_1: 6; /*!< bit: 10..15 ICI/IT part 1 */
|
||||
uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */
|
||||
uint32_t _reserved1: 4; /*!< bit: 20..23 Reserved */
|
||||
uint32_t T: 1; /*!< bit: 24 Thumb bit */
|
||||
uint32_t ICI_IT_2: 2; /*!< bit: 25..26 ICI/IT part 2 */
|
||||
uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */
|
||||
uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} xPSR_Type;
|
||||
|
|
@ -372,10 +372,10 @@ typedef union
|
|||
{
|
||||
struct
|
||||
{
|
||||
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
|
||||
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
|
||||
uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
|
||||
uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
|
||||
uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */
|
||||
uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */
|
||||
uint32_t FPCA: 1; /*!< bit: 2 FP extension active flag */
|
||||
uint32_t _reserved0: 29; /*!< bit: 3..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} CONTROL_Type;
|
||||
|
|
@ -1562,8 +1562,8 @@ typedef struct
|
|||
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
|
||||
|
||||
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
|
||||
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
|
||||
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
|
||||
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
|
||||
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
|
||||
#endif
|
||||
|
||||
#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
|
||||
|
|
@ -1596,33 +1596,33 @@ typedef struct
|
|||
*/
|
||||
|
||||
#ifdef CMSIS_NVIC_VIRTUAL
|
||||
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#else
|
||||
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
|
||||
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
|
||||
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
||||
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
||||
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
||||
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||
#define NVIC_GetActive __NVIC_GetActive
|
||||
#define NVIC_SetPriority __NVIC_SetPriority
|
||||
#define NVIC_GetPriority __NVIC_GetPriority
|
||||
#define NVIC_SystemReset __NVIC_SystemReset
|
||||
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
|
||||
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
|
||||
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
||||
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
||||
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
||||
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||
#define NVIC_GetActive __NVIC_GetActive
|
||||
#define NVIC_SetPriority __NVIC_SetPriority
|
||||
#define NVIC_GetPriority __NVIC_GetPriority
|
||||
#define NVIC_SystemReset __NVIC_SystemReset
|
||||
#endif /* CMSIS_NVIC_VIRTUAL */
|
||||
|
||||
#ifdef CMSIS_VECTAB_VIRTUAL
|
||||
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#else
|
||||
#define NVIC_SetVector __NVIC_SetVector
|
||||
#define NVIC_GetVector __NVIC_GetVector
|
||||
#define NVIC_SetVector __NVIC_SetVector
|
||||
#define NVIC_GetVector __NVIC_GetVector
|
||||
#endif /* (CMSIS_VECTAB_VIRTUAL) */
|
||||
|
||||
#define NVIC_USER_IRQ_OFFSET 16
|
||||
|
|
@ -1647,7 +1647,7 @@ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|||
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
|
||||
reg_value = (reg_value |
|
||||
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||||
(PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
|
||||
(PriorityGroupTmp << 8U)); /* Insert write key and priorty group */
|
||||
SCB->AIRCR = reg_value;
|
||||
}
|
||||
|
||||
|
|
@ -1690,11 +1690,11 @@ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
|
|||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
return ((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
return (0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1728,11 +1728,11 @@ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
|||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
return ((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
return (0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1779,11 +1779,11 @@ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
|
|||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
return ((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
return (0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1805,7 +1805,7 @@ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
|||
}
|
||||
else
|
||||
{
|
||||
SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
||||
SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1824,11 +1824,11 @@ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
|||
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
|
||||
return (((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
|
||||
return (((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1844,7 +1844,7 @@ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
|||
\param [in] SubPriority Subpriority value (starting from 0).
|
||||
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
||||
*/
|
||||
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
||||
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
||||
{
|
||||
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||
uint32_t PreemptPriorityBits;
|
||||
|
|
@ -1855,7 +1855,7 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
|
|||
|
||||
return (
|
||||
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
||||
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
||||
((SubPriority & (uint32_t)((1UL << (SubPriorityBits)) - 1UL)))
|
||||
);
|
||||
}
|
||||
|
||||
|
|
@ -1871,7 +1871,7 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
|
|||
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
|
||||
\param [out] pSubPriority Subpriority value (starting from 0).
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
|
||||
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
|
||||
{
|
||||
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||
uint32_t PreemptPriorityBits;
|
||||
|
|
@ -1881,7 +1881,7 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
|
|||
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||
|
||||
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
|
||||
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
|
||||
*pSubPriority = (Priority) & (uint32_t)((1UL << (SubPriorityBits)) - 1UL);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -1926,10 +1926,10 @@ __STATIC_INLINE void __NVIC_SystemReset(void)
|
|||
buffered write are completed before reset */
|
||||
SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||||
(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
|
||||
SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
|
||||
SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
|
||||
__DSB(); /* Ensure completion of memory access */
|
||||
|
||||
for(;;) /* wait until reset */
|
||||
for (;;) /* wait until reset */
|
||||
{
|
||||
__NOP();
|
||||
}
|
||||
|
|
@ -2011,7 +2011,7 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
|||
}
|
||||
|
||||
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
||||
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||
NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
SysTick_CTRL_TICKINT_Msk |
|
||||
|
|
@ -2045,10 +2045,10 @@ extern volatile int32_t ITM_RxBuffer; /*!< External
|
|||
\param [in] ch Character to transmit.
|
||||
\returns Character to transmit.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
|
||||
__STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch)
|
||||
{
|
||||
if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
|
||||
((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
|
||||
((ITM->TER & 1UL) != 0UL)) /* ITM Port #0 enabled */
|
||||
{
|
||||
while (ITM->PORT[0U].u32 == 0UL)
|
||||
{
|
||||
|
|
@ -2066,7 +2066,7 @@ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
|
|||
\return Received character.
|
||||
\return -1 No character pending.
|
||||
*/
|
||||
__STATIC_INLINE int32_t ITM_ReceiveChar (void)
|
||||
__STATIC_INLINE int32_t ITM_ReceiveChar(void)
|
||||
{
|
||||
int32_t ch = -1; /* no character available */
|
||||
|
||||
|
|
@ -2086,7 +2086,7 @@ __STATIC_INLINE int32_t ITM_ReceiveChar (void)
|
|||
\return 0 No character available.
|
||||
\return 1 Character available.
|
||||
*/
|
||||
__STATIC_INLINE int32_t ITM_CheckChar (void)
|
||||
__STATIC_INLINE int32_t ITM_CheckChar(void)
|
||||
{
|
||||
|
||||
if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
|
||||
|
|
|
|||
|
|
@ -95,7 +95,8 @@
|
|||
/**
|
||||
* Struct for a single MPU Region
|
||||
*/
|
||||
typedef struct _ARM_MPU_Region_t {
|
||||
typedef struct _ARM_MPU_Region_t
|
||||
{
|
||||
uint32_t RBAR; //!< The region base address register value (RBAR)
|
||||
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
|
||||
} ARM_MPU_Region_t;
|
||||
|
|
@ -161,7 +162,7 @@ __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t r
|
|||
* \param src Source data is copied from.
|
||||
* \param len Amount of data words to be copied.
|
||||
*/
|
||||
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||
__STATIC_INLINE void orderedCpy(volatile uint32_t *dst, const uint32_t *__RESTRICT src, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0u; i < len; ++i)
|
||||
|
|
@ -174,9 +175,9 @@ __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRI
|
|||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const *table, uint32_t cnt)
|
||||
{
|
||||
orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*sizeof(ARM_MPU_Region_t)/4u);
|
||||
orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt * sizeof(ARM_MPU_Region_t) / 4u);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -33,9 +33,9 @@
|
|||
#include <stdint.h>
|
||||
|
||||
#ifndef TZ_MODULEID_T
|
||||
#define TZ_MODULEID_T
|
||||
/// \details Data type that identifies secure software modules called by a process.
|
||||
typedef uint32_t TZ_ModuleId_t;
|
||||
#define TZ_MODULEID_T
|
||||
/// \details Data type that identifies secure software modules called by a process.
|
||||
typedef uint32_t TZ_ModuleId_t;
|
||||
#endif
|
||||
|
||||
/// \details TZ Memory ID identifies an allocated memory slot.
|
||||
|
|
@ -43,27 +43,27 @@ typedef uint32_t TZ_MemoryId_t;
|
|||
|
||||
/// Initialize secure context memory system
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_InitContextSystem_S (void);
|
||||
uint32_t TZ_InitContextSystem_S(void);
|
||||
|
||||
/// Allocate context memory for calling secure software modules in TrustZone
|
||||
/// \param[in] module identifies software modules called from non-secure mode
|
||||
/// \return value != 0 id TrustZone memory slot identifier
|
||||
/// \return value 0 no memory available or internal error
|
||||
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
|
||||
TZ_MemoryId_t TZ_AllocModuleContext_S(TZ_ModuleId_t module);
|
||||
|
||||
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
|
||||
uint32_t TZ_FreeModuleContext_S(TZ_MemoryId_t id);
|
||||
|
||||
/// Load secure context (called on RTOS thread context switch)
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
|
||||
uint32_t TZ_LoadContext_S(TZ_MemoryId_t id);
|
||||
|
||||
/// Store secure context (called on RTOS thread context switch)
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
|
||||
uint32_t TZ_StoreContext_S(TZ_MemoryId_t id);
|
||||
|
||||
#endif // TZ_CONTEXT_H
|
||||
|
|
|
|||
|
|
@ -57,7 +57,7 @@
|
|||
/* Re-defined staff for various compiler */
|
||||
/*----------------------------------------------------------------------------------------*/
|
||||
#ifdef __ICCARM__
|
||||
#define __inline inline
|
||||
#define __inline inline
|
||||
#endif
|
||||
|
||||
|
||||
|
|
@ -70,21 +70,21 @@
|
|||
//#define DUMP_DESCRIPTOR /* dump descriptors */
|
||||
|
||||
#ifdef ENABLE_ERROR_MSG
|
||||
#define USB_error rt_kprintf
|
||||
#define USB_error rt_kprintf
|
||||
#else
|
||||
#define USB_error(...)
|
||||
#define USB_error(...)
|
||||
#endif
|
||||
|
||||
#ifdef ENABLE_DEBUG_MSG
|
||||
#define USB_debug rt_kprintf
|
||||
#ifdef ENABLE_VERBOSE_DEBUG
|
||||
#define USB_vdebug rt_kprintf
|
||||
#define USB_debug rt_kprintf
|
||||
#ifdef ENABLE_VERBOSE_DEBUG
|
||||
#define USB_vdebug rt_kprintf
|
||||
#else
|
||||
#define USB_vdebug(...)
|
||||
#endif
|
||||
#else
|
||||
#define USB_vdebug(...)
|
||||
#endif
|
||||
#else
|
||||
#define USB_debug(...)
|
||||
#define USB_vdebug(...)
|
||||
#define USB_debug(...)
|
||||
#define USB_vdebug(...)
|
||||
#endif
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -51,7 +51,7 @@ extern "C"
|
|||
#define USBH_ERR_DISCONNECTED -259 /*!< USB device was disconnected */
|
||||
|
||||
#define USBH_ERR_TRANSACTION -271 /*!< USB transaction timeout, CRC, Bad PID, etc. */
|
||||
#define USBH_ERR_BABBLE_DETECTED -272 /*!< A ¡§babble¡¨ is detected during the transaction */
|
||||
#define USBH_ERR_BABBLE_DETECTED -272 /*!< A 'babble' is detected during the transaction */
|
||||
#define USBH_ERR_DATA_BUFF -274 /*!< Data buffer overrun or underrun */
|
||||
|
||||
#define USBH_ERR_CC_NO_ERR -280 /*!< OHCI CC code - no error */
|
||||
|
|
@ -145,7 +145,7 @@ extern int usbh_polling_root_hubs(void);
|
|||
extern void usbh_install_conn_callback(CONN_FUNC *conn_func, CONN_FUNC *disconn_func);
|
||||
extern void usbh_suspend(void);
|
||||
extern void usbh_resume(void);
|
||||
extern struct udev_t * usbh_find_device(char *hub_id, int port);
|
||||
extern struct udev_t *usbh_find_device(char *hub_id, int port);
|
||||
/**
|
||||
* @brief A function return current tick count.
|
||||
* @return Current tick.
|
||||
|
|
@ -161,7 +161,7 @@ extern uint32_t usbh_tick_from_millisecond(uint32_t msec); /* This function mu
|
|||
/* */
|
||||
/*------------------------------------------------------------------*/
|
||||
extern void usbh_cdc_init(void);
|
||||
extern struct cdc_dev_t * usbh_cdc_get_device_list(void);
|
||||
extern struct cdc_dev_t *usbh_cdc_get_device_list(void);
|
||||
/// @cond HIDDEN_SYMBOLS
|
||||
extern int32_t usbh_cdc_get_line_coding(struct cdc_dev_t *cdev, struct line_coding_t *line_code);
|
||||
extern int32_t usbh_cdc_set_line_coding(struct cdc_dev_t *cdev, struct line_coding_t *line_code);
|
||||
|
|
@ -178,7 +178,7 @@ extern int32_t usbh_cdc_send_data(struct cdc_dev_t *cdev, uint8_t *buff, int bu
|
|||
/* */
|
||||
/*------------------------------------------------------------------*/
|
||||
extern void usbh_hid_init(void);
|
||||
extern struct usbhid_dev * usbh_hid_get_device_list(void);
|
||||
extern struct usbhid_dev *usbh_hid_get_device_list(void);
|
||||
extern int32_t usbh_hid_get_report_descriptor(struct usbhid_dev *hdev, uint8_t *desc_buf, int buf_max_len);
|
||||
extern int32_t usbh_hid_get_report(struct usbhid_dev *hdev, int rtp_typ, int rtp_id, uint8_t *data, int len);
|
||||
extern int32_t usbh_hid_set_report(struct usbhid_dev *hdev, int rtp_typ, int rtp_id, uint8_t *data, int len);
|
||||
|
|
@ -211,7 +211,7 @@ extern int usbh_umas_reset_disk(int drv_no);
|
|||
/*------------------------------------------------------------------*/
|
||||
extern void usbh_uac_init(void);
|
||||
extern int usbh_uac_open(struct uac_dev_t *audev);
|
||||
extern struct uac_dev_t * usbh_uac_get_device_list(void);
|
||||
extern struct uac_dev_t *usbh_uac_get_device_list(void);
|
||||
extern int usbh_uac_get_channel_number(struct uac_dev_t *audev, uint8_t target);
|
||||
extern int usbh_uac_get_bit_resolution(struct uac_dev_t *audev, uint8_t target, uint8_t *byte_cnt);
|
||||
extern int usbh_uac_get_sampling_rate(struct uac_dev_t *audev, uint8_t target, uint32_t *srate_list, int max_cnt, uint8_t *type);
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@
|
|||
|
||||
USBH_T *_ohci;
|
||||
|
||||
static UDEV_DRV_T * _drivers[MAX_UDEV_DRIVER];
|
||||
static UDEV_DRV_T *_drivers[MAX_UDEV_DRIVER];
|
||||
static CONN_FUNC *g_conn_func, *g_disconn_func;
|
||||
|
||||
/// @endcond HIDDEN_SYMBOLS
|
||||
|
|
@ -34,7 +34,7 @@ static CONN_FUNC *g_conn_func, *g_disconn_func;
|
|||
*/
|
||||
void usbh_core_init()
|
||||
{
|
||||
if((__PC() & NS_OFFSET) == NS_OFFSET)
|
||||
if ((__PC() & NS_OFFSET) == NS_OFFSET)
|
||||
{
|
||||
_ohci = USBH_NS;
|
||||
}
|
||||
|
|
@ -50,7 +50,7 @@ void usbh_core_init()
|
|||
g_conn_func = NULL;
|
||||
g_disconn_func = NULL;
|
||||
|
||||
// usbh_hub_init();
|
||||
// usbh_hub_init();
|
||||
|
||||
usbh_memory_init();
|
||||
|
||||
|
|
@ -153,7 +153,7 @@ int usbh_reset_port(UDEV_T *udev)
|
|||
if (udev->parent == NULL)
|
||||
{
|
||||
if (udev->hc_driver)
|
||||
return udev->hc_driver->rthub_port_reset(udev->port_num-1);
|
||||
return udev->hc_driver->rthub_port_reset(udev->port_num - 1);
|
||||
else
|
||||
return USBH_ERR_NOT_FOUND;
|
||||
}
|
||||
|
|
@ -171,7 +171,7 @@ int usbh_reset_port(UDEV_T *udev)
|
|||
*/
|
||||
int usbh_quit_utr(UTR_T *utr)
|
||||
{
|
||||
if(!utr || !utr->udev)
|
||||
if (!utr || !utr->udev)
|
||||
return USBH_ERR_NOT_FOUND;
|
||||
|
||||
return utr->udev->hc_driver->quit_xfer(utr, NULL);
|
||||
|
|
|
|||
|
|
@ -46,34 +46,34 @@
|
|||
#include "arm_math.h"
|
||||
#include "arm_common_tables.h"
|
||||
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
|
||||
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
|
||||
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
|
||||
|
||||
#endif
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -10,7 +10,7 @@
|
|||
#define __SYS_REG_H__
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma anon_unions
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
||||
/**
|
||||
|
|
@ -3656,7 +3656,7 @@ typedef struct
|
|||
/**@}*/ /* end of REGISTER group */
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma no_anon_unions
|
||||
#pragma no_anon_unions
|
||||
#endif
|
||||
|
||||
#endif /* __SYS_REG_H__ */
|
||||
|
|
|
|||
|
|
@ -617,7 +617,7 @@ __STATIC_INLINE void CLK_SysTickDelay(uint32_t us)
|
|||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
|
||||
|
||||
/* Waiting for down-count to zero */
|
||||
while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL)
|
||||
while ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL)
|
||||
{
|
||||
}
|
||||
|
||||
|
|
@ -642,7 +642,7 @@ __STATIC_INLINE void CLK_SysTickLongDelay(uint32_t us)
|
|||
|
||||
do
|
||||
{
|
||||
if(us > delay)
|
||||
if (us > delay)
|
||||
{
|
||||
us -= delay;
|
||||
}
|
||||
|
|
@ -657,13 +657,13 @@ __STATIC_INLINE void CLK_SysTickLongDelay(uint32_t us)
|
|||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
|
||||
|
||||
/* Waiting for down-count to zero */
|
||||
while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL);
|
||||
while ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL);
|
||||
|
||||
/* Disable SysTick counter */
|
||||
SysTick->CTRL = 0UL;
|
||||
|
||||
}
|
||||
while(us > 0UL);
|
||||
while (us > 0UL);
|
||||
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -16,9 +16,9 @@
|
|||
#define ENABLE_DEBUG 0
|
||||
|
||||
#if ENABLE_DEBUG
|
||||
#define CRPT_DBGMSG printf
|
||||
#define CRPT_DBGMSG printf
|
||||
#else
|
||||
#define CRPT_DBGMSG(...) do { } while (0) /* disable debug */
|
||||
#define CRPT_DBGMSG(...) do { } while (0) /* disable debug */
|
||||
#endif
|
||||
|
||||
/** @endcond HIDDEN_SYMBOLS */
|
||||
|
|
@ -178,7 +178,7 @@ void AES_SetKey(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32Keys[], uint32_t
|
|||
uint32_t i, wcnt, key_reg_addr;
|
||||
|
||||
key_reg_addr = (uint32_t)&crpt->AES0_KEY[0] + (u32Channel * 0x3CUL);
|
||||
wcnt = 4UL + u32KeySize*2UL;
|
||||
wcnt = 4UL + u32KeySize * 2UL;
|
||||
|
||||
for (i = 0U; i < wcnt; i++)
|
||||
{
|
||||
|
|
@ -379,9 +379,9 @@ void SHA_Open(CRPT_T *crpt, uint32_t u32OpMode, uint32_t u32SwapType, uint32_t h
|
|||
crpt->HMAC_KEYCNT = hmac_key_len;
|
||||
|
||||
if ((SYS->CSERVER & SYS_CSERVER_VERSION_Msk) == 0x0)
|
||||
crpt->HMAC_CTL |= (1<<4); /* M480MD HMACEN is CRYPTO_HMAC_CTL[4] */
|
||||
crpt->HMAC_CTL |= (1 << 4); /* M480MD HMACEN is CRYPTO_HMAC_CTL[4] */
|
||||
else
|
||||
crpt->HMAC_CTL |= (1<<11); /* M480LD HMACEN is CRYPTO_HMAC_CTL[11] */
|
||||
crpt->HMAC_CTL |= (1 << 11); /* M480LD HMACEN is CRYPTO_HMAC_CTL[11] */
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -447,7 +447,7 @@ void SHA_Read(CRPT_T *crpt, uint32_t u32Digest[])
|
|||
wcnt = 16UL;
|
||||
}
|
||||
|
||||
reg_addr = (uint32_t)&(crpt->HMAC_DGST[0]);
|
||||
reg_addr = (uint32_t) & (crpt->HMAC_DGST[0]);
|
||||
for (i = 0UL; i < wcnt; i++)
|
||||
{
|
||||
u32Digest[i] = inpw(reg_addr);
|
||||
|
|
@ -887,7 +887,7 @@ const ECC_CURVE _Curve[] =
|
|||
static ECC_CURVE *pCurve;
|
||||
static ECC_CURVE Curve_Copy;
|
||||
|
||||
static ECC_CURVE * get_curve(E_ECC_CURVE ecc_curve);
|
||||
static ECC_CURVE *get_curve(E_ECC_CURVE ecc_curve);
|
||||
static int32_t ecc_init_curve(CRPT_T *crpt, E_ECC_CURVE ecc_curve);
|
||||
static void run_ecc_codec(CRPT_T *crpt, uint32_t mode);
|
||||
|
||||
|
|
@ -990,7 +990,7 @@ static void Hex2RegEx(char input[], uint32_t volatile reg[], int shift)
|
|||
*/
|
||||
static char get_Nth_nibble_char(uint32_t val32, uint32_t idx)
|
||||
{
|
||||
return hex_char_tbl[ (val32 >> (idx * 4U)) & 0xfU ];
|
||||
return hex_char_tbl[(val32 >> (idx * 4U)) & 0xfU ];
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -1012,7 +1012,7 @@ static void Reg2Hex(int32_t count, uint32_t volatile reg[], char output[])
|
|||
}
|
||||
}
|
||||
|
||||
static ECC_CURVE * get_curve(E_ECC_CURVE ecc_curve)
|
||||
static ECC_CURVE *get_curve(E_ECC_CURVE ecc_curve)
|
||||
{
|
||||
uint32_t i;
|
||||
ECC_CURVE *ret = NULL;
|
||||
|
|
@ -1108,7 +1108,7 @@ static int ecc_strcmp(char *s1, char *s2)
|
|||
while (*s1 == '0') s1++;
|
||||
while (*s2 == '0') s2++;
|
||||
|
||||
for ( ; *s1 || *s2; s1++, s2++)
|
||||
for (; *s1 || *s2; s1++, s2++)
|
||||
{
|
||||
if ((*s1 >= 'A') && (*s1 <= 'Z'))
|
||||
c1 = *s1 + 32;
|
||||
|
|
@ -1502,7 +1502,7 @@ int32_t ECC_GenerateSignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *messag
|
|||
Reg2Hex(pCurve->Echar, temp_result1, R);
|
||||
|
||||
/*
|
||||
* 4. Compute s = k ? 1 ｝ (e + d ｝ r)(mod n). If s = 0, go to step 2
|
||||
* 4. Compute s = k ? 1 ｝ (e + d ｝ r)(mod n). If s = 0, go to step 2
|
||||
* (1) Write the curve order to N registers according
|
||||
* (2) Write 0x1 to Y1 registers
|
||||
* (3) Write the random integer k to X1 registers according
|
||||
|
|
@ -1732,7 +1732,7 @@ int32_t ECC_VerifySignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message,
|
|||
#endif
|
||||
|
||||
/*
|
||||
* 4. Compute u1 = e ｝ w (mod n) and u2 = r ｝ w (mod n)
|
||||
* 4. Compute u1 = e ｝ w (mod n) and u2 = r ｝ w (mod n)
|
||||
* (1) Write the curve order and curve length to N ,M registers
|
||||
* (2) Write e, w to X1, Y1 registers
|
||||
* (3) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01
|
||||
|
|
@ -1814,7 +1814,7 @@ int32_t ECC_VerifySignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message,
|
|||
#endif
|
||||
|
||||
/*
|
||||
* 5. Compute X・ (x1・, y1・) = u1 * G + u2 * Q
|
||||
* 5. Compute X・ (x1・, y1・) = u1 * G + u2 * Q
|
||||
* (1) Write the curve parameter A, B, N, and curve length M to corresponding registers
|
||||
* (2) Write the point G(x, y) to X1, Y1 registers
|
||||
* (3) Write u1 to K registers
|
||||
|
|
@ -1833,17 +1833,17 @@ int32_t ECC_VerifySignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message,
|
|||
* (16) Set ECCOP(CRPT_ECC_CTL[10:9]) to 10
|
||||
* (17) Set START(CRPT_ECC_CTL[0]) to 1
|
||||
* (18) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
|
||||
* (19) Read X1, Y1 registers to get X・(x1・, y1・)
|
||||
* (19) Read X1, Y1 registers to get X・(x1・, y1・)
|
||||
* (20) Write the curve order and curve length to N ,M registers
|
||||
* (21) Write x1・ to X1 registers
|
||||
* (21) Write x1・ to X1 registers
|
||||
* (22) Write 0x0 to Y1 registers
|
||||
* (23) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01
|
||||
* (24) Set MOPOP(CRPT_ECC_CTL[12:11]) to 10
|
||||
* (25) Set START(CRPT_ECC_CTL[0]) to 1
|
||||
* (26) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
|
||||
* (27) Read X1 registers to get x1・ (mod n)
|
||||
* (27) Read X1 registers to get x1・ (mod n)
|
||||
*
|
||||
* 6. The signature is valid if x1・ = r, otherwise it is invalid
|
||||
* 6. The signature is valid if x1・ = r, otherwise it is invalid
|
||||
*/
|
||||
|
||||
/*
|
||||
|
|
@ -1927,7 +1927,7 @@ int32_t ECC_VerifySignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message,
|
|||
|
||||
run_ecc_codec(crpt, ECCOP_POINT_ADD);
|
||||
|
||||
/* (19) Read X1, Y1 registers to get X・(x1・, y1・) */
|
||||
/* (19) Read X1, Y1 registers to get X・(x1・, y1・) */
|
||||
for (i = 0; i < 18; i++)
|
||||
{
|
||||
temp_x[i] = crpt->ECC_X1[i];
|
||||
|
|
@ -1949,7 +1949,7 @@ int32_t ECC_VerifySignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message,
|
|||
Hex2Reg(pCurve->Eorder, crpt->ECC_N);
|
||||
|
||||
/*
|
||||
* (21) Write x1・ to X1 registers
|
||||
* (21) Write x1・ to X1 registers
|
||||
* (22) Write 0x0 to Y1 registers
|
||||
*/
|
||||
for (i = 0; i < 18; i++)
|
||||
|
|
@ -1967,11 +1967,11 @@ int32_t ECC_VerifySignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message,
|
|||
|
||||
run_ecc_codec(crpt, ECCOP_MODULE | MODOP_ADD);
|
||||
|
||||
/* (27) Read X1 registers to get x1・ (mod n) */
|
||||
/* (27) Read X1 registers to get x1・ (mod n) */
|
||||
Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str);
|
||||
CRPT_DBGMSG("5-(27) x1' (mod n) = %s\n", temp_hex_str);
|
||||
|
||||
/* 6. The signature is valid if x1・ = r, otherwise it is invalid */
|
||||
/* 6. The signature is valid if x1・ = r, otherwise it is invalid */
|
||||
|
||||
/* Compare with test pattern to check if r is correct or not */
|
||||
if (ecc_strcmp(temp_hex_str, R) != 0)
|
||||
|
|
|
|||
|
|
@ -29,7 +29,7 @@
|
|||
#define ENABLE_OHCI /* Enable OHCI host controller */
|
||||
|
||||
#if defined(BSP_USING_HSUSBH)
|
||||
#define ENABLE_EHCI /* Enable EHCI host controller */
|
||||
#define ENABLE_EHCI /* Enable EHCI host controller */
|
||||
#endif
|
||||
|
||||
#define EHCI_PORT_CNT 1 /* Number of EHCI roothub ports */
|
||||
|
|
@ -75,7 +75,7 @@
|
|||
/* Re-defined staff for various compiler */
|
||||
/*----------------------------------------------------------------------------------------*/
|
||||
#ifdef __ICCARM__
|
||||
#define __inline inline
|
||||
#define __inline inline
|
||||
#endif
|
||||
|
||||
|
||||
|
|
@ -88,21 +88,21 @@
|
|||
//#define DUMP_DESCRIPTOR /* dump descriptors */
|
||||
|
||||
#ifdef ENABLE_ERROR_MSG
|
||||
#define USB_error rt_kprintf
|
||||
#define USB_error rt_kprintf
|
||||
#else
|
||||
#define USB_error(...)
|
||||
#define USB_error(...)
|
||||
#endif
|
||||
|
||||
#ifdef ENABLE_DEBUG_MSG
|
||||
#define USB_debug rt_kprintf
|
||||
#ifdef ENABLE_VERBOSE_DEBUG
|
||||
#define USB_vdebug rt_kprintf
|
||||
#define USB_debug rt_kprintf
|
||||
#ifdef ENABLE_VERBOSE_DEBUG
|
||||
#define USB_vdebug rt_kprintf
|
||||
#else
|
||||
#define USB_vdebug(...)
|
||||
#endif
|
||||
#else
|
||||
#define USB_vdebug(...)
|
||||
#endif
|
||||
#else
|
||||
#define USB_debug(...)
|
||||
#define USB_vdebug(...)
|
||||
#define USB_debug(...)
|
||||
#define USB_vdebug(...)
|
||||
#endif
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -51,7 +51,7 @@ extern "C"
|
|||
#define USBH_ERR_DISCONNECTED -259 /*!< USB device was disconnected */
|
||||
|
||||
#define USBH_ERR_TRANSACTION -271 /*!< USB transaction timeout, CRC, Bad PID, etc. */
|
||||
#define USBH_ERR_BABBLE_DETECTED -272 /*!< A ¡§babble¡¨ is detected during the transaction */
|
||||
#define USBH_ERR_BABBLE_DETECTED -272 /*!< A 'babble' is detected during the transaction */
|
||||
#define USBH_ERR_DATA_BUFF -274 /*!< Data buffer overrun or underrun */
|
||||
|
||||
#define USBH_ERR_CC_NO_ERR -280 /*!< OHCI CC code - no error */
|
||||
|
|
@ -145,7 +145,7 @@ extern int usbh_polling_root_hubs(void);
|
|||
extern void usbh_install_conn_callback(CONN_FUNC *conn_func, CONN_FUNC *disconn_func);
|
||||
extern void usbh_suspend(void);
|
||||
extern void usbh_resume(void);
|
||||
extern struct udev_t * usbh_find_device(char *hub_id, int port);
|
||||
extern struct udev_t *usbh_find_device(char *hub_id, int port);
|
||||
|
||||
/**
|
||||
* @brief A function return current tick count.
|
||||
|
|
|
|||
|
|
@ -29,13 +29,13 @@ extern int ehci_iso_xfer(UTR_T *utr); /* EHCI isochronous transfer functio
|
|||
extern int ehci_quit_iso_xfer(UTR_T *utr, EP_INFO_T *ep);
|
||||
|
||||
#ifdef __ICCARM__
|
||||
#pragma data_alignment=4096
|
||||
uint32_t _PFList[FL_SIZE]; /* Periodic frame list (IAR) */
|
||||
#pragma data_alignment=4096
|
||||
uint32_t _PFList[FL_SIZE]; /* Periodic frame list (IAR) */
|
||||
#else
|
||||
uint32_t _PFList[FL_SIZE] __attribute__((aligned(4096))); /* Periodic frame list */
|
||||
uint32_t _PFList[FL_SIZE] __attribute__((aligned(4096))); /* Periodic frame list */
|
||||
#endif
|
||||
|
||||
QH_T * _Iqh[NUM_IQH];
|
||||
QH_T *_Iqh[NUM_IQH];
|
||||
|
||||
|
||||
#ifdef ENABLE_ERROR_MSG
|
||||
|
|
@ -65,7 +65,7 @@ void dump_ehci_qtd(qTD_T *qtd)
|
|||
USB_debug(" [qTD] - 0x%08x\n", (int)qtd);
|
||||
USB_debug(" 0x%08x (Next qtd Pointer)\n", qtd->Next_qTD);
|
||||
USB_debug(" 0x%08x (Alternate Next qtd Pointer)\n", qtd->Alt_Next_qTD);
|
||||
USB_debug(" 0x%08x (qtd Token) PID: %s, Bytes: %d, IOC: %d\n", qtd->Token, (((qtd->Token>>8)&0x3)==0) ? "OUT" : ((((qtd->Token>>8)&0x3)==1) ? "IN" : "SETUP"), (qtd->Token>>16)&0x7FFF, (qtd->Token>>15)&0x1);
|
||||
USB_debug(" 0x%08x (qtd Token) PID: %s, Bytes: %d, IOC: %d\n", qtd->Token, (((qtd->Token >> 8) & 0x3) == 0) ? "OUT" : ((((qtd->Token >> 8) & 0x3) == 1) ? "IN" : "SETUP"), (qtd->Token >> 16) & 0x7FFF, (qtd->Token >> 15) & 0x1);
|
||||
USB_debug(" 0x%08x (Buffer Pointer (page 0))\n", qtd->Bptr[0]);
|
||||
//USB_debug(" 0x%08x (Buffer Pointer (page 1))\n", qtd->Bptr[1]);
|
||||
//USB_debug(" 0x%08x (Buffer Pointer (page 2))\n", qtd->Bptr[2]);
|
||||
|
|
@ -84,7 +84,7 @@ void dump_ehci_asynclist(void)
|
|||
{
|
||||
USB_debug("[QH] - 0x%08x\n", (int)qh);
|
||||
USB_debug(" 0x%08x (Queue Head Horizontal Link Pointer, Queue Head DWord 0)\n", qh->HLink);
|
||||
USB_debug(" 0x%08x (Endpoint Characteristics) DevAddr: %d, EP: 0x%x, PktSz: %d, Speed: %s\n", qh->Chrst, qh->Chrst&0x7F, (qh->Chrst>>8)&0xF, (qh->Chrst>>16)&0x7FF, ((qh->Chrst>>12)&0x3 == 0) ? "Full" : (((qh->Chrst>>12)&0x3 == 1) ? "Low" : "High"));
|
||||
USB_debug(" 0x%08x (Endpoint Characteristics) DevAddr: %d, EP: 0x%x, PktSz: %d, Speed: %s\n", qh->Chrst, qh->Chrst & 0x7F, (qh->Chrst >> 8) & 0xF, (qh->Chrst >> 16) & 0x7FF, ((qh->Chrst >> 12) & 0x3 == 0) ? "Full" : (((qh->Chrst >> 12) & 0x3 == 1) ? "Low" : "High"));
|
||||
USB_debug(" 0x%08x (Endpoint Capabilities: Queue Head DWord 2)\n", qh->Cap);
|
||||
USB_debug(" 0x%08x (Current qtd Pointer)\n", qh->Curr_qTD);
|
||||
USB_debug(" --- Overlay Area ---\n");
|
||||
|
|
@ -122,7 +122,7 @@ void dump_ehci_asynclist_simple(void)
|
|||
|
||||
void dump_ehci_period_frame_list_simple(void)
|
||||
{
|
||||
QH_T *qh = _Iqh[NUM_IQH-1];
|
||||
QH_T *qh = _Iqh[NUM_IQH - 1];
|
||||
|
||||
USB_debug(">>> EHCI period frame list simple <<<\n");
|
||||
USB_debug("[FList] => ");
|
||||
|
|
@ -165,7 +165,7 @@ static void init_periodic_frame_list()
|
|||
|
||||
iso_ep_list = NULL;
|
||||
|
||||
for (i = NUM_IQH-1; i >= 0; i--) /* interval = i^2 */
|
||||
for (i = NUM_IQH - 1; i >= 0; i--) /* interval = i^2 */
|
||||
{
|
||||
_Iqh[i] = alloc_ehci_QH();
|
||||
|
||||
|
|
@ -204,19 +204,19 @@ static void init_periodic_frame_list()
|
|||
}
|
||||
}
|
||||
|
||||
static QH_T * get_int_tree_head_node(int interval)
|
||||
static QH_T *get_int_tree_head_node(int interval)
|
||||
{
|
||||
int i;
|
||||
|
||||
interval /= 8; /* each frame list entry for 8 micro-frame */
|
||||
|
||||
for (i = 0; i < NUM_IQH-1; i++)
|
||||
for (i = 0; i < NUM_IQH - 1; i++)
|
||||
{
|
||||
interval >>= 1;
|
||||
if (interval == 0)
|
||||
return _Iqh[i];
|
||||
}
|
||||
return _Iqh[NUM_IQH-1];
|
||||
return _Iqh[NUM_IQH - 1];
|
||||
}
|
||||
|
||||
static int make_int_s_mask(int bInterval)
|
||||
|
|
@ -245,7 +245,7 @@ static int make_int_s_mask(int bInterval)
|
|||
|
||||
static int ehci_init(void)
|
||||
{
|
||||
int timeout = 250*1000; /* EHCI reset time-out 250 ms */
|
||||
int timeout = 250 * 1000; /* EHCI reset time-out 250 ms */
|
||||
|
||||
/*------------------------------------------------------------------------------------*/
|
||||
/* Reset EHCI host controller */
|
||||
|
|
@ -283,11 +283,11 @@ static int ehci_init(void)
|
|||
/* Initialize periodic list */
|
||||
/*------------------------------------------------------------------------------------*/
|
||||
if (FL_SIZE == 256)
|
||||
_ehci->UCMDR |= (0x2<<HSUSBH_UCMDR_FLSZ_Pos);
|
||||
_ehci->UCMDR |= (0x2 << HSUSBH_UCMDR_FLSZ_Pos);
|
||||
else if (FL_SIZE == 512)
|
||||
_ehci->UCMDR |= (0x1<<HSUSBH_UCMDR_FLSZ_Pos);
|
||||
_ehci->UCMDR |= (0x1 << HSUSBH_UCMDR_FLSZ_Pos);
|
||||
else if (FL_SIZE == 1024)
|
||||
_ehci->UCMDR |= (0x0<<HSUSBH_UCMDR_FLSZ_Pos);
|
||||
_ehci->UCMDR |= (0x0 << HSUSBH_UCMDR_FLSZ_Pos);
|
||||
else
|
||||
return USBH_ERR_EHCI_INIT; /* Invalid FL_SIZE setting! */
|
||||
|
||||
|
|
@ -371,7 +371,7 @@ static void move_qh_to_remove_list(QH_T *qh)
|
|||
/*------------------------------------------------------------------------------------*/
|
||||
/* Search periodic frame list and remove qh if found in list. */
|
||||
/*------------------------------------------------------------------------------------*/
|
||||
q = _Iqh[NUM_IQH-1];
|
||||
q = _Iqh[NUM_IQH - 1];
|
||||
while (q->HLink != QH_HLNK_END)
|
||||
{
|
||||
if (QH_PTR(q->HLink) == qh)
|
||||
|
|
@ -508,7 +508,7 @@ static int ehci_ctrl_xfer(UTR_T *utr)
|
|||
|
||||
if (utr->data_len > 0)
|
||||
{
|
||||
if (((uint32_t)utr->buff + utr->data_len) > (((uint32_t)utr->buff & ~0xFFF)+0x5000))
|
||||
if (((uint32_t)utr->buff + utr->data_len) > (((uint32_t)utr->buff & ~0xFFF) + 0x5000))
|
||||
return USBH_ERR_BUFF_OVERRUN;
|
||||
}
|
||||
|
||||
|
|
@ -918,7 +918,7 @@ static int visit_qtd(qTD_T *qtd)
|
|||
static void scan_asynchronous_list()
|
||||
{
|
||||
QH_T *qh, *qh_tmp;
|
||||
qTD_T *q_pre=NULL, *qtd, *qtd_tmp;
|
||||
qTD_T *q_pre = NULL, *qtd, *qtd_tmp;
|
||||
UTR_T *utr;
|
||||
|
||||
qh = QH_PTR(_H_qh->HLink);
|
||||
|
|
@ -982,7 +982,7 @@ static void scan_periodic_frame_list()
|
|||
/*------------------------------------------------------------------------------------*/
|
||||
/* Scan interrupt frame list */
|
||||
/*------------------------------------------------------------------------------------*/
|
||||
qh = _Iqh[NUM_IQH-1];
|
||||
qh = _Iqh[NUM_IQH - 1];
|
||||
while (qh != NULL)
|
||||
{
|
||||
qtd = qh->qtd_list;
|
||||
|
|
@ -1095,7 +1095,7 @@ void iaad_remove_qh()
|
|||
/*------------------------------------------------------------------------------------*/
|
||||
/* Free all qTD in done_list of each QH of periodic frame list */
|
||||
/*------------------------------------------------------------------------------------*/
|
||||
qh = _Iqh[NUM_IQH-1];
|
||||
qh = _Iqh[NUM_IQH - 1];
|
||||
while (qh != NULL)
|
||||
{
|
||||
while (qh->done_list) /* we can free the qTDs now */
|
||||
|
|
@ -1138,7 +1138,7 @@ void EHCI_IRQHandler(void)
|
|||
}
|
||||
}
|
||||
|
||||
static UDEV_T * ehci_find_device_by_port(int port)
|
||||
static UDEV_T *ehci_find_device_by_port(int port)
|
||||
{
|
||||
UDEV_T *udev;
|
||||
|
||||
|
|
@ -1165,12 +1165,12 @@ static int ehci_rh_port_reset(int port)
|
|||
_ehci->UPSCR[port] = (_ehci->UPSCR[port] | HSUSBH_UPSCR_PRST_Msk) & ~HSUSBH_UPSCR_PE_Msk;
|
||||
|
||||
t0 = usbh_get_ticks();
|
||||
while (usbh_get_ticks() - t0 < (reset_time)+1) ; /* wait at least 50 ms */
|
||||
while (usbh_get_ticks() - t0 < (reset_time) + 1) ; /* wait at least 50 ms */
|
||||
|
||||
_ehci->UPSCR[port] &= ~HSUSBH_UPSCR_PRST_Msk;
|
||||
|
||||
t0 = usbh_get_ticks();
|
||||
while (usbh_get_ticks() - t0 < (reset_time)+1)
|
||||
while (usbh_get_ticks() - t0 < (reset_time) + 1)
|
||||
{
|
||||
if (!(_ehci->UPSCR[port] & HSUSBH_UPSCR_CCS_Msk) ||
|
||||
((_ehci->UPSCR[port] & (HSUSBH_UPSCR_CCS_Msk | HSUSBH_UPSCR_PE_Msk)) == (HSUSBH_UPSCR_CCS_Msk | HSUSBH_UPSCR_PE_Msk)))
|
||||
|
|
@ -1179,7 +1179,7 @@ static int ehci_rh_port_reset(int port)
|
|||
reset_time += PORT_RESET_RETRY_INC_MS;
|
||||
}
|
||||
|
||||
USB_debug("EHCI port %d - port reset failed!\n", port+1);
|
||||
USB_debug("EHCI port %d - port reset failed!\n", port + 1);
|
||||
return USBH_ERR_PORT_RESET;
|
||||
|
||||
port_reset_done:
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@
|
|||
USBH_T *_ohci;
|
||||
HSUSBH_T *_ehci;
|
||||
|
||||
static UDEV_DRV_T * _drivers[MAX_UDEV_DRIVER];
|
||||
static UDEV_DRV_T *_drivers[MAX_UDEV_DRIVER];
|
||||
static CONN_FUNC *g_conn_func, *g_disconn_func;
|
||||
|
||||
/**
|
||||
|
|
@ -172,7 +172,7 @@ int usbh_reset_port(UDEV_T *udev)
|
|||
if (udev->parent == NULL)
|
||||
{
|
||||
if (udev->hc_driver)
|
||||
return udev->hc_driver->rthub_port_reset(udev->port_num-1);
|
||||
return udev->hc_driver->rthub_port_reset(udev->port_num - 1);
|
||||
else
|
||||
return USBH_ERR_NOT_FOUND;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -267,7 +267,7 @@ void CAP_Close(void)
|
|||
{
|
||||
// 1. Disable IP's interrupt
|
||||
sysDisableInterrupt(CAP_IRQn);
|
||||
// 2. Disable IP’s clock
|
||||
// 2. Disable IP's clock
|
||||
outp32(REG_CLK_HCLKEN, inp32(REG_CLK_HCLKEN) & ~(0x1 << 25));
|
||||
CAP_Reset();
|
||||
outp32(REG_CLK_HCLKEN, inp32(REG_CLK_HCLKEN) & ~(0x1 << 26));
|
||||
|
|
|
|||
|
|
@ -53,7 +53,7 @@ extern "C"
|
|||
#define USBH_ERR_DISCONNECTED -259 /*!< USB device was disconnected */
|
||||
|
||||
#define USBH_ERR_TRANSACTION -271 /*!< USB transaction timeout, CRC, Bad PID, etc. */
|
||||
#define USBH_ERR_BABBLE_DETECTED -272 /*!< A ¡§babble¡¨ is detected during the transaction */
|
||||
#define USBH_ERR_BABBLE_DETECTED -272 /*!< A 'babble' is detected during the transaction */
|
||||
#define USBH_ERR_DATA_BUFF -274 /*!< Data buffer overrun or underrun */
|
||||
|
||||
#define USBH_ERR_CC_NO_ERR -280 /*!< OHCI CC code - no error */
|
||||
|
|
|
|||
|
|
@ -1372,7 +1372,7 @@ int32_t ECC_GenerateSignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *messag
|
|||
Reg2Hex(pCurve->Echar, temp_result1, R);
|
||||
|
||||
/*
|
||||
* 4. Compute s = k ? 1 ｝ (e + d ｝ r)(mod n). If s = 0, go to step 2
|
||||
* 4. Compute s = k ? 1 * (e + d * r)(mod n). If s = 0, go to step 2
|
||||
* (1) Write the curve order to N registers according
|
||||
* (2) Write 0x1 to Y1 registers
|
||||
* (3) Write the random integer k to X1 registers according
|
||||
|
|
@ -1602,7 +1602,7 @@ int32_t ECC_VerifySignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message,
|
|||
#endif
|
||||
|
||||
/*
|
||||
* 4. Compute u1 = e ｝ w (mod n) and u2 = r ｝ w (mod n)
|
||||
* 4. Compute u1 = e * w (mod n) and u2 = r * w (mod n)
|
||||
* (1) Write the curve order and curve length to N ,M registers
|
||||
* (2) Write e, w to X1, Y1 registers
|
||||
* (3) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01
|
||||
|
|
@ -1684,7 +1684,7 @@ int32_t ECC_VerifySignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message,
|
|||
#endif
|
||||
|
||||
/*
|
||||
* 5. Compute X・ (x1・, y1・) = u1 * G + u2 * Q
|
||||
* 5. Compute X' (x1' y1') = u1 * G + u2 * Q
|
||||
* (1) Write the curve parameter A, B, N, and curve length M to corresponding registers
|
||||
* (2) Write the point G(x, y) to X1, Y1 registers
|
||||
* (3) Write u1 to K registers
|
||||
|
|
@ -1703,17 +1703,17 @@ int32_t ECC_VerifySignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message,
|
|||
* (16) Set ECCOP(CRPT_ECC_CTL[10:9]) to 10
|
||||
* (17) Set START(CRPT_ECC_CTL[0]) to 1
|
||||
* (18) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
|
||||
* (19) Read X1, Y1 registers to get X・(x1・, y1・)
|
||||
* (19) Read X1, Y1 registers to get X('x1', y1')
|
||||
* (20) Write the curve order and curve length to N ,M registers
|
||||
* (21) Write x1・ to X1 registers
|
||||
* (21) Write x1' to X1 registers
|
||||
* (22) Write 0x0 to Y1 registers
|
||||
* (23) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01
|
||||
* (24) Set MOPOP(CRPT_ECC_CTL[12:11]) to 10
|
||||
* (25) Set START(CRPT_ECC_CTL[0]) to 1
|
||||
* (26) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
|
||||
* (27) Read X1 registers to get x1・ (mod n)
|
||||
* (27) Read X1 registers to get x1' (mod n)
|
||||
*
|
||||
* 6. The signature is valid if x1・ = r, otherwise it is invalid
|
||||
* 6. The signature is valid if x1' = r, otherwise it is invalid
|
||||
*/
|
||||
|
||||
/*
|
||||
|
|
@ -1797,7 +1797,7 @@ int32_t ECC_VerifySignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message,
|
|||
|
||||
run_ecc_codec(crpt, ECCOP_POINT_ADD);
|
||||
|
||||
/* (19) Read X1, Y1 registers to get X・(x1・, y1・) */
|
||||
/* (19) Read X1, Y1 registers to get X'(x1' y1') */
|
||||
for (i = 0; i < 18; i++)
|
||||
{
|
||||
temp_x[i] = crpt->ECC_X1[i];
|
||||
|
|
@ -1819,7 +1819,7 @@ int32_t ECC_VerifySignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message,
|
|||
Hex2Reg(pCurve->Eorder, crpt->ECC_N);
|
||||
|
||||
/*
|
||||
* (21) Write x1・ to X1 registers
|
||||
* (21) Write x1' to X1 registers
|
||||
* (22) Write 0x0 to Y1 registers
|
||||
*/
|
||||
for (i = 0; i < 18; i++)
|
||||
|
|
@ -1837,11 +1837,11 @@ int32_t ECC_VerifySignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message,
|
|||
|
||||
run_ecc_codec(crpt, ECCOP_MODULE | MODOP_ADD);
|
||||
|
||||
/* (27) Read X1 registers to get x1・ (mod n) */
|
||||
/* (27) Read X1 registers to get x1' (mod n) */
|
||||
Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str);
|
||||
CRPT_DBGMSG("5-(27) x1' (mod n) = %s\n", temp_hex_str);
|
||||
|
||||
/* 6. The signature is valid if x1・ = r, otherwise it is invalid */
|
||||
/* 6. The signature is valid if x1' = r, otherwise it is invalid */
|
||||
|
||||
/* Compare with test pattern to check if r is correct or not */
|
||||
if (ecc_strcmp(temp_hex_str, R) != 0)
|
||||
|
|
|
|||
|
|
@ -53,7 +53,7 @@ extern "C"
|
|||
#define USBH_ERR_DISCONNECTED -259 /*!< USB device was disconnected */
|
||||
|
||||
#define USBH_ERR_TRANSACTION -271 /*!< USB transaction timeout, CRC, Bad PID, etc. */
|
||||
#define USBH_ERR_BABBLE_DETECTED -272 /*!< A ¡§babble¡¨ is detected during the transaction */
|
||||
#define USBH_ERR_BABBLE_DETECTED -272 /*!< A 'babble' is detected during the transaction */
|
||||
#define USBH_ERR_DATA_BUFF -274 /*!< Data buffer overrun or underrun */
|
||||
|
||||
#define USBH_ERR_CC_NO_ERR -280 /*!< OHCI CC code - no error */
|
||||
|
|
|
|||
|
|
@ -1160,14 +1160,14 @@ void nutool_modclkcfg_init_base(void)
|
|||
{
|
||||
/* LXT source from external LXT */
|
||||
CLK_EnableModuleClock(RTC_MODULE);
|
||||
RTC->LXTCTL &= ~(RTC_LXTCTL_LIRC32KEN_Msk|RTC_LXTCTL_C32KSEL_Msk);
|
||||
RTC->LXTCTL &= ~(RTC_LXTCTL_LIRC32KEN_Msk | RTC_LXTCTL_C32KSEL_Msk);
|
||||
CLK_DisableModuleClock(RTC_MODULE);
|
||||
|
||||
/* Enable clock source */
|
||||
CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk|CLK_PWRCTL_LXTEN_Msk|CLK_PWRCTL_HXTEN_Msk|CLK_PWRCTL_HIRC48EN_Msk|CLK_PWRCTL_MIRCEN_Msk);
|
||||
CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk | CLK_PWRCTL_LXTEN_Msk | CLK_PWRCTL_HXTEN_Msk | CLK_PWRCTL_HIRC48EN_Msk | CLK_PWRCTL_MIRCEN_Msk);
|
||||
|
||||
/* Waiting for clock source ready */
|
||||
CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk|CLK_STATUS_LXTSTB_Msk|CLK_STATUS_HXTSTB_Msk|CLK_STATUS_HIRC48STB_Msk|CLK_STATUS_MIRCSTB_Msk);
|
||||
CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk | CLK_STATUS_LXTSTB_Msk | CLK_STATUS_HXTSTB_Msk | CLK_STATUS_HIRC48STB_Msk | CLK_STATUS_MIRCSTB_Msk);
|
||||
|
||||
/* Disable PLL first to avoid unstable when setting PLL */
|
||||
CLK_DisablePLL();
|
||||
|
|
|
|||
|
|
@ -353,7 +353,7 @@ void pincfg_init_slcd(void)
|
|||
SYS->GPA_MFPL = (SYS->GPA_MFPL &
|
||||
~(SYS_GPA_MFPL_PA0MFP_Msk | SYS_GPA_MFPL_PA1MFP_Msk | SYS_GPA_MFPL_PA2MFP_Msk | SYS_GPA_MFPL_PA3MFP_Msk |
|
||||
SYS_GPA_MFPL_PA4MFP_Msk | SYS_GPA_MFPL_PA5MFP_Msk)) |
|
||||
(LCD_SEG24_PA0 | LCD_SEG25_PA1 | LCD_SEG26_PA2 | LCD_SEG27_PA3 | LCD_SEG28_PA4 |LCD_SEG29_PA5);
|
||||
(LCD_SEG24_PA0 | LCD_SEG25_PA1 | LCD_SEG26_PA2 | LCD_SEG27_PA3 | LCD_SEG28_PA4 | LCD_SEG29_PA5);
|
||||
/* SEG 30~32 */
|
||||
SYS->GPE_MFPH = (SYS->GPE_MFPH & ~(SYS_GPE_MFPH_PE10MFP_Msk | SYS_GPE_MFPH_PE9MFP_Msk | SYS_GPE_MFPH_PE8MFP_Msk)) |
|
||||
(LCD_SEG30_PE10 | LCD_SEG31_PE9 | LCD_SEG32_PE8);
|
||||
|
|
|
|||
Loading…
Reference in New Issue