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This commit is contained in:
Huang bo 2021-11-17 18:31:58 +08:00
parent 456492e7ea
commit cbc0e1ffcf
10 changed files with 102 additions and 124 deletions
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30
bsp/ti-tms320c6678/applications/board.c
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@ -9,28 +9,12 @@
*/
#include "board.h"
#include "trap.h"
#include "interrupt.h"
#include "drv_timer.h"
#include "KeyStone_common.h"
#include <rtthread.h>
/**
* This is the timer interrupt service routine.
*
*/
void rt_hw_systick_isr(void)
{
/* enter interrupt */
rt_interrupt_enter();
rt_tick_increase();
/* leave interrupt */
rt_interrupt_leave();
}
/**
* This function will initial board.
*/
@ -42,16 +26,12 @@ void rt_hw_board_init(void)
// initial interrupt controller
rt_hw_interrupt_init();
// initial system trap
rt_trap_init();
// initial system timer
hw_system_timer_init();
hw_system_timer_init();
/* initialize memory system */
rt_kprintf("heap: 0x%08x - 0x%08x\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
/* initialize memory system */
rt_kprintf("heap: 0x%08x - 0x%08x\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
hw_system_timer_start();
hw_system_timer_start();
}

40
bsp/ti-tms320c6678/driver/drv_timer.c
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@ -15,41 +15,51 @@
#include <rtthread.h>
/**
* @b Description
* @n
* The function initial system timer.
* Use local timer (==DNUM of a core) to generate a clock on TIMO0,interrupts are generated as well
* This is the timer interrupt service routine.
*
* @param[]
*
* @retval
* NULL
*/
void rt_hw_systick_isr(void)
{
/* enter interrupt */
rt_interrupt_enter();
rt_tick_increase();
/* leave interrupt */
rt_interrupt_leave();
}
/**
* The function initial system timer interrupt.
*/
void hw_system_timer_init(void)
{
// initial system timer interrupt
// map local timer interrupt to INT14
// initial system timer interrupt, map local timer interrupt to INT14
gpCGEM_regs->INTMUX3 = (CSL_GEM_TINTLN<<CSL_CGEM_INTMUX3_INTSEL14_SHIFT);
// enable INT14
// enable CPU INT14
CPU_interrupt_enable(1<<14);
return ;
}
/**
* The function initial system timer.
* Use local timer (==DNUM of a core) to generate a clock on TIMO0,interrupts are generated as well
*
*/
void hw_system_timer_start(void)
{
Timer64_Config tmrCfg;
//select output on TIMO0 from local timer.
// select output on TIMO0 from local timer.
gpBootCfgRegs->TOUTSEL = (DNUM*2)<<CSL_BOOTCFG_TOUTSEL_TOUTSEL0_SHIFT;
/* configure the timer to generate clocks and interrupts */
// configure the timer to generate clocks and interrupts
tmrCfg.timer_num= DNUM;
tmrCfg.timerMode= TIMER_PERIODIC_CLOCK;
tmrCfg.period= (unsigned long long) RT_TICK_PER_SECOND*gDSP_Core_Speed_Hz/6000;
tmrCfg.reload_period= 0; //not used for this case
tmrCfg.reload_period= 0;
// initial timer
Timer64_Init(&tmrCfg);
}

18
libcpu/ti-dsp/c6x/c66xx.h
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@ -74,21 +74,6 @@ struct rt_hw_exp_stack_register
struct rt_hw_register hw_register;
};
extern cregister volatile unsigned int IERR; /* Internal Exception Report Register */
extern cregister volatile unsigned int ECR; /* Exception Clear Register */
extern cregister volatile unsigned int EFR; /* Exception Flag Register */
extern cregister volatile unsigned int TSR; /* Task State Register */
extern cregister volatile unsigned int ITSR; /* Interrupt Task State Register */
extern cregister volatile unsigned int NTSR; /* NMI/exception Task State Register */
extern cregister volatile unsigned int TSCL; /* Time Stamp Counter Register - Low Half */
extern cregister volatile unsigned int TSCH; /* Time Stamp Counter Register - High Half */
extern cregister volatile unsigned int DNUM; /* Core number */
#define get_creg(reg) reg
#define set_creg(reg, v) reg = (v)
#define or_creg(reg, n) reg |= (n)
#define and_creg(reg, n) reg &= (n)
#define __dint() asm(" DINT")
#define __rint() asm(" RINT")
#define __system_call() asm(" SWE")
@ -99,7 +84,4 @@ extern cregister volatile unsigned int DNUM; /* Core number */
#define __SYSREG(ADDR, TYPE) (*(volatile TYPE*)(ADDR))
#define __SYSREGA(ADDR, TYPE) ((volatile TYPE*)(ADDR))
extern void rt_hw_enable_exception(void);
#endif /* __C66XX_H__ */

2
libcpu/ti-dsp/c6x/context.asm
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@ -9,7 +9,7 @@
;
;-----------------------------------------------------------
; context switch for C6678 DSP
; context switch for C6000 DSP
;-----------------------------------------------------------
.include "contextinc.asm"

7
libcpu/ti-dsp/c6x/interrupt.c
View File

@ -8,8 +8,10 @@
* 2021-11-16 Dystopia the first version
*/
#include "c66xx.h"
#include "interrupt.h"
#include "c66xx.h"
#include "trap.h"
#define MAX_HANDLERS 128
@ -24,6 +26,9 @@ rt_uint32_t rt_thread_switch_interrupt_flag;
*/
void rt_hw_interrupt_init(void)
{
// initial system trap
rt_trap_init();
/* init exceptions table */
rt_memset(isr_table, 0x00, sizeof(isr_table));

2
libcpu/ti-dsp/c6x/intexc.asm
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@ -9,7 +9,7 @@
;
;-----------------------------------------------------------
; interrupt and execption handler for C6678 DSP
; interrupt and execption handler for C000 DSP
;-----------------------------------------------------------
;-----------------------------------------------------------

122
libcpu/ti-dsp/c6x/stack.asm
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@ -9,7 +9,7 @@
;
;-----------------------------------------------------------
; build system stack for C6678 DSP
; build thread stack for C6000 DSP
;-----------------------------------------------------------
;-----------------------------------------------------------
@ -35,73 +35,73 @@ ADDRESS_MSK .set 0xFFFFFFF0
;{
.global rt_hw_stack_init
rt_hw_stack_init:
SUB A6,1,B1 ;
MVKL ADDRESS_MSK,A1 ;
MVKH ADDRESS_MSK,A1 ; Build address mask
MVC CSR,B0 ;
AND -2,B0,B0 ; Clear GIE bit
OR 2,B0,B0 ; Set PGIE bit for interrupt return
AND A1,B1,B1 ; Ensure alignment
SUB A6,1,B1 ;
MVKL ADDRESS_MSK,A1 ;
MVKH ADDRESS_MSK,A1 ; Build address mask
MVC CSR,B0 ;
AND -2,B0,B0 ; Clear GIE bit
OR 2,B0,B0 ; Set PGIE bit for interrupt return
AND A1,B1,B1 ; Ensure alignment
;
; Actually build the stack frame.
;
MV B1,A3
MV B14,A2
STDW A3:A2,*--B1[1] ; Initial B15:B14
SUBAW .D2 B1,2,B1
ZERO A2
ZERO A3 ; Clear value
STDW A3:A2,*B1--[1] ; Initial A15:A14
STDW A3:A2,*B1--[1] ; Initial A13:A12
STDW A3:A2,*B1--[1] ; Initial A11:A10
STDW A3:A2,*B1--[1] ; Initial A9:A8
STDW A3:A2,*B1--[1] ; Initial A7:A6
MV B4,A2
STDW A3:A2,*B1--[1] ; Initial A5:A4
ZERO A2
STDW A3:A2,*B1--[1] ; Initial A3:A2
STDW A3:A2,*B1--[1] ; Initial A1:A0
MV B1,A3
MV B14,A2
STDW A3:A2,*--B1[1] ; Initial B15:B14
SUBAW .D2 B1,2,B1
ZERO A2
ZERO A3 ; Clear value
STDW A3:A2,*B1--[1] ; Initial A15:A14
STDW A3:A2,*B1--[1] ; Initial A13:A12
STDW A3:A2,*B1--[1] ; Initial A11:A10
STDW A3:A2,*B1--[1] ; Initial A9:A8
STDW A3:A2,*B1--[1] ; Initial A7:A6
MV B4,A2
STDW A3:A2,*B1--[1] ; Initial A5:A4
ZERO A2
STDW A3:A2,*B1--[1] ; Initial A3:A2
STDW A3:A2,*B1--[1] ; Initial A1:A0
STDW A3:A2,*B1--[1] ; Initial A31:A30
STDW A3:A2,*B1--[1] ; Initial A29:A28
STDW A3:A2,*B1--[1] ; Initial A27:A26
STDW A3:A2,*B1--[1] ; Initial A25:A24
STDW A3:A2,*B1--[1] ; Initial A23:A22
STDW A3:A2,*B1--[1] ; Initial A21:A20
STDW A3:A2,*B1--[1] ; Initial A19:A18
STDW A3:A2,*B1--[1] ; Initial A17:A16
STDW A3:A2,*B1--[1] ; Initial A31:A30
STDW A3:A2,*B1--[1] ; Initial A29:A28
STDW A3:A2,*B1--[1] ; Initial A27:A26
STDW A3:A2,*B1--[1] ; Initial A25:A24
STDW A3:A2,*B1--[1] ; Initial A23:A22
STDW A3:A2,*B1--[1] ; Initial A21:A20
STDW A3:A2,*B1--[1] ; Initial A19:A18
STDW A3:A2,*B1--[1] ; Initial A17:A16
STDW A3:A2,*B1--[1] ; Initial B13:B12
STDW A3:A2,*B1--[1] ; Initial B11:B10
STDW A3:A2,*B1--[1] ; Initial B9:B8
STDW A3:A2,*B1--[1] ; Initial B7:B6
STDW A3:A2,*B1--[1] ; Initial B5:B4
MV B6,A3
STDW A3:A2,*B1--[1] ; Initial B3:B2
ZERO A3
STDW A3:A2,*B1--[1] ; Initial B1:B0
STDW A3:A2,*B1--[1] ; Initial B13:B12
STDW A3:A2,*B1--[1] ; Initial B11:B10
STDW A3:A2,*B1--[1] ; Initial B9:B8
STDW A3:A2,*B1--[1] ; Initial B7:B6
STDW A3:A2,*B1--[1] ; Initial B5:B4
MV B6,A3
STDW A3:A2,*B1--[1] ; Initial B3:B2
ZERO A3
STDW A3:A2,*B1--[1] ; Initial B1:B0
STDW A3:A2,*B1--[1] ; Initial B31:B30
STDW A3:A2,*B1--[1] ; Initial B29:B28
STDW A3:A2,*B1--[1] ; Initial B27:B26
STDW A3:A2,*B1--[1] ; Initial B25:B24
STDW A3:A2,*B1--[1] ; Initial B23:B22
STDW A3:A2,*B1--[1] ; Initial B21:B20
STDW A3:A2,*B1--[1] ; Initial B19:B18
STDW A3:A2,*B1--[1] ; Initial B17:B16
STDW A3:A2,*B1--[1] ; Initial B31:B30
STDW A3:A2,*B1--[1] ; Initial B29:B28
STDW A3:A2,*B1--[1] ; Initial B27:B26
STDW A3:A2,*B1--[1] ; Initial B25:B24
STDW A3:A2,*B1--[1] ; Initial B23:B22
STDW A3:A2,*B1--[1] ; Initial B21:B20
STDW A3:A2,*B1--[1] ; Initial B19:B18
STDW A3:A2,*B1--[1] ; Initial B17:B16
MV A4,A3
MV B0,A2
STDW A3:A2,*B1--[1] ; Initial PC:CSR
MV A4,A3
MV B0,A2
STDW A3:A2,*B1--[1] ; Initial PC:CSR
ZERO A2
ZERO A3
STDW A3:A2,*B1--[1] ; Initial ILC:RILC
B B3
MVKL 0x3,B0
MV B0,A3
MVKL 1,A2
STDW A3:A2,*B1--[1] ; Initial TSR:stack type
MV B1,A4 ; Save to TCB
ZERO A2
ZERO A3
STDW A3:A2,*B1--[1] ; Initial ILC:RILC
B B3
MVKL 0x3,B0
MV B0,A3
MVKL 1,A2
STDW A3:A2,*B1--[1] ; Initial TSR:stack type
MV B1,A4 ; Save to TCB
;}
.end

1
libcpu/ti-dsp/c6x/trap.c
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@ -18,6 +18,7 @@
#define RT_SYS_STACK_SIZE 4096
extern void rt_hw_enable_exception(void);
rt_uint8_t rt_system_stack[RT_SYS_STACK_SIZE];
rt_uint8_t *rt_system_stack_top;

2
libcpu/ti-dsp/c6x/trap.h
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@ -70,7 +70,7 @@ struct rt_exception_info {
#define __ffs(a) (_lmbd(1, _bitr(a)))
#define __fls(a) (!(a) ? 0 : (32 - _lmbd(1, (a))))
void rt_trap_init(void);
extern void rt_trap_init(void);
#endif /* __TRAP_H__ */

2
libcpu/ti-dsp/c6x/vector.asm
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@ -9,7 +9,7 @@
;
;-----------------------------------------------------------
; interrupt vector table for C6678 DSP
; interrupt vector table for C6000 DSP
;-----------------------------------------------------------
;-----------------------------------------------------------