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add spi flash driver

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This commit is contained in:
tanek liang 2017-08-29 19:30:21 +08:00
parent ea2a9db341
commit c7c0edebba
11 changed files with 4152 additions and 2560 deletions
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26
bsp/gd32450z-eval/applications/application.c
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@ -22,6 +22,16 @@
#include <rtgui/driver.h>
#endif
#ifdef RT_USING_DFS
/* dfs init */
#include <dfs_init.h>
/* dfs filesystem:ELM filesystem init */
#include <dfs_elm.h>
/* dfs Filesystem APIs */
#include <dfs_fs.h>
#include <dfs_posix.h>
#endif
#include <gd32f4xx.h>
void gd_eval_led_init (void)
@ -56,6 +66,22 @@ void rt_init_thread_entry(void* parameter)
}
#endif
#ifdef RT_USING_DFS
#ifdef RT_USING_DFS_ELMFAT
/* mount sd card fat partition 0 as root directory */
if (dfs_mount("gd25q16", "/", "elm", 0, 0) == 0)
{
rt_kprintf("spi flash mount to / !\n");
}
else
{
rt_kprintf("spi flash mount to / failed!\n");
}
#endif /* RT_USING_DFS_ELMFAT */
#endif /* DFS */
while(1)
{
GPIO_TG(GPIOD) = GPIO_PIN_4;

19
bsp/gd32450z-eval/drivers/SConscript
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@ -9,14 +9,25 @@ src = Split("""
board.c
drv_exmc_sdram.c
drv_usart.c
gd32f450z_lcd_eval.c
drv_lcd.c
drv_enet.c
synopsys_emac.c
""")
CPPPATH = [cwd]
# add Ethernet drivers.
if GetDepend('RT_USING_LWIP'):
src += ['drv_enet.c', 'synopsys_emac.c']
# add lcd drivers.
if GetDepend('RT_USING_GUIENGINE'):
src += ['drv_lcd.c', 'gd32f450z_lcd_eval.c']
# add spi flash drivers.
if GetDepend('RT_USING_SFUD'):
src += ['drv_spi_flash.c', 'drv_spi.c']
elif GetDepend('RT_USING_SPI'):
src += ['drv_spi.c']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

347
bsp/gd32450z-eval/drivers/drv_spi.c Normal file
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@ -0,0 +1,347 @@
/*
* File : drv_spi.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2017 RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2017-06-05 tanek first implementation.
*/
#include "drv_spi.h"
#include <board.h>
#include <finsh.h>
//#define DEBUG
#define ARR_LEN(__N) (sizeof(__N) / sizeof(__N[0]))
#ifdef DEBUG
#define DEBUG_PRINTF(...) rt_kprintf(__VA_ARGS__)
#else
#define DEBUG_PRINTF(...)
#endif
/* private rt-thread spi ops function */
static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configuration* configuration);
static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* message);
static struct rt_spi_ops stm32_spi_ops =
{
configure,
xfer
};
static rt_err_t configure(struct rt_spi_device* device,
struct rt_spi_configuration* configuration)
{
struct rt_spi_bus * spi_bus = (struct rt_spi_bus *)device->bus;
struct stm32f4_spi *f4_spi = (struct stm32f4_spi *)spi_bus->parent.user_data;
spi_parameter_struct spi_init_struct;
uint32_t spi_periph = f4_spi->spi_periph;
RT_ASSERT(device != RT_NULL);
RT_ASSERT(configuration != RT_NULL);
/* data_width */
if(configuration->data_width <= 8)
{
spi_init_struct.frame_size = SPI_FRAMESIZE_8BIT;
}
else if(configuration->data_width <= 16)
{
spi_init_struct.frame_size = SPI_FRAMESIZE_16BIT;
}
else
{
return RT_EIO;
}
/* baudrate */
{
rcu_clock_freq_enum spi_src;
uint32_t spi_apb_clock;
uint32_t max_hz;
max_hz = configuration->max_hz;
DEBUG_PRINTF("sys freq: %d\n", HAL_RCC_GetSysClockFreq());
DEBUG_PRINTF("pclk2 freq: %d\n", HAL_RCC_GetPCLK2Freq());
DEBUG_PRINTF("max freq: %d\n", max_hz);
if (spi_periph == SPI1 || spi_periph == SPI2)
{
spi_src = CK_APB1;
}
else
{
spi_src = CK_APB2;
}
spi_apb_clock = rcu_clock_freq_get(spi_src);
if(max_hz >= spi_apb_clock/2)
{
spi_init_struct.prescale = SPI_PSC_2;
}
else if (max_hz >= spi_apb_clock/4)
{
spi_init_struct.prescale = SPI_PSC_4;
}
else if (max_hz >= spi_apb_clock/8)
{
spi_init_struct.prescale = SPI_PSC_8;
}
else if (max_hz >= spi_apb_clock/16)
{
spi_init_struct.prescale = SPI_PSC_16;
}
else if (max_hz >= spi_apb_clock/32)
{
spi_init_struct.prescale = SPI_PSC_32;
}
else if (max_hz >= spi_apb_clock/64)
{
spi_init_struct.prescale = SPI_PSC_64;
}
else if (max_hz >= spi_apb_clock/128)
{
spi_init_struct.prescale = SPI_PSC_128;
}
else
{
/* min prescaler 256 */
spi_init_struct.prescale = SPI_PSC_256;
}
} /* baudrate */
switch(configuration->mode)
{
case RT_SPI_MODE_0:
spi_init_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE;
break;
case RT_SPI_MODE_1:
spi_init_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_2EDGE;
break;
case RT_SPI_MODE_2:
spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_1EDGE;
break;
case RT_SPI_MODE_3:
spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_2EDGE;
break;
}
/* MSB or LSB */
if(configuration->mode & RT_SPI_MSB)
{
spi_init_struct.endian = SPI_ENDIAN_MSB;
}
else
{
spi_init_struct.endian = SPI_ENDIAN_LSB;
}
spi_init_struct.trans_mode = SPI_TRANSMODE_FULLDUPLEX;
spi_init_struct.device_mode = SPI_MASTER;
spi_init_struct.nss = SPI_NSS_SOFT;
spi_crc_off(spi_periph);
/* init SPI */
spi_init(spi_periph, &spi_init_struct);
/* Enable SPI_MASTER */
spi_enable(spi_periph);
return RT_EOK;
};
static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* message)
{
struct rt_spi_bus * stm32_spi_bus = (struct rt_spi_bus *)device->bus;
struct stm32f4_spi *f4_spi = (struct stm32f4_spi *)stm32_spi_bus->parent.user_data;
struct rt_spi_configuration * config = &device->config;
struct stm32_spi_cs * stm32_spi_cs = device->parent.user_data;
uint32_t spi_periph = f4_spi->spi_periph;
RT_ASSERT(device != NULL);
RT_ASSERT(message != NULL);
/* take CS */
if(message->cs_take)
{
gpio_bit_reset(stm32_spi_cs->GPIOx, stm32_spi_cs->GPIO_Pin);
DEBUG_PRINTF("spi take cs\n");
}
{
if(config->data_width <= 8)
{
const rt_uint8_t * send_ptr = message->send_buf;
rt_uint8_t * recv_ptr = message->recv_buf;
rt_uint32_t size = message->length;
DEBUG_PRINTF("spi poll transfer start: %d\n", size);
while(size--)
{
rt_uint8_t data = 0xFF;
if(send_ptr != RT_NULL)
{
data = *send_ptr++;
}
// Todo: replace register read/write by stm32f4 lib
//Wait until the transmit buffer is empty
while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE));
// Send the byte
spi_i2s_data_transmit(spi_periph, data);
//Wait until a data is received
while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_RBNE));
// Get the received data
data = spi_i2s_data_receive(spi_periph);
if(recv_ptr != RT_NULL)
{
*recv_ptr++ = data;
}
}
DEBUG_PRINTF("spi poll transfer finsh\n");
}
else if(config->data_width <= 16)
{
const rt_uint16_t * send_ptr = message->send_buf;
rt_uint16_t * recv_ptr = message->recv_buf;
rt_uint32_t size = message->length;
while(size--)
{
rt_uint16_t data = 0xFF;
if(send_ptr != RT_NULL)
{
data = *send_ptr++;
}
//Wait until the transmit buffer is empty
while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE));
// Send the byte
spi_i2s_data_transmit(spi_periph, data);
//Wait until a data is received
while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_RBNE));
// Get the received data
data = spi_i2s_data_receive(spi_periph);
if(recv_ptr != RT_NULL)
{
*recv_ptr++ = data;
}
}
}
}
/* release CS */
if(message->cs_release)
{
gpio_bit_set(stm32_spi_cs->GPIOx, stm32_spi_cs->GPIO_Pin);
DEBUG_PRINTF("spi release cs\n");
}
return message->length;
};
static struct rt_spi_bus spi_bus[];
static const struct stm32f4_spi spis[] = {
#ifdef RT_USING_SPI0
{SPI0, RCU_SPI0, &spi_bus[0]},
#endif
#ifdef RT_USING_SPI1
{SPI1, RCU_SPI1, &spi_bus[1]},
#endif
#ifdef RT_USING_SPI2
{SPI2, RCU_SPI2, &spi_bus[2]},
#endif
#ifdef RT_USING_SPI3
{SPI3, RCU_SPI3, &spi_bus[3]},
#endif
#ifdef RT_USING_SPI4
{SPI4, RCU_SPI4, &spi_bus[4]},
#endif
#ifdef RT_USING_SPI5
{SPI5, RCU_SPI5, &spi_bus[5]},
#endif
};
static struct rt_spi_bus spi_bus[ARR_LEN(spis)];
/** \brief init and register stm32 spi bus.
*
* \param SPI: STM32 SPI, e.g: SPI1,SPI2,SPI3.
* \param spi_bus_name: spi bus name, e.g: "spi1"
* \return
*
*/
rt_err_t stm32_spi_bus_register(uint32_t spi_periph,
//struct stm32_spi_bus * stm32_spi,
const char * spi_bus_name)
{
int i;
RT_ASSERT(spi_bus_name != RT_NULL);
for (i = 0; i < ARR_LEN(spis); i++)
{
if (spi_periph == spis[i].spi_periph)
{
rcu_periph_clock_enable(spis[i].spi_clk);
spis[i].spi_bus->parent.user_data = (void *)&spis[i];
rt_spi_bus_register(spis[i].spi_bus, spi_bus_name, &stm32_spi_ops);
return RT_EOK;
}
}
return RT_ERROR;
#ifdef SPI_USE_DMA
/* Configure the DMA handler for Transmission process */
p_spi_bus->hdma_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
p_spi_bus->hdma_tx.Init.PeriphInc = DMA_PINC_DISABLE;
//p_spi_bus->hdma_tx.Init.MemInc = DMA_MINC_ENABLE;
p_spi_bus->hdma_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
p_spi_bus->hdma_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
p_spi_bus->hdma_tx.Init.Mode = DMA_NORMAL;
p_spi_bus->hdma_tx.Init.Priority = DMA_PRIORITY_LOW;
p_spi_bus->hdma_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
p_spi_bus->hdma_tx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
p_spi_bus->hdma_tx.Init.MemBurst = DMA_MBURST_INC4;
p_spi_bus->hdma_tx.Init.PeriphBurst = DMA_PBURST_INC4;
p_spi_bus->hdma_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
p_spi_bus->hdma_rx.Init.PeriphInc = DMA_PINC_DISABLE;
//p_spi_bus->hdma_rx.Init.MemInc = DMA_MINC_ENABLE;
p_spi_bus->hdma_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
p_spi_bus->hdma_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
p_spi_bus->hdma_rx.Init.Mode = DMA_NORMAL;
p_spi_bus->hdma_rx.Init.Priority = DMA_PRIORITY_HIGH;
p_spi_bus->hdma_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
p_spi_bus->hdma_rx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
p_spi_bus->hdma_rx.Init.MemBurst = DMA_MBURST_INC4;
p_spi_bus->hdma_rx.Init.PeriphBurst = DMA_PBURST_INC4;
#endif
}

42
bsp/gd32450z-eval/drivers/drv_spi.h Normal file
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@ -0,0 +1,42 @@
/*
* File : stm32f20x_40x_spi.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009 RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 20012-01-01 aozima first implementation.
*/
#ifndef STM32F20X_40X_SPI_H_INCLUDED
#define STM32F20X_40X_SPI_H_INCLUDED
#include <rtthread.h>
#include <drivers/spi.h>
#include "gd32f4xx.h"
struct stm32f4_spi
{
uint32_t spi_periph;
rcu_periph_enum spi_clk;
struct rt_spi_bus *spi_bus;
};
struct stm32_spi_cs
{
uint32_t GPIOx;
uint32_t GPIO_Pin;
};
/* public function */
rt_err_t stm32_spi_bus_register(uint32_t spi_periph,
//struct stm32_spi_bus * stm32_spi,
const char * spi_bus_name);
#endif // STM32F20X_40X_SPI_H_INCLUDED

105
bsp/gd32450z-eval/drivers/drv_spi_flash.c Normal file
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@ -0,0 +1,105 @@
/*
* File : stm32f20x_40x_spi.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009 RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2012-01-01 aozima first implementation.
* 2012-07-27 aozima fixed variable uninitialized.
*/
#include <board.h>
#include "drv_spi.h"
#include "spi_flash.h"
#ifdef RT_USING_SFUD
#include "spi_flash_sfud.h"
#endif
#ifdef RT_USING_W25QXX
#include "spi_flash_w25qxx.h"
#endif
#include <rthw.h>
#include <finsh.h>
#if defined(RT_USING_SFUD) && defined(RT_USING_W25QXX)
#error "RT_USING_SFUD and RT_USING_W25QXX only need one"
#endif
#define SPI_PERIPH SPI5
#define SPI_BUS_NAME "spi5"
#define SPI_FLASH_DEVICE_NAME "spi50"
#define SPI_FLASH_CHIP "gd25q16"
static int rt_hw_spi5_init(void)
{
/* register spi bus */
{
rt_err_t result;
rcu_periph_clock_enable(RCU_GPIOG);
rcu_periph_clock_enable(RCU_SPI5);
/* SPI5_CLK(PG13), SPI5_MISO(PG12), SPI5_MOSI(PG14),SPI5_IO2(PG10) and SPI5_IO3(PG11) GPIO pin configuration */
gpio_af_set(GPIOG, GPIO_AF_5, GPIO_PIN_10|GPIO_PIN_11| GPIO_PIN_12|GPIO_PIN_13| GPIO_PIN_14);
gpio_mode_set(GPIOG, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_10|GPIO_PIN_11| GPIO_PIN_12|GPIO_PIN_13| GPIO_PIN_14);
gpio_output_options_set(GPIOG, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ, GPIO_PIN_10|GPIO_PIN_11| GPIO_PIN_12|GPIO_PIN_13| GPIO_PIN_14);
result = stm32_spi_bus_register(SPI5, SPI_BUS_NAME);
if (result != RT_EOK)
{
return result;
}
}
/* attach cs */
{
static struct rt_spi_device spi_device;
static struct stm32_spi_cs spi_cs;
rt_err_t result;
spi_cs.GPIOx = GPIOG;
spi_cs.GPIO_Pin = GPIO_PIN_9;
/* SPI5_CS(PG9) GPIO pin configuration */
gpio_mode_set(GPIOG, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO_PIN_9);
gpio_output_options_set(GPIOG, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_9);
gpio_bit_set(GPIOG,GPIO_PIN_9);
result = rt_spi_bus_attach_device(&spi_device, SPI_FLASH_DEVICE_NAME, SPI_BUS_NAME, (void*)&spi_cs);
if (result != RT_EOK)
{
return result;
}
}
return RT_EOK;
}
INIT_DEVICE_EXPORT(rt_hw_spi5_init);
#ifdef RT_USING_SFUD
static int rt_hw_spi_flash_with_sfud_init(void)
{
if (RT_NULL == rt_sfud_flash_probe(SPI_FLASH_CHIP, SPI_FLASH_DEVICE_NAME))
{
return RT_ERROR;
};
return RT_EOK;
}
INIT_COMPONENT_EXPORT(rt_hw_spi_flash_with_sfud_init)
#endif
#ifdef RT_USING_W25QXX
static int rt_hw_spi_flash_init(void)
{
return w25qxx_init(SPI_FLASH_CHIP, SPI_FLASH_DEVICE_NAME);
}
INIT_COMPONENT_EXPORT(rt_hw_spi_flash_init)
#endif

4948
bsp/gd32450z-eval/project.ewp
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671
bsp/gd32450z-eval/project.uvproj
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bsp/gd32450z-eval/project.uvprojx
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61
bsp/gd32450z-eval/rtconfig.h
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@ -120,45 +120,40 @@
#define FINSH_USING_DESCRIPTION
//#define FINSH_USING_MSH
#define RT_USING_RTC
#ifdef RT_USING_RTC
#define RT_RTC_NAME "rtc"
#endif
// <section name="LIBC" description="C Runtime library setting" default="always" >
// <bool name="RT_USING_LIBC" description="Using libc library" default="true" />
#define RT_USING_LIBC
/* SECTION: device filesystem */
/* Using Device file system */
//#define RT_USING_DFS /**/
#define RT_USING_DFS /**/
// <bool name="RT_USING_DFS_DEVFS" description="Using devfs for device objects" default="true" />
#define RT_USING_DFS_DEVFS
// <integer name="DFS_FILESYSTEM_TYPES_MAX" description="The maximal number of the supported file system type" default="4" />
#define DFS_FILESYSTEM_TYPES_MAX 4
//// <integer name="DFS_FILESYSTEM_TYPES_MAX" description="The maximal number of the supported file system type" default="4" />
//#define DFS_FILESYSTEM_TYPES_MAX 2
/* the max number of mounted filesystem */
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEMS_MAX 2
/* the max number of opened files */
#define DFS_FD_MAX 16
#define DFS_FD_MAX 4
//#define DFS_USING_WORKDIR
/* Using ELM FATFS */
#define RT_USING_DFS_ELMFAT
#define RT_DFS_ELM_WORD_ACCESS
/* Reentrancy (thread safe) of the FatFs module. */
#define RT_DFS_ELM_REENTRANT
/* Number of volumes (logical drives) to be used. */
////#define RT_DFS_ELM_WORD_ACCESS
///* Reentrancy (thread safe) of the FatFs module. */
//#define RT_DFS_ELM_REENTRANT
///* Number of volumes (logical drives) to be used. */
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_USE_LFN 3 /* */
#define RT_DFS_ELM_CODE_PAGE 437
//#define RT_DFS_ELM_USE_LFN 3 /* */
#define RT_DFS_ELM_MAX_LFN 255
/* Maximum sector size to be handled. */
///* Maximum sector size to be handled. */
#define RT_DFS_ELM_MAX_SECTOR_SIZE 4096
/* DFS: UFFS nand file system options */
#define RT_USING_DFS_UFFS
/* configuration for uffs, more to see dfs_uffs.h and uffs_config.h */
#define RT_CONFIG_UFFS_ECC_MODE UFFS_ECC_HW_AUTO
//UFFS_ECC_SOFT
//UFFS_ECC_HW_AUTO
/* enable this ,you need provide a mark_badblock/check_block function */
/* #define RT_UFFS_USE_CHECK_MARK_FUNCITON */
/* Using ROM file system */
// #define RT_USING_DFS_ROMFS
/* SECTION: lwip, a lighwight TCP/IP protocol stack */
#define RT_USING_LWIP
/* LwIP uses RT-Thread Memory Management */
@ -225,14 +220,18 @@
/* spi driver */
#define RT_USING_SPI
#define RT_USING_SPI0
#define RT_USING_SPI1
#define RT_USING_SPI2
#define RT_USING_SPI3
#define RT_USING_SPI4
#define RT_USING_SPI5
//#define RT_USING_W25QXX
//#define FLASH_DEBUG
/* Serial Flash Universal Driver */
//#define RT_USING_SFUD
/* Enable SFUD debug output */
//#define RT_DEBUG_SFUD 1
/* serial flash discoverable parameters by JEDEC standard */
#define RT_SFUD_USING_SFDP
#define RT_USING_SFUD
//#define RT_SFUD_USING_SFDP
#define RT_SFUD_USING_FLASH_INFO_TABLE
#define RT_USING_I2C
#define RT_USING_I2C_BITOPS

22
bsp/gd32450z-eval/rtconfig.py
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@ -3,7 +3,7 @@ import os
# toolchains options
ARCH='arm'
CPU='cortex-m4'
CROSS_TOOL='keil'
CROSS_TOOL='iar'
if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
@ -20,11 +20,9 @@ elif CROSS_TOOL == 'keil':
PLATFORM = 'armcc'
EXEC_PATH = r'C:/Keil_v5'
elif CROSS_TOOL == 'iar':
print '================ERROR============================'
print 'Not support iar yet!'
print '================================================='
exit(0)
PLATFORM = 'iar'
EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0'
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
@ -44,12 +42,14 @@ elif PLATFORM == 'armcc':
DEVICE = ' --cpu=cortex-m4.fp'
CFLAGS = DEVICE + ' --apcs=interwork --cpu Cortex-M4.fp'
AFLAGS = DEVICE
LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-gd32.map --scatter stm32_rom.sct'
LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-gd32.map --scatter gd32_rom.sct'
CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
EXEC_PATH += '/arm/bin40/'
CFLAGS += ' --c99'
if BUILD == 'debug':
CFLAGS += ' -g -O0'
@ -67,7 +67,7 @@ elif PLATFORM == 'iar':
LINK = 'ilinkarm'
TARGET_EXT = 'out'
DEVICE = ' -D USE_STDPERIPH_DRIVER' + ' -D STM32F10X_HD'
DEVICE = ' -D USE_STDPERIPH_DRIVER' + ' -D GD32F450xK'
CFLAGS = DEVICE
CFLAGS += ' --diag_suppress Pa050'
@ -83,7 +83,7 @@ elif PLATFORM == 'iar':
CFLAGS += ' --cpu=Cortex-M4'
CFLAGS += ' -e'
CFLAGS += ' --fpu=None'
CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
CFLAGS += ' -Ol'
CFLAGS += ' --use_c++_inline'
@ -94,10 +94,10 @@ elif PLATFORM == 'iar':
AFLAGS += ' --cpu Cortex-M4'
AFLAGS += ' --fpu None'
LFLAGS = ' --config stm32f10x_flash.icf'
LFLAGS = ' --config gd32_rom.icf'
LFLAGS += ' --redirect _Printf=_PrintfTiny'
LFLAGS += ' --redirect _Scanf=_ScanfSmall'
LFLAGS += ' --entry __iar_program_start'
EXEC_PATH = IAR_PATH + '/arm/bin/'
EXEC_PATH += '/arm/bin/'
POST_ACTION = ''

2
bsp/gd32450z-eval/template.uvprojx
View File

@ -321,7 +321,7 @@
<wLevel>0</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>0</uC99>
<uC99>1</uC99>
<useXO>0</useXO>
<v6Lang>1</v6Lang>
<v6LangP>1</v6LangP>