update V850 BSP, now supporting scons + IAR
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2306 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
dzzxzz@gmail.com
parent
6dcb1207b1
commit
c784dd2ed8
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@ -0,0 +1,12 @@
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from building import *
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cwd = GetCurrentDir()
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objs = []
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list = os.listdir(cwd)
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for d in list:
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path = os.path.join(cwd, d)
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if os.path.isfile(os.path.join(path, 'SConscript')):
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objs = objs + SConscript(os.path.join(d, 'SConscript'))
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Return('objs')
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@ -0,0 +1,37 @@
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import os
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import sys
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import rtconfig
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if os.getenv('RTT_ROOT'):
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RTT_ROOT = os.getenv('RTT_ROOT')
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else:
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RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
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sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
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from building import *
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TARGET = 'rtthread.' + rtconfig.TARGET_EXT
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env = Environment(tools = ['mingw'],
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AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
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CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
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AR = rtconfig.AR, ARFLAGS = '-rc',
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LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
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env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
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if rtconfig.PLATFORM == 'iar':
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env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
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env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -f lnk70f3454.xcl -l rtthread.map -Omotorola-s28=$TARGET'])
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env.Replace(ARFLAGS = '')
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Export('RTT_ROOT')
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Export('rtconfig')
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# prepare building environment
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objs = PrepareBuilding(env, RTT_ROOT)
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# build program
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env.Program(TARGET, objs)
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# end building
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EndBuilding(TARGET)
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@ -0,0 +1,9 @@
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from building import *
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cwd = GetCurrentDir()
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src = Glob('*.c')
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CPPPATH = [cwd, str(Dir('#'))]
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group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
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Return('group')
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@ -1,7 +1,7 @@
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/*
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* File : application.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2009, RT-Thread Development Team
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* COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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@ -28,19 +28,15 @@
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static struct rt_thread led;
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#if defined(__ICCM16C__) || defined(__ICCV850__)
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#pragma data_alignment=4
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#endif
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ALIGN(RT_ALIGN_SIZE)
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static rt_uint8_t led_stack[256];
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static void rt_thread_entry_led(void *parameter)
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{
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while (1)
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{
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/* led off */
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led_off();
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rt_thread_delay(20); /* sleep 1 second and switch to other thread */
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/* led on */
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rt_thread_delay(20);
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led_on();
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rt_thread_delay(40);
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}
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@ -48,14 +44,18 @@ static void rt_thread_entry_led(void* parameter)
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int rt_application_init(void)
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{
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/* create led thread */
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rt_thread_init(&led,
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"led",
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rt_thread_entry_led, RT_NULL,
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&led_stack[0], sizeof(led_stack),
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5, 32);
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rt_err_t result;
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if (&led != RT_NULL)
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result = rt_thread_init(&led,
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"led",
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rt_thread_entry_led,
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RT_NULL,
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&led_stack[0],
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sizeof(led_stack),
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RT_THREAD_PRIORITY_MAX / 2,
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32);
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if (result == RT_EOK)
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rt_thread_startup(&led);
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return 0;
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@ -1,7 +1,7 @@
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/*
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* File : startup.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2009, RT-Thread Development Team
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* COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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@ -0,0 +1,110 @@
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/*
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*******************************************************************************
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* Copyright(C) NEC Electronics Corporation 2010
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* All rights reserved by NEC Electronics Corporation.
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* This program should be used on your own responsibility.
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* NEC Electronics Corporation assumes no responsibility for any losses
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* incurred by customers or third parties arising from the use of this file.
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*
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* This device driver was created by Applilet3 for V850ES/Jx3
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* 32-Bit Single-Chip Microcontrollers
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* Filename: CG_macrodriver.h
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* Abstract: This file implements general head file.
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* APIlib: Applilet3 for V850ES/Jx3 V2.01 [20 Apr 2010]
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* Device: uPD70F3746
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* Compiler: IAR Systems ICCV850
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* Creation date: 6/26/2010
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*******************************************************************************
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*/
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#ifndef _MDSTATUS_
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#define _MDSTATUS_
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/*
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*******************************************************************************
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** Include files
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*******************************************************************************
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*/
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#include <intrinsics.h>
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#include "io70f3454.h"
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/*
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*******************************************************************************
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** Register bit define
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*******************************************************************************
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*/
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/*
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*******************************************************************************
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** Macro define
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*******************************************************************************
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*/
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#define DI __disable_interrupt
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#define EI __enable_interrupt
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#define NOP __no_operation
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#define HALT __halt
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/* Data type defintion */
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typedef unsigned long ULONG;
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typedef signed long SLONG;
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typedef unsigned int UINT;
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typedef signed int SINT;
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typedef unsigned short USHORT;
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typedef signed short SHORT;
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typedef unsigned char UCHAR;
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typedef signed char SCHAR;
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typedef unsigned char BOOL;
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typedef unsigned short MD_STATUS;
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#define MD_ON 1U
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#define MD_OFF 0U
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#define MD_TRUE 1U
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#define MD_FALSE 0U
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#define MD_SET 1U
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#define MD_CLEAR 0U
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/* Status list definition */
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#define MD_STATUSBASE 0x00U
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#define MD_OK (MD_STATUSBASE + 0x00U) /* register setting OK */
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#define MD_RESET (MD_STATUSBASE + 0x01U) /* reset input */
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#define MD_SENDCOMPLETE (MD_STATUSBASE + 0x02U) /* send data complete */
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#define MD_ADDRESSMATCH (MD_STATUSBASE + 0x03U) /* IIC slave address match */
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#define MD_OVF (MD_STATUSBASE + 0x04U) /* timer count overflow */
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#define MD_SPT (MD_STATUSBASE + 0x07U) /* IIC stop */
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#define MD_NACK (MD_STATUSBASE + 0x08U) /* IIC no ACK */
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#define MD_SLAVE_SEND_END (MD_STATUSBASE + 0x09U) /* IIC slave send end */
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#define MD_SLAVE_RCV_END (MD_STATUSBASE + 0x0AU) /* IIC slave receive end */
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#define MD_MASTER_SEND_END (MD_STATUSBASE + 0x0BU) /* IIC master send end */
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#define MD_MASTER_RCV_END (MD_STATUSBASE + 0x0CU) /* IIC master receive end */
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#define MD_UNDEREXEC (MD_STATUSBASE + 0x0DU) /* DMA transfer under execute */
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#define MD_COMPLETED (MD_STATUSBASE + 0x0EU) /* DMA transfer completed */
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#define MD_BUSY1 (MD_STATUSBASE + 0x0FU) /* busy 1 */
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#define MD_BUSY2 (MD_STATUSBASE + 0x10U) /* busy 2 */
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/* Error list definition */
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#define MD_ERRORBASE 0x80U
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#define MD_ERROR (MD_ERRORBASE + 0x00U) /* error */
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#define MD_RESOURCEERROR (MD_ERRORBASE + 0x01U) /* no resource available */
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#define MD_PARITYERROR (MD_ERRORBASE + 0x02U) /* UARTn parity error n=0,1,2 */
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#define MD_OVERRUNERROR (MD_ERRORBASE + 0x03U) /* UARTn overrun error n=0,1,2 */
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#define MD_FRAMEERROR (MD_ERRORBASE + 0x04U) /* UARTn frame error n=0,1,2 */
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#define MD_ARGERROR (MD_ERRORBASE + 0x05U) /* Error agrument input error */
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#define MD_TIMINGERROR (MD_ERRORBASE + 0x06U) /* Error timing operation error */
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#define MD_SETPROHIBITED (MD_ERRORBASE + 0x07U) /* setting prohibited */
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#define MD_ODDBUF (MD_ERRORBASE + 0x08U) /* in 16bit transfer mode,buffer size should be even */
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#define MD_DATAEXISTS (MD_ERRORBASE + 0x09U) /* Data to be transferred next exists in TXBn register */
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#define MD_STSERROR (MD_ERRORBASE + 0x0AU) /* CAN status error */
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#define MD_ALRDYSTART (MD_ERRORBASE + 0x0BU) /* CAN-controller is already started error */
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#define MD_NOMSG (MD_ERRORBASE + 0x0CU) /* CAN message not received */
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#define MD_ERROR1 (MD_ERRORBASE + 0x0DU) /* error 1 */
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#define MD_ERROR2 (MD_ERRORBASE + 0x0EU) /* error 2 */
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/*
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*******************************************************************************
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** Function define
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*******************************************************************************
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*/
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#endif
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@ -0,0 +1,71 @@
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/*
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*******************************************************************************
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* Copyright(C) NEC Electronics Corporation 2010
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* All rights reserved by NEC Electronics Corporation.
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* This program should be used on your own responsibility.
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* NEC Electronics Corporation assumes no responsibility for any losses
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* incurred by customers or third parties arising from the use of this file.
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*
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* This device driver was created by Applilet3 for V850ES/Jx3
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* 32-Bit Single-Chip Microcontrollers
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* Filename: CG_port.c
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* Abstract: This file implements device driver for PORT module.
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* APIlib: Applilet3 for V850ES/Jx3 V2.01 [20 Apr 2010]
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* Device: uPD70F3746
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* Compiler: IAR Systems ICCV850
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* Creation date: 6/26/2010
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*******************************************************************************
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*/
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/*
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*******************************************************************************
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** Include files
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*******************************************************************************
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*/
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#include "CG_macrodriver.h"
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#include "CG_port.h"
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/* Start user code for include. Do not edit comment generated here */
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/* End user code. Do not edit comment generated here */
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#include "CG_userdefine.h"
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/*
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*******************************************************************************
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** Global define
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*******************************************************************************
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*/
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/* Start user code for global. Do not edit comment generated here */
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/* End user code. Do not edit comment generated here */
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/*
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**-----------------------------------------------------------------------------
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**
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** Abstract:
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** This function initializes setting for Port I/O.
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**
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** Parameters:
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** None
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**
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** Returns:
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** None
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**
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**-----------------------------------------------------------------------------
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*/
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void PORT_Init(void)
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{
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PDLH = _10_Pn4_OUTPUT_1;
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PMDLH = _01_PMn0_MODE_UNUSED | _02_PMn1_MODE_UNUSED | _04_PMn2_MODE_UNUSED | _08_PMn3_MODE_UNUSED | _00_PMn4_MODE_OUTPUT | _20_PMn5_MODE_UNUSED | _40_PMn6_MODE_UNUSED | _80_PMn7_MODE_UNUSED;
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PMCDLH = _00_PMCn4_OPER_PORT;
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}
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void led_on(void)
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{
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PDLH = _10_Pn4_OUTPUT_1;
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}
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void led_off(void)
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{
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PDLH = _00_Pn4_OUTPUT_0;
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}
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/* Start user code for adding. Do not edit comment generated here */
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/* End user code. Do not edit comment generated here */
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@ -0,0 +1,130 @@
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/*
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*******************************************************************************
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* Copyright(C) NEC Electronics Corporation 2010
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* All rights reserved by NEC Electronics Corporation.
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* This program should be used on your own responsibility.
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* NEC Electronics Corporation assumes no responsibility for any losses
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* incurred by customers or third parties arising from the use of this file.
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*
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* This device driver was created by Applilet3 for V850ES/Jx3
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* 32-Bit Single-Chip Microcontrollers
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* Filename: CG_port.h
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* Abstract: This file implements device driver for PORT module.
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* APIlib: Applilet3 for V850ES/Jx3 V2.01 [20 Apr 2010]
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* Device: uPD70F3746
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* Compiler: IAR Systems ICCV850
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* Creation date: 6/26/2010
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*******************************************************************************
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*/
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#ifndef _MDPORT_
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#define _MDPORT_
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/*
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*******************************************************************************
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** Register bit define
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*******************************************************************************
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*/
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/* Port mode control register (PMCn.7 - PMCn.0) */
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#define _00_PMCn0_OPER_PORT 0x00U /* Pn0 as port mode */
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#define _00_PMCn1_OPER_PORT 0x00U /* Pn1 as port mode */
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#define _00_PMCn2_OPER_PORT 0x00U /* Pn2 as port mode */
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#define _00_PMCn3_OPER_PORT 0x00U /* Pn3 as port mode */
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#define _00_PMCn4_OPER_PORT 0x00U /* Pn4 as port mode */
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#define _00_PMCn5_OPER_PORT 0x00U /* Pn5 as port mode */
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#define _00_PMCn6_OPER_PORT 0x00U /* Pn6 as port mode */
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#define _00_PMCn7_OPER_PORT 0x00U /* Pn7 as port mode */
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#define _01_PMCn0_OPER_ALTER 0x01U /* Pn0 as alternative mode */
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#define _02_PMCn1_OPER_ALTER 0x02U /* Pn1 as alternative mode */
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#define _04_PMCn2_OPER_ALTER 0x04U /* Pn2 as alternative mode */
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#define _08_PMCn3_OPER_ALTER 0x08U /* Pn3 as alternative mode */
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#define _10_PMCn4_OPER_ALTER 0x10U /* Pn4 as alternative mode */
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#define _20_PMCn5_OPER_ALTER 0x20U /* Pn5 as alternative mode */
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#define _40_PMCn6_OPER_ALTER 0x40U /* Pn6 as alternative mode */
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#define _80_PMCn7_OPER_ALTER 0x80U /* Pn7 as alternative mode */
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#define _00_PMCn0_OPER_OCD 0x00U /* PMC0 for MINI2 */
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/* Port mode register (PMn.7 - PMn.0) */
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#define _01_PMn0_MODE_INPUT 0x01U /* Pn0 as input mode */
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#define _02_PMn1_MODE_INPUT 0x02U /* Pn1 as input mode */
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#define _04_PMn2_MODE_INPUT 0x04U /* Pn2 as input mode */
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#define _08_PMn3_MODE_INPUT 0x08U /* Pn3 as input mode */
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#define _10_PMn4_MODE_INPUT 0x10U /* Pn4 as input mode */
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#define _20_PMn5_MODE_INPUT 0x20U /* Pn5 as input mode */
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#define _40_PMn6_MODE_INPUT 0x40U /* Pn6 as input mode */
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#define _80_PMn7_MODE_INPUT 0x80U /* Pn7 as input mode */
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#define _00_PMn0_MODE_OUTPUT 0x00U /* Pn0 as output mode */
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#define _00_PMn1_MODE_OUTPUT 0x00U /* Pn1 as output mode */
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#define _00_PMn2_MODE_OUTPUT 0x00U /* Pn2 as output mode */
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#define _00_PMn3_MODE_OUTPUT 0x00U /* Pn3 as output mode */
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#define _00_PMn4_MODE_OUTPUT 0x00U /* Pn4 as output mode */
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#define _00_PMn5_MODE_OUTPUT 0x00U /* Pn5 as output mode */
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#define _00_PMn6_MODE_OUTPUT 0x00U /* Pn6 as output mode */
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#define _00_PMn7_MODE_OUTPUT 0x00U /* Pn7 as output mode */
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#define _01_PMn0_MODE_UNUSED 0x01U /* Pn0 as default mode */
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#define _02_PMn1_MODE_UNUSED 0x02U /* Pn1 as default mode */
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#define _04_PMn2_MODE_UNUSED 0x04U /* Pn2 as default mode */
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#define _08_PMn3_MODE_UNUSED 0x08U /* Pn3 as default mode */
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#define _10_PMn4_MODE_UNUSED 0x10U /* Pn4 as default mode */
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#define _20_PMn5_MODE_UNUSED 0x20U /* Pn5 as default mode */
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#define _40_PMn6_MODE_UNUSED 0x40U /* Pn6 as default mode */
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#define _80_PMn7_MODE_UNUSED 0x80U /* Pn7 as default mode */
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#define _00_PMn0_MODE_OCD 0x00U /* PMC0 for MINI2 */
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/* Port register (Pn.7 - Pn.0) */
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#define _00_Pn0_OUTPUT_0 0x00U /* Pn0 output 0 */
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#define _00_Pn1_OUTPUT_0 0x00U /* Pn1 output 0 */
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#define _00_Pn2_OUTPUT_0 0x00U /* Pn2 output 0 */
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#define _00_Pn3_OUTPUT_0 0x00U /* Pn3 output 0 */
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#define _00_Pn4_OUTPUT_0 0x00U /* Pn4 output 0 */
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#define _00_Pn5_OUTPUT_0 0x00U /* Pn5 output 0 */
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#define _00_Pn6_OUTPUT_0 0x00U /* Pn6 output 0 */
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#define _00_Pn7_OUTPUT_0 0x00U /* Pn7 output 0 */
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#define _01_Pn0_OUTPUT_1 0x01U /* Pn0 output 1 */
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#define _02_Pn1_OUTPUT_1 0x02U /* Pn1 output 1 */
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#define _04_Pn2_OUTPUT_1 0x04U /* Pn2 output 1 */
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#define _08_Pn3_OUTPUT_1 0x08U /* Pn3 output 1 */
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#define _10_Pn4_OUTPUT_1 0x10U /* Pn4 output 1 */
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#define _20_Pn5_OUTPUT_1 0x20U /* Pn5 output 1 */
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#define _40_Pn6_OUTPUT_1 0x40U /* Pn6 output 1 */
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#define _80_Pn7_OUTPUT_1 0x80U /* Pn7 output 1 */
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/* Function register resistor (PFn.7 - PFn.0) */
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#define _00_PFn0_FUN_NORMAL 0x00U /* Pn0 normal output */
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#define _00_PFn1_FUN_NORMAL 0x00U /* Pn1 normal output */
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#define _00_PFn2_FUN_NORMAL 0x00U /* Pn2 normal output */
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#define _00_PFn3_FUN_NORMAL 0x00U /* Pn3 normal output */
|
||||
#define _00_PFn4_FUN_NORMAL 0x00U /* Pn4 normal output */
|
||||
#define _00_PFn5_FUN_NORMAL 0x00U /* Pn5 normal output */
|
||||
#define _00_PFn6_FUN_NORMAL 0x00U /* Pn6 normal output */
|
||||
#define _00_PFn7_FUN_NORMAL 0x00U /* Pn7 normal output */
|
||||
#define _01_PFn0_FUN_OPEN 0x01U /* Pn0 open-drain output */
|
||||
#define _02_PFn1_FUN_OPEN 0x02U /* Pn1 open-drain output */
|
||||
#define _04_PFn2_FUN_OPEN 0x04U /* Pn2 open-drain output */
|
||||
#define _08_PFn3_FUN_OPEN 0x08U /* Pn3 open-drain output */
|
||||
#define _10_PFn4_FUN_OPEN 0x10U /* Pn4 open-drain output */
|
||||
#define _20_PFn5_FUN_OPEN 0x20U /* Pn5 open-drain output */
|
||||
#define _40_PFn6_FUN_OPEN 0x40U /* Pn6 open-drain output */
|
||||
#define _80_PFn7_FUN_OPEN 0x80U /* Pn7 open-drain output */
|
||||
/*
|
||||
*******************************************************************************
|
||||
** Macro define
|
||||
*******************************************************************************
|
||||
*/
|
||||
#define _80_PM0_DEFAULT 0x80U /* PM0 default value */
|
||||
#define _FC_PM1_DEFAULT 0xFCU /* PM1 default value */
|
||||
#define _FC_PM3H_DEFAULT 0xFCU /* PM3H default value */
|
||||
#define _F8_PM4_DEFAULT 0xF8U /* PM4 default value */
|
||||
#define _C0_PM5_DEFAULT 0xC0U /* PM5 default value */
|
||||
#define _FC_PM8_DEFAULT 0xFCU /* PM8 default value */
|
||||
#define _F0_PMCD_DEFAULT 0xF0U /* PMCD default value */
|
||||
/*
|
||||
*******************************************************************************
|
||||
** Function define
|
||||
*******************************************************************************
|
||||
*/
|
||||
void PORT_Init(void);
|
||||
void led_on(void);
|
||||
void led_off(void);
|
||||
/* Start user code for function. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#endif
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
/*
|
||||
*******************************************************************************
|
||||
* Copyright(C) NEC Electronics Corporation 2010
|
||||
* All rights reserved by NEC Electronics Corporation.
|
||||
* This program should be used on your own responsibility.
|
||||
* NEC Electronics Corporation assumes no responsibility for any losses
|
||||
* incurred by customers or third parties arising from the use of this file.
|
||||
*
|
||||
* This device driver was created by Applilet3 for V850ES/Jx3
|
||||
* 32-Bit Single-Chip Microcontrollers
|
||||
* Filename: CG_port_user.c
|
||||
* Abstract: This file implements device driver for PORT module.
|
||||
* APIlib: Applilet3 for V850ES/Jx3 V2.01 [20 Apr 2010]
|
||||
* Device: uPD70F3746
|
||||
* Compiler: IAR Systems ICCV850
|
||||
* Creation date: 6/26/2010
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/*
|
||||
*******************************************************************************
|
||||
** Include files
|
||||
*******************************************************************************
|
||||
*/
|
||||
#include "CG_macrodriver.h"
|
||||
#include "CG_port.h"
|
||||
/* Start user code for include. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#include "CG_userdefine.h"
|
||||
|
||||
/*
|
||||
*******************************************************************************
|
||||
** Global define
|
||||
*******************************************************************************
|
||||
*/
|
||||
/* Start user code for global. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
|
||||
/* Start user code for adding. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
|
@ -0,0 +1,113 @@
|
|||
/*
|
||||
*******************************************************************************
|
||||
* Copyright(C) NEC Electronics Corporation 2010
|
||||
* All rights reserved by NEC Electronics Corporation.
|
||||
* This program should be used on your own responsibility.
|
||||
* NEC Electronics Corporation assumes no responsibility for any losses
|
||||
* incurred by customers or third parties arising from the use of this file.
|
||||
*
|
||||
* This device driver was created by Applilet3 for V850ES/Jx3
|
||||
* 32-Bit Single-Chip Microcontrollers
|
||||
* Filename: CG_system.c
|
||||
* Abstract: This file implements device driver for System module.
|
||||
* APIlib: Applilet3 for V850ES/Jx3 V2.01 [20 Apr 2010]
|
||||
* Device: uPD70F3746
|
||||
* Compiler: IAR Systems ICCV850
|
||||
* Creation date: 6/26/2010
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/*
|
||||
*******************************************************************************
|
||||
** Include files
|
||||
*******************************************************************************
|
||||
*/
|
||||
#include "CG_macrodriver.h"
|
||||
#include "CG_system.h"
|
||||
/* Start user code for include. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#include "CG_userdefine.h"
|
||||
|
||||
/*
|
||||
*******************************************************************************
|
||||
** Global define
|
||||
*******************************************************************************
|
||||
*/
|
||||
/* Start user code for global. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
void clock_pll_mode(void)
|
||||
{
|
||||
/* CPU operation clock selection */
|
||||
/* Set PLL mode. */
|
||||
PLLCTL = 0x03; /* bit 1: CPU clock selection (PLL mode/clock-through mode selection) */
|
||||
/* 1: PLL mode, 0: Clock-through mode */
|
||||
|
||||
__asm("_loop: set1 1,0xF82C[r0]"); //__IO_REG8_BIT( PLLCTL, 0xFFFFF82C, __READ_WRITE )
|
||||
__asm(" tst1 1,0xF82C[r0]"); //__IO_REG8_BIT( PLLCTL, 0xFFFFF82C, __READ_WRITE )
|
||||
__asm(" bz _loop");
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
void clock_pcc_mode(void)
|
||||
{
|
||||
/* DMA is forcibly terminated in this sample since DMA transfer must be terminated
|
||||
before data is set to a special register. */
|
||||
|
||||
if(TC0 == 0 && E00 == 1){ /* DMA0 transfer judgment */
|
||||
INIT0 = 1; /* DMA0 forcible termination */
|
||||
}
|
||||
if(TC1 == 0 && E11 == 1){ /* DMA1 transfer judgment */
|
||||
INIT1 = 1; /* DMA1 forcible termination */
|
||||
}
|
||||
if(TC2 == 0 && E22 == 1){ /* DMA2 transfer judgment */
|
||||
INIT2 = 1; /* DMA2 forcible termination */
|
||||
}
|
||||
if(TC3 == 0 && E33 == 1){ /* DMA3 transfer judgment */
|
||||
INIT3 = 1; /* DMA3 forcible termination */
|
||||
}
|
||||
|
||||
/* The PCC register is a special register. Data can be written to this register only in a combination of specific sequences. */
|
||||
/* bit 1, bit 0: Clock selection, 11: fxx/8, 10: fxx/4, 01: fxx/2, 00: fxx */
|
||||
/* Clock selection: fxx */
|
||||
__asm("mov 0x00, r10"); /* Set general-purpose register data to be set to special register. */
|
||||
__asm("st.b r10, 0xF1FC[r0]"); /* Write to PRCMD register. */ //__IO_REG8(PRCMD, 0xFFFFF1FC, __WRITE)
|
||||
__asm("st.b r10, 0xF828[r0]"); /* Set PCC register. */ //__IO_REG8_BIT(PCC, 0xFFFFF828, __READ_WRITE)
|
||||
__asm("nop"); /* Insert five or more NOP instructions. */
|
||||
__asm("nop");
|
||||
__asm("nop");
|
||||
__asm("nop");
|
||||
__asm("nop");
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
**-----------------------------------------------------------------------------
|
||||
**
|
||||
** Abstract:
|
||||
** This function initializes the clock generator module.
|
||||
**
|
||||
** Parameters:
|
||||
** None
|
||||
**
|
||||
** Returns:
|
||||
** None
|
||||
**
|
||||
**-----------------------------------------------------------------------------
|
||||
*/
|
||||
void CLOCK_Init(void)
|
||||
{
|
||||
DI(); /* Maskable interrupt disabled */
|
||||
|
||||
do{
|
||||
clock_pll_mode(); /* PLL mode setting function */
|
||||
|
||||
clock_pcc_mode(); /* PCC register setting function */
|
||||
|
||||
}while(PRERR); /* Written in correct sequence? */
|
||||
}
|
||||
|
||||
/* Start user code for adding. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
|
@ -0,0 +1,172 @@
|
|||
/*
|
||||
*******************************************************************************
|
||||
* Copyright(C) NEC Electronics Corporation 2010
|
||||
* All rights reserved by NEC Electronics Corporation.
|
||||
* This program should be used on your own responsibility.
|
||||
* NEC Electronics Corporation assumes no responsibility for any losses
|
||||
* incurred by customers or third parties arising from the use of this file.
|
||||
*
|
||||
* This device driver was created by Applilet3 for V850ES/Jx3
|
||||
* 32-Bit Single-Chip Microcontrollers
|
||||
* Filename: CG_system.h
|
||||
* Abstract: This file implements device driver for System module.
|
||||
* APIlib: Applilet3 for V850ES/Jx3 V2.01 [20 Apr 2010]
|
||||
* Device: uPD70F3746
|
||||
* Compiler: IAR Systems ICCV850
|
||||
* Creation date: 6/26/2010
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef _MDSYSTEM_
|
||||
#define _MDSYSTEM_
|
||||
/*
|
||||
*******************************************************************************
|
||||
** Register bit define
|
||||
*******************************************************************************
|
||||
*/
|
||||
/*
|
||||
Processor clock control register (PCC)
|
||||
*/
|
||||
#define _03_CG_PCC_INITIALVALUE 0x03U
|
||||
/* Use of subclock on-chip feedback resistor (FRC) */
|
||||
#define _00_CG_SUBCLK_FEEDBACK_USE 0x00U /* subclock on-chip feedback resistor connected */
|
||||
#define _08_CG_SUBCLK_FEEDBACK_UNUSE 0x80U /* subclock on-chip feedback resistor not connected */
|
||||
/* Main clock osillator control (MCK) */
|
||||
#define _00_CG_MAINCLK_ENABLE 0x00U /* main clock oscillation enabled */
|
||||
#define _04_CG_MAINCLK_STOP 0x40U /* main clock oscillation stopped */
|
||||
/* Use of main clock on-chip feedback resistor (MFRC) */
|
||||
#define _00_CG_MAINCLK_FEEDBACK_USE 0x00U /* main clock feedback resistor connected */
|
||||
#define _20_CG_MAINCLK_FEEDBACK_UNUSE 0x20U /* main clock feedback resistor not connected */
|
||||
/* Status of CPU clock fCPU (CLS) */
|
||||
#define _00_CG_CPUCLK_MAINCLK 0x00U /* main clock operation */
|
||||
#define _10_CG_CPUCLK_SUBCLK 0x10U /* subclock operation */
|
||||
/* Clock(fCLK/fCPU) selection (CK3 - CK0) */
|
||||
#define _0F_CG_CPUCLK 0x0FU
|
||||
#define _00_CG_CPUCLK_MAIN0 0x00U /* fCPU = fXX */
|
||||
#define _01_CG_CPUCLK_MAIN1 0x01U /* fCPU = fXX/2 */
|
||||
#define _02_CG_CPUCLK_MAIN2 0x02U /* fCPU = fXX/2^2 */
|
||||
#define _03_CG_CPUCLK_MAIN3 0x03U /* fCPU = fXX/2^3 */
|
||||
#define _04_CG_CPUCLK_MAIN4 0x04U /* fCPU = fXX/2^4 */
|
||||
#define _05_CG_CPUCLK_MAIN5 0x05U /* fCPU = fXX/2^5 */
|
||||
#define _0B_CG_CPUCLK_SUB 0x0BU /* fXT */
|
||||
|
||||
/*
|
||||
Internal oscillator mode register (RCM)
|
||||
*/
|
||||
/* Oscillation/stop of internal oscillator (RSTOP) */
|
||||
#define _00_CG_INTER_OSC_ON 0x00U /* internal oscillator oscillation */
|
||||
#define _01_CG_INTER_OSC_OFF 0x01U /* internal oscillator stopped */
|
||||
|
||||
/*
|
||||
CPU operation clock status register (CCLS)
|
||||
*/
|
||||
/* CPU operation clock status (CCLSF) */
|
||||
#define _00_CG_CPUCLK_STATUS_MAINORSUB 0x00U /* operating on main clock(fX) or subclock(fXT) */
|
||||
#define _01_CG_CPUCLK_STATUS_INTEROSC 0x01U /* operating on internal oscillation clock(fR) */
|
||||
|
||||
/*
|
||||
Lock register (LOCKR)
|
||||
*/
|
||||
/* PLL lock status check (LOCK) */
|
||||
#define _00_CG_PLLSTATUS_LOCK 0x00U /* locked status */
|
||||
#define _01_CG_PLLSTATUS_UNLOCK 0x01U /* unlocked status */
|
||||
|
||||
/*
|
||||
PLL control register (PLLCTL)
|
||||
*/
|
||||
#define _01_CG_PLLCTL_INITIALVALUE 0x01U
|
||||
/* CPU operation clock selection register (SELPLL) */
|
||||
#define _00_CG_CPUCLK_CLKTHROUGH 0x00U /* clock-through mode */
|
||||
#define _02_CG_CPUCLK_PLL 0x02U /* PLL mode */
|
||||
/* PLL operation stop register (PLLON) */
|
||||
#define _00_CG_CPUCLK_PLLOFF 0x00U /* PLL stopped */
|
||||
#define _01_CG_CPUCLK_PLLON 0x01U /* PLL operating */
|
||||
|
||||
/*
|
||||
Clock control register (CKC)
|
||||
*/
|
||||
#define _0A_CG_CKC_INITIALVALUE 0x0AU
|
||||
/* Internal system clock(fXX) in PLL mode */
|
||||
#define _00_CG_CPUCLK_4PLL 0x00U /* fXX = 4* fX (fX = 2.5 to 5.0 MHz) */
|
||||
#define _01_CG_CPUCLK_8PLL 0x01U /* fXX = 8* fX (fX = 2.5 to 4.0 MHz) */
|
||||
|
||||
/*
|
||||
PLL lockup time specification register (PLLS)
|
||||
*/
|
||||
#define _03_CG_PLLS_INITIALVALUE 0x03U
|
||||
/* PLL lockup time selection (PLLS2 - PLLS0) */
|
||||
#define _00_CG_PLLLOCKUP_SEL0 0x00U /* 2^10/fX */
|
||||
#define _01_CG_PLLLOCKUP_SEL1 0x01U /* 2^11/fX*/
|
||||
#define _02_CG_PLLLOCKUP_SEL2 0x02U /* 2^12/fX */
|
||||
#define _03_CG_PLLLOCKUP_SEL3 0x03U /* 2^13/fX (default value) */
|
||||
|
||||
/*
|
||||
Power save control register (PSC)
|
||||
*/
|
||||
/* Stand-by mode release control by occurrence of INTWDT2 signal (NMI1M) */
|
||||
#define _00_CG_STANDBY_INTWDT2EN 0x00U /* enable releasing stand-by mode by INTWDT2 signal */
|
||||
#define _40_CG_STANDBY_INTWDT2DIS 0x40U /* disable releasing stand-by mode by INTWDT2 signal */
|
||||
/* Stand-by mode release control by NMI pin input (NMI0M) */
|
||||
#define _00_CG_STANDBY_NMIEN 0x00U /* enable releasing stand-by mode by NMI pin input */
|
||||
#define _20_CG_STANDBY_NMIDIS 0x20U /* disable releasing stand-by mode by NMI pin input */
|
||||
/* Stand-by mode release control by maskable interrupt request signal (NMI0M) */
|
||||
#define _00_CG_STANDBY_MASKIEN 0x00U /* enable releasing stand-by mode by maskable interrupt request signal */
|
||||
#define _10_CG_STANDBY_MASKIDIS 0x10U /* disable releasing stand-by mode by maskable interrupt request signal */
|
||||
/* Setting of stand-by mode (STP) */
|
||||
#define _00_CG_STANDBY_UNUSE 0x00U /* normal mode */
|
||||
#define _02_CG_STANDBY_USE 0x02U /* stand-by mode */
|
||||
|
||||
/*
|
||||
Power save mode control register (PSMR)
|
||||
*/
|
||||
/* Specification of operation in software stand-by mode (PSM1,PSM0) */
|
||||
#define _00_CG_POWERSAVE_IDLE1 0x00U /* IDLE1, sub-IDLE modes */
|
||||
#define _01_CG_POWERSAVE_STOP1 0x01U /* STOP, sub-IDLE modes */
|
||||
#define _02_CG_POWERSAVE_IDLE2 0x02U /* IDLE2, sub-IDLE modes */
|
||||
#define _03_CG_POWERSAVE_STOP2 0x03U /* STOP mode */
|
||||
|
||||
/*
|
||||
Clock monitor mode register (CLM)
|
||||
*/
|
||||
/* Clock monitor operation enable or disable (CLME) */
|
||||
#define _01_CG_MONITOR_ENABLE 0x01U /* enable clock monitor operation */
|
||||
#define _00_CG_MONITOR_DISABLE 0x00U /* disable clock monitor operation */
|
||||
|
||||
/*
|
||||
Watchdog Timer 2 mode register (WDTM2)
|
||||
*/
|
||||
/* Selection of operation mode (WDM21, WDM20) */
|
||||
#define _00_WDT2_OPERMODE_STOP 0x00U /* stops operation */
|
||||
#define _20_WDT2_OPERMODE_NONMASK 0x20U /* non-maskable interrupt request mode (generation of INTWDT2) */
|
||||
#define _40_WDT2_OPERMODE_RESET 0x40U /* reset mode (generation of RESWDT2) */
|
||||
/* Selection of clock mode (WDCS24,WDCS23) */
|
||||
#define _00_WDT2_CLKMODE_INTEROSC 0x00U /* use internal oscillator */
|
||||
#define _08_WDT2_CLKMODE_MAINCLK 0x08U /* use Main clock */
|
||||
#define _10_WDT2_CLKMODE_SUBCLK 0x10U /* use subclock */
|
||||
/* Watchdog Timer 2 clock Selection (WDCS22 - WDCS20) */
|
||||
#define _00_WDT2_CLOCK_SEL0 0x00U /* 2^12/fR or 2^18/fXX or 2^9/fXT */
|
||||
#define _01_WDT2_CLOCK_SEL1 0x01U /* 2^13/fR or 2^19/fXX or 2^10/fXT */
|
||||
#define _02_WDT2_CLOCK_SEL2 0x02U /* 2^14/fR or 2^20/fXX or 2^11/fXT */
|
||||
#define _03_WDT2_CLOCK_SEL3 0x03U /* 2^15/fR or 2^21/fXX or 2^12/fXT */
|
||||
#define _04_WDT2_CLOCK_SEL4 0x04U /* 2^16/fR or 2^22/fXX or 2^13/fXT */
|
||||
#define _05_WDT2_CLOCK_SEL5 0x05U /* 2^17/fR or 2^23/fXX or 2^14/fXT */
|
||||
#define _06_WDT2_CLOCK_SEL6 0x06U /* 2^18/fR or 2^24/fXX or 2^15/fXT */
|
||||
#define _07_WDT2_CLOCK_SEL7 0x07U /* 2^19/fR or 2^25/fXX or 2^16/fXT */
|
||||
/*
|
||||
*******************************************************************************
|
||||
** Macro define
|
||||
*******************************************************************************
|
||||
*/
|
||||
#define _00_CG_VSWC_VALUE 0x00U
|
||||
/*
|
||||
*******************************************************************************
|
||||
** Function define
|
||||
*******************************************************************************
|
||||
*/
|
||||
void CLOCK_Init(void);
|
||||
void WDT2_Restart(void);
|
||||
void CG_ReadResetSource(void);
|
||||
|
||||
/* Start user code for function. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#endif
|
||||
|
|
@ -0,0 +1,62 @@
|
|||
/*
|
||||
*******************************************************************************
|
||||
* Copyright(C) NEC Electronics Corporation 2010
|
||||
* All rights reserved by NEC Electronics Corporation.
|
||||
* This program should be used on your own responsibility.
|
||||
* NEC Electronics Corporation assumes no responsibility for any losses
|
||||
* incurred by customers or third parties arising from the use of this file.
|
||||
*
|
||||
* This device driver was created by Applilet3 for V850ES/Jx3
|
||||
* 32-Bit Single-Chip Microcontrollers
|
||||
* Filename: CG_system_user.c
|
||||
* Abstract: This file implements device driver for System module.
|
||||
* APIlib: Applilet3 for V850ES/Jx3 V2.01 [20 Apr 2010]
|
||||
* Device: uPD70F3746
|
||||
* Compiler: IAR Systems ICCV850
|
||||
* Creation date: 6/26/2010
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/*
|
||||
*******************************************************************************
|
||||
** Include files
|
||||
*******************************************************************************
|
||||
*/
|
||||
#include "CG_macrodriver.h"
|
||||
#include "CG_system.h"
|
||||
/* Start user code for include. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#include "CG_userdefine.h"
|
||||
|
||||
/*
|
||||
*******************************************************************************
|
||||
** Global define
|
||||
*******************************************************************************
|
||||
*/
|
||||
/* Start user code for global. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/*
|
||||
**-----------------------------------------------------------------------------
|
||||
**
|
||||
** Abstract:
|
||||
** This function processes of Reset.
|
||||
**
|
||||
** Parameters:
|
||||
** None
|
||||
**
|
||||
** Returns:
|
||||
** None
|
||||
**
|
||||
**-----------------------------------------------------------------------------
|
||||
*/
|
||||
void CG_ReadResetSource( void )
|
||||
{
|
||||
UCHAR resetflag = RESF;
|
||||
|
||||
/* Start user code. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
}
|
||||
|
||||
/* Start user code for adding. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
|
@ -0,0 +1,89 @@
|
|||
/*
|
||||
*******************************************************************************
|
||||
* Copyright(C) NEC Electronics Corporation 2010
|
||||
* All rights reserved by NEC Electronics Corporation.
|
||||
* This program should be used on your own responsibility.
|
||||
* NEC Electronics Corporation assumes no responsibility for any losses
|
||||
* incurred by customers or third parties arising from the use of this file.
|
||||
*
|
||||
* This device driver was created by Applilet3 for V850ES/Jx3
|
||||
* 32-Bit Single-Chip Microcontrollers
|
||||
* Filename: CG_systeminit.c
|
||||
* Abstract: This file implements system initializing function.
|
||||
* APIlib: Applilet3 for V850ES/Jx3 V2.01 [20 Apr 2010]
|
||||
* Device: uPD70F3746
|
||||
* Compiler: IAR Systems ICCV850
|
||||
* Creation date: 6/26/2010
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/*
|
||||
*******************************************************************************
|
||||
** Include files
|
||||
*******************************************************************************
|
||||
*/
|
||||
#include "CG_macrodriver.h"
|
||||
#include "CG_system.h"
|
||||
#include "CG_port.h"
|
||||
#include "CG_timer.h"
|
||||
/* Start user code for include. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#include "CG_userdefine.h"
|
||||
|
||||
/*
|
||||
*******************************************************************************
|
||||
** Global define
|
||||
*******************************************************************************
|
||||
*/
|
||||
/* Start user code for global. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
UCHAR __low_level_init(void);
|
||||
void systeminit(void);
|
||||
/*
|
||||
**-----------------------------------------------------------------------------
|
||||
**
|
||||
** Abstract:
|
||||
** This function initializes each macro.
|
||||
**
|
||||
** Parameters:
|
||||
** None
|
||||
**
|
||||
** Returns:
|
||||
** None
|
||||
**
|
||||
**-----------------------------------------------------------------------------
|
||||
*/
|
||||
void systeminit(void)
|
||||
{
|
||||
DI(); /* disable interrupt */
|
||||
CG_ReadResetSource();
|
||||
PORT_Init();
|
||||
TAB0_Init();
|
||||
EI(); /* enable interrupt */
|
||||
}
|
||||
/*
|
||||
**-----------------------------------------------------------------------------
|
||||
**
|
||||
** Abstract:
|
||||
** This function initializes hardware setting.
|
||||
**
|
||||
** Parameters:
|
||||
** None
|
||||
**
|
||||
** Returns:
|
||||
** None
|
||||
**
|
||||
**-----------------------------------------------------------------------------
|
||||
*/
|
||||
UCHAR __low_level_init(void)
|
||||
{
|
||||
VSWC = 0x13U;
|
||||
CLOCK_Init(); /* call Clock_Init function */
|
||||
systeminit();
|
||||
|
||||
return MD_TRUE;
|
||||
}
|
||||
|
||||
/* Start user code for adding. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
|
@ -0,0 +1,200 @@
|
|||
/*
|
||||
*******************************************************************************
|
||||
* Copyright(C) NEC Electronics Corporation 2010
|
||||
* All rights reserved by NEC Electronics Corporation.
|
||||
* This program should be used on your own responsibility.
|
||||
* NEC Electronics Corporation assumes no responsibility for any losses
|
||||
* incurred by customers or third parties arising from the use of this file.
|
||||
*
|
||||
* This device driver was created by Applilet3 for V850ES/Jx3
|
||||
* 32-Bit Single-Chip Microcontrollers
|
||||
* Filename: CG_timer.c
|
||||
* Abstract: This file implements device driver for Timer module.
|
||||
* APIlib: Applilet3 for V850ES/Jx3 V2.01 [20 Apr 2010]
|
||||
* Device: uPD70F3746
|
||||
* Compiler: IAR Systems ICCV850
|
||||
* Creation date: 6/26/2010
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/*
|
||||
*******************************************************************************
|
||||
** Include files
|
||||
*******************************************************************************
|
||||
*/
|
||||
#include "CG_macrodriver.h"
|
||||
#include "CG_timer.h"
|
||||
/* Start user code for include. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#include "CG_userdefine.h"
|
||||
|
||||
/*
|
||||
*******************************************************************************
|
||||
** Global define
|
||||
*******************************************************************************
|
||||
*/
|
||||
/* Count Clock (TABnCTL0) */
|
||||
#define TAB_CNT_CLK 0x00 /* Count Clock fxx */
|
||||
#define TAB_CNT_CLK_2 0x01 /* Count Clock fxx/2 */
|
||||
#define TAB_CNT_CLK_4 0x02 /* Count Clock fxx/4 */
|
||||
#define TAB_CNT_CLK_8 0x03 /* Count Clock fxx/8 */
|
||||
#define TAB_CNT_CLK_16 0x04 /* Count Clock fxx/16 */
|
||||
#define TAB_CNT_CLK_32 0x05 /* Count Clock fxx/32 */
|
||||
#define TAB_CNT_CLK_64 0x06 /* Count Clock fxx/64 */
|
||||
#define TAB_CNT_CLK_128 0x07 /* Count Clock fxx/128 */
|
||||
/* Mode (TABkMD2 + TABkMD1 + TABkMD0) */
|
||||
#define TAB_INTERVAL_MODE 0x00 /* Interval Timer Mode */
|
||||
/* TAB0I/O Control Register (TABmIOC0) */
|
||||
#define TAB_TOB00_DISABLE 0x00 /* TOB00 Output Disable */
|
||||
#define TAB_TOB00_ENABLE 0x01 /* TOB00 Output Enable */
|
||||
#define TAB_TOB00_HI_LEV_ST 0x00 /* TOB00 Output High Level Start */
|
||||
#define TAB_TOB00_LO_LEV_ST 0x02 /* TOB00 Output Low Level Start */
|
||||
#define TAB_TOB01_DISABLE 0x00 /* TOB01 Output Disable */
|
||||
#define TAB_TOB01_ENABLE 0x04 /* TOB01 Output Enable */
|
||||
#define TAB_TOB01_HI_LEV_ST 0x00 /* TOB01 Output High Level Start */
|
||||
#define TAB_TOB01_LO_LEV_ST 0x08 /* TOB01 Output Low Level Start */
|
||||
#define TAB_TOB02_DISABLE 0x00 /* TOB02 Output Disable */
|
||||
#define TAB_TOB02_ENABLE 0x10 /* TOB02 Output Enable */
|
||||
#define TAB_TOB02_HI_LEV_ST 0x00 /* TOB02 Output High Level Start */
|
||||
#define TAB_TOB02_LO_LEV_ST 0x20 /* TOB02 Output Low Level Start */
|
||||
#define TAB_TOB03_DISABLE 0x00 /* TOB03 Output Disable */
|
||||
#define TAB_TOB03_ENABLE 0x40 /* TOB03 Output Enable */
|
||||
#define TAB_TOB03_HI_LEV_ST 0x00 /* TOB03 Output High Level Start */
|
||||
#define TAB_TOB03_LO_LEV_ST 0x80 /* TOB03 Output Low Level Start */
|
||||
/* Start user code for global. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
void timerab_interval(void)
|
||||
{
|
||||
TAB0CTL0 = TAB_CNT_CLK_32; /* TAB0CKS2 = 1 + TAB0CKS1 = 0 + TAB0CKS0 = 0 */
|
||||
/* : Clock Count = fxx/32 */
|
||||
TAB0CTL1 = TAB_INTERVAL_MODE; /* TAB0MD2 = 0 + TAB0MD1 = 0 + TAB0MD0 = 0 */
|
||||
/* : Interval Timer Mode */
|
||||
// TAB0IOC2 = TAB_TOB03_LO_LEV_ST | /* TAB0OL3 = 1 : TOB03 Low Level Start */
|
||||
// TAB_TOB03_DISABLE | /* TAB0OE3 = 0 : TOB03 Output Disable */
|
||||
// TAB_TOB02_LO_LEV_ST | /* TAB0OL2 = 1 : TOB02 Low Level Start */
|
||||
// TAB_TOB02_DISABLE | /* TAB0OE2 = 0 : TOB02 Output Disable */
|
||||
// TAB_TOB01_HI_LEV_ST | /* TAB0OL1 = 0 : TOB01 High Level Start */
|
||||
// TAB_TOB01_ENABLE | /* TAB0OE1 = 1 : TOB01 Output Enable */
|
||||
// TAB_TOB00_HI_LEV_ST | /* TAB0OL0 = 0 : TOB00 High Level Start */
|
||||
// TAB_TOB00_ENABLE; /* TAB0OE0 = 1 : TOB00 Output Enable */
|
||||
TAB0CCR0 = 19999; /* Compare Register */
|
||||
TAB0CCR1 = 0xFFFF; /* Compare Register */
|
||||
TAB0CCR2 = 0xFFFF; /* No Use */
|
||||
TAB0CCR3 = 0xFFFF; /* No Use */
|
||||
}
|
||||
|
||||
/*
|
||||
**-----------------------------------------------------------------------------
|
||||
**
|
||||
** Abstract:
|
||||
** This function initializes the TAB0 module.
|
||||
**
|
||||
** Parameters:
|
||||
** None
|
||||
**
|
||||
** Returns:
|
||||
** None
|
||||
**
|
||||
**-----------------------------------------------------------------------------
|
||||
*/
|
||||
void TAB0_Init(void)
|
||||
{
|
||||
TAB0CE = 0; /* Stop TAB */
|
||||
|
||||
/* Port Definition */
|
||||
// PFC1 = 0x00; /* PFC17 = 0 : TOB00 Output */
|
||||
/* PFC10 = 0 : TOB01 Output */
|
||||
// PFCE1 = 0x01; /* PFCE10 = 1 : TOB01 Output */
|
||||
// PMC1 = 0x81; /* PMC17 = 1 : TOB00 Output/INTP09 Input */
|
||||
/* PMC10 = 1 : TOB0T1 Output/TIB01 Input/TOB01 Output */
|
||||
|
||||
/* Enable Interrupt */
|
||||
TB0CCMK0 = 0; /* TB0CCMK0 = 0 : INTTB0CC0 Enable */
|
||||
TB0CCMK1 = 1; /* TB0CCMK1 = 0 : INTTB0CC1 Enable */
|
||||
TB0CCMK2 = 1; /* TB0CCMK2 = 1 : INTTB0CC2 Disable */
|
||||
TB0CCMK3 = 1; /* TB0CCMK3 = 1 : INTTB0CC3 Disable */
|
||||
|
||||
timerab_interval();
|
||||
}
|
||||
/*
|
||||
**-----------------------------------------------------------------------------
|
||||
**
|
||||
** Abstract:
|
||||
** This function starts TMP0 counter.
|
||||
**
|
||||
** Parameters:
|
||||
** None
|
||||
**
|
||||
** Returns:
|
||||
** None
|
||||
**
|
||||
**-----------------------------------------------------------------------------
|
||||
*/
|
||||
void TAB0_Start(void)
|
||||
{
|
||||
TB0CCIF0 = 0U; /* clear INTTP0CC0 interrupt flag */
|
||||
TB0CCMK0 = 0U; /* enable INTTP0CC0 interrupt */
|
||||
TAB0CE = 1U; /* enable TMP0 operation */
|
||||
}
|
||||
/*
|
||||
**-----------------------------------------------------------------------------
|
||||
**
|
||||
** Abstract:
|
||||
** This function stops TMP0 counter.
|
||||
**
|
||||
** Parameters:
|
||||
** None
|
||||
**
|
||||
** Returns:
|
||||
** None
|
||||
**
|
||||
**-----------------------------------------------------------------------------
|
||||
*/
|
||||
void TAB0_Stop(void)
|
||||
{
|
||||
TAB0CE = 0U; /* disable TMP0 operation */
|
||||
TB0CCMK0 = 1U; /* disable INTTP0CC0 interrupt */
|
||||
TB0CCIF0 = 0U; /* clear INTTP0CC0 interrupt flag */
|
||||
}
|
||||
/*
|
||||
**-----------------------------------------------------------------------------
|
||||
**
|
||||
** Abstract:
|
||||
** This function changes TMP0 register value.
|
||||
**
|
||||
** Parameters:
|
||||
** array_reg: register value buffer
|
||||
** array_num: register index to be changed
|
||||
**
|
||||
** Returns:
|
||||
** MD_OK
|
||||
** MD_ARGERROR
|
||||
**
|
||||
**-----------------------------------------------------------------------------
|
||||
*/
|
||||
MD_STATUS TAB0_ChangeTimerCondition(USHORT *array_reg, UCHAR array_num)
|
||||
{
|
||||
MD_STATUS status = MD_OK;
|
||||
|
||||
switch (array_num)
|
||||
{
|
||||
case 1U:
|
||||
TAB0CCR0 = array_reg[0U];
|
||||
status = MD_OK;
|
||||
break;
|
||||
case 2U:
|
||||
TAB0CCR0 = array_reg[0U];
|
||||
TAB0CCR1 = array_reg[1U];
|
||||
status = MD_OK;
|
||||
break;
|
||||
default:
|
||||
status = MD_ARGERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
return (status);
|
||||
}
|
||||
|
||||
/* Start user code for adding. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
|
@ -0,0 +1,278 @@
|
|||
/*
|
||||
*******************************************************************************
|
||||
* Copyright(C) NEC Electronics Corporation 2010
|
||||
* All rights reserved by NEC Electronics Corporation.
|
||||
* This program should be used on your own responsibility.
|
||||
* NEC Electronics Corporation assumes no responsibility for any losses
|
||||
* incurred by customers or third parties arising from the use of this file.
|
||||
*
|
||||
* This device driver was created by Applilet3 for V850ES/Jx3
|
||||
* 32-Bit Single-Chip Microcontrollers
|
||||
* Filename: CG_timer.h
|
||||
* Abstract: This file implements device driver for Timer module.
|
||||
* APIlib: Applilet3 for V850ES/Jx3 V2.01 [20 Apr 2010]
|
||||
* Device: uPD70F3746
|
||||
* Compiler: IAR Systems ICCV850
|
||||
* Creation date: 6/26/2010
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef _MDTIMER_
|
||||
#define _MDTIMER_
|
||||
/*
|
||||
*******************************************************************************
|
||||
** Register bit define
|
||||
*******************************************************************************
|
||||
*/
|
||||
/*
|
||||
TMP control register 0 (TPnCTL0)
|
||||
*/
|
||||
/* TMP operation control (TPnCE) */
|
||||
#define _00_TMP_OPERATION_DISABLE 0x00U /* disable internal operating clock operation (asynchronously reset TMPn) */
|
||||
#define _80_TMP_OPERATION_ENABLE 0x80U /* enable internal operating clock operation */
|
||||
/* Internal count clock selection (TPnCKS2 - TPnCKS0) */
|
||||
#define _00_TMP_INTERNAL_CLOCK0 0x00U /* fXX */
|
||||
#define _01_TMP_INTERNAL_CLOCK1 0x01U /* fXX/2 */
|
||||
#define _02_TMP_INTERNAL_CLOCK2 0x02U /* fXX/2^2 */
|
||||
#define _03_TMP_INTERNAL_CLOCK3 0x03U /* fXX/2^3 */
|
||||
#define _04_TMP_INTERNAL_CLOCK4 0x04U /* fXX/2^4 */
|
||||
#define _05_TMP_INTERNAL_CLOCK5 0x05U /* fXX/2^5 */
|
||||
#define _06_TMP_INTERNAL_CLOCK6 0x06U /* fXX/2^6 or fXX/2^8 */
|
||||
#define _07_TMP_INTERNAL_CLOCK7 0x07U /* fXX/2^7 or fXX/2^9 */
|
||||
|
||||
/*
|
||||
TMP control register 1 (TPnCTL1)
|
||||
*/
|
||||
/* Software trigger control (TPnEST) */
|
||||
#define _00_TMP_SOFTTRIGGER_OFF 0x00U /* no operation */
|
||||
#define _40_TMP_SOFTTRIGGER_ON 0x40U /* in one-shot pulse mode: One-shot pulse software trigger */
|
||||
/* in external trigger pulse output mode: Pulse output software trigger */
|
||||
/* Count clock selection (TPnEEE) */
|
||||
#define _00_TMP_INTERNAL_CLOCK 0x00U /* use the internal clock (clock selected with bits TPnCKS2 to TPnCKS0) */
|
||||
#define _20_TMP_EXTERNAL_CLOCK 0x20U /* use the external clock from the TIPn0 input pin */
|
||||
/* Timer mode selection (TPnMD2 - TPnMD0) */
|
||||
#define _00_TMP_MODE_INTERVAL 0x00U /* interval timer mode */
|
||||
#define _01_TMP_MODE_EXTERNALCOUNT 0x01U /* external event counter mode */
|
||||
#define _02_TMP_MODE_EXTERNALTRG 0x02U /* external trigger pulse output mode */
|
||||
#define _03_TMP_MODE_ONESHOT 0x03U /* one-shot pulse mode */
|
||||
#define _04_TMP_MODE_PWM 0x04U /* PWM mode */
|
||||
#define _05_TMP_MODE_FREERUNNING 0x05U /* free-running mode */
|
||||
#define _06_TMP_MODE_PULSEMEASURE 0x06U /* pulse width measurement mode */
|
||||
|
||||
/*
|
||||
TMP I/O control register 0 (TPnIOC0)
|
||||
*/
|
||||
/* TOPn0 pin output level setting (TPnOL0) */
|
||||
#define _00_TMP_OUTPUT0_NORMAL 0x00U /* normal output */
|
||||
#define _02_TMP_OUTPUT0_INVERTED 0x02U /* inverted output */
|
||||
/* TOPn0 pin output setting (TPnOE0) */
|
||||
#define _00_TMP_OUTPUT0_DISABLE 0x00U /* disable timer output */
|
||||
#define _01_TMP_OUTPUT0_ENABLE 0x01U /* enable timer output (TOPn0 pin outputs pulses) */
|
||||
/* TOPn1 pin output level setting (TPnOL1) */
|
||||
#define _00_TMP_OUTPUT1_NORMAL 0x00U /* normal output */
|
||||
#define _08_TMP_OUTPUT1_INVERTED 0x08U /* inverted output */
|
||||
/* TOPn1 pin output setting (TPnOE1) */
|
||||
#define _00_TMP_OUTPUT1_DISABLE 0x00U /* disable timer output */
|
||||
#define _04_TMP_OUTPUT1_ENABLE 0x04U /* enable timer output (TOPn1 pin outputs pulses) */
|
||||
|
||||
/*
|
||||
TMP I/O control register 1 (TPnIOC1)
|
||||
*/
|
||||
/* Capture trigger input signal (TIPn1 pin) valid edge setting (TPnIS3,TPnIS2) */
|
||||
#define _00_TMP_INPUT1_EDGE_NONE 0x00U /* detect no edge (capture operation is invalid) */
|
||||
#define _04_TMP_INPUT1_EDGE_RISING 0x04U /* detection of rising edge */
|
||||
#define _08_TMP_INPUT1_EDGE_FALLING 0x08U /* detection of falling edge */
|
||||
#define _0C_TMP_INPUT1_EDGE_BOTH 0x0CU /* detection of both edges */
|
||||
/* Capture trigger input signal (TIPn0 pin) valid edge setting (TPnIS1,TPnIS0) */
|
||||
#define _00_TMP_INPUT0_EDGE_NONE 0x00U /* detect no edge (capture operation is invalid) */
|
||||
#define _01_TMP_INPUT0_EDGE_RISING 0x01U /* detection of rising edge */
|
||||
#define _02_TMP_INPUT0_EDGE_FALLING 0x02U /* detection of falling edge */
|
||||
#define _03_TMP_INPUT0_EDGE_BOTH 0x03U /* detection of both edges */
|
||||
|
||||
/*
|
||||
TMP I/O control register 2 (TPnIOC2)
|
||||
*/
|
||||
/* External event count input signal (TIPn0 pin) valid edge setting (TPnEES1,TPnEES0) */
|
||||
#define _00_TMP_EXTCOUNT_EDGE_NONE 0x00U /* detect no edge (external event count is invalid) */
|
||||
#define _04_TMP_EXTCOUNT_EDGE_RISING 0x04U /* detection of rising edge */
|
||||
#define _08_TMP_EXTCOUNT_EDGE_FALLING 0x08U /* detection of falling edge */
|
||||
#define _0C_TMP_EXTCOUNT_EDGE_BOTH 0x0CU /* detection of both edges */
|
||||
/* External trigger input signal (TIPn0 pin) valid edge setting (TPnETS1,TPnETS0) */
|
||||
#define _00_TMP_EXTTRIGGER_EDGE_NONE 0x00U /* detect no edge (external trigger is invalid) */
|
||||
#define _01_TMP_EXTTRIGGER_EDGE_RISING 0x01U /* detection of rising edge */
|
||||
#define _02_TMP_EXTTRIGGER_EDGE_FALLING 0x02U /* detection of falling edge */
|
||||
#define _03_TMP_EXTTRIGGER_EDGE_BOTH 0x03U /* detection of both edges */
|
||||
|
||||
/*
|
||||
TMP option register 0 (TPnOPT0)
|
||||
*/
|
||||
/* TPnCCR1 register capture/compare selection (TPnCCS1) */
|
||||
#define _00_TMP_CCR1_COMPARE 0x00U /* compare register */
|
||||
#define _20_TMP_CCR1_CAPTURE 0x20U /* capture register */
|
||||
/* TPnCCR0 register capture/compare selection (TPnCCS0) */
|
||||
#define _00_TMP_CCR0_COMPARE 0x00U /* compare register */
|
||||
#define _10_TMP_CCR0_CAPTURE 0x10U /* capture register */
|
||||
/* TMPn overflow detection flag (TPnOVF) */
|
||||
#define _01_TMP_OVERFLOW_OCCUR 0x01U /* overflow occurred */
|
||||
#define _00_TMP_OVERFLOW_CLEAR 0x00U /* clear overflow */
|
||||
|
||||
/*
|
||||
TMQ0 control register 0 (TQ0CTL0)
|
||||
*/
|
||||
/* TMQ operation control (TQ0CE) */
|
||||
#define _00_TMQ_OPERATION_DISABLE 0x00U /* disable internal operating clock operation (asynchronously reset TMQ0) */
|
||||
#define _80_TMQ_OPERATION_ENABLE 0x80U /* enable internal operating clock operation */
|
||||
/* Internal count clock selection (TQ0CKS2 - TQ0CKS0) */
|
||||
#define _00_TMQ_INTERNAL_CLOCK0 0x00U /* fXX */
|
||||
#define _01_TMQ_INTERNAL_CLOCK1 0x01U /* fXX/2 */
|
||||
#define _02_TMQ_INTERNAL_CLOCK2 0x02U /* fXX/2^2 */
|
||||
#define _03_TMQ_INTERNAL_CLOCK3 0x03U /* fXX/2^3 */
|
||||
#define _04_TMQ_INTERNAL_CLOCK4 0x04U /* fXX/2^4 */
|
||||
#define _05_TMQ_INTERNAL_CLOCK5 0x05U /* fXX/2^5 */
|
||||
#define _06_TMQ_INTERNAL_CLOCK6 0x06U /* fXX/2^6 */
|
||||
#define _07_TMQ_INTERNAL_CLOCK7 0x07U /* fXX/2^7 */
|
||||
|
||||
/*
|
||||
TMQ0 control register 1 (TQ0CTL1)
|
||||
*/
|
||||
/* Software trigger control (TQ0EST) */
|
||||
#define _00_TMQ_SOFTTRIGGER_OFF 0x00U /* no operation */
|
||||
#define _40_TMQ_SOFTTRIGGER_ON 0x40U /* in one-shot pulse mode: One-shot pulse software trigger */
|
||||
/* in external trigger pulse output mode: Pulse output software trigger */
|
||||
/* Count clock selection (TQ0EEE) */
|
||||
#define _00_TMQ_INTERNAL_CLOCK 0x00U /* use the internal clock (clock selected with bits TQ0CKS2 to TQ0CKS0) */
|
||||
#define _20_TMQ_EXTERNAL_CLOCK 0x20U /* use the external clock from the TIQ00 input pin */
|
||||
/* Timer mode selection (TQ0MD2 - TQ0MD0) */
|
||||
#define _00_TMQ_MODE_INTERVAL 0x00U /* interval timer mode */
|
||||
#define _01_TMQ_MODE_EXTERNALCOUNT 0x01U /* external event counter mode */
|
||||
#define _02_TMQ_MODE_EXTERNALTRG 0x02U /* external trigger pulse output mode */
|
||||
#define _03_TMQ_MODE_ONESHOT 0x03U /* one-shot pulse mode */
|
||||
#define _04_TMQ_MODE_PWM 0x04U /* PWM mode */
|
||||
#define _05_TMQ_MODE_FREERUNNING 0x05U /* free-running mode */
|
||||
#define _06_TMQ_MODE_PULSEMEASURE 0x06U /* pulse width measurement mode */
|
||||
|
||||
/*
|
||||
TMQ0 I/O control register 0 (TQ0IOC0)
|
||||
*/
|
||||
/* TOQ00 pin output level setting (TQ0OL0) */
|
||||
#define _00_TMQ_OUTPUT0_NORMAL 0x00U /* normal output */
|
||||
#define _02_TMQ_OUTPUT0_INVERTED 0x02U /* inverted output */
|
||||
/* TOQ00 pin output setting (TQ0OE0) */
|
||||
#define _00_TMQ_OUTPUT0_DISABLE 0x00U /* disable timer output */
|
||||
#define _01_TMQ_OUTPUT0_ENABLE 0x01U /* enable timer output (TOQ00 pin outputs pulses) */
|
||||
/* TOQ01 pin output level setting (TQ0OL1) */
|
||||
#define _00_TMQ_OUTPUT1_NORMAL 0x00U /* normal output */
|
||||
#define _08_TMQ_OUTPUT1_INVERTED 0x08U /* inverted output */
|
||||
/* TOQ01 pin output setting (TQ0OE1) */
|
||||
#define _00_TMQ_OUTPUT1_DISABLE 0x00U /* disable timer output */
|
||||
#define _04_TMQ_OUTPUT1_ENABLE 0x04U /* enable timer output (TOQ01 pin outputs pulses) */
|
||||
/* TOQ02 pin output level setting (TQ0OL2) */
|
||||
#define _00_TMQ_OUTPUT2_NORMAL 0x00U /* normal output */
|
||||
#define _20_TMQ_OUTPUT2_INVERTED 0x20U /* inverted output */
|
||||
/* TOQ02 pin output setting (TQ0OE2) */
|
||||
#define _00_TMQ_OUTPUT2_DISABLE 0x00U /* disable timer output */
|
||||
#define _10_TMQ_OUTPUT2_ENABLE 0x10U /* enable timer output (TOQ02 pin outputs pulses) */
|
||||
/* TOQ03 pin output level setting (TQ0OL3) */
|
||||
#define _00_TMQ_OUTPUT3_NORMAL 0x00U /* normal output */
|
||||
#define _80_TMQ_OUTPUT3_INVERTED 0x80U /* inverted output */
|
||||
/* TOQ03 pin output setting (TQ0OE3) */
|
||||
#define _00_TMQ_OUTPUT3_DISABLE 0x00U /* disable timer output */
|
||||
#define _40_TMQ_OUTPUT3_ENABLE 0x40U /* enable timer output (TOQ03 pin outputs pulses) */
|
||||
|
||||
/*
|
||||
TMQ0 I/O control register 1 (TQ0IOC1)
|
||||
*/
|
||||
/* Capture trigger input signal (TIQ00 pin) valid edge setting (TQ0IS1,TQ0IS0) */
|
||||
#define _00_TMQ_INPUT0_EDGE_NONE 0x00U /* detect no edge (capture operation is invalid) */
|
||||
#define _01_TMQ_INPUT0_EDGE_RISING 0x01U /* detection of rising edge */
|
||||
#define _02_TMQ_INPUT0_EDGE_FALLING 0x02U /* detection of falling edge */
|
||||
#define _03_TMQ_INPUT0_EDGE_BOTH 0x03U /* detection of both edges */
|
||||
/* Capture trigger input signal (TIQ01 pin) valid edge setting (TQ0IS3,TQ0IS2) */
|
||||
#define _00_TMQ_INPUT1_EDGE_NONE 0x00U /* detect no edge (capture operation is invalid) */
|
||||
#define _04_TMQ_INPUT1_EDGE_RISING 0x04U /* detection of rising edge */
|
||||
#define _08_TMQ_INPUT1_EDGE_FALLING 0x08U /* detection of falling edge */
|
||||
#define _0C_TMQ_INPUT1_EDGE_BOTH 0x0CU /* detection of both edges */
|
||||
/* Capture trigger input signal (TIQ02 pin) valid edge setting (TQ0IS5,TQ0IS4) */
|
||||
#define _00_TMQ_INPUT2_EDGE_NONE 0x00U /* detect no edge (capture operation is invalid) */
|
||||
#define _10_TMQ_INPUT2_EDGE_RISING 0x10U /* detection of rising edge */
|
||||
#define _20_TMQ_INPUT2_EDGE_FALLING 0x20U /* detection of falling edge */
|
||||
#define _30_TMQ_INPUT2_EDGE_BOTH 0x30U /* detection of both edges */
|
||||
/* Capture trigger input signal (TIQ03 pin) valid edge setting (TQ0IS7,TQ0IS6) */
|
||||
#define _00_TMQ_INPUT3_EDGE_NONE 0x00U /* detect no edge (capture operation is invalid) */
|
||||
#define _40_TMQ_INPUT3_EDGE_RISING 0x40U /* detection of rising edge */
|
||||
#define _80_TMQ_INPUT3_EDGE_FALLING 0x80U /* detection of falling edge */
|
||||
#define _C0_TMQ_INPUT3_EDGE_BOTH 0xC0U /* detection of both edges */
|
||||
|
||||
/*
|
||||
TMQ0 I/O control register 2 (TQ0IOC2)
|
||||
*/
|
||||
/* External event count input signal (TIQ00 pin) valid edge setting (TQ0EES1,TQ0EES0) */
|
||||
#define _00_TMQ_EXTCOUNT_EDGE_NONE 0x00U /* detect no edge (external event count is invalid) */
|
||||
#define _04_TMQ_EXTCOUNT_EDGE_RISING 0x04U /* detection of rising edge */
|
||||
#define _08_TMQ_EXTCOUNT_EDGE_FALLING 0x08U /* detection of falling edge */
|
||||
#define _0C_TMQ_EXTCOUNT_EDGE_BOTH 0x0CU /* detection of both edges */
|
||||
/* External trigger input signal (TIQ00 pin) valid edge setting (TQ0ETS1,TQ0ETS0) */
|
||||
#define _00_TMQ_EXTTRIGGER_EDGE_NONE 0x00U /* detect no edge (external trigger is invalid) */
|
||||
#define _01_TMQ_EXTTRIGGER_EDGE_RISING 0x01U /* detection of rising edge */
|
||||
#define _02_TMQ_EXTTRIGGER_EDGE_FALLING 0x02U /* detection of falling edge */
|
||||
#define _03_TMQ_EXTTRIGGER_EDGE_BOTH 0x03U /* detection of both edges */
|
||||
|
||||
/*
|
||||
TMQ0 option register 0 (TQ0OPT0)
|
||||
*/
|
||||
/* TQ0CCR3 register capture/compare selection (TQ0CCS3) */
|
||||
#define _00_TMQ_CCR3_COMPARE 0x00U /* compare register */
|
||||
#define _80_TMQ_CCR3_CAPTURE 0x80U /* capture register */
|
||||
/* TQ0CCR2 register capture/compare selection (TQ0CCS2) */
|
||||
#define _00_TMQ_CCR2_COMPARE 0x00U /* compare register */
|
||||
#define _40_TMQ_CCR2_CAPTURE 0x40U /* capture register */
|
||||
/* TQ0CCR1 register capture/compare selection (TQ0CCS1) */
|
||||
#define _00_TMQ_CCR1_COMPARE 0x00U /* compare register */
|
||||
#define _20_TMQ_CCR1_CAPTURE 0x20U /* capture register */
|
||||
/* TQ0CCR0 register capture/compare selection (TQ0CCS0) */
|
||||
#define _00_TMQ_CCR0_COMPARE 0x00U /* compare register */
|
||||
#define _10_TMQ_CCR0_CAPTURE 0x10U /* capture register */
|
||||
/* TMQ0 overflow detection flag (TQ0OVF) */
|
||||
#define _01_TMQ_OVERFLOW_OCCUR 0x01U /* overflow occurred */
|
||||
#define _00_TMQ_OVERFLOW_CLEAR 0x00U /* clear overflow */
|
||||
|
||||
/*
|
||||
TMM0 control register 0 (TM0CTL0)
|
||||
*/
|
||||
/* TMM0 operation control (TM0CE) */
|
||||
#define _00_TMM_OPERATION_DISABLE 0x00U /* disable internal operating clock operation (asynchronously reset TMM0) */
|
||||
#define _80_TMM_OPERATION_ENABLE 0x80U /* enable internal operating clock operation */
|
||||
/* Internal count clock selection (TM0CKS2 - TM0CKS0) */
|
||||
#define _00_TMM_INTERNAL_CLOCK0 0x00U /* fXX */
|
||||
#define _01_TMM_INTERNAL_CLOCK1 0x01U /* fXX/2 */
|
||||
#define _02_TMM_INTERNAL_CLOCK2 0x02U /* fXX/4 */
|
||||
#define _03_TMM_INTERNAL_CLOCK3 0x03U /* fXX/64 */
|
||||
#define _04_TMM_INTERNAL_CLOCK4 0x04U /* fXX/512 */
|
||||
#define _05_TMM_INTERNAL_CLOCK5 0x05U /* INTWT */
|
||||
#define _06_TMM_INTERNAL_CLOCK6 0x06U /* fR/8 */
|
||||
#define _07_TMM_INTERNAL_CLOCK7 0x07U /* fXT */
|
||||
/*
|
||||
*******************************************************************************
|
||||
** Macro define
|
||||
*******************************************************************************
|
||||
*/
|
||||
/* TMP0 compare register 0 (TP0CCR0)*/
|
||||
#define _9C3F_TMP0_CCR0_VALUE 0x9C3FU
|
||||
enum TMChannel
|
||||
{
|
||||
TMCHANNEL0, TMCHANNEL1, TMCHANNEL2, TMCHANNEL3
|
||||
};
|
||||
/*
|
||||
*******************************************************************************
|
||||
** Function define
|
||||
*******************************************************************************
|
||||
*/
|
||||
void TAB0_Init(void);
|
||||
void TAB0_Start(void);
|
||||
void TAB0_Stop(void);
|
||||
MD_STATUS TAB0_ChangeTimerCondition(USHORT *array_reg, UCHAR array_num);
|
||||
__interrupt void MD_INTTP0CC0(void);
|
||||
|
||||
/* Start user code for function. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#endif
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
/*
|
||||
*******************************************************************************
|
||||
* Copyright(C) NEC Electronics Corporation 2010
|
||||
* All rights reserved by NEC Electronics Corporation.
|
||||
* This program should be used on your own responsibility.
|
||||
* NEC Electronics Corporation assumes no responsibility for any losses
|
||||
* incurred by customers or third parties arising from the use of this file.
|
||||
*
|
||||
* This device driver was created by Applilet3 for V850ES/Jx3
|
||||
* 32-Bit Single-Chip Microcontrollers
|
||||
* Filename: CG_timer_user.c
|
||||
* Abstract: This file implements device driver for Timer module.
|
||||
* APIlib: Applilet3 for V850ES/Jx3 V2.01 [20 Apr 2010]
|
||||
* Device: uPD70F3746
|
||||
* Compiler: IAR Systems ICCV850
|
||||
* Creation date: 6/26/2010
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/*
|
||||
*******************************************************************************
|
||||
** Include files
|
||||
*******************************************************************************
|
||||
*/
|
||||
#include "CG_macrodriver.h"
|
||||
#include "CG_timer.h"
|
||||
/* Start user code for include. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#include "CG_userdefine.h"
|
||||
|
||||
/*
|
||||
*******************************************************************************
|
||||
** Global define
|
||||
*******************************************************************************
|
||||
*/
|
||||
/* Start user code for global. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/*
|
||||
**-----------------------------------------------------------------------------
|
||||
**
|
||||
** Abstract:
|
||||
** This function is INTTP0CC0 interrupt service routine.
|
||||
**
|
||||
** Parameters:
|
||||
** None
|
||||
**
|
||||
** Returns:
|
||||
** None
|
||||
**
|
||||
**-----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
///#pragma vector = INTTB0CC0_vector
|
||||
///__interrupt void MD_INTTB0CC0(void)
|
||||
///{
|
||||
/* Start user code. Do not edit comment generated here */
|
||||
/// PDLH = ~PDLH;
|
||||
/* End user code. Do not edit comment generated here */
|
||||
///}
|
||||
|
||||
/* Start user code for adding. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/*
|
||||
*******************************************************************************
|
||||
* Copyright(C) NEC Electronics Corporation 2010
|
||||
* All rights reserved by NEC Electronics Corporation.
|
||||
* This program should be used on your own responsibility.
|
||||
* NEC Electronics Corporation assumes no responsibility for any losses
|
||||
* incurred by customers or third parties arising from the use of this file.
|
||||
*
|
||||
* This device driver was created by Applilet3 for V850ES/Jx3
|
||||
* 32-Bit Single-Chip Microcontrollers
|
||||
* Filename: CG_userdefine.h
|
||||
* Abstract: This file includes user definition.
|
||||
* APIlib: Applilet3 for V850ES/Jx3 V2.01 [20 Apr 2010]
|
||||
* Device: uPD70F3746
|
||||
* Compiler: IAR Systems ICCV850
|
||||
* Creation date: 6/26/2010
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef _MD_USER_DEF_
|
||||
#define _MD_USER_DEF_
|
||||
/*
|
||||
*******************************************************************************
|
||||
** User define
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/* Start user code for function. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#endif
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
from building import *
|
||||
import rtconfig
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src_c = Glob('*.c')
|
||||
|
||||
# add for startup script
|
||||
if rtconfig.CROSS_TOOL == 'gcc':
|
||||
src_asm = ['start_gcc.S', 'vectors_gcc.S', 'interrupts_gcc.S']
|
||||
elif rtconfig.CROSS_TOOL == 'iar':
|
||||
src_asm = ['cstartup.asm']
|
||||
|
||||
src = File(src_c + src_asm)
|
||||
|
||||
CPPPATH = [cwd]
|
||||
|
||||
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
Return('group')
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* File : board.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2009, RT-Thread Development Team
|
||||
* COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
|
|
@ -21,7 +21,7 @@
|
|||
#include "uart.h"
|
||||
#include "board.h"
|
||||
|
||||
void rt_hw_board_init()
|
||||
void rt_hw_board_init(void)
|
||||
{
|
||||
#ifdef RT_USING_UART0
|
||||
rt_hw_uart_init();
|
||||
|
|
@ -30,4 +30,3 @@ void rt_hw_board_init()
|
|||
|
||||
rt_kprintf("\r\n\r\nSystemInit......\r\n");
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,839 @@
|
|||
;-----------------------------------------------------------------------------
|
||||
; This file contains the startup code used by the V850 C/C++ compiler.
|
||||
;
|
||||
; Copyright (c) 1998-2009 IAR Systems AB.
|
||||
;
|
||||
; $Revision: 5028 $
|
||||
;
|
||||
;-----------------------------------------------------------------------------
|
||||
|
||||
;
|
||||
; Naming covention of labels in this file:
|
||||
;
|
||||
; ?xxx - External labels only accessed from assembler.
|
||||
; __xxx - External labels accessed from or defined in C.
|
||||
; xxx - Labels local to one module (note: this file contains
|
||||
; several modules).
|
||||
; main - The starting point of the user program.
|
||||
;
|
||||
|
||||
#include "lxx.h"
|
||||
#include "cfi.h"
|
||||
|
||||
CASEON
|
||||
|
||||
#define A0 R1
|
||||
#define A1 R5
|
||||
#define A2 R6
|
||||
|
||||
;---------------------------------------------------------------;
|
||||
; Call Frame Informatio ;
|
||||
;---------------------------------------------------------------;
|
||||
|
||||
CFNAMES
|
||||
CFCOMMON
|
||||
|
||||
;---------------------------------------------------------------;
|
||||
; Reset Vector ;
|
||||
;---------------------------------------------------------------;
|
||||
|
||||
MODULE ?RESET
|
||||
|
||||
PUBLIC ?creset
|
||||
EXTERN __program_start
|
||||
|
||||
COMMON INTVEC:CODE:ROOT(2)
|
||||
|
||||
?creset:
|
||||
MOV __program_start, R1
|
||||
JMP [R1]
|
||||
|
||||
ENDMOD
|
||||
|
||||
;---------------------------------------------------------------;
|
||||
; Module start. ;
|
||||
;---------------------------------------------------------------;
|
||||
|
||||
MODULE __program_start
|
||||
|
||||
PUBLIC __program_start
|
||||
PUBLIC ?cstartup
|
||||
EXTERN ?creset
|
||||
REQUIRE ?creset
|
||||
|
||||
;---------------------------------------------------------------;
|
||||
; Forward declarations of segments used in this module. ;
|
||||
;---------------------------------------------------------------;
|
||||
|
||||
RSEG CODE:CODE:NOROOT(2)
|
||||
RSEG CSTACK:DATA(2)
|
||||
|
||||
;---------------------------------------------------------------;
|
||||
; The startup code. ;
|
||||
;---------------------------------------------------------------;
|
||||
|
||||
RSEG CSTART:CODE:NOROOT(1)
|
||||
|
||||
;;
|
||||
;; The startup sequence contained in the final linked
|
||||
;; application will consist of a mosaic containing
|
||||
;; modules and segment parts defined in this file.
|
||||
;;
|
||||
;; The only part which is required is the call to
|
||||
;; the function "main".
|
||||
;;
|
||||
|
||||
EXTERN ?cstart_call_main
|
||||
REQUIRE ?cstart_call_main
|
||||
|
||||
EXTERN __cstart_low_level_init
|
||||
REQUIRE __cstart_low_level_init
|
||||
|
||||
PUBLIC ?BTT_cstart_begin
|
||||
?BTT_cstart_begin:
|
||||
|
||||
?cstartup:
|
||||
__program_start:
|
||||
|
||||
;---------------------------------------------------------------;
|
||||
; Set up the stack and the global pointer. ;
|
||||
;---------------------------------------------------------------;
|
||||
|
||||
#if __CORE__ == __CORE_V850__
|
||||
;; If an interrupt is issued beteween the MOVEA and
|
||||
;; MOVHI instructions the SP will point into
|
||||
;; nowhere. To fix this problem we build the new SP
|
||||
;; value in R1 and moves it with an atomic operation
|
||||
;; to SP.
|
||||
MOVE_M SFE CSTACK, R1
|
||||
MOV R1, SP
|
||||
#else
|
||||
MOVE_M SFE CSTACK, SP
|
||||
#endif
|
||||
|
||||
EXTERN ?BREL_BASE
|
||||
MOVE_M ?BREL_BASE + 0x8000, GP
|
||||
|
||||
EXTERN ?BREL_CBASE
|
||||
MOVE_M ?BREL_CBASE + 0x8000, R25
|
||||
|
||||
;---------------------------------------------------------------;
|
||||
; Setup constant registers. ;
|
||||
;---------------------------------------------------------------;
|
||||
|
||||
RSEG CSTART:CODE:NOROOT(1)
|
||||
PUBLIC ?INIT_REG
|
||||
|
||||
?INIT_REG: MOV 255, R18
|
||||
ORI 65535, zero, R19
|
||||
|
||||
ENDMOD
|
||||
|
||||
|
||||
;---------------------------------------------------------------;
|
||||
; Initialize the saddr base pointers. ;
|
||||
;---------------------------------------------------------------;
|
||||
|
||||
MODULE ?INIT_SADDR_BASE
|
||||
|
||||
RTMODEL "__reg_ep", "saddr"
|
||||
|
||||
RSEG CSTART:CODE:NOROOT(1)
|
||||
PUBLIC ?INIT_SADDR_BASE
|
||||
|
||||
?INIT_SADDR_BASE:
|
||||
EXTERN ?SADDR_BASE
|
||||
MOVE_M ?SADDR_BASE, EP
|
||||
|
||||
ENDMOD
|
||||
|
||||
|
||||
;---------------------------------------------------------------;
|
||||
; If hardware must be initialized from C or if watch dog timer ;
|
||||
; must be handled or if the segment init should not be ;
|
||||
; performed it can now be done in `__low_level_init'. ;
|
||||
;---------------------------------------------------------------;
|
||||
; Call the user function __low_level_init, if defined. ;
|
||||
; It is the responsibility of __low_level_init to require ;
|
||||
; __cstart_low_level_init in order to be called by cstartup. ;
|
||||
;---------------------------------------------------------------;
|
||||
|
||||
MODULE ?CSTART_LOW_LEVEL_INIT
|
||||
RSEG CSTART:CODE:NOROOT(1)
|
||||
|
||||
PUBLIC __cstart_low_level_init
|
||||
EXTERN __low_level_init
|
||||
REQUIRE __low_level_init
|
||||
EXTERN ?no_seg_init
|
||||
|
||||
__cstart_low_level_init:
|
||||
CALL_FUNC __low_level_init, LP, R1
|
||||
ANDI 0xFF, R1, R1
|
||||
BZ ?no_seg_init
|
||||
|
||||
ENDMOD
|
||||
|
||||
|
||||
;---------------------------------------------------------------;
|
||||
; Segment initialization code. Copy initialized ROMmed code to ;
|
||||
; RAM and ?seg_clear uninitialized variables. ;
|
||||
;---------------------------------------------------------------;
|
||||
|
||||
MODULE ?INIT_MEMORY
|
||||
|
||||
;---------------------------------------------------------------;
|
||||
; Zero out NEAR_Z ;
|
||||
;---------------------------------------------------------------;
|
||||
PUBLIC ?INIT_NEAR_Z
|
||||
|
||||
RSEG NEAR_Z(2)
|
||||
RSEG CSTART:CODE:NOROOT(1)
|
||||
|
||||
EXTERN ?seg_clear
|
||||
?INIT_NEAR_Z:
|
||||
|
||||
MOVE_M SFB NEAR_Z, A0
|
||||
MOVE_M SFE NEAR_Z, A1
|
||||
JARL ?seg_clear, LP
|
||||
|
||||
|
||||
;---------------------------------------------------------------;
|
||||
; Zero out BREL_Z ;
|
||||
;---------------------------------------------------------------;
|
||||
PUBLIC ?INIT_BREL_Z
|
||||
|
||||
RSEG BREL_Z(2)
|
||||
RSEG CSTART:CODE:NOROOT(1)
|
||||
|
||||
EXTERN ?seg_clear
|
||||
?INIT_BREL_Z:
|
||||
|
||||
MOVE_M SFB BREL_Z, A0
|
||||
MOVE_M SFE BREL_Z, A1
|
||||
JARL ?seg_clear, LP
|
||||
|
||||
;---------------------------------------------------------------;
|
||||
; Zero out SADDR7_Z ;
|
||||
;---------------------------------------------------------------;
|
||||
PUBLIC ?INIT_SADDR7_Z
|
||||
|
||||
RSEG SADDR7_Z(2)
|
||||
|
||||
RSEG CSTART:CODE:NOROOT(1)
|
||||
|
||||
EXTERN ?seg_clear
|
||||
?INIT_SADDR7_Z:
|
||||
|
||||
MOVE_M SFB SADDR7_Z, A0
|
||||
MOVE_M SFE SADDR7_Z, A1
|
||||
JARL ?seg_clear, LP
|
||||
|
||||
|
||||
;---------------------------------------------------------------;
|
||||
; Zero out SADDR8_Z ;
|
||||
;---------------------------------------------------------------;
|
||||
PUBLIC ?INIT_SADDR8_Z
|
||||
|
||||
RSEG SADDR8_Z(2)
|
||||
|
||||
RSEG CSTART:CODE:NOROOT(1)
|
||||
|
||||
EXTERN ?seg_clear
|
||||
?INIT_SADDR8_Z:
|
||||
|
||||
MOVE_M SFB SADDR8_Z, A0
|
||||
MOVE_M SFE SADDR8_Z, A1
|
||||
JARL ?seg_clear, LP
|
||||
|
||||
|
||||
;---------------------------------------------------------------;
|
||||
; Zero out BREL23_Z ;
|
||||
;---------------------------------------------------------------;
|
||||
|
||||
#if __CORE__ >= __CORE_V850E2M__
|
||||
|
||||
PUBLIC ?INIT_BREL23_Z
|
||||
|
||||
RSEG BREL23_Z(2)
|
||||
|
||||
RSEG CSTART:CODE:NOROOT(1)
|
||||
|
||||
EXTERN ?seg_clear
|
||||
?INIT_BREL23_Z:
|
||||
|
||||
MOVE_M SFB BREL23_Z, A0
|
||||
MOVE_M SFE BREL23_Z, A1
|
||||
JARL ?seg_clear, LP
|
||||
#endif
|
||||
|
||||
;---------------------------------------------------------------;
|
||||
; Zero out HUGE_Z ;
|
||||
;---------------------------------------------------------------;
|
||||
PUBLIC ?INIT_HUGE_Z
|
||||
|
||||
RSEG HUGE_Z(2)
|
||||
|
||||
RSEG CSTART:CODE:NOROOT(1)
|
||||
|
||||
EXTERN ?seg_clear
|
||||
?INIT_HUGE_Z:
|
||||
|
||||
MOVE_M SFB HUGE_Z, A0
|
||||
MOVE_M SFE HUGE_Z, A1
|
||||
JARL ?seg_clear, LP
|
||||
|
||||
;---------------------------------------------------------------;
|
||||
; Copy NEAR_ID into NEAR_I ;
|
||||
;---------------------------------------------------------------;
|
||||
PUBLIC ?INIT_NEAR_I
|
||||
|
||||
RSEG NEAR_I(2)
|
||||
RSEG NEAR_ID(2)
|
||||
|
||||
RSEG CSTART:CODE:NOROOT(1)
|
||||
|
||||
EXTERN ?seg_copy
|
||||
?INIT_NEAR_I:
|
||||
|
||||
MOVE_M SFB NEAR_ID, A0
|
||||
MOVE_M SFE NEAR_ID, A1
|
||||
MOVE_M SFB NEAR_I, A2
|
||||
JARL ?seg_copy, LP
|
||||
|
||||
;---------------------------------------------------------------;
|
||||
; Copy BREL_ID into BREL_I ;
|
||||
;---------------------------------------------------------------;
|
||||
PUBLIC ?INIT_BREL_I
|
||||
|
||||
RSEG BREL_I(2)
|
||||
RSEG BREL_ID(2)
|
||||
|
||||
RSEG CSTART:CODE:NOROOT(1)
|
||||
|
||||
EXTERN ?seg_copy
|
||||
?INIT_BREL_I:
|
||||
|
||||
MOVE_M SFB BREL_ID, A0
|
||||
MOVE_M SFE BREL_ID, A1
|
||||
MOVE_M SFB BREL_I, A2
|
||||
JARL ?seg_copy, LP
|
||||
|
||||
;---------------------------------------------------------------;
|
||||
; Copy SADDR7_ID into SADDR7_I ;
|
||||
;---------------------------------------------------------------;
|
||||
PUBLIC ?INIT_SADDR7_I
|
||||
|
||||
RSEG SADDR7_I(2)
|
||||
RSEG SADDR7_ID(2)
|
||||
|
||||
RSEG CSTART:CODE:NOROOT(1)
|
||||
|
||||
EXTERN ?seg_copy
|
||||
?INIT_SADDR7_I:
|
||||
|
||||
MOVE_M SFB SADDR7_ID, A0
|
||||
MOVE_M SFE SADDR7_ID, A1
|
||||
MOVE_M SFB SADDR7_I, A2
|
||||
JARL ?seg_copy, LP
|
||||
|
||||
;---------------------------------------------------------------;
|
||||
; Copy SADDR8_ID into SADDR8_I ;
|
||||
;---------------------------------------------------------------;
|
||||
PUBLIC ?INIT_SADDR8_I
|
||||
|
||||
RSEG SADDR8_I(2)
|
||||
RSEG SADDR8_ID(2)
|
||||
|
||||
RSEG CSTART:CODE:NOROOT(1)
|
||||
|
||||
EXTERN ?seg_copy
|
||||
?INIT_SADDR8_I:
|
||||
|
||||
MOVE_M SFB SADDR8_ID, A0
|
||||
MOVE_M SFE SADDR8_ID, A1
|
||||
MOVE_M SFB SADDR8_I, A2
|
||||
JARL ?seg_copy, LP
|
||||
|
||||
;---------------------------------------------------------------;
|
||||
; Copy BREL23_ID into BREL23_I ;
|
||||
;---------------------------------------------------------------;
|
||||
|
||||
#if __CORE__ >= __CORE_V850E2M__
|
||||
|
||||
PUBLIC ?INIT_BREL23_I
|
||||
|
||||
RSEG BREL23_I(1)
|
||||
RSEG BREL23_ID(1)
|
||||
|
||||
RSEG CSTART:CODE:NOROOT(1)
|
||||
|
||||
EXTERN ?seg_copy
|
||||
|
||||
?INIT_BREL23_I:
|
||||
|
||||
MOVE_M SFB BREL23_ID, A0
|
||||
MOVE_M SFE BREL23_ID, A1
|
||||
MOVE_M SFB BREL23_I, A2
|
||||
JARL ?seg_copy, LP
|
||||
|
||||
#endif
|
||||
|
||||
;---------------------------------------------------------------;
|
||||
; Copy HUGE_ID into HUGE_I ;
|
||||
;---------------------------------------------------------------;
|
||||
PUBLIC ?INIT_HUGE_I
|
||||
|
||||
RSEG HUGE_I(1)
|
||||
RSEG HUGE_ID(1)
|
||||
|
||||
RSEG CSTART:CODE:NOROOT(1)
|
||||
|
||||
EXTERN ?seg_copy
|
||||
|
||||
?INIT_HUGE_I:
|
||||
|
||||
MOVE_M SFB HUGE_ID, A0
|
||||
MOVE_M SFE HUGE_ID, A1
|
||||
MOVE_M SFB HUGE_I, A2
|
||||
JARL ?seg_copy, LP
|
||||
|
||||
|
||||
;---------------------------------------------------------------;
|
||||
; Destination label when skipping data initialization. ;
|
||||
;---------------------------------------------------------------;
|
||||
PUBLIC ?no_seg_init
|
||||
|
||||
RSEG CSTART:CODE:NOROOT(1)
|
||||
|
||||
?no_seg_init:
|
||||
|
||||
ENDMOD
|
||||
|
||||
|
||||
;---------------------------------------------------------------;
|
||||
; Calculate code distance (PIC only). ;
|
||||
;---------------------------------------------------------------;
|
||||
|
||||
MODULE ?INIT_PIC
|
||||
PUBLIC ?INIT_PIC
|
||||
|
||||
RSEG CSTART:CODE:NOROOT(1)
|
||||
|
||||
RTMODEL "__code_model", "pic"
|
||||
|
||||
EXTERN ?CODE_DISTANCE
|
||||
EXTERN_LS_M
|
||||
|
||||
?INIT_PIC:
|
||||
JARL ref_point, A1
|
||||
ref_point: MOVE_M ref_point, A2
|
||||
SUB A2, A1
|
||||
;; Expands to correct store instruction/sequence.
|
||||
STORE_M A1, ?CODE_DISTANCE, A2
|
||||
;; Note: A1 (the value of ?CODE_DISTANCE) is used below!
|
||||
|
||||
ENDMOD
|
||||
|
||||
|
||||
#if __CORE__ >= __CORE_V850E2M__
|
||||
|
||||
;---------------------------------------------------------------;
|
||||
; Initialize the BSEL system register bank selector. ;
|
||||
;---------------------------------------------------------------;
|
||||
|
||||
MODULE ?INIT_BSEL
|
||||
RSEG CSTART:CODE:NOROOT(1)
|
||||
PUBLIC ?INIT_BSEL
|
||||
|
||||
?INIT_BSEL:
|
||||
LDSR R0, 31 ; BSEL
|
||||
|
||||
ENDMOD
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#if __CORE__ >= __CORE_V850E__
|
||||
|
||||
;---------------------------------------------------------------;
|
||||
; Initialize the CALLT base pointers. ;
|
||||
;---------------------------------------------------------------;
|
||||
|
||||
|
||||
MODULE ?INIT_CALLT
|
||||
PUBLIC ?INIT_CALLT
|
||||
EXTERN ?CALLT_BASE
|
||||
COMMON CLTVEC(2)
|
||||
RSEG CSTART:CODE:NOROOT(1)
|
||||
|
||||
RTMODEL "__cpu", "v850e"
|
||||
|
||||
REQUIRE ?CALLT_BASE
|
||||
|
||||
;; The Call table base pointer
|
||||
?INIT_CALLT:
|
||||
MOVE_M SFB CLTVEC, A2
|
||||
#ifdef CODE_MODEL_PIC
|
||||
EXTERN ?CODE_DISTANCE
|
||||
REQUIRE ?CODE_DISTANCE
|
||||
|
||||
;; Add the value of ?CODE_DISTANCE calculated above
|
||||
ADD A1, A2
|
||||
#endif
|
||||
#if __CORE__ >= __CORE_V850E2M__
|
||||
EXTERN ?INIT_BSEL
|
||||
REQUIRE ?INIT_BSEL
|
||||
#endif
|
||||
LDSR A2, 20 ; CTBP
|
||||
|
||||
ENDMOD
|
||||
#endif
|
||||
|
||||
|
||||
#if __CORE__ >= __CORE_V850E2M__
|
||||
|
||||
;---------------------------------------------------------------;
|
||||
; Initialize the SYSCALL base pointers. ;
|
||||
;---------------------------------------------------------------;
|
||||
|
||||
MODULE ?INIT_SYSCALL
|
||||
PUBLIC ?INIT_SYSCALL
|
||||
EXTERN ?INIT_BSEL
|
||||
EXTERN ?SYSCALL_BASE
|
||||
COMMON SYSCALLVEC(2)
|
||||
|
||||
RSEG CSTART:CODE:NOROOT(1)
|
||||
|
||||
REQUIRE ?INIT_BSEL
|
||||
REQUIRE ?SYSCALL_BASE
|
||||
|
||||
;; The syscall table base pointer
|
||||
?INIT_SYSCALL:
|
||||
MOVE_M SFB SYSCALLVEC, A2
|
||||
#ifdef CODE_MODEL_PIC
|
||||
EXTERN ?CODE_DISTANCE
|
||||
REQUIRE ?CODE_DISTANCE
|
||||
|
||||
;; Add the value of ?CODE_DISTANCE calculated above
|
||||
ADD A1, A2
|
||||
#endif
|
||||
LDSR A2, 12 ; SCBP
|
||||
|
||||
MOVE_M ((SFE SYSCALLVEC - SFB SYSCALLVEC)/4) - 1, A2
|
||||
LDSR A2, 11 ; SCCFG
|
||||
|
||||
ENDMOD
|
||||
|
||||
#endif
|
||||
|
||||
;---------------------------------------------------------------;
|
||||
; This segment part is required by the compiler when it is ;
|
||||
; necessary to call constructors of global objects. ;
|
||||
;---------------------------------------------------------------;
|
||||
|
||||
MODULE ?CALL_MAIN
|
||||
RSEG DIFUNCT(2)
|
||||
RSEG CSTART:CODE:NOROOT(1)
|
||||
PUBLIC ?cstart_call_ctors
|
||||
|
||||
EXTERN __call_ctors
|
||||
|
||||
?cstart_call_ctors:
|
||||
MOVE_M SFB DIFUNCT, R1
|
||||
MOVE_M SFE DIFUNCT, R5
|
||||
|
||||
CALL_FUNC __call_ctors, LP, R6
|
||||
|
||||
|
||||
;---------------------------------------------------------------;
|
||||
; Call C main() with no parameters. ;
|
||||
;---------------------------------------------------------------;
|
||||
|
||||
RSEG CSTART:CODE:NOROOT(1)
|
||||
PUBLIC ?cstart_call_main
|
||||
|
||||
EXTERN main
|
||||
EXTERN exit
|
||||
EXTERN __exit
|
||||
|
||||
?cstart_call_main:
|
||||
CALL_FUNC main, LP, R6
|
||||
|
||||
;---------------------------------------------------------------;
|
||||
; If we come here we have returned from main with a 'return' ;
|
||||
; statement, not with a call to exit() or abort(). ;
|
||||
; In this case we must call exit() here for a nice ending. ;
|
||||
; Note: The return value of main() is the argument to exit(). ;
|
||||
;---------------------------------------------------------------;
|
||||
CALL_FUNC exit, LP, R6
|
||||
|
||||
;---------------------------------------------------------------;
|
||||
; We should never come here, but just in case. ;
|
||||
;---------------------------------------------------------------;
|
||||
|
||||
MOV __exit, LP
|
||||
JMP [LP]
|
||||
|
||||
PUBLIC ?BTT_cstart_end
|
||||
?BTT_cstart_end:
|
||||
|
||||
|
||||
;---------------------------------------------------------------;
|
||||
; Copy a chunk of memory. ;
|
||||
; A0 = Start of from block ;
|
||||
; A1 = End of from block (+1) ;
|
||||
; A2 = Start of to block ;
|
||||
;---------------------------------------------------------------;
|
||||
|
||||
PUBLIC ?seg_copy
|
||||
PUBLIC ?seg_clear
|
||||
|
||||
RSEG CSTART:CODE:NOROOT(1)
|
||||
REQUIRE done
|
||||
|
||||
cp_cont: LD.B 0[A0], R7
|
||||
ADD 1, A0
|
||||
ST.B R7, 0[A2]
|
||||
ADD 1, A2
|
||||
|
||||
;; Note: The entry point is here.
|
||||
?seg_copy: CMP A0, A1
|
||||
BNE cp_cont
|
||||
|
||||
RSEG CSTART:CODE:NOROOT(1)
|
||||
|
||||
done: JMP [LP]
|
||||
|
||||
;---------------------------------------------------------------;
|
||||
; Clear a chunk of memory. ;
|
||||
; A0 = Start of block ;
|
||||
; A1 = End of block (+1) ;
|
||||
;---------------------------------------------------------------;
|
||||
|
||||
RSEG CSTART:CODE:NOROOT(1)
|
||||
REQUIRE done
|
||||
|
||||
?seg_clear: CMP A0, A1
|
||||
BE done
|
||||
cl_cont: ST.B zero, 0[A0]
|
||||
ADD 1, A0
|
||||
BR ?seg_clear
|
||||
|
||||
ENDMOD
|
||||
|
||||
|
||||
;---------------------------------------------------------------;
|
||||
; _exit code ;
|
||||
; ;
|
||||
; Call destructors (if required), then fall through to __exit. ;
|
||||
;---------------------------------------------------------------;
|
||||
|
||||
MODULE ?_exit
|
||||
PUBLIC _exit
|
||||
PUBLIC ?BTT_exit_begin
|
||||
EXTERN ?exit_restore2
|
||||
RSEG RCODE:CODE:NOROOT(1)
|
||||
|
||||
?BTT_exit_begin:
|
||||
_exit:
|
||||
REQUIRE ?exit_restore2
|
||||
;; If any of the two pieces of code "__cstart_call_dtors"
|
||||
;; or "__cstart_closeall" is called we need to save the
|
||||
;; argument to "_exit". However, since we never will
|
||||
;; from this function we can use a permanent register
|
||||
;; rather than storing the value on the stack.
|
||||
|
||||
RSEG RCODE:CODE:NOROOT(1)
|
||||
EXTERN ?exit_restore
|
||||
PUBLIC ?exit_save
|
||||
?exit_save:
|
||||
REQUIRE ?exit_restore
|
||||
|
||||
MOV R1, R29
|
||||
|
||||
RSEG RCODE:CODE:NOROOT(1)
|
||||
PUBLIC __cstart_call_dtors
|
||||
EXTERN __call_dtors
|
||||
REQUIRE ?exit_save
|
||||
|
||||
;; This label is required by "__record_needed_destruction".
|
||||
|
||||
__cstart_call_dtors:
|
||||
CALL_FUNC __call_dtors, LP, R1
|
||||
|
||||
ENDMOD
|
||||
|
||||
;; A new module is needed so that a non-terminal-IO program
|
||||
;; doesn't include this, which requires __putchar.
|
||||
|
||||
MODULE ?__cstart_closeall
|
||||
RSEG RCODE:CODE:NOROOT(1)
|
||||
|
||||
;; When stdio is used, the following piece of code is
|
||||
;; required by the _Closreg macro.
|
||||
|
||||
PUBLIC __cstart_closeall
|
||||
EXTERN ?exit_save
|
||||
REQUIRE ?exit_save
|
||||
|
||||
;; This label is required by _Closreg
|
||||
|
||||
__cstart_closeall:
|
||||
EXTERN _Close_all
|
||||
CALL_FUNC _Close_all, LP, R1
|
||||
|
||||
ENDMOD
|
||||
|
||||
;; Restore the argument previously stored by the "save" section
|
||||
;; above.
|
||||
|
||||
MODULE ?_exit_end
|
||||
RSEG RCODE:CODE:NOROOT(1)
|
||||
|
||||
PUBLIC ?exit_restore
|
||||
EXTERN ?exit_restore2
|
||||
|
||||
?exit_restore:
|
||||
REQUIRE ?exit_restore2
|
||||
MOV R29, R1
|
||||
|
||||
ENDMOD
|
||||
|
||||
MODULE ?_exit_end2
|
||||
PUBLIC ?BTT_exit_end
|
||||
RSEG RCODE:CODE:NOROOT(1)
|
||||
|
||||
PUBLIC ?exit_restore2
|
||||
EXTERN __exit
|
||||
?exit_restore2:
|
||||
|
||||
MOV __exit, LP
|
||||
JMP [LP]
|
||||
|
||||
?BTT_exit_end:
|
||||
ENDMOD
|
||||
|
||||
|
||||
;---------------------------------------------------------------;
|
||||
; Define the base of the base relative (brel) data for RAM. ;
|
||||
; ;
|
||||
; This empty segment should be places in front of the brel ;
|
||||
; RAM data segments. ;
|
||||
;---------------------------------------------------------------;
|
||||
|
||||
MODULE ?BREL_BASE
|
||||
PUBLIC ?BREL_BASE
|
||||
|
||||
RSEG BREL_BASE:DATA:NOROOT(2)
|
||||
|
||||
?BREL_BASE:
|
||||
|
||||
ENDMOD
|
||||
|
||||
|
||||
;---------------------------------------------------------------;
|
||||
; Define the base of the base relative (brel) data for ROM. ;
|
||||
; ;
|
||||
; This empty segment should be places in front of the brel ;
|
||||
; ROM data segment. ;
|
||||
;---------------------------------------------------------------;
|
||||
|
||||
MODULE ?BREL_CBASE
|
||||
PUBLIC ?BREL_CBASE
|
||||
|
||||
RSEG BREL_CBASE:CONST:NOROOT(2)
|
||||
|
||||
?BREL_CBASE:
|
||||
|
||||
ENDMOD
|
||||
|
||||
|
||||
;---------------------------------------------------------------;
|
||||
; Define the base of the short addressing (saddr) data. ;
|
||||
; ;
|
||||
; This empty segment should be places in front of the saddr ;
|
||||
; data segments. ;
|
||||
;---------------------------------------------------------------;
|
||||
|
||||
MODULE ?SADDR_BASE
|
||||
|
||||
RTMODEL "__reg_ep", "saddr"
|
||||
|
||||
PUBLIC ?SADDR_BASE
|
||||
RSEG SADDR_BASE:CONST:NOROOT(2)
|
||||
|
||||
EXTERN ?INIT_SADDR_BASE
|
||||
REQUIRE ?INIT_SADDR_BASE
|
||||
|
||||
?SADDR_BASE:
|
||||
|
||||
ENDMOD
|
||||
|
||||
|
||||
;---------------------------------------------------------------;
|
||||
; The base of the CALLT vector. ;
|
||||
;---------------------------------------------------------------;
|
||||
|
||||
MODULE ?CALLT_BASE
|
||||
|
||||
PUBLIC ?CALLT_BASE
|
||||
COMMON CLTVEC:CONST:NOROOT(2)
|
||||
DATA
|
||||
?CALLT_BASE:
|
||||
|
||||
ENDMOD
|
||||
|
||||
|
||||
#if __CORE__ >= __CORE_V850E2M__
|
||||
|
||||
;---------------------------------------------------------------;
|
||||
; The base of the SYSCALL vector. ;
|
||||
;---------------------------------------------------------------;
|
||||
|
||||
MODULE ?SYSCALL_BASE
|
||||
|
||||
PUBLIC ?SYSCALL_BASE
|
||||
COMMON SYSCALLVEC:CONST:NOROOT(2)
|
||||
DATA
|
||||
?SYSCALL_BASE:
|
||||
|
||||
ENDMOD
|
||||
|
||||
#endif
|
||||
|
||||
;---------------------------------------------------------------;
|
||||
; The distance the code has been moved when using position ;
|
||||
; independent code. ;
|
||||
;---------------------------------------------------------------;
|
||||
|
||||
MODULE ?CODE_DISTANCE
|
||||
|
||||
RTMODEL "__code_model", "pic"
|
||||
|
||||
PUBLIC ?CODE_DISTANCE
|
||||
RSEG LIBRARY_N:DATA:NOROOT(2)
|
||||
|
||||
EXTERN ?INIT_PIC
|
||||
REQUIRE ?INIT_PIC
|
||||
|
||||
?CODE_DISTANCE:
|
||||
DS 4
|
||||
|
||||
ENDMOD
|
||||
|
||||
|
||||
;---------------------------------------------------------------;
|
||||
; A dummy "low level init" that will be used if the user ;
|
||||
; hasn't defined this function. ;
|
||||
;---------------------------------------------------------------;
|
||||
|
||||
MODULE ?__low_level_init_stub
|
||||
PUBLIC __low_level_init
|
||||
RSEG RCODE:CODE:NOROOT
|
||||
__low_level_init:
|
||||
MOV 1, R1
|
||||
JMP [LP]
|
||||
|
||||
ENDMOD
|
||||
|
||||
END
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,247 @@
|
|||
/*
|
||||
* File : board.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2009 - 2012 RT-Thread Develop Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rt-thread.org/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2010-03-08 Bernard The first version for LPC17xx
|
||||
* 2010-06-29 lgnq Modified for V850
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include "io70f3454.h"
|
||||
#include "uart.h"
|
||||
|
||||
#if defined(RT_USING_UART0) && defined(RT_USING_DEVICE)
|
||||
|
||||
struct rt_uart_v850
|
||||
{
|
||||
struct rt_device parent;
|
||||
|
||||
/* buffer for reception */
|
||||
rt_uint8_t read_index, save_index;
|
||||
rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
|
||||
}uart_device;
|
||||
|
||||
void uarta1_receive_handler(void)
|
||||
{
|
||||
rt_ubase_t level;
|
||||
rt_uint8_t c;
|
||||
|
||||
struct rt_uart_v850 *uart = &uart_device;
|
||||
|
||||
// while(ri_u0c1 == 0)
|
||||
// ;
|
||||
c = (char) UA1RX;
|
||||
|
||||
/* Receive Data Available */
|
||||
uart->rx_buffer[uart->save_index] = c;
|
||||
|
||||
level = rt_hw_interrupt_disable();
|
||||
uart->save_index ++;
|
||||
if (uart->save_index >= RT_UART_RX_BUFFER_SIZE)
|
||||
uart->save_index = 0;
|
||||
rt_hw_interrupt_enable(level);
|
||||
|
||||
/* invoke callback */
|
||||
if (uart->parent.rx_indicate != RT_NULL)
|
||||
{
|
||||
rt_size_t length;
|
||||
if (uart->read_index > uart->save_index)
|
||||
length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index;
|
||||
else
|
||||
length = uart->save_index - uart->read_index;
|
||||
|
||||
uart->parent.rx_indicate(&uart->parent, length);
|
||||
}
|
||||
}
|
||||
|
||||
static rt_err_t rt_uart_init (rt_device_t dev)
|
||||
{
|
||||
UA1TXE = 0U; /* disable UARTA1 transmission operation */
|
||||
UA1RXE = 0U; /* disable UARTA1 reception operation */
|
||||
UA1PWR = 0U; /* disable UARTA1 operation */
|
||||
UA1TMK = 1U; /* disable INTUA1T interrupt */
|
||||
UA1TIF = 0U; /* clear INTUA1T interrupt flag */
|
||||
UA1RMK = 1U; /* disable INTUA1R interrupt */
|
||||
UA1RIF = 0U; /* clear INTUA1R interrupt flag */
|
||||
/* Set INTUA1T level low priority */
|
||||
UA1TIC |= 0x07U;
|
||||
/* Set INTUA1R level low priority */
|
||||
UA1RIC |= 0x07U;
|
||||
//BAUDRATE = 9600
|
||||
UA1CTL1 = _03_UARTA_BASECLK_FXX_16;
|
||||
UA1CTL2 = _11_UARTA1_BASECLK_DIVISION;
|
||||
UA1CTL0 = _10_UARTA_TRANSFDIR_LSB | _00_UARTA_PARITY_NONE | _02_UARTA_DATALENGTH_8BIT | _00_UARTA_STOPLENGTH_1BIT;
|
||||
UA1OPT0 = _14_UARTA_UAnOPT0_INITIALVALUE | _00_UARTA_TRAN_DATALEVEL_NORMAL | _00_UARTA_REC_DATALEVEL_NORMAL;
|
||||
UA1PWR = 1U; /* enable UARTA1 operation */
|
||||
/* Set TXDA1 pin */
|
||||
/* Set RXDA1 pin */
|
||||
PFC3_bit.no0 = 0;
|
||||
PFCE3_bit.no0 = 0;
|
||||
PMC3_bit.no0 = 1;
|
||||
|
||||
PFC3_bit.no1 = 0;
|
||||
PFCE3_bit.no1 = 0;
|
||||
PMC3_bit.no1 = 1;
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag)
|
||||
{
|
||||
RT_ASSERT(dev != RT_NULL);
|
||||
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
|
||||
{
|
||||
/* Enable the UART Interrupt */
|
||||
UA1TIF = 0U; /* clear INTUA1T interrupt flag */
|
||||
UA1TMK = 1U; /* disable INTUA1T interrupt */
|
||||
UA1RIF = 0U; /* clear INTUA1R interrupt flag */
|
||||
UA1RMK = 0U; /* enable INTUA1R interrupt */
|
||||
UA1TXE = 1U; /* enable UARTA1 transmission operation */
|
||||
UA1RXE = 1U; /* enable UARTA1 reception operation */
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t rt_uart_close(rt_device_t dev)
|
||||
{
|
||||
RT_ASSERT(dev != RT_NULL);
|
||||
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
|
||||
{
|
||||
/* Disable the UART Interrupt */
|
||||
UA1TXE = 0U; /* disable UARTA1 transmission operation */
|
||||
UA1RXE = 0U; /* disable UARTA1 reception operation */
|
||||
UA1TMK = 1U; /* disable INTUA1T interrupt */
|
||||
UA1TIF = 0U; /* clear INTUA1T interrupt flag */
|
||||
UA1RMK = 1U; /* disable INTUA1R interrupt */
|
||||
UA1RIF = 0U; /* clear INTUA1R interrupt flag */
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
|
||||
{
|
||||
rt_uint8_t *ptr;
|
||||
struct rt_uart_v850 *uart = (struct rt_uart_v850 *)dev;
|
||||
RT_ASSERT(uart != RT_NULL);
|
||||
|
||||
/* point to buffer */
|
||||
ptr = (rt_uint8_t *)buffer;
|
||||
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
|
||||
{
|
||||
while (size)
|
||||
{
|
||||
/* interrupt receive */
|
||||
rt_base_t level;
|
||||
|
||||
/* disable interrupt */
|
||||
level = rt_hw_interrupt_disable();
|
||||
if (uart->read_index != uart->save_index)
|
||||
{
|
||||
*ptr = uart->rx_buffer[uart->read_index];
|
||||
|
||||
uart->read_index ++;
|
||||
if (uart->read_index >= RT_UART_RX_BUFFER_SIZE)
|
||||
uart->read_index = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* no data in rx buffer */
|
||||
|
||||
/* enable interrupt */
|
||||
rt_hw_interrupt_enable(level);
|
||||
break;
|
||||
}
|
||||
|
||||
/* enable interrupt */
|
||||
rt_hw_interrupt_enable(level);
|
||||
|
||||
ptr ++;
|
||||
size --;
|
||||
}
|
||||
|
||||
return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
|
||||
{
|
||||
char *ptr;
|
||||
ptr = (char*)buffer;
|
||||
|
||||
if (dev->flag & RT_DEVICE_FLAG_STREAM)
|
||||
{
|
||||
/* stream mode */
|
||||
while (size)
|
||||
{
|
||||
if (*ptr == '\n')
|
||||
{
|
||||
while (UA1TSF == 1U)
|
||||
;
|
||||
UA1TX = '\r';
|
||||
}
|
||||
|
||||
/* THRE status, contain valid data */
|
||||
while (UA1TSF == 1U)
|
||||
;
|
||||
UA1TX = *ptr;
|
||||
|
||||
ptr ++;
|
||||
size --;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
while (size != 0)
|
||||
{
|
||||
/* THRE status, contain valid data */
|
||||
while (UA1TSF == 1U)
|
||||
;
|
||||
UA1TX = *ptr;
|
||||
|
||||
ptr ++;
|
||||
size --;
|
||||
}
|
||||
}
|
||||
|
||||
return (rt_size_t)ptr - (rt_size_t)buffer;
|
||||
}
|
||||
|
||||
void rt_hw_uart_init(void)
|
||||
{
|
||||
struct rt_uart_v850 *uart;
|
||||
|
||||
/* get uart device */
|
||||
uart = &uart_device;
|
||||
|
||||
/* device initialization */
|
||||
uart->parent.type = RT_Device_Class_Char;
|
||||
rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
|
||||
uart->read_index = uart->save_index = 0;
|
||||
|
||||
/* device interface */
|
||||
uart->parent.init = rt_uart_init;
|
||||
uart->parent.open = rt_uart_open;
|
||||
uart->parent.close = rt_uart_close;
|
||||
uart->parent.read = rt_uart_read;
|
||||
uart->parent.write = rt_uart_write;
|
||||
uart->parent.control = RT_NULL;
|
||||
uart->parent.user_data = RT_NULL;
|
||||
|
||||
rt_device_register(&uart->parent,
|
||||
"uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX);
|
||||
}
|
||||
#endif /* end of UART */
|
||||
|
||||
/*@}*/
|
||||
|
|
@ -150,7 +150,7 @@
|
|||
|
||||
// Set up near RT_HEAP
|
||||
//fify 20100505 HEAP for RTT
|
||||
-Z(DATA)RT_HEAP+400=FFFFC000-FFFFEFFF
|
||||
-Z(DATA)RT_HEAP+800=FFFFC000-FFFFEFFF
|
||||
|
||||
//-------------------------------------------------------------------------
|
||||
// End of File
|
||||
|
|
|
|||
|
|
@ -15,20 +15,6 @@
|
|||
<version>7</version>
|
||||
<wantNonLocal>1</wantNonLocal>
|
||||
<debug>1</debug>
|
||||
<option>
|
||||
<name>GeneralMisraVer</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>GeneralMisraRules04</name>
|
||||
<version>0</version>
|
||||
<state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>GeneralMisraRules98</name>
|
||||
<version>0</version>
|
||||
<state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>GMemoryModel</name>
|
||||
<state>0</state>
|
||||
|
|
@ -103,7 +89,7 @@
|
|||
</option>
|
||||
<option>
|
||||
<name>GHeapSize</name>
|
||||
<state>4096</state>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>GeneralEnableMisra</name>
|
||||
|
|
@ -117,6 +103,20 @@
|
|||
<name>GDeviceSelect</name>
|
||||
<state>70F3454 V850E - uPD70F3454</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>GeneralMisraVer</name>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>GeneralMisraRules04</name>
|
||||
<version>0</version>
|
||||
<state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>GeneralMisraRules98</name>
|
||||
<version>0</version>
|
||||
<state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>GFloatingPointUnit</name>
|
||||
<version>0</version>
|
||||
|
|
@ -283,10 +283,13 @@
|
|||
</option>
|
||||
<option>
|
||||
<name>CCIncludePath2</name>
|
||||
<state>$PROJ_DIR$\</state>
|
||||
<state>$PROJ_DIR$\applilet3_src\</state>
|
||||
<state>$PROJ_DIR$\..\..\include\</state>
|
||||
<state>$PROJ_DIR$\..\..\libcpu\v850\70f34</state>
|
||||
<state>$PROJ_DIR$\..\..\include</state>
|
||||
<state>$PROJ_DIR$\drivers</state>
|
||||
<state>$PROJ_DIR$\.</state>
|
||||
<state>$PROJ_DIR$\applications</state>
|
||||
<state>$PROJ_DIR$\..\..\components\finsh</state>
|
||||
<state>$PROJ_DIR$\..\..\libcpu\v850\common</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCStdIncCheck</name>
|
||||
|
|
@ -550,12 +553,12 @@
|
|||
</option>
|
||||
<option>
|
||||
<name>OutputFile</name>
|
||||
<state>upd70f3454.d85</state>
|
||||
<state>project.d85</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OutputFormat</name>
|
||||
<version>11</version>
|
||||
<state>23</state>
|
||||
<state>27</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>FormatVariant</name>
|
||||
|
|
@ -728,7 +731,7 @@
|
|||
</option>
|
||||
<option>
|
||||
<name>ExtraOutputFile</name>
|
||||
<state>upd70f3454.hex</state>
|
||||
<state>rtthread.hex</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>ExtraOutputFormat</name>
|
||||
|
|
@ -932,7 +935,7 @@
|
|||
</option>
|
||||
<option>
|
||||
<name>GDeviceSelect</name>
|
||||
<state>70F3746 V850ES- uPD70F3746</state>
|
||||
<state></state>
|
||||
</option>
|
||||
<option>
|
||||
<name>GeneralMisraVer</name>
|
||||
|
|
@ -1066,7 +1069,7 @@
|
|||
</option>
|
||||
<option>
|
||||
<name>CCEnableMigration</name>
|
||||
<state>1</state>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>IRegConstCompCheck</name>
|
||||
|
|
@ -1114,7 +1117,13 @@
|
|||
</option>
|
||||
<option>
|
||||
<name>CCIncludePath2</name>
|
||||
<state></state>
|
||||
<state>$PROJ_DIR$\..\..\libcpu\v850\70f34</state>
|
||||
<state>$PROJ_DIR$\..\..\include</state>
|
||||
<state>$PROJ_DIR$\drivers</state>
|
||||
<state>$PROJ_DIR$\.</state>
|
||||
<state>$PROJ_DIR$\applications</state>
|
||||
<state>$PROJ_DIR$\..\..\components\finsh</state>
|
||||
<state>$PROJ_DIR$\..\..\libcpu\v850\common</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCStdIncCheck</name>
|
||||
|
|
@ -1161,11 +1170,11 @@
|
|||
<option>
|
||||
<name>CCOptStrategy</name>
|
||||
<version>0</version>
|
||||
<state>1</state>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCOptLevelSlave</name>
|
||||
<state>3</state>
|
||||
<state>1</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>CCAggressiveInlining</name>
|
||||
|
|
@ -1660,95 +1669,101 @@
|
|||
<data/>
|
||||
</settings>
|
||||
</configuration>
|
||||
<group>
|
||||
<name>70F34</name>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\libcpu\v850\70f34\context_iar.asm</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\libcpu\v850\70f34\cpuport.c</name>
|
||||
</file>
|
||||
</group>
|
||||
<group>
|
||||
<name>Applications</name>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\applications\application.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\applications\startup.c</name>
|
||||
</file>
|
||||
</group>
|
||||
<group>
|
||||
<name>Drivers</name>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\drivers\board.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\drivers\CG_port.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\drivers\CG_port_user.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\drivers\CG_system.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\drivers\CG_system_user.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\drivers\CG_systeminit.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\drivers\CG_timer.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\drivers\CG_timer_user.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\drivers\cstartup.asm</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\drivers\uart.c</name>
|
||||
</file>
|
||||
</group>
|
||||
<group>
|
||||
<name>finsh</name>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\components\finsh\cmd.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\components\finsh\finsh.h</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\components\finsh\finsh_compiler.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\components\finsh\finsh_error.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\components\finsh\finsh_error.h</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\components\finsh\finsh_heap.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\components\finsh\finsh_heap.h</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\components\finsh\finsh_init.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\components\finsh\finsh_node.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\components\finsh\finsh_node.h</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\components\finsh\finsh_ops.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\components\finsh\finsh_ops.h</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\components\finsh\finsh_parser.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\components\finsh\finsh_parser.h</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\components\finsh\finsh_token.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\components\finsh\finsh_token.h</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\components\finsh\finsh_var.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\components\finsh\finsh_var.h</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\components\finsh\finsh_vm.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\components\finsh\finsh_vm.h</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\components\finsh\shell.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\components\finsh\shell.h</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\components\finsh\symbol.c</name>
|
||||
</file>
|
||||
</group>
|
||||
<group>
|
||||
<name>include</name>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\include\rtdef.h</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\include\rthw.h</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\include\rtm.h</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\include\rtthread.h</name>
|
||||
</file>
|
||||
</group>
|
||||
<group>
|
||||
<name>kernel</name>
|
||||
<name>Kernel</name>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\src\clock.c</name>
|
||||
</file>
|
||||
|
|
@ -1767,33 +1782,18 @@
|
|||
<file>
|
||||
<name>$PROJ_DIR$\..\..\src\kservice.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\src\kservice.h</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\src\mem.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\src\mempool.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\src\module.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\src\module.h</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\src\object.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\src\rtm.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\src\scheduler.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\src\slab.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\src\thread.c</name>
|
||||
</file>
|
||||
|
|
@ -1801,51 +1801,6 @@
|
|||
<name>$PROJ_DIR$\..\..\src\timer.c</name>
|
||||
</file>
|
||||
</group>
|
||||
<group>
|
||||
<name>libcpu</name>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\libcpu\v850\context.asm</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\..\..\libcpu\v850\cpuport.c</name>
|
||||
</file>
|
||||
</group>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\application.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\board.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\applilet3_src\CG_port.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\applilet3_src\CG_port_user.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\applilet3_src\CG_system.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\applilet3_src\CG_system_user.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\applilet3_src\CG_systeminit.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\applilet3_src\CG_timer.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\applilet3_src\CG_timer_user.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\cstartup.s85</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\startup.c</name>
|
||||
</file>
|
||||
<file>
|
||||
<name>$PROJ_DIR$\uart.c</name>
|
||||
</file>
|
||||
</project>
|
||||
|
||||
|
||||
|
|
@ -2,7 +2,9 @@
|
|||
|
||||
<workspace>
|
||||
<project>
|
||||
<path>$WS_DIR$\upd70f3454.ewp</path>
|
||||
<path>$WS_DIR$\project.ewp</path>
|
||||
</project>
|
||||
<batchBuild/>
|
||||
</workspace>
|
||||
|
||||
|
||||
|
|
@ -86,67 +86,4 @@
|
|||
/* the max number of cached sector */
|
||||
///#define DFS_CACHE_MAX_NUM 4
|
||||
|
||||
/* SECTION: lwip, a lighwight TCP/IP protocol stack */
|
||||
//#define RT_USING_LWIP
|
||||
|
||||
/* Enable ICMP protocol*/
|
||||
///#define RT_LWIP_ICMP
|
||||
/* Enable UDP protocol*/
|
||||
///#define RT_LWIP_UDP
|
||||
/* Enable TCP protocol*/
|
||||
///#define RT_LWIP_TCP
|
||||
/* Enable DNS */
|
||||
///#define RT_LWIP_DNS
|
||||
|
||||
/* the number of simulatenously active TCP connections*/
|
||||
///#define RT_LWIP_TCP_PCB_NUM 5
|
||||
|
||||
/* ip address of target*/
|
||||
///#define RT_LWIP_IPADDR0 192
|
||||
///#define RT_LWIP_IPADDR1 168
|
||||
///#define RT_LWIP_IPADDR2 1
|
||||
///#define RT_LWIP_IPADDR3 30
|
||||
|
||||
/* gateway address of target*/
|
||||
#define RT_LWIP_GWADDR0 192
|
||||
#define RT_LWIP_GWADDR1 168
|
||||
#define RT_LWIP_GWADDR2 1
|
||||
#define RT_LWIP_GWADDR3 1
|
||||
|
||||
/* mask address of target*/
|
||||
#define RT_LWIP_MSKADDR0 255
|
||||
#define RT_LWIP_MSKADDR1 255
|
||||
#define RT_LWIP_MSKADDR2 255
|
||||
#define RT_LWIP_MSKADDR3 0
|
||||
|
||||
/* tcp thread options */
|
||||
#define RT_LWIP_TCPTHREAD_PRIORITY 12
|
||||
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 4
|
||||
#define RT_LWIP_TCPTHREAD_STACKSIZE 1024
|
||||
|
||||
/* ethernet if thread options */
|
||||
#define RT_LWIP_ETHTHREAD_PRIORITY 15
|
||||
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 4
|
||||
#define RT_LWIP_ETHTHREAD_STACKSIZE 512
|
||||
|
||||
/* SECTION: RT-Thread/GUI */
|
||||
/* #define RT_USING_RTGUI */
|
||||
|
||||
/* name length of RTGUI object */
|
||||
#define RTGUI_NAME_MAX 12
|
||||
/* support 16 weight font */
|
||||
#define RTGUI_USING_FONT16
|
||||
/* support Chinese font */
|
||||
#define RTGUI_USING_FONTHZ
|
||||
/* use DFS as file interface */
|
||||
#define RTGUI_USING_DFS_FILERW
|
||||
/* use font file as Chinese font */
|
||||
#define RTGUI_USING_HZ_FILE
|
||||
/* use small size in RTGUI */
|
||||
#define RTGUI_USING_SMALL_SIZE
|
||||
/* use mouse cursor */
|
||||
/* #define RTGUI_USING_MOUSE_CURSOR */
|
||||
/* default font size in RTGUI */
|
||||
#define RTGUI_DEFAULT_FONT_SIZE 16
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -0,0 +1,111 @@
|
|||
import os
|
||||
|
||||
# toolchains options
|
||||
ARCH = 'v850'
|
||||
CPU = '70f34'
|
||||
|
||||
CROSS_TOOL = 'iar'
|
||||
|
||||
if os.getenv('RTT_CC'):
|
||||
CROSS_TOOL = os.getenv('RTT_CC')
|
||||
|
||||
if CROSS_TOOL == 'gcc':
|
||||
print '================ERROR============================'
|
||||
print 'Not support gcc yet!'
|
||||
print '================================================='
|
||||
exit(0)
|
||||
elif CROSS_TOOL == 'iar':
|
||||
PLATFORM = 'iar'
|
||||
IAR_PATH = 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation_0'
|
||||
elif CROSS_TOOL == 'keil':
|
||||
print '================ERROR============================'
|
||||
print 'Not support keil yet!'
|
||||
print '================================================='
|
||||
exit(0)
|
||||
|
||||
if os.getenv('RTT_EXEC_PATH'):
|
||||
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
|
||||
|
||||
BUILD = 'debug'
|
||||
|
||||
if PLATFORM == 'gcc':
|
||||
# toolchains
|
||||
PREFIX = 'm32c-elf-'
|
||||
CC = PREFIX + 'gcc'
|
||||
AS = PREFIX + 'gcc'
|
||||
AR = PREFIX + 'ar'
|
||||
LINK = PREFIX + 'gcc'
|
||||
TARGET_EXT = 'out'
|
||||
SIZE = PREFIX + 'size'
|
||||
OBJDUMP = PREFIX + 'objdump'
|
||||
OBJCPY = PREFIX + 'objcopy'
|
||||
|
||||
DEVICE = ' -mcpu=m16c'
|
||||
CFLAGS = DEVICE
|
||||
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
|
||||
LFLAGS = DEVICE + ' -nostartfiles' + ' -Wl,--gc-sections,-Map=rtthread_m16c.map,-cref,-u,_start -T m16c62p.ld'
|
||||
|
||||
CPATH = ''
|
||||
LPATH = ''
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -O0 -gdwarf-2'
|
||||
AFLAGS += ' -gdwarf-2'
|
||||
else:
|
||||
CFLAGS += ' -O2'
|
||||
|
||||
POST_ACTION = OBJCPY + ' -O srec $TARGET rtthread.mot\n' + SIZE + ' $TARGET \n'
|
||||
|
||||
elif PLATFORM == 'iar':
|
||||
# toolchains
|
||||
CC = 'iccv850'
|
||||
AS = 'av850'
|
||||
AR = 'xar'
|
||||
LINK = 'xlink'
|
||||
TARGET_EXT = 'hex'
|
||||
|
||||
DEVICE = '--cpu V850'
|
||||
|
||||
EXEC_PATH = IAR_PATH + '/v850/bin'
|
||||
|
||||
AFLAGS = '-s+'
|
||||
AFLAGS = ' -v1'
|
||||
# AFLAGS += ' -M<>'
|
||||
AFLAGS += ' -s+'
|
||||
AFLAGS += ' -DCODE_MODEL_NORMAL'
|
||||
AFLAGS += ' -DDATA_MODEL_TINY'
|
||||
AFLAGS += ' -w+'
|
||||
AFLAGS += ' -r'
|
||||
AFLAGS += ' -I"' + IAR_PATH + '/v850/INC"'
|
||||
|
||||
LFLAGS = '-xms'
|
||||
LFLAGS += ' -I"' + IAR_PATH + '/v850/LIB"'
|
||||
LFLAGS += ' -rt'
|
||||
LFLAGS += ' -s __program_start'
|
||||
LFLAGS += ' -D_CSTACK_SIZE=1000'
|
||||
LFLAGS += ' "' + IAR_PATH + '/v850/LIB/dl85nn1.r85"'
|
||||
LFLAGS += ' -D_HEAP_SIZE=0'
|
||||
|
||||
# LFLAGS += ' "' + IAR_PATH + '/v850/lib/CLIB/clm16cfnffwc.r34"'
|
||||
# LFLAGS += ' -e_small_write=_formatted_write'
|
||||
# LFLAGS += ' -e_medium_read=_formatted_read'
|
||||
|
||||
# CFLAGS = DEVICE
|
||||
CFLAGS = '--diag_suppress Pa050'
|
||||
CFLAGS += ' -v1'
|
||||
CFLAGS += ' -mt'
|
||||
CFLAGS += ' --code_model normal'
|
||||
CFLAGS += ' --no_cse'
|
||||
CFLAGS += ' --no_unroll'
|
||||
CFLAGS += ' --no_inline'
|
||||
CFLAGS += ' --no_code_motion'
|
||||
CFLAGS += ' --dlib_config "' + IAR_PATH + '/v850/LIB/dl85nn1.h"'
|
||||
CFLAGS += ' -I"' + IAR_PATH + '/v850/INC"'
|
||||
CFLAGS += ' --no_tbaa'
|
||||
CFLAGS += ' --debug'
|
||||
CFLAGS += ' --lock_regs 0'
|
||||
CFLAGS += ' --migration_preprocessor_extensions'
|
||||
CFLAGS += ' -e'
|
||||
CFLAGS += ' -Ol'
|
||||
|
||||
POST_ACTION = ''
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,247 +0,0 @@
|
|||
/*
|
||||
* File : board.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2009 RT-Thread Develop Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rt-thread.org/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2010-03-08 Bernard The first version for LPC17xx
|
||||
* 2010-06-29 lgnq Modified for V850
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include "io70f3454.h"
|
||||
#include "uart.h"
|
||||
|
||||
#if defined(RT_USING_UART0) && defined(RT_USING_DEVICE)
|
||||
|
||||
struct rt_uart_v850
|
||||
{
|
||||
struct rt_device parent;
|
||||
|
||||
/* buffer for reception */
|
||||
rt_uint8_t read_index, save_index;
|
||||
rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
|
||||
}uart_device;
|
||||
|
||||
void uarta1_receive_handler(void)
|
||||
{
|
||||
rt_ubase_t level;
|
||||
rt_uint8_t c;
|
||||
|
||||
struct rt_uart_v850* uart = &uart_device;
|
||||
|
||||
// while(ri_u0c1 == 0)
|
||||
// ;
|
||||
c = (char) UA1RX;
|
||||
|
||||
/* Receive Data Available */
|
||||
uart->rx_buffer[uart->save_index] = c;
|
||||
|
||||
level = rt_hw_interrupt_disable();
|
||||
uart->save_index ++;
|
||||
if (uart->save_index >= RT_UART_RX_BUFFER_SIZE)
|
||||
uart->save_index = 0;
|
||||
rt_hw_interrupt_enable(level);
|
||||
|
||||
/* invoke callback */
|
||||
if(uart->parent.rx_indicate != RT_NULL)
|
||||
{
|
||||
rt_size_t length;
|
||||
if (uart->read_index > uart->save_index)
|
||||
length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index;
|
||||
else
|
||||
length = uart->save_index - uart->read_index;
|
||||
|
||||
uart->parent.rx_indicate(&uart->parent, length);
|
||||
}
|
||||
}
|
||||
|
||||
static rt_err_t rt_uart_init (rt_device_t dev)
|
||||
{
|
||||
UA1TXE = 0U; /* disable UARTA1 transmission operation */
|
||||
UA1RXE = 0U; /* disable UARTA1 reception operation */
|
||||
UA1PWR = 0U; /* disable UARTA1 operation */
|
||||
UA1TMK = 1U; /* disable INTUA1T interrupt */
|
||||
UA1TIF = 0U; /* clear INTUA1T interrupt flag */
|
||||
UA1RMK = 1U; /* disable INTUA1R interrupt */
|
||||
UA1RIF = 0U; /* clear INTUA1R interrupt flag */
|
||||
/* Set INTUA1T level low priority */
|
||||
UA1TIC |= 0x07U;
|
||||
/* Set INTUA1R level low priority */
|
||||
UA1RIC |= 0x07U;
|
||||
//BAUDRATE = 9600
|
||||
UA1CTL1 = _03_UARTA_BASECLK_FXX_16;
|
||||
UA1CTL2 = _11_UARTA1_BASECLK_DIVISION;
|
||||
UA1CTL0 = _10_UARTA_TRANSFDIR_LSB | _00_UARTA_PARITY_NONE | _02_UARTA_DATALENGTH_8BIT | _00_UARTA_STOPLENGTH_1BIT;
|
||||
UA1OPT0 = _14_UARTA_UAnOPT0_INITIALVALUE | _00_UARTA_TRAN_DATALEVEL_NORMAL | _00_UARTA_REC_DATALEVEL_NORMAL;
|
||||
UA1PWR = 1U; /* enable UARTA1 operation */
|
||||
/* Set TXDA1 pin */
|
||||
/* Set RXDA1 pin */
|
||||
PFC3_bit.no0 = 0;
|
||||
PFCE3_bit.no0 = 0;
|
||||
PMC3_bit.no0 = 1;
|
||||
|
||||
PFC3_bit.no1 = 0;
|
||||
PFCE3_bit.no1 = 0;
|
||||
PMC3_bit.no1 = 1;
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag)
|
||||
{
|
||||
RT_ASSERT(dev != RT_NULL);
|
||||
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
|
||||
{
|
||||
/* Enable the UART Interrupt */
|
||||
UA1TIF = 0U; /* clear INTUA1T interrupt flag */
|
||||
UA1TMK = 1U; /* disable INTUA1T interrupt */
|
||||
UA1RIF = 0U; /* clear INTUA1R interrupt flag */
|
||||
UA1RMK = 0U; /* enable INTUA1R interrupt */
|
||||
UA1TXE = 1U; /* enable UARTA1 transmission operation */
|
||||
UA1RXE = 1U; /* enable UARTA1 reception operation */
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t rt_uart_close(rt_device_t dev)
|
||||
{
|
||||
RT_ASSERT(dev != RT_NULL);
|
||||
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
|
||||
{
|
||||
/* Disable the UART Interrupt */
|
||||
UA1TXE = 0U; /* disable UARTA1 transmission operation */
|
||||
UA1RXE = 0U; /* disable UARTA1 reception operation */
|
||||
UA1TMK = 1U; /* disable INTUA1T interrupt */
|
||||
UA1TIF = 0U; /* clear INTUA1T interrupt flag */
|
||||
UA1RMK = 1U; /* disable INTUA1R interrupt */
|
||||
UA1RIF = 0U; /* clear INTUA1R interrupt flag */
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
|
||||
{
|
||||
rt_uint8_t* ptr;
|
||||
struct rt_uart_v850 *uart = (struct rt_uart_v850*)dev;
|
||||
RT_ASSERT(uart != RT_NULL);
|
||||
|
||||
/* point to buffer */
|
||||
ptr = (rt_uint8_t*) buffer;
|
||||
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
|
||||
{
|
||||
while (size)
|
||||
{
|
||||
/* interrupt receive */
|
||||
rt_base_t level;
|
||||
|
||||
/* disable interrupt */
|
||||
level = rt_hw_interrupt_disable();
|
||||
if (uart->read_index != uart->save_index)
|
||||
{
|
||||
*ptr = uart->rx_buffer[uart->read_index];
|
||||
|
||||
uart->read_index ++;
|
||||
if (uart->read_index >= RT_UART_RX_BUFFER_SIZE)
|
||||
uart->read_index = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* no data in rx buffer */
|
||||
|
||||
/* enable interrupt */
|
||||
rt_hw_interrupt_enable(level);
|
||||
break;
|
||||
}
|
||||
|
||||
/* enable interrupt */
|
||||
rt_hw_interrupt_enable(level);
|
||||
|
||||
ptr ++;
|
||||
size --;
|
||||
}
|
||||
|
||||
return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
|
||||
{
|
||||
char *ptr;
|
||||
ptr = (char*)buffer;
|
||||
|
||||
if (dev->flag & RT_DEVICE_FLAG_STREAM)
|
||||
{
|
||||
/* stream mode */
|
||||
while (size)
|
||||
{
|
||||
if (*ptr == '\n')
|
||||
{
|
||||
while(UA1TSF == 1U)
|
||||
;
|
||||
UA1TX = '\r';
|
||||
}
|
||||
|
||||
/* THRE status, contain valid data */
|
||||
while(UA1TSF == 1U)
|
||||
;
|
||||
UA1TX = *ptr;
|
||||
|
||||
ptr ++;
|
||||
size --;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
while ( size != 0 )
|
||||
{
|
||||
/* THRE status, contain valid data */
|
||||
while(UA1TSF == 1U)
|
||||
;
|
||||
UA1TX = *ptr;
|
||||
|
||||
ptr++;
|
||||
size--;
|
||||
}
|
||||
}
|
||||
|
||||
return (rt_size_t) ptr - (rt_size_t) buffer;
|
||||
}
|
||||
|
||||
void rt_hw_uart_init(void)
|
||||
{
|
||||
struct rt_uart_v850* uart;
|
||||
|
||||
/* get uart device */
|
||||
uart = &uart_device;
|
||||
|
||||
/* device initialization */
|
||||
uart->parent.type = RT_Device_Class_Char;
|
||||
rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
|
||||
uart->read_index = uart->save_index = 0;
|
||||
|
||||
/* device interface */
|
||||
uart->parent.init = rt_uart_init;
|
||||
uart->parent.open = rt_uart_open;
|
||||
uart->parent.close = rt_uart_close;
|
||||
uart->parent.read = rt_uart_read;
|
||||
uart->parent.write = rt_uart_write;
|
||||
uart->parent.control = RT_NULL;
|
||||
uart->parent.user_data = RT_NULL;
|
||||
|
||||
rt_device_register(&uart->parent,
|
||||
"uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX);
|
||||
}
|
||||
#endif /* end of UART */
|
||||
|
||||
/*@}*/
|
||||
|
|
@ -0,0 +1,174 @@
|
|||
#include "macdefs.inc"
|
||||
|
||||
name OS_Core
|
||||
|
||||
COMMON INTVEC:CODE
|
||||
|
||||
;********************************************************************
|
||||
;
|
||||
; function:
|
||||
; description: Trap 0x10 vector used for context switch
|
||||
; Right now, all TRAPs to $1x are trated the same way
|
||||
;
|
||||
org 50h
|
||||
jr OSCtxSW
|
||||
|
||||
|
||||
;********************************************************************
|
||||
;
|
||||
; function:
|
||||
; description: Timer 40 compare match interrupt used for system
|
||||
; tick interrupt
|
||||
;
|
||||
org 0x220
|
||||
jr OSTickIntr
|
||||
|
||||
org 0x0520
|
||||
jr uarta1_int_r
|
||||
|
||||
RSEG CODE(1)
|
||||
|
||||
EXTERN rt_thread_switch_interrupt_flag
|
||||
EXTERN rt_interrupt_from_thread
|
||||
EXTERN rt_interrupt_to_thread
|
||||
|
||||
EXTERN rt_interrupt_enter
|
||||
EXTERN rt_interrupt_leave
|
||||
EXTERN rt_tick_increase
|
||||
EXTERN uarta1_receive_handler
|
||||
|
||||
PUBLIC rt_hw_interrupt_disable
|
||||
PUBLIC rt_hw_interrupt_enable
|
||||
PUBLIC rt_hw_context_switch_to
|
||||
PUBLIC OSCtxSW
|
||||
PUBLIC OS_Restore_CPU_Context
|
||||
|
||||
rt_hw_interrupt_disable:
|
||||
stsr psw, r1
|
||||
di
|
||||
jmp [lp]
|
||||
|
||||
rt_hw_interrupt_enable:
|
||||
ldsr r1, psw
|
||||
jmp [lp]
|
||||
|
||||
OS_Restore_CPU_Context:
|
||||
mov sp, ep
|
||||
sld.w 4[ep], r2
|
||||
sld.w 8[ep], r5
|
||||
sld.w 12[ep],r6
|
||||
sld.w 16[ep],r7
|
||||
sld.w 20[ep],r8
|
||||
sld.w 24[ep],r9
|
||||
sld.w 28[ep],r10
|
||||
sld.w 32[ep],r11
|
||||
sld.w 36[ep],r12
|
||||
sld.w 40[ep],r13
|
||||
sld.w 44[ep],r14
|
||||
sld.w 48[ep],r15
|
||||
sld.w 52[ep],r16
|
||||
|
||||
;See what was the latest interruption (trap or interrupt)
|
||||
stsr ecr, r17 ;Move ecr to r17
|
||||
mov 0x050,r1
|
||||
cmp r1, r17 ;If latest break was due to TRAP, set EP
|
||||
be _SetEP
|
||||
|
||||
_ClrEP:
|
||||
mov 0x20, r17 ;Set only ID
|
||||
ldsr r17, psw
|
||||
|
||||
;Restore caller address
|
||||
sld.w 56[ep], r1
|
||||
ldsr r1, EIPC
|
||||
;Restore PSW
|
||||
sld.w 60[ep], r1
|
||||
andi 0xffdf,r1,r1
|
||||
ldsr r1, EIPSW
|
||||
sld.w 0[ep], r1
|
||||
dispose (8+(4*14)),{r23,r24,r25,r26,r27,r28,r29,r30,r31}
|
||||
|
||||
;Return from interrupt starts new task!
|
||||
reti
|
||||
|
||||
_SetEP:
|
||||
mov 0x60, r17 ;Set both EIPC and ID bits
|
||||
ldsr r17, psw
|
||||
|
||||
;Restore caller address
|
||||
sld.w 56[ep], r1
|
||||
ldsr r1, EIPC
|
||||
;Restore PSW
|
||||
sld.w 60[ep], r1
|
||||
andi 0xffdf,r1,r1
|
||||
ldsr r1, EIPSW
|
||||
sld.w 0[ep], r1
|
||||
dispose (8+(4*14)),{r23,r24,r25,r26,r27,r28,r29,r30,r31}
|
||||
|
||||
;Return from interrupt starts new task!
|
||||
reti
|
||||
|
||||
//rseg CODE:CODE
|
||||
//public rt_hw_context_switch_to
|
||||
rt_hw_context_switch_to:
|
||||
;Load stack pointer of the task to run
|
||||
ld.w 0[r1], sp ;load sp from struct
|
||||
|
||||
;Restore all Processor registers from stack and return from interrupt
|
||||
jr OS_Restore_CPU_Context
|
||||
|
||||
OSCtxSW:
|
||||
SAVE_CPU_CTX ;Save all CPU registers
|
||||
|
||||
mov rt_interrupt_from_thread, r21
|
||||
ld.w 0[r21], r21
|
||||
st.w sp, 0[r21]
|
||||
|
||||
mov rt_interrupt_to_thread, r1
|
||||
ld.w 0[r1], r1
|
||||
ld.w 0[r1], sp
|
||||
|
||||
;Restore all Processor registers from stack and return from interrupt
|
||||
jr OS_Restore_CPU_Context
|
||||
|
||||
rt_hw_context_switch_interrupt_do:
|
||||
mov rt_thread_switch_interrupt_flag, r8
|
||||
mov 0, r9
|
||||
st.b r9, 0[r8]
|
||||
|
||||
mov rt_interrupt_from_thread, r21
|
||||
ld.w 0[r21], r21
|
||||
st.w sp, 0[r21]
|
||||
|
||||
mov rt_interrupt_to_thread, r1
|
||||
ld.w 0[r1], r1
|
||||
ld.w 0[r1], sp
|
||||
jr OS_Restore_CPU_Context
|
||||
|
||||
OSTickIntr:
|
||||
SAVE_CPU_CTX ;Save current task's registers
|
||||
jarl rt_interrupt_enter,lp
|
||||
jarl rt_tick_increase,lp
|
||||
jarl rt_interrupt_leave,lp
|
||||
|
||||
mov rt_thread_switch_interrupt_flag, r8
|
||||
ld.w 0[r8],r9
|
||||
cmp 1, r9
|
||||
be rt_hw_context_switch_interrupt_do
|
||||
|
||||
jr OS_Restore_CPU_Context
|
||||
|
||||
uarta1_int_r:
|
||||
SAVE_CPU_CTX ;Save current task's registers
|
||||
jarl rt_interrupt_enter,lp
|
||||
jarl uarta1_receive_handler,lp
|
||||
jarl rt_interrupt_leave,lp
|
||||
|
||||
mov rt_thread_switch_interrupt_flag, r8
|
||||
ld.w 0[r8],r9
|
||||
cmp 1, r9
|
||||
be rt_hw_context_switch_interrupt_do
|
||||
|
||||
jr OS_Restore_CPU_Context
|
||||
|
||||
END
|
||||
|
|
@ -10,7 +10,7 @@
|
|||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-02-23 Bernard the first version
|
||||
* 2012-09-23 lgnq initialize register r31(LP) with texit
|
||||
* 2012-09-23 lgnq set the texit to R31
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
Loading…
Reference in New Issue