[bsp/bouffalo_lab]add bl808-d0 (#7373)
Co-authored-by: chenyisong <chenyisong@tuya.com>
This commit is contained in:
flyingcys
GitHub
parent
efbdeb25ee
commit
c2ac614c59
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@ -2,4 +2,5 @@
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scons -C m0
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scons -C m0
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scons -C lp
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scons -C lp
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scons -C d0
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,24 @@
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mainmenu "RT-Thread Project Configuration"
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config BSP_DIR
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string
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option env="BSP_ROOT"
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default "."
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config RTT_DIR
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string
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option env="RTT_ROOT"
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default "../../../.."
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config PKGS_DIR
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string
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option env="PKGS_ROOT"
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default "packages"
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source "$RTT_DIR/Kconfig"
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source "$PKGS_DIR/Kconfig"
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source "board/Kconfig"
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config __STACKSIZE__
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int "stack size for interrupt"
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default 4096
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@ -0,0 +1,14 @@
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# for module compiling
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import os
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from building import *
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cwd = GetCurrentDir()
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objs = []
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list = os.listdir(cwd)
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for d in list:
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path = os.path.join(cwd, d)
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if os.path.isfile(os.path.join(path, 'SConscript')):
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objs = objs + SConscript(os.path.join(d, 'SConscript'))
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Return('objs')
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@ -0,0 +1,52 @@
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import os
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import sys
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import rtconfig
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from rtconfig import RTT_ROOT
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sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
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from building import *
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TARGET = 'rtthread.' + rtconfig.TARGET_EXT
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DefaultEnvironment(tools=[])
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env = Environment(tools = ['mingw'],
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AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
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CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
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CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
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AR = rtconfig.AR, ARFLAGS = '-rc',
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LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
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env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
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env['ASCOM'] = env['ASPPCOM']
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Export('RTT_ROOT')
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Export('rtconfig')
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SDK_ROOT = os.path.abspath('./')
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if os.path.exists(SDK_ROOT + '/../libraries'):
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libraries_path_prefix = SDK_ROOT + '/../libraries'
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else:
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libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/../libraries'
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SDK_LIB = libraries_path_prefix
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Export('SDK_LIB')
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# prepare building environment
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objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False)
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# include libraries
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objs.extend(SConscript(libraries_path_prefix + '/bl_mcu_sdk/SConscript', variant_dir='build/libraries/bl_mcu_sdk', duplicate=0))
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# include drivers
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objs.extend(SConscript(libraries_path_prefix + '/rt_drivers/SConscript', variant_dir='build/libraries/rt_drivers', duplicate=0))
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stack_size = 4096
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stack_lds = open('link_stacksize.lds', 'w')
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if GetDepend('__STACKSIZE__'): stack_size = GetDepend('__STACKSIZE__')
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stack_lds.write('__STACKSIZE__ = %d;' % stack_size)
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stack_lds.close()
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# make a building
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DoBuilding(TARGET, objs)
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@ -0,0 +1,9 @@
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from building import *
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cwd = GetCurrentDir()
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src = Glob('*.c') + Glob('*.cpp')
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CPPPATH = [cwd]
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group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
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Return('group')
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@ -0,0 +1,19 @@
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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2023/04/25 flyingcys first version
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*/
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#include <rtthread.h>
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#include <stdio.h>
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int main(void)
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{
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rt_kprintf("Hello RT-Smart!\n");
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return 0;
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}
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@ -0,0 +1,92 @@
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config BSP_USING_BL808
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bool
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select ARCH_RISCV64
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select RT_USING_COMPONENTS_INIT
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select RT_USING_USER_MAIN
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select RT_USING_CACHE
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select ARCH_MM_MMU
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select BL808_CORE_D0
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default y
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config BL808_CORE_D0
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bool
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default y
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config C906_PLIC_PHY_ADDR
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hex
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default 0xe0000000
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config IRQ_MAX_NR
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int
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default 64
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config TIMER_CLK_FREQ
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int
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default 1000000
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menu "General Drivers Configuration"
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menuconfig BSP_USING_UART3
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bool "Enable UART3"
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default y
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if BSP_USING_UART3
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choice
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prompt "UART3 TX PIN"
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default UART3_TX_USING_GPIO16
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config UART3_TX_USING_GPIO0
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bool "GPIO_0"
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config UART3_TX_USING_GPIO4
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bool "GPIO_4"
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config UART3_TX_USING_GPIO8
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bool "GPIO_8"
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config UART3_TX_USING_GPIO12
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bool "GPIO_12"
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config UART3_TX_USING_GPIO16
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bool "GPIO_16"
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config UART3_TX_USING_GPIO20
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bool "GPIO_20"
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config UART3_TX_USING_GPIO24
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bool "GPIO_24"
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config UART3_TX_USING_GPIO28
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bool "GPIO_28"
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config UART3_TX_USING_GPIO32
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bool "GPIO_32"
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config UART3_TX_USING_GPIO36
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bool "GPIO_36"
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config UART3_TX_USING_GPIO40
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bool "GPIO_40"
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config UART3_TX_USING_GPIO44
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bool "GPIO_44"
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endchoice
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choice
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prompt "UART3 RX PIN"
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default UART3_RX_USING_GPIO17
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config UART3_RX_USING_GPIO1
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bool "GPIO_1"
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config UART3_RX_USING_GPIO5
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bool "GPIO_5"
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config UART3_RX_USING_GPIO9
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bool "GPIO_9"
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config UART3_RX_USING_GPIO13
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bool "GPIO_12"
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config UART3_RX_USING_GPIO17
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bool "GPIO_17"
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config UART3_RX_USING_GPIO21
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bool "GPIO_21"
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config UART3_RX_USING_GPIO25
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bool "GPIO_25"
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config UART3_RX_USING_GPIO29
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bool "GPIO_29"
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config UART3_RX_USING_GPIO33
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bool "GPIO_33"
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config UART3_RX_USING_GPIO37
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bool "GPIO_37"
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config UART3_RX_USING_GPIO41
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bool "GPIO_41"
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config UART3_RX_USING_GPIO45
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bool "GPIO_45"
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endchoice
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endif
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endmenu
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from building import *
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cwd = GetCurrentDir()
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src = Glob('*.c') + Glob('*.cpp') + Glob('*.S')
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CPPPATH = [cwd]
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group = DefineGroup('Board', src, depend = [''], CPPPATH = CPPPATH)
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Return('group')
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@ -0,0 +1,122 @@
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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022/04/25 flyingcys first version
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include "board.h"
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#include "sbi.h"
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#ifdef RT_USING_SMART
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#include "riscv_mmu.h"
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#include "mmu.h"
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#include "page.h"
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#include "lwp_arch.h"
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rt_region_t init_page_region = {(rt_size_t)RT_HW_PAGE_START, (rt_size_t)RT_HW_PAGE_END};
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extern size_t MMUTable[];
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struct mem_desc platform_mem_desc[] = {
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{KERNEL_VADDR_START, (rt_size_t)RT_HW_PAGE_END - 1, (rt_size_t)ARCH_MAP_FAILED, NORMAL_MEM},
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};
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#define NUM_MEM_DESC (sizeof(platform_mem_desc) / sizeof(platform_mem_desc[0]))
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#endif /* RT_USING_SMART */
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void init_bss(void)
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{
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unsigned int *dst;
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dst = &__bss_start;
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while (dst < &__bss_end)
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{
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*dst++ = 0;
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}
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}
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static void __rt_assert_handler(const char *ex_string, const char *func, rt_size_t line)
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{
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rt_kprintf("(%s) assertion failed at function:%s, line number:%d \n", ex_string, func, line);
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asm volatile("ebreak" ::
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: "memory");
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}
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void primary_cpu_entry(void)
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{
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extern void entry(void);
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/* disable global interrupt */
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rt_hw_interrupt_disable();
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rt_assert_set_hook(__rt_assert_handler);
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entry();
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}
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#define IOREMAP_SIZE (1ul << 30)
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#ifndef ARCH_KERNEL_IN_HIGH_VA
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#define IOREMAP_VEND USER_VADDR_START
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#else
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#define IOREMAP_VEND 0ul
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#endif
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void rt_hw_board_init(void)
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{
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#ifdef RT_USING_SMART
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/* init data structure */
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rt_hw_mmu_map_init(&rt_kernel_space, (void *)(IOREMAP_VEND - IOREMAP_SIZE), IOREMAP_SIZE, (rt_size_t *)MMUTable, PV_OFFSET);
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/* init page allocator */
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rt_page_init(init_page_region);
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/* setup region, and enable MMU */
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rt_hw_mmu_setup(&rt_kernel_space, platform_mem_desc, NUM_MEM_DESC);
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#endif
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/* initialize memory system */
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#ifdef RT_USING_HEAP
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rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
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#endif
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/* initalize interrupt */
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rt_hw_interrupt_init();
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/* init rtthread hardware */
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rt_hw_tick_init();
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/* UART driver initialization is open by default */
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#ifdef RT_USING_SERIAL
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rt_hw_uart_init();
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#endif
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#ifdef RT_USING_CONSOLE
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/* set console device */
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rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
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#endif /* RT_USING_CONSOLE */
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#ifdef RT_USING_COMPONENTS_INIT
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rt_components_board_init();
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#endif
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#ifdef RT_USING_HEAP
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rt_kprintf("heap: [0x%08x - 0x%08x]\n", (rt_ubase_t)RT_HW_HEAP_BEGIN, (rt_ubase_t)RT_HW_HEAP_END);
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#endif /* RT_USING_HEAP */
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}
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void rt_hw_cpu_reset(void)
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{
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sbi_shutdown();
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while (1)
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;
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}
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MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reboot, reset machine);
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022/04/25 flyingcys first version
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*/
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#ifndef BOARD_H__
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#define BOARD_H__
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#include <rtconfig.h>
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extern unsigned int __bss_start;
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extern unsigned int __bss_end;
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#ifndef RT_USING_SMART
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#define KERNEL_VADDR_START 0x0
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#endif
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#define RT_HW_HEAP_BEGIN ((void *)&__bss_end)
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#define RT_HW_HEAP_END ((void *)(RT_HW_HEAP_BEGIN + 16 * 1024 * 1024))
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#define RT_HW_PAGE_START RT_HW_HEAP_END
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#define RT_HW_PAGE_END ((void *)(KERNEL_VADDR_START + 64 * 1024 * 1024))
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void rt_hw_board_init(void);
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#endif
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@ -0,0 +1,197 @@
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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020/12/12 bernard The first version
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*/
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INCLUDE "link_stacksize.lds"
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OUTPUT_ARCH( "riscv" )
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/*
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* Memory layout:
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* 0x10200000 - 0x10201000: Bootloader
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* 0x10201000 - 0x10A00000: Kernel
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|
* 0x10A00000 - 0x11200000: Heap
|
||||||
|
*/
|
||||||
|
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
SRAM : ORIGIN = 0x50100000, LENGTH = 63M
|
||||||
|
}
|
||||||
|
|
||||||
|
ENTRY(_start)
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
. = 0x50100000 ;
|
||||||
|
|
||||||
|
/* __STACKSIZE__ = 4096; */
|
||||||
|
__text_start = .;
|
||||||
|
.start :
|
||||||
|
{
|
||||||
|
*(.start);
|
||||||
|
} > SRAM
|
||||||
|
|
||||||
|
. = ALIGN(8);
|
||||||
|
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
*(.text) /* remaining code */
|
||||||
|
*(.text.*) /* remaining code */
|
||||||
|
*(.rodata) /* read-only data (constants) */
|
||||||
|
*(.rodata*)
|
||||||
|
*(.glue_7)
|
||||||
|
*(.glue_7t)
|
||||||
|
*(.gnu.linkonce.t*)
|
||||||
|
|
||||||
|
/* section information for finsh shell */
|
||||||
|
. = ALIGN(8);
|
||||||
|
__fsymtab_start = .;
|
||||||
|
KEEP(*(FSymTab))
|
||||||
|
__fsymtab_end = .;
|
||||||
|
. = ALIGN(8);
|
||||||
|
__vsymtab_start = .;
|
||||||
|
KEEP(*(VSymTab))
|
||||||
|
__vsymtab_end = .;
|
||||||
|
. = ALIGN(8);
|
||||||
|
|
||||||
|
/* section information for initial. */
|
||||||
|
. = ALIGN(8);
|
||||||
|
__rt_init_start = .;
|
||||||
|
KEEP(*(SORT(.rti_fn*)))
|
||||||
|
__rt_init_end = .;
|
||||||
|
. = ALIGN(8);
|
||||||
|
|
||||||
|
__rt_utest_tc_tab_start = .;
|
||||||
|
KEEP(*(UtestTcTab))
|
||||||
|
__rt_utest_tc_tab_end = .;
|
||||||
|
|
||||||
|
. = ALIGN(8);
|
||||||
|
_etext = .;
|
||||||
|
} > SRAM
|
||||||
|
|
||||||
|
.eh_frame_hdr :
|
||||||
|
{
|
||||||
|
*(.eh_frame_hdr)
|
||||||
|
*(.eh_frame_entry)
|
||||||
|
} > SRAM
|
||||||
|
.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } > SRAM
|
||||||
|
|
||||||
|
. = ALIGN(8);
|
||||||
|
__text_end = .;
|
||||||
|
__text_size = __text_end - __text_start;
|
||||||
|
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
*(.data)
|
||||||
|
*(.data.*)
|
||||||
|
|
||||||
|
*(.data1)
|
||||||
|
*(.data1.*)
|
||||||
|
|
||||||
|
. = ALIGN(8);
|
||||||
|
PROVIDE( __global_pointer$ = . + 0x800 );
|
||||||
|
|
||||||
|
*(.sdata)
|
||||||
|
*(.sdata.*)
|
||||||
|
} > SRAM
|
||||||
|
|
||||||
|
. = ALIGN(8);
|
||||||
|
.ctors :
|
||||||
|
{
|
||||||
|
PROVIDE(__ctors_start__ = .);
|
||||||
|
KEEP(*(SORT(.init_array.*)))
|
||||||
|
KEEP(*(.init_array))
|
||||||
|
PROVIDE(__ctors_end__ = .);
|
||||||
|
} > SRAM
|
||||||
|
|
||||||
|
.dtors :
|
||||||
|
{
|
||||||
|
PROVIDE(__dtors_start__ = .);
|
||||||
|
KEEP(*(SORT(.fini_array.*)))
|
||||||
|
KEEP(*(.fini_array))
|
||||||
|
PROVIDE(__dtors_end__ = .);
|
||||||
|
} > SRAM
|
||||||
|
|
||||||
|
/* stack for dual core */
|
||||||
|
.stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(64);
|
||||||
|
__stack_start__ = .;
|
||||||
|
|
||||||
|
. += __STACKSIZE__;
|
||||||
|
__stack_cpu0 = .;
|
||||||
|
|
||||||
|
. += __STACKSIZE__;
|
||||||
|
__stack_cpu1 = .;
|
||||||
|
} > SRAM
|
||||||
|
|
||||||
|
. = ALIGN(8);
|
||||||
|
|
||||||
|
.osdebug :
|
||||||
|
{
|
||||||
|
_osdebug_start = .;
|
||||||
|
. += 87K;
|
||||||
|
_osdebug_end = .;
|
||||||
|
} > SRAM
|
||||||
|
|
||||||
|
. = ALIGN(8);
|
||||||
|
|
||||||
|
.sbss :
|
||||||
|
{
|
||||||
|
__bss_start = .;
|
||||||
|
*(.sbss)
|
||||||
|
*(.sbss.*)
|
||||||
|
*(.dynsbss)
|
||||||
|
*(.scommon)
|
||||||
|
} > SRAM
|
||||||
|
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
*(.bss)
|
||||||
|
*(.bss.*)
|
||||||
|
*(.dynbss)
|
||||||
|
*(COMMON)
|
||||||
|
__bss_end = .;
|
||||||
|
} > SRAM
|
||||||
|
|
||||||
|
_end = .;
|
||||||
|
|
||||||
|
/* Stabs debugging sections. */
|
||||||
|
.stab 0 : { *(.stab) }
|
||||||
|
.stabstr 0 : { *(.stabstr) }
|
||||||
|
.stab.excl 0 : { *(.stab.excl) }
|
||||||
|
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||||
|
.stab.index 0 : { *(.stab.index) }
|
||||||
|
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||||
|
.comment 0 : { *(.comment) }
|
||||||
|
/* DWARF debug sections.
|
||||||
|
* Symbols in the DWARF debugging sections are relative to the beginning
|
||||||
|
* of the section so we begin them at 0. */
|
||||||
|
/* DWARF 1 */
|
||||||
|
.debug 0 : { *(.debug) }
|
||||||
|
.line 0 : { *(.line) }
|
||||||
|
/* GNU DWARF 1 extensions */
|
||||||
|
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||||
|
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||||
|
/* DWARF 1.1 and DWARF 2 */
|
||||||
|
.debug_aranges 0 : { *(.debug_aranges) }
|
||||||
|
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||||
|
/* DWARF 2 */
|
||||||
|
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
|
||||||
|
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||||
|
.debug_line 0 : { *(.debug_line) }
|
||||||
|
.debug_frame 0 : { *(.debug_frame) }
|
||||||
|
.debug_str 0 : { *(.debug_str) }
|
||||||
|
.debug_loc 0 : { *(.debug_loc) }
|
||||||
|
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||||
|
/* SGI/MIPS DWARF 2 extensions */
|
||||||
|
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||||
|
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||||
|
.debug_typenames 0 : { *(.debug_typenames) }
|
||||||
|
.debug_varnames 0 : { *(.debug_varnames) }
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,12 @@
|
||||||
|
[cfg]
|
||||||
|
# 0: no erase, 1:programmed section erase, 2: chip erase
|
||||||
|
erase = 1
|
||||||
|
# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated
|
||||||
|
skip_mode = 0x0, 0x0
|
||||||
|
# 0: not use isp mode, #1: isp mode
|
||||||
|
boot2_isp_mode = 0
|
||||||
|
|
||||||
|
[FW2]
|
||||||
|
filedir = ./whole_img_d0.bin
|
||||||
|
address = 0x100000
|
||||||
|
|
||||||
|
|
@ -0,0 +1 @@
|
||||||
|
__STACKSIZE__ = 16384;
|
||||||
|
|
@ -0,0 +1,88 @@
|
||||||
|
import os
|
||||||
|
import sys
|
||||||
|
|
||||||
|
compress_flag = 0
|
||||||
|
|
||||||
|
def create_flash_default_data(length):
|
||||||
|
datas = bytearray(length)
|
||||||
|
for i in range(length):
|
||||||
|
datas[i] = 0xff
|
||||||
|
return datas
|
||||||
|
|
||||||
|
def gen_flash_bin():
|
||||||
|
bootload_file = "./pre_build_bin/spl_bl808_d0.bin"
|
||||||
|
dtb_file = "./pre_build_bin/hw.dtb.5M" # 64k
|
||||||
|
opensbi_file = "./pre_build_bin/opensbi_v0.6.bin" # 64k
|
||||||
|
kernel_file = "./Image.bin"
|
||||||
|
|
||||||
|
kernel_out_img_file = "./whole_img_d0.bin"
|
||||||
|
|
||||||
|
bootload_file_size = os.stat(bootload_file).st_size
|
||||||
|
dtb_file_size = os.stat(dtb_file).st_size
|
||||||
|
linux_opensbi_file_size = os.stat(opensbi_file).st_size
|
||||||
|
kernel_file_size = os.stat(kernel_file).st_size
|
||||||
|
|
||||||
|
whole_img_data = create_flash_default_data(0x10000 + 0x10000 + 0x10000 + kernel_file_size)
|
||||||
|
|
||||||
|
# bootload
|
||||||
|
print("bootload size:", bootload_file_size)
|
||||||
|
fp = open(bootload_file, 'rb')
|
||||||
|
data00 = fp.read() + bytearray(0)
|
||||||
|
fp.close()
|
||||||
|
whole_img_data[0x0:0x0+len(data00)] = data00 # 0x0~0x10000 64k
|
||||||
|
|
||||||
|
# dtb
|
||||||
|
print("dtb size:", dtb_file_size)
|
||||||
|
fp = open(dtb_file, 'rb')
|
||||||
|
data0 = fp.read() + bytearray(0)
|
||||||
|
fp.close()
|
||||||
|
whole_img_data[0x10000:0x10000+len(data0)] = data0 # 0x0~0x10000 64k
|
||||||
|
|
||||||
|
# opensbi
|
||||||
|
print("opensbi size:",linux_opensbi_file_size)
|
||||||
|
fp = open(opensbi_file, 'rb')
|
||||||
|
data1 = fp.read() + bytearray(0)
|
||||||
|
fp.close()
|
||||||
|
whole_img_data[0x20000:0x20000+len(data1)] = data1 # 0x10000~0x20000 64k
|
||||||
|
|
||||||
|
# linux kernel
|
||||||
|
print("kernel img size:",kernel_file_size)
|
||||||
|
|
||||||
|
b0 = (kernel_file_size & 0xff000000) >> 24
|
||||||
|
b1 = (kernel_file_size & 0xff0000) >> 16
|
||||||
|
b2 = (kernel_file_size & 0xff00) >> 8
|
||||||
|
b3 = kernel_file_size & 0xff
|
||||||
|
# print(b0)
|
||||||
|
# print(b1)
|
||||||
|
# print(b2)
|
||||||
|
# print(b3)
|
||||||
|
header2 = [0x00,0x00,0x00,compress_flag,b3,b2,b1,b0]
|
||||||
|
whole_img_data[0x2fff8:0x30000] = bytearray((header2)) # image header
|
||||||
|
fp = open(kernel_file, 'rb')
|
||||||
|
data2 = fp.read() + bytearray(0)
|
||||||
|
fp.close()
|
||||||
|
whole_img_data[0x30000:0x30000+len(data2)] = data2 # 4M
|
||||||
|
|
||||||
|
fp = open(kernel_out_img_file, 'wb+')
|
||||||
|
fp.write(whole_img_data)
|
||||||
|
fp.close()
|
||||||
|
|
||||||
|
if __name__ == '__main__':
|
||||||
|
if(len(sys.argv) < 2):
|
||||||
|
compress_flag = 0
|
||||||
|
os.system('cp -rf rtthread_d0.bin Image.bin')
|
||||||
|
else:
|
||||||
|
if int(sys.argv[1]) == 1:
|
||||||
|
print("compress mode...")
|
||||||
|
compress_flag = 1
|
||||||
|
os.system('lz4 -9 -f rtthread_d0.bin Image.bin')
|
||||||
|
else:
|
||||||
|
compress_flag = 0
|
||||||
|
os.system('cp -rf rtthread_d0.bin Image.bin')
|
||||||
|
|
||||||
|
print("merge bin start...")
|
||||||
|
gen_flash_bin()
|
||||||
|
print("merge done!")
|
||||||
|
|
||||||
|
os.system('rm -rf Image.bin')
|
||||||
|
|
||||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1,278 @@
|
||||||
|
#ifndef RT_CONFIG_H__
|
||||||
|
#define RT_CONFIG_H__
|
||||||
|
|
||||||
|
/* Automatically generated file; DO NOT EDIT. */
|
||||||
|
/* RT-Thread Project Configuration */
|
||||||
|
|
||||||
|
/* RT-Thread Kernel */
|
||||||
|
|
||||||
|
#define RT_NAME_MAX 20
|
||||||
|
#define RT_USING_SMART
|
||||||
|
#define RT_ALIGN_SIZE 8
|
||||||
|
#define RT_THREAD_PRIORITY_32
|
||||||
|
#define RT_THREAD_PRIORITY_MAX 32
|
||||||
|
#define RT_TICK_PER_SECOND 1000
|
||||||
|
#define RT_USING_OVERFLOW_CHECK
|
||||||
|
#define RT_USING_HOOK
|
||||||
|
#define RT_HOOK_USING_FUNC_PTR
|
||||||
|
#define RT_USING_IDLE_HOOK
|
||||||
|
#define RT_IDLE_HOOK_LIST_SIZE 4
|
||||||
|
#define IDLE_THREAD_STACK_SIZE 16384
|
||||||
|
#define RT_USING_TIMER_SOFT
|
||||||
|
#define RT_TIMER_THREAD_PRIO 4
|
||||||
|
#define RT_TIMER_THREAD_STACK_SIZE 16384
|
||||||
|
|
||||||
|
/* kservice optimization */
|
||||||
|
|
||||||
|
#define RT_KSERVICE_USING_STDLIB
|
||||||
|
#define RT_KPRINTF_USING_LONGLONG
|
||||||
|
#define RT_DEBUG
|
||||||
|
#define RT_DEBUG_COLOR
|
||||||
|
|
||||||
|
/* Inter-Thread communication */
|
||||||
|
|
||||||
|
#define RT_USING_SEMAPHORE
|
||||||
|
#define RT_USING_MUTEX
|
||||||
|
#define RT_USING_EVENT
|
||||||
|
#define RT_USING_MAILBOX
|
||||||
|
#define RT_USING_MESSAGEQUEUE
|
||||||
|
|
||||||
|
/* Memory Management */
|
||||||
|
|
||||||
|
#define RT_PAGE_MAX_ORDER 11
|
||||||
|
#define RT_USING_MEMPOOL
|
||||||
|
#define RT_USING_SMALL_MEM
|
||||||
|
#define RT_USING_SMALL_MEM_AS_HEAP
|
||||||
|
#define RT_USING_MEMTRACE
|
||||||
|
#define RT_USING_HEAP
|
||||||
|
|
||||||
|
/* Kernel Device Object */
|
||||||
|
|
||||||
|
#define RT_USING_DEVICE
|
||||||
|
#define RT_USING_CONSOLE
|
||||||
|
#define RT_CONSOLEBUF_SIZE 256
|
||||||
|
#define RT_CONSOLE_DEVICE_NAME "uart3"
|
||||||
|
#define RT_VER_NUM 0x50001
|
||||||
|
#define ARCH_CPU_64BIT
|
||||||
|
#define RT_USING_CACHE
|
||||||
|
#define ARCH_MM_MMU
|
||||||
|
#define KERNEL_VADDR_START 0x50000000
|
||||||
|
#define ARCH_RISCV
|
||||||
|
#define ARCH_RISCV64
|
||||||
|
|
||||||
|
/* RT-Thread Components */
|
||||||
|
|
||||||
|
#define RT_USING_COMPONENTS_INIT
|
||||||
|
#define RT_USING_USER_MAIN
|
||||||
|
#define RT_MAIN_THREAD_STACK_SIZE 16384
|
||||||
|
#define RT_MAIN_THREAD_PRIORITY 10
|
||||||
|
#define RT_USING_MSH
|
||||||
|
#define RT_USING_FINSH
|
||||||
|
#define FINSH_USING_MSH
|
||||||
|
#define FINSH_THREAD_NAME "tshell"
|
||||||
|
#define FINSH_THREAD_PRIORITY 20
|
||||||
|
#define FINSH_THREAD_STACK_SIZE 8192
|
||||||
|
#define FINSH_USING_HISTORY
|
||||||
|
#define FINSH_HISTORY_LINES 5
|
||||||
|
#define FINSH_USING_SYMTAB
|
||||||
|
#define FINSH_CMD_SIZE 80
|
||||||
|
#define MSH_USING_BUILT_IN_COMMANDS
|
||||||
|
#define FINSH_USING_DESCRIPTION
|
||||||
|
#define FINSH_ARG_MAX 10
|
||||||
|
|
||||||
|
/* DFS: device virtual file system */
|
||||||
|
|
||||||
|
#define RT_USING_DFS
|
||||||
|
#define DFS_USING_POSIX
|
||||||
|
#define DFS_USING_WORKDIR
|
||||||
|
#define DFS_FD_MAX 16
|
||||||
|
#define RT_USING_DFS_V1
|
||||||
|
#define DFS_FILESYSTEMS_MAX 4
|
||||||
|
#define DFS_FILESYSTEM_TYPES_MAX 4
|
||||||
|
#define RT_USING_DFS_DEVFS
|
||||||
|
#define RT_USING_LWP
|
||||||
|
#define RT_LWP_MAX_NR 30
|
||||||
|
#define LWP_TASK_STACK_SIZE 16384
|
||||||
|
#define RT_CH_MSG_MAX_NR 1024
|
||||||
|
#define LWP_CONSOLE_INPUT_BUFFER_SIZE 1024
|
||||||
|
#define LWP_TID_MAX_NR 64
|
||||||
|
#define RT_LWP_SHM_MAX_NR 64
|
||||||
|
|
||||||
|
/* Device Drivers */
|
||||||
|
|
||||||
|
#define RT_USING_DEVICE_IPC
|
||||||
|
#define RT_UNAMED_PIPE_NUMBER 64
|
||||||
|
#define RT_USING_SERIAL
|
||||||
|
#define RT_USING_SERIAL_V1
|
||||||
|
#define RT_SERIAL_USING_DMA
|
||||||
|
#define RT_SERIAL_RB_BUFSZ 64
|
||||||
|
#define RT_USING_TTY
|
||||||
|
#define RT_USING_NULL
|
||||||
|
#define RT_USING_ZERO
|
||||||
|
#define RT_USING_RANDOM
|
||||||
|
#define RT_USING_RTC
|
||||||
|
|
||||||
|
/* Using USB */
|
||||||
|
|
||||||
|
|
||||||
|
/* C/C++ and POSIX layer */
|
||||||
|
|
||||||
|
#define RT_LIBC_DEFAULT_TIMEZONE 8
|
||||||
|
|
||||||
|
/* POSIX (Portable Operating System Interface) layer */
|
||||||
|
|
||||||
|
#define RT_USING_POSIX_FS
|
||||||
|
#define RT_USING_POSIX_DEVIO
|
||||||
|
#define RT_USING_POSIX_STDIO
|
||||||
|
#define RT_USING_POSIX_POLL
|
||||||
|
#define RT_USING_POSIX_SELECT
|
||||||
|
#define RT_USING_POSIX_TERMIOS
|
||||||
|
#define RT_USING_POSIX_DELAY
|
||||||
|
#define RT_USING_POSIX_CLOCK
|
||||||
|
#define RT_USING_POSIX_TIMER
|
||||||
|
|
||||||
|
/* Interprocess Communication (IPC) */
|
||||||
|
|
||||||
|
#define RT_USING_POSIX_PIPE
|
||||||
|
#define RT_USING_POSIX_PIPE_SIZE 512
|
||||||
|
|
||||||
|
/* Socket is in the 'Network' category */
|
||||||
|
|
||||||
|
|
||||||
|
/* Network */
|
||||||
|
|
||||||
|
|
||||||
|
/* Utilities */
|
||||||
|
|
||||||
|
#define RT_USING_ADT
|
||||||
|
|
||||||
|
/* RT-Thread Utestcases */
|
||||||
|
|
||||||
|
|
||||||
|
/* RT-Thread online packages */
|
||||||
|
|
||||||
|
/* IoT - internet of things */
|
||||||
|
|
||||||
|
|
||||||
|
/* Wi-Fi */
|
||||||
|
|
||||||
|
/* Marvell WiFi */
|
||||||
|
|
||||||
|
|
||||||
|
/* Wiced WiFi */
|
||||||
|
|
||||||
|
|
||||||
|
/* IoT Cloud */
|
||||||
|
|
||||||
|
|
||||||
|
/* security packages */
|
||||||
|
|
||||||
|
|
||||||
|
/* language packages */
|
||||||
|
|
||||||
|
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
|
||||||
|
|
||||||
|
|
||||||
|
/* XML: Extensible Markup Language */
|
||||||
|
|
||||||
|
|
||||||
|
/* multimedia packages */
|
||||||
|
|
||||||
|
/* LVGL: powerful and easy-to-use embedded GUI library */
|
||||||
|
|
||||||
|
|
||||||
|
/* u8g2: a monochrome graphic library */
|
||||||
|
|
||||||
|
|
||||||
|
/* tools packages */
|
||||||
|
|
||||||
|
|
||||||
|
/* system packages */
|
||||||
|
|
||||||
|
/* enhanced kernel services */
|
||||||
|
|
||||||
|
|
||||||
|
/* acceleration: Assembly language or algorithmic acceleration packages */
|
||||||
|
|
||||||
|
|
||||||
|
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
|
||||||
|
|
||||||
|
|
||||||
|
/* Micrium: Micrium software products porting for RT-Thread */
|
||||||
|
|
||||||
|
|
||||||
|
/* peripheral libraries and drivers */
|
||||||
|
|
||||||
|
/* sensors drivers */
|
||||||
|
|
||||||
|
|
||||||
|
/* touch drivers */
|
||||||
|
|
||||||
|
|
||||||
|
/* Kendryte SDK */
|
||||||
|
|
||||||
|
|
||||||
|
/* AI packages */
|
||||||
|
|
||||||
|
|
||||||
|
/* Signal Processing and Control Algorithm Packages */
|
||||||
|
|
||||||
|
|
||||||
|
/* miscellaneous packages */
|
||||||
|
|
||||||
|
/* project laboratory */
|
||||||
|
|
||||||
|
/* samples: kernel and components samples */
|
||||||
|
|
||||||
|
|
||||||
|
/* entertainment: terminal games and other interesting software packages */
|
||||||
|
|
||||||
|
|
||||||
|
/* Arduino libraries */
|
||||||
|
|
||||||
|
|
||||||
|
/* Projects */
|
||||||
|
|
||||||
|
|
||||||
|
/* Sensors */
|
||||||
|
|
||||||
|
|
||||||
|
/* Display */
|
||||||
|
|
||||||
|
|
||||||
|
/* Timing */
|
||||||
|
|
||||||
|
|
||||||
|
/* Data Processing */
|
||||||
|
|
||||||
|
|
||||||
|
/* Data Storage */
|
||||||
|
|
||||||
|
/* Communication */
|
||||||
|
|
||||||
|
|
||||||
|
/* Device Control */
|
||||||
|
|
||||||
|
|
||||||
|
/* Other */
|
||||||
|
|
||||||
|
|
||||||
|
/* Signal IO */
|
||||||
|
|
||||||
|
|
||||||
|
/* Uncategorized */
|
||||||
|
|
||||||
|
#define BSP_USING_BL808
|
||||||
|
#define BL808_CORE_D0
|
||||||
|
#define C906_PLIC_PHY_ADDR 0xe0000000
|
||||||
|
#define IRQ_MAX_NR 64
|
||||||
|
#define TIMER_CLK_FREQ 1000000
|
||||||
|
|
||||||
|
/* General Drivers Configuration */
|
||||||
|
|
||||||
|
#define BSP_USING_UART3
|
||||||
|
#define UART3_TX_USING_GPIO16
|
||||||
|
#define UART3_RX_USING_GPIO17
|
||||||
|
#define __STACKSIZE__ 16384
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,63 @@
|
||||||
|
import os
|
||||||
|
|
||||||
|
# toolchains options
|
||||||
|
ARCH ='risc-v'
|
||||||
|
VENDOR ='t-head'
|
||||||
|
CPU ='c906'
|
||||||
|
CROSS_TOOL ='gcc'
|
||||||
|
|
||||||
|
if os.getenv('RTT_ROOT'):
|
||||||
|
RTT_ROOT = os.getenv('RTT_ROOT')
|
||||||
|
else:
|
||||||
|
RTT_ROOT = r'../../../..'
|
||||||
|
|
||||||
|
if os.getenv('RTT_CC'):
|
||||||
|
CROSS_TOOL = os.getenv('RTT_CC')
|
||||||
|
|
||||||
|
if CROSS_TOOL == 'gcc':
|
||||||
|
PLATFORM = 'gcc'
|
||||||
|
EXEC_PATH = r'/opt/riscv64_musl/bin'
|
||||||
|
else:
|
||||||
|
print('Please make sure your toolchains is GNU GCC!')
|
||||||
|
exit(0)
|
||||||
|
|
||||||
|
if os.getenv('RTT_EXEC_PATH'):
|
||||||
|
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
|
||||||
|
|
||||||
|
BUILD = 'debug'
|
||||||
|
|
||||||
|
if PLATFORM == 'gcc':
|
||||||
|
# toolchains
|
||||||
|
PREFIX = os.getenv('RTT_CC_PREFIX') or 'riscv64-unknown-linux-musl-'
|
||||||
|
CC = PREFIX + 'gcc'
|
||||||
|
CXX = PREFIX + 'g++'
|
||||||
|
AS = PREFIX + 'gcc'
|
||||||
|
AR = PREFIX + 'ar'
|
||||||
|
LINK = PREFIX + 'gcc'
|
||||||
|
TARGET_EXT = 'elf'
|
||||||
|
SIZE = PREFIX + 'size'
|
||||||
|
OBJDUMP = PREFIX + 'objdump'
|
||||||
|
OBJCPY = PREFIX + 'objcopy'
|
||||||
|
|
||||||
|
DEVICE = ' -march=rv64imafdc -mabi=lp64 -mcmodel=medany'
|
||||||
|
CFLAGS = DEVICE + ' -Wall -Wno-cpp -Wno-error=unused-function -Wno-error=unused-but-set-variable -Wno-error=unused-variable -Wno-error=deprecated-declarations -Wextra -Wno-unused-parameter -Wno-sign-compare'
|
||||||
|
CFLAGS += ' -Wno-old-style-declaration -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -fshort-enums -fcommon -ffreestanding -fno-strict-aliasing -fno-jump-tables -save-temps=obj'
|
||||||
|
CFLAGS += ' -D_POSIX_SOURCE'
|
||||||
|
CFLAGS += ' -DCFG_COMPONENT_BLOG_ENABLE=0 -DBFLB_USE_HAL_DRIVER -DCPU_D0 -DBL808 -DLOG_UART_ID_0'
|
||||||
|
|
||||||
|
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -D__ASSEMBLY__'
|
||||||
|
LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T board/linker_scripts/link.lds' + ' -lsupc++ -lgcc -static'
|
||||||
|
CPATH = ''
|
||||||
|
LPATH = ''
|
||||||
|
|
||||||
|
if BUILD == 'debug':
|
||||||
|
CFLAGS += ' -O0 -gdwarf'
|
||||||
|
AFLAGS += ' -gdwarf'
|
||||||
|
else:
|
||||||
|
CFLAGS += ' -O3'
|
||||||
|
|
||||||
|
CXXFLAGS = CFLAGS
|
||||||
|
|
||||||
|
DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
|
||||||
|
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread_d0.bin\n' + SIZE + ' $TARGET \n'
|
||||||
|
POST_ACTION += 'python3 merge_rtsmart.py'
|
||||||
|
|
@ -13,3 +13,8 @@ address = 0x000000
|
||||||
[FW2]
|
[FW2]
|
||||||
filedir = ./lp/rtthread_lp.bin
|
filedir = ./lp/rtthread_lp.bin
|
||||||
address = 0xC0000
|
address = 0xC0000
|
||||||
|
|
||||||
|
[FW3]
|
||||||
|
filedir = ./d0/whole_img_d0.bin
|
||||||
|
address = 0x100000
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -59,7 +59,6 @@ CONFIG_RT_USING_MESSAGEQUEUE=y
|
||||||
#
|
#
|
||||||
# Memory Management
|
# Memory Management
|
||||||
#
|
#
|
||||||
CONFIG_RT_PAGE_MAX_ORDER=11
|
|
||||||
CONFIG_RT_USING_MEMPOOL=y
|
CONFIG_RT_USING_MEMPOOL=y
|
||||||
CONFIG_RT_USING_SMALL_MEM=y
|
CONFIG_RT_USING_SMALL_MEM=y
|
||||||
# CONFIG_RT_USING_SLAB is not set
|
# CONFIG_RT_USING_SLAB is not set
|
||||||
|
|
@ -83,7 +82,7 @@ CONFIG_RT_USING_DEVICE=y
|
||||||
CONFIG_RT_USING_CONSOLE=y
|
CONFIG_RT_USING_CONSOLE=y
|
||||||
CONFIG_RT_CONSOLEBUF_SIZE=128
|
CONFIG_RT_CONSOLEBUF_SIZE=128
|
||||||
CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
|
CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
|
||||||
CONFIG_RT_VER_NUM=0x50000
|
CONFIG_RT_VER_NUM=0x50001
|
||||||
# CONFIG_RT_USING_STDC_ATOMIC is not set
|
# CONFIG_RT_USING_STDC_ATOMIC is not set
|
||||||
# CONFIG_RT_USING_CACHE is not set
|
# CONFIG_RT_USING_CACHE is not set
|
||||||
# CONFIG_RT_USING_HW_ATOMIC is not set
|
# CONFIG_RT_USING_HW_ATOMIC is not set
|
||||||
|
|
@ -118,6 +117,10 @@ CONFIG_FINSH_USING_DESCRIPTION=y
|
||||||
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
|
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
|
||||||
# CONFIG_FINSH_USING_AUTH is not set
|
# CONFIG_FINSH_USING_AUTH is not set
|
||||||
CONFIG_FINSH_ARG_MAX=10
|
CONFIG_FINSH_ARG_MAX=10
|
||||||
|
|
||||||
|
#
|
||||||
|
# DFS: device virtual file system
|
||||||
|
#
|
||||||
# CONFIG_RT_USING_DFS is not set
|
# CONFIG_RT_USING_DFS is not set
|
||||||
# CONFIG_RT_USING_FAL is not set
|
# CONFIG_RT_USING_FAL is not set
|
||||||
|
|
||||||
|
|
@ -608,7 +611,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
|
||||||
# CONFIG_PKG_USING_LKDGUI is not set
|
# CONFIG_PKG_USING_LKDGUI is not set
|
||||||
# CONFIG_PKG_USING_NRF5X_SDK is not set
|
# CONFIG_PKG_USING_NRF5X_SDK is not set
|
||||||
# CONFIG_PKG_USING_NRFX is not set
|
# CONFIG_PKG_USING_NRFX is not set
|
||||||
# CONFIG_PKG_USING_WM_LIBRARIES is not set
|
|
||||||
|
|
||||||
#
|
#
|
||||||
# Kendryte SDK
|
# Kendryte SDK
|
||||||
|
|
@ -667,7 +669,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
|
||||||
# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
|
# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
|
||||||
# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
|
# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
|
||||||
# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
|
# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
|
||||||
# CONFIG_PKG_USING_BL_MCU_SDK is not set
|
|
||||||
# CONFIG_PKG_USING_SOFT_SERIAL is not set
|
# CONFIG_PKG_USING_SOFT_SERIAL is not set
|
||||||
# CONFIG_PKG_USING_MB85RS16 is not set
|
# CONFIG_PKG_USING_MB85RS16 is not set
|
||||||
# CONFIG_PKG_USING_RFM300 is not set
|
# CONFIG_PKG_USING_RFM300 is not set
|
||||||
|
|
@ -973,7 +974,8 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
|
||||||
#
|
#
|
||||||
CONFIG_BSP_USING_BL808=y
|
CONFIG_BSP_USING_BL808=y
|
||||||
CONFIG_BL808_CORE_M0=y
|
CONFIG_BL808_CORE_M0=y
|
||||||
# CONFIG_BSP_USING_PSRAM is not set
|
CONFIG_BSP_USING_TRIPLECORE=y
|
||||||
|
CONFIG_BSP_USING_PSRAM=y
|
||||||
|
|
||||||
#
|
#
|
||||||
# General Drivers Configuration
|
# General Drivers Configuration
|
||||||
|
|
@ -997,3 +999,5 @@ CONFIG_UART0_RX_USING_GPIO15=y
|
||||||
# CONFIG_BSP_USING_RTC is not set
|
# CONFIG_BSP_USING_RTC is not set
|
||||||
# CONFIG_BSP_USING_WDT is not set
|
# CONFIG_BSP_USING_WDT is not set
|
||||||
# CONFIG_BSP_USING_PWM is not set
|
# CONFIG_BSP_USING_PWM is not set
|
||||||
|
# CONFIG_BSP_USING_HWTIMER is not set
|
||||||
|
# CONFIG_BSP_USING_ON_CHIP_FLASH is not set
|
||||||
|
|
|
||||||
|
|
@ -11,6 +11,11 @@ config BL808_CORE_M0
|
||||||
bool
|
bool
|
||||||
default y
|
default y
|
||||||
|
|
||||||
|
config BSP_USING_TRIPLECORE
|
||||||
|
bool "Enable Triplecore"
|
||||||
|
default y
|
||||||
|
select BSP_USING_PSRAM
|
||||||
|
|
||||||
config BSP_USING_PSRAM
|
config BSP_USING_PSRAM
|
||||||
bool "Enable PSRAM"
|
bool "Enable PSRAM"
|
||||||
default n
|
default n
|
||||||
|
|
|
||||||
|
|
@ -184,16 +184,17 @@ void rt_hw_board_init(void)
|
||||||
rt_components_board_init();
|
rt_components_board_init();
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#ifdef BSP_USING_TRIPLECORE
|
||||||
/* set CPU D0 boot XIP address and flash address */
|
/* set CPU D0 boot XIP address and flash address */
|
||||||
Tzc_Sec_Set_CPU_Group(GLB_CORE_ID_D0, 1);
|
Tzc_Sec_Set_CPU_Group(GLB_CORE_ID_D0, 1);
|
||||||
/* D0 boot from 0x58000000 */
|
/* D0 boot from 0x58000000 */
|
||||||
GLB_Set_CPU_Reset_Address(GLB_CORE_ID_D0, 0x58000000);
|
GLB_Set_CPU_Reset_Address(GLB_CORE_ID_D0, 0x58000000);
|
||||||
/* D0 image offset on flash is CONFIG_D0_FLASH_ADDR+0x1000(header) */
|
/* D0 image offset on flash is CONFIG_D0_FLASH_ADDR */
|
||||||
bflb_sf_ctrl_set_flash_image_offset(CONFIG_D0_FLASH_ADDR + 0x1000, 1, SF_CTRL_FLASH_BANK0);
|
bflb_sf_ctrl_set_flash_image_offset(CONFIG_D0_FLASH_ADDR, 1, SF_CTRL_FLASH_BANK0);
|
||||||
|
|
||||||
Tzc_Sec_Set_CPU_Group(GLB_CORE_ID_LP, 0);
|
Tzc_Sec_Set_CPU_Group(GLB_CORE_ID_LP, 0);
|
||||||
/* LP boot from 0x580C0000 */
|
/* LP boot from 0x580C0000 */
|
||||||
GLB_Set_CPU_Reset_Address(GLB_CORE_ID_LP, 0x580C0000);
|
GLB_Set_CPU_Reset_Address(GLB_CORE_ID_LP, 0x58000000 + CONFIG_LP_FLASH_ADDR);
|
||||||
|
|
||||||
GLB_Release_CPU(GLB_CORE_ID_D0);
|
GLB_Release_CPU(GLB_CORE_ID_D0);
|
||||||
GLB_Release_CPU(GLB_CORE_ID_LP);
|
GLB_Release_CPU(GLB_CORE_ID_LP);
|
||||||
|
|
@ -202,6 +203,7 @@ void rt_hw_board_init(void)
|
||||||
BL_WR_WORD(IPC_SYNC_ADDR1, IPC_SYNC_FLAG);
|
BL_WR_WORD(IPC_SYNC_ADDR1, IPC_SYNC_FLAG);
|
||||||
BL_WR_WORD(IPC_SYNC_ADDR2, IPC_SYNC_FLAG);
|
BL_WR_WORD(IPC_SYNC_ADDR2, IPC_SYNC_FLAG);
|
||||||
L1C_DCache_Clean_By_Addr(IPC_SYNC_ADDR1, 8);
|
L1C_DCache_Clean_By_Addr(IPC_SYNC_ADDR1, 8);
|
||||||
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
void rt_hw_cpu_reset(void)
|
void rt_hw_cpu_reset(void)
|
||||||
|
|
|
||||||
|
|
@ -26,6 +26,7 @@
|
||||||
#include "bl808_uhs_phy.h"
|
#include "bl808_uhs_phy.h"
|
||||||
|
|
||||||
#define CONFIG_D0_FLASH_ADDR 0x100000
|
#define CONFIG_D0_FLASH_ADDR 0x100000
|
||||||
|
#define CONFIG_LP_FLASH_ADDR 0x0C0000
|
||||||
|
|
||||||
extern uint8_t __HeapBase;
|
extern uint8_t __HeapBase;
|
||||||
extern uint8_t __HeapLimit;
|
extern uint8_t __HeapLimit;
|
||||||
|
|
|
||||||
|
|
@ -36,7 +36,6 @@
|
||||||
|
|
||||||
/* Memory Management */
|
/* Memory Management */
|
||||||
|
|
||||||
#define RT_PAGE_MAX_ORDER 11
|
|
||||||
#define RT_USING_MEMPOOL
|
#define RT_USING_MEMPOOL
|
||||||
#define RT_USING_SMALL_MEM
|
#define RT_USING_SMALL_MEM
|
||||||
#define RT_USING_SMALL_MEM_AS_HEAP
|
#define RT_USING_SMALL_MEM_AS_HEAP
|
||||||
|
|
@ -48,7 +47,7 @@
|
||||||
#define RT_USING_CONSOLE
|
#define RT_USING_CONSOLE
|
||||||
#define RT_CONSOLEBUF_SIZE 128
|
#define RT_CONSOLEBUF_SIZE 128
|
||||||
#define RT_CONSOLE_DEVICE_NAME "uart0"
|
#define RT_CONSOLE_DEVICE_NAME "uart0"
|
||||||
#define RT_VER_NUM 0x50000
|
#define RT_VER_NUM 0x50001
|
||||||
#define ARCH_RISCV
|
#define ARCH_RISCV
|
||||||
#define ARCH_RISCV_FPU
|
#define ARCH_RISCV_FPU
|
||||||
#define ARCH_RISCV_FPU_S
|
#define ARCH_RISCV_FPU_S
|
||||||
|
|
@ -74,6 +73,9 @@
|
||||||
#define FINSH_USING_DESCRIPTION
|
#define FINSH_USING_DESCRIPTION
|
||||||
#define FINSH_ARG_MAX 10
|
#define FINSH_ARG_MAX 10
|
||||||
|
|
||||||
|
/* DFS: device virtual file system */
|
||||||
|
|
||||||
|
|
||||||
/* Device Drivers */
|
/* Device Drivers */
|
||||||
|
|
||||||
#define RT_USING_DEVICE_IPC
|
#define RT_USING_DEVICE_IPC
|
||||||
|
|
@ -227,6 +229,8 @@
|
||||||
|
|
||||||
#define BSP_USING_BL808
|
#define BSP_USING_BL808
|
||||||
#define BL808_CORE_M0
|
#define BL808_CORE_M0
|
||||||
|
#define BSP_USING_TRIPLECORE
|
||||||
|
#define BSP_USING_PSRAM
|
||||||
|
|
||||||
/* General Drivers Configuration */
|
/* General Drivers Configuration */
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -11,29 +11,35 @@ CPPPATH = [cwd,
|
||||||
cwd + r'/include/arch/risc-v/t-head/Core/Include',
|
cwd + r'/include/arch/risc-v/t-head/Core/Include',
|
||||||
cwd + r'/src/flash']
|
cwd + r'/src/flash']
|
||||||
|
|
||||||
src = Split("""
|
if GetDepend('BL808_CORE_D0'):
|
||||||
src/bflb_adc.c
|
src = Split("""
|
||||||
src/bflb_cks.c
|
src/bflb_gpio.c
|
||||||
src/bflb_ef_ctrl.c
|
src/bflb_uart.c
|
||||||
src/bflb_gpio.c
|
""")
|
||||||
src/bflb_i2c.c
|
else:
|
||||||
src/bflb_dma.c
|
src = Split("""
|
||||||
src/bflb_rtc.c
|
src/bflb_adc.c
|
||||||
src/bflb_sec_aes.c
|
src/bflb_cks.c
|
||||||
src/bflb_sec_sha.c
|
src/bflb_ef_ctrl.c
|
||||||
src/bflb_sec_trng.c
|
src/bflb_gpio.c
|
||||||
src/bflb_spi.c
|
src/bflb_i2c.c
|
||||||
src/bflb_timer.c
|
src/bflb_dma.c
|
||||||
src/bflb_uart.c
|
src/bflb_rtc.c
|
||||||
src/bflb_wdg.c
|
src/bflb_sec_aes.c
|
||||||
src/bflb_flash.c
|
src/bflb_sec_sha.c
|
||||||
src/flash/bflb_sf_cfg.c
|
src/bflb_sec_trng.c
|
||||||
src/flash/bflb_xip_sflash.c
|
src/bflb_spi.c
|
||||||
src/flash/bflb_sflash.c
|
src/bflb_timer.c
|
||||||
src/flash/bflb_sf_ctrl.c
|
src/bflb_uart.c
|
||||||
src/bflb_l1c.c
|
src/bflb_wdg.c
|
||||||
src/bflb_mtimer.c
|
src/bflb_flash.c
|
||||||
""")
|
src/flash/bflb_sf_cfg.c
|
||||||
|
src/flash/bflb_xip_sflash.c
|
||||||
|
src/flash/bflb_sflash.c
|
||||||
|
src/flash/bflb_sf_ctrl.c
|
||||||
|
src/bflb_l1c.c
|
||||||
|
src/bflb_mtimer.c
|
||||||
|
""")
|
||||||
|
|
||||||
if not GetDepend('BL808_CORE_D0'):
|
if not GetDepend('BL808_CORE_D0'):
|
||||||
src += ['src/bflb_irq.c']
|
src += ['src/bflb_irq.c']
|
||||||
|
|
|
||||||
|
|
@ -90,7 +90,7 @@ void assert_func(uint8_t *file, uint32_t line, uint8_t *function, uint8_t *strin
|
||||||
|
|
||||||
struct bflb_device_s {
|
struct bflb_device_s {
|
||||||
const char *name;
|
const char *name;
|
||||||
uint32_t reg_base;
|
size_t reg_base;
|
||||||
uint8_t irq_num;
|
uint8_t irq_num;
|
||||||
uint8_t idx;
|
uint8_t idx;
|
||||||
uint8_t sub_idx;
|
uint8_t sub_idx;
|
||||||
|
|
|
||||||
|
|
@ -4,8 +4,8 @@
|
||||||
void bflb_gpio_init(struct bflb_device_s *dev, uint8_t pin, uint32_t cfgset)
|
void bflb_gpio_init(struct bflb_device_s *dev, uint8_t pin, uint32_t cfgset)
|
||||||
{
|
{
|
||||||
uint32_t cfg = 0;
|
uint32_t cfg = 0;
|
||||||
uint32_t reg_base;
|
size_t reg_base;
|
||||||
uint32_t cfg_address;
|
size_t cfg_address;
|
||||||
uint8_t drive;
|
uint8_t drive;
|
||||||
uint8_t function;
|
uint8_t function;
|
||||||
uint16_t mode;
|
uint16_t mode;
|
||||||
|
|
@ -202,7 +202,7 @@ uint32_t bflb_gpio_pin32_63_read(struct bflb_device_s *dev)
|
||||||
|
|
||||||
void bflb_gpio_int_init(struct bflb_device_s *dev, uint8_t pin, uint8_t trig_mode)
|
void bflb_gpio_int_init(struct bflb_device_s *dev, uint8_t pin, uint8_t trig_mode)
|
||||||
{
|
{
|
||||||
uint32_t reg_base;
|
size_t reg_base;
|
||||||
uint32_t cfg_address;
|
uint32_t cfg_address;
|
||||||
uint32_t regval;
|
uint32_t regval;
|
||||||
|
|
||||||
|
|
@ -234,7 +234,7 @@ void bflb_gpio_int_init(struct bflb_device_s *dev, uint8_t pin, uint8_t trig_mod
|
||||||
|
|
||||||
void bflb_gpio_int_mask(struct bflb_device_s *dev, uint8_t pin, bool mask)
|
void bflb_gpio_int_mask(struct bflb_device_s *dev, uint8_t pin, bool mask)
|
||||||
{
|
{
|
||||||
uint32_t reg_base;
|
size_t reg_base;
|
||||||
uint32_t cfg_address;
|
uint32_t cfg_address;
|
||||||
uint32_t regval;
|
uint32_t regval;
|
||||||
|
|
||||||
|
|
@ -272,7 +272,7 @@ bool bflb_gpio_get_intstatus(struct bflb_device_s *dev, uint8_t pin)
|
||||||
|
|
||||||
void bflb_gpio_int_clear(struct bflb_device_s *dev, uint8_t pin)
|
void bflb_gpio_int_clear(struct bflb_device_s *dev, uint8_t pin)
|
||||||
{
|
{
|
||||||
uint32_t reg_base;
|
size_t reg_base;
|
||||||
uint32_t cfg_address;
|
uint32_t cfg_address;
|
||||||
uint32_t regval;
|
uint32_t regval;
|
||||||
|
|
||||||
|
|
@ -298,7 +298,7 @@ void bflb_gpio_int_clear(struct bflb_device_s *dev, uint8_t pin)
|
||||||
|
|
||||||
void bflb_gpio_uart_init(struct bflb_device_s *dev, uint8_t pin, uint8_t uart_func)
|
void bflb_gpio_uart_init(struct bflb_device_s *dev, uint8_t pin, uint8_t uart_func)
|
||||||
{
|
{
|
||||||
uint32_t reg_base;
|
size_t reg_base;
|
||||||
uint32_t regval;
|
uint32_t regval;
|
||||||
uint8_t sig;
|
uint8_t sig;
|
||||||
uint8_t sig_pos;
|
uint8_t sig_pos;
|
||||||
|
|
@ -412,7 +412,7 @@ void bflb_gpio_uart_init(struct bflb_device_s *dev, uint8_t pin, uint8_t uart_fu
|
||||||
int bflb_gpio_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
|
int bflb_gpio_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
|
||||||
{
|
{
|
||||||
int ret = 0;
|
int ret = 0;
|
||||||
uint32_t reg_base;
|
size_t reg_base;
|
||||||
uint32_t regval;
|
uint32_t regval;
|
||||||
uint8_t pin = arg;
|
uint8_t pin = arg;
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -7,7 +7,7 @@ void bflb_uart_init(struct bflb_device_s *dev, const struct bflb_uart_config_s *
|
||||||
uint32_t div = 0;
|
uint32_t div = 0;
|
||||||
uint32_t tx_cfg;
|
uint32_t tx_cfg;
|
||||||
uint32_t rx_cfg;
|
uint32_t rx_cfg;
|
||||||
uint32_t reg_base;
|
size_t reg_base;
|
||||||
uint32_t regval;
|
uint32_t regval;
|
||||||
|
|
||||||
reg_base = dev->reg_base;
|
reg_base = dev->reg_base;
|
||||||
|
|
@ -119,7 +119,7 @@ void bflb_uart_init(struct bflb_device_s *dev, const struct bflb_uart_config_s *
|
||||||
|
|
||||||
void bflb_uart_deinit(struct bflb_device_s *dev)
|
void bflb_uart_deinit(struct bflb_device_s *dev)
|
||||||
{
|
{
|
||||||
uint32_t reg_base;
|
size_t reg_base;
|
||||||
uint32_t tx_cfg;
|
uint32_t tx_cfg;
|
||||||
uint32_t rx_cfg;
|
uint32_t rx_cfg;
|
||||||
|
|
||||||
|
|
@ -134,7 +134,7 @@ void bflb_uart_deinit(struct bflb_device_s *dev)
|
||||||
|
|
||||||
void bflb_uart_enable(struct bflb_device_s *dev)
|
void bflb_uart_enable(struct bflb_device_s *dev)
|
||||||
{
|
{
|
||||||
uint32_t reg_base;
|
size_t reg_base;
|
||||||
uint32_t tx_cfg;
|
uint32_t tx_cfg;
|
||||||
uint32_t rx_cfg;
|
uint32_t rx_cfg;
|
||||||
|
|
||||||
|
|
@ -149,7 +149,7 @@ void bflb_uart_enable(struct bflb_device_s *dev)
|
||||||
|
|
||||||
void bflb_uart_disable(struct bflb_device_s *dev)
|
void bflb_uart_disable(struct bflb_device_s *dev)
|
||||||
{
|
{
|
||||||
uint32_t reg_base;
|
size_t reg_base;
|
||||||
uint32_t tx_cfg;
|
uint32_t tx_cfg;
|
||||||
uint32_t rx_cfg;
|
uint32_t rx_cfg;
|
||||||
|
|
||||||
|
|
@ -164,7 +164,7 @@ void bflb_uart_disable(struct bflb_device_s *dev)
|
||||||
|
|
||||||
void bflb_uart_link_txdma(struct bflb_device_s *dev, bool enable)
|
void bflb_uart_link_txdma(struct bflb_device_s *dev, bool enable)
|
||||||
{
|
{
|
||||||
uint32_t reg_base;
|
size_t reg_base;
|
||||||
uint32_t regval;
|
uint32_t regval;
|
||||||
|
|
||||||
reg_base = dev->reg_base;
|
reg_base = dev->reg_base;
|
||||||
|
|
@ -179,7 +179,7 @@ void bflb_uart_link_txdma(struct bflb_device_s *dev, bool enable)
|
||||||
|
|
||||||
void bflb_uart_link_rxdma(struct bflb_device_s *dev, bool enable)
|
void bflb_uart_link_rxdma(struct bflb_device_s *dev, bool enable)
|
||||||
{
|
{
|
||||||
uint32_t reg_base;
|
size_t reg_base;
|
||||||
uint32_t regval;
|
uint32_t regval;
|
||||||
|
|
||||||
reg_base = dev->reg_base;
|
reg_base = dev->reg_base;
|
||||||
|
|
@ -195,14 +195,14 @@ void bflb_uart_link_rxdma(struct bflb_device_s *dev, bool enable)
|
||||||
ATTR_TCM_SECTION int bflb_uart_putchar(struct bflb_device_s *dev, int ch)
|
ATTR_TCM_SECTION int bflb_uart_putchar(struct bflb_device_s *dev, int ch)
|
||||||
{
|
{
|
||||||
uint64_t start_time;
|
uint64_t start_time;
|
||||||
uint32_t reg_base;
|
size_t reg_base;
|
||||||
|
|
||||||
reg_base = dev->reg_base;
|
reg_base = dev->reg_base;
|
||||||
start_time = bflb_mtimer_get_time_ms();
|
// start_time = bflb_mtimer_get_time_ms();
|
||||||
while ((getreg32(reg_base + UART_FIFO_CONFIG_1_OFFSET) & UART_TX_FIFO_CNT_MASK) == 0) {
|
while ((getreg32(reg_base + UART_FIFO_CONFIG_1_OFFSET) & UART_TX_FIFO_CNT_MASK) == 0) {
|
||||||
if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
|
// if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
|
||||||
return -ETIMEDOUT;
|
// return -ETIMEDOUT;
|
||||||
}
|
// }
|
||||||
}
|
}
|
||||||
putreg8(ch, reg_base + UART_FIFO_WDATA_OFFSET);
|
putreg8(ch, reg_base + UART_FIFO_WDATA_OFFSET);
|
||||||
return 0;
|
return 0;
|
||||||
|
|
@ -211,7 +211,7 @@ ATTR_TCM_SECTION int bflb_uart_putchar(struct bflb_device_s *dev, int ch)
|
||||||
ATTR_TCM_SECTION int bflb_uart_getchar(struct bflb_device_s *dev)
|
ATTR_TCM_SECTION int bflb_uart_getchar(struct bflb_device_s *dev)
|
||||||
{
|
{
|
||||||
int ch = -1;
|
int ch = -1;
|
||||||
uint32_t reg_base;
|
size_t reg_base;
|
||||||
|
|
||||||
reg_base = dev->reg_base;
|
reg_base = dev->reg_base;
|
||||||
if ((getreg32(reg_base + UART_FIFO_CONFIG_1_OFFSET) & UART_RX_FIFO_CNT_MASK) != 0) {
|
if ((getreg32(reg_base + UART_FIFO_CONFIG_1_OFFSET) & UART_RX_FIFO_CNT_MASK) != 0) {
|
||||||
|
|
@ -250,7 +250,7 @@ ATTR_TCM_SECTION int bflb_uart_get(struct bflb_device_s *dev, uint8_t *data, uin
|
||||||
|
|
||||||
bool bflb_uart_txready(struct bflb_device_s *dev)
|
bool bflb_uart_txready(struct bflb_device_s *dev)
|
||||||
{
|
{
|
||||||
uint32_t reg_base;
|
size_t reg_base;
|
||||||
|
|
||||||
reg_base = dev->reg_base;
|
reg_base = dev->reg_base;
|
||||||
if ((getreg32(reg_base + UART_FIFO_CONFIG_1_OFFSET) & UART_TX_FIFO_CNT_MASK) != 0) {
|
if ((getreg32(reg_base + UART_FIFO_CONFIG_1_OFFSET) & UART_TX_FIFO_CNT_MASK) != 0) {
|
||||||
|
|
@ -262,7 +262,7 @@ bool bflb_uart_txready(struct bflb_device_s *dev)
|
||||||
|
|
||||||
bool bflb_uart_txempty(struct bflb_device_s *dev)
|
bool bflb_uart_txempty(struct bflb_device_s *dev)
|
||||||
{
|
{
|
||||||
uint32_t reg_base;
|
size_t reg_base;
|
||||||
|
|
||||||
reg_base = dev->reg_base;
|
reg_base = dev->reg_base;
|
||||||
if ((getreg32(reg_base + UART_FIFO_CONFIG_1_OFFSET) & UART_TX_FIFO_CNT_MASK) == (UART_TX_FIFO_CNT_MASK >> 1) + 1) {
|
if ((getreg32(reg_base + UART_FIFO_CONFIG_1_OFFSET) & UART_TX_FIFO_CNT_MASK) == (UART_TX_FIFO_CNT_MASK >> 1) + 1) {
|
||||||
|
|
@ -274,7 +274,7 @@ bool bflb_uart_txempty(struct bflb_device_s *dev)
|
||||||
|
|
||||||
bool bflb_uart_rxavailable(struct bflb_device_s *dev)
|
bool bflb_uart_rxavailable(struct bflb_device_s *dev)
|
||||||
{
|
{
|
||||||
uint32_t reg_base;
|
size_t reg_base;
|
||||||
|
|
||||||
reg_base = dev->reg_base;
|
reg_base = dev->reg_base;
|
||||||
return ((getreg32(reg_base + UART_FIFO_CONFIG_1_OFFSET) & UART_RX_FIFO_CNT_MASK) != 0);
|
return ((getreg32(reg_base + UART_FIFO_CONFIG_1_OFFSET) & UART_RX_FIFO_CNT_MASK) != 0);
|
||||||
|
|
@ -282,7 +282,7 @@ bool bflb_uart_rxavailable(struct bflb_device_s *dev)
|
||||||
|
|
||||||
void bflb_uart_txint_mask(struct bflb_device_s *dev, bool mask)
|
void bflb_uart_txint_mask(struct bflb_device_s *dev, bool mask)
|
||||||
{
|
{
|
||||||
uint32_t reg_base;
|
size_t reg_base;
|
||||||
uint32_t int_mask;
|
uint32_t int_mask;
|
||||||
|
|
||||||
reg_base = dev->reg_base;
|
reg_base = dev->reg_base;
|
||||||
|
|
@ -297,7 +297,7 @@ void bflb_uart_txint_mask(struct bflb_device_s *dev, bool mask)
|
||||||
|
|
||||||
void bflb_uart_rxint_mask(struct bflb_device_s *dev, bool mask)
|
void bflb_uart_rxint_mask(struct bflb_device_s *dev, bool mask)
|
||||||
{
|
{
|
||||||
uint32_t reg_base;
|
size_t reg_base;
|
||||||
uint32_t int_mask;
|
uint32_t int_mask;
|
||||||
|
|
||||||
reg_base = dev->reg_base;
|
reg_base = dev->reg_base;
|
||||||
|
|
@ -314,7 +314,7 @@ void bflb_uart_rxint_mask(struct bflb_device_s *dev, bool mask)
|
||||||
|
|
||||||
void bflb_uart_errint_mask(struct bflb_device_s *dev, bool mask)
|
void bflb_uart_errint_mask(struct bflb_device_s *dev, bool mask)
|
||||||
{
|
{
|
||||||
uint32_t reg_base;
|
size_t reg_base;
|
||||||
uint32_t int_mask;
|
uint32_t int_mask;
|
||||||
|
|
||||||
reg_base = dev->reg_base;
|
reg_base = dev->reg_base;
|
||||||
|
|
@ -339,7 +339,7 @@ void bflb_uart_errint_mask(struct bflb_device_s *dev, bool mask)
|
||||||
|
|
||||||
uint32_t bflb_uart_get_intstatus(struct bflb_device_s *dev)
|
uint32_t bflb_uart_get_intstatus(struct bflb_device_s *dev)
|
||||||
{
|
{
|
||||||
uint32_t reg_base;
|
size_t reg_base;
|
||||||
uint32_t int_status;
|
uint32_t int_status;
|
||||||
uint32_t int_mask;
|
uint32_t int_mask;
|
||||||
|
|
||||||
|
|
@ -351,7 +351,7 @@ uint32_t bflb_uart_get_intstatus(struct bflb_device_s *dev)
|
||||||
|
|
||||||
void bflb_uart_int_clear(struct bflb_device_s *dev, uint32_t int_clear)
|
void bflb_uart_int_clear(struct bflb_device_s *dev, uint32_t int_clear)
|
||||||
{
|
{
|
||||||
uint32_t reg_base;
|
size_t reg_base;
|
||||||
|
|
||||||
reg_base = dev->reg_base;
|
reg_base = dev->reg_base;
|
||||||
putreg32(int_clear, reg_base + UART_INT_CLEAR_OFFSET);
|
putreg32(int_clear, reg_base + UART_INT_CLEAR_OFFSET);
|
||||||
|
|
@ -360,7 +360,7 @@ void bflb_uart_int_clear(struct bflb_device_s *dev, uint32_t int_clear)
|
||||||
int bflb_uart_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
|
int bflb_uart_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
|
||||||
{
|
{
|
||||||
int ret = 0;
|
int ret = 0;
|
||||||
uint32_t reg_base;
|
size_t reg_base;
|
||||||
uint32_t tmp;
|
uint32_t tmp;
|
||||||
uint32_t tx_tmp;
|
uint32_t tx_tmp;
|
||||||
uint32_t rx_tmp;
|
uint32_t rx_tmp;
|
||||||
|
|
|
||||||
|
|
@ -7,6 +7,7 @@ src = []
|
||||||
|
|
||||||
CPPPATH = [cwd]
|
CPPPATH = [cwd]
|
||||||
CPPDEFINES = []
|
CPPDEFINES = []
|
||||||
|
LOCAL_CFLAGS = ' -DARCH_RISCV'
|
||||||
|
|
||||||
if GetDepend('BL808_CORE_M0'):
|
if GetDepend('BL808_CORE_M0'):
|
||||||
src += Split("""
|
src += Split("""
|
||||||
|
|
@ -52,12 +53,18 @@ if GetDepend('BL808_CORE_M0') or GetDepend('BL808_CORE_LP'):
|
||||||
std/src/bl808_uhs_phy.c
|
std/src/bl808_uhs_phy.c
|
||||||
std/port/bl808_clock.c
|
std/port/bl808_clock.c
|
||||||
""")
|
""")
|
||||||
|
elif GetDepend('BL808_CORE_D0'):
|
||||||
|
src += Split("""
|
||||||
|
std/src/bl808_ioremap.c
|
||||||
|
std/src/bl808_clock.c
|
||||||
|
std/src/bl808_hbn.c
|
||||||
|
std/port/bl808_clock.c
|
||||||
|
""")
|
||||||
|
|
||||||
CPPPATH += [cwd + r'/std/include',
|
CPPPATH += [cwd + r'/std/include',
|
||||||
cwd + r'/std/include/hardware']
|
cwd + r'/std/include/hardware']
|
||||||
|
|
||||||
CPPDEFINES += ['CONFIG_IRQ_NUM=80', 'BFLB_USE_HAL_DRIVER', 'BL808', 'default_interrupt_handler=SW_handler']
|
CPPDEFINES += ['CONFIG_IRQ_NUM=80', 'BFLB_USE_HAL_DRIVER', 'BL808', 'default_interrupt_handler=SW_handler']
|
||||||
LOCAL_CFLAGS = ' -DARCH_RISCV'
|
|
||||||
|
|
||||||
group = DefineGroup('bl808', src, depend = ['BSP_USING_BL808'], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES, LOCAL_CFLAGS = LOCAL_CFLAGS)
|
group = DefineGroup('bl808', src, depend = ['BSP_USING_BL808'], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES, LOCAL_CFLAGS = LOCAL_CFLAGS)
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,163 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file bl808_ioremap.h
|
||||||
|
* @version V1.0
|
||||||
|
* @date
|
||||||
|
* @brief This file is the standard driver header file
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
#ifndef __BL808_IOREMAP_H__
|
||||||
|
#define __BL808_IOREMAP_H__
|
||||||
|
|
||||||
|
#include <stdlib.h>
|
||||||
|
|
||||||
|
#define GLB_BASE_PHY ((uint32_t)0x20000000)
|
||||||
|
#define MIX_BASE ((uint32_t)0x20001000)
|
||||||
|
#define GPIP_BASE ((uint32_t)0x20002000)
|
||||||
|
#define PHY_BASE ((uint32_t)0x20002800)
|
||||||
|
#define AGC_BASE ((uint32_t)0x20002c00)
|
||||||
|
#define SEC_DBG_BASE ((uint32_t)0x20003000)
|
||||||
|
#define SEC_ENG_BASE ((uint32_t)0x20004000)
|
||||||
|
#define TZ1_BASE ((uint32_t)0x20005000)
|
||||||
|
#define TZC_SEC_BASE ((uint32_t)0x20005000)
|
||||||
|
#define TZ2_BASE ((uint32_t)0x20006000)
|
||||||
|
#define TZC_NSEC_BASE ((uint32_t)0x20006000)
|
||||||
|
#define EFUSE_BASE ((uint32_t)0x20056000)
|
||||||
|
#define EF_DATA_BASE ((uint32_t)0x20056000)
|
||||||
|
#define EF_CTRL_BASE ((uint32_t)0x20056000)
|
||||||
|
#define CCI_BASE_PHY ((uint32_t)0x20008000)
|
||||||
|
#define MCU_MISC_BASE ((uint32_t)0x20009000)
|
||||||
|
#define L1C_BASE ((uint32_t)0x20009000)
|
||||||
|
#define UART0_BASE ((uint32_t)0x2000a000)
|
||||||
|
#define UART1_BASE ((uint32_t)0x2000a100)
|
||||||
|
#define SPI0_BASE ((uint32_t)0x2000a200)
|
||||||
|
#define I2C0_BASE ((uint32_t)0x2000a300)
|
||||||
|
#define PWM_BASE ((uint32_t)0x2000a400)
|
||||||
|
#define TIMER0_BASE ((uint32_t)0x2000a500)
|
||||||
|
#define IR_BASE ((uint32_t)0x2000a600)
|
||||||
|
#define CKS_BASE ((uint32_t)0x2000a700)
|
||||||
|
#define IPC0_BASE ((uint32_t)0x2000a800)
|
||||||
|
#define IPC1_BASE ((uint32_t)0x2000a840)
|
||||||
|
#define I2C1_BASE ((uint32_t)0x2000a900)
|
||||||
|
#define UART2_BASE ((uint32_t)0x2000aa00)
|
||||||
|
#define I2S_BASE ((uint32_t)0x2000ab00)
|
||||||
|
#define PDM0_BASE ((uint32_t)0x2000a000)
|
||||||
|
#define LZ4D_BASE ((uint32_t)0x2000ad00)
|
||||||
|
#define QSPI_BASE ((uint32_t)0x2000b000)
|
||||||
|
#define SF_CTRL_BASE ((uint32_t)0x2000b000)
|
||||||
|
#define SF_CTRL_BUF_BASE ((uint32_t)0x2000b600)
|
||||||
|
#define DMA0_BASE ((uint32_t)0x2000c000)
|
||||||
|
#define PDS_BASE_PHY ((uint32_t)0x2000e000)
|
||||||
|
#define HBN_BASE_PHY ((uint32_t)0x2000f000)
|
||||||
|
#define AON_BASE ((uint32_t)0x2000f000)
|
||||||
|
#define EMI_MISC_BASE ((uint32_t)0x20050000)
|
||||||
|
#define PSRAM_CTRL_BASE ((uint32_t)0x20052000)
|
||||||
|
#define USB_BASE ((uint32_t)0x20072000)
|
||||||
|
#define AUDIO_BASE ((uint32_t)0x20055000)
|
||||||
|
#define SDH_BASE ((uint32_t)0x20060000)
|
||||||
|
#define EMAC_BASE ((uint32_t)0x20070000)
|
||||||
|
#define DMA1_BASE ((uint32_t)0x20071000)
|
||||||
|
|
||||||
|
/* MMSYS */
|
||||||
|
#define MM_MISC_BASE ((uint32_t)0x30000000)
|
||||||
|
#define DMA2_BASE ((uint32_t)0x30001000)
|
||||||
|
#define UART3_BASE ((uint32_t)0x30002000)
|
||||||
|
#define I2C2_BASE ((uint32_t)0x30003000)
|
||||||
|
#define I2C3_BASE ((uint32_t)0x30004000)
|
||||||
|
#define IPC2_BASE ((uint32_t)0x30005000)
|
||||||
|
#define DMA2D_BASE ((uint32_t)0x30006000)
|
||||||
|
#define CLKRST_CTRL_BASE ((uint32_t)0x30007000)
|
||||||
|
#define MM_GLB_BASE_PHY ((uint32_t)0x30007000)
|
||||||
|
#define SPI1_BASE ((uint32_t)0x30008000)
|
||||||
|
#define TIMER1_BASE ((uint32_t)0x30009000)
|
||||||
|
#define PSRAM_UHS_BASE ((uint32_t)0x3000f000)
|
||||||
|
|
||||||
|
/* SUBSYS */
|
||||||
|
#define SUB_MISC_BASE ((uint32_t)0x30010000)
|
||||||
|
#define SUB_BASE ((uint32_t)0x30011000)
|
||||||
|
#define DVP0_BASE ((uint32_t)0x30012000)
|
||||||
|
#define DVP1_BASE ((uint32_t)0x30012100)
|
||||||
|
#define DVP2_BASE ((uint32_t)0x30012200)
|
||||||
|
#define DVP3_BASE ((uint32_t)0x30012300)
|
||||||
|
#define DVP4_BASE ((uint32_t)0x30012400)
|
||||||
|
#define DVP5_BASE ((uint32_t)0x30012500)
|
||||||
|
#define DVP6_BASE ((uint32_t)0x30012600)
|
||||||
|
#define DVP7_BASE ((uint32_t)0x30012700)
|
||||||
|
#define DVP_TSRC0_BASE ((uint32_t)0x30012800)
|
||||||
|
#define DVP_TSRC1_BASE ((uint32_t)0x30012900)
|
||||||
|
#define AXI_CTRL_NR3D_BASE ((uint32_t)0x30012a00)
|
||||||
|
#define OSD_PROBE_BASE ((uint32_t)0x30012b00)
|
||||||
|
#define OSD_A_BASE ((uint32_t)0x30013000)
|
||||||
|
#define OSD_B_BASE ((uint32_t)0x30014000)
|
||||||
|
#define OSD_DP_BASE ((uint32_t)0x30015000)
|
||||||
|
#define OSD_BLEND0_OFFSET (0x000)
|
||||||
|
#define OSD_BLEND1_OFFSET (0x100)
|
||||||
|
#define OSD_BLEND2_OFFSET (0x200)
|
||||||
|
#define OSD_BLEND3_OFFSET (0x300)
|
||||||
|
#define OSD_DRAW_LOW_OFFSET (0x400)
|
||||||
|
#define OSD_DRAW_HIGH_OFFSET (0x504)
|
||||||
|
#define MIPI_BASE ((uint32_t)0x3001a000)
|
||||||
|
#define DBI_BASE ((uint32_t)0x3001b000)
|
||||||
|
#define DSI_BASE ((uint32_t)0x3001a100)
|
||||||
|
#define CSI_BASE ((uint32_t)0x3001a000)
|
||||||
|
|
||||||
|
/* CODEC_SUBSYS */
|
||||||
|
#define CODEC_MISC_BASE ((uint32_t)0x30020000)
|
||||||
|
#define MJPEG_BASE ((uint32_t)0x30021000)
|
||||||
|
#define VIDEO_BASE ((uint32_t)0x30022000)
|
||||||
|
#define MJPEG_DEC_BASE ((uint32_t)0x30023000)
|
||||||
|
#define BL_CNN_BASE ((uint32_t)0x30024000)
|
||||||
|
|
||||||
|
#define HBN_RAM_BASE ((uint32_t)0x20010000)
|
||||||
|
|
||||||
|
#define RF_BASE ((uint32_t)0x20001000)
|
||||||
|
|
||||||
|
|
||||||
|
extern void *glb_base;
|
||||||
|
extern size_t get_glb_base(void);
|
||||||
|
#define GLB_BASE get_glb_base()
|
||||||
|
|
||||||
|
extern void *cci_base;
|
||||||
|
extern size_t get_cci_base(void);
|
||||||
|
#define CCI_BASE get_cci_base()
|
||||||
|
|
||||||
|
extern void *hbn_base;
|
||||||
|
extern size_t get_hbn_base(void);
|
||||||
|
#define PDS_BASE get_pds_base()
|
||||||
|
|
||||||
|
extern void *pds_base;
|
||||||
|
extern size_t get_pds_base(void);
|
||||||
|
#define HBN_BASE get_hbn_base()
|
||||||
|
|
||||||
|
extern void *mm_glb_base;
|
||||||
|
extern size_t get_mm_glb_base(void);
|
||||||
|
#define MM_GLB_BASE get_mm_glb_base()
|
||||||
|
|
||||||
|
#endif /* __BL808_IOREMAP_H__ */
|
||||||
|
|
@ -399,6 +399,9 @@ typedef enum {
|
||||||
/*@} end of group Memory_Map_Section */
|
/*@} end of group Memory_Map_Section */
|
||||||
|
|
||||||
/* BL808 peripherals base address */
|
/* BL808 peripherals base address */
|
||||||
|
|
||||||
|
#ifndef RT_USING_SMART
|
||||||
|
|
||||||
/* WLSYS */
|
/* WLSYS */
|
||||||
#define GLB_BASE ((uint32_t)0x20000000)
|
#define GLB_BASE ((uint32_t)0x20000000)
|
||||||
#define MIX_BASE ((uint32_t)0x20001000)
|
#define MIX_BASE ((uint32_t)0x20001000)
|
||||||
|
|
@ -501,6 +504,12 @@ typedef enum {
|
||||||
|
|
||||||
#define RF_BASE ((uint32_t)0x20001000)
|
#define RF_BASE ((uint32_t)0x20001000)
|
||||||
|
|
||||||
|
#else
|
||||||
|
|
||||||
|
#include "bl808_ioremap.h"
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
typedef enum {
|
typedef enum {
|
||||||
BL_AHB_MASTER_CPU = 0x00,
|
BL_AHB_MASTER_CPU = 0x00,
|
||||||
BL_AHB_MASTER_SDU = 0x01,
|
BL_AHB_MASTER_SDU = 0x01,
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,93 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file bl808_ioremap.c
|
||||||
|
* @version V1.0
|
||||||
|
* @date
|
||||||
|
* @brief This file is the standard driver c file
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef RT_USING_SMART
|
||||||
|
|
||||||
|
#include <stdlib.h>
|
||||||
|
#include <ioremap.h>
|
||||||
|
#include "bl808.h"
|
||||||
|
|
||||||
|
void *glb_base = NULL;
|
||||||
|
size_t get_glb_base(void)
|
||||||
|
{
|
||||||
|
if(glb_base == NULL)
|
||||||
|
{
|
||||||
|
glb_base = rt_ioremap((void *)GLB_BASE_PHY, 0x1000);
|
||||||
|
}
|
||||||
|
return (size_t)glb_base;
|
||||||
|
}
|
||||||
|
|
||||||
|
void *cci_base = NULL;
|
||||||
|
size_t get_cci_base(void)
|
||||||
|
{
|
||||||
|
if(cci_base == NULL)
|
||||||
|
{
|
||||||
|
cci_base = rt_ioremap((void *)CCI_BASE_PHY, 0x1000);
|
||||||
|
}
|
||||||
|
return (size_t)cci_base;
|
||||||
|
}
|
||||||
|
|
||||||
|
void *pds_base = NULL;
|
||||||
|
size_t get_pds_base(void)
|
||||||
|
{
|
||||||
|
if(pds_base == NULL)
|
||||||
|
{
|
||||||
|
pds_base = rt_ioremap((void *)PDS_BASE_PHY, 0x1000);
|
||||||
|
}
|
||||||
|
return (size_t)pds_base;
|
||||||
|
}
|
||||||
|
|
||||||
|
void *hbn_base = NULL;
|
||||||
|
size_t get_hbn_base(void)
|
||||||
|
{
|
||||||
|
if(hbn_base == NULL)
|
||||||
|
{
|
||||||
|
hbn_base = rt_ioremap((void *)HBN_BASE_PHY, 0x1000);
|
||||||
|
}
|
||||||
|
return (size_t)hbn_base;
|
||||||
|
}
|
||||||
|
|
||||||
|
void *mm_glb_base = NULL;
|
||||||
|
size_t get_mm_glb_base(void)
|
||||||
|
{
|
||||||
|
if(mm_glb_base == NULL)
|
||||||
|
{
|
||||||
|
mm_glb_base = rt_ioremap((void *)MM_GLB_BASE_PHY, 0x1000);
|
||||||
|
}
|
||||||
|
return (size_t)mm_glb_base;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -15,6 +15,10 @@
|
||||||
#include "board.h"
|
#include "board.h"
|
||||||
#include "drv_uart.h"
|
#include "drv_uart.h"
|
||||||
|
|
||||||
|
#ifdef RT_USING_SMART
|
||||||
|
#include <ioremap.h>
|
||||||
|
#endif
|
||||||
|
|
||||||
#define DBG_TAG "DRV.UART"
|
#define DBG_TAG "DRV.UART"
|
||||||
#define DBG_LVL DBG_WARNING
|
#define DBG_LVL DBG_WARNING
|
||||||
#include <rtdbg.h>
|
#include <rtdbg.h>
|
||||||
|
|
@ -86,13 +90,69 @@
|
||||||
#define UART2_GPIO_RX GPIO_PIN_21
|
#define UART2_GPIO_RX GPIO_PIN_21
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
// uart3
|
||||||
|
#ifdef UART3_TX_USING_GPIO0
|
||||||
|
#define UART3_GPIO_TX GPIO_PIN_0
|
||||||
|
#elif defined(UART3_TX_USING_GPIO4)
|
||||||
|
#define UART3_GPIO_TX GPIO_PIN_4
|
||||||
|
#elif defined(UART3_TX_USING_GPIO8)
|
||||||
|
#define UART3_GPIO_TX GPIO_PIN_8
|
||||||
|
#elif defined(UART3_TX_USING_GPIO12)
|
||||||
|
#define UART3_GPIO_TX GPIO_PIN_12
|
||||||
|
#elif defined(UART3_TX_USING_GPIO16)
|
||||||
|
#define UART3_GPIO_TX GPIO_PIN_16
|
||||||
|
#elif defined(UART3_TX_USING_GPIO18)
|
||||||
|
#define UART3_GPIO_TX GPIO_PIN_18
|
||||||
|
#elif defined(UART3_TX_USING_GPIO20)
|
||||||
|
#define UART3_GPIO_TX GPIO_PIN_20
|
||||||
|
#elif defined(UART3_TX_USING_GPIO24)
|
||||||
|
#define UART3_GPIO_TX GPIO_PIN_24
|
||||||
|
#elif defined(UART3_TX_USING_GPIO28)
|
||||||
|
#define UART3_GPIO_TX GPIO_PIN_28
|
||||||
|
#elif defined(UART3_TX_USING_GPIO32)
|
||||||
|
#define UART3_GPIO_TX GPIO_PIN_32
|
||||||
|
#elif defined(UART3_TX_USING_GPIO36)
|
||||||
|
#define UART3_GPIO_TX GPIO_PIN_36
|
||||||
|
#elif defined(UART3_TX_USING_GPIO40)
|
||||||
|
#define UART3_GPIO_TX GPIO_PIN_40
|
||||||
|
#elif defined(UART3_TX_USING_GPIO44)
|
||||||
|
#define UART3_GPIO_TX GPIO_PIN_44
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef UART3_RX_USING_GPIO1
|
||||||
|
#define UART3_GPIO_RX GPIO_PIN_1
|
||||||
|
#elif defined(UART3_RX_USING_GPIO5)
|
||||||
|
#define UART3_GPIO_RX GPIO_PIN_5
|
||||||
|
#elif defined(UART3_RX_USING_GPIO9)
|
||||||
|
#define UART3_GPIO_RX GPIO_PIN_9
|
||||||
|
#elif defined(UART3_RX_USING_GPIO13)
|
||||||
|
#define UART3_GPIO_RX GPIO_PIN_13
|
||||||
|
#elif defined(UART3_RX_USING_GPIO17)
|
||||||
|
#define UART3_GPIO_RX GPIO_PIN_17
|
||||||
|
#elif defined(UART3_RX_USING_GPIO21)
|
||||||
|
#define UART3_GPIO_RX GPIO_PIN_21
|
||||||
|
#elif defined(UART3_RX_USING_GPIO25)
|
||||||
|
#define UART3_GPIO_RX GPIO_PIN_25
|
||||||
|
#elif defined(UART3_RX_USING_GPIO29)
|
||||||
|
#define UART3_GPIO_RX GPIO_PIN_29
|
||||||
|
#elif defined(UART3_RX_USING_GPIO33)
|
||||||
|
#define UART3_GPIO_RX GPIO_PIN_33
|
||||||
|
#elif defined(UART3_RX_USING_GPIO37)
|
||||||
|
#define UART3_GPIO_RX GPIO_PIN_37
|
||||||
|
#elif defined(UART3_RX_USING_GPIO41)
|
||||||
|
#define UART3_GPIO_RX GPIO_PIN_41
|
||||||
|
#elif defined(UART3_RX_USING_GPIO45)
|
||||||
|
#define UART3_GPIO_RX GPIO_PIN_45
|
||||||
|
#endif
|
||||||
|
|
||||||
struct device_uart
|
struct device_uart
|
||||||
{
|
{
|
||||||
struct rt_serial_device serial;
|
struct rt_serial_device serial;
|
||||||
struct bflb_device_s *bflb_device;
|
struct bflb_device_s *bflb_device;
|
||||||
};
|
};
|
||||||
|
|
||||||
static void _uart_rx_irq(int irq, void *arg)
|
static void uart_irq_handler(int irq, void *arg)
|
||||||
{
|
{
|
||||||
struct rt_serial_device *serial = (struct rt_serial_device *)arg;
|
struct rt_serial_device *serial = (struct rt_serial_device *)arg;
|
||||||
RT_ASSERT(serial != RT_NULL);
|
RT_ASSERT(serial != RT_NULL);
|
||||||
|
|
@ -212,15 +272,26 @@ static rt_err_t _uart_control(struct rt_serial_device *serial, int cmd, void *ar
|
||||||
{
|
{
|
||||||
/* disable interrupt */
|
/* disable interrupt */
|
||||||
case RT_DEVICE_CTRL_CLR_INT:
|
case RT_DEVICE_CTRL_CLR_INT:
|
||||||
|
bflb_uart_rxint_mask(uart->bflb_device, true);
|
||||||
|
#ifdef BL808_CORE_D0
|
||||||
|
rt_hw_interrupt_mask(uart->bflb_device->irq_num);
|
||||||
|
rt_hw_interrupt_install(uart->bflb_device->irq_num, RT_NULL, serial, RT_NULL);
|
||||||
|
#else
|
||||||
bflb_irq_disable(uart->bflb_device->irq_num);
|
bflb_irq_disable(uart->bflb_device->irq_num);
|
||||||
bflb_irq_attach(uart->bflb_device->irq_num, NULL, NULL);
|
bflb_irq_attach(uart->bflb_device->irq_num, RT_NULL, RT_NULL);
|
||||||
|
#endif
|
||||||
break;
|
break;
|
||||||
|
|
||||||
/* enable interrupt */
|
/* enable interrupt */
|
||||||
case RT_DEVICE_CTRL_SET_INT:
|
case RT_DEVICE_CTRL_SET_INT:
|
||||||
bflb_uart_rxint_mask(uart->bflb_device, false);
|
bflb_uart_rxint_mask(uart->bflb_device, false);
|
||||||
bflb_irq_attach(uart->bflb_device->irq_num, _uart_rx_irq, serial);
|
#ifdef BL808_CORE_D0
|
||||||
|
rt_hw_interrupt_install(uart->bflb_device->irq_num, uart_irq_handler, serial, RT_NULL);
|
||||||
|
rt_hw_interrupt_umask(uart->bflb_device->irq_num);
|
||||||
|
#else
|
||||||
|
bflb_irq_attach(uart->bflb_device->irq_num, uart_irq_handler, serial);
|
||||||
bflb_irq_enable(uart->bflb_device->irq_num);
|
bflb_irq_enable(uart->bflb_device->irq_num);
|
||||||
|
#endif
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
return RT_EOK;
|
return RT_EOK;
|
||||||
|
|
@ -265,85 +336,90 @@ static const struct rt_uart_ops _uart_ops =
|
||||||
.dma_transmit = RT_NULL
|
.dma_transmit = RT_NULL
|
||||||
};
|
};
|
||||||
|
|
||||||
|
static void _uart_init(const char *name, struct device_uart *uart, rt_uint32_t flag)
|
||||||
|
{
|
||||||
|
rt_err_t result = RT_EOK;
|
||||||
|
|
||||||
|
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
|
||||||
|
struct rt_serial_device *serial;
|
||||||
|
|
||||||
|
serial = &uart->serial;
|
||||||
|
|
||||||
|
serial->ops = &_uart_ops;
|
||||||
|
serial->config = config;
|
||||||
|
serial->config.baud_rate = UART_DEFAULT_BAUDRATE;
|
||||||
|
|
||||||
|
/* register USART device */
|
||||||
|
result = rt_hw_serial_register(serial,
|
||||||
|
name,
|
||||||
|
flag,
|
||||||
|
uart);
|
||||||
|
RT_ASSERT(result == RT_EOK);
|
||||||
|
}
|
||||||
/*
|
/*
|
||||||
* UART Initiation
|
* UART Initiation
|
||||||
*/
|
*/
|
||||||
int rt_hw_uart_init(void)
|
int rt_hw_uart_init(void)
|
||||||
{
|
{
|
||||||
rt_err_t result = 0;
|
|
||||||
struct bflb_device_s *gpio;
|
struct bflb_device_s *gpio;
|
||||||
|
rt_uint32_t flag;
|
||||||
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
|
|
||||||
struct rt_serial_device *serial;
|
|
||||||
struct device_uart *uart;
|
|
||||||
|
|
||||||
gpio = bflb_device_get_by_name("gpio");
|
gpio = bflb_device_get_by_name("gpio");
|
||||||
|
|
||||||
#ifdef BSP_USING_UART0
|
#ifdef BSP_USING_UART0
|
||||||
static struct device_uart bl_uart0;
|
static struct device_uart bl_uart0;
|
||||||
|
bl_uart0.bflb_device = bflb_device_get_by_name("uart0");
|
||||||
serial = &bl_uart0.serial;
|
|
||||||
uart = &bl_uart0;
|
|
||||||
|
|
||||||
serial->ops = &_uart_ops;
|
|
||||||
serial->config = config;
|
|
||||||
serial->config.baud_rate = UART_DEFAULT_BAUDRATE;
|
|
||||||
|
|
||||||
uart->bflb_device = bflb_device_get_by_name("uart0");
|
|
||||||
|
|
||||||
bflb_gpio_uart_init(gpio, UART0_GPIO_TX, GPIO_UART_FUNC_UART0_TX);
|
bflb_gpio_uart_init(gpio, UART0_GPIO_TX, GPIO_UART_FUNC_UART0_TX);
|
||||||
bflb_gpio_uart_init(gpio, UART0_GPIO_RX, GPIO_UART_FUNC_UART0_RX);
|
bflb_gpio_uart_init(gpio, UART0_GPIO_RX, GPIO_UART_FUNC_UART0_RX);
|
||||||
|
|
||||||
/* register USART device */
|
flag = RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX;
|
||||||
result = rt_hw_serial_register(serial,
|
|
||||||
"uart0",
|
_uart_init("uart0", &bl_uart0, flag);
|
||||||
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
|
|
||||||
uart);
|
|
||||||
RT_ASSERT(result == RT_EOK);
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef BSP_USING_UART1
|
#ifdef BSP_USING_UART1
|
||||||
static struct device_uart bl_uart1;
|
static struct device_uart bl_uart1;
|
||||||
|
bl_uart1.bflb_device = bflb_device_get_by_name("uart1");
|
||||||
|
|
||||||
serial = &bl_uart1.serial;
|
|
||||||
uart = &bl_uart1;
|
|
||||||
|
|
||||||
serial->ops = &_uart_ops;
|
|
||||||
serial->config = config;
|
|
||||||
serial->config.baud_rate = UART_DEFAULT_BAUDRATE;
|
|
||||||
|
|
||||||
uart->bflb_device = bflb_device_get_by_name("uart1");
|
|
||||||
bflb_gpio_uart_init(gpio, UART1_GPIO_TX, GPIO_UART_FUNC_UART1_TX);
|
bflb_gpio_uart_init(gpio, UART1_GPIO_TX, GPIO_UART_FUNC_UART1_TX);
|
||||||
bflb_gpio_uart_init(gpio, UART1_GPIO_RX, GPIO_UART_FUNC_UART1_RX);
|
bflb_gpio_uart_init(gpio, UART1_GPIO_RX, GPIO_UART_FUNC_UART1_RX);
|
||||||
|
|
||||||
/* register USART device */
|
flag = RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX;
|
||||||
result = rt_hw_serial_register(serial,
|
|
||||||
"uart1",
|
_uart_init("uart1", &bl_uart1, flag);
|
||||||
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
|
|
||||||
uart);
|
|
||||||
RT_ASSERT(result == RT_EOK);
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef BSP_USING_UART2
|
#ifdef BSP_USING_UART2
|
||||||
static struct device_uart bl_uart2;
|
static struct device_uart bl_uart2;
|
||||||
|
bl_uart2.bflb_device = bflb_device_get_by_name("uart2");
|
||||||
|
|
||||||
serial = &bl_uart2.serial;
|
|
||||||
uart = &bl_uart2;
|
|
||||||
|
|
||||||
serial->ops = &_uart_ops;
|
|
||||||
serial->config = config;
|
|
||||||
serial->config.baud_rate = UART_DEFAULT_BAUDRATE;
|
|
||||||
|
|
||||||
uart->bflb_device = bflb_device_get_by_name("uart2");
|
|
||||||
bflb_gpio_uart_init(gpio, UART2_GPIO_TX, GPIO_UART_FUNC_UART2_TX);
|
bflb_gpio_uart_init(gpio, UART2_GPIO_TX, GPIO_UART_FUNC_UART2_TX);
|
||||||
bflb_gpio_uart_init(gpio, UART2_GPIO_RX, GPIO_UART_FUNC_UART2_RX);
|
bflb_gpio_uart_init(gpio, UART2_GPIO_RX, GPIO_UART_FUNC_UART2_RX);
|
||||||
|
|
||||||
/* register USART device */
|
flag = RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX;
|
||||||
result = rt_hw_serial_register(serial,
|
|
||||||
"uart2",
|
_uart_init("uart2", &bl_uart2, flag);
|
||||||
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
|
|
||||||
uart);
|
|
||||||
RT_ASSERT(result == RT_EOK);
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#ifdef BSP_USING_UART3
|
||||||
|
static struct device_uart bl_uart3;
|
||||||
|
bl_uart3.bflb_device = bflb_device_get_by_name("uart3");
|
||||||
|
|
||||||
|
#ifdef RT_USING_SMART
|
||||||
|
gpio->reg_base = (size_t)rt_ioremap((void *)gpio->reg_base, 0x1000);
|
||||||
|
bl_uart3.bflb_device->reg_base = (size_t)rt_ioremap((void *)bl_uart3.bflb_device->reg_base, 0x1000);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
bflb_gpio_init(gpio, UART3_GPIO_TX, 21 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
|
||||||
|
bflb_gpio_init(gpio, UART3_GPIO_RX, 21 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
|
||||||
|
|
||||||
|
flag = RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX;
|
||||||
|
if(strcmp("uart3", RT_CONSOLE_DEVICE_NAME) == 0)
|
||||||
|
flag |= RT_DEVICE_FLAG_STREAM;
|
||||||
|
|
||||||
|
_uart_init("uart3", &bl_uart3, flag);
|
||||||
|
#endif
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue