[bsp][CV1800B] add SPI driver for CV1800B
Signed-off-by: Jingbao Qiu <qiujingbao.dlmu@gmail.com>
This commit is contained in:
Jingbao Qiu
Meco Man
parent
d856f77a55
commit
c24280f6ef
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@ -56,6 +56,7 @@ $ scons
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| gpio | 支持 | |
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| i2c | 支持 | |
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| adc | 支持 | |
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| spi | 支持 | 默认CS引脚，每个数据之间CS会拉高，请根据时序选择GPIO作为CS。若读取数据，tx需持续dummy数据。|
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## 支持开发板
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- milk-v duo: [https://milkv.io/duo](https://milkv.io/duo)
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@ -45,6 +45,11 @@ menu "General Drivers Configuration"
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select RT_USING_ADC
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default n
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config BSP_USING_SPI
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bool "Using SPI"
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select RT_USING_SPI
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default n
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menuconfig BSP_USING_WDT
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bool "Enable Watchdog Timer"
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select RT_USING_WDT
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@ -37,6 +37,11 @@ menu "General Drivers Configuration"
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select RT_USING_ADC
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default n
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config BSP_USING_SPI
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bool "Using SPI"
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select RT_USING_SPI
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default n
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menuconfig BSP_USING_PWM
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bool "Using PWM"
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select RT_USING_PWM
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@ -30,6 +30,9 @@ if GetDepend('BSP_USING_ADC'):
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if GetDepend('BSP_USING_WDT'):
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src += ['drv_wdt.c']
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if GetDepend(['BSP_USING_SPI']):
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src += ['drv_spi.c']
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if GetDepend('BSP_USING_PWM'):
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src += ['drv_pwm.c']
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CPPPATH += [cwd + r'/libraries/cv180x/pwm']
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@ -0,0 +1,235 @@
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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2024-03-28 qiujingbao first version
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*/
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#include "drv_spi.h"
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#ifdef RT_USING_SPI
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#define DBG_TAG "drv.spi"
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#define DBG_LVL DBG_INFO
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#include <rtdbg.h>
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static struct cv1800_spi cv1800_spi_obj[] =
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{
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#ifdef BSP_USING_SPI
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{
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.spi_id = SPI2,
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.device_name = "spi2",
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.fifo_len = SPI_TXFTLR,
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},
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#endif
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};
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static struct spi_regs *get_spi_base(uint8_t spi_id)
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{
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struct spi_regs *spi_base = NULL;
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switch (spi_id)
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{
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case SPI0:
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spi_base = (struct spi_regs *)SPI0_BASE;
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break;
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case SPI1:
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spi_base = (struct spi_regs *)SPI1_BASE;
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break;
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case SPI2:
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spi_base = (struct spi_regs *)SPI2_BASE;
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break;
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case SPI3:
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spi_base = (struct spi_regs *)SPI3_BASE;
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break;
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}
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return spi_base;
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}
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static rt_err_t drv_spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration)
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{
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rt_err_t ret = RT_EOK;
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struct cv1800_spi *spi_dev = RT_NULL;
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uint32_t mode;
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spi_dev = (struct cv1800_spi *)(device->bus->parent.user_data);
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spi_dev->data_width = configuration->data_width;
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/* disable spi */
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spi_enable(spi_dev->reg, 0);
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/* clear irq */
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spi_clear_irq(spi_dev->reg, SPI_IRQ_MSAK);
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/* set clk */
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ret = spi_set_frequency(spi_dev->reg, configuration->max_hz);
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if (ret)
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return ret;
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/* set mode */
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ret = gen_spi_mode(configuration, &mode);
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if (ret)
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return ret;
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spi_set_mode(spi_dev->reg, mode);
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/* set cs */
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spi_enable_cs(spi_dev->reg, 0x1);
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spi_enable(spi_dev->reg, 0x1);
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mode = mmio_read_32((uintptr_t)&spi_dev->reg->spi_ctrl0);
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LOG_D("mode: %x", mode);
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mode = mmio_read_32((uintptr_t)&spi_dev->reg->spi_baudr);
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LOG_D("spi_baudr: %x", mode);
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return ret;
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}
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int hw_spi_recv(struct cv1800_spi *dev) {
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uint32_t rever;
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uint32_t tem;
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int ret;
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rever = mmio_read_32((uintptr_t)&dev->reg->spi_rxflr);
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ret = (int)rever;
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while (rever)
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{
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tem = mmio_read_32((uintptr_t)&dev->reg->spi_dr);
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if (dev->recv_buf < dev->recv_end)
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{
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if (dev->data_width == 8)
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*(uint8_t *)(dev->recv_buf) = tem;
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else
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*(uint16_t *)(dev->recv_buf) = tem;
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}
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else
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{
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return 0;
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}
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rever--;
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dev->recv_buf += dev->data_width >> 3;
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}
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return ret;
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}
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int hw_spi_send(struct cv1800_spi *dev) {
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uint32_t txflr;
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uint32_t max;
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uint16_t value;
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txflr = mmio_read_32((uintptr_t)&dev->reg->spi_txflr);
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max = dev->fifo_len - txflr;
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while (max)
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{
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if (dev->send_end - dev->send_buf)
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{
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if (dev->data_width == 8)
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value = *(uint8_t *)(dev->send_buf);
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else
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value = *(uint16_t *)(dev->send_buf);
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}
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else
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{
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return 0;
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}
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mmio_write_32((uintptr_t)&dev->reg->spi_dr, value);
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dev->send_buf += dev->data_width >> 3;
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max--;
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}
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return 0;
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}
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static rt_ssize_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message) {
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int ret = 0;
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struct cv1800_spi *spi_dev;
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RT_ASSERT(device != RT_NULL);
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RT_ASSERT(device->bus != RT_NULL);
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RT_ASSERT(message != RT_NULL);
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spi_dev = (struct cv1800_spi *)(device->bus->parent.user_data);
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if (message->send_buf != RT_NULL)
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{
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spi_dev->send_buf = message->send_buf;
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spi_dev->send_end = (void *)((uint8_t *)spi_dev->send_buf + message->length);
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}
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if (message->recv_buf != RT_NULL)
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{
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spi_dev->recv_buf = message->recv_buf;
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spi_dev->recv_end = (void *)((uint8_t *)spi_dev->recv_buf + message->length);
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}
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/* if user use their cs */
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if (message->cs_take && device->cs_pin != PIN_NONE)
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rt_pin_write(device->cs_pin, PIN_LOW);
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if (message->send_buf)
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{
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while (spi_dev->send_buf != spi_dev->send_end)
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{
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hw_spi_send(spi_dev);
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}
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/* wait for complete */
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while (mmio_read_32((uintptr_t)&spi_dev->reg->spi_txflr)) {}
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ret = message->length;
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}
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if (message->recv_buf)
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{
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while (spi_dev->recv_buf != spi_dev->recv_end)
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{
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hw_spi_recv(spi_dev);
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}
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ret = message->length;
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}
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if (message->cs_release && device->cs_pin != PIN_NONE)
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rt_pin_write(device->cs_pin, PIN_HIGH);
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return ret;
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}
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const static struct rt_spi_ops drv_spi_ops =
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{
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drv_spi_configure,
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spixfer,
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};
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int rt_hw_spi_init(void)
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{
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rt_err_t ret = RT_EOK;
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struct spi_regs *reg = NULL;
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for (rt_size_t i = 0; i < sizeof(cv1800_spi_obj) / sizeof(struct cv1800_spi); i++) {
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/* set reg base addr */
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reg = get_spi_base(cv1800_spi_obj[i].spi_id);
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if (!reg)
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return -RT_ERROR;
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cv1800_spi_obj[i].reg = reg;
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cv1800_spi_obj[i].spi_bus.parent.user_data = &cv1800_spi_obj[i];
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/* register spix bus */
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ret = rt_spi_bus_register(&cv1800_spi_obj[i].spi_bus, cv1800_spi_obj[i].device_name, &drv_spi_ops);
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}
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return ret;
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}
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INIT_BOARD_EXPORT(rt_hw_spi_init);
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#endif /* RT_USING_SPI */
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@ -0,0 +1,155 @@
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/*
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* Copyright (c) 2006-2024, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2024-03-28 qiujingbao first version
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*/
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#ifndef __DRV_SPI_H__
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#define __DRV_SPI_H__
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#include "rtdevice.h"
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#include <rthw.h>
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#include <rtthread.h>
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#include "mmio.h"
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#include "pinctrl.h"
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#define SPI0 0x0
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#define SPI1 0x1
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#define SPI2 0x2
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#define SPI3 0x3
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#define SPI0_BASE 0x04180000
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#define SPI1_BASE 0x04190000
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#define SPI2_BASE 0x041A0000
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#define SPI3_BASE 0x041B0000
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#define SPI_IRQ_MSAK 0x3e
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#define SPI_FREQUENCY 187500000
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/* Transmit FiFO Threshold Level */
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#define SPI_TXFTLR 0xf
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#define SPI_CTRL0_DATA_FREAM_SHIFT 0
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#define SPI_CTRL0_FREAM_FORMAT_SHIFT 4
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#define SPI_CTRL0_CPHA_SHIFT 6
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#define SPI_CTRL0_CPOL_SHIFT 7
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#define SPI_CTRL0_TRANS_MODE 8
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#define SPI_CTRL0_LOOP_SHIFT 11
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#define SPI_CTRL0_CTRL_FREAM_SHIFT 12
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struct cv1800_spi {
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uint8_t spi_id;
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char *device_name;
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uint8_t fifo_len;
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uint8_t data_width;
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const void *send_buf;
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void *recv_buf;
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const void *send_end;
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void *recv_end;
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struct rt_spi_bus spi_bus;
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struct spi_regs *reg;
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};
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struct spi_regs {
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uint32_t spi_ctrl0; // 0x00
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uint32_t spi_ctrl1; // 0x04
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uint32_t spi_ssienr; // 0x08
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uint32_t spi_mwcr; // 0x0c
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uint32_t spi_ser; // 0x10
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uint32_t spi_baudr; // 0x14
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uint32_t spi_txftlr; // 0x18
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uint32_t spi_rxftlr; // 0x1c
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uint32_t spi_txflr; // 0x20
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uint32_t spi_rxflr; // 0x24
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uint32_t spi_sr; // 0x28
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uint32_t spi_imr; // 0x2c
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uint32_t spi_isr; // 0x30
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uint32_t spi_risr; // 0x34
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uint32_t spi_txoicr; // 0x38
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uint32_t spi_rxoicr; // 0x3c
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uint32_t spi_rxuicr; // 0x40
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uint32_t spi_msticr; // 0x44
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uint32_t spi_icr; // 0x48
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uint32_t spi_dmacr; // 0x4c
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uint32_t spi_dmatdlr; // 0x50
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uint32_t spi_dmardlr; // 0x54
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uint32_t spi_idr; // 0x58
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uint32_t spi_version; // 0x5c
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uint32_t spi_dr; // 0x60
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uint32_t spi_rx_sample_dly; // 0xf0
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uint32_t spi_cs_override; // 0xf4
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};
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uint32_t gen_spi_mode(struct rt_spi_configuration *cfg, uint32_t *mode)
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{
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uint32_t value = 0;
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if (cfg->data_width != 8 && cfg->data_width != 16)
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return -1;
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value |= (cfg->data_width - 1) >> SPI_CTRL0_DATA_FREAM_SHIFT;
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value |= cfg->mode >> SPI_CTRL0_CPHA_SHIFT;
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*mode = value;
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return 0;
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}
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/* set spi mode */
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static inline void spi_set_mode(struct spi_regs *reg, uint32_t mode)
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{
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mmio_write_32((uintptr_t)®->spi_ctrl0, mode);
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}
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/* clear irq */
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static inline void spi_clear_irq(struct spi_regs *reg, uint32_t mode)
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{
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mmio_write_32((uintptr_t)®->spi_imr, mode);
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}
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static inline void spi_enable_cs(struct spi_regs *reg, uint32_t enable)
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{
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if (enable)
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enable = 0x1;
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else
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enable = 0x0;
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mmio_write_32((uintptr_t)®->spi_ser, enable);
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}
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/* set spi frequency*/
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static inline rt_err_t spi_set_frequency(struct spi_regs *reg, uint32_t speed)
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{
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uint16_t value;
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/* The value of the BAUDR register must be an even number between 2-65534 */
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value = SPI_FREQUENCY / speed;
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if (value % 2 != 0)
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value++;
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if (value < 4 || value > 65534)
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value = 4;
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mmio_write_32((uintptr_t)®->spi_baudr, value);
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return RT_EOK;
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}
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static inline void spi_enable(struct spi_regs *reg, uint32_t enable)
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{
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if (enable)
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enable = 0x1;
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else
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enable = 0x0;
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mmio_write_32((uintptr_t)®->spi_ssienr, enable);
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}
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#endif /* __DRV_SPI_H__ */
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