[bsp] Adapt ls{1b,1c}dev to new mips common code
LS1C selfboot feature have been rewiritten, and we changed bare boot base to 0x80000000 to better utilize memory. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
This commit is contained in:
Jiaxun Yang
parent
4584054e17
commit
c236e8c5d5
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@ -0,0 +1,44 @@
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mainmenu "RT-Thread Configuration"
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config BSP_DIR
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string
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option env="BSP_ROOT"
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default "."
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config RTT_DIR
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string
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option env="RTT_ROOT"
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default "../.."
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config PKGS_DIR
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string
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option env="PKGS_ROOT"
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default "packages"
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source "$RTT_DIR/Kconfig"
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source "$RTT_DIR/libcpu/mips/common/Kconfig"
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source "$PKGS_DIR/Kconfig"
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config SOC_LS1B
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bool
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select RT_USING_COMPONENTS_INIT
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select RT_USING_USER_MAIN
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default y
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if RT_USING_SERIAL
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config RT_USING_UART0
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bool "Using RT_USING_UART0"
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default y
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config RT_USING_UART1
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bool "Using RT_USING_UART1"
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default n
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config RT_USING_UART3
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bool "Using RT_USING_UART3"
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default n
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config RT_UART_RX_BUFFER_SIZE
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int "The rx buffer size"
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default 64 if RT_USING_SERIAL
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default 64
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endif
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@ -1,59 +0,0 @@
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/*
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* File : application.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006-2012, RT-Thread Develop Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2010-06-25 Bernard first version
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* 2011-08-08 lgnq modified for Loongson LS1B
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*/
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#include <rtthread.h>
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#include <ls1b.h>
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#ifdef RT_USING_RTGUI
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#include <rtgui/rtgui.h>
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extern void rt_hw_dc_init(void);
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#endif
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void rt_init_thread_entry(void *parameter)
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{
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#ifdef RT_USING_RTGUI
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{
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rt_device_t dc;
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/* init Display Controller */
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rt_hw_dc_init();
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/* find Display Controller device */
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dc = rt_device_find("dc");
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/* set Display Controller device as rtgui graphic driver */
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rtgui_graphic_set_device(dc);
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}
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#endif
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#ifdef RT_USING_COMPONENTS_INIT
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/* initialization RT-Thread Components */
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rt_components_init();
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#endif
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}
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int rt_application_init(void)
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{
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rt_thread_t tid;
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/* create initialization thread */
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tid = rt_thread_create("init",
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rt_init_thread_entry, RT_NULL,
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4096, 8, 20);
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if (tid != RT_NULL)
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rt_thread_startup(tid);
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return 0;
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}
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@ -0,0 +1,17 @@
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/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-05-10 zhuangwei first version
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*/
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#include <rtthread.h>
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int main(int argc, char** argv)
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{
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return 0;
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}
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@ -1,92 +0,0 @@
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/*
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* File : startup.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006-2012, RT-Thread Develop Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2010-06-25 Bernard first version
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* 2011-08-08 lgnq modified for Loongson LS1B
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include "board.h"
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#define A_K0BASE 0x80000000
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/**
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* @addtogroup Loongson LS1B
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*/
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/*@{*/
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extern unsigned char __bss_end;
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extern int rt_application_init(void);
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extern void tlb_refill_exception(void);
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extern void general_exception(void);
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extern void irq_exception(void);
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extern void rt_hw_cache_init(void);
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extern void invalidate_writeback_dcache_all(void);
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extern void invalidate_icache_all(void);
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/**
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* This function will startup RT-Thread RTOS.
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*/
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void rtthread_startup(void)
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{
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/* disable interrupt first */
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rt_hw_interrupt_disable();
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/* init cache */
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rt_hw_cache_init();
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/* init hardware interrupt */
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rt_hw_interrupt_init();
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/* copy vector */
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rt_memcpy((void *)A_K0BASE, tlb_refill_exception, 0x20);
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rt_memcpy((void *)(A_K0BASE + 0x180), general_exception, 0x20);
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rt_memcpy((void *)(A_K0BASE + 0x200), irq_exception, 0x20);
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invalidate_writeback_dcache_all();
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invalidate_icache_all();
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/* init board */
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rt_hw_board_init();
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/* show version */
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rt_show_version();
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#ifdef RT_USING_HEAP
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rt_system_heap_init((void*)&__bss_end, (void*)RT_HW_HEAP_END);
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#endif
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/* init scheduler system */
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rt_system_scheduler_init();
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/* initialize timer */
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rt_system_timer_init();
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/* initialize timer thread */
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rt_system_timer_thread_init();
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/* init idle thread */
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rt_thread_idle_init();
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/* init application */
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rt_application_init();
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/* start scheduler */
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rt_system_scheduler_start();
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/* never reach here */
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return;
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}
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/*@}*/
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@ -11,6 +11,7 @@
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* Date Author Notes
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* 2010-06-25 Bernard first version
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* 2011-08-08 lgnq modified for Loongson LS1B
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* 2019-12-04 Jiaxun Yang Adapt new MIPS generic code
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*/
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#include <rtthread.h>
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@ -20,92 +21,68 @@
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#include "uart.h"
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#include "ls1b.h"
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#ifdef RT_USING_RTGUI
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#include <rtgui/rtgui.h>
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rt_device_t dc;
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extern void rt_hw_dc_init(void);
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#endif
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extern unsigned char __bss_end;
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/**
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* @addtogroup Loongson LS1B
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*/
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/*@{*/
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/**
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* This is the timer interrupt service routine.
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*/
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void rt_hw_timer_handler(void)
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{
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unsigned int count;
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count = read_c0_compare();
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write_c0_compare(count);
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write_c0_count(0);
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/* increase a OS tick */
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rt_tick_increase();
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}
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/**
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* This function will initial OS timer
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*/
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void rt_hw_timer_init(void)
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{
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write_c0_compare(CPU_HZ/2/RT_TICK_PER_SECOND);
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write_c0_count(0);
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}
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/**
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* This function will initial sam7s64 board.
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*/
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void rt_hw_board_init(void)
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{
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#ifdef RT_USING_UART
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/* init hardware interrupt */
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rt_hw_exception_init();
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/* init hardware interrupt */
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rt_hw_interrupt_init();
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#ifdef RT_USING_HEAP
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rt_system_heap_init((void*)&__bss_end, (void*)RT_HW_HEAP_END);
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#endif
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#ifdef RT_USING_SERIAL
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/* init hardware UART device */
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rt_hw_uart_init();
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#endif
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#ifdef RT_USING_CONSOLE
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/* set console device */
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rt_console_set_device("uart0");
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rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
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#endif
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/* init operating system timer */
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rt_hw_timer_init();
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rt_kprintf("current sr: 0x%08x\n", read_c0_status());
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}
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#define __raw_out_put(unr) \
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while (*ptr) \
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{ \
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if (*ptr == '\n') \
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{ \
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/* FIFO status, contain valid data */ \
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while (!(UART_LSR(UART##unr##_BASE) & (UARTLSR_TE | UARTLSR_TFE))); \
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/* write data */ \
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UART_DAT(UART##unr##_BASE) = '\r'; \
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} \
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/* FIFO status, contain valid data */ \
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while (!(UART_LSR(UART##unr##_BASE) & (UARTLSR_TE | UARTLSR_TFE))); \
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/* write data */ \
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UART_DAT(UART##unr##_BASE) = *ptr; \
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ptr ++; \
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}
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/* UART line status register value */
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#define UARTLSR_ERROR (1 << 7)
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#define UARTLSR_TE (1 << 6)
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#define UARTLSR_TFE (1 << 5)
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#define UARTLSR_BI (1 << 4)
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#define UARTLSR_FE (1 << 3)
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#define UARTLSR_PE (1 << 2)
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#define UARTLSR_OE (1 << 1)
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#define UARTLSR_DR (1 << 0)
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void rt_hw_console_output(const char *ptr)
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{
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#if defined(RT_USING_UART0)
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__raw_out_put(0);
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#elif defined(RT_USING_UART1)
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__raw_out_put(1);
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#elif defined(RT_USING_UART3)
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__raw_out_put(3);
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#ifdef RT_USING_FPU
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/* init hardware fpu */
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rt_hw_fpu_init();
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#endif
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}
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#ifdef RT_USING_RTGUI
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rt_device_t dc;
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/* init Display Controller */
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rt_hw_dc_init();
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/* find Display Controller device */
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dc = rt_device_find("dc");
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/* set Display Controller device as rtgui graphic driver */
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rtgui_graphic_set_device(dc);
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#endif
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#ifdef RT_USING_COMPONENTS_INIT
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rt_components_board_init();
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#endif
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}
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/*@}*/
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@ -23,7 +23,7 @@
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/*@{*/
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#if defined(RT_USING_UART) && defined(RT_USING_DEVICE)
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#if defined(RT_USING_DEVICE)
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struct rt_uart_ls1b
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{
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@ -16,6 +16,7 @@
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#define __UART_H__
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#include "ls1b.h"
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#include <rthw.h>
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#define UART0_BASE 0xBFE40000
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#define UART0_1_BASE 0xBFE41000
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@ -31,43 +32,43 @@
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#define UART5_BASE 0xBFE7C000
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/* UART registers */
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#define UART_DAT(base) __REG8(base + 0x00)
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#define UART_IER(base) __REG8(base + 0x01)
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#define UART_IIR(base) __REG8(base + 0x02)
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#define UART_FCR(base) __REG8(base + 0x02)
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#define UART_LCR(base) __REG8(base + 0x03)
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#define UART_MCR(base) __REG8(base + 0x04)
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#define UART_LSR(base) __REG8(base + 0x05)
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#define UART_MSR(base) __REG8(base + 0x06)
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#define UART_DAT(base) HWREG8(base + 0x00)
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#define UART_IER(base) HWREG8(base + 0x01)
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#define UART_IIR(base) HWREG8(base + 0x02)
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#define UART_FCR(base) HWREG8(base + 0x02)
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#define UART_LCR(base) HWREG8(base + 0x03)
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#define UART_MCR(base) HWREG8(base + 0x04)
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#define UART_LSR(base) HWREG8(base + 0x05)
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#define UART_MSR(base) HWREG8(base + 0x06)
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#define UART_LSB(base) __REG8(base + 0x00)
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#define UART_MSB(base) __REG8(base + 0x01)
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#define UART_LSB(base) HWREG8(base + 0x00)
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#define UART_MSB(base) HWREG8(base + 0x01)
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/* UART0 registers */
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#define UART0_DAT __REG8(UART0_BASE + 0x00)
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#define UART0_IER __REG8(UART0_BASE + 0x01)
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#define UART0_IIR __REG8(UART0_BASE + 0x02)
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#define UART0_FCR __REG8(UART0_BASE + 0x02)
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#define UART0_LCR __REG8(UART0_BASE + 0x03)
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#define UART0_MCR __REG8(UART0_BASE + 0x04)
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#define UART0_LSR __REG8(UART0_BASE + 0x05)
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#define UART0_MSR __REG8(UART0_BASE + 0x06)
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#define UART0_DAT HWREG8(UART0_BASE + 0x00)
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#define UART0_IER HWREG8(UART0_BASE + 0x01)
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#define UART0_IIR HWREG8(UART0_BASE + 0x02)
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#define UART0_FCR HWREG8(UART0_BASE + 0x02)
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#define UART0_LCR HWREG8(UART0_BASE + 0x03)
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#define UART0_MCR HWREG8(UART0_BASE + 0x04)
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#define UART0_LSR HWREG8(UART0_BASE + 0x05)
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#define UART0_MSR HWREG8(UART0_BASE + 0x06)
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#define UART0_LSB __REG8(UART0_BASE + 0x00)
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#define UART0_MSB __REG8(UART0_BASE + 0x01)
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#define UART0_LSB HWREG8(UART0_BASE + 0x00)
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#define UART0_MSB HWREG8(UART0_BASE + 0x01)
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/* UART1 registers */
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#define UART1_DAT __REG8(UART1_BASE + 0x00)
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#define UART1_IER __REG8(UART1_BASE + 0x01)
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#define UART1_IIR __REG8(UART1_BASE + 0x02)
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#define UART1_FCR __REG8(UART1_BASE + 0x02)
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#define UART1_LCR __REG8(UART1_BASE + 0x03)
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#define UART1_MCR __REG8(UART1_BASE + 0x04)
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#define UART1_LSR __REG8(UART1_BASE + 0x05)
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#define UART1_MSR __REG8(UART1_BASE + 0x06)
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#define UART1_DAT HWREG8(UART1_BASE + 0x00)
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#define UART1_IER HWREG8(UART1_BASE + 0x01)
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#define UART1_IIR HWREG8(UART1_BASE + 0x02)
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#define UART1_FCR HWREG8(UART1_BASE + 0x02)
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#define UART1_LCR HWREG8(UART1_BASE + 0x03)
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#define UART1_MCR HWREG8(UART1_BASE + 0x04)
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#define UART1_LSR HWREG8(UART1_BASE + 0x05)
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#define UART1_MSR HWREG8(UART1_BASE + 0x06)
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#define UART1_LSB __REG8(UART1_BASE + 0x00)
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#define UART1_MSB __REG8(UART1_BASE + 0x01)
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#define UART1_LSB HWREG8(UART1_BASE + 0x00)
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#define UART1_MSB HWREG8(UART1_BASE + 0x01)
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/* UART interrupt enable register value */
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#define UARTIER_IME (1 << 3)
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@ -11,6 +11,7 @@
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* Date Author Notes
|
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* 2010-05-17 swkyer first version
|
||||
* 2010-09-04 bernard move the beginning entry to 0x80200000
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* 2019-12-04 Jiaxun Yang Adapt new memory layout
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*/
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OUTPUT_ARCH(mips)
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@ -20,15 +21,18 @@ ENTRY(_start)
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SECTIONS
|
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{
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. = 0x80200000;
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.start :
|
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{
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*(.start);
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}
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. = ALIGN(4);
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.text :
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{
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start = ABSOLUTE(.);
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*(.selfboot);
|
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*(.selfboot_data);
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. = ALIGN(4);
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__selfboot_end = .;
|
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. = ALIGN(0x1000);
|
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__ebase_entry = .;
|
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KEEP(*(.exc_vectors))
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__ebase_end = .;
|
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*(.start);
|
||||
*(.text)
|
||||
*(.text.*)
|
||||
*(.rodata)
|
||||
|
|
@ -76,6 +80,15 @@ SECTIONS
|
|||
*(.sdata)
|
||||
*(.sdata.*)
|
||||
}
|
||||
_edata = .;
|
||||
|
||||
.stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_system_stack_start = .;
|
||||
. = . + 0x400; /* 1kb system stack */
|
||||
_system_stack = .;
|
||||
}
|
||||
|
||||
.sbss :
|
||||
{
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
this bsp is based on LS1G DEMO BOARD V1.1
|
||||
This bsp is based on LS1B DEMO BOARD V1.1
|
||||
|
||||
# download script for RT-Thread
|
||||
ifaddr syn0 192.168.1.100;load tftp://192.168.1.5/rtthread.elf;g
|
||||
|
|
@ -1,223 +1,163 @@
|
|||
#ifndef __RTTHREAD_CFG_H__
|
||||
#define __RTTHREAD_CFG_H__
|
||||
#ifndef RT_CONFIG_H__
|
||||
#define RT_CONFIG_H__
|
||||
|
||||
// <RDTConfigurator URL="http://www.rt-thread.com/eclipse">
|
||||
/* Automatically generated file; DO NOT EDIT. */
|
||||
/* RT-Thread Configuration */
|
||||
|
||||
// <integer name="RT_NAME_MAX" description="Maximal size of kernel object name length" default="6" />
|
||||
#define RT_NAME_MAX 10
|
||||
// <integer name="RT_ALIGN_SIZE" description="Alignment size for CPU architecture data access" default="4" />
|
||||
/* RT-Thread Kernel */
|
||||
|
||||
#define RT_NAME_MAX 8
|
||||
#define RT_ALIGN_SIZE 4
|
||||
// <integer name="RT_THREAD_PRIORITY_MAX" description="Maximal level of thread priority" default="32">
|
||||
// <item description="8">8</item>
|
||||
// <item description="32">32</item>
|
||||
// <item description="256">256</item>
|
||||
// </integer>
|
||||
#define RT_THREAD_PRIORITY_32
|
||||
#define RT_THREAD_PRIORITY_MAX 32
|
||||
// <integer name="RT_TICK_PER_SECOND" description="OS tick per second" default="100" />
|
||||
#define RT_TICK_PER_SECOND 100
|
||||
// <section name="RT_DEBUG" description="Kernel Debug Configuration" default="true" >
|
||||
#define RT_DEBUG
|
||||
#define RT_DEBUG_COLOR
|
||||
// <bool name="RT_THREAD_DEBUG" description="Thread debug enable" default="false" />
|
||||
// #define RT_THREAD_DEBUG
|
||||
// <bool name="RT_USING_OVERFLOW_CHECK" description="Thread stack over flow detect" default="true" />
|
||||
#define RT_USING_OVERFLOW_CHECK
|
||||
// <bool name="RT_USING_INTERRUPT_INFO" description="Show more interrupt description" default="true" />
|
||||
#define RT_USING_INTERRUPT_INFO
|
||||
// </section>
|
||||
|
||||
// <bool name="RT_USING_HOOK" description="Using hook functions" default="true" />
|
||||
#define RT_USING_HOOK
|
||||
// <section name="RT_USING_TIMER_SOFT" description="Using software timer which will start a thread to handle soft-timer" default="true" >
|
||||
// #define RT_USING_TIMER_SOFT
|
||||
// <integer name="RT_TIMER_THREAD_PRIO" description="The priority level of timer thread" default="4" />
|
||||
#define RT_USING_IDLE_HOOK
|
||||
#define RT_IDLE_HOOK_LIST_SIZE 4
|
||||
#define IDLE_THREAD_STACK_SIZE 256
|
||||
#define RT_USING_TIMER_SOFT
|
||||
#define RT_TIMER_THREAD_PRIO 4
|
||||
// <integer name="RT_TIMER_THREAD_STACK_SIZE" description="The stack size of timer thread" default="512" />
|
||||
#define RT_TIMER_THREAD_STACK_SIZE 512
|
||||
// <integer name="RT_TIMER_TICK_PER_SECOND" description="The soft-timer tick per second" default="10" />
|
||||
#define RT_TIMER_TICK_PER_SECOND 10
|
||||
// </section>
|
||||
#define RT_DEBUG
|
||||
|
||||
/* Inter-Thread communication */
|
||||
|
||||
// <section name="IPC" description="Inter-Thread communication" default="always" >
|
||||
// <bool name="RT_USING_SEMAPHORE" description="Using semaphore in the system" default="true" />
|
||||
#define RT_USING_SEMAPHORE
|
||||
// <bool name="RT_USING_MUTEX" description="Using mutex in the system" default="true" />
|
||||
#define RT_USING_MUTEX
|
||||
// <bool name="RT_USING_EVENT" description="Using event group in the system" default="true" />
|
||||
#define RT_USING_EVENT
|
||||
// <bool name="RT_USING_MAILBOX" description="Using mailbox in the system" default="true" />
|
||||
#define RT_USING_MAILBOX
|
||||
// <bool name="RT_USING_MESSAGEQUEUE" description="Using message queue in the system" default="true" />
|
||||
#define RT_USING_MESSAGEQUEUE
|
||||
// </section>
|
||||
|
||||
// <section name="MM" description="Memory Management" default="always" >
|
||||
// <bool name="RT_USING_MEMPOOL" description="Using Memory Pool Management in the system" default="true" />
|
||||
/* Memory Management */
|
||||
|
||||
#define RT_USING_MEMPOOL
|
||||
// <bool name="RT_USING_MEMHEAP" description="Using Memory Heap Object in the system" default="true" />
|
||||
#define RT_USING_MEMHEAP
|
||||
// <bool name="RT_USING_HEAP" description="Using Dynamic Heap Management in the system" default="true" />
|
||||
#define RT_USING_HEAP
|
||||
// <bool name="RT_USING_SMALL_MEM" description="Optimizing for small memory" default="false" />
|
||||
#define RT_USING_SMALL_MEM
|
||||
// <bool name="RT_USING_SLAB" description="Using SLAB memory management for large memory" default="false" />
|
||||
// #define RT_USING_SLAB
|
||||
// </section>
|
||||
#define RT_USING_HEAP
|
||||
|
||||
/* Kernel Device Object */
|
||||
|
||||
// <section name="RT_USING_DEVICE" description="Using Device Driver Framework" default="true" >
|
||||
#define RT_USING_DEVICE
|
||||
// <bool name="RT_USING_UART" description="Using UART" default="true" />
|
||||
#define RT_USING_UART
|
||||
// <bool name="RT_USING_UART0" description="Using UART0" default="true" />
|
||||
#define RT_USING_UART0
|
||||
// <integer name="RT_UART_RX_BUFFER_SIZE" description="The buffer size for UART reception" default="64" />
|
||||
#define RT_UART_RX_BUFFER_SIZE 64
|
||||
// </section>
|
||||
|
||||
// <section name="RT_USING_CONSOLE" description="Using console" default="true" >
|
||||
#define RT_USING_CONSOLE
|
||||
// <integer name="RT_CONSOLEBUF_SIZE" description="The buffer size for console output" default="128" />
|
||||
#define RT_CONSOLEBUF_SIZE 128
|
||||
// <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart" />
|
||||
#define RT_CONSOLE_DEVICE_NAME "uart0"
|
||||
// </section>
|
||||
#define RT_CONSOLE_DEVICE_NAME "uart"
|
||||
#define RT_VER_NUM 0x40002
|
||||
|
||||
/* RT-Thread Components */
|
||||
|
||||
// <bool name="RT_USING_COMPONENTS_INIT" description="Using RT-Thread components initialization" default="true" />
|
||||
#define RT_USING_COMPONENTS_INIT
|
||||
// <section name="RT_USING_FINSH" description="Using finsh as shell, which is a C-Express shell" default="true" >
|
||||
#define RT_USING_USER_MAIN
|
||||
#define RT_MAIN_THREAD_STACK_SIZE 2048
|
||||
#define RT_MAIN_THREAD_PRIORITY 10
|
||||
|
||||
/* C++ features */
|
||||
|
||||
|
||||
/* Command shell */
|
||||
|
||||
#define RT_USING_FINSH
|
||||
// <bool name="FINSH_USING_SYMTAB" description="Using symbol table in finsh shell" default="true" />
|
||||
#define FINSH_THREAD_NAME "tshell"
|
||||
#define FINSH_USING_HISTORY
|
||||
#define FINSH_HISTORY_LINES 5
|
||||
#define FINSH_USING_SYMTAB
|
||||
// <bool name="FINSH_USING_DESCRIPTION" description="Keeping description in symbol table" default="true" />
|
||||
#define FINSH_USING_DESCRIPTION
|
||||
// <integer name="FINSH_THREAD_STACK_SIZE" description="The stack size for finsh thread" default="4096" />
|
||||
#define FINSH_THREAD_PRIORITY 20
|
||||
#define FINSH_THREAD_STACK_SIZE 4096
|
||||
// </section>
|
||||
#define FINSH_CMD_SIZE 80
|
||||
#define FINSH_USING_MSH
|
||||
#define FINSH_USING_MSH_DEFAULT
|
||||
#define FINSH_ARG_MAX 10
|
||||
|
||||
// <section name="RT_USING_LIBC" description="C Runtime library setting" default="true" >
|
||||
#define RT_USING_LIBC
|
||||
// <bool name="RT_USING_PTHREADS" description="Using POSIX threads library" default="true" />
|
||||
#define RT_USING_PTHREADS
|
||||
// </section>
|
||||
/* Device virtual file system */
|
||||
|
||||
// <section name="RT_USING_DFS" description="Device file system" default="true" >
|
||||
// #define RT_USING_DFS
|
||||
// <bool name="DFS_USING_WORKDIR" description="Using working directory" default="true" />
|
||||
// #define DFS_USING_WORKDIR
|
||||
// <integer name="DFS_FILESYSTEMS_MAX" description="The maximal number of mounted file system" default="4" />
|
||||
#define RT_USING_DFS
|
||||
#define DFS_USING_WORKDIR
|
||||
#define DFS_FILESYSTEMS_MAX 2
|
||||
// <integer name="DFS_FD_MAX" description="The maximal number of opened files" default="4" />
|
||||
#define DFS_FD_MAX 4
|
||||
// <bool name="RT_USING_DFS_ELMFAT" description="Using ELM FatFs" default="true" />
|
||||
#define RT_USING_DFS_ELMFAT
|
||||
// <integer name="RT_DFS_ELM_USE_LFN" description="Support long file name" default="0">
|
||||
// <item description="LFN1">1</item>
|
||||
// <item description="LFN1">2</item>
|
||||
// </integer>
|
||||
#define RT_DFS_ELM_USE_LFN 1
|
||||
// <integer name="RT_DFS_ELM_MAX_LFN" description="Maximal size of file name length" default="255" />
|
||||
#define RT_DFS_ELM_MAX_LFN 64
|
||||
// <bool name="RT_USING_DFS_YAFFS2" description="Using YAFFS2" default="false" />
|
||||
// #define RT_USING_DFS_YAFFS2
|
||||
// <bool name="RT_USING_DFS_UFFS" description="Using UFFS" default="false" />
|
||||
// #define RT_USING_DFS_UFFS
|
||||
// <bool name="RT_USING_DFS_DEVFS" description="Using devfs for device objects" default="true" />
|
||||
// #define RT_USING_DFS_DEVFS
|
||||
// <bool name="RT_USING_DFS_NFS" description="Using NFS v3 client file system" default="false" />
|
||||
// #define RT_USING_DFS_NFS
|
||||
// <string name="RT_NFS_HOST_EXPORT" description="NFSv3 host export" default="192.168.1.5:/" />
|
||||
#define RT_NFS_HOST_EXPORT "192.168.1.5:/"
|
||||
// </section>
|
||||
#define DFS_FILESYSTEM_TYPES_MAX 2
|
||||
#define DFS_FD_MAX 16
|
||||
#define RT_USING_DFS_DEVFS
|
||||
|
||||
// <section name="RT_USING_LWIP" description="lwip, a lightweight TCP/IP protocol stack" default="true" >
|
||||
// #define RT_USING_LWIP
|
||||
// <bool name="RT_LWIP_ICMP" description="Enable ICMP protocol" default="true" />
|
||||
#define RT_LWIP_ICMP
|
||||
// <bool name="RT_LWIP_IGMP" description="Enable IGMP protocol" default="false" />
|
||||
// #define RT_LWIP_IGMP
|
||||
// <bool name="RT_LWIP_UDP" description="Enable UDP protocol" default="true" />
|
||||
#define RT_LWIP_UDP
|
||||
// <bool name="RT_LWIP_TCP" description="Enable TCP protocol" default="true" />
|
||||
#define RT_LWIP_TCP
|
||||
// <bool name="RT_LWIP_DNS" description="Enable DNS protocol" default="true" />
|
||||
#define RT_LWIP_DNS
|
||||
// <integer name="RT_LWIP_PBUF_NUM" description="Maximal number of buffers in the pbuf pool" default="4" />
|
||||
#define RT_LWIP_PBUF_NUM 4
|
||||
// <integer name="RT_LWIP_TCP_PCB_NUM" description="Maximal number of simultaneously active TCP connections" default="5" />
|
||||
#define RT_LWIP_TCP_PCB_NUM 3
|
||||
// <integer name="RT_LWIP_TCP_SND_BUF" description="TCP sender buffer size" default="8192" />
|
||||
#define RT_LWIP_TCP_SND_BUF 2048
|
||||
// <integer name="RT_LWIP_TCP_WND" description="TCP receive window" default="8192" />
|
||||
#define RT_LWIP_TCP_WND 2048
|
||||
// <bool name="RT_LWIP_SNMP" description="Enable SNMP protocol" default="false" />
|
||||
// #define RT_LWIP_SNMP
|
||||
// <bool name="RT_LWIP_DHCP" description="Enable DHCP client to get IP address" default="false" />
|
||||
// #define RT_LWIP_DHCP
|
||||
// <integer name="RT_LWIP_TCP_SEG_NUM" description="the number of simultaneously queued TCP" default="4" />
|
||||
#define RT_LWIP_TCP_SEG_NUM 4
|
||||
// <integer name="RT_LWIP_TCPTHREAD_PRIORITY" description="the thread priority of TCP thread" default="128" />
|
||||
#define RT_LWIP_TCPTHREAD_PRIORITY 12
|
||||
// <integer name="RT_LWIP_TCPTHREAD_MBOX_SIZE" description="the mail box size of TCP thread to wait for" default="32" />
|
||||
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
|
||||
// <integer name="RT_LWIP_TCPTHREAD_STACKSIZE" description="the thread stack size of TCP thread" default="4096" />
|
||||
#define RT_LWIP_TCPTHREAD_STACKSIZE 4096
|
||||
// <integer name="RT_LWIP_ETHTHREAD_PRIORITY" description="the thread priority of ethnetif thread" default="144" />
|
||||
#define RT_LWIP_ETHTHREAD_PRIORITY 14
|
||||
// <integer name="RT_LWIP_ETHTHREAD_MBOX_SIZE" description="the mail box size of ethnetif thread to wait for" default="8" />
|
||||
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
|
||||
// <integer name="RT_LWIP_ETHTHREAD_STACKSIZE" description="the stack size of ethnetif thread" default="512" />
|
||||
#define RT_LWIP_ETHTHREAD_STACKSIZE 512
|
||||
// <ipaddr name="RT_LWIP_IPADDR" description="IP address of device" default="192.168.1.30" />
|
||||
#define RT_LWIP_IPADDR0 192
|
||||
#define RT_LWIP_IPADDR1 168
|
||||
#define RT_LWIP_IPADDR2 1
|
||||
#define RT_LWIP_IPADDR3 30
|
||||
// <ipaddr name="RT_LWIP_GWADDR" description="Gateway address of device" default="192.168.1.1" />
|
||||
#define RT_LWIP_GWADDR0 192
|
||||
#define RT_LWIP_GWADDR1 168
|
||||
#define RT_LWIP_GWADDR2 1
|
||||
#define RT_LWIP_GWADDR3 1
|
||||
// <ipaddr name="RT_LWIP_MSKADDR" description="Mask address of device" default="255.255.255.0" />
|
||||
#define RT_LWIP_MSKADDR0 255
|
||||
#define RT_LWIP_MSKADDR1 255
|
||||
#define RT_LWIP_MSKADDR2 255
|
||||
#define RT_LWIP_MSKADDR3 0
|
||||
// </section>
|
||||
/* Device Drivers */
|
||||
|
||||
// <section name="RT_USING_MODULE" description="Application module" default="true" >
|
||||
// #define RT_USING_MODULE
|
||||
// </section>
|
||||
#define RT_USING_DEVICE_IPC
|
||||
#define RT_PIPE_BUFSZ 512
|
||||
#define RT_USING_SERIAL
|
||||
#define RT_SERIAL_USING_DMA
|
||||
#define RT_SERIAL_RB_BUFSZ 64
|
||||
#define RT_USING_PIN
|
||||
|
||||
// <section name="RT_USING_RTGUI" description="RTGUI, a graphic user interface" default="true" >
|
||||
// #define RT_USING_RTGUI
|
||||
// <integer name="RTGUI_NAME_MAX" description="Maximal size of RTGUI object name length" default="16" />
|
||||
#define RTGUI_NAME_MAX 16
|
||||
// <bool name="RTGUI_USING_FONT16" description="Support 16 weight font" default="true" />
|
||||
#define RTGUI_USING_FONT16
|
||||
// <bool name="RTGUI_USING_FONT12" description="Support 12 weight font" default="true" />
|
||||
#define RTGUI_USING_FONT12
|
||||
// <bool name="RTGUI_USING_FONTHZ" description="Support Chinese font" default="true" />
|
||||
#define RTGUI_USING_FONTHZ
|
||||
// <bool name="RTGUI_USING_DFS_FILERW" description="Using DFS as file interface " default="true" />
|
||||
#define RTGUI_USING_DFS_FILERW
|
||||
// <bool name="RTGUI_USING_HZ_FILE" description="Using font file as Chinese font" default="false" />
|
||||
// #define RTGUI_USING_HZ_FILE
|
||||
// <bool name="RTGUI_USING_HZ_BMP" description="Using Chinese bitmap font" default="true" />
|
||||
#define RTGUI_USING_HZ_BMP
|
||||
// <bool name="RTGUI_USING_SMALL_SIZE" description="Using small size in RTGUI" default="false" />
|
||||
#define RTGUI_USING_SMALL_SIZE
|
||||
// <bool name="RTGUI_USING_MOUSE_CURSOR" description="Using mouse cursor in RTGUI" default="false" />
|
||||
// #define RTGUI_USING_MOUSE_CURSOR
|
||||
// <bool name="RTGUI_IMAGE_XPM" description="Using xpm image in RTGUI" default="true" />
|
||||
#define RTGUI_IMAGE_XPM
|
||||
// <bool name="RTGUI_IMAGE_JPEG" description="Using jpeg image in RTGUI" default="true" />
|
||||
// #define RTGUI_IMAGE_JPEG
|
||||
// <bool name="RTGUI_IMAGE_PNG" description="Using png image in RTGUI" default="true" />
|
||||
// #define RTGUI_IMAGE_PNG
|
||||
// <bool name="RTGUI_IMAGE_BMP" description="Using bmp image in RTGUI" default="true" />
|
||||
#define RTGUI_IMAGE_BMP
|
||||
// </section>
|
||||
/* Using USB */
|
||||
|
||||
// </RDTConfigurator>
|
||||
|
||||
/* POSIX layer and C standard library */
|
||||
|
||||
#define RT_USING_LIBC
|
||||
#define RT_USING_POSIX
|
||||
|
||||
/* Network */
|
||||
|
||||
/* Socket abstraction layer */
|
||||
|
||||
|
||||
/* Network interface device */
|
||||
|
||||
|
||||
/* light weight TCP/IP stack */
|
||||
|
||||
|
||||
/* AT commands */
|
||||
|
||||
|
||||
/* VBUS(Virtual Software BUS) */
|
||||
|
||||
|
||||
/* Utilities */
|
||||
|
||||
|
||||
/* RT-Thread MIPS CPU */
|
||||
|
||||
|
||||
/* RT-Thread online packages */
|
||||
|
||||
/* IoT - internet of things */
|
||||
|
||||
|
||||
/* Wi-Fi */
|
||||
|
||||
/* Marvell WiFi */
|
||||
|
||||
|
||||
/* Wiced WiFi */
|
||||
|
||||
|
||||
/* IoT Cloud */
|
||||
|
||||
|
||||
/* security packages */
|
||||
|
||||
|
||||
/* language packages */
|
||||
|
||||
|
||||
/* multimedia packages */
|
||||
|
||||
|
||||
/* tools packages */
|
||||
|
||||
|
||||
/* system packages */
|
||||
|
||||
|
||||
/* peripheral libraries and drivers */
|
||||
|
||||
|
||||
/* miscellaneous packages */
|
||||
|
||||
|
||||
/* samples: kernel and components samples */
|
||||
|
||||
#define SOC_LS1B
|
||||
#define RT_USING_UART0
|
||||
#define RT_UART_RX_BUFFER_SIZE 64
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@ import os
|
|||
|
||||
# CPU options
|
||||
ARCH='mips'
|
||||
CPU ='loongson_1b'
|
||||
CPU ='gs232'
|
||||
|
||||
# toolchains options
|
||||
CROSS_TOOL = 'gcc'
|
||||
|
|
@ -12,7 +12,8 @@ if os.getenv('RTT_CC'):
|
|||
|
||||
if CROSS_TOOL == 'gcc':
|
||||
PLATFORM = 'gcc'
|
||||
EXEC_PATH = r'C:\Program Files\CodeSourcery\Sourcery G++ Lite For MIPS ELF\bin'
|
||||
EXEC_PATH = "/opt/mips-2016.05/bin"
|
||||
# EXEC_PATH = r'D:\mgc\embedded\codebench\bin'
|
||||
else:
|
||||
print('================ERROR============================')
|
||||
print('Not support %s yet!' % CROSS_TOOL)
|
||||
|
|
@ -37,7 +38,7 @@ READELF = PREFIX + 'readelf'
|
|||
|
||||
DEVICE = ' -mips32'
|
||||
CFLAGS = DEVICE + ' -EL -G0 -mno-abicalls -fno-pic -fno-builtin -fno-exceptions -ffunction-sections -fomit-frame-pointer'
|
||||
AFLAGS = ' -c' + DEVICE + ' -EL -fno-pic -fno-builtin -mno-abicalls -x assembler-with-cpp -DSYSTEM_STACK=0x80003fe8'
|
||||
AFLAGS = ' -c' + DEVICE + ' -EL -fno-pic -fno-builtin -mno-abicalls -x assembler-with-cpp'
|
||||
LFLAGS = DEVICE + ' -nostartfiles -EL -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T ls1b_ram.lds'
|
||||
|
||||
CPATH = ''
|
||||
|
|
|
|||
|
|
@ -16,6 +16,7 @@ config PKGS_DIR
|
|||
default "packages"
|
||||
|
||||
source "$RTT_DIR/Kconfig"
|
||||
source "$RTT_DIR/libcpu/mips/common/Kconfig"
|
||||
source "$PKGS_DIR/Kconfig"
|
||||
|
||||
config SOC_1C300
|
||||
|
|
@ -24,10 +25,24 @@ config SOC_1C300
|
|||
select RT_USING_USER_MAIN
|
||||
default y
|
||||
|
||||
choice
|
||||
prompt "Board Type"
|
||||
config RT_LS1C_OPENLOONGSON
|
||||
bool "OpenLoongson Board"
|
||||
config RT_LS1C_BAICAIBOARD
|
||||
bool "Baicai Board"
|
||||
endchoice
|
||||
|
||||
config RT_USING_SELF_BOOT
|
||||
bool "Enable RT-Thread run without bootloader"
|
||||
default n
|
||||
|
||||
if RT_USING_SELF_BOOT
|
||||
config RT_SELF_BOOT_DEBUG
|
||||
bool "Debug self boot code"
|
||||
default n
|
||||
endif
|
||||
|
||||
if RT_USING_SERIAL
|
||||
config RT_USING_UART2
|
||||
bool "Using RT_USING_UART2"
|
||||
|
|
@ -49,10 +64,6 @@ config RT_USING_GMAC_INT_MODE
|
|||
bool "Using RT_USING_GMAC_INT_MODE"
|
||||
default y
|
||||
|
||||
config RT_USING_FPU
|
||||
bool "Using RT_USING_FPU"
|
||||
default y
|
||||
|
||||
config RT_USING_SPI0
|
||||
bool "Enable SPI0"
|
||||
select RT_USING_SPI
|
||||
|
|
@ -113,4 +124,3 @@ config RT_RTC_NAME
|
|||
default "RTC"
|
||||
endif
|
||||
|
||||
|
||||
|
|
@ -29,7 +29,7 @@ Export('rtconfig')
|
|||
objs = PrepareBuilding(env, RTT_ROOT)
|
||||
|
||||
if GetDepend('RT_USING_SELF_BOOT'):
|
||||
rtconfig.LFLAGS += " -Ttext 0x80010000"
|
||||
rtconfig.LFLAGS += " -Ttext 0x80000000"
|
||||
else:
|
||||
rtconfig.LFLAGS += " -Ttext 0x80200000"
|
||||
env.Replace(LINKFLAGS = rtconfig.LFLAGS)
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src = Glob('*.c')
|
||||
src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
|
||||
|
||||
CPPPATH = [cwd]
|
||||
|
||||
|
|
|
|||
|
|
@ -8,74 +8,20 @@
|
|||
* 2010-06-25 Bernard first version
|
||||
* 2011-08-08 lgnq modified for Loongson LS1B
|
||||
* 2015-07-06 chinesebear modified for Loongson LS1C
|
||||
* 2019-12-04 Jiaxun Yang Adapt new generic MIPS code
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rthw.h>
|
||||
#include <mips.h>
|
||||
|
||||
#include "board.h"
|
||||
#include "drv_uart.h"
|
||||
#include "ls1c.h"
|
||||
|
||||
#define A_K0BASE 0x80000000
|
||||
|
||||
extern unsigned char __bss_end;
|
||||
|
||||
|
||||
extern void tlb_refill_exception(void);
|
||||
extern void general_exception(void);
|
||||
extern void irq_exception(void);
|
||||
extern void rt_hw_cache_init(void);
|
||||
extern void invalidate_writeback_dcache_all(void);
|
||||
extern void invalidate_icache_all(void);
|
||||
|
||||
/**
|
||||
* This is the timer interrupt service routine.
|
||||
*/
|
||||
void rt_hw_timer_handler(void)
|
||||
{
|
||||
unsigned int count;
|
||||
|
||||
count = read_c0_compare();
|
||||
write_c0_compare(count);
|
||||
write_c0_count(0);
|
||||
|
||||
/* increase a OS tick */
|
||||
rt_tick_increase();
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will initial OS timer
|
||||
*/
|
||||
void rt_hw_timer_init(void)
|
||||
{
|
||||
write_c0_compare(CPU_HZ/2/RT_TICK_PER_SECOND);
|
||||
write_c0_count(0);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* init hardware FPU
|
||||
*/
|
||||
void rt_hw_fpu_init(void)
|
||||
{
|
||||
rt_uint32_t c0_status = 0;
|
||||
rt_uint32_t c1_status = 0;
|
||||
|
||||
// 使能协处理器1--FPU
|
||||
c0_status = read_c0_status();
|
||||
c0_status |= (ST0_CU1 | ST0_FR);
|
||||
write_c0_status(c0_status);
|
||||
|
||||
// 配置FPU
|
||||
c1_status = read_c1_status();
|
||||
c1_status |= (FPU_CSR_FS | FPU_CSR_FO | FPU_CSR_FN); // set FS, FO, FN
|
||||
c1_status &= ~(FPU_CSR_ALL_E); // disable exception
|
||||
c1_status = (c1_status & (~FPU_CSR_RM)) | FPU_CSR_RN; // set RN
|
||||
write_c1_status(c1_status);
|
||||
|
||||
return ;
|
||||
}
|
||||
#define RT_HW_HEAP_END (0x80000000 + MEM_SIZE)
|
||||
|
||||
|
||||
/**
|
||||
|
|
@ -83,23 +29,12 @@ void rt_hw_fpu_init(void)
|
|||
*/
|
||||
void rt_hw_board_init(void)
|
||||
{
|
||||
/* init cache */
|
||||
rt_hw_cache_init();
|
||||
/* init hardware interrupt */
|
||||
rt_hw_exception_init();
|
||||
|
||||
/* init hardware interrupt */
|
||||
rt_hw_interrupt_init();
|
||||
|
||||
/* clear bev */
|
||||
write_c0_status(read_c0_status()&(~(1<<22)));
|
||||
|
||||
/* copy vector */
|
||||
rt_memcpy((void *)A_K0BASE, tlb_refill_exception, 0x80);
|
||||
rt_memcpy((void *)(A_K0BASE + 0x180), general_exception, 0x80);
|
||||
rt_memcpy((void *)(A_K0BASE + 0x200), irq_exception, 0x80);
|
||||
|
||||
invalidate_writeback_dcache_all();
|
||||
invalidate_icache_all();
|
||||
|
||||
#ifdef RT_USING_HEAP
|
||||
rt_system_heap_init((void*)&__bss_end, (void*)RT_HW_HEAP_END);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -8,15 +8,55 @@
|
|||
* 2010-06-25 Bernard first version
|
||||
* 2011-08-08 lgnq modified for Loongson LS1B
|
||||
* 2015-07-06 chinesebear modified for Loongson LS1C
|
||||
* 2019-12-04 Jiaxun Yang Add board config defines
|
||||
*/
|
||||
|
||||
#ifndef __BOARD_H__
|
||||
#define __BOARD_H__
|
||||
#include <rtconfig.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
void rt_hw_board_init(void);
|
||||
#endif
|
||||
|
||||
/* 32M SDRAM */
|
||||
#define RT_HW_HEAP_END (0x80000000 + 32 * 1024 * 1024)
|
||||
/*
|
||||
* SDRAM config
|
||||
*
|
||||
* Take IS42S16400 SDRAM chip as a example
|
||||
* The specfication is
|
||||
* Size 8MB
|
||||
* WIDTH: 16 bits
|
||||
* COL WIDTH: 8 bits, so we should take the 8 power of 2, it's 256
|
||||
* ROW WIDTH: 12 bits, so we take the 12 power of 2, it's 4K
|
||||
*
|
||||
* Please reference macro SD_PARA0 and SDRAM registers intruduction
|
||||
* in user's manual to edit the SDRAM config.
|
||||
*/
|
||||
|
||||
#if defined(RT_LS1C_BAICAIBOARD)
|
||||
/* 8MByte IS42S16400 appeared in bacai_board V1.x V2.x */
|
||||
#define MEM_SIZE (0x800000)
|
||||
#define SDRAM_WIDTH (WIDTH_16)
|
||||
#define SDRAM_COL (COL_256)
|
||||
#define SDRAM_ROW (ROW_4K)
|
||||
#elif defined(RT_LS1C_OPENLOONGSON)
|
||||
/* 32MByte appeared in SmartLoong board */
|
||||
#define MEM_SIZE (0x2000000)
|
||||
#define SDRAM_WIDTH (WIDTH_16)
|
||||
#define SDRAM_COL (COL_512)
|
||||
#define SDRAM_ROW (ROW_8K)
|
||||
#else
|
||||
#error Unknown Board
|
||||
#endif
|
||||
|
||||
/* Early Debug config */
|
||||
#define EARLY_DEBUG /* UART2 serial print debug in early stage */
|
||||
#define EARLY_DEBUG_BAUD (115200)
|
||||
|
||||
/* Clock config */
|
||||
#define CPU_HZ (252 * 1000000)
|
||||
#define PLL_MULT (0x54) /* When external clock is 24Mhz PLL=504Mhz */
|
||||
#define SDRAM_DIV (0) /* SDRAM is CPU divided by 2*/
|
||||
#define CPU_DIV (2) /* CPU clock is PLL divided by 2 */
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@
|
|||
#define __DRV_UART_H__
|
||||
|
||||
#include "ls1c.h"
|
||||
#include <rthw.h>
|
||||
|
||||
#define DEV_CLK 252000000 // 252MHz
|
||||
#define UART_BAUDRATE 115200
|
||||
|
|
@ -31,43 +32,43 @@
|
|||
#define UART11_BASE 0xBFE4Cb00
|
||||
|
||||
/* UART registers */
|
||||
#define UART_DAT(base) __REG8(base + 0x00)
|
||||
#define UART_IER(base) __REG8(base + 0x01)
|
||||
#define UART_IIR(base) __REG8(base + 0x02)
|
||||
#define UART_FCR(base) __REG8(base + 0x02)
|
||||
#define UART_LCR(base) __REG8(base + 0x03)
|
||||
#define UART_MCR(base) __REG8(base + 0x04)
|
||||
#define UART_LSR(base) __REG8(base + 0x05)
|
||||
#define UART_MSR(base) __REG8(base + 0x06)
|
||||
#define UART_DAT(base) HWREG8(base + 0x00)
|
||||
#define UART_IER(base) HWREG8(base + 0x01)
|
||||
#define UART_IIR(base) HWREG8(base + 0x02)
|
||||
#define UART_FCR(base) HWREG8(base + 0x02)
|
||||
#define UART_LCR(base) HWREG8(base + 0x03)
|
||||
#define UART_MCR(base) HWREG8(base + 0x04)
|
||||
#define UART_LSR(base) HWREG8(base + 0x05)
|
||||
#define UART_MSR(base) HWREG8(base + 0x06)
|
||||
|
||||
#define UART_LSB(base) __REG8(base + 0x00)
|
||||
#define UART_MSB(base) __REG8(base + 0x01)
|
||||
#define UART_LSB(base) HWREG8(base + 0x00)
|
||||
#define UART_MSB(base) HWREG8(base + 0x01)
|
||||
|
||||
/* UART0 registers */
|
||||
#define UART0_DAT __REG8(UART0_BASE + 0x00)
|
||||
#define UART0_IER __REG8(UART0_BASE + 0x01)
|
||||
#define UART0_IIR __REG8(UART0_BASE + 0x02)
|
||||
#define UART0_FCR __REG8(UART0_BASE + 0x02)
|
||||
#define UART0_LCR __REG8(UART0_BASE + 0x03)
|
||||
#define UART0_MCR __REG8(UART0_BASE + 0x04)
|
||||
#define UART0_LSR __REG8(UART0_BASE + 0x05)
|
||||
#define UART0_MSR __REG8(UART0_BASE + 0x06)
|
||||
#define UART0_DAT HWREG8(UART0_BASE + 0x00)
|
||||
#define UART0_IER HWREG8(UART0_BASE + 0x01)
|
||||
#define UART0_IIR HWREG8(UART0_BASE + 0x02)
|
||||
#define UART0_FCR HWREG8(UART0_BASE + 0x02)
|
||||
#define UART0_LCR HWREG8(UART0_BASE + 0x03)
|
||||
#define UART0_MCR HWREG8(UART0_BASE + 0x04)
|
||||
#define UART0_LSR HWREG8(UART0_BASE + 0x05)
|
||||
#define UART0_MSR HWREG8(UART0_BASE + 0x06)
|
||||
|
||||
#define UART0_LSB __REG8(UART0_BASE + 0x00)
|
||||
#define UART0_MSB __REG8(UART0_BASE + 0x01)
|
||||
#define UART0_LSB HWREG8(UART0_BASE + 0x00)
|
||||
#define UART0_MSB HWREG8(UART0_BASE + 0x01)
|
||||
|
||||
/* UART1 registers */
|
||||
#define UART1_DAT __REG8(UART1_BASE + 0x00)
|
||||
#define UART1_IER __REG8(UART1_BASE + 0x01)
|
||||
#define UART1_IIR __REG8(UART1_BASE + 0x02)
|
||||
#define UART1_FCR __REG8(UART1_BASE + 0x02)
|
||||
#define UART1_LCR __REG8(UART1_BASE + 0x03)
|
||||
#define UART1_MCR __REG8(UART1_BASE + 0x04)
|
||||
#define UART1_LSR __REG8(UART1_BASE + 0x05)
|
||||
#define UART1_MSR __REG8(UART1_BASE + 0x06)
|
||||
#define UART1_DAT HWREG8(UART1_BASE + 0x00)
|
||||
#define UART1_IER HWREG8(UART1_BASE + 0x01)
|
||||
#define UART1_IIR HWREG8(UART1_BASE + 0x02)
|
||||
#define UART1_FCR HWREG8(UART1_BASE + 0x02)
|
||||
#define UART1_LCR HWREG8(UART1_BASE + 0x03)
|
||||
#define UART1_MCR HWREG8(UART1_BASE + 0x04)
|
||||
#define UART1_LSR HWREG8(UART1_BASE + 0x05)
|
||||
#define UART1_MSR HWREG8(UART1_BASE + 0x06)
|
||||
|
||||
#define UART1_LSB __REG8(UART1_BASE + 0x00)
|
||||
#define UART1_MSB __REG8(UART1_BASE + 0x01)
|
||||
#define UART1_LSB HWREG8(UART1_BASE + 0x00)
|
||||
#define UART1_MSB HWREG8(UART1_BASE + 0x01)
|
||||
|
||||
/* UART interrupt enable register value */
|
||||
#define UARTIER_IME (1 << 3)
|
||||
|
|
|
|||
|
|
@ -39,14 +39,6 @@
|
|||
typedef int bool;
|
||||
//typedef unsigned long dma_addr_t;
|
||||
|
||||
//sw
|
||||
/* write/read MMIO register */
|
||||
#define writeb(val, addr) (*(volatile u8*)(addr) = (val))
|
||||
#define writew(val, addr) (*(volatile u16*)(addr) = (val))
|
||||
#define writel(val, addr) (*(volatile u32*)(addr) = (val))
|
||||
#define readb(addr) (*(volatile u8*)(addr))
|
||||
#define readw(addr) (*(volatile u16*)(addr))
|
||||
#define readl(addr) (*(volatile u32*)(addr))
|
||||
|
||||
|
||||
#define KUSEG_ADDR 0x0
|
||||
|
|
|
|||
|
|
@ -0,0 +1,168 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2019, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-12-04 Jiaxun Yang Initial version
|
||||
*/
|
||||
|
||||
#ifndef __RT_LS1C_SELFBOOT_H
|
||||
#define __RT_LS1C_SELFBOOT_H
|
||||
|
||||
/* SDRAM PARAM macro */
|
||||
#define SD_FREQ (((APB_CLK / 4) * (PLL_MULT / CPU_DIV)) / SDRAM_PARAM_DIV_NUM)
|
||||
|
||||
|
||||
/* SDRAM ROW */
|
||||
#define ROW_1K 0x7
|
||||
#define ROW_2K 0x0
|
||||
#define ROW_4K 0x1
|
||||
#define ROW_8K 0x2
|
||||
#define ROW_16K 0x3
|
||||
/* SDRAM COL */
|
||||
#define COL_256 0x7
|
||||
#define COL_512 0x0
|
||||
#define COL_1K 0x1
|
||||
#define COL_2K 0x2
|
||||
#define COL_4K 0x3
|
||||
/* SDRAM WIDTH */
|
||||
#define WIDTH_8 0x0
|
||||
#define WIDTH_16 0x1
|
||||
#define WIDTH_32 0x2
|
||||
|
||||
#define TRCD 3
|
||||
#define TCL 3
|
||||
#define TRP 3
|
||||
#define TRFC 8
|
||||
#define TRAS 6
|
||||
#define TREF 0x818
|
||||
#define TWR 2
|
||||
|
||||
#define DEF_SEL 0x1
|
||||
#define DEF_SEL_N 0x0
|
||||
#define HANG_UP 0x1
|
||||
#define HANG_UP_N 0x0
|
||||
#define CFG_VALID 0x1
|
||||
|
||||
#include "board.h"
|
||||
|
||||
#define SD_PARA0 (0x7f<<25 | \
|
||||
(TRAS << 21) | \
|
||||
(TRFC << 17) | (TRP << 14) | (TCL << 11) | \
|
||||
(TRCD << 8) | (SDRAM_WIDTH << 6) | (SDRAM_COL << 3) | \
|
||||
SDRAM_ROW)
|
||||
|
||||
#define SD_PARA1 ((HANG_UP_N << 8) | (DEF_SEL_N << 7) | (TWR << 5) | (TREF >> 7))
|
||||
|
||||
#define SD_PARA1_EN ((CFG_VALID << 9) | (HANG_UP_N << 8) | \
|
||||
(DEF_SEL_N << 7) | (TWR << 5) | (TREF >> 7))
|
||||
|
||||
#define LS1C_CBUS_FIRST1 0xBFE011C4
|
||||
#define LS1C_UART2_BASE 0xBFE48000
|
||||
|
||||
/* UART register offset*/
|
||||
#define LS1C_UART_DAT_OFFSET (0)
|
||||
#define LS1C_UART_IER_OFFSET (1)
|
||||
#define LS1C_UART_IIR_OFFSET (2)
|
||||
#define LS1C_UART_FCR_OFFSET (2)
|
||||
#define LS1C_UART_LCR_OFFSET (3)
|
||||
#define LS1C_UART_MCR_OFFSET (4)
|
||||
#define LS1C_UART_LSR_OFFSET (5)
|
||||
#define LS1C_UART_MSR_OFFSET (6)
|
||||
|
||||
#define LS1C_UART_LSB_OFFSET (0)
|
||||
#define LS1C_UART_MSB_OFFSET (1)
|
||||
|
||||
/* interrupt enable register */
|
||||
#define IER_IRxE 0x1
|
||||
#define IER_ITxE 0x2
|
||||
#define IER_ILE 0x4
|
||||
#define IER_IME 0x8
|
||||
|
||||
/* interrupt identification register */
|
||||
#define IIR_IMASK 0xf /* mask */
|
||||
#define IIR_RXTOUT 0xc /* receive timeout */
|
||||
#define IIR_RLS 0x6 /* receive line status */
|
||||
#define IIR_RXRDY 0x4 /* receive ready */
|
||||
#define IIR_TXRDY 0x2 /* transmit ready */
|
||||
#define IIR_NOPEND 0x1 /* nothing */
|
||||
#define IIR_MLSC 0x0 /* modem status */
|
||||
#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */
|
||||
|
||||
/* fifo control register */
|
||||
#define FIFO_ENABLE 0x01 /* enable fifo */
|
||||
#define FIFO_RCV_RST 0x02 /* reset receive fifo */
|
||||
#define FIFO_XMT_RST 0x04 /* reset transmit fifo */
|
||||
#define FIFO_DMA_MODE 0x08 /* enable dma mode */
|
||||
#define FIFO_TRIGGER_1 0x00 /* trigger at 1 char */
|
||||
#define FIFO_TRIGGER_4 0x40 /* trigger at 4 chars */
|
||||
#define FIFO_TRIGGER_8 0x80 /* trigger at 8 chars */
|
||||
#define FIFO_TRIGGER_14 0xc0 /* trigger at 14 chars */
|
||||
|
||||
/* character format control register */
|
||||
#define CFCR_DLAB 0x80 /* divisor latch */
|
||||
#define CFCR_SBREAK 0x40 /* send break */
|
||||
#define CFCR_PZERO 0x30 /* zero parity */
|
||||
#define CFCR_PONE 0x20 /* one parity */
|
||||
#define CFCR_PEVEN 0x10 /* even parity */
|
||||
#define CFCR_PODD 0x00 /* odd parity */
|
||||
#define CFCR_PENAB 0x08 /* parity enable */
|
||||
#define CFCR_STOPB 0x04 /* 2 stop bits */
|
||||
#define CFCR_8BITS 0x03 /* 8 data bits */
|
||||
#define CFCR_7BITS 0x02 /* 7 data bits */
|
||||
#define CFCR_6BITS 0x01 /* 6 data bits */
|
||||
#define CFCR_5BITS 0x00 /* 5 data bits */
|
||||
|
||||
/* modem control register */
|
||||
#define MCR_LOOPBACK 0x10 /* loopback */
|
||||
#define MCR_IENABLE 0x08 /* output 2 = int enable */
|
||||
#define MCR_DRS 0x04 /* output 1 = xxx */
|
||||
#define MCR_RTS 0x02 /* enable RTS */
|
||||
#define MCR_DTR 0x01 /* enable DTR */
|
||||
|
||||
/* line status register */
|
||||
#define LSR_RCV_FIFO 0x80 /* error in receive fifo */
|
||||
#define LSR_TSRE 0x40 /* transmitter empty */
|
||||
#define LSR_TXRDY 0x20 /* transmitter ready */
|
||||
#define LSR_BI 0x10 /* break detected */
|
||||
#define LSR_FE 0x08 /* framing error */
|
||||
#define LSR_PE 0x04 /* parity error */
|
||||
#define LSR_OE 0x02 /* overrun error */
|
||||
#define LSR_RXRDY 0x01 /* receiver ready */
|
||||
#define LSR_RCV_MASK 0x1f
|
||||
|
||||
|
||||
/* External clock frequency */
|
||||
#define AHB_CLK (24000000)
|
||||
#define APB_CLK (AHB_CLK)
|
||||
|
||||
|
||||
/* START_FREQ register bits */
|
||||
#define M_PLL_SHIFT (8)
|
||||
#define M_PLL (0xff << M_PLL_SHIFT)
|
||||
#define FRAC_N_SHIFT (16)
|
||||
#define FRAC_N (0xff << FRAC_N_SHIFT)
|
||||
#define DIV_SDRAM_SHIFT (0)
|
||||
#define DIV_SDRAM (0x3 << DIV_SDRAM_SHIFT)
|
||||
|
||||
/* CLK_DIV_PARAM register bits */
|
||||
#define DIV_PIX_EN (0x1 << 31)
|
||||
#define DIV_PIX (0x7f << 24)
|
||||
#define DIV_CAM_EN (0x1 << 23)
|
||||
#define DIV_CAM (0x7f << 16)
|
||||
#define DIV_CPU_EN (0x1 << 15)
|
||||
#define DIV_CPU (0x7f << 8)
|
||||
#define DIV_PIX_VALID (0x1 << 5)
|
||||
#define DIV_PIX_SEL (0x1 << 4)
|
||||
#define DIV_CAM_VALID (0x1 << 3)
|
||||
#define DIV_CAM_SEL (0x1 << 2)
|
||||
#define DIV_CPU_VALID (0x1 << 1)
|
||||
#define DIV_CPU_SEL (0x1 << 0)
|
||||
|
||||
#define DIV_PIX_SHIFT (24)
|
||||
#define DIV_CAM_SHIFT (16)
|
||||
#define DIV_CPU_SHIFT (8)
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,549 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2019, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Origin Authors: Loongson Technology Corporation Limited,
|
||||
* caogos <1207280597@qq.com>, Jiaxun Yang <jiaxun.yang@flygoat.com>,
|
||||
*
|
||||
* Also thanks to Liu Shiwei <liushiwei@gmail.com> and other Loongson
|
||||
* Community developers.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-12-04 Jiaxun Yang Initial version
|
||||
*/
|
||||
|
||||
#include <rtconfig.h>
|
||||
|
||||
#ifdef RT_USING_SELF_BOOT
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#define __ASSEMBLY__
|
||||
#endif
|
||||
|
||||
#include <mips.h>
|
||||
#include "selfboot.h"
|
||||
#include "ls1c.h"
|
||||
#include "cache.h"
|
||||
|
||||
/*
|
||||
* Register usage:
|
||||
*
|
||||
* s0 link versus load offset, used to relocate absolute adresses.
|
||||
* s1 free
|
||||
* s2 memory size
|
||||
* s3 free
|
||||
* s4 free
|
||||
* s5 dbg
|
||||
* s6 sdCfg
|
||||
* s7 rasave
|
||||
* s8 free
|
||||
*/
|
||||
|
||||
#define tmpsize s1
|
||||
#define msize s2
|
||||
#define bonito s4
|
||||
#define dbg s5
|
||||
#define sdCfg s6
|
||||
|
||||
|
||||
/* Macros */
|
||||
#ifdef RT_SELF_BOOT_DEBUG
|
||||
#define PRINTSTR(str) \
|
||||
.pushsection .selfboot_data; .align 4; 98: .asciz str; .popsection; la a0, 98b; bal stringserial; nop
|
||||
#else
|
||||
#define PRINTSTR(x)
|
||||
#endif
|
||||
|
||||
#define DELAY(count) \
|
||||
li v0, count; \
|
||||
99: \
|
||||
bnez v0, 99b;\
|
||||
addiu v0, -1
|
||||
|
||||
.section ".selfboot", "ax"
|
||||
.set noreorder
|
||||
.set mips32
|
||||
.globl _start
|
||||
.extern start
|
||||
_start:
|
||||
|
||||
/* NMI/Reset vector starts here*/
|
||||
mtc0 zero, CP0_STATUS /* set cp0 status register to zero */
|
||||
mtc0 zero, CP0_CAUSE /* set cp0 cause register to zero */
|
||||
|
||||
li t0, ST0_BEV /* set exception vector to in flash location */
|
||||
mtc0 t0, CP0_STATUS
|
||||
|
||||
/* Speed up SPI reading */
|
||||
li t0, 0xbfe80000 /* load SPI0 controler base address to t0 */
|
||||
li t1, 0x17 /* load "div 4, fast_read + burst_en + memory_en double I/O" to
|
||||
* to t0 for write, not all the flash chips support this mode */
|
||||
sb t1, 0x4(t0) /* set sfc_param register */
|
||||
li t1, 0x05
|
||||
sb t1, 0x6(t0) /* set sfc_timing register */
|
||||
|
||||
bal locate /* branch out of vector and get current address to ra */
|
||||
nop
|
||||
|
||||
/* in-flash exception vectors start here */
|
||||
/* save the exception types to a0 and print out PANIC message in exc_common */
|
||||
#define EXC_TLB_REFILL 0x0
|
||||
#define EXC_CACHE_ERR 0x1
|
||||
#define EXC_GEN 0x2
|
||||
#define EXC_INT 0x3
|
||||
|
||||
.org 0x200 /* 0xbfc00200 TLB_REFILL exception */
|
||||
li a0, EXC_TLB_REFILL
|
||||
b exc_common
|
||||
nop
|
||||
|
||||
.org 0x300 /* 0xbfc00300 Cache Error exception */
|
||||
li a0, EXC_CACHE_ERR
|
||||
b exc_common
|
||||
nop
|
||||
|
||||
.org 0x380 /* 0xbfc00300 General exception */
|
||||
li a0,EXC_GEN
|
||||
b exc_common
|
||||
nop
|
||||
|
||||
.org 0x400 /* 0xbfc00400 Interrupt exception */
|
||||
li a0, EXC_INT
|
||||
b exc_common
|
||||
nop
|
||||
|
||||
1: /* impossible to reach here, so make a dead loop */
|
||||
b 1b
|
||||
nop
|
||||
|
||||
exc_common: /* try one cause and pass to next */
|
||||
li s1, EXC_TLB_REFILL
|
||||
bne a0, s1, 1f
|
||||
nop
|
||||
PRINTSTR("\r\nEARLY_PANIC: Exception TLB Refill")
|
||||
b print_cause
|
||||
nop
|
||||
1:
|
||||
li s1, EXC_CACHE_ERR
|
||||
bne a0, s1, 1f
|
||||
nop
|
||||
PRINTSTR("\r\nEARLY_PANIC: CACHE Error: ")
|
||||
mfc0 a0, CP0_CACHEERR
|
||||
bal hexserial
|
||||
nop
|
||||
b print_cause
|
||||
nop
|
||||
1:
|
||||
li s1, EXC_GEN
|
||||
bne a0, s1, 1f
|
||||
nop
|
||||
PRINTSTR("\r\nEARLY_PANIC: General Exception")
|
||||
b print_cause
|
||||
nop
|
||||
1:
|
||||
li s1, EXC_INT
|
||||
bne a0, s1, print_cause /* if all exceptions in a0 not reached,
|
||||
* print_cause directly*/
|
||||
nop
|
||||
PRINTSTR("\r\nEARLY_PANIC: Interrupt Exception")
|
||||
print_cause:
|
||||
PRINTSTR("\r\nCAUSE=")
|
||||
mfc0 a0, CP0_CAUSE
|
||||
bal hexserial
|
||||
nop
|
||||
|
||||
PRINTSTR("\r\nSTATUS=")
|
||||
mfc0 a0, CP0_STATUS
|
||||
bal hexserial
|
||||
nop
|
||||
|
||||
PRINTSTR("\r\nERRORPC=")
|
||||
mfc0 a0, CP0_ERROREPC
|
||||
bal hexserial
|
||||
nop
|
||||
|
||||
PRINTSTR("\r\nEPC=")
|
||||
mfc0 a0, CP0_EPC
|
||||
bal hexserial
|
||||
nop
|
||||
|
||||
PRINTSTR("\r\nBADADDR=")
|
||||
mfc0 a0, CP0_BADVADDR
|
||||
bal hexserial
|
||||
nop
|
||||
|
||||
PRINTSTR("\r\nEARLY: LOOP! Noting to do")
|
||||
1: /* Make a dead loop here, wait user to reset the MCU */
|
||||
b 1b
|
||||
nop
|
||||
|
||||
/* locate here, continue the start progress */
|
||||
|
||||
locate:
|
||||
/* fix the absolute address by ra */
|
||||
la s0, start /* s0 = start */
|
||||
subu s0, ra, s0 /* s0 = ra - s0 */
|
||||
and s0, 0xffff0000 /* s0 = s0 & 0xffff0000 */
|
||||
|
||||
li t0, 0xbfe78030 /* load PLL/SDRAM freq config register base to t0 */
|
||||
li t2, (0x80000008 | (PLL_MULT << 8) | (0x3 << 2) | SDRAM_DIV) /* Set PLL
|
||||
* MULT and PLL DIV */
|
||||
li t3, (0x00008003 | (CPU_DIV << 8)) /* set CPU DEV */
|
||||
|
||||
li t1, 0x2
|
||||
sw t1, 0x4(t0) /* disable CPU_DIV_VALID firstly for adjustment */
|
||||
sw t2, 0x0(t0) /* write START_FREQ */
|
||||
sw t3, 0x4(t0) /* write CLK_DIV_PARAM */
|
||||
|
||||
/* start to initialize debug uart port */
|
||||
la v0, LS1C_UART2_BASE /* load UART2 base to v0, only UART2 can be debug port */
|
||||
1:
|
||||
li v1, FIFO_ENABLE|FIFO_RCV_RST|FIFO_XMT_RST|FIFO_TRIGGER_4 /* clear Rx,Tx FIFO
|
||||
* declear 4 bit int trigger */
|
||||
sb v1, LS1C_UART_FCR_OFFSET(v0) /* write FCR (FIFO control register) */
|
||||
li v1, CFCR_DLAB /* reach freq div register */
|
||||
sb v1, LS1C_UART_LCR_OFFSET(v0) /* write LCR (Line control register)*/
|
||||
/* Set UART2 reuse with GPIO36,37*/
|
||||
li a0, LS1C_CBUS_FIRST1 /* load CBUS_FIRST1 offset to a0 */
|
||||
lw a1, 0x10(a0) /* load value from CBUS_SECOND1 to a1 */
|
||||
ori a1, 0x30 /* a1 |= 0x30, GPIO36,37 as secondary function */
|
||||
sw a1, 0x10(a0) /* write back modified CBUS_SECOND1 from a1 */
|
||||
/* Caculate PLL and bit rate */
|
||||
li a0, 0xbfe78030 /* load START_FREQ register address to a0 */
|
||||
lw a1, 0(a0) /* load value from START_FREQ to a1*/
|
||||
srl a1, 8 /* a1 >>= 8 */
|
||||
andi a1, 0xff /* a1 &= 0xff, as a1=PLL_MULT */
|
||||
li a2, APB_CLK /* a2 = APB_CLK = 24Mhz (External Clock Freq) */
|
||||
srl a2, 2 /* a2 = a2 >> 2 = APB_CLK/4 */
|
||||
multu a1, a2 /* hilo = a1 * a2 = PLL_MULT * APB_CLK /4 */
|
||||
mflo v1 /* v1 = lo. put low 32 bit of a1 * a2 to v1 as PLL freq */
|
||||
/* Determine if we need to devide the clock */
|
||||
lw a1, 4(a0) /* load value frm CLK_DIV_PARAM to a1 */
|
||||
andi a2, a1, DIV_CPU_SEL /* a2 = a1 & DIV_CPU_SEL, if CPU_SEL=1, devide the clock,
|
||||
* if CPU_SEL=0, bypass the clock */
|
||||
bnez a2, 1f /* if (a2 != 0), branch to next tag 1 */
|
||||
nop
|
||||
li v1, APB_CLK /* v1 = APB_CLK */
|
||||
b 3f
|
||||
nop
|
||||
1: /* Determine if the CPU_DIV is valid*/
|
||||
andi a2, a1, DIV_CPU_EN /* a2 = a1 & DIV_CPU_EN */
|
||||
bnez a2, 2f /* if (a2 != 0), branch to next tag 2 */
|
||||
nop
|
||||
srl v1, 1 /* v1 >>= 1, so v1 = APB_CLK/4 * PLL_MULT/2 */
|
||||
b 3f
|
||||
nop
|
||||
2: /* caculate CPU freq */
|
||||
andi a1, DIV_CPU /* a1 &= DIV_CPU */
|
||||
srl a1, DIV_CPU_SHIFT /* a1 >>= DIV_CPU_SHIFT */
|
||||
divu v1, a1 /* lo = v1/a1, hi = v1 % a1 */
|
||||
mflo v1 /* v1 = lo, CPU Freq */
|
||||
3:
|
||||
li a1, (16 * EARLY_DEBUG_BAUD) /* a1 = 16 * BIT RATE */
|
||||
divu v1, v1, a1 /* v1 = v1 / a1 */
|
||||
srl v1, 1 /* v1 >>= 1 */
|
||||
sb v1, LS1C_UART_LSB_OFFSET(v0) /* write 8bit low into LSB */
|
||||
srl v1, 8 /* v1 >>= 8 */
|
||||
sb v1, LS1C_UART_MSB_OFFSET(v0) /* write 8bit low into MSB */
|
||||
|
||||
li v1, CFCR_8BITS /* 8n1, no check */
|
||||
sb v1, LS1C_UART_LCR_OFFSET(v0) /* write to LCR (Line Control Register) */
|
||||
|
||||
#ifdef EARLY_DEBUG_UART_FLOW_CTRL
|
||||
li v1, MCR_DTR|MCR_RTS /* valid DTR and RTS */
|
||||
sb v1, LS1C_UART_MCR_OFFSET(v0) /* write to MCR (MODEM Control Register) */
|
||||
#endif
|
||||
|
||||
li v1, 0x0 /* disable all the interruptions */
|
||||
sb v1, LS1C_UART_IER_OFFSET(v0) /* write to IER (Interruptions Enable Registers) */
|
||||
|
||||
PRINTSTR("\r\INFO: Loongson 1C300 Starting :) \r\n")
|
||||
|
||||
/* disable all GPIOs for conflict functions */
|
||||
li a0,0xbfd00000
|
||||
sw zero,0x10c0(a0) /* disable GPIO 0-31 */
|
||||
sw zero,0x10c4(a0) /* disable GPIO 32-63 */
|
||||
sw zero,0x10c8(a0) /* disable GPIO 64-95 */
|
||||
sw zero,0x10cc(a0)
|
||||
|
||||
li t0, 0xffffffff
|
||||
sw t0, 0x10d0(a0)
|
||||
sw t0, 0x10d4(a0)
|
||||
sw t0, 0x10d8(a0)
|
||||
sw t0, 0x10dc(a0)
|
||||
|
||||
sw t0, 0x10f0(a0)
|
||||
sw t0, 0x10f4(a0)
|
||||
sw t0, 0x10f8(a0)
|
||||
sw t0, 0x10fc(a0)
|
||||
|
||||
PRINTSTR("\r\INFO: All GPIOs are disabled\r\n")
|
||||
|
||||
/* SDRAM initialize starts here */
|
||||
|
||||
li msize, MEM_SIZE
|
||||
|
||||
#ifdef EJTAG_SEL_AS_SDRAM_CS1
|
||||
li a0, 0xbfd011c0
|
||||
lw a1, 0x40(a0)
|
||||
ori a1, 0x01
|
||||
sw a1, 0x40(a0)
|
||||
PRINTSTR("\r\INFO: EJTAG_SEL PIN as SDRAM_CS1\r\n")
|
||||
#endif
|
||||
|
||||
/*
|
||||
* recommanded by user manual, we should write SD_CONFIG[31:0] first, then
|
||||
* write SD_CONFIG[63:32]. Repeat writing for three times, valid the config in
|
||||
* the last time.
|
||||
*/
|
||||
|
||||
/* write first time */
|
||||
li t1, 0xbfd00410 /* load SD_CONFIG[31:0] address to t1 */
|
||||
li a1, SD_PARA0 /* get the memory config from macro SD_PARA0 */
|
||||
sw a1, 0x0(t1) /* write to SD_CONFIG[31:0] */
|
||||
li a1, SD_PARA1
|
||||
sw a1, 0x4(t1) /* write to SD_CONFIG[63:32] with offset */
|
||||
PRINTSTR("\r\INFO: SDRAM Config Pass1\r\n")
|
||||
|
||||
/* write second time,the same */
|
||||
li a1, SD_PARA0
|
||||
sw a1, 0x0(t1)
|
||||
li a1, SD_PARA1
|
||||
sw a1, 0x4(t1)
|
||||
PRINTSTR("\r\INFO: SDRAM Config Pass2\r\n")
|
||||
|
||||
/* write third time, enable controller this time */
|
||||
li a1, SD_PARA0
|
||||
sw a1, 0x0(t1)
|
||||
li a1, SD_PARA1_EN /* enable it */
|
||||
sw a1, 0x4(t1)
|
||||
PRINTSTR("\r\INFO: SDRAM initialize compeleted\r\n")
|
||||
|
||||
|
||||
/* initialize cache */
|
||||
bal cache_init /* branch to cache_init */
|
||||
nop
|
||||
|
||||
/* enable cache */
|
||||
mfc0 a0, CP0_CONFIG /* load cp0 config to a0 */
|
||||
and a0, a0, ~((1<<12) | 7) /* a0 = a0 & ~((1<<12) | 7) */
|
||||
or a0, a0, 2 /* a0 |= 2 */
|
||||
mtc0 a0, CP0_CONFIG /* write back to CP0 config */
|
||||
|
||||
/*
|
||||
* relocate: copy selfboot code to memory in kseg0, fix PC and jump to kseg0.
|
||||
* in order to speed up the copy progress, we will execute copy code in kseg0
|
||||
*/
|
||||
|
||||
PRINTSTR("\r\INFO: Relocating")
|
||||
la t0, text_copy_start /* load the adress of start tag to t0 */
|
||||
move t2, t0
|
||||
addu t0, s0 /* correct t0 address in rom by s0 */
|
||||
la t1, text_copy_end
|
||||
|
||||
selfboot_copy_loop:
|
||||
lw v0, (t0) /* copy from memory address in t0 to register v0 */
|
||||
sw v0, (t2) /* write data in register v0 to memory address t0 */
|
||||
addiu t0, 0x4 /* t0 moves forward 4 bytes */
|
||||
addiu t2, 0x4 /* t2 moves forward 4 bytes */
|
||||
ble t2, t1, selfboot_copy_loop /* if t1 <= t2 loop to continue the copy */
|
||||
nop
|
||||
|
||||
la t0, text_copy_start /* load start address to t0 */
|
||||
jr t0 /* jump to 122 in kseg0 to start copy code progress */
|
||||
nop
|
||||
|
||||
text_copy_start:
|
||||
/* Copy code to memory*/
|
||||
la a0, start /* load address of start symbol to a0 */
|
||||
addu a1, a0, s0 /* correct a0 to address in flash */
|
||||
la a2, _edata /* load symbol _edata address to a2 */
|
||||
subu t1, a2, a0 /* t1 = a2 - a0, the space of text area */
|
||||
|
||||
move t0, a0 /* the start address in ram */
|
||||
move t1, a1 /* the start address in rom */
|
||||
move t2, a2 /* the end address in rom (symbol _edata) */
|
||||
|
||||
/* copy text section */
|
||||
1:
|
||||
and t3, t0, 0x0000ffff /* t3 = t0 & 0x0000ffff, get low 16 bit */
|
||||
bnez t3, 2f /* if t3 != 0, jump to next tag 2 */
|
||||
nop
|
||||
2:
|
||||
lw t3, 0(t1) /* copy 4 bit from memory address t1 to register t3 */
|
||||
nop
|
||||
sw t3, 0(t0) /* copy 4 bit from register t3 to memory address in t0 */
|
||||
addu t0, 4 /* t0 move forward 4 bytes */
|
||||
addu t1, 4 /* t1 move forward 4 bytes */
|
||||
bne t2, t0, 1b /* if t2 != t0, branch to last tag 1 to continue copy */
|
||||
nop
|
||||
/* copy text section done. */
|
||||
|
||||
move a0, msize /* a0 = msize, will be passed to main */
|
||||
srl a0, 20 /* a0 >>= 20, convert to unit in MB */
|
||||
|
||||
/* execute main */
|
||||
la v0, _rtthread_entry /* load address of function main to v0 */
|
||||
jalr v0 /* call address in v0, congrats! all low_level things done!
|
||||
* switch brain out of assembly */
|
||||
nop
|
||||
text_copy_end: /* end of self-copy in memory */
|
||||
|
||||
loop: /* impossible to reach here, make a dead loop */
|
||||
b loop
|
||||
nop
|
||||
|
||||
/* functions here */
|
||||
|
||||
LEAF(stringserial) /* print out the string in address passed in a0 */
|
||||
nop
|
||||
move a2, ra /* save the return address to a2 */
|
||||
addu a1, a0, s0 /* correct the address in ROM */
|
||||
lbu a0, 0(a1) /* read the first byte in memory address a1 to a0 */
|
||||
1:
|
||||
beqz a0, 2f /* if a0 == 0, jump to next tag 2, empty char */
|
||||
nop
|
||||
bal tgt_putchar /* print a char */
|
||||
addiu a1, 1 /* a1 += 1 move forward to next byte */
|
||||
b 1b /* branch to the last tag 1, continue */
|
||||
lbu a0, 0(a1) /* load the next bit from address a1 to a0, in delay solt,
|
||||
* will be execuated before branch */
|
||||
2:
|
||||
j a2 /* return */
|
||||
nop
|
||||
END(stringserial)
|
||||
|
||||
|
||||
LEAF(hexserial) /* print out single hex char passed in register a0 */
|
||||
nop
|
||||
move a2, ra /* move return address from ra to a2 */
|
||||
move a1, a0 /* move hex char from register a0 to a1 */
|
||||
li a3, 7 /* load 7 to a3 */
|
||||
1:
|
||||
rol a0, a1, 4 /* rotate left ward shift for 4 bit in a1 to a0 */
|
||||
move a1, a0
|
||||
and a0, 0xf
|
||||
la v0, hexchar
|
||||
|
||||
.pushsection .selfboot_data
|
||||
.align 4
|
||||
hexchar:
|
||||
.ascii "0123456789abcdef"
|
||||
.popsection
|
||||
.align 4
|
||||
|
||||
addu v0, s0
|
||||
addu v0, a0
|
||||
bal tgt_putchar
|
||||
lbu a0, 0(v0)
|
||||
|
||||
bnez a3, 1b
|
||||
addu a3, -1
|
||||
|
||||
j a2
|
||||
nop
|
||||
END(hexserial)
|
||||
|
||||
LEAF(tgt_putchar) /* print out a char in a0 */
|
||||
la v0, LS1C_UART2_BASE /* load UART register address to a0 */
|
||||
lbu v1, LS1C_UART_LSR_OFFSET(v0) /* load value from LSR to v0 */
|
||||
1:
|
||||
and v1, LSR_TXRDY /* v1 &= LSR_TXRDY determine wether we can send by TFE bit */
|
||||
beqz v1, 1b /* if (v1 == 0) jump to last 1 tag, waiting until TFE is 1 */
|
||||
lbu v1, LS1C_UART_LSR_OFFSET(v0) /* load value from LSR to v0 again, in delay solt */
|
||||
|
||||
sb a0, LS1C_UART_DAT_OFFSET(v0) /* write a0 into DAT, send out */
|
||||
j ra /* */
|
||||
nop
|
||||
END(tgt_putchar)
|
||||
|
||||
LEAF(CPU_SetSR) /* modify SR value, arg 1 = set bits, arg 2 = clear bits. */
|
||||
mfc0 v0, CP0_STATUS
|
||||
not v1, a1
|
||||
and v1, v0
|
||||
or v1, a0
|
||||
mtc0 v1, CP0_STATUS
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
j ra
|
||||
nop
|
||||
END(CPU_SetSR)
|
||||
|
||||
cache_init:
|
||||
move t1, ra
|
||||
####part 2####
|
||||
cache_detect_4way:
|
||||
mfc0 t4, CP0_CONFIG,1 /* move CP0 CONFIG to t4 */
|
||||
lui v0, 0x7 /* v0 = 0x7 << 16 */
|
||||
and v0, t4, v0 /* v0 = t4 & v0 */
|
||||
srl t3, v0, 16 /* t3 = v0 >> 16 Icache组相联数 IA */
|
||||
|
||||
li t5, 0x800 //32*64
|
||||
srl v1, t4,22 //v1 = t4 >> 22
|
||||
andi v1, 7 //Icache每路的组数 64x2^S IS
|
||||
sll t5, v1 //InstCacheSetSize
|
||||
sll t5, t3 //t5 InstCacheSize
|
||||
|
||||
|
||||
andi v0, t4, 0x0380
|
||||
srl t7, v0, 7 //DA
|
||||
|
||||
li t6, 0x800 // 32*64
|
||||
srl v1, t4,13
|
||||
andi v1, 7 //DS
|
||||
sll t6, v1 // DataCacheSetSize
|
||||
sll t6, t7 // t5 DataCacheSize
|
||||
|
||||
####part 3####
|
||||
lui a0, 0x8000 //a0 = 0x8000 << 16
|
||||
addu a1, $0, t5
|
||||
addu a2, $0, t6
|
||||
cache_init_d2way:
|
||||
/* a0=0x80000000, a1=icache_size, a2=dcache_size */
|
||||
/* a3, v0 and v1 used as local registers */
|
||||
mtc0 $0, CP0_TAGHI
|
||||
addu v0, $0, a0 /* v0 = 0 + a0 */
|
||||
addu v1, a0, a2 /* v1 = a0 + a2 */
|
||||
1: slt a3, v0, v1 /* a3 = v0 < v1 ? 1 : 0 */
|
||||
beq a3, $0, 1f /* if (a3 == 0) goto 1f */
|
||||
nop
|
||||
mtc0 $0, CP0_TAGLO
|
||||
cache Index_Store_Tag_D, 0x0(v0) /* 1 way */
|
||||
4: beq $0, $0, 1b
|
||||
addiu v0, v0, 0x20
|
||||
1:
|
||||
cache_flush_i2way:
|
||||
addu v0, $0, a0
|
||||
addu v1, a0, a1
|
||||
1:
|
||||
slt a3, v0, v1
|
||||
beq a3, $0, 1f
|
||||
nop
|
||||
cache Index_Invalidate_I, 0x0(v0) /* 1 way */
|
||||
4:
|
||||
beq $0, $0, 1b
|
||||
addiu v0, v0, 0x20
|
||||
1:
|
||||
cache_flush_d2way:
|
||||
addu v0, $0, a0
|
||||
addu v1, a0, a2
|
||||
1: slt a3, v0, v1
|
||||
beq a3, $0, 1f
|
||||
nop
|
||||
cache Index_Writeback_Inv_D, 0x0(v0) /* 1 way */
|
||||
4: beq $0, $0, 1b
|
||||
addiu v0, v0, 0x20
|
||||
|
||||
1:
|
||||
cache_init_finish:
|
||||
jr t1
|
||||
nop
|
||||
#endif
|
||||
|
|
@ -12,6 +12,7 @@
|
|||
* 2010-05-17 swkyer first version
|
||||
* 2010-09-04 bernard move the beginning entry to 0x80200000
|
||||
* 2018-05-12 zhuangwei use -Ttext
|
||||
* 2019-12-04 Jiaxun Yang Adapt new memory layout
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(mips)
|
||||
|
|
@ -20,12 +21,18 @@ GROUP(-lgcc -lc)
|
|||
ENTRY(_start)
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x80000000 ;
|
||||
|
||||
. = ALIGN(4);
|
||||
.text :
|
||||
{
|
||||
start = ABSOLUTE(.);
|
||||
*(.selfboot);
|
||||
*(.selfboot_data);
|
||||
. = ALIGN(4);
|
||||
__selfboot_end = .;
|
||||
. = ALIGN(0x1000);
|
||||
__ebase_entry = .;
|
||||
KEEP(*(.exc_vectors))
|
||||
__ebase_end = .;
|
||||
*(.start);
|
||||
*(.text)
|
||||
*(.text.*)
|
||||
|
|
@ -74,6 +81,15 @@ SECTIONS
|
|||
*(.sdata)
|
||||
*(.sdata.*)
|
||||
}
|
||||
_edata = .;
|
||||
|
||||
.stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_system_stack_start = .;
|
||||
. = . + 0x400; /* 1kb system stack */
|
||||
_system_stack = .;
|
||||
}
|
||||
|
||||
.sbss :
|
||||
{
|
||||
|
|
|
|||
|
|
@ -8,28 +8,16 @@
|
|||
|
||||
#define RT_NAME_MAX 10
|
||||
#define RT_ALIGN_SIZE 8
|
||||
/* RT_THREAD_PRIORITY_8 is not set */
|
||||
#define RT_THREAD_PRIORITY_32
|
||||
/* RT_THREAD_PRIORITY_256 is not set */
|
||||
#define RT_THREAD_PRIORITY_MAX 32
|
||||
#define RT_TICK_PER_SECOND 1000
|
||||
#define RT_USING_OVERFLOW_CHECK
|
||||
#define RT_USING_HOOK
|
||||
#define RT_USING_IDLE_HOOK
|
||||
#define RT_IDLE_HOOK_LIST_SIZE 4
|
||||
#define IDLE_THREAD_STACK_SIZE 1024
|
||||
/* RT_USING_TIMER_SOFT is not set */
|
||||
#define RT_DEBUG
|
||||
#define RT_DEBUG_COLOR
|
||||
/* RT_DEBUG_INIT_CONFIG is not set */
|
||||
/* RT_DEBUG_THREAD_CONFIG is not set */
|
||||
/* RT_DEBUG_SCHEDULER_CONFIG is not set */
|
||||
/* RT_DEBUG_IPC_CONFIG is not set */
|
||||
/* RT_DEBUG_TIMER_CONFIG is not set */
|
||||
/* RT_DEBUG_IRQ_CONFIG is not set */
|
||||
/* RT_DEBUG_MEM_CONFIG is not set */
|
||||
/* RT_DEBUG_SLAB_CONFIG is not set */
|
||||
/* RT_DEBUG_MEMHEAP_CONFIG is not set */
|
||||
/* RT_DEBUG_MODULE_CONFIG is not set */
|
||||
|
||||
/* Inter-Thread communication */
|
||||
|
||||
|
|
@ -38,27 +26,22 @@
|
|||
#define RT_USING_EVENT
|
||||
#define RT_USING_MAILBOX
|
||||
#define RT_USING_MESSAGEQUEUE
|
||||
/* RT_USING_SIGNALS is not set */
|
||||
|
||||
/* Memory Management */
|
||||
|
||||
#define RT_USING_MEMPOOL
|
||||
#define RT_USING_MEMHEAP
|
||||
/* RT_USING_NOHEAP is not set */
|
||||
#define RT_USING_SMALL_MEM
|
||||
/* RT_USING_SLAB is not set */
|
||||
/* RT_USING_MEMHEAP_AS_HEAP is not set */
|
||||
/* RT_USING_MEMTRACE is not set */
|
||||
#define RT_USING_HEAP
|
||||
|
||||
/* Kernel Device Object */
|
||||
|
||||
#define RT_USING_DEVICE
|
||||
/* RT_USING_DEVICE_OPS is not set */
|
||||
#define RT_USING_INTERRUPT_INFO
|
||||
#define RT_USING_CONSOLE
|
||||
#define RT_CONSOLEBUF_SIZE 128
|
||||
#define RT_CONSOLE_DEVICE_NAME "uart2"
|
||||
#define RT_VER_NUM 0x40002
|
||||
|
||||
/* RT-Thread Components */
|
||||
|
||||
|
|
@ -69,7 +52,6 @@
|
|||
|
||||
/* C++ features */
|
||||
|
||||
/* RT_USING_CPLUSPLUS is not set */
|
||||
|
||||
/* Command shell */
|
||||
|
||||
|
|
@ -79,14 +61,11 @@
|
|||
#define FINSH_HISTORY_LINES 5
|
||||
#define FINSH_USING_SYMTAB
|
||||
#define FINSH_USING_DESCRIPTION
|
||||
/* FINSH_ECHO_DISABLE_DEFAULT is not set */
|
||||
#define FINSH_THREAD_PRIORITY 20
|
||||
#define FINSH_THREAD_STACK_SIZE 4096
|
||||
#define FINSH_CMD_SIZE 80
|
||||
/* FINSH_USING_AUTH is not set */
|
||||
#define FINSH_USING_MSH
|
||||
#define FINSH_USING_MSH_DEFAULT
|
||||
/* FINSH_USING_MSH_ONLY is not set */
|
||||
#define FINSH_ARG_MAX 10
|
||||
|
||||
/* Device virtual file system */
|
||||
|
|
@ -96,29 +75,6 @@
|
|||
#define DFS_FILESYSTEMS_MAX 2
|
||||
#define DFS_FILESYSTEM_TYPES_MAX 2
|
||||
#define DFS_FD_MAX 4
|
||||
/* RT_USING_DFS_MNTTABLE is not set */
|
||||
#define RT_USING_DFS_ELMFAT
|
||||
|
||||
/* elm-chan's FatFs, Generic FAT Filesystem Module */
|
||||
|
||||
#define RT_DFS_ELM_CODE_PAGE 936
|
||||
#define RT_DFS_ELM_WORD_ACCESS
|
||||
#define RT_DFS_ELM_USE_LFN_0
|
||||
/* RT_DFS_ELM_USE_LFN_1 is not set */
|
||||
/* RT_DFS_ELM_USE_LFN_2 is not set */
|
||||
/* RT_DFS_ELM_USE_LFN_3 is not set */
|
||||
#define RT_DFS_ELM_USE_LFN 0
|
||||
#define RT_DFS_ELM_MAX_LFN 64
|
||||
#define RT_DFS_ELM_DRIVES 2
|
||||
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
|
||||
/* RT_DFS_ELM_USE_ERASE is not set */
|
||||
#define RT_DFS_ELM_REENTRANT
|
||||
/* RT_USING_DFS_DEVFS is not set */
|
||||
/* RT_USING_DFS_ROMFS is not set */
|
||||
/* RT_USING_DFS_RAMFS is not set */
|
||||
/* RT_USING_DFS_UFFS is not set */
|
||||
/* RT_USING_DFS_JFFS2 is not set */
|
||||
/* RT_USING_DFS_NFS is not set */
|
||||
|
||||
/* Device Drivers */
|
||||
|
||||
|
|
@ -126,200 +82,95 @@
|
|||
#define RT_PIPE_BUFSZ 512
|
||||
#define RT_USING_SERIAL
|
||||
#define RT_SERIAL_USING_DMA
|
||||
#define RT_SERIAL_RB_BUFSZ 64
|
||||
#define RT_USING_CAN
|
||||
/* RT_CAN_USING_HDR is not set */
|
||||
/* RT_USING_HWTIMER is not set */
|
||||
/* RT_USING_CPUTIME is not set */
|
||||
#define RT_USING_I2C
|
||||
#define RT_USING_I2C_BITOPS
|
||||
#define RT_USING_PIN
|
||||
/* RT_USING_PWM is not set */
|
||||
/* RT_USING_MTD_NOR is not set */
|
||||
/* RT_USING_MTD_NAND is not set */
|
||||
/* RT_USING_MTD is not set */
|
||||
/* RT_USING_PM is not set */
|
||||
/* RT_USING_RTC is not set */
|
||||
/* RT_USING_SDIO is not set */
|
||||
#define RT_USING_SPI
|
||||
#define RT_USING_SPI_MSD
|
||||
/* RT_USING_SFUD is not set */
|
||||
/* RT_USING_W25QXX is not set */
|
||||
/* RT_USING_GD is not set */
|
||||
/* RT_USING_ENC28J60 is not set */
|
||||
/* RT_USING_SPI_WIFI is not set */
|
||||
/* RT_USING_WDT is not set */
|
||||
/* RT_USING_AUDIO is not set */
|
||||
|
||||
/* Using WiFi */
|
||||
|
||||
/* RT_USING_WIFI is not set */
|
||||
|
||||
/* Using USB */
|
||||
|
||||
/* RT_USING_USB_HOST is not set */
|
||||
/* RT_USING_USB_DEVICE is not set */
|
||||
|
||||
/* POSIX layer and C standard library */
|
||||
|
||||
#define RT_USING_LIBC
|
||||
#define RT_USING_PTHREADS
|
||||
/* RT_USING_POSIX is not set */
|
||||
/* RT_USING_MODULE is not set */
|
||||
#define PTHREAD_NUM_MAX 8
|
||||
|
||||
/* Network */
|
||||
|
||||
/* Socket abstraction layer */
|
||||
|
||||
/* RT_USING_SAL is not set */
|
||||
|
||||
/* Network interface device */
|
||||
|
||||
|
||||
/* light weight TCP/IP stack */
|
||||
|
||||
#define RT_USING_LWIP
|
||||
#define RT_USING_LWIP141
|
||||
/* RT_USING_LWIP202 is not set */
|
||||
/* RT_USING_LWIP210 is not set */
|
||||
#define RT_LWIP_IGMP
|
||||
#define RT_LWIP_ICMP
|
||||
/* RT_LWIP_SNMP is not set */
|
||||
#define RT_LWIP_DNS
|
||||
#define RT_LWIP_DHCP
|
||||
#define IP_SOF_BROADCAST 1
|
||||
#define IP_SOF_BROADCAST_RECV 1
|
||||
|
||||
/* Static IPv4 Address */
|
||||
|
||||
#define RT_LWIP_IPADDR "192.168.1.254"
|
||||
#define RT_LWIP_GWADDR "192.168.1.1"
|
||||
#define RT_LWIP_MSKADDR "255.255.255.0"
|
||||
#define RT_LWIP_UDP
|
||||
#define RT_LWIP_TCP
|
||||
/* RT_LWIP_RAW is not set */
|
||||
/* RT_LWIP_PPP is not set */
|
||||
#define RT_MEMP_NUM_NETCONN 8
|
||||
#define RT_LWIP_PBUF_NUM 4
|
||||
#define RT_LWIP_RAW_PCB_NUM 4
|
||||
#define RT_LWIP_UDP_PCB_NUM 4
|
||||
#define RT_LWIP_TCP_PCB_NUM 3
|
||||
#define RT_LWIP_TCP_SEG_NUM 40
|
||||
#define RT_LWIP_TCP_SND_BUF 4096
|
||||
#define RT_LWIP_TCP_WND 2048
|
||||
#define RT_LWIP_TCPTHREAD_PRIORITY 12
|
||||
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
|
||||
#define RT_LWIP_TCPTHREAD_STACKSIZE 4096
|
||||
/* LWIP_NO_RX_THREAD is not set */
|
||||
/* LWIP_NO_TX_THREAD is not set */
|
||||
#define RT_LWIP_ETHTHREAD_PRIORITY 14
|
||||
#define RT_LWIP_ETHTHREAD_STACKSIZE 512
|
||||
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
|
||||
/* RT_LWIP_REASSEMBLY_FRAG is not set */
|
||||
#define LWIP_NETIF_STATUS_CALLBACK 1
|
||||
#define SO_REUSE 1
|
||||
#define LWIP_SO_RCVTIMEO 1
|
||||
#define LWIP_SO_SNDTIMEO 1
|
||||
#define LWIP_SO_RCVBUF 1
|
||||
/* RT_LWIP_NETIF_LOOPBACK is not set */
|
||||
#define LWIP_NETIF_LOOPBACK 0
|
||||
/* RT_LWIP_STATS is not set */
|
||||
/* RT_LWIP_DEBUG is not set */
|
||||
|
||||
/* Modbus master and slave stack */
|
||||
|
||||
/* RT_USING_MODBUS is not set */
|
||||
|
||||
/* AT commands */
|
||||
|
||||
/* RT_USING_AT is not set */
|
||||
/* LWIP_USING_DHCPD is not set */
|
||||
|
||||
/* VBUS(Virtual Software BUS) */
|
||||
|
||||
/* RT_USING_VBUS is not set */
|
||||
|
||||
/* Utilities */
|
||||
|
||||
/* RT_USING_LOGTRACE is not set */
|
||||
/* RT_USING_RYM is not set */
|
||||
/* RT_USING_ULOG is not set */
|
||||
|
||||
/* RT-Thread MIPS CPU */
|
||||
|
||||
|
||||
/* RT-Thread online packages */
|
||||
|
||||
/* system packages */
|
||||
|
||||
/* RT-Thread GUI Engine */
|
||||
|
||||
/* PKG_USING_GUIENGINE is not set */
|
||||
/* PKG_USING_LWEXT4 is not set */
|
||||
/* PKG_USING_PARTITION is not set */
|
||||
/* PKG_USING_SQLITE is not set */
|
||||
/* PKG_USING_RTI is not set */
|
||||
|
||||
/* IoT - internet of things */
|
||||
|
||||
/* PKG_USING_PAHOMQTT is not set */
|
||||
/* PKG_USING_WEBCLIENT is not set */
|
||||
/* PKG_USING_MONGOOSE is not set */
|
||||
/* PKG_USING_WEBTERMINAL is not set */
|
||||
/* PKG_USING_CJSON is not set */
|
||||
/* PKG_USING_LJSON is not set */
|
||||
/* PKG_USING_EZXML is not set */
|
||||
/* PKG_USING_NANOPB is not set */
|
||||
/* PKG_USING_GAGENT_CLOUD is not set */
|
||||
|
||||
/* Wi-Fi */
|
||||
|
||||
/* Marvell WiFi */
|
||||
|
||||
/* PKG_USING_WLANMARVELL is not set */
|
||||
|
||||
/* Wiced WiFi */
|
||||
|
||||
/* PKG_USING_WLAN_WICED is not set */
|
||||
/* PKG_USING_COAP is not set */
|
||||
/* PKG_USING_NOPOLL is not set */
|
||||
/* PKG_USING_NETUTILS is not set */
|
||||
|
||||
/* IoT Cloud */
|
||||
|
||||
|
||||
/* security packages */
|
||||
|
||||
/* PKG_USING_MBEDTLS is not set */
|
||||
/* PKG_USING_libsodium is not set */
|
||||
/* PKG_USING_TINYCRYPT is not set */
|
||||
|
||||
/* language packages */
|
||||
|
||||
/* PKG_USING_JERRYSCRIPT is not set */
|
||||
/* PKG_USING_MICROPYTHON is not set */
|
||||
|
||||
/* multimedia packages */
|
||||
|
||||
/* PKG_USING_OPENMV is not set */
|
||||
|
||||
/* tools packages */
|
||||
|
||||
/* PKG_USING_CMBACKTRACE is not set */
|
||||
/* PKG_USING_EASYLOGGER is not set */
|
||||
/* PKG_USING_SYSTEMVIEW is not set */
|
||||
/* PKG_USING_IPERF is not set */
|
||||
|
||||
/* system packages */
|
||||
|
||||
|
||||
/* peripheral libraries and drivers */
|
||||
|
||||
|
||||
/* miscellaneous packages */
|
||||
|
||||
/* PKG_USING_FASTLZ is not set */
|
||||
/* PKG_USING_MINILZO is not set */
|
||||
/* PKG_USING_QUICKLZ is not set */
|
||||
/* PKG_USING_MULTIBUTTON is not set */
|
||||
|
||||
/* example package: hello */
|
||||
/* samples: kernel and components samples */
|
||||
|
||||
/* PKG_USING_HELLO is not set */
|
||||
/* RT_USING_SELF_BOOT is not set */
|
||||
#define SOC_1C300
|
||||
#define RT_LS1C_BAICAIBOARD
|
||||
#define RT_USING_SELF_BOOT
|
||||
#define RT_SELF_BOOT_DEBUG
|
||||
#define RT_USING_UART2
|
||||
#define RT_USING_UART1
|
||||
#define RT_UART_RX_BUFFER_SIZE 64
|
||||
#define RT_USING_GMAC_INT_MODE
|
||||
/* RT_USING_FPU is not set */
|
||||
/* RT_USING_SPI0 is not set */
|
||||
/* RT_USING_SPI1 is not set */
|
||||
#define RT_USING_I2C1
|
||||
#define RT_USING_I2C2
|
||||
#define USING_BXCAN0
|
||||
#define USING_BXCAN1
|
||||
#define NO_TOUCH
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@ import os
|
|||
|
||||
# CPU options
|
||||
ARCH='mips'
|
||||
CPU ='loongson_1c'
|
||||
CPU ='gs232'
|
||||
|
||||
# toolchains options
|
||||
CROSS_TOOL = 'gcc'
|
||||
|
|
@ -12,8 +12,8 @@ if os.getenv('RTT_CC'):
|
|||
|
||||
if CROSS_TOOL == 'gcc':
|
||||
PLATFORM = 'gcc'
|
||||
# EXEC_PATH = "/opt/mips-2015.05/bin"
|
||||
EXEC_PATH = r'D:\mgc\embedded\codebench\bin'
|
||||
EXEC_PATH = "/opt/mips-2016.05/bin"
|
||||
# EXEC_PATH = r'D:\mgc\embedded\codebench\bin'
|
||||
else:
|
||||
print('================ERROR===========================')
|
||||
print('Not support %s yet!' % CROSS_TOOL)
|
||||
|
|
@ -41,7 +41,7 @@ READELF = PREFIX + 'readelf'
|
|||
|
||||
DEVICE = ' -mips32 -msoft-float -mfp32'
|
||||
CFLAGS = DEVICE + ' -EL -G0 -mno-abicalls -fno-pic -fno-builtin -fno-exceptions -ffunction-sections -fomit-frame-pointer'
|
||||
AFLAGS = ' -c' + DEVICE + ' -EL -fno-pic -fno-builtin -mno-abicalls -x assembler-with-cpp -DSYSTEM_STACK=0x80003fe8'
|
||||
AFLAGS = ' -c' + DEVICE + ' -EL -fno-pic -fno-builtin -mno-abicalls -x assembler-with-cpp'
|
||||
LFLAGS = DEVICE + ' -nostartfiles -EL -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T ls1c_ram.lds'
|
||||
|
||||
CPATH = ''
|
||||
|
|
|
|||
Loading…
Reference in New Issue