[BSP] correct stm32l412-st-nucleo capacity info
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@ -8,7 +8,7 @@ config SOC_STM32L412RB
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default y
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default y
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menu "Onboard Peripheral Drivers"
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menu "Onboard Peripheral Drivers"
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config BSP_USING_STLINK_TO_USART
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config BSP_USING_STLINK_TO_USART
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bool "Enable STLINK TO USART (uart2)"
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bool "Enable STLINK TO USART (uart2)"
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select BSP_USING_UART
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select BSP_USING_UART
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select BSP_USING_UART2
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select BSP_USING_UART2
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@ -22,7 +22,7 @@ menu "On-chip Peripheral Drivers"
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select RT_USING_PIN
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select RT_USING_PIN
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default y
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default y
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menuconfig BSP_USING_UART
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menuconfig BSP_USING_UART
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bool "Enable UART"
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bool "Enable UART"
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default y
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default y
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select RT_USING_SERIAL
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select RT_USING_SERIAL
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@ -5,9 +5,9 @@
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/* Program Entry, set to mark it as "used" and avoid gc */
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/* Program Entry, set to mark it as "used" and avoid gc */
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MEMORY
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MEMORY
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{
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{
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ROM (rx) : ORIGIN = 0x08000000, LENGTH = 256k /* 256KB flash */
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ROM (rx) : ORIGIN = 0x08000000, LENGTH = 128k /* 128KB flash */
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RAM1 (rw) : ORIGIN = 0x20000000, LENGTH = 48k /* 48K sram */
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RAM1 (rw) : ORIGIN = 0x20000000, LENGTH = 32k /* 32K sram */
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RAM2 (rw) : ORIGIN = 0x10000000, LENGTH = 16k /* 16K sram */
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RAM2 (rw) : ORIGIN = 0x10000000, LENGTH = 8k /* 8K sram */
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}
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}
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ENTRY(Reset_Handler)
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ENTRY(Reset_Handler)
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_system_stack_size = 0x200;
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_system_stack_size = 0x200;
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@ -90,7 +90,7 @@ SECTIONS
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. = ALIGN(4);
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. = ALIGN(4);
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/* This is used by the startup in order to initialize the .data secion */
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/* This is used by the startup in order to initialize the .data secion */
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_edata = . ;
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_edata = . ;
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} >RAM2
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} >RAM1
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.stack :
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.stack :
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{
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{
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@ -99,7 +99,7 @@ SECTIONS
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. = . + _system_stack_size;
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. = . + _system_stack_size;
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. = ALIGN(4);
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. = ALIGN(4);
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_estack = .;
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_estack = .;
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} >RAM2
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} >RAM1
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__bss_start = .;
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__bss_start = .;
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.bss :
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.bss :
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@ -117,7 +117,7 @@ SECTIONS
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_ebss = . ;
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_ebss = . ;
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*(.bss.init)
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*(.bss.init)
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} > RAM2
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} > RAM1
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__bss_end = .;
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__bss_end = .;
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_end = .;
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_end = .;
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