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[bsp\raspi4]move io to `iomap.h`

This commit is contained in:
bigmagic 2020-04-17 22:19:54 +08:00
parent 098eccc057
commit bcae196541
6 changed files with 21 additions and 19 deletions
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6
bsp/raspberry-pi/raspi4/driver/board.c
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@ -18,10 +18,6 @@
#include "mmu.h"
static rt_uint64_t timerStep;
// 0x40, 0x44, 0x48, 0x4c: Core 0~3 Timers interrupt control
#define CORE0_TIMER_IRQ_CTRL HWREG32(0xFF800040)
#define TIMER_IRQ 30
#define NON_SECURE_TIMER_IRQ (1 << 1)
int rt_hw_get_gtimer_frq(void);
void rt_hw_set_gtimer_val(rt_uint64_t value);
@ -29,7 +25,7 @@ int rt_hw_get_gtimer_val(void);
int rt_hw_get_cntpct_val(void);
void rt_hw_gtimer_enable(void);
void core0_timer_enable_interrupt_controller()
void core0_timer_enable_interrupt_controller(void)
{
CORE0_TIMER_IRQ_CTRL |= NON_SECURE_TIMER_IRQ;
}

2
bsp/raspberry-pi/raspi4/driver/board.h
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@ -12,6 +12,7 @@
#define BOARD_H__
#include <stdint.h>
#include "iomap.h"
extern unsigned char __bss_start;
extern unsigned char __bss_end;
@ -22,4 +23,3 @@ extern unsigned char __bss_end;
void rt_hw_board_init(void);
#endif

2
bsp/raspberry-pi/raspi4/driver/drv_gpio.h
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@ -17,8 +17,6 @@
#include "board.h"
#include "interrupt.h"
#define GPIO_BASE (0xFE000000 + 0x00200000)
#define GPIO_REG_GPFSEL0(BASE) HWREG32(BASE + 0x00)
#define GPIO_REG_GPFSEL1(BASE) HWREG32(BASE + 0x04)
#define GPIO_REG_GPFSEL2(BASE) HWREG32(BASE + 0x08)

6
bsp/raspberry-pi/raspi4/driver/drv_uart.c
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@ -16,12 +16,6 @@
#include "drv_uart.h"
#include "drv_gpio.h"
#define UART0_BASE (0xFE000000 + 0x00201000)
#define PL011_BASE UART0_BASE
#define IRQ_PL011 (121 + 32)
#define UART_REFERENCE_CLOCK 48000000
struct hw_uart_device
{
rt_ubase_t hw_base;

1
bsp/raspberry-pi/raspi4/driver/drv_uart.h
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@ -81,4 +81,3 @@
int rt_hw_uart_init(void);
#endif /* DRV_UART_H__ */

19
bsp/raspberry-pi/raspi4/driver/iomap.h
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@ -1,8 +1,23 @@
#ifndef __RASPI4_H__
#define __RASPI4_H__
#define ARM_GIC_NR_IRQS 512
#define INTC_BASE 0xff800000
//gpio
#define GPIO_BASE (0xFE000000 + 0x00200000)
//uart
#define UART0_BASE (0xFE000000 + 0x00201000)
#define PL011_BASE UART0_BASE
#define IRQ_PL011 (121 + 32)
#define UART_REFERENCE_CLOCK (48000000)
// 0x40, 0x44, 0x48, 0x4c: Core 0~3 Timers interrupt control
#define CORE0_TIMER_IRQ_CTRL HWREG32(0xFF800040)
#define TIMER_IRQ 30
#define NON_SECURE_TIMER_IRQ (1 << 1)
//gic max
#define ARM_GIC_NR_IRQS (512)
#define INTC_BASE (0xff800000)
#define GIC_V2_DISTRIBUTOR_BASE (INTC_BASE + 0x00041000)
#define GIC_V2_CPU_INTERFACE_BASE (INTC_BASE + 0x00042000)
#define GIC_V2_HYPERVISOR_BASE (INTC_BASE + 0x00044000)