code cleanup for interrupt description
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17ab3fcdba
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bb72be94b2
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@ -22,6 +22,8 @@
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#define RT_USING_OVERFLOW_CHECK
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#define RT_USING_OVERFLOW_CHECK
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#define RT_USING_INTERRUPT_INFO
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/* Using Hook */
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/* Using Hook */
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#define RT_USING_HOOK
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#define RT_USING_HOOK
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@ -24,6 +24,9 @@
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extern "C" {
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extern "C" {
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#endif
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#endif
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/*
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* CPU interfaces
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*/
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void rt_hw_cpu_icache_enable(void);
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void rt_hw_cpu_icache_enable(void);
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void rt_hw_cpu_icache_disable(void);
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void rt_hw_cpu_icache_disable(void);
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rt_base_t rt_hw_cpu_icache_status(void);
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rt_base_t rt_hw_cpu_icache_status(void);
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@ -38,6 +41,24 @@ rt_uint8_t *rt_hw_stack_init(void *entry,
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rt_uint8_t *stack_addr,
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rt_uint8_t *stack_addr,
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void *exit);
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void *exit);
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/*
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* Interrupt handler definition
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*/
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typedef void (*rt_isr_handler_t)(int vector, void *param);
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struct rt_irq_desc {
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rt_isr_handler_t handler;
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void *param;
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#ifdef RT_USING_INTERRUPT_INFO
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char name[RT_NAME_MAX];
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rt_uint32_t counter;
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#endif
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};
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/*
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* Interrupt interfaces
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*/
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void rt_hw_interrupt_init(void);
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void rt_hw_interrupt_init(void);
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void rt_hw_interrupt_mask(int vector);
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void rt_hw_interrupt_mask(int vector);
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void rt_hw_interrupt_umask(int vector);
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void rt_hw_interrupt_umask(int vector);
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@ -45,10 +66,13 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector,
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rt_isr_handler_t handler,
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rt_isr_handler_t handler,
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void *param,
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void *param,
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char *name);
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char *name);
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void rt_hw_interrupt_handle(int vector);
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rt_base_t rt_hw_interrupt_disable(void);
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rt_base_t rt_hw_interrupt_disable(void);
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void rt_hw_interrupt_enable(rt_base_t level);
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void rt_hw_interrupt_enable(rt_base_t level);
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/*
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* Context interfaces
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*/
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void rt_hw_context_switch(rt_uint32_t from, rt_uint32_t to);
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void rt_hw_context_switch(rt_uint32_t from, rt_uint32_t to);
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void rt_hw_context_switch_to(rt_uint32_t to);
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void rt_hw_context_switch_to(rt_uint32_t to);
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void rt_hw_context_switch_interrupt(rt_uint32_t from, rt_uint32_t to);
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void rt_hw_context_switch_interrupt(rt_uint32_t from, rt_uint32_t to);
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@ -59,7 +83,7 @@ void rt_hw_backtrace(rt_uint32_t *fp, rt_uint32_t thread_entry);
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void rt_hw_show_memory(rt_uint32_t addr, rt_uint32_t size);
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void rt_hw_show_memory(rt_uint32_t addr, rt_uint32_t size);
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/*
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/*
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* exception interfaces
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* Exception interfaces
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*/
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*/
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void rt_hw_exception_install(rt_err_t (*exception_handle)(void* context));
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void rt_hw_exception_install(rt_err_t (*exception_handle)(void* context));
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@ -425,15 +425,6 @@ void rt_module_unload_sethook(void (*hook)(rt_module_t module));
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/*
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/*
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* interrupt service
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* interrupt service
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*/
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*/
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typedef void (*rt_isr_handler_t)(int vector, void *param);
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struct rt_irq_desc {
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char irq_name[RT_NAME_MAX];
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rt_isr_handler_t isr_handle;
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void *param;
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rt_uint32_t interrupt_cnt;
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};
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/*
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/*
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* rt_interrupt_enter and rt_interrupt_leave only can be called by BSP
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* rt_interrupt_enter and rt_interrupt_leave only can be called by BSP
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@ -12,7 +12,7 @@
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* 2011-01-13 weety first version
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* 2011-01-13 weety first version
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*/
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*/
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#include <rtthread.h>
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#include <rthw.h>
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#include "at91sam926x.h"
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#include "at91sam926x.h"
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#define MAX_HANDLERS (AIC_IRQS + PIN_IRQS)
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#define MAX_HANDLERS (AIC_IRQS + PIN_IRQS)
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@ -114,7 +114,7 @@ rt_isr_handler_t at91_gpio_irq_handle(rt_uint32_t vector, void *param)
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if (isr & 1)
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if (isr & 1)
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{
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{
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parameter = irq_desc[irq_n].param;
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parameter = irq_desc[irq_n].param;
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irq_desc[irq_n].isr_handle(irq_n, parameter);
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irq_desc[irq_n].handler(irq_n, parameter);
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}
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}
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isr >>= 1;
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isr >>= 1;
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irq_n++;
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irq_n++;
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@ -173,10 +173,10 @@ static void at91_gpio_irq_init()
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idx = AT91SAM9260_ID_PIOA;
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idx = AT91SAM9260_ID_PIOA;
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for (i = 0; i < 3; i++)
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for (i = 0; i < 3; i++)
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{
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{
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rt_snprintf(irq_desc[idx].irq_name, RT_NAME_MAX - 1, name[i]);
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rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, name[i]);
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irq_desc[idx].isr_handle = (rt_isr_handler_t)at91_gpio_irq_handle;
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irq_desc[idx].handler = (rt_isr_handler_t)at91_gpio_irq_handle;
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irq_desc[idx].param = RT_NULL;
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irq_desc[idx].param = RT_NULL;
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irq_desc[idx].interrupt_cnt = 0;
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irq_desc[idx].counter = 0;
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idx++;
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idx++;
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}
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}
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@ -204,10 +204,9 @@ void rt_hw_interrupt_init(void)
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/* init exceptions table */
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/* init exceptions table */
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for(idx=0; idx < MAX_HANDLERS; idx++)
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for(idx=0; idx < MAX_HANDLERS; idx++)
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{
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{
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rt_snprintf(irq_desc[idx].irq_name, RT_NAME_MAX - 1, "default");
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rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, "default");
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irq_desc[idx].isr_handle = (rt_isr_handler_t)rt_hw_interrupt_handle;
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irq_desc[idx].handler = (rt_isr_handler_t)rt_hw_interrupt_handle;
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irq_desc[idx].param = RT_NULL;
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irq_desc[idx].param = RT_NULL;
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irq_desc[idx].interrupt_cnt = 0;
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}
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}
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at91_gpio_irq_init();
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at91_gpio_irq_init();
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@ -316,13 +315,12 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
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if(vector < MAX_HANDLERS)
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if(vector < MAX_HANDLERS)
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{
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{
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old_handler = irq_desc[vector].isr_handle;
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old_handler = irq_desc[vector].handler;
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if (handler != RT_NULL)
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if (handler != RT_NULL)
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{
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{
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rt_snprintf(irq_desc[vector].irq_name, RT_NAME_MAX - 1, "%s", name);
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rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name);
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irq_desc[vector].isr_handle = (rt_isr_handler_t)handler;
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irq_desc[vector].handler = (rt_isr_handler_t)handler;
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irq_desc[vector].param = param;
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irq_desc[vector].param = param;
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irq_desc[vector].interrupt_cnt = 0;
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}
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}
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}
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}
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@ -372,9 +370,9 @@ void list_irq(void)
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rt_kprintf("number\tcount\tname\n");
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rt_kprintf("number\tcount\tname\n");
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for (irq = 0; irq < MAX_HANDLERS; irq++)
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for (irq = 0; irq < MAX_HANDLERS; irq++)
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{
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{
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if (rt_strncmp(irq_desc[irq].irq_name, "default", sizeof("default")))
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if (rt_strncmp(irq_desc[irq].name, "default", sizeof("default")))
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{
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{
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rt_kprintf("%02ld: %10ld %s\n", irq, irq_desc[irq].interrupt_cnt, irq_desc[irq].irq_name);
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rt_kprintf("%02ld: %10ld %s\n", irq, irq_desc[irq].name);
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}
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}
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}
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}
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}
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}
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@ -159,13 +159,13 @@ void rt_hw_trap_irq()
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//at91_sys_write(AT91_AIC_EOICR, 0x55555555);
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//at91_sys_write(AT91_AIC_EOICR, 0x55555555);
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/* get interrupt service routine */
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/* get interrupt service routine */
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isr_func = irq_desc[irq].isr_handle;
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isr_func = irq_desc[irq].handler;
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param = irq_desc[irq].param;
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param = irq_desc[irq].param;
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/* turn to interrupt service routine */
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/* turn to interrupt service routine */
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isr_func(irq, param);
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isr_func(irq, param);
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at91_sys_write(AT91_AIC_EOICR, 0x55555555); //EIOCR must be write any value after interrupt, or else can't response next interrupt
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at91_sys_write(AT91_AIC_EOICR, 0x55555555); //EIOCR must be write any value after interrupt, or else can't response next interrupt
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irq_desc[irq].interrupt_cnt++;
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irq_desc[irq].counter ++;
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}
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}
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void rt_hw_trap_fiq()
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void rt_hw_trap_fiq()
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