[BSP][Phytium] add support for mainbranch cherryusb (xhci host + pusb2 device/host)

This commit is contained in:
zhugengyu 2024-08-28 10:06:13 +08:00 committed by GitHub
parent 66738d71da
commit b9f4daa97a
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
62 changed files with 11603 additions and 637 deletions

4
.gitignore vendored
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@ -54,3 +54,7 @@ cmake-build-debug
# vDSO
vdso_sys.os
vdso.lds
# cherryusb libraries
!components/drivers/usb/cherryusb/port/pusb2/*.a
!components/drivers/usb/cherryusb/port/xhci/phytium/*.a

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@ -246,7 +246,41 @@ CONFIG_RT_USING_QSPI=y
CONFIG_RT_USING_PIN=y
CONFIG_RT_USING_KTIME=y
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CHERRYUSB is not set
CONFIG_RT_USING_CHERRYUSB=y
# CONFIG_RT_CHERRYUSB_DEVICE is not set
CONFIG_RT_CHERRYUSB_HOST=y
# CONFIG_RT_CHERRYUSB_HOST_CUSTOM is not set
# CONFIG_RT_CHERRYUSB_HOST_EHCI_BL is not set
# CONFIG_RT_CHERRYUSB_HOST_EHCI_HPM is not set
# CONFIG_RT_CHERRYUSB_HOST_EHCI_AIC is not set
# CONFIG_RT_CHERRYUSB_HOST_EHCI_NUVOTON_NUC980 is not set
# CONFIG_RT_CHERRYUSB_HOST_EHCI_NUVOTON_MA35D0 is not set
# CONFIG_RT_CHERRYUSB_HOST_EHCI_CUSTOM is not set
# CONFIG_RT_CHERRYUSB_HOST_DWC2_ST is not set
# CONFIG_RT_CHERRYUSB_HOST_DWC2_ESP is not set
# CONFIG_RT_CHERRYUSB_HOST_DWC2_CUSTOM is not set
# CONFIG_RT_CHERRYUSB_HOST_MUSB_ES is not set
# CONFIG_RT_CHERRYUSB_HOST_MUSB_SUNXI is not set
# CONFIG_RT_CHERRYUSB_HOST_MUSB_BK is not set
# CONFIG_RT_CHERRYUSB_HOST_MUSB_CUSTOM is not set
CONFIG_RT_CHERRYUSB_HOST_PUSB2=y
# CONFIG_RT_CHERRYUSB_HOST_XHCI is not set
# CONFIG_RT_CHERRYUSB_HOST_CDC_ACM is not set
CONFIG_RT_CHERRYUSB_HOST_HID=y
CONFIG_RT_CHERRYUSB_HOST_MSC=y
# CONFIG_RT_CHERRYUSB_HOST_CDC_ECM is not set
# CONFIG_RT_CHERRYUSB_HOST_CDC_RNDIS is not set
# CONFIG_RT_CHERRYUSB_HOST_CDC_NCM is not set
# CONFIG_RT_CHERRYUSB_HOST_VIDEO is not set
# CONFIG_RT_CHERRYUSB_HOST_AUDIO is not set
# CONFIG_RT_CHERRYUSB_HOST_BLUETOOTH is not set
# CONFIG_RT_CHERRYUSB_HOST_ASIX is not set
# CONFIG_RT_CHERRYUSB_HOST_RTL8152 is not set
# CONFIG_RT_CHERRYUSB_HOST_FTDI is not set
# CONFIG_RT_CHERRYUSB_HOST_CH34X is not set
# CONFIG_RT_CHERRYUSB_HOST_CP210X is not set
# CONFIG_RT_CHERRYUSB_HOST_PL2303 is not set
# CONFIG_CHERRYUSB_HOST_TEMPLATE is not set
# end of Device Drivers
#
@ -325,6 +359,7 @@ CONFIG_NETDEV_USING_IFCONFIG=y
CONFIG_NETDEV_USING_PING=y
CONFIG_NETDEV_USING_NETSTAT=y
CONFIG_NETDEV_USING_AUTO_DEFAULT=y
# CONFIG_NETDEV_USING_LINK_STATUS_CALLBACK is not set
# CONFIG_NETDEV_USING_IPV6 is not set
CONFIG_NETDEV_IPV4=1
CONFIG_NETDEV_IPV6=0
@ -587,6 +622,7 @@ CONFIG_RT_USING_ADT_REF=y
# CONFIG_PKG_USING_JSMN is not set
# CONFIG_PKG_USING_AGILE_JSMN is not set
# CONFIG_PKG_USING_PARSON is not set
# CONFIG_PKG_USING_RYAN_JSON is not set
# end of JSON: JavaScript Object Notation, a lightweight data-interchange format
#
@ -706,6 +742,8 @@ CONFIG_RT_USING_ADT_REF=y
# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
# end of enhanced kernel services
# CONFIG_PKG_USING_AUNITY is not set
#
# acceleration: Assembly language or algorithmic acceleration packages
#
@ -796,12 +834,29 @@ CONFIG_RT_USING_ADT_REF=y
#
# STM32 HAL & SDK Drivers
#
# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set
# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set
# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set
# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set
# CONFIG_PKG_USING_STM32WB55_SDK is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# end of STM32 HAL & SDK Drivers
#
# Infineon HAL Packages
#
# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set
# CONFIG_PKG_USING_INFINEON_CMSIS is not set
# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set
# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set
# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set
# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set
# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set
# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set
# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set
# CONFIG_PKG_USING_INFINEON_USBDEV is not set
# end of Infineon HAL Packages
# CONFIG_PKG_USING_BLUETRUM_SDK is not set
# CONFIG_PKG_USING_EMBARC_BSP is not set
# CONFIG_PKG_USING_ESP_IDF is not set
@ -974,6 +1029,7 @@ CONFIG_RT_USING_ADT_REF=y
# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set
# CONFIG_PKG_USING_BT_MX01 is not set
# CONFIG_PKG_USING_RGPOWER is not set
# CONFIG_PKG_USING_BT_MX02 is not set
# CONFIG_PKG_USING_SPI_TOOLS is not set
# end of peripheral libraries and drivers
@ -995,6 +1051,7 @@ CONFIG_RT_USING_ADT_REF=y
#
# Signal Processing and Control Algorithm Packages
#
# CONFIG_PKG_USING_APID is not set
# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
# CONFIG_PKG_USING_QPID is not set
# CONFIG_PKG_USING_UKAL is not set
@ -1322,15 +1379,11 @@ CONFIG_RT_USING_UART1=y
# CONFIG_RT_USING_UART2 is not set
# CONFIG_RT_USING_UART3 is not set
CONFIG_BSP_USING_SPI=y
# CONFIG_RT_USING_SPIM0 is not set
CONFIG_RT_USING_SPIM0=y
# CONFIG_RT_USING_SPIM1 is not set
CONFIG_RT_USING_SPIM2=y
# CONFIG_RT_USING_SPIM2 is not set
# CONFIG_RT_USING_SPIM3 is not set
CONFIG_BSP_USING_CAN=y
CONFIG_RT_USING_CANFD=y
# CONFIG_RT_USING_FILTER is not set
CONFIG_RT_USING_CAN0=y
CONFIG_RT_USING_CAN1=y
# CONFIG_BSP_USING_CAN is not set
CONFIG_BSP_USING_GPIO=y
CONFIG_BSP_USING_QSPI=y
CONFIG_RT_USING_QSPI0=y
@ -1341,7 +1394,7 @@ CONFIG_RT_LWIP_PBUF_POOL_BUFSIZE=1700
CONFIG_BSP_USING_PWM=y
# CONFIG_RT_USING_PWM0 is not set
# CONFIG_RT_USING_PWM1 is not set
CONFIG_RT_USING_PWM2=y
# CONFIG_RT_USING_PWM2 is not set
# CONFIG_RT_USING_PWM3 is not set
# CONFIG_RT_USING_PWM4 is not set
# CONFIG_RT_USING_PWM5 is not set
@ -1349,8 +1402,8 @@ CONFIG_RT_USING_PWM2=y
# CONFIG_RT_USING_PWM7 is not set
CONFIG_BSP_USING_I2C=y
CONFIG_I2C_USE_MIO=y
# CONFIG_RT_USING_MIO0 is not set
# CONFIG_RT_USING_MIO1 is not set
CONFIG_RT_USING_MIO0=y
CONFIG_RT_USING_MIO1=y
# CONFIG_RT_USING_MIO2 is not set
# CONFIG_RT_USING_MIO3 is not set
# CONFIG_RT_USING_MIO4 is not set
@ -1364,21 +1417,15 @@ CONFIG_I2C_USE_MIO=y
# CONFIG_RT_USING_MIO12 is not set
# CONFIG_RT_USING_MIO13 is not set
# CONFIG_RT_USING_MIO14 is not set
CONFIG_RT_USING_MIO15=y
# CONFIG_RT_USING_MIO15 is not set
# CONFIG_I2C_USE_CONTROLLER is not set
CONFIG_BSP_USING_SDIF=y
CONFIG_BSP_USING_SDCARD_FATFS=y
CONFIG_USING_SDIF0=y
# CONFIG_USE_SDIF0_TF is not set
CONFIG_USE_SDIF0_EMMC=y
CONFIG_USING_SDIF1=y
CONFIG_USE_SDIF1_TF=y
# CONFIG_USE_SDIF1_EMMC is not set
# CONFIG_BSP_USING_SDCARD_FATFS is not set
# CONFIG_USING_SDIF0 is not set
# CONFIG_USING_SDIF1 is not set
CONFIG_BSP_USING_DC=y
CONFIG_RT_USING_DC_CHANNEL0=y
CONFIG_RT_USING_DC_CHANNEL1=y
# CONFIG_BSP_USING_XHCI is not set
# CONFIG_BSP_USING_PUSB2 is not set
# end of On-chip Peripheral Drivers
#
@ -1397,15 +1444,14 @@ CONFIG_USE_AARCH64_L1_TO_AARCH32=y
#
# Soc configuration
#
# CONFIG_TARGET_PHYTIUMPI is not set
CONFIG_TARGET_E2000Q=y
CONFIG_TARGET_PHYTIUMPI=y
# CONFIG_TARGET_E2000Q is not set
# CONFIG_TARGET_E2000D is not set
# CONFIG_TARGET_E2000S is not set
# CONFIG_TARGET_FT2004 is not set
# CONFIG_TARGET_D2000 is not set
# CONFIG_TARGET_PD2308 is not set
CONFIG_SOC_NAME="e2000"
CONFIG_TARGET_TYPE_NAME="q"
CONFIG_SOC_NAME="phytiumpi"
CONFIG_SOC_CORE_NUM=4
CONFIG_F32BIT_MEMORY_ADDRESS=0x80000000
CONFIG_F32BIT_MEMORY_LENGTH=0x80000000
@ -1420,7 +1466,7 @@ CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
#
# Board Configuration
#
CONFIG_BOARD_NAME="demo"
CONFIG_BOARD_NAME="firefly"
# CONFIG_USE_SPI_IOPAD is not set
# CONFIG_USE_GPIO_IOPAD is not set
# CONFIG_USE_CAN_IOPAD is not set
@ -1430,7 +1476,7 @@ CONFIG_BOARD_NAME="demo"
# CONFIG_USE_TACHO_IOPAD is not set
# CONFIG_USE_UART_IOPAD is not set
# CONFIG_USE_THIRD_PARTY_IOPAD is not set
CONFIG_E2000Q_DEMO_BOARD=y
CONFIG_FIREFLY_DEMO_BOARD=y
#
# IO mux configuration when board start up

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@ -246,7 +246,41 @@ CONFIG_RT_USING_QSPI=y
CONFIG_RT_USING_PIN=y
CONFIG_RT_USING_KTIME=y
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CHERRYUSB is not set
CONFIG_RT_USING_CHERRYUSB=y
# CONFIG_RT_CHERRYUSB_DEVICE is not set
CONFIG_RT_CHERRYUSB_HOST=y
# CONFIG_RT_CHERRYUSB_HOST_CUSTOM is not set
# CONFIG_RT_CHERRYUSB_HOST_EHCI_BL is not set
# CONFIG_RT_CHERRYUSB_HOST_EHCI_HPM is not set
# CONFIG_RT_CHERRYUSB_HOST_EHCI_AIC is not set
# CONFIG_RT_CHERRYUSB_HOST_EHCI_NUVOTON_NUC980 is not set
# CONFIG_RT_CHERRYUSB_HOST_EHCI_NUVOTON_MA35D0 is not set
# CONFIG_RT_CHERRYUSB_HOST_EHCI_CUSTOM is not set
# CONFIG_RT_CHERRYUSB_HOST_DWC2_ST is not set
# CONFIG_RT_CHERRYUSB_HOST_DWC2_ESP is not set
# CONFIG_RT_CHERRYUSB_HOST_DWC2_CUSTOM is not set
# CONFIG_RT_CHERRYUSB_HOST_MUSB_ES is not set
# CONFIG_RT_CHERRYUSB_HOST_MUSB_SUNXI is not set
# CONFIG_RT_CHERRYUSB_HOST_MUSB_BK is not set
# CONFIG_RT_CHERRYUSB_HOST_MUSB_CUSTOM is not set
# CONFIG_RT_CHERRYUSB_HOST_PUSB2 is not set
CONFIG_RT_CHERRYUSB_HOST_XHCI=y
# CONFIG_RT_CHERRYUSB_HOST_CDC_ACM is not set
CONFIG_RT_CHERRYUSB_HOST_HID=y
CONFIG_RT_CHERRYUSB_HOST_MSC=y
# CONFIG_RT_CHERRYUSB_HOST_CDC_ECM is not set
# CONFIG_RT_CHERRYUSB_HOST_CDC_RNDIS is not set
# CONFIG_RT_CHERRYUSB_HOST_CDC_NCM is not set
# CONFIG_RT_CHERRYUSB_HOST_VIDEO is not set
# CONFIG_RT_CHERRYUSB_HOST_AUDIO is not set
# CONFIG_RT_CHERRYUSB_HOST_BLUETOOTH is not set
# CONFIG_RT_CHERRYUSB_HOST_ASIX is not set
# CONFIG_RT_CHERRYUSB_HOST_RTL8152 is not set
# CONFIG_RT_CHERRYUSB_HOST_FTDI is not set
# CONFIG_RT_CHERRYUSB_HOST_CH34X is not set
# CONFIG_RT_CHERRYUSB_HOST_CP210X is not set
# CONFIG_RT_CHERRYUSB_HOST_PL2303 is not set
# CONFIG_CHERRYUSB_HOST_TEMPLATE is not set
# end of Device Drivers
#
@ -325,6 +359,7 @@ CONFIG_NETDEV_USING_IFCONFIG=y
CONFIG_NETDEV_USING_PING=y
CONFIG_NETDEV_USING_NETSTAT=y
CONFIG_NETDEV_USING_AUTO_DEFAULT=y
# CONFIG_NETDEV_USING_LINK_STATUS_CALLBACK is not set
# CONFIG_NETDEV_USING_IPV6 is not set
CONFIG_NETDEV_IPV4=1
CONFIG_NETDEV_IPV6=0
@ -587,6 +622,7 @@ CONFIG_RT_USING_ADT_REF=y
# CONFIG_PKG_USING_JSMN is not set
# CONFIG_PKG_USING_AGILE_JSMN is not set
# CONFIG_PKG_USING_PARSON is not set
# CONFIG_PKG_USING_RYAN_JSON is not set
# end of JSON: JavaScript Object Notation, a lightweight data-interchange format
#
@ -706,6 +742,8 @@ CONFIG_RT_USING_ADT_REF=y
# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
# end of enhanced kernel services
# CONFIG_PKG_USING_AUNITY is not set
#
# acceleration: Assembly language or algorithmic acceleration packages
#
@ -796,12 +834,29 @@ CONFIG_RT_USING_ADT_REF=y
#
# STM32 HAL & SDK Drivers
#
# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set
# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set
# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set
# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set
# CONFIG_PKG_USING_STM32WB55_SDK is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# end of STM32 HAL & SDK Drivers
#
# Infineon HAL Packages
#
# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set
# CONFIG_PKG_USING_INFINEON_CMSIS is not set
# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set
# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set
# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set
# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set
# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set
# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set
# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set
# CONFIG_PKG_USING_INFINEON_USBDEV is not set
# end of Infineon HAL Packages
# CONFIG_PKG_USING_BLUETRUM_SDK is not set
# CONFIG_PKG_USING_EMBARC_BSP is not set
# CONFIG_PKG_USING_ESP_IDF is not set
@ -974,6 +1029,7 @@ CONFIG_RT_USING_ADT_REF=y
# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set
# CONFIG_PKG_USING_BT_MX01 is not set
# CONFIG_PKG_USING_RGPOWER is not set
# CONFIG_PKG_USING_BT_MX02 is not set
# CONFIG_PKG_USING_SPI_TOOLS is not set
# end of peripheral libraries and drivers
@ -995,6 +1051,7 @@ CONFIG_RT_USING_ADT_REF=y
#
# Signal Processing and Control Algorithm Packages
#
# CONFIG_PKG_USING_APID is not set
# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
# CONFIG_PKG_USING_QPID is not set
# CONFIG_PKG_USING_UKAL is not set
@ -1377,8 +1434,6 @@ CONFIG_USE_SDIF1_TF=y
CONFIG_BSP_USING_DC=y
CONFIG_RT_USING_DC_CHANNEL0=y
CONFIG_RT_USING_DC_CHANNEL1=y
# CONFIG_BSP_USING_XHCI is not set
# CONFIG_BSP_USING_PUSB2 is not set
# end of On-chip Peripheral Drivers
#

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@ -153,6 +153,11 @@
#define RT_USING_QSPI
#define RT_USING_PIN
#define RT_USING_KTIME
#define RT_USING_CHERRYUSB
#define RT_CHERRYUSB_HOST
#define RT_CHERRYUSB_HOST_XHCI
#define RT_CHERRYUSB_HOST_HID
#define RT_CHERRYUSB_HOST_MSC
/* end of Device Drivers */
/* C/C++ and POSIX layer */
@ -373,6 +378,10 @@
/* end of STM32 HAL & SDK Drivers */
/* Infineon HAL Packages */
/* end of Infineon HAL Packages */
/* Kendryte SDK */
/* end of Kendryte SDK */

File diff suppressed because it is too large Load Diff

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@ -0,0 +1,550 @@
#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* RT-Thread Kernel */
#define RT_NAME_MAX 16
#define RT_USING_SMP
#define RT_CPUS_NR 2
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 4096
#define SYSTEM_THREAD_STACK_SIZE 4096
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 4096
/* kservice optimization */
/* end of kservice optimization */
/* klibc optimization */
/* end of klibc optimization */
#define RT_USING_DEBUG
#define RT_DEBUGING_ASSERT
#define RT_DEBUGING_COLOR
#define RT_DEBUGING_CONTEXT
#define RT_USING_OVERFLOW_CHECK
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
#define RT_USING_MESSAGEQUEUE_PRIORITY
/* end of Inter-Thread communication */
/* Memory Management */
#define RT_PAGE_MAX_ORDER 11
#define RT_USING_SLAB
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SLAB_AS_HEAP
#define RT_USING_HEAP_ISR
#define RT_USING_HEAP
/* end of Memory Management */
#define RT_USING_DEVICE
#define RT_USING_SCHED_THREAD_CTX
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 256
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x50200
#define RT_USING_STDC_ATOMIC
#define RT_BACKTRACE_LEVEL_MAX_NR 32
/* end of RT-Thread Kernel */
#define RT_USING_CACHE
#define RT_USING_HW_ATOMIC
#define RT_USING_CPU_FFS
#define ARCH_MM_MMU
#define ARCH_ARM
#define ARCH_ARM_MMU
#define ARCH_ARM_CORTEX_A
#define RT_USING_GIC_V3
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 8192
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
#define FINSH_USING_OPTION_COMPLETION
/* DFS: device virtual file system */
#define RT_USING_DFS
#define DFS_USING_POSIX
#define DFS_USING_WORKDIR
#define DFS_FD_MAX 16
#define RT_USING_DFS_V1
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_LFN_UNICODE_0
#define RT_DFS_ELM_LFN_UNICODE 0
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
#define RT_DFS_ELM_REENTRANT
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
/* end of elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_RAMFS
#define RT_USING_DFS_MQUEUE
/* end of DFS: device virtual file system */
/* Device Drivers */
#define RT_USING_DEV_BUS
#define RT_USING_DEVICE_IPC
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 4096
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 1024
#define RT_USING_CAN
#define RT_CAN_USING_CANFD
#define RT_USING_I2C
#define RT_USING_I2C_BITOPS
#define RT_USING_NULL
#define RT_USING_ZERO
#define RT_USING_RANDOM
#define RT_USING_PWM
#define RT_USING_RTC
#define RT_USING_SDIO
#define RT_SDIO_STACK_SIZE 4096
#define RT_SDIO_THREAD_PRIORITY 15
#define RT_MMCSD_STACK_SIZE 4096
#define RT_MMCSD_THREAD_PREORITY 22
#define RT_MMCSD_MAX_PARTITION 16
#define RT_USING_SPI
#define RT_USING_QSPI
#define RT_USING_PIN
#define RT_USING_KTIME
#define RT_USING_CHERRYUSB
#define RT_CHERRYUSB_DEVICE
#define RT_CHERRYUSB_DEVICE_SPEED_HS
#define RT_CHERRYUSB_DEVICE_PUSB2
#define RT_CHERRYUSB_DEVICE_MSC
#define RT_CHERRYUSB_DEVICE_TEMPLATE_MSC
/* end of Device Drivers */
/* C/C++ and POSIX layer */
/* ISO-ANSI C layer */
/* Timezone and Daylight Saving Time */
#define RT_LIBC_USING_LIGHT_TZ_DST
#define RT_LIBC_TZ_DEFAULT_HOUR 8
#define RT_LIBC_TZ_DEFAULT_MIN 0
#define RT_LIBC_TZ_DEFAULT_SEC 0
/* end of Timezone and Daylight Saving Time */
/* end of ISO-ANSI C layer */
/* POSIX (Portable Operating System Interface) layer */
#define RT_USING_POSIX_FS
#define RT_USING_POSIX_DEVIO
#define RT_USING_POSIX_STDIO
#define RT_USING_POSIX_POLL
#define RT_USING_POSIX_SELECT
#define RT_USING_POSIX_TERMIOS
#define RT_USING_POSIX_AIO
#define RT_USING_POSIX_DELAY
#define RT_USING_POSIX_CLOCK
#define RT_USING_POSIX_TIMER
/* Interprocess Communication (IPC) */
#define RT_USING_POSIX_PIPE
#define RT_USING_POSIX_PIPE_SIZE 512
#define RT_USING_POSIX_MESSAGE_QUEUE
#define RT_USING_POSIX_MESSAGE_SEMAPHORE
/* Socket is in the 'Network' category */
/* end of Interprocess Communication (IPC) */
/* end of POSIX (Portable Operating System Interface) layer */
/* end of C/C++ and POSIX layer */
/* Network */
#define RT_USING_SAL
#define SAL_INTERNET_CHECK
/* Docking with protocol stacks */
#define SAL_USING_LWIP
/* end of Docking with protocol stacks */
#define SAL_USING_POSIX
#define RT_USING_NETDEV
#define NETDEV_USING_IFCONFIG
#define NETDEV_USING_PING
#define NETDEV_USING_NETSTAT
#define NETDEV_USING_AUTO_DEFAULT
#define NETDEV_IPV4 1
#define NETDEV_IPV6 0
#define RT_USING_LWIP
#define RT_USING_LWIP212
#define RT_USING_LWIP_VER_NUM 0x20102
#define RT_LWIP_MEM_ALIGNMENT 64
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
#define RT_LWIP_DNS
/* Static IPv4 Address */
#define RT_LWIP_IPADDR "192.168.4.10"
#define RT_LWIP_GWADDR "192.168.4.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
/* end of Static IPv4 Address */
#define RT_LWIP_UDP
#define RT_LWIP_TCP
#define RT_LWIP_RAW
#define RT_MEMP_NUM_NETCONN 8
#define RT_LWIP_PBUF_NUM 512
#define RT_LWIP_RAW_PCB_NUM 4
#define RT_LWIP_UDP_PCB_NUM 4
#define RT_LWIP_TCP_PCB_NUM 4
#define RT_LWIP_TCP_SEG_NUM 40
#define RT_LWIP_TCP_SND_BUF 8196
#define RT_LWIP_TCP_WND 8196
#define RT_LWIP_TCPTHREAD_PRIORITY 16
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_STACKSIZE 16184
#define RT_LWIP_ETHTHREAD_PRIORITY 12
#define RT_LWIP_ETHTHREAD_STACKSIZE 8192
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
#define RT_LWIP_REASSEMBLY_FRAG
#define LWIP_NETIF_STATUS_CALLBACK 1
#define LWIP_NETIF_LINK_CALLBACK 1
#define RT_LWIP_NETIF_NAMESIZE 6
#define SO_REUSE 1
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
#define LWIP_SO_LINGER 0
#define LWIP_NETIF_LOOPBACK 0
#define RT_LWIP_USING_PING
/* end of Network */
/* Memory protection */
/* end of Memory protection */
/* Utilities */
#define RT_USING_RYM
#define YMODEM_USING_FILE_TRANSFER
#define RT_USING_UTEST
#define UTEST_THR_STACK_SIZE 4096
#define UTEST_THR_PRIORITY 20
#define RT_USING_RESOURCE_ID
#define RT_USING_ADT
#define RT_USING_ADT_AVL
#define RT_USING_ADT_BITMAP
#define RT_USING_ADT_HASHMAP
#define RT_USING_ADT_REF
/* end of Utilities */
/* Using USB legacy version */
/* end of Using USB legacy version */
/* end of RT-Thread Components */
/* RT-Thread Utestcases */
/* end of RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* end of Marvell WiFi */
/* Wiced WiFi */
/* end of Wiced WiFi */
/* CYW43012 WiFi */
/* end of CYW43012 WiFi */
/* BL808 WiFi */
/* end of BL808 WiFi */
/* CYW43439 WiFi */
/* end of CYW43439 WiFi */
/* end of Wi-Fi */
/* IoT Cloud */
/* end of IoT Cloud */
/* end of IoT - internet of things */
/* security packages */
/* end of security packages */
/* language packages */
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* XML: Extensible Markup Language */
/* end of XML: Extensible Markup Language */
/* end of language packages */
/* multimedia packages */
/* LVGL: powerful and easy-to-use embedded GUI library */
/* end of LVGL: powerful and easy-to-use embedded GUI library */
/* u8g2: a monochrome graphic library */
/* end of u8g2: a monochrome graphic library */
/* end of multimedia packages */
/* tools packages */
/* end of tools packages */
/* system packages */
/* enhanced kernel services */
/* end of enhanced kernel services */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* end of acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
/* end of Micrium: Micrium software products porting for RT-Thread */
/* end of system packages */
/* peripheral libraries and drivers */
/* HAL & SDK Drivers */
/* STM32 HAL & SDK Drivers */
/* end of STM32 HAL & SDK Drivers */
/* Infineon HAL Packages */
/* end of Infineon HAL Packages */
/* Kendryte SDK */
/* end of Kendryte SDK */
/* end of HAL & SDK Drivers */
/* sensors drivers */
/* end of sensors drivers */
/* touch drivers */
/* end of touch drivers */
/* end of peripheral libraries and drivers */
/* AI packages */
/* end of AI packages */
/* Signal Processing and Control Algorithm Packages */
/* end of Signal Processing and Control Algorithm Packages */
/* miscellaneous packages */
/* project laboratory */
/* end of project laboratory */
/* samples: kernel and components samples */
/* end of samples: kernel and components samples */
/* entertainment: terminal games and other interesting software packages */
/* end of entertainment: terminal games and other interesting software packages */
/* end of miscellaneous packages */
/* Arduino libraries */
/* Projects and Demos */
/* end of Projects and Demos */
/* Sensors */
/* end of Sensors */
/* Display */
/* end of Display */
/* Timing */
/* end of Timing */
/* Data Processing */
/* end of Data Processing */
/* Data Storage */
/* Communication */
/* end of Communication */
/* Device Control */
/* end of Device Control */
/* Other */
/* end of Other */
/* Signal IO */
/* end of Signal IO */
/* Uncategorized */
/* end of Arduino libraries */
/* end of RT-Thread online packages */
/* Hardware Drivers */
/* On-chip Peripheral Drivers */
#define BSP_USING_IOPAD
#define BSP_USING_UART
#define RT_USING_UART0
#define RT_USING_UART1
#define BSP_USING_SPI
#define RT_USING_SPIM2
#define BSP_USING_CAN
#define RT_USING_CANFD
#define RT_USING_CAN0
#define RT_USING_CAN1
#define BSP_USING_GPIO
#define BSP_USING_QSPI
#define RT_USING_QSPI0
#define USING_QSPI_CHANNEL0
#define BSP_USING_ETH
#define RT_LWIP_PBUF_POOL_BUFSIZE 1700
#define BSP_USING_PWM
#define RT_USING_PWM2
#define BSP_USING_I2C
#define I2C_USE_MIO
#define RT_USING_MIO0
#define RT_USING_MIO1
#define BSP_USING_SDIF
#define BSP_USING_SDCARD_FATFS
#define USING_SDIF0
#define USE_SDIF0_EMMC
#define USING_SDIF1
#define USE_SDIF1_TF
#define BSP_USING_DC
#define RT_USING_DC_CHANNEL0
#define RT_USING_DC_CHANNEL1
/* end of On-chip Peripheral Drivers */
/* Board extended module Drivers */
/* end of Hardware Drivers */
#define PHYTIUM_ARCH_AARCH32
/* Standalone Setting */
#define TARGET_ARMV8_AARCH32
#define USE_AARCH64_L1_TO_AARCH32
/* Soc configuration */
#define TARGET_E2000D
#define SOC_NAME "e2000"
#define TARGET_TYPE_NAME "d"
#define SOC_CORE_NUM 2
#define F32BIT_MEMORY_ADDRESS 0x80000000
#define F32BIT_MEMORY_LENGTH 0x80000000
#define F64BIT_MEMORY_ADDRESS 0x2000000000
#define F64BIT_MEMORY_LENGTH 0x800000000
#define TARGET_E2000
#define DEFAULT_DEBUG_PRINT_UART1
/* end of Soc configuration */
/* Board Configuration */
#define E2000D_DEMO_BOARD
#define BOARD_NAME "demo"
/* IO mux configuration when board start up */
/* end of IO mux configuration when board start up */
/* end of Board Configuration */
/* Sdk common configuration */
#define ELOG_LINE_BUF_SIZE 0x100
#define LOG_ERROR
#define USE_DEFAULT_INTERRUPT_CONFIG
#define INTERRUPT_ROLE_MASTER
/* end of Sdk common configuration */
/* end of Standalone Setting */
#endif

View File

@ -246,7 +246,41 @@ CONFIG_RT_USING_QSPI=y
CONFIG_RT_USING_PIN=y
CONFIG_RT_USING_KTIME=y
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CHERRYUSB is not set
CONFIG_RT_USING_CHERRYUSB=y
# CONFIG_RT_CHERRYUSB_DEVICE is not set
CONFIG_RT_CHERRYUSB_HOST=y
# CONFIG_RT_CHERRYUSB_HOST_CUSTOM is not set
# CONFIG_RT_CHERRYUSB_HOST_EHCI_BL is not set
# CONFIG_RT_CHERRYUSB_HOST_EHCI_HPM is not set
# CONFIG_RT_CHERRYUSB_HOST_EHCI_AIC is not set
# CONFIG_RT_CHERRYUSB_HOST_EHCI_NUVOTON_NUC980 is not set
# CONFIG_RT_CHERRYUSB_HOST_EHCI_NUVOTON_MA35D0 is not set
# CONFIG_RT_CHERRYUSB_HOST_EHCI_CUSTOM is not set
# CONFIG_RT_CHERRYUSB_HOST_DWC2_ST is not set
# CONFIG_RT_CHERRYUSB_HOST_DWC2_ESP is not set
# CONFIG_RT_CHERRYUSB_HOST_DWC2_CUSTOM is not set
# CONFIG_RT_CHERRYUSB_HOST_MUSB_ES is not set
# CONFIG_RT_CHERRYUSB_HOST_MUSB_SUNXI is not set
# CONFIG_RT_CHERRYUSB_HOST_MUSB_BK is not set
# CONFIG_RT_CHERRYUSB_HOST_MUSB_CUSTOM is not set
# CONFIG_RT_CHERRYUSB_HOST_PUSB2 is not set
CONFIG_RT_CHERRYUSB_HOST_XHCI=y
# CONFIG_RT_CHERRYUSB_HOST_CDC_ACM is not set
CONFIG_RT_CHERRYUSB_HOST_HID=y
CONFIG_RT_CHERRYUSB_HOST_MSC=y
# CONFIG_RT_CHERRYUSB_HOST_CDC_ECM is not set
# CONFIG_RT_CHERRYUSB_HOST_CDC_RNDIS is not set
# CONFIG_RT_CHERRYUSB_HOST_CDC_NCM is not set
# CONFIG_RT_CHERRYUSB_HOST_VIDEO is not set
# CONFIG_RT_CHERRYUSB_HOST_AUDIO is not set
# CONFIG_RT_CHERRYUSB_HOST_BLUETOOTH is not set
# CONFIG_RT_CHERRYUSB_HOST_ASIX is not set
# CONFIG_RT_CHERRYUSB_HOST_RTL8152 is not set
# CONFIG_RT_CHERRYUSB_HOST_FTDI is not set
# CONFIG_RT_CHERRYUSB_HOST_CH34X is not set
# CONFIG_RT_CHERRYUSB_HOST_CP210X is not set
# CONFIG_RT_CHERRYUSB_HOST_PL2303 is not set
# CONFIG_CHERRYUSB_HOST_TEMPLATE is not set
# end of Device Drivers
#
@ -325,6 +359,7 @@ CONFIG_NETDEV_USING_IFCONFIG=y
CONFIG_NETDEV_USING_PING=y
CONFIG_NETDEV_USING_NETSTAT=y
CONFIG_NETDEV_USING_AUTO_DEFAULT=y
# CONFIG_NETDEV_USING_LINK_STATUS_CALLBACK is not set
# CONFIG_NETDEV_USING_IPV6 is not set
CONFIG_NETDEV_IPV4=1
CONFIG_NETDEV_IPV6=0
@ -587,6 +622,7 @@ CONFIG_RT_USING_ADT_REF=y
# CONFIG_PKG_USING_JSMN is not set
# CONFIG_PKG_USING_AGILE_JSMN is not set
# CONFIG_PKG_USING_PARSON is not set
# CONFIG_PKG_USING_RYAN_JSON is not set
# end of JSON: JavaScript Object Notation, a lightweight data-interchange format
#
@ -706,6 +742,8 @@ CONFIG_RT_USING_ADT_REF=y
# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
# end of enhanced kernel services
# CONFIG_PKG_USING_AUNITY is not set
#
# acceleration: Assembly language or algorithmic acceleration packages
#
@ -796,12 +834,29 @@ CONFIG_RT_USING_ADT_REF=y
#
# STM32 HAL & SDK Drivers
#
# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set
# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set
# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set
# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set
# CONFIG_PKG_USING_STM32WB55_SDK is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# end of STM32 HAL & SDK Drivers
#
# Infineon HAL Packages
#
# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set
# CONFIG_PKG_USING_INFINEON_CMSIS is not set
# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set
# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set
# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set
# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set
# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set
# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set
# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set
# CONFIG_PKG_USING_INFINEON_USBDEV is not set
# end of Infineon HAL Packages
# CONFIG_PKG_USING_BLUETRUM_SDK is not set
# CONFIG_PKG_USING_EMBARC_BSP is not set
# CONFIG_PKG_USING_ESP_IDF is not set
@ -974,6 +1029,7 @@ CONFIG_RT_USING_ADT_REF=y
# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set
# CONFIG_PKG_USING_BT_MX01 is not set
# CONFIG_PKG_USING_RGPOWER is not set
# CONFIG_PKG_USING_BT_MX02 is not set
# CONFIG_PKG_USING_SPI_TOOLS is not set
# end of peripheral libraries and drivers
@ -995,6 +1051,7 @@ CONFIG_RT_USING_ADT_REF=y
#
# Signal Processing and Control Algorithm Packages
#
# CONFIG_PKG_USING_APID is not set
# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
# CONFIG_PKG_USING_QPID is not set
# CONFIG_PKG_USING_UKAL is not set
@ -1337,7 +1394,7 @@ CONFIG_RT_LWIP_PBUF_POOL_BUFSIZE=1700
CONFIG_BSP_USING_PWM=y
# CONFIG_RT_USING_PWM0 is not set
# CONFIG_RT_USING_PWM1 is not set
CONFIG_RT_USING_PWM2=y
# CONFIG_RT_USING_PWM2 is not set
# CONFIG_RT_USING_PWM3 is not set
# CONFIG_RT_USING_PWM4 is not set
# CONFIG_RT_USING_PWM5 is not set
@ -1363,16 +1420,12 @@ CONFIG_RT_USING_MIO1=y
# CONFIG_RT_USING_MIO15 is not set
# CONFIG_I2C_USE_CONTROLLER is not set
CONFIG_BSP_USING_SDIF=y
CONFIG_BSP_USING_SDCARD_FATFS=y
CONFIG_USING_SDIF0=y
CONFIG_USE_SDIF0_TF=y
# CONFIG_USE_SDIF0_EMMC is not set
# CONFIG_BSP_USING_SDCARD_FATFS is not set
# CONFIG_USING_SDIF0 is not set
# CONFIG_USING_SDIF1 is not set
CONFIG_BSP_USING_DC=y
CONFIG_RT_USING_DC_CHANNEL0=y
CONFIG_RT_USING_DC_CHANNEL1=y
# CONFIG_BSP_USING_XHCI is not set
# CONFIG_BSP_USING_PUSB2 is not set
# end of On-chip Peripheral Drivers
#

View File

@ -153,6 +153,11 @@
#define RT_USING_QSPI
#define RT_USING_PIN
#define RT_USING_KTIME
#define RT_USING_CHERRYUSB
#define RT_CHERRYUSB_HOST
#define RT_CHERRYUSB_HOST_XHCI
#define RT_CHERRYUSB_HOST_HID
#define RT_CHERRYUSB_HOST_MSC
/* end of Device Drivers */
/* C/C++ and POSIX layer */
@ -373,6 +378,10 @@
/* end of STM32 HAL & SDK Drivers */
/* Infineon HAL Packages */
/* end of Infineon HAL Packages */
/* Kendryte SDK */
/* end of Kendryte SDK */
@ -474,15 +483,11 @@
#define BSP_USING_ETH
#define RT_LWIP_PBUF_POOL_BUFSIZE 1700
#define BSP_USING_PWM
#define RT_USING_PWM2
#define BSP_USING_I2C
#define I2C_USE_MIO
#define RT_USING_MIO0
#define RT_USING_MIO1
#define BSP_USING_SDIF
#define BSP_USING_SDCARD_FATFS
#define USING_SDIF0
#define USE_SDIF0_TF
#define BSP_USING_DC
#define RT_USING_DC_CHANNEL0
#define RT_USING_DC_CHANNEL1

File diff suppressed because it is too large Load Diff

View File

@ -0,0 +1,538 @@
#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* RT-Thread Kernel */
#define RT_NAME_MAX 16
#define RT_USING_SMP
#define RT_CPUS_NR 4
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 4096
#define SYSTEM_THREAD_STACK_SIZE 4096
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 4096
/* kservice optimization */
/* end of kservice optimization */
/* klibc optimization */
/* end of klibc optimization */
#define RT_USING_DEBUG
#define RT_DEBUGING_ASSERT
#define RT_DEBUGING_COLOR
#define RT_DEBUGING_CONTEXT
#define RT_USING_OVERFLOW_CHECK
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
#define RT_USING_MESSAGEQUEUE_PRIORITY
/* end of Inter-Thread communication */
/* Memory Management */
#define RT_PAGE_MAX_ORDER 11
#define RT_USING_SLAB
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SLAB_AS_HEAP
#define RT_USING_HEAP_ISR
#define RT_USING_HEAP
/* end of Memory Management */
#define RT_USING_DEVICE
#define RT_USING_SCHED_THREAD_CTX
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 256
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x50200
#define RT_USING_STDC_ATOMIC
#define RT_BACKTRACE_LEVEL_MAX_NR 32
/* end of RT-Thread Kernel */
#define RT_USING_CACHE
#define RT_USING_HW_ATOMIC
#define RT_USING_CPU_FFS
#define ARCH_MM_MMU
#define ARCH_ARM
#define ARCH_ARM_MMU
#define ARCH_ARM_CORTEX_A
#define RT_USING_GIC_V3
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 8192
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
#define FINSH_USING_OPTION_COMPLETION
/* DFS: device virtual file system */
#define RT_USING_DFS
#define DFS_USING_POSIX
#define DFS_USING_WORKDIR
#define DFS_FD_MAX 16
#define RT_USING_DFS_V1
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_LFN_UNICODE_0
#define RT_DFS_ELM_LFN_UNICODE 0
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
#define RT_DFS_ELM_REENTRANT
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
/* end of elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_RAMFS
#define RT_USING_DFS_MQUEUE
/* end of DFS: device virtual file system */
/* Device Drivers */
#define RT_USING_DEV_BUS
#define RT_USING_DEVICE_IPC
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 4096
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 1024
#define RT_USING_CAN
#define RT_CAN_USING_CANFD
#define RT_USING_I2C
#define RT_USING_I2C_BITOPS
#define RT_USING_NULL
#define RT_USING_ZERO
#define RT_USING_RANDOM
#define RT_USING_PWM
#define RT_USING_RTC
#define RT_USING_SDIO
#define RT_SDIO_STACK_SIZE 4096
#define RT_SDIO_THREAD_PRIORITY 15
#define RT_MMCSD_STACK_SIZE 4096
#define RT_MMCSD_THREAD_PREORITY 22
#define RT_MMCSD_MAX_PARTITION 16
#define RT_USING_SPI
#define RT_USING_QSPI
#define RT_USING_PIN
#define RT_USING_KTIME
#define RT_USING_CHERRYUSB
#define RT_CHERRYUSB_HOST
#define RT_CHERRYUSB_HOST_PUSB2
#define RT_CHERRYUSB_HOST_HID
#define RT_CHERRYUSB_HOST_MSC
/* end of Device Drivers */
/* C/C++ and POSIX layer */
/* ISO-ANSI C layer */
/* Timezone and Daylight Saving Time */
#define RT_LIBC_USING_LIGHT_TZ_DST
#define RT_LIBC_TZ_DEFAULT_HOUR 8
#define RT_LIBC_TZ_DEFAULT_MIN 0
#define RT_LIBC_TZ_DEFAULT_SEC 0
/* end of Timezone and Daylight Saving Time */
/* end of ISO-ANSI C layer */
/* POSIX (Portable Operating System Interface) layer */
#define RT_USING_POSIX_FS
#define RT_USING_POSIX_DEVIO
#define RT_USING_POSIX_STDIO
#define RT_USING_POSIX_POLL
#define RT_USING_POSIX_SELECT
#define RT_USING_POSIX_TERMIOS
#define RT_USING_POSIX_AIO
#define RT_USING_POSIX_DELAY
#define RT_USING_POSIX_CLOCK
#define RT_USING_POSIX_TIMER
/* Interprocess Communication (IPC) */
#define RT_USING_POSIX_PIPE
#define RT_USING_POSIX_PIPE_SIZE 512
#define RT_USING_POSIX_MESSAGE_QUEUE
#define RT_USING_POSIX_MESSAGE_SEMAPHORE
/* Socket is in the 'Network' category */
/* end of Interprocess Communication (IPC) */
/* end of POSIX (Portable Operating System Interface) layer */
/* end of C/C++ and POSIX layer */
/* Network */
#define RT_USING_SAL
#define SAL_INTERNET_CHECK
/* Docking with protocol stacks */
#define SAL_USING_LWIP
/* end of Docking with protocol stacks */
#define SAL_USING_POSIX
#define RT_USING_NETDEV
#define NETDEV_USING_IFCONFIG
#define NETDEV_USING_PING
#define NETDEV_USING_NETSTAT
#define NETDEV_USING_AUTO_DEFAULT
#define NETDEV_IPV4 1
#define NETDEV_IPV6 0
#define RT_USING_LWIP
#define RT_USING_LWIP212
#define RT_USING_LWIP_VER_NUM 0x20102
#define RT_LWIP_MEM_ALIGNMENT 64
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
#define RT_LWIP_DNS
/* Static IPv4 Address */
#define RT_LWIP_IPADDR "192.168.4.10"
#define RT_LWIP_GWADDR "192.168.4.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
/* end of Static IPv4 Address */
#define RT_LWIP_UDP
#define RT_LWIP_TCP
#define RT_LWIP_RAW
#define RT_MEMP_NUM_NETCONN 8
#define RT_LWIP_PBUF_NUM 512
#define RT_LWIP_RAW_PCB_NUM 4
#define RT_LWIP_UDP_PCB_NUM 4
#define RT_LWIP_TCP_PCB_NUM 4
#define RT_LWIP_TCP_SEG_NUM 40
#define RT_LWIP_TCP_SND_BUF 8196
#define RT_LWIP_TCP_WND 8196
#define RT_LWIP_TCPTHREAD_PRIORITY 16
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_STACKSIZE 16184
#define RT_LWIP_ETHTHREAD_PRIORITY 12
#define RT_LWIP_ETHTHREAD_STACKSIZE 8192
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
#define RT_LWIP_REASSEMBLY_FRAG
#define LWIP_NETIF_STATUS_CALLBACK 1
#define LWIP_NETIF_LINK_CALLBACK 1
#define RT_LWIP_NETIF_NAMESIZE 6
#define SO_REUSE 1
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
#define LWIP_SO_LINGER 0
#define LWIP_NETIF_LOOPBACK 0
#define RT_LWIP_USING_PING
/* end of Network */
/* Memory protection */
/* end of Memory protection */
/* Utilities */
#define RT_USING_RYM
#define YMODEM_USING_FILE_TRANSFER
#define RT_USING_UTEST
#define UTEST_THR_STACK_SIZE 4096
#define UTEST_THR_PRIORITY 20
#define RT_USING_RESOURCE_ID
#define RT_USING_ADT
#define RT_USING_ADT_AVL
#define RT_USING_ADT_BITMAP
#define RT_USING_ADT_HASHMAP
#define RT_USING_ADT_REF
/* end of Utilities */
/* Using USB legacy version */
/* end of Using USB legacy version */
/* end of RT-Thread Components */
/* RT-Thread Utestcases */
/* end of RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* end of Marvell WiFi */
/* Wiced WiFi */
/* end of Wiced WiFi */
/* CYW43012 WiFi */
/* end of CYW43012 WiFi */
/* BL808 WiFi */
/* end of BL808 WiFi */
/* CYW43439 WiFi */
/* end of CYW43439 WiFi */
/* end of Wi-Fi */
/* IoT Cloud */
/* end of IoT Cloud */
/* end of IoT - internet of things */
/* security packages */
/* end of security packages */
/* language packages */
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* XML: Extensible Markup Language */
/* end of XML: Extensible Markup Language */
/* end of language packages */
/* multimedia packages */
/* LVGL: powerful and easy-to-use embedded GUI library */
/* end of LVGL: powerful and easy-to-use embedded GUI library */
/* u8g2: a monochrome graphic library */
/* end of u8g2: a monochrome graphic library */
/* end of multimedia packages */
/* tools packages */
/* end of tools packages */
/* system packages */
/* enhanced kernel services */
/* end of enhanced kernel services */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* end of acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
/* end of Micrium: Micrium software products porting for RT-Thread */
/* end of system packages */
/* peripheral libraries and drivers */
/* HAL & SDK Drivers */
/* STM32 HAL & SDK Drivers */
/* end of STM32 HAL & SDK Drivers */
/* Infineon HAL Packages */
/* end of Infineon HAL Packages */
/* Kendryte SDK */
/* end of Kendryte SDK */
/* end of HAL & SDK Drivers */
/* sensors drivers */
/* end of sensors drivers */
/* touch drivers */
/* end of touch drivers */
/* end of peripheral libraries and drivers */
/* AI packages */
/* end of AI packages */
/* Signal Processing and Control Algorithm Packages */
/* end of Signal Processing and Control Algorithm Packages */
/* miscellaneous packages */
/* project laboratory */
/* end of project laboratory */
/* samples: kernel and components samples */
/* end of samples: kernel and components samples */
/* entertainment: terminal games and other interesting software packages */
/* end of entertainment: terminal games and other interesting software packages */
/* end of miscellaneous packages */
/* Arduino libraries */
/* Projects and Demos */
/* end of Projects and Demos */
/* Sensors */
/* end of Sensors */
/* Display */
/* end of Display */
/* Timing */
/* end of Timing */
/* Data Processing */
/* end of Data Processing */
/* Data Storage */
/* Communication */
/* end of Communication */
/* Device Control */
/* end of Device Control */
/* Other */
/* end of Other */
/* Signal IO */
/* end of Signal IO */
/* Uncategorized */
/* end of Arduino libraries */
/* end of RT-Thread online packages */
/* Hardware Drivers */
/* On-chip Peripheral Drivers */
#define BSP_USING_IOPAD
#define BSP_USING_UART
#define RT_USING_UART0
#define RT_USING_UART1
#define BSP_USING_SPI
#define RT_USING_SPIM0
#define BSP_USING_GPIO
#define BSP_USING_QSPI
#define RT_USING_QSPI0
#define USING_QSPI_CHANNEL0
#define BSP_USING_ETH
#define RT_LWIP_PBUF_POOL_BUFSIZE 1700
#define BSP_USING_PWM
#define BSP_USING_I2C
#define I2C_USE_MIO
#define RT_USING_MIO0
#define RT_USING_MIO1
#define BSP_USING_SDIF
#define BSP_USING_DC
#define RT_USING_DC_CHANNEL0
#define RT_USING_DC_CHANNEL1
/* end of On-chip Peripheral Drivers */
/* Board extended module Drivers */
/* end of Hardware Drivers */
#define PHYTIUM_ARCH_AARCH32
/* Standalone Setting */
#define TARGET_ARMV8_AARCH32
#define USE_AARCH64_L1_TO_AARCH32
/* Soc configuration */
#define TARGET_PHYTIUMPI
#define SOC_NAME "phytiumpi"
#define SOC_CORE_NUM 4
#define F32BIT_MEMORY_ADDRESS 0x80000000
#define F32BIT_MEMORY_LENGTH 0x80000000
#define F64BIT_MEMORY_ADDRESS 0x2000000000
#define F64BIT_MEMORY_LENGTH 0x800000000
#define TARGET_E2000
#define DEFAULT_DEBUG_PRINT_UART1
/* end of Soc configuration */
/* Board Configuration */
#define BOARD_NAME "firefly"
#define FIREFLY_DEMO_BOARD
/* IO mux configuration when board start up */
/* end of IO mux configuration when board start up */
/* end of Board Configuration */
/* Sdk common configuration */
#define ELOG_LINE_BUF_SIZE 0x100
#define LOG_ERROR
#define USE_DEFAULT_INTERRUPT_CONFIG
#define INTERRUPT_ROLE_MASTER
/* end of Sdk common configuration */
/* end of Standalone Setting */
#endif

View File

@ -46,6 +46,13 @@ SECTIONS
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
/* section information for usb usbh_class_info */
. = ALIGN(4);
__usbh_class_info_start__ = .;
KEEP(*(.usbh_class_info))
. = ALIGN(4);
__usbh_class_info_end__ = .;
} =0
__text_end = .;

View File

@ -35,6 +35,14 @@ ifdef CONFIG_PHYTIUM_RTT_TEST
RTCONFIG := $(RTCONFIG)_test
endif
ifdef CONFIG_RT_CHERRYUSB_HOST_PUSB2
RTCONFIG := $(RTCONFIG)_pusb2_hc
endif
ifdef CONFIG_RT_CHERRYUSB_DEVICE_PUSB2
RTCONFIG := $(RTCONFIG)_pusb2_dc
endif
boot:
make all
cp rtthread_a32.elf /mnt/d/tftpboot
@ -43,7 +51,7 @@ boot:
debug:
@$(OD) -D rtthread_a32.elf > rtthread_a32.asm
@$(OD) -S rtthread_a32.elf > rtthread_a32.dis
all:
@echo "Build started..."
scons -j1024
@ -115,6 +123,12 @@ load_phytium_pi_rtthread:
@cp ./configs/phytium_pi_rtthread.h ./rtconfig.h -f
scons -c
load_phytium_pi_rtthread_pusb2_hc:
@echo "Load configs from ./configs/phytium_pi_rtthread_pusb2_hc"
@cp ./configs/phytium_pi_rtthread_pusb2_hc ./.config -f
@cp ./configs/phytium_pi_rtthread_pusb2_hc.h ./rtconfig.h -f
scons -c
load_phytium_pi_rtsmart:
@echo "Load configs from ./configs/phytium_pi_rtsmart"
@cp ./configs/phytium_pi_rtsmart ./.config -f

View File

@ -153,6 +153,11 @@
#define RT_USING_QSPI
#define RT_USING_PIN
#define RT_USING_KTIME
#define RT_USING_CHERRYUSB
#define RT_CHERRYUSB_HOST
#define RT_CHERRYUSB_HOST_PUSB2
#define RT_CHERRYUSB_HOST_HID
#define RT_CHERRYUSB_HOST_MSC
/* end of Device Drivers */
/* C/C++ and POSIX layer */
@ -373,6 +378,10 @@
/* end of STM32 HAL & SDK Drivers */
/* Infineon HAL Packages */
/* end of Infineon HAL Packages */
/* Kendryte SDK */
/* end of Kendryte SDK */
@ -466,11 +475,7 @@
#define RT_USING_UART0
#define RT_USING_UART1
#define BSP_USING_SPI
#define RT_USING_SPIM2
#define BSP_USING_CAN
#define RT_USING_CANFD
#define RT_USING_CAN0
#define RT_USING_CAN1
#define RT_USING_SPIM0
#define BSP_USING_GPIO
#define BSP_USING_QSPI
#define RT_USING_QSPI0
@ -478,16 +483,11 @@
#define BSP_USING_ETH
#define RT_LWIP_PBUF_POOL_BUFSIZE 1700
#define BSP_USING_PWM
#define RT_USING_PWM2
#define BSP_USING_I2C
#define I2C_USE_MIO
#define RT_USING_MIO15
#define RT_USING_MIO0
#define RT_USING_MIO1
#define BSP_USING_SDIF
#define BSP_USING_SDCARD_FATFS
#define USING_SDIF0
#define USE_SDIF0_EMMC
#define USING_SDIF1
#define USE_SDIF1_TF
#define BSP_USING_DC
#define RT_USING_DC_CHANNEL0
#define RT_USING_DC_CHANNEL1
@ -505,9 +505,8 @@
/* Soc configuration */
#define TARGET_E2000Q
#define SOC_NAME "e2000"
#define TARGET_TYPE_NAME "q"
#define TARGET_PHYTIUMPI
#define SOC_NAME "phytiumpi"
#define SOC_CORE_NUM 4
#define F32BIT_MEMORY_ADDRESS 0x80000000
#define F32BIT_MEMORY_LENGTH 0x80000000
@ -519,8 +518,8 @@
/* Board Configuration */
#define BOARD_NAME "demo"
#define E2000Q_DEMO_BOARD
#define BOARD_NAME "firefly"
#define FIREFLY_DEMO_BOARD
/* IO mux configuration when board start up */

View File

@ -8,7 +8,7 @@ CONFIG_RT_NAME_MAX=16
# CONFIG_RT_USING_NANO is not set
# CONFIG_RT_USING_AMP is not set
CONFIG_RT_USING_SMP=y
CONFIG_RT_CPUS_NR=4
CONFIG_RT_CPUS_NR=2
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32=y
@ -257,7 +257,42 @@ CONFIG_RT_USING_QSPI=y
CONFIG_RT_USING_PIN=y
CONFIG_RT_USING_KTIME=y
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CHERRYUSB is not set
CONFIG_RT_USING_CHERRYUSB=y
# CONFIG_RT_CHERRYUSB_DEVICE is not set
CONFIG_RT_CHERRYUSB_HOST=y
# CONFIG_RT_CHERRYUSB_HOST_CUSTOM is not set
# CONFIG_RT_CHERRYUSB_HOST_EHCI_BL is not set
# CONFIG_RT_CHERRYUSB_HOST_EHCI_HPM is not set
# CONFIG_RT_CHERRYUSB_HOST_EHCI_AIC is not set
# CONFIG_RT_CHERRYUSB_HOST_EHCI_MCX is not set
# CONFIG_RT_CHERRYUSB_HOST_EHCI_NUC980 is not set
# CONFIG_RT_CHERRYUSB_HOST_EHCI_MA35D0 is not set
# CONFIG_RT_CHERRYUSB_HOST_EHCI_CUSTOM is not set
# CONFIG_RT_CHERRYUSB_HOST_DWC2_ST is not set
# CONFIG_RT_CHERRYUSB_HOST_DWC2_ESP is not set
# CONFIG_RT_CHERRYUSB_HOST_DWC2_CUSTOM is not set
# CONFIG_RT_CHERRYUSB_HOST_MUSB_ES is not set
# CONFIG_RT_CHERRYUSB_HOST_MUSB_SUNXI is not set
# CONFIG_RT_CHERRYUSB_HOST_MUSB_BK is not set
# CONFIG_RT_CHERRYUSB_HOST_MUSB_CUSTOM is not set
# CONFIG_RT_CHERRYUSB_HOST_PUSB2 is not set
CONFIG_RT_CHERRYUSB_HOST_XHCI=y
# CONFIG_RT_CHERRYUSB_HOST_CDC_ACM is not set
CONFIG_RT_CHERRYUSB_HOST_HID=y
CONFIG_RT_CHERRYUSB_HOST_MSC=y
# CONFIG_RT_CHERRYUSB_HOST_CDC_ECM is not set
# CONFIG_RT_CHERRYUSB_HOST_CDC_RNDIS is not set
# CONFIG_RT_CHERRYUSB_HOST_CDC_NCM is not set
# CONFIG_RT_CHERRYUSB_HOST_VIDEO is not set
# CONFIG_RT_CHERRYUSB_HOST_AUDIO is not set
# CONFIG_RT_CHERRYUSB_HOST_BLUETOOTH is not set
# CONFIG_RT_CHERRYUSB_HOST_ASIX is not set
# CONFIG_RT_CHERRYUSB_HOST_RTL8152 is not set
# CONFIG_RT_CHERRYUSB_HOST_FTDI is not set
# CONFIG_RT_CHERRYUSB_HOST_CH34X is not set
# CONFIG_RT_CHERRYUSB_HOST_CP210X is not set
# CONFIG_RT_CHERRYUSB_HOST_PL2303 is not set
# CONFIG_RT_CHERRYUSB_HOST_TEMPLATE is not set
# end of Device Drivers
#
@ -335,6 +370,7 @@ CONFIG_NETDEV_USING_IFCONFIG=y
CONFIG_NETDEV_USING_PING=y
CONFIG_NETDEV_USING_NETSTAT=y
CONFIG_NETDEV_USING_AUTO_DEFAULT=y
# CONFIG_NETDEV_USING_LINK_STATUS_CALLBACK is not set
# CONFIG_NETDEV_USING_IPV6 is not set
CONFIG_NETDEV_IPV4=1
CONFIG_NETDEV_IPV6=0
@ -595,6 +631,7 @@ CONFIG_RT_USING_ADT_REF=y
# CONFIG_PKG_USING_JSMN is not set
# CONFIG_PKG_USING_AGILE_JSMN is not set
# CONFIG_PKG_USING_PARSON is not set
# CONFIG_PKG_USING_RYAN_JSON is not set
# end of JSON: JavaScript Object Notation, a lightweight data-interchange format
#
@ -713,6 +750,8 @@ CONFIG_RT_USING_ADT_REF=y
# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
# end of enhanced kernel services
# CONFIG_PKG_USING_AUNITY is not set
#
# acceleration: Assembly language or algorithmic acceleration packages
#
@ -803,12 +842,29 @@ CONFIG_RT_USING_ADT_REF=y
#
# STM32 HAL & SDK Drivers
#
# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set
# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set
# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set
# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set
# CONFIG_PKG_USING_STM32WB55_SDK is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# end of STM32 HAL & SDK Drivers
#
# Infineon HAL Packages
#
# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set
# CONFIG_PKG_USING_INFINEON_CMSIS is not set
# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set
# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set
# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set
# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set
# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set
# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set
# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set
# CONFIG_PKG_USING_INFINEON_USBDEV is not set
# end of Infineon HAL Packages
# CONFIG_PKG_USING_BLUETRUM_SDK is not set
# CONFIG_PKG_USING_EMBARC_BSP is not set
# CONFIG_PKG_USING_ESP_IDF is not set
@ -981,6 +1037,7 @@ CONFIG_RT_USING_ADT_REF=y
# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set
# CONFIG_PKG_USING_BT_MX01 is not set
# CONFIG_PKG_USING_RGPOWER is not set
# CONFIG_PKG_USING_BT_MX02 is not set
# CONFIG_PKG_USING_SPI_TOOLS is not set
# end of peripheral libraries and drivers
@ -1003,6 +1060,7 @@ CONFIG_RT_USING_ADT_REF=y
#
# Signal Processing and Control Algorithm Packages
#
# CONFIG_PKG_USING_APID is not set
# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
# CONFIG_PKG_USING_QPID is not set
# CONFIG_PKG_USING_UKAL is not set
@ -1377,7 +1435,7 @@ CONFIG_BSP_USING_PWM=y
# CONFIG_RT_USING_PWM3 is not set
# CONFIG_RT_USING_PWM4 is not set
# CONFIG_RT_USING_PWM5 is not set
CONFIG_RT_USING_PWM6=y
# CONFIG_RT_USING_PWM6 is not set
# CONFIG_RT_USING_PWM7 is not set
CONFIG_BSP_USING_I2C=y
CONFIG_I2C_USE_MIO=y
@ -1409,8 +1467,6 @@ CONFIG_USE_SDIF1_TF=y
CONFIG_BSP_USING_DC=y
CONFIG_RT_USING_DC_CHANNEL0=y
CONFIG_RT_USING_DC_CHANNEL1=y
# CONFIG_BSP_USING_XHCI is not set
# CONFIG_BSP_USING_PUSB2 is not set
# end of On-chip Peripheral Drivers
#
@ -1421,7 +1477,7 @@ CONFIG_RT_USING_DC_CHANNEL1=y
CONFIG_BSP_USING_GIC=y
CONFIG_BSP_USING_GICV3=y
CONFIG_PHYTIUM_ARCH_AARCH64=y
CONFIG_ARM_SPI_BIND_CPU_ID=2
CONFIG_ARM_SPI_BIND_CPU_ID=0
#
# Standalone Setting
@ -1432,15 +1488,15 @@ CONFIG_TARGET_ARMV8_AARCH64=y
# Soc configuration
#
# CONFIG_TARGET_PHYTIUMPI is not set
CONFIG_TARGET_E2000Q=y
# CONFIG_TARGET_E2000D is not set
# CONFIG_TARGET_E2000Q is not set
CONFIG_TARGET_E2000D=y
# CONFIG_TARGET_E2000S is not set
# CONFIG_TARGET_FT2004 is not set
# CONFIG_TARGET_D2000 is not set
# CONFIG_TARGET_PD2308 is not set
CONFIG_SOC_NAME="e2000"
CONFIG_TARGET_TYPE_NAME="q"
CONFIG_SOC_CORE_NUM=4
CONFIG_TARGET_TYPE_NAME="d"
CONFIG_SOC_CORE_NUM=2
CONFIG_F32BIT_MEMORY_ADDRESS=0x80000000
CONFIG_F32BIT_MEMORY_LENGTH=0x80000000
CONFIG_F64BIT_MEMORY_ADDRESS=0x2000000000
@ -1454,21 +1510,22 @@ CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
#
# Board Configuration
#
CONFIG_E2000D_DEMO_BOARD=y
CONFIG_BOARD_NAME="demo"
#
# IO mux configuration when board start up
#
# CONFIG_USE_SPI_IOPAD is not set
# CONFIG_USE_GPIO_IOPAD is not set
# CONFIG_USE_CAN_IOPAD is not set
# CONFIG_USE_QSPI_IOPAD is not set
# CONFIG_USE_PWM_IOPAD is not set
# CONFIG_USE_ADC_IOPAD is not set
# CONFIG_USE_MIO_IOPAD is not set
# CONFIG_USE_TACHO_IOPAD is not set
# CONFIG_USE_UART_IOPAD is not set
# CONFIG_USE_THIRD_PARTY_IOPAD is not set
CONFIG_E2000Q_DEMO_BOARD=y
#
# IO mux configuration when board start up
#
# end of IO mux configuration when board start up
# CONFIG_CUS_DEMO_BOARD is not set

View File

@ -257,7 +257,41 @@ CONFIG_RT_USING_QSPI=y
CONFIG_RT_USING_PIN=y
CONFIG_RT_USING_KTIME=y
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CHERRYUSB is not set
CONFIG_RT_USING_CHERRYUSB=y
# CONFIG_RT_CHERRYUSB_DEVICE is not set
CONFIG_RT_CHERRYUSB_HOST=y
# CONFIG_RT_CHERRYUSB_HOST_CUSTOM is not set
# CONFIG_RT_CHERRYUSB_HOST_EHCI_BL is not set
# CONFIG_RT_CHERRYUSB_HOST_EHCI_HPM is not set
# CONFIG_RT_CHERRYUSB_HOST_EHCI_AIC is not set
# CONFIG_RT_CHERRYUSB_HOST_EHCI_NUVOTON_NUC980 is not set
# CONFIG_RT_CHERRYUSB_HOST_EHCI_NUVOTON_MA35D0 is not set
# CONFIG_RT_CHERRYUSB_HOST_EHCI_CUSTOM is not set
# CONFIG_RT_CHERRYUSB_HOST_DWC2_ST is not set
# CONFIG_RT_CHERRYUSB_HOST_DWC2_ESP is not set
# CONFIG_RT_CHERRYUSB_HOST_DWC2_CUSTOM is not set
# CONFIG_RT_CHERRYUSB_HOST_MUSB_ES is not set
# CONFIG_RT_CHERRYUSB_HOST_MUSB_SUNXI is not set
# CONFIG_RT_CHERRYUSB_HOST_MUSB_BK is not set
# CONFIG_RT_CHERRYUSB_HOST_MUSB_CUSTOM is not set
# CONFIG_RT_CHERRYUSB_HOST_PUSB2 is not set
CONFIG_RT_CHERRYUSB_HOST_XHCI=y
# CONFIG_RT_CHERRYUSB_HOST_CDC_ACM is not set
CONFIG_RT_CHERRYUSB_HOST_HID=y
CONFIG_RT_CHERRYUSB_HOST_MSC=y
# CONFIG_RT_CHERRYUSB_HOST_CDC_ECM is not set
# CONFIG_RT_CHERRYUSB_HOST_CDC_RNDIS is not set
# CONFIG_RT_CHERRYUSB_HOST_CDC_NCM is not set
# CONFIG_RT_CHERRYUSB_HOST_VIDEO is not set
# CONFIG_RT_CHERRYUSB_HOST_AUDIO is not set
# CONFIG_RT_CHERRYUSB_HOST_BLUETOOTH is not set
# CONFIG_RT_CHERRYUSB_HOST_ASIX is not set
# CONFIG_RT_CHERRYUSB_HOST_RTL8152 is not set
# CONFIG_RT_CHERRYUSB_HOST_FTDI is not set
# CONFIG_RT_CHERRYUSB_HOST_CH34X is not set
# CONFIG_RT_CHERRYUSB_HOST_CP210X is not set
# CONFIG_RT_CHERRYUSB_HOST_PL2303 is not set
# CONFIG_CHERRYUSB_HOST_TEMPLATE is not set
# end of Device Drivers
#
@ -335,6 +369,7 @@ CONFIG_NETDEV_USING_IFCONFIG=y
CONFIG_NETDEV_USING_PING=y
CONFIG_NETDEV_USING_NETSTAT=y
CONFIG_NETDEV_USING_AUTO_DEFAULT=y
# CONFIG_NETDEV_USING_LINK_STATUS_CALLBACK is not set
# CONFIG_NETDEV_USING_IPV6 is not set
CONFIG_NETDEV_IPV4=1
CONFIG_NETDEV_IPV6=0
@ -595,6 +630,7 @@ CONFIG_RT_USING_ADT_REF=y
# CONFIG_PKG_USING_JSMN is not set
# CONFIG_PKG_USING_AGILE_JSMN is not set
# CONFIG_PKG_USING_PARSON is not set
# CONFIG_PKG_USING_RYAN_JSON is not set
# end of JSON: JavaScript Object Notation, a lightweight data-interchange format
#
@ -713,6 +749,8 @@ CONFIG_RT_USING_ADT_REF=y
# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
# end of enhanced kernel services
# CONFIG_PKG_USING_AUNITY is not set
#
# acceleration: Assembly language or algorithmic acceleration packages
#
@ -803,12 +841,29 @@ CONFIG_RT_USING_ADT_REF=y
#
# STM32 HAL & SDK Drivers
#
# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set
# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set
# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set
# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set
# CONFIG_PKG_USING_STM32WB55_SDK is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# end of STM32 HAL & SDK Drivers
#
# Infineon HAL Packages
#
# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set
# CONFIG_PKG_USING_INFINEON_CMSIS is not set
# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set
# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set
# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set
# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set
# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set
# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set
# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set
# CONFIG_PKG_USING_INFINEON_USBDEV is not set
# end of Infineon HAL Packages
# CONFIG_PKG_USING_BLUETRUM_SDK is not set
# CONFIG_PKG_USING_EMBARC_BSP is not set
# CONFIG_PKG_USING_ESP_IDF is not set
@ -981,6 +1036,7 @@ CONFIG_RT_USING_ADT_REF=y
# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set
# CONFIG_PKG_USING_BT_MX01 is not set
# CONFIG_PKG_USING_RGPOWER is not set
# CONFIG_PKG_USING_BT_MX02 is not set
# CONFIG_PKG_USING_SPI_TOOLS is not set
# end of peripheral libraries and drivers
@ -1003,6 +1059,7 @@ CONFIG_RT_USING_ADT_REF=y
#
# Signal Processing and Control Algorithm Packages
#
# CONFIG_PKG_USING_APID is not set
# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
# CONFIG_PKG_USING_QPID is not set
# CONFIG_PKG_USING_UKAL is not set
@ -1377,7 +1434,7 @@ CONFIG_BSP_USING_PWM=y
# CONFIG_RT_USING_PWM3 is not set
# CONFIG_RT_USING_PWM4 is not set
# CONFIG_RT_USING_PWM5 is not set
CONFIG_RT_USING_PWM6=y
# CONFIG_RT_USING_PWM6 is not set
# CONFIG_RT_USING_PWM7 is not set
CONFIG_BSP_USING_I2C=y
CONFIG_I2C_USE_MIO=y
@ -1409,8 +1466,6 @@ CONFIG_USE_SDIF1_TF=y
CONFIG_BSP_USING_DC=y
CONFIG_RT_USING_DC_CHANNEL0=y
CONFIG_RT_USING_DC_CHANNEL1=y
# CONFIG_BSP_USING_XHCI is not set
# CONFIG_BSP_USING_PUSB2 is not set
# end of On-chip Peripheral Drivers
#

View File

@ -163,6 +163,11 @@
#define RT_USING_QSPI
#define RT_USING_PIN
#define RT_USING_KTIME
#define RT_USING_CHERRYUSB
#define RT_CHERRYUSB_HOST
#define RT_CHERRYUSB_HOST_XHCI
#define RT_CHERRYUSB_HOST_HID
#define RT_CHERRYUSB_HOST_MSC
/* end of Device Drivers */
/* C/C++ and POSIX layer */
@ -373,6 +378,10 @@
/* end of STM32 HAL & SDK Drivers */
/* Infineon HAL Packages */
/* end of Infineon HAL Packages */
/* Kendryte SDK */
/* end of Kendryte SDK */
@ -481,7 +490,6 @@
#define BSP_USING_ETH
#define RT_LWIP_PBUF_POOL_BUFSIZE 1700
#define BSP_USING_PWM
#define RT_USING_PWM6
#define BSP_USING_I2C
#define I2C_USE_MIO
#define RT_USING_MIO15

File diff suppressed because it is too large Load Diff

View File

@ -0,0 +1,551 @@
#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* RT-Thread Kernel */
#define RT_NAME_MAX 16
#define RT_USING_SMP
#define RT_CPUS_NR 2
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 8192
#define SYSTEM_THREAD_STACK_SIZE 8192
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 8192
/* kservice optimization */
/* end of kservice optimization */
/* klibc optimization */
#define RT_KLIBC_USING_PRINTF_LONGLONG
/* end of klibc optimization */
#define RT_USING_DEBUG
#define RT_DEBUGING_ASSERT
#define RT_DEBUGING_COLOR
#define RT_USING_OVERFLOW_CHECK
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* end of Inter-Thread communication */
/* Memory Management */
#define RT_PAGE_MAX_ORDER 16
#define RT_USING_SLAB
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SLAB_AS_HEAP
#define RT_USING_HEAP_ISR
#define RT_USING_HEAP
/* end of Memory Management */
#define RT_USING_DEVICE
#define RT_USING_SCHED_THREAD_CTX
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x50200
#define RT_USING_STDC_ATOMIC
#define RT_BACKTRACE_LEVEL_MAX_NR 32
/* end of RT-Thread Kernel */
/* AArch64 Architecture Configuration */
#define ARCH_TEXT_OFFSET 0x80000
#define ARCH_RAM_OFFSET 0x80000000
#define ARCH_SECONDARY_CPU_STACK_SIZE 4096
#define ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS
#define ARCH_HEAP_SIZE 0x4000000
#define ARCH_INIT_PAGE_SIZE 0x200000
/* end of AArch64 Architecture Configuration */
#define ARCH_CPU_64BIT
#define RT_USING_CACHE
#define RT_USING_HW_ATOMIC
#define ARCH_ARM_BOOTWITH_FLUSH_CACHE
#define RT_USING_CPU_FFS
#define ARCH_MM_MMU
#define ARCH_ARM
#define ARCH_ARM_MMU
#define ARCH_ARMV8
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 8192
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
#define FINSH_USING_OPTION_COMPLETION
/* DFS: device virtual file system */
#define RT_USING_DFS
#define DFS_USING_POSIX
#define DFS_USING_WORKDIR
#define DFS_FD_MAX 16
#define RT_USING_DFS_V1
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_LFN_UNICODE_0
#define RT_DFS_ELM_LFN_UNICODE 0
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
#define RT_DFS_ELM_REENTRANT
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
/* end of elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_RAMFS
/* end of DFS: device virtual file system */
/* Device Drivers */
#define RT_USING_DEV_BUS
#define RT_USING_DEVICE_IPC
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 8192
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_CAN
#define RT_CAN_USING_HDR
#define RT_CAN_USING_CANFD
#define RT_USING_I2C
#define RT_USING_I2C_BITOPS
#define RT_USING_NULL
#define RT_USING_ZERO
#define RT_USING_RANDOM
#define RT_USING_PWM
#define RT_USING_RTC
#define RT_USING_SDIO
#define RT_SDIO_STACK_SIZE 8192
#define RT_SDIO_THREAD_PRIORITY 15
#define RT_MMCSD_STACK_SIZE 8192
#define RT_MMCSD_THREAD_PREORITY 22
#define RT_MMCSD_MAX_PARTITION 16
#define RT_USING_SPI
#define RT_USING_QSPI
#define RT_USING_PIN
#define RT_USING_KTIME
#define RT_USING_CHERRYUSB
#define RT_CHERRYUSB_DEVICE
#define RT_CHERRYUSB_DEVICE_SPEED_HS
#define RT_CHERRYUSB_DEVICE_PUSB2
#define RT_CHERRYUSB_DEVICE_MSC
#define RT_CHERRYUSB_DEVICE_TEMPLATE_MSC
/* end of Device Drivers */
/* C/C++ and POSIX layer */
/* ISO-ANSI C layer */
/* Timezone and Daylight Saving Time */
#define RT_LIBC_USING_LIGHT_TZ_DST
#define RT_LIBC_TZ_DEFAULT_HOUR 8
#define RT_LIBC_TZ_DEFAULT_MIN 0
#define RT_LIBC_TZ_DEFAULT_SEC 0
/* end of Timezone and Daylight Saving Time */
/* end of ISO-ANSI C layer */
/* POSIX (Portable Operating System Interface) layer */
#define RT_USING_POSIX_FS
#define RT_USING_POSIX_DEVIO
#define RT_USING_POSIX_STDIO
#define RT_USING_POSIX_TERMIOS
#define RT_USING_POSIX_DELAY
#define RT_USING_POSIX_CLOCK
#define RT_USING_POSIX_TIMER
/* Interprocess Communication (IPC) */
/* Socket is in the 'Network' category */
/* end of Interprocess Communication (IPC) */
/* end of POSIX (Portable Operating System Interface) layer */
/* end of C/C++ and POSIX layer */
/* Network */
#define RT_USING_SAL
#define SAL_INTERNET_CHECK
/* Docking with protocol stacks */
#define SAL_USING_LWIP
/* end of Docking with protocol stacks */
#define SAL_USING_POSIX
#define RT_USING_NETDEV
#define NETDEV_USING_IFCONFIG
#define NETDEV_USING_PING
#define NETDEV_USING_NETSTAT
#define NETDEV_USING_AUTO_DEFAULT
#define NETDEV_IPV4 1
#define NETDEV_IPV6 0
#define RT_USING_LWIP
#define RT_USING_LWIP212
#define RT_USING_LWIP_VER_NUM 0x20102
#define RT_LWIP_MEM_ALIGNMENT 64
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
#define RT_LWIP_DNS
/* Static IPv4 Address */
#define RT_LWIP_IPADDR "192.168.4.10"
#define RT_LWIP_GWADDR "192.168.4.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
/* end of Static IPv4 Address */
#define RT_LWIP_UDP
#define RT_LWIP_TCP
#define RT_LWIP_RAW
#define RT_MEMP_NUM_NETCONN 8
#define RT_LWIP_PBUF_NUM 512
#define RT_LWIP_RAW_PCB_NUM 4
#define RT_LWIP_UDP_PCB_NUM 4
#define RT_LWIP_TCP_PCB_NUM 4
#define RT_LWIP_TCP_SEG_NUM 40
#define RT_LWIP_TCP_SND_BUF 8196
#define RT_LWIP_TCP_WND 8196
#define RT_LWIP_TCPTHREAD_PRIORITY 16
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_STACKSIZE 16184
#define RT_LWIP_ETHTHREAD_PRIORITY 12
#define RT_LWIP_ETHTHREAD_STACKSIZE 8192
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
#define RT_LWIP_REASSEMBLY_FRAG
#define LWIP_NETIF_STATUS_CALLBACK 1
#define LWIP_NETIF_LINK_CALLBACK 1
#define RT_LWIP_NETIF_NAMESIZE 6
#define SO_REUSE 1
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
#define LWIP_SO_LINGER 0
#define LWIP_NETIF_LOOPBACK 0
#define RT_LWIP_USING_PING
/* end of Network */
/* Memory protection */
/* end of Memory protection */
/* Utilities */
#define RT_USING_RYM
#define YMODEM_USING_FILE_TRANSFER
#define RT_USING_RESOURCE_ID
#define RT_USING_ADT
#define RT_USING_ADT_AVL
#define RT_USING_ADT_BITMAP
#define RT_USING_ADT_HASHMAP
#define RT_USING_ADT_REF
/* end of Utilities */
/* Using USB legacy version */
/* end of Using USB legacy version */
/* end of RT-Thread Components */
/* RT-Thread Utestcases */
/* end of RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* end of Marvell WiFi */
/* Wiced WiFi */
/* end of Wiced WiFi */
/* CYW43012 WiFi */
/* end of CYW43012 WiFi */
/* BL808 WiFi */
/* end of BL808 WiFi */
/* CYW43439 WiFi */
/* end of CYW43439 WiFi */
/* end of Wi-Fi */
/* IoT Cloud */
/* end of IoT Cloud */
/* end of IoT - internet of things */
/* security packages */
/* end of security packages */
/* language packages */
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* XML: Extensible Markup Language */
/* end of XML: Extensible Markup Language */
/* end of language packages */
/* multimedia packages */
/* LVGL: powerful and easy-to-use embedded GUI library */
/* end of LVGL: powerful and easy-to-use embedded GUI library */
/* u8g2: a monochrome graphic library */
/* end of u8g2: a monochrome graphic library */
/* end of multimedia packages */
/* tools packages */
/* end of tools packages */
/* system packages */
/* enhanced kernel services */
/* end of enhanced kernel services */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* end of acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
/* end of Micrium: Micrium software products porting for RT-Thread */
/* end of system packages */
/* peripheral libraries and drivers */
/* HAL & SDK Drivers */
/* STM32 HAL & SDK Drivers */
/* end of STM32 HAL & SDK Drivers */
/* Infineon HAL Packages */
/* end of Infineon HAL Packages */
/* Kendryte SDK */
/* end of Kendryte SDK */
/* end of HAL & SDK Drivers */
/* sensors drivers */
/* end of sensors drivers */
/* touch drivers */
/* end of touch drivers */
/* end of peripheral libraries and drivers */
/* AI packages */
/* end of AI packages */
/* Signal Processing and Control Algorithm Packages */
/* end of Signal Processing and Control Algorithm Packages */
/* miscellaneous packages */
/* project laboratory */
/* end of project laboratory */
/* samples: kernel and components samples */
#define PKG_USING_KERNEL_SAMPLES
#define PKG_USING_KERNEL_SAMPLES_LATEST_VERSION
#define PKG_USING_KERNEL_SAMPLES_EN
/* end of samples: kernel and components samples */
/* entertainment: terminal games and other interesting software packages */
/* end of entertainment: terminal games and other interesting software packages */
/* end of miscellaneous packages */
/* Arduino libraries */
/* Projects and Demos */
/* end of Projects and Demos */
/* Sensors */
/* end of Sensors */
/* Display */
/* end of Display */
/* Timing */
/* end of Timing */
/* Data Processing */
/* end of Data Processing */
/* Data Storage */
/* Communication */
/* end of Communication */
/* Device Control */
/* end of Device Control */
/* Other */
/* end of Other */
/* Signal IO */
/* end of Signal IO */
/* Uncategorized */
/* end of Arduino libraries */
/* end of RT-Thread online packages */
/* Hardware Drivers */
/* On-chip Peripheral Drivers */
#define BSP_USING_IOPAD
#define BSP_USING_UART
#define RT_USING_UART0
#define RT_USING_UART1
#define BSP_USING_SPI
#define RT_USING_SPIM2
#define BSP_USING_CAN
#define RT_USING_CANFD
#define RT_USING_CAN0
#define RT_USING_CAN1
#define BSP_USING_GPIO
#define BSP_USING_QSPI
#define RT_USING_QSPI0
#define USING_QSPI_CHANNEL0
#define BSP_USING_ETH
#define RT_LWIP_PBUF_POOL_BUFSIZE 1700
#define BSP_USING_PWM
#define BSP_USING_I2C
#define I2C_USE_MIO
#define RT_USING_MIO15
#define BSP_USING_SDIF
#define BSP_USING_SDCARD_FATFS
#define USING_SDIF0
#define USE_SDIF0_EMMC
#define USING_SDIF1
#define USE_SDIF1_TF
#define BSP_USING_DC
#define RT_USING_DC_CHANNEL0
#define RT_USING_DC_CHANNEL1
/* end of On-chip Peripheral Drivers */
/* Board extended module Drivers */
/* end of Hardware Drivers */
#define BSP_USING_GIC
#define BSP_USING_GICV3
#define PHYTIUM_ARCH_AARCH64
#define ARM_SPI_BIND_CPU_ID 0
/* Standalone Setting */
#define TARGET_ARMV8_AARCH64
/* Soc configuration */
#define TARGET_E2000D
#define SOC_NAME "e2000"
#define TARGET_TYPE_NAME "d"
#define SOC_CORE_NUM 2
#define F32BIT_MEMORY_ADDRESS 0x80000000
#define F32BIT_MEMORY_LENGTH 0x80000000
#define F64BIT_MEMORY_ADDRESS 0x2000000000
#define F64BIT_MEMORY_LENGTH 0x800000000
#define TARGET_E2000
#define DEFAULT_DEBUG_PRINT_UART1
/* end of Soc configuration */
/* Board Configuration */
#define E2000D_DEMO_BOARD
#define BOARD_NAME "demo"
/* IO mux configuration when board start up */
/* end of IO mux configuration when board start up */
/* end of Board Configuration */
/* Sdk common configuration */
#define ELOG_LINE_BUF_SIZE 0x100
#define LOG_DEBUG
/* end of Sdk common configuration */
/* end of Standalone Setting */
#endif

View File

@ -257,7 +257,41 @@ CONFIG_RT_USING_QSPI=y
CONFIG_RT_USING_PIN=y
CONFIG_RT_USING_KTIME=y
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CHERRYUSB is not set
CONFIG_RT_USING_CHERRYUSB=y
# CONFIG_RT_CHERRYUSB_DEVICE is not set
CONFIG_RT_CHERRYUSB_HOST=y
# CONFIG_RT_CHERRYUSB_HOST_CUSTOM is not set
# CONFIG_RT_CHERRYUSB_HOST_EHCI_BL is not set
# CONFIG_RT_CHERRYUSB_HOST_EHCI_HPM is not set
# CONFIG_RT_CHERRYUSB_HOST_EHCI_AIC is not set
# CONFIG_RT_CHERRYUSB_HOST_EHCI_NUVOTON_NUC980 is not set
# CONFIG_RT_CHERRYUSB_HOST_EHCI_NUVOTON_MA35D0 is not set
# CONFIG_RT_CHERRYUSB_HOST_EHCI_CUSTOM is not set
# CONFIG_RT_CHERRYUSB_HOST_DWC2_ST is not set
# CONFIG_RT_CHERRYUSB_HOST_DWC2_ESP is not set
# CONFIG_RT_CHERRYUSB_HOST_DWC2_CUSTOM is not set
# CONFIG_RT_CHERRYUSB_HOST_MUSB_ES is not set
# CONFIG_RT_CHERRYUSB_HOST_MUSB_SUNXI is not set
# CONFIG_RT_CHERRYUSB_HOST_MUSB_BK is not set
# CONFIG_RT_CHERRYUSB_HOST_MUSB_CUSTOM is not set
# CONFIG_RT_CHERRYUSB_HOST_PUSB2 is not set
CONFIG_RT_CHERRYUSB_HOST_XHCI=y
# CONFIG_RT_CHERRYUSB_HOST_CDC_ACM is not set
CONFIG_RT_CHERRYUSB_HOST_HID=y
CONFIG_RT_CHERRYUSB_HOST_MSC=y
# CONFIG_RT_CHERRYUSB_HOST_CDC_ECM is not set
# CONFIG_RT_CHERRYUSB_HOST_CDC_RNDIS is not set
# CONFIG_RT_CHERRYUSB_HOST_CDC_NCM is not set
# CONFIG_RT_CHERRYUSB_HOST_VIDEO is not set
# CONFIG_RT_CHERRYUSB_HOST_AUDIO is not set
# CONFIG_RT_CHERRYUSB_HOST_BLUETOOTH is not set
# CONFIG_RT_CHERRYUSB_HOST_ASIX is not set
# CONFIG_RT_CHERRYUSB_HOST_RTL8152 is not set
# CONFIG_RT_CHERRYUSB_HOST_FTDI is not set
# CONFIG_RT_CHERRYUSB_HOST_CH34X is not set
# CONFIG_RT_CHERRYUSB_HOST_CP210X is not set
# CONFIG_RT_CHERRYUSB_HOST_PL2303 is not set
# CONFIG_CHERRYUSB_HOST_TEMPLATE is not set
# end of Device Drivers
#
@ -335,6 +369,7 @@ CONFIG_NETDEV_USING_IFCONFIG=y
CONFIG_NETDEV_USING_PING=y
CONFIG_NETDEV_USING_NETSTAT=y
CONFIG_NETDEV_USING_AUTO_DEFAULT=y
# CONFIG_NETDEV_USING_LINK_STATUS_CALLBACK is not set
# CONFIG_NETDEV_USING_IPV6 is not set
CONFIG_NETDEV_IPV4=1
CONFIG_NETDEV_IPV6=0
@ -595,6 +630,7 @@ CONFIG_RT_USING_ADT_REF=y
# CONFIG_PKG_USING_JSMN is not set
# CONFIG_PKG_USING_AGILE_JSMN is not set
# CONFIG_PKG_USING_PARSON is not set
# CONFIG_PKG_USING_RYAN_JSON is not set
# end of JSON: JavaScript Object Notation, a lightweight data-interchange format
#
@ -713,6 +749,8 @@ CONFIG_RT_USING_ADT_REF=y
# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
# end of enhanced kernel services
# CONFIG_PKG_USING_AUNITY is not set
#
# acceleration: Assembly language or algorithmic acceleration packages
#
@ -803,12 +841,29 @@ CONFIG_RT_USING_ADT_REF=y
#
# STM32 HAL & SDK Drivers
#
# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set
# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set
# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set
# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set
# CONFIG_PKG_USING_STM32WB55_SDK is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# end of STM32 HAL & SDK Drivers
#
# Infineon HAL Packages
#
# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set
# CONFIG_PKG_USING_INFINEON_CMSIS is not set
# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set
# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set
# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set
# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set
# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set
# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set
# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set
# CONFIG_PKG_USING_INFINEON_USBDEV is not set
# end of Infineon HAL Packages
# CONFIG_PKG_USING_BLUETRUM_SDK is not set
# CONFIG_PKG_USING_EMBARC_BSP is not set
# CONFIG_PKG_USING_ESP_IDF is not set
@ -981,6 +1036,7 @@ CONFIG_RT_USING_ADT_REF=y
# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set
# CONFIG_PKG_USING_BT_MX01 is not set
# CONFIG_PKG_USING_RGPOWER is not set
# CONFIG_PKG_USING_BT_MX02 is not set
# CONFIG_PKG_USING_SPI_TOOLS is not set
# end of peripheral libraries and drivers
@ -1003,6 +1059,7 @@ CONFIG_RT_USING_ADT_REF=y
#
# Signal Processing and Control Algorithm Packages
#
# CONFIG_PKG_USING_APID is not set
# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
# CONFIG_PKG_USING_QPID is not set
# CONFIG_PKG_USING_UKAL is not set
@ -1369,7 +1426,7 @@ CONFIG_RT_LWIP_PBUF_POOL_BUFSIZE=1700
CONFIG_BSP_USING_PWM=y
# CONFIG_RT_USING_PWM0 is not set
# CONFIG_RT_USING_PWM1 is not set
CONFIG_RT_USING_PWM2=y
# CONFIG_RT_USING_PWM2 is not set
# CONFIG_RT_USING_PWM3 is not set
# CONFIG_RT_USING_PWM4 is not set
# CONFIG_RT_USING_PWM5 is not set
@ -1403,8 +1460,6 @@ CONFIG_USE_SDIF1_TF=y
CONFIG_BSP_USING_DC=y
CONFIG_RT_USING_DC_CHANNEL0=y
CONFIG_RT_USING_DC_CHANNEL1=y
# CONFIG_BSP_USING_XHCI is not set
# CONFIG_BSP_USING_PUSB2 is not set
# end of On-chip Peripheral Drivers
#

View File

@ -163,6 +163,11 @@
#define RT_USING_QSPI
#define RT_USING_PIN
#define RT_USING_KTIME
#define RT_USING_CHERRYUSB
#define RT_CHERRYUSB_HOST
#define RT_CHERRYUSB_HOST_XHCI
#define RT_CHERRYUSB_HOST_HID
#define RT_CHERRYUSB_HOST_MSC
/* end of Device Drivers */
/* C/C++ and POSIX layer */
@ -373,6 +378,10 @@
/* end of STM32 HAL & SDK Drivers */
/* Infineon HAL Packages */
/* end of Infineon HAL Packages */
/* Kendryte SDK */
/* end of Kendryte SDK */
@ -477,7 +486,6 @@
#define BSP_USING_ETH
#define RT_LWIP_PBUF_POOL_BUFSIZE 1700
#define BSP_USING_PWM
#define RT_USING_PWM2
#define BSP_USING_I2C
#define I2C_USE_MIO
#define RT_USING_MIO0

File diff suppressed because it is too large Load Diff

View File

@ -0,0 +1,546 @@
#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* RT-Thread Kernel */
#define RT_NAME_MAX 16
#define RT_USING_SMP
#define RT_CPUS_NR 4
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 8192
#define SYSTEM_THREAD_STACK_SIZE 8192
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 8192
/* kservice optimization */
/* end of kservice optimization */
/* klibc optimization */
#define RT_KLIBC_USING_PRINTF_LONGLONG
/* end of klibc optimization */
#define RT_USING_DEBUG
#define RT_DEBUGING_ASSERT
#define RT_DEBUGING_COLOR
#define RT_DEBUGING_CONTEXT
#define RT_USING_OVERFLOW_CHECK
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* end of Inter-Thread communication */
/* Memory Management */
#define RT_PAGE_MAX_ORDER 16
#define RT_USING_SLAB
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SLAB_AS_HEAP
#define RT_USING_HEAP_ISR
#define RT_USING_HEAP
/* end of Memory Management */
#define RT_USING_DEVICE
#define RT_USING_SCHED_THREAD_CTX
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x50200
#define RT_USING_STDC_ATOMIC
#define RT_BACKTRACE_LEVEL_MAX_NR 32
/* end of RT-Thread Kernel */
/* AArch64 Architecture Configuration */
#define ARCH_TEXT_OFFSET 0x80000
#define ARCH_RAM_OFFSET 0x80000000
#define ARCH_SECONDARY_CPU_STACK_SIZE 4096
#define ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS
#define ARCH_HEAP_SIZE 0x4000000
#define ARCH_INIT_PAGE_SIZE 0x200000
/* end of AArch64 Architecture Configuration */
#define ARCH_CPU_64BIT
#define RT_USING_CACHE
#define RT_USING_HW_ATOMIC
#define ARCH_ARM_BOOTWITH_FLUSH_CACHE
#define RT_USING_CPU_FFS
#define ARCH_MM_MMU
#define ARCH_ARM
#define ARCH_ARM_MMU
#define ARCH_ARMV8
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 8192
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
#define FINSH_USING_OPTION_COMPLETION
/* DFS: device virtual file system */
#define RT_USING_DFS
#define DFS_USING_POSIX
#define DFS_USING_WORKDIR
#define DFS_FD_MAX 16
#define RT_USING_DFS_V1
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_LFN_UNICODE_0
#define RT_DFS_ELM_LFN_UNICODE 0
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
#define RT_DFS_ELM_REENTRANT
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
/* end of elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_RAMFS
/* end of DFS: device virtual file system */
/* Device Drivers */
#define RT_USING_DEV_BUS
#define RT_USING_DEVICE_IPC
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 8192
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_CAN
#define RT_CAN_USING_CANFD
#define RT_USING_I2C
#define RT_USING_I2C_BITOPS
#define RT_USING_NULL
#define RT_USING_ZERO
#define RT_USING_RANDOM
#define RT_USING_PWM
#define RT_USING_RTC
#define RT_USING_SDIO
#define RT_SDIO_STACK_SIZE 8192
#define RT_SDIO_THREAD_PRIORITY 15
#define RT_MMCSD_STACK_SIZE 8192
#define RT_MMCSD_THREAD_PREORITY 22
#define RT_MMCSD_MAX_PARTITION 16
#define RT_USING_SPI
#define RT_USING_QSPI
#define RT_USING_PIN
#define RT_USING_KTIME
#define RT_USING_CHERRYUSB
#define RT_CHERRYUSB_HOST
#define RT_CHERRYUSB_HOST_PUSB2
#define RT_CHERRYUSB_HOST_HID
#define RT_CHERRYUSB_HOST_MSC
/* end of Device Drivers */
/* C/C++ and POSIX layer */
/* ISO-ANSI C layer */
/* Timezone and Daylight Saving Time */
#define RT_LIBC_USING_LIGHT_TZ_DST
#define RT_LIBC_TZ_DEFAULT_HOUR 8
#define RT_LIBC_TZ_DEFAULT_MIN 0
#define RT_LIBC_TZ_DEFAULT_SEC 0
/* end of Timezone and Daylight Saving Time */
/* end of ISO-ANSI C layer */
/* POSIX (Portable Operating System Interface) layer */
#define RT_USING_POSIX_FS
#define RT_USING_POSIX_DEVIO
#define RT_USING_POSIX_STDIO
#define RT_USING_POSIX_TERMIOS
#define RT_USING_POSIX_DELAY
#define RT_USING_POSIX_CLOCK
#define RT_USING_POSIX_TIMER
/* Interprocess Communication (IPC) */
/* Socket is in the 'Network' category */
/* end of Interprocess Communication (IPC) */
/* end of POSIX (Portable Operating System Interface) layer */
/* end of C/C++ and POSIX layer */
/* Network */
#define RT_USING_SAL
#define SAL_INTERNET_CHECK
/* Docking with protocol stacks */
#define SAL_USING_LWIP
/* end of Docking with protocol stacks */
#define SAL_USING_POSIX
#define RT_USING_NETDEV
#define NETDEV_USING_IFCONFIG
#define NETDEV_USING_PING
#define NETDEV_USING_NETSTAT
#define NETDEV_USING_AUTO_DEFAULT
#define NETDEV_IPV4 1
#define NETDEV_IPV6 0
#define RT_USING_LWIP
#define RT_USING_LWIP212
#define RT_USING_LWIP_VER_NUM 0x20102
#define RT_LWIP_MEM_ALIGNMENT 64
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
#define RT_LWIP_DNS
/* Static IPv4 Address */
#define RT_LWIP_IPADDR "192.168.4.10"
#define RT_LWIP_GWADDR "192.168.4.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
/* end of Static IPv4 Address */
#define RT_LWIP_UDP
#define RT_LWIP_TCP
#define RT_LWIP_RAW
#define RT_MEMP_NUM_NETCONN 8
#define RT_LWIP_PBUF_NUM 512
#define RT_LWIP_RAW_PCB_NUM 4
#define RT_LWIP_UDP_PCB_NUM 4
#define RT_LWIP_TCP_PCB_NUM 4
#define RT_LWIP_TCP_SEG_NUM 40
#define RT_LWIP_TCP_SND_BUF 8196
#define RT_LWIP_TCP_WND 8196
#define RT_LWIP_TCPTHREAD_PRIORITY 16
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_STACKSIZE 16184
#define RT_LWIP_ETHTHREAD_PRIORITY 12
#define RT_LWIP_ETHTHREAD_STACKSIZE 8192
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
#define RT_LWIP_REASSEMBLY_FRAG
#define LWIP_NETIF_STATUS_CALLBACK 1
#define LWIP_NETIF_LINK_CALLBACK 1
#define RT_LWIP_NETIF_NAMESIZE 6
#define SO_REUSE 1
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
#define LWIP_SO_LINGER 0
#define LWIP_NETIF_LOOPBACK 0
#define RT_LWIP_USING_PING
/* end of Network */
/* Memory protection */
/* end of Memory protection */
/* Utilities */
#define RT_USING_RYM
#define YMODEM_USING_FILE_TRANSFER
#define RT_USING_RESOURCE_ID
#define RT_USING_ADT
#define RT_USING_ADT_AVL
#define RT_USING_ADT_BITMAP
#define RT_USING_ADT_HASHMAP
#define RT_USING_ADT_REF
/* end of Utilities */
/* Using USB legacy version */
/* end of Using USB legacy version */
/* end of RT-Thread Components */
/* RT-Thread Utestcases */
/* end of RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* end of Marvell WiFi */
/* Wiced WiFi */
/* end of Wiced WiFi */
/* CYW43012 WiFi */
/* end of CYW43012 WiFi */
/* BL808 WiFi */
/* end of BL808 WiFi */
/* CYW43439 WiFi */
/* end of CYW43439 WiFi */
/* end of Wi-Fi */
/* IoT Cloud */
/* end of IoT Cloud */
/* end of IoT - internet of things */
/* security packages */
/* end of security packages */
/* language packages */
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* XML: Extensible Markup Language */
/* end of XML: Extensible Markup Language */
/* end of language packages */
/* multimedia packages */
/* LVGL: powerful and easy-to-use embedded GUI library */
/* end of LVGL: powerful and easy-to-use embedded GUI library */
/* u8g2: a monochrome graphic library */
/* end of u8g2: a monochrome graphic library */
/* end of multimedia packages */
/* tools packages */
/* end of tools packages */
/* system packages */
/* enhanced kernel services */
/* end of enhanced kernel services */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* end of acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
/* end of Micrium: Micrium software products porting for RT-Thread */
/* end of system packages */
/* peripheral libraries and drivers */
/* HAL & SDK Drivers */
/* STM32 HAL & SDK Drivers */
/* end of STM32 HAL & SDK Drivers */
/* Infineon HAL Packages */
/* end of Infineon HAL Packages */
/* Kendryte SDK */
/* end of Kendryte SDK */
/* end of HAL & SDK Drivers */
/* sensors drivers */
/* end of sensors drivers */
/* touch drivers */
/* end of touch drivers */
/* end of peripheral libraries and drivers */
/* AI packages */
/* end of AI packages */
/* Signal Processing and Control Algorithm Packages */
/* end of Signal Processing and Control Algorithm Packages */
/* miscellaneous packages */
/* project laboratory */
/* end of project laboratory */
/* samples: kernel and components samples */
#define PKG_USING_KERNEL_SAMPLES
#define PKG_USING_KERNEL_SAMPLES_LATEST_VERSION
#define PKG_USING_KERNEL_SAMPLES_EN
/* end of samples: kernel and components samples */
/* entertainment: terminal games and other interesting software packages */
/* end of entertainment: terminal games and other interesting software packages */
/* end of miscellaneous packages */
/* Arduino libraries */
/* Projects and Demos */
/* end of Projects and Demos */
/* Sensors */
/* end of Sensors */
/* Display */
/* end of Display */
/* Timing */
/* end of Timing */
/* Data Processing */
/* end of Data Processing */
/* Data Storage */
/* Communication */
/* end of Communication */
/* Device Control */
/* end of Device Control */
/* Other */
/* end of Other */
/* Signal IO */
/* end of Signal IO */
/* Uncategorized */
/* end of Arduino libraries */
/* end of RT-Thread online packages */
/* Hardware Drivers */
/* On-chip Peripheral Drivers */
#define BSP_USING_IOPAD
#define BSP_USING_UART
#define RT_USING_UART0
#define RT_USING_UART1
#define BSP_USING_SPI
#define RT_USING_SPIM0
#define BSP_USING_GPIO
#define BSP_USING_QSPI
#define RT_USING_QSPI0
#define USING_QSPI_CHANNEL0
#define BSP_USING_ETH
#define RT_LWIP_PBUF_POOL_BUFSIZE 1700
#define BSP_USING_PWM
#define BSP_USING_I2C
#define I2C_USE_MIO
#define RT_USING_MIO0
#define RT_USING_MIO1
#define RT_USING_MIO2
#define RT_USING_MIO10
#define BSP_USING_SDIF
#define BSP_USING_SDCARD_FATFS
#define USING_SDIF1
#define USE_SDIF1_TF
#define BSP_USING_DC
#define RT_USING_DC_CHANNEL0
#define RT_USING_DC_CHANNEL1
/* end of On-chip Peripheral Drivers */
/* Board extended module Drivers */
/* end of Hardware Drivers */
#define BSP_USING_GIC
#define BSP_USING_GICV3
#define PHYTIUM_ARCH_AARCH64
#define ARM_SPI_BIND_CPU_ID 2
/* Standalone Setting */
#define TARGET_ARMV8_AARCH64
/* Soc configuration */
#define TARGET_PHYTIUMPI
#define SOC_NAME "phytiumpi"
#define SOC_CORE_NUM 4
#define F32BIT_MEMORY_ADDRESS 0x80000000
#define F32BIT_MEMORY_LENGTH 0x80000000
#define F64BIT_MEMORY_ADDRESS 0x2000000000
#define F64BIT_MEMORY_LENGTH 0x800000000
#define TARGET_E2000
#define DEFAULT_DEBUG_PRINT_UART1
/* end of Soc configuration */
/* Board Configuration */
#define BOARD_NAME "firefly"
#define FIREFLY_DEMO_BOARD
/* IO mux configuration when board start up */
/* end of IO mux configuration when board start up */
/* end of Board Configuration */
/* Sdk common configuration */
#define ELOG_LINE_BUF_SIZE 0x100
#define LOG_DEBUG
/* end of Sdk common configuration */
/* end of Standalone Setting */
#endif

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#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* RT-Thread Kernel */
#define RT_NAME_MAX 16
#define RT_USING_SMP
#define RT_CPUS_NR 4
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 8192
#define SYSTEM_THREAD_STACK_SIZE 8192
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 8192
/* kservice optimization */
/* end of kservice optimization */
/* klibc optimization */
#define RT_KLIBC_USING_PRINTF_LONGLONG
/* end of klibc optimization */
#define RT_USING_DEBUG
#define RT_DEBUGING_ASSERT
#define RT_DEBUGING_COLOR
#define RT_DEBUGING_CONTEXT
#define RT_USING_OVERFLOW_CHECK
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* end of Inter-Thread communication */
/* Memory Management */
#define RT_PAGE_MAX_ORDER 16
#define RT_USING_SLAB
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SLAB_AS_HEAP
#define RT_USING_HEAP_ISR
#define RT_USING_HEAP
/* end of Memory Management */
#define RT_USING_DEVICE
#define RT_USING_SCHED_THREAD_CTX
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x50200
#define RT_USING_STDC_ATOMIC
#define RT_BACKTRACE_LEVEL_MAX_NR 32
/* end of RT-Thread Kernel */
/* AArch64 Architecture Configuration */
#define ARCH_TEXT_OFFSET 0x80000
#define ARCH_RAM_OFFSET 0x80000000
#define ARCH_SECONDARY_CPU_STACK_SIZE 4096
#define ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS
#define ARCH_HEAP_SIZE 0x4000000
#define ARCH_INIT_PAGE_SIZE 0x200000
/* end of AArch64 Architecture Configuration */
#define ARCH_CPU_64BIT
#define RT_USING_CACHE
#define RT_USING_HW_ATOMIC
#define ARCH_ARM_BOOTWITH_FLUSH_CACHE
#define RT_USING_CPU_FFS
#define ARCH_MM_MMU
#define ARCH_ARM
#define ARCH_ARM_MMU
#define ARCH_ARMV8
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 8192
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
#define FINSH_USING_OPTION_COMPLETION
/* DFS: device virtual file system */
#define RT_USING_DFS
#define DFS_USING_POSIX
#define DFS_USING_WORKDIR
#define DFS_FD_MAX 16
#define RT_USING_DFS_V1
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_LFN_UNICODE_0
#define RT_DFS_ELM_LFN_UNICODE 0
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
#define RT_DFS_ELM_REENTRANT
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
/* end of elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_RAMFS
/* end of DFS: device virtual file system */
/* Device Drivers */
#define RT_USING_DEV_BUS
#define RT_USING_DEVICE_IPC
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 8192
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_CAN
#define RT_CAN_USING_CANFD
#define RT_USING_I2C
#define RT_USING_I2C_BITOPS
#define RT_USING_NULL
#define RT_USING_ZERO
#define RT_USING_RANDOM
#define RT_USING_PWM
#define RT_USING_RTC
#define RT_USING_SDIO
#define RT_SDIO_STACK_SIZE 8192
#define RT_SDIO_THREAD_PRIORITY 15
#define RT_MMCSD_STACK_SIZE 8192
#define RT_MMCSD_THREAD_PREORITY 22
#define RT_MMCSD_MAX_PARTITION 16
#define RT_USING_SPI
#define RT_USING_QSPI
#define RT_USING_PIN
#define RT_USING_KTIME
#define RT_USING_CHERRYUSB
#define RT_CHERRYUSB_HOST
#define RT_CHERRYUSB_HOST_XHCI
#define RT_CHERRYUSB_HOST_HID
#define RT_CHERRYUSB_HOST_MSC
/* end of Device Drivers */
/* C/C++ and POSIX layer */
/* ISO-ANSI C layer */
/* Timezone and Daylight Saving Time */
#define RT_LIBC_USING_LIGHT_TZ_DST
#define RT_LIBC_TZ_DEFAULT_HOUR 8
#define RT_LIBC_TZ_DEFAULT_MIN 0
#define RT_LIBC_TZ_DEFAULT_SEC 0
/* end of Timezone and Daylight Saving Time */
/* end of ISO-ANSI C layer */
/* POSIX (Portable Operating System Interface) layer */
#define RT_USING_POSIX_FS
#define RT_USING_POSIX_DEVIO
#define RT_USING_POSIX_STDIO
#define RT_USING_POSIX_TERMIOS
#define RT_USING_POSIX_DELAY
#define RT_USING_POSIX_CLOCK
#define RT_USING_POSIX_TIMER
/* Interprocess Communication (IPC) */
/* Socket is in the 'Network' category */
/* end of Interprocess Communication (IPC) */
/* end of POSIX (Portable Operating System Interface) layer */
/* end of C/C++ and POSIX layer */
/* Network */
#define RT_USING_SAL
#define SAL_INTERNET_CHECK
/* Docking with protocol stacks */
#define SAL_USING_LWIP
/* end of Docking with protocol stacks */
#define SAL_USING_POSIX
#define RT_USING_NETDEV
#define NETDEV_USING_IFCONFIG
#define NETDEV_USING_PING
#define NETDEV_USING_NETSTAT
#define NETDEV_USING_AUTO_DEFAULT
#define NETDEV_IPV4 1
#define NETDEV_IPV6 0
#define RT_USING_LWIP
#define RT_USING_LWIP212
#define RT_USING_LWIP_VER_NUM 0x20102
#define RT_LWIP_MEM_ALIGNMENT 64
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
#define RT_LWIP_DNS
/* Static IPv4 Address */
#define RT_LWIP_IPADDR "192.168.4.10"
#define RT_LWIP_GWADDR "192.168.4.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
/* end of Static IPv4 Address */
#define RT_LWIP_UDP
#define RT_LWIP_TCP
#define RT_LWIP_RAW
#define RT_MEMP_NUM_NETCONN 8
#define RT_LWIP_PBUF_NUM 512
#define RT_LWIP_RAW_PCB_NUM 4
#define RT_LWIP_UDP_PCB_NUM 4
#define RT_LWIP_TCP_PCB_NUM 4
#define RT_LWIP_TCP_SEG_NUM 40
#define RT_LWIP_TCP_SND_BUF 8196
#define RT_LWIP_TCP_WND 8196
#define RT_LWIP_TCPTHREAD_PRIORITY 16
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_STACKSIZE 16184
#define RT_LWIP_ETHTHREAD_PRIORITY 12
#define RT_LWIP_ETHTHREAD_STACKSIZE 8192
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
#define RT_LWIP_REASSEMBLY_FRAG
#define LWIP_NETIF_STATUS_CALLBACK 1
#define LWIP_NETIF_LINK_CALLBACK 1
#define RT_LWIP_NETIF_NAMESIZE 6
#define SO_REUSE 1
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
#define LWIP_SO_LINGER 0
#define LWIP_NETIF_LOOPBACK 0
#define RT_LWIP_USING_PING
/* end of Network */
/* Memory protection */
/* end of Memory protection */
/* Utilities */
#define RT_USING_RYM
#define YMODEM_USING_FILE_TRANSFER
#define RT_USING_RESOURCE_ID
#define RT_USING_ADT
#define RT_USING_ADT_AVL
#define RT_USING_ADT_BITMAP
#define RT_USING_ADT_HASHMAP
#define RT_USING_ADT_REF
/* end of Utilities */
/* Using USB legacy version */
/* end of Using USB legacy version */
/* end of RT-Thread Components */
/* RT-Thread Utestcases */
/* end of RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* end of Marvell WiFi */
/* Wiced WiFi */
/* end of Wiced WiFi */
/* CYW43012 WiFi */
/* end of CYW43012 WiFi */
/* BL808 WiFi */
/* end of BL808 WiFi */
/* CYW43439 WiFi */
/* end of CYW43439 WiFi */
/* end of Wi-Fi */
/* IoT Cloud */
/* end of IoT Cloud */
/* end of IoT - internet of things */
/* security packages */
/* end of security packages */
/* language packages */
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* XML: Extensible Markup Language */
/* end of XML: Extensible Markup Language */
/* end of language packages */
/* multimedia packages */
/* LVGL: powerful and easy-to-use embedded GUI library */
/* end of LVGL: powerful and easy-to-use embedded GUI library */
/* u8g2: a monochrome graphic library */
/* end of u8g2: a monochrome graphic library */
/* end of multimedia packages */
/* tools packages */
/* end of tools packages */
/* system packages */
/* enhanced kernel services */
/* end of enhanced kernel services */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* end of acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
/* end of Micrium: Micrium software products porting for RT-Thread */
/* end of system packages */
/* peripheral libraries and drivers */
/* HAL & SDK Drivers */
/* STM32 HAL & SDK Drivers */
/* end of STM32 HAL & SDK Drivers */
/* Infineon HAL Packages */
/* end of Infineon HAL Packages */
/* Kendryte SDK */
/* end of Kendryte SDK */
/* end of HAL & SDK Drivers */
/* sensors drivers */
/* end of sensors drivers */
/* touch drivers */
/* end of touch drivers */
/* end of peripheral libraries and drivers */
/* AI packages */
/* end of AI packages */
/* Signal Processing and Control Algorithm Packages */
/* end of Signal Processing and Control Algorithm Packages */
/* miscellaneous packages */
/* project laboratory */
/* end of project laboratory */
/* samples: kernel and components samples */
#define PKG_USING_KERNEL_SAMPLES
#define PKG_USING_KERNEL_SAMPLES_LATEST_VERSION
#define PKG_USING_KERNEL_SAMPLES_EN
/* end of samples: kernel and components samples */
/* entertainment: terminal games and other interesting software packages */
/* end of entertainment: terminal games and other interesting software packages */
/* end of miscellaneous packages */
/* Arduino libraries */
/* Projects and Demos */
/* end of Projects and Demos */
/* Sensors */
/* end of Sensors */
/* Display */
/* end of Display */
/* Timing */
/* end of Timing */
/* Data Processing */
/* end of Data Processing */
/* Data Storage */
/* Communication */
/* end of Communication */
/* Device Control */
/* end of Device Control */
/* Other */
/* end of Other */
/* Signal IO */
/* end of Signal IO */
/* Uncategorized */
/* end of Arduino libraries */
/* end of RT-Thread online packages */
/* Hardware Drivers */
/* On-chip Peripheral Drivers */
#define BSP_USING_IOPAD
#define BSP_USING_UART
#define RT_USING_UART0
#define RT_USING_UART1
#define BSP_USING_SPI
#define RT_USING_SPIM0
#define BSP_USING_GPIO
#define BSP_USING_QSPI
#define RT_USING_QSPI0
#define USING_QSPI_CHANNEL0
#define BSP_USING_ETH
#define RT_LWIP_PBUF_POOL_BUFSIZE 1700
#define BSP_USING_PWM
#define BSP_USING_I2C
#define I2C_USE_MIO
#define RT_USING_MIO0
#define RT_USING_MIO1
#define RT_USING_MIO2
#define RT_USING_MIO10
#define BSP_USING_SDIF
#define BSP_USING_SDCARD_FATFS
#define USING_SDIF1
#define USE_SDIF1_TF
#define BSP_USING_DC
#define RT_USING_DC_CHANNEL0
#define RT_USING_DC_CHANNEL1
/* end of On-chip Peripheral Drivers */
/* Board extended module Drivers */
/* end of Hardware Drivers */
#define BSP_USING_GIC
#define BSP_USING_GICV3
#define PHYTIUM_ARCH_AARCH64
#define ARM_SPI_BIND_CPU_ID 2
/* Standalone Setting */
#define TARGET_ARMV8_AARCH64
/* Soc configuration */
#define TARGET_PHYTIUMPI
#define SOC_NAME "phytiumpi"
#define SOC_CORE_NUM 4
#define F32BIT_MEMORY_ADDRESS 0x80000000
#define F32BIT_MEMORY_LENGTH 0x80000000
#define F64BIT_MEMORY_ADDRESS 0x2000000000
#define F64BIT_MEMORY_LENGTH 0x800000000
#define TARGET_E2000
#define DEFAULT_DEBUG_PRINT_UART1
/* end of Soc configuration */
/* Board Configuration */
#define BOARD_NAME "firefly"
#define FIREFLY_DEMO_BOARD
/* IO mux configuration when board start up */
/* end of IO mux configuration when board start up */
/* end of Board Configuration */
/* Sdk common configuration */
#define ELOG_LINE_BUF_SIZE 0x100
#define LOG_DEBUG
/* end of Sdk common configuration */
/* end of Standalone Setting */
#endif

View File

@ -36,6 +36,14 @@ ifdef CONFIG_PHYTIUM_RTT_TEST
RTCONFIG := $(RTCONFIG)_test
endif
ifdef CONFIG_RT_CHERRYUSB_HOST_PUSB2
RTCONFIG := $(RTCONFIG)_pusb2_hc
endif
ifdef CONFIG_RT_CHERRYUSB_DEVICE_PUSB2
RTCONFIG := $(RTCONFIG)_pusb2_dc
endif
boot:
make all
cp rtthread_a64.elf /mnt/d/tftpboot
@ -44,7 +52,7 @@ boot:
debug:
@$(OD) -D rtthread_a64.elf > rtthread_a64.asm
@$(OD) -S rtthread_a64.elf > rtthread_a64.dis
all:
@echo "Build started..."
scons -j1024
@ -116,6 +124,12 @@ load_phytium_pi_rtthread:
@cp ./configs/phytium_pi_rtthread.h ./rtconfig.h -f
scons -c
load_phytium_pi_rtthread_pusb2_hc:
@echo "Load configs from ./configs/phytium_pi_rtthread_pusb2_hc"
@cp ./configs/phytium_pi_rtthread_pusb2_hc ./.config -f
@cp ./configs/phytium_pi_rtthread_pusb2_hc.h ./rtconfig.h -f
scons -c
load_phytium_pi_rtsmart:
@echo "Load configs from ./configs/phytium_pi_rtsmart"
@cp ./configs/phytium_pi_rtsmart ./.config -f

View File

@ -5,7 +5,7 @@
#define RT_NAME_MAX 16
#define RT_USING_SMP
#define RT_CPUS_NR 4
#define RT_CPUS_NR 2
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
@ -163,6 +163,11 @@
#define RT_USING_QSPI
#define RT_USING_PIN
#define RT_USING_KTIME
#define RT_USING_CHERRYUSB
#define RT_CHERRYUSB_HOST
#define RT_CHERRYUSB_HOST_XHCI
#define RT_CHERRYUSB_HOST_HID
#define RT_CHERRYUSB_HOST_MSC
/* end of Device Drivers */
/* C/C++ and POSIX layer */
@ -373,6 +378,10 @@
/* end of STM32 HAL & SDK Drivers */
/* Infineon HAL Packages */
/* end of Infineon HAL Packages */
/* Kendryte SDK */
/* end of Kendryte SDK */
@ -481,7 +490,6 @@
#define BSP_USING_ETH
#define RT_LWIP_PBUF_POOL_BUFSIZE 1700
#define BSP_USING_PWM
#define RT_USING_PWM6
#define BSP_USING_I2C
#define I2C_USE_MIO
#define RT_USING_MIO15
@ -502,7 +510,7 @@
#define BSP_USING_GIC
#define BSP_USING_GICV3
#define PHYTIUM_ARCH_AARCH64
#define ARM_SPI_BIND_CPU_ID 2
#define ARM_SPI_BIND_CPU_ID 0
/* Standalone Setting */
@ -510,10 +518,10 @@
/* Soc configuration */
#define TARGET_E2000Q
#define TARGET_E2000D
#define SOC_NAME "e2000"
#define TARGET_TYPE_NAME "q"
#define SOC_CORE_NUM 4
#define TARGET_TYPE_NAME "d"
#define SOC_CORE_NUM 2
#define F32BIT_MEMORY_ADDRESS 0x80000000
#define F32BIT_MEMORY_LENGTH 0x80000000
#define F64BIT_MEMORY_ADDRESS 0x2000000000
@ -524,8 +532,8 @@
/* Board Configuration */
#define E2000D_DEMO_BOARD
#define BOARD_NAME "demo"
#define E2000Q_DEMO_BOARD
/* IO mux configuration when board start up */

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@ -6,103 +6,115 @@
- 2. USB 主机 (PUSB2), 可以识别 U 盘/鼠标/键盘等设备
- 3. USB 从机 (PUSB2), 可以将开发板作为一个 USB 设备U 盘)运行,连接 Windows/Ubuntu 等主机进行识别和访问
> 目前只在 AARCH64 RT-Thread 模式下测试过
> Note: 目前 CherryUSB 没有适配 RT-Smart, 只能在 RT-Thread 模式下使用
## 通过 Package 使用 CherryUSB
> Note: CherryUSB 不支持同时使用不同类型的控制器PUSB2 和 XHCI 只能选择一种工作
- 进入 bsp 目录下的 aarch64 或者 aarch32 目录,然后 scons --menuconfig 进入 Kconfig 配置界面,选择 `Enable usb host mode` -> `XHCI`,最后选中需要的主机侧设备驱动
## 使用 USB 3.0 控制器 (XHCI)
![](../figures/cherryusb.png)
> Note: 飞腾派上只有CPU 正面侧靠网口的插槽是 USB 3.0 XHCI 接口,飞腾派中只引出了 USB 3.0 0 号控制器
- 保存配置后,更新 Packages
> Note: 飞腾派上 USB 3.0 控制器引脚和 PWM 及 GPIO 有复用关系,不能同时使用,具体的可以查阅数据手册
- 如果是在 E2000 D/Q Demo 板上,如下图所示连接 USB 设备
![](./figs/e2000_demo_usb3.png)
- 如果是在飞腾派上,如下图所示连接 USB 设备
![](./figs/phytiumpi_usb3.png)
- 加载默认配置 `make load_phytium_pi_rtthread`或者使能下面的配置USB 3.0 控制器可以识别键盘鼠标、U盘和外扩HUB
```
source ~/.env/env.sh
pkgs --update
RT_USING_CHERRYUSB
RT_CHERRYUSB_HOST
RT_CHERRYUSB_HOST_XHCI
RT_CHERRYUSB_HOST_HID
RT_CHERRYUSB_HOST_MSC
```
- 对于 XHCI, 相关的配置包括
![](../figures/cherryusb_xhci.png)
- 编译镜像后加载到开发板中启动,然后输入下面的命令启动 CherryUSB
```
#define PKG_USING_CHERRYUSB
#define PKG_CHERRYUSB_HOST
#define PKG_CHERRYUSB_HOST_XHCI
#define PKG_CHERRYUSB_HOST_HID
#define PKG_CHERRYUSB_HOST_MSC
#define PKG_CHERRYUSB_HOST_TEMPLATE
#define PKG_USING_CHERRYUSB_LATEST_VERSION
usb_host_init 0
```
- 对于 PUSB2相关的配置包括
> 如果需要使用 1 号控制器,输入 `usb_host_init 1`
![](../figures/pusb2_cherryusb.png)
- 主机模式
- 之后输入命令可以看到挂载的设备,可以看到 0 号 bus 和 1 号 bus 上通过 Hub 挂载了若干设备
```
#define PKG_USING_CHERRYUSB
#define PKG_CHERRYUSB_HOST
#define PKG_CHERRYUSB_HOST_PUSB2
#define PKG_CHERRYUSB_HOST_HID
#define PKG_CHERRYUSB_HOST_MSC
#define PKG_CHERRYUSB_HOST_TEMPLATE
lsusb -t
```
- 从机模式
![](./figs/e2000_demo_devices.png)
- 具体的 USB 设备使用可以参考 CherryUSB 使用说明,以及 [Phytium FreeRTOS SDK 的使用键盘、鼠标和U盘](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/blob/master/example/peripheral/usb/xhci_platform),以及[在 LVGL 中使用鼠标键盘](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/tree/master/example/peripheral/media/lvgl_indev)
## 使用 USB 2.0 控制器PUSB2 Device 模式)
> Note: 固件会配置 USB 2.0 控制器的的工作模式默认地E2000 D/Q Demo 板工作为 Device 模式,飞腾派工作为 Host 模式,本例程不支持切换工作模式,修改默认工作模式需要联系 FAE 更换固件或修改电路
- 如图所示将 E2000 D/Q Demo 板的 USB_OTG 接口和一台 Windows PC 连接
> E2000 D/Q Demo 板只引出 USB 2.0 0 号控制器,使用其它控制器需要修改代码
![](./figs/e2000d_demo_usb2.png)
- 使能下面的配置USB 2.0 控制器会模拟出一个 MSC 设备U 盘)给连接的上位机识别
> U 盘的存储空间用开发板的内存空间实现,所以掉电之后 U 盘中的数据就没有了,如果有需要持久保存数据的需要,可以修改例程用 SD 卡或者 Flash 存储空间实现 U 盘
```
#define PKG_USING_CHERRYUSB
#define PKG_CHERRYUSB_DEVICE
#define PKG_CHERRYUSB_DEVICE_FS
#define PKG_CHERRYUSB_DEVICE_PUSB2
#define PKG_CHERRYUSB_DEVICE_MSC
#define PKG_CHERRYUSB_DEVICE_MSC_STORAGE_TEMPLATE
#define PKG_USING_CHERRYUSB_LATEST_VERSION
RT_USING_CHERRYUSB
RT_CHERRYUSB_DEVICE
RT_CHERRYUSB_DEVICE_SPEED_HS
RT_CHERRYUSB_DEVICE_PUSB2
RT_CHERRYUSB_DEVICE_MSC
RT_CHERRYUSB_DEVICE_TEMPLATE_MSC
```
- 更新成功后会出现目录 aarch64/packages/CherryUSB-latest
- 随后进行编译即可
## 测试 CherryUSB 功能
### USB3 (XHCI)
> CherryUSB 更新比较频繁,稳定使用 XHCI 功能可以使用最后一次变更功能的 commit 号
- 编译镜像后加载到开发板中启动,然后输入下面的命令启动 CherryUSB
```
cd packages
rm ./CherryUSB-latest/ -rf
git clone https://github.com/cherry-embedded/CherryUSB.git ./CherryUSB-latest
cd ./CherryUSB-latest
git checkout aeffaea016f74cb5d6301b5ca5088c03e3dbe3a6
usb_device_init
```
- 将 U 盘插入到 USB3 0 号控制器,然后输入命令 `usbh_initialize` 开始枚举设备
- 枚举完成后输入 `lsusb -t` 查看识别到的设备
- 之后会在 PC 端识别出一个 U 盘,之后可以对 U 盘进行读写
![](../figures/xhci_0.png)
![](./figs/msc_device.png)
- 参考 CherryUSB 中的 demo 使用 USB 设备
![](./figs/msc_rw.png)
### USB2 (PUSB2 主机模式)
> 如果需要修改 U 盘的容量,可以在 msc_ram_template.c 中指定 BLOCK_COUNT 的值
> PUSB2 驱动欢迎联系 `opensource_embedded@phytium.com.cn` 获取
## 使用 USB 2.0 控制器 PUSB2 Host 模式)
- 将 U 盘插入到 USB2 0 号控制器,然后输入命令 `usbh_initialize` 开始枚举设备
- 枚举完成后输入 `lsusb -t` 查看识别到的设备
> Note: USB 2.0 控制器 Host 模式硬件上不支持使用 Hub 扩展插槽
![](../figures/pusb2_hid.png)
- 如图所示,在飞腾派引出的三个 USB 2.0 插槽上接上鼠标、键盘和 U 盘,注意 CPU 正面侧靠网口的插槽是 USB 3.0 XHCI 接口,其余 USB 接口是 USB 2.0 接口
- 参考 CherryUSB 中的 demo 使用 USB 设备
![](./figs/phytiumpi_usb2.jpg)
### USB2 (PUSB2 从机模式)
- 加载配置 `make load_phytium_pi_rtthread_pusb2_hc` 或者使能下面的配置USB 2.0 控制器作为 Host 工作,能够识别 HID 和 MSC 设备
> PUSB2 驱动欢迎联系 `opensource_embedded@phytium.com.cn` 获取
```
RT_USING_CHERRYUSB
RT_CHERRYUSB_HOST
RT_CHERRYUSB_HOST_PUSB2
RT_CHERRYUSB_HOST_HID
RT_CHERRYUSB_HOST_MSC
```
- 通过 USB 线连接开发板和主机 Windows 主机),然后输入命令 `msc_storage_init` 创建一个 USB 设备,等待连接的主机完成识别
> 在 RT-Thread 中,可以将 SD/eMMC 介质映射成一个 U 盘给上位机访问,上位机格式化 U 盘文件系统,可以将数据保存在 SD/eMMC 介质中
- 编译镜像后加载到开发板中启动,随后输入命令,初始化三个 USB 2.0 控制器,初始化完成后可以看到枚举到的三个设备,两个 HID 设备对应鼠标和键盘,一个 MSC 设备对应 U 盘,由于 U 盘没有文件系统udisk 尝试挂载 U 盘失败
![](../figures/cherryusb_device.png)
```
usb_host_init 0
usb_host_init 1
usb_host_init 2
```
![](./figs/usb2_host_init.png)

View File

@ -183,16 +183,7 @@ src += Glob(cwd+'/port/lwip_port/*.c')
path += [cwd + '/port/lwip_port']
## cherryusb port
if GetDepend(['BSP_USING_XHCI']):
src += Glob(cwd +'/port/cherryusb_port/drv_xhci.c')
path += [cwd + '/port/cherryusb_port']
if GetDepend(['BSP_USING_PUSB2']):
if GetDepend(['PKG_CHERRYUSB_HOST_PUSB2']):
src += Glob(cwd +'/port/cherryusb_port/drv_pusb2_hc.c')
if GetDepend(['PKG_CHERRYUSB_DEVICE_PUSB2']):
src += Glob(cwd +'/port/cherryusb_port/drv_pusb2_dc.c')
path += [cwd + '/port/cherryusb_port']
src += Glob(cwd + '/port/cherryusb_port/*.c')
# phytium ports rt-thread examples
PORT_DRV_DIR = cwd + '/examples'

View File

@ -273,29 +273,6 @@ menu "On-chip Peripheral Drivers"
bool "using dc channel_1"
default n
endif
menuconfig BSP_USING_XHCI
bool "Enable USB3.0(XHCI)"
default n
select PKG_USING_CHERRYUSB
if BSP_USING_XHCI
config RT_USING_XHCI0
bool "Enable xhci0"
default y if BSP_USING_XHCI
endif
menuconfig BSP_USING_PUSB2
bool "Enable USB2.0(PUSB2)"
default n
select PKG_USING_CHERRYUSB
if BSP_USING_PUSB2
config RT_USING_PUSB20
bool "Enable pusb20"
default y if BSP_USING_PUSB2
endif
endmenu
menu "Board extended module Drivers"

View File

@ -19,6 +19,6 @@ def clone_repository(branch, commit_hash):
if __name__ == "__main__":
branch_to_clone = "master"
commit_to_clone = "3a353d48ee1db27acf77241a62fb7e35c779e110"
commit_to_clone = "2ff7883c95cd312c636c9f35903b46ae74f8749d"
clone_repository(branch_to_clone, commit_to_clone)

View File

@ -1,93 +0,0 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Email: opensource_embedded@phytium.com.cn
*
* Change Logs:
* Date Author Notes
* 2023-11-14 zhugengyu first version
*
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <rtdbg.h>
#if defined(BSP_USING_PUSB2) && defined(PKG_CHERRYUSB_DEVICE_PUSB2)
#include "board.h"
#include "interrupt.h"
#include "mm_aspace.h"
#ifdef RT_USING_SMART
#include "ioremap.h"
#endif
#include "usbd_core.h"
#include "fcpu_info.h"
struct usb_pusb2_config
{
rt_uint32_t id;
rt_ubase_t base_addr; /* virtual address */
rt_uint32_t irq;
rt_uint32_t irq_priority;
};
static struct usb_pusb2_config pusb2_config[1U] =
{
[FUSB2_ID_VHUB_0] =
{
.id = FUSB2_ID_VHUB_0,
.base_addr = FUSB2_0_VHUB_BASE_ADDR,
.irq = FUSB2_0_VHUB_IRQ_NUM,
.irq_priority = 0xd0,
},
};
/* cherry usb support unique instance yet */
#define PUSB2_DEVICE_ID FUSB2_ID_VHUB_0
extern void USBD_IRQHandler(void *);
static void usb_pusb2_interrupt_handler(rt_int32_t vector, void *args)
{
/* args not in use */
USBD_IRQHandler(args);
}
static void usb_pusb2_setup_interrupt(struct usb_pusb2_config *config)
{
RT_ASSERT(config);
rt_uint32_t irq_num = config->irq;
rt_uint32_t irq_priority = config->irq_priority;
rt_uint32_t cpu_id = 0;
GetCpuId((u32 *)&cpu_id);
rt_hw_interrupt_set_target_cpus(irq_num, cpu_id);
rt_hw_interrupt_set_priority(irq_num, irq_priority);
rt_hw_interrupt_install(irq_num, usb_pusb2_interrupt_handler, config, "pusb2");
rt_hw_interrupt_umask(irq_num);
}
/* implement cherryusb weak functions */
void usb_dc_low_level_init()
{
usb_pusb2_setup_interrupt(&pusb2_config[PUSB2_DEVICE_ID]);
}
void usb_dc_low_level_deinit(void)
{
}
void usb_assert(const char *filename, int linenum)
{
RT_ASSERT(0);
}
#endif

View File

@ -1,98 +0,0 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Email: opensource_embedded@phytium.com.cn
*
* Change Logs:
* Date Author Notes
* 2023-11-14 zhugengyu first version
*
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <rtdbg.h>
#if defined(BSP_USING_PUSB2) && defined(PKG_CHERRYUSB_HOST_PUSB2)
#include "board.h"
#include "interrupt.h"
#include "mm_aspace.h"
#ifdef RT_USING_SMART
#include "ioremap.h"
#endif
#include "usbh_core.h"
#include "fcpu_info.h"
struct usb_pusb2_config
{
rt_uint32_t id;
rt_ubase_t base_addr; /* virtual address */
rt_uint32_t irq;
rt_uint32_t irq_priority;
};
static struct usb_pusb2_config pusb2_config[1U] =
{
[FUSB2_ID_VHUB_0] =
{
.id = FUSB2_ID_VHUB_0,
.base_addr = FUSB2_0_VHUB_BASE_ADDR,
.irq = FUSB2_0_VHUB_IRQ_NUM,
.irq_priority = 0xd0,
},
};
/* cherry usb support unique instance yet */
#define PUSB2_DEVICE_ID FUSB2_ID_VHUB_0
extern void USBH_IRQHandler(void *);
static void usb_pusb2_interrupt_handler(rt_int32_t vector, void *args)
{
/* args not in use */
USBH_IRQHandler(args);
}
static void usb_pusb2_setup_interrupt(struct usb_pusb2_config *config)
{
RT_ASSERT(config);
rt_uint32_t irq_num = config->irq;
rt_uint32_t irq_priority = config->irq_priority;
rt_uint32_t cpu_id = 0;
GetCpuId((u32 *)&cpu_id);
rt_hw_interrupt_set_target_cpus(irq_num, cpu_id);
rt_hw_interrupt_set_priority(irq_num, irq_priority);
rt_hw_interrupt_install(irq_num, usb_pusb2_interrupt_handler, config, "pusb2");
rt_hw_interrupt_umask(irq_num);
}
/* implement cherryusb weak functions */
void usb_hc_low_level_init()
{
usb_pusb2_setup_interrupt(&pusb2_config[PUSB2_DEVICE_ID]);
}
void usb_hc_low_level_deinit(void)
{
}
unsigned long usb_hc_get_register_base(void)
{
return pusb2_config[PUSB2_DEVICE_ID].base_addr;
}
void usb_assert(const char *filename, int linenum)
{
RT_ASSERT(0);
}
#endif

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@ -1,98 +0,0 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Email: opensource_embedded@phytium.com.cn
*
* Change Logs:
* Date Author Notes
* 2023-11-13 zhugengyu first version
*
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <rtdbg.h>
#ifdef BSP_USING_XHCI
#include "board.h"
#include "interrupt.h"
#include "mm_aspace.h"
#ifdef RT_USING_SMART
#include "ioremap.h"
#endif
#include "usbh_core.h"
#include "fcpu_info.h"
struct usb_xhci_config
{
rt_uint32_t id;
rt_ubase_t base_addr; /* virtual address */
rt_uint32_t irq;
rt_uint32_t irq_priority;
};
static struct usb_xhci_config xhci_config[FUSB3_NUM] =
{
[FUSB3_ID_0] = {
.id = FUSB3_ID_0,
.base_addr = FUSB3_0_BASE_ADDR + FUSB3_XHCI_OFFSET,
.irq = FUSB3_0_IRQ_NUM,
.irq_priority = 0xd0,
},
[FUSB3_ID_1] = {
.id = FUSB3_ID_1,
.base_addr = FUSB3_1_BASE_ADDR + FUSB3_XHCI_OFFSET,
.irq = FUSB3_1_IRQ_NUM,
.irq_priority = 0xd0,
},
};
/* cherry usb support unique instance yet */
#define XHCI_DEVICE_ID CONFIG_USBHOST_XHCI_ID
extern void USBH_IRQHandler(void *);
static void usb_xhci_interrupt_handler(rt_int32_t vector, void *args)
{
/* args not in used */
USBH_IRQHandler(args);
}
static void usb_xhci_setup_interrupt(struct usb_xhci_config *config)
{
RT_ASSERT(config);
rt_uint32_t irq_num = config->irq;
rt_uint32_t irq_priority = config->irq_priority;
rt_uint32_t cpu_id = 0;
GetCpuId((u32 *)&cpu_id);
rt_hw_interrupt_set_target_cpus(irq_num, cpu_id);
rt_hw_interrupt_set_priority(irq_num, irq_priority);
rt_hw_interrupt_install(irq_num, usb_xhci_interrupt_handler, config, "xhci");
rt_hw_interrupt_umask(irq_num);
}
/* implement cherryusb weak functions */
void usb_hc_low_level_init(void)
{
usb_xhci_setup_interrupt(&xhci_config[XHCI_DEVICE_ID]);
}
unsigned long usb_hc_get_register_base(void)
{
return xhci_config[XHCI_DEVICE_ID].base_addr;
}
void usb_assert(const char *filename, int linenum)
{
RT_ASSERT(0);
}
#endif

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@ -1,156 +0,0 @@
/*
* Copyright (c) 2022, sakumisu
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef CHERRYUSB_CONFIG_H
#define CHERRYUSB_CONFIG_H
#include <rtthread.h>
#define CHERRYUSB_VERSION 0x001002
/* ================ USB common Configuration ================ */
#define CONFIG_USB_PRINTF(...) rt_kprintf(__VA_ARGS__)
#define usb_malloc(size) rt_malloc(size)
#define usb_free(ptr) rt_free(ptr)
#define usb_align(align, size) rt_malloc_align(size, align)
#ifndef CONFIG_USB_DBG_LEVEL
#define CONFIG_USB_DBG_LEVEL USB_DBG_ERROR
#endif
/* Enable print with color */
#define CONFIG_USB_PRINTF_COLOR_ENABLE
/* data align size when use dma */
#ifndef CONFIG_USB_ALIGN_SIZE
#define CONFIG_USB_ALIGN_SIZE 4
#endif
/* attribute data into no cache ram */
#define USB_NOCACHE_RAM_SECTION __attribute__((section(".noncacheable")))
/* ================= USB Device Stack Configuration ================ */
/* Ep0 max transfer buffer, specially for receiving data from ep0 out */
#define CONFIG_USBDEV_REQUEST_BUFFER_LEN 512
/* Setup packet log for debug */
#define CONFIG_USBDEV_SETUP_LOG_PRINT
/* Check if the input descriptor is correct */
#define CONFIG_USBDEV_DESC_CHECK
#ifndef CONFIG_USB_ERROR_USE_SYSTEM
#define CONFIG_USB_ERROR_USE_SYSTEM
#endif
/* Enable test mode */
// #define CONFIG_USBDEV_TEST_MODE
#ifndef CONFIG_USBDEV_MSC_BLOCK_SIZE
#define CONFIG_USBDEV_MSC_BLOCK_SIZE 512
#endif
#ifndef CONFIG_USBDEV_MSC_MANUFACTURER_STRING
#define CONFIG_USBDEV_MSC_MANUFACTURER_STRING ""
#endif
#ifndef CONFIG_USBDEV_MSC_PRODUCT_STRING
#define CONFIG_USBDEV_MSC_PRODUCT_STRING ""
#endif
#ifndef CONFIG_USBDEV_MSC_VERSION_STRING
#define CONFIG_USBDEV_MSC_VERSION_STRING "0.01"
#endif
#define CONFIG_USBDEV_MSC_THREAD
#ifndef CONFIG_USBDEV_MSC_PRIO
#define CONFIG_USBDEV_MSC_PRIO 4
#endif
#ifndef CONFIG_USBDEV_MSC_STACKSIZE
#define CONFIG_USBDEV_MSC_STACKSIZE 8192
#endif
#ifndef CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE
#define CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE 156
#endif
#ifndef CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE
#define CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE 1536
#endif
#ifndef CONFIG_USBDEV_RNDIS_VENDOR_ID
#define CONFIG_USBDEV_RNDIS_VENDOR_ID 0x0000ffff
#endif
#ifndef CONFIG_USBDEV_RNDIS_VENDOR_DESC
#define CONFIG_USBDEV_RNDIS_VENDOR_DESC "CherryUSB"
#endif
#define CONFIG_USBDEV_RNDIS_USING_LWIP
/* ================ USB HOST Stack Configuration ================== */
#define CONFIG_USBHOST_MAX_RHPORTS 1
#define CONFIG_USBHOST_MAX_EXTHUBS 1
#define CONFIG_USBHOST_MAX_EHPORTS 4
#define CONFIG_USBHOST_MAX_INTERFACES 6
#define CONFIG_USBHOST_MAX_INTF_ALTSETTINGS 1
#define CONFIG_USBHOST_MAX_ENDPOINTS 4
#define CONFIG_USBHOST_MAX_CDC_ACM_CLASS 4
#define CONFIG_USBHOST_MAX_HID_CLASS 4
#define CONFIG_USBHOST_MAX_MSC_CLASS 2
#define CONFIG_USBHOST_MAX_AUDIO_CLASS 1
#define CONFIG_USBHOST_MAX_VIDEO_CLASS 1
#define CONFIG_USBHOST_DEV_NAMELEN 16
#ifndef CONFIG_USBHOST_PSC_PRIO
#define CONFIG_USBHOST_PSC_PRIO 4
#endif
#ifndef CONFIG_USBHOST_PSC_STACKSIZE
#define CONFIG_USBHOST_PSC_STACKSIZE 81920
#endif
// #define CONFIG_USBHOST_GET_STRING_DESC
// #define CONFIG_USBHOST_MSOS_ENABLE
#define CONFIG_USBHOST_MSOS_VENDOR_CODE 0x00
/* Ep0 max transfer buffer */
#define CONFIG_USBHOST_REQUEST_BUFFER_LEN 512
#ifndef CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT
#define CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT 500
#endif
#ifndef CONFIG_USBHOST_MSC_TIMEOUT
#define CONFIG_USBHOST_MSC_TIMEOUT 5000
#endif
/* ================ USB Device Port Configuration ================*/
/* ================ USB Host Port Configuration ==================*/
#define CONFIG_USBHOST_PIPE_NUM 10
/* ================ XHCI Configuration ================ */
#if defined(PKG_CHERRYUSB_HOST_XHCI)
#define CONFIG_USBHOST_XHCI
#define CONFIG_USBHOST_XHCI_ID 0U
#endif
/* ================ PUSB2 Configuration ================ */
#if defined(PKG_CHERRYUSB_HOST_PUSB2) || defined(PKG_CHERRYUSB_DEVICE_PUSB2)
#define CONFIG_USBDEV_PUSB2_CTRL_ID 0U
#define CONFIG_USBDEV_PUSB2_CTRL_NUM 1U
#endif
#endif

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@ -0,0 +1,29 @@
/*
* Copyright (c) 2024, sakumisu
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "rtthread.h"
#ifdef RT_CHERRYUSB_DEVICE_TEMPLATE_MSC
#include "usbd_core.h"
void msc_ram_init(uint8_t busid, uintptr_t reg_base);
static int usb_device_init(int argc, char **argv)
{
uint8_t busid = 0;
msc_ram_init(busid, usb_dc_get_register_base(busid));
return 0;
}
static int usb_device_deinit(int argc, char **argv)
{
uint8_t busid = 0;
return usbd_deinitialize(busid);
}
MSH_CMD_EXPORT(usb_device_init, init usb device as msc);
MSH_CMD_EXPORT(usb_device_deinit, deinit usb device as msc);
#endif

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@ -0,0 +1,60 @@
/*
* Copyright (c) 2024, sakumisu
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "rtthread.h"
#ifdef RT_CHERRYUSB_HOST
#include "usbh_core.h"
static int usb_host_init(int argc, char **argv)
{
uint8_t busid;
int err;
if (argc < 2) {
busid = 0;
} else {
busid = atoi(argv[1]);
}
err = usbh_initialize(busid, usb_hc_get_register_base(busid));
if (err) {
rt_kprintf("initialize usb%d@0x%x failed, err = %d\n",
busid, usb_hc_get_register_base(busid), err);
} else {
rt_kprintf("initialize usb%d@0x%x success\n",
busid, usb_hc_get_register_base(busid));
}
return err;
}
static int usb_host_deinit(int argc, char **argv)
{
uint8_t busid;
int err;
if (argc < 2) {
busid = 0;
} else {
busid = atoi(argv[1]);
}
err = usbh_deinitialize(busid);
if (err) {
rt_kprintf("deinitialize usb%d@0x%x failed, err = %d\n",
busid, usb_hc_get_register_base(busid), err);
} else {
rt_kprintf("deinitialize usb%d@0x%x success\n",
busid, usb_hc_get_register_base(busid));
}
return err;
}
MSH_CMD_EXPORT(usb_host_init, init usb host);
MSH_CMD_EXPORT(usb_host_deinit, deinit usb host);
#endif

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@ -255,7 +255,7 @@ if GetDepend(['RT_CHERRYUSB_HOST']):
src += Glob('platform/rtthread/usb_msh.c')
src += Glob('platform/rtthread/usb_check.c')
group = DefineGroup('CherryUSB', src, depend = ['RT_USING_CHERRYUSB'], CPPPATH = path, CPPDEFINES = CPPDEFINES)
group = DefineGroup('CherryUSB', src, depend = ['RT_USING_CHERRYUSB'], LIBS = LIBS, LIBPATH=LIBPATH, CPPPATH = path, CPPDEFINES = CPPDEFINES)
Return('group')

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# USB 2.0 OTG 控制器 (PUSB2)
- Phytium PI 和 Phyium E2000 系列开发板提供了兼容 USB2.0 的 OTG 接口
- 相关的使用例程可以在 Phytium PI飞腾派和 E2000 D/Q Demo 板上运行,例程包括
---------------------------------------------
- Host 模式
- - 1. [FreeRTOS 上作为主机使用键盘/鼠标/U盘](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/tree/master/example/peripheral/usb/pusb2_host/README.md)
- - 5. [RT-Thread 上作为主机识别键盘/鼠标/U盘](https://github.com/RT-Thread/rt-thread/blob/master/bsp/phytium/doc/use_cherryusb.md)
---------------------------------------------
- Device 模式
- - 1. [裸机上模拟为一个 U 盘](https://gitee.com/phytium_embedded/phytium-standalone-sdk/tree/master/example/peripherals/usb/pusb2_device/README.md)
- - 2. [裸机上模拟为一个虚拟串口](https://gitee.com/phytium_embedded/phytium-standalone-sdk/tree/master/example/peripherals/usb/pusb2_device/README.md)
- - 3. [FreeRTOS 上模拟为一个 U 盘](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/tree/master/example/peripheral/usb/pusb2_device/README.md)
- - 4. [FreeRTOS 上模拟为虚拟串口](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/tree/master/example/peripheral/usb/pusb2_device/README.md)
- - 5. [RT-Thread 上模拟为一个 U 盘](https://github.com/RT-Thread/rt-thread/blob/master/bsp/phytium/doc/use_cherryusb.md)
---------------------------------------------
- PUSB2 的驱动功能以静态库的方式提供,
- - libpusb2_hc_a64.a : AARCH64 主机模式驱动库
- - libpusb2_dc_a64.a : AARCH64 从机模式驱动库
- - libpusb2_hc_a32_hardfp.a AARCH32 主机模式驱动库,使用硬浮点
- - libpusb2_hc_a32_softfp.a AARCH32 主机模式驱动库,使用软浮点
- - libpusb2_dc_a32_hardfp.a AARCH32 从机模式驱动库,使用硬浮点
- - libpusb2_dc_a32_softfp.a AARCH32 从机模式驱动库,使用软浮点
需要获取源代码请联系 `opensource_embedded@phytium.com.cn` 获取
# USB 2.0 OTG Controller (PUSB2)
- Phytium PI and the Phytium E2000 series development boards offer OTG interfaces compatible with USB 2.0.
- Relevant usage examples can be run on the Phytium PI and E2000 D/Q Demo boards, including:
---------------------------------------------
- Host Mode
- 1. [Using a keyboard/mouse/USB flash drive as a host on FreeRTOS](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/tree/master/example/peripheral/usb/pusb2_host/README.md)
- 5. [Recognizing a keyboard/mouse/USB flash drive as a host on RT-Thread](https://github.com/RT-Thread/rt-thread/blob/master/bsp/phytium/doc/use_cherryusb.md)
---------------------------------------------
- Device Mode
- 1. [Simulating as a USB flash drive on a standalone system](https://gitee.com/phytium_embedded/phytium-standalone-sdk/tree/master/example/peripherals/usb/pusb2_device/README.md)
- 2. [Simulating as a virtual serial port on a standalone system](https://gitee.com/phytium_embedded/phytium-standalone-sdk/tree/master/example/peripherals/usb/pusb2_device/README.md)
- 3. [Simulating as a USB flash drive on FreeRTOS](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/tree/master/example/peripheral/usb/pusb2_device/README.md)
- 4. [Simulating as a virtual serial port on FreeRTOS](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/tree/master/example/peripheral/usb/pusb2_device/README.md)
- 5. [Simulating as a USB flash drive on RT-Thread](https://github.com/RT-Thread/rt-thread/blob/master/bsp/phytium/doc/use_cherryusb.md)
---------------------------------------------
- The driver functionality of PUSB2 is provided as static libraries:
- - `libpusb2_hc_a64.a` : Host mode driver library for AARCH64
- - `libpusb2_dc_a64.a` : Device mode driver library for AARCH64
- - `libpusb2_hc_a32_hardfp.a` : Host mode driver library for AARCH32, using hard floating point
- - `libpusb2_hc_a32_softfp.a` : Host mode driver library for AARCH32, using soft floating point
- - `libpusb2_dc_a32_hardfp.a` : Device mode driver library for AARCH32, using hard floating point
- - `libpusb2_dc_a32_softfp.a` : Device mode driver library for AARCH32, using soft floating point
- To obtain the source code, please contact `opensource_embedded@phytium.com.cn`.

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@ -0,0 +1,265 @@
/*
* Copyright : (C) 2024 Phytium Information Technology, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
* 1.0 zhugengyu 2024/6/26 first commit
*/
#ifndef CHERRYUSB_CONFIG_H
#define CHERRYUSB_CONFIG_H
#include "rtconfig.h"
/* ================ USB common Configuration ================ */
#define CONFIG_USB_PRINTF(...) rt_kprintf(__VA_ARGS__)
void *usb_sys_mem_malloc(size_t size);
void usb_sys_mem_free(void *ptr);
void *usb_sys_malloc_align(size_t align, size_t size);
#define usb_malloc(size) usb_sys_mem_malloc(size)
#define usb_free(ptr) usb_sys_mem_free(ptr)
#define usb_align(align, size) usb_sys_malloc_align(align, size)
unsigned long usb_hc_get_register_base(uint32_t id);
unsigned long usb_dc_get_register_base(uint32_t id);
#define CONFIG_USB_DBG_LEVEL USB_DBG_ERROR
/* Enable print with color */
#define CONFIG_USB_PRINTF_COLOR_ENABLE
/* data align size when use dma */
#ifndef CONFIG_USB_ALIGN_SIZE
#define CONFIG_USB_ALIGN_SIZE 4
#endif
/* attribute data into no cache ram */
#define USB_NOCACHE_RAM_SECTION __attribute__((section(".noncacheable")))
/* ================= USB Device Stack Configuration ================ */
/* Ep0 in and out transfer buffer */
#ifndef CONFIG_USBDEV_REQUEST_BUFFER_LEN
#define CONFIG_USBDEV_REQUEST_BUFFER_LEN 512
#endif
/* Setup packet log for debug */
// #define CONFIG_USBDEV_SETUP_LOG_PRINT
/* Send ep0 in data from user buffer instead of copying into ep0 reqdata
* Please note that user buffer must be aligned with CONFIG_USB_ALIGN_SIZE
*/
// #define CONFIG_USBDEV_EP0_INDATA_NO_COPY
/* Check if the input descriptor is correct */
// #define CONFIG_USBDEV_DESC_CHECK
/* Enable test mode */
// #define CONFIG_USBDEV_TEST_MODE
#ifndef CONFIG_USBDEV_MSC_MAX_LUN
#define CONFIG_USBDEV_MSC_MAX_LUN 1
#endif
#ifndef CONFIG_USBDEV_MSC_MAX_BUFSIZE
#define CONFIG_USBDEV_MSC_MAX_BUFSIZE 4096
#endif
#ifndef CONFIG_USBDEV_MSC_MANUFACTURER_STRING
#define CONFIG_USBDEV_MSC_MANUFACTURER_STRING ""
#endif
#ifndef CONFIG_USBDEV_MSC_PRODUCT_STRING
#define CONFIG_USBDEV_MSC_PRODUCT_STRING ""
#endif
#ifndef CONFIG_USBDEV_MSC_VERSION_STRING
#define CONFIG_USBDEV_MSC_VERSION_STRING "0.01"
#endif
// #define CONFIG_USBDEV_MSC_THREAD
#ifndef CONFIG_USBDEV_MSC_PRIO
#define CONFIG_USBDEV_MSC_PRIO 4
#endif
#ifndef CONFIG_USBDEV_MSC_STACKSIZE
#define CONFIG_USBDEV_MSC_STACKSIZE 8192
#endif
#ifndef CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE
#define CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE 156
#endif
/* rndis transfer buffer size, must be a multiple of (1536 + 44)*/
#ifndef CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE
#define CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE 1580
#endif
#ifndef CONFIG_USBDEV_RNDIS_VENDOR_ID
#define CONFIG_USBDEV_RNDIS_VENDOR_ID 0x0000ffff
#endif
#ifndef CONFIG_USBDEV_RNDIS_VENDOR_DESC
#define CONFIG_USBDEV_RNDIS_VENDOR_DESC "CherryUSB"
#endif
#define CONFIG_USBDEV_RNDIS_USING_LWIP
/* ================ USB HOST Stack Configuration ================== */
#define CONFIG_USBHOST_MAX_RHPORTS 1
#define CONFIG_USBHOST_MAX_EXTHUBS 0
#define CONFIG_USBHOST_MAX_EHPORTS 8
#define CONFIG_USBHOST_MAX_INTERFACES 8
#define CONFIG_USBHOST_MAX_INTF_ALTSETTINGS 8
#define CONFIG_USBHOST_MAX_ENDPOINTS 8
#define CONFIG_USBHOST_MAX_CDC_ACM_CLASS 4
#define CONFIG_USBHOST_MAX_HID_CLASS 4
#define CONFIG_USBHOST_MAX_MSC_CLASS 2
#define CONFIG_USBHOST_MAX_AUDIO_CLASS 1
#define CONFIG_USBHOST_MAX_VIDEO_CLASS 1
#define CONFIG_USBHOST_DEV_NAMELEN 16
#ifndef CONFIG_USBHOST_PSC_PRIO
#define CONFIG_USBHOST_PSC_PRIO 0
#endif
#ifndef CONFIG_USBHOST_PSC_STACKSIZE
#define CONFIG_USBHOST_PSC_STACKSIZE 8192
#endif
//#define CONFIG_USBHOST_GET_STRING_DESC
// #define CONFIG_USBHOST_MSOS_ENABLE
#ifndef CONFIG_USBHOST_MSOS_VENDOR_CODE
#define CONFIG_USBHOST_MSOS_VENDOR_CODE 0x00
#endif
/* Ep0 max transfer buffer */
#ifndef CONFIG_USBHOST_REQUEST_BUFFER_LEN
#define CONFIG_USBHOST_REQUEST_BUFFER_LEN 512
#endif
#ifndef CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT
#define CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT 500
#endif
#ifndef CONFIG_USBHOST_MSC_TIMEOUT
#define CONFIG_USBHOST_MSC_TIMEOUT 5000
#endif
/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size,
* you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow.
*/
#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE
#define CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE (2048)
#endif
/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */
#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE
#define CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE (2048)
#endif
/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size,
* you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow.
*/
#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE
#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE (2048)
#endif
/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */
#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE
#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE (2048)
#endif
/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size,
* you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow.
*/
#ifndef CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE
#define CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE (2048)
#endif
/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */
#ifndef CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE
#define CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE (2048)
#endif
/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size,
* you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow.
*/
#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE
#define CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE (2048)
#endif
/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */
#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE
#define CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE (2048)
#endif
#define CONFIG_USBHOST_BLUETOOTH_HCI_H4
// #define CONFIG_USBHOST_BLUETOOTH_HCI_LOG
#ifndef CONFIG_USBHOST_BLUETOOTH_TX_SIZE
#define CONFIG_USBHOST_BLUETOOTH_TX_SIZE 2048
#endif
#ifndef CONFIG_USBHOST_BLUETOOTH_RX_SIZE
#define CONFIG_USBHOST_BLUETOOTH_RX_SIZE 2048
#endif
/* ================ USB Device Port Configuration ================*/
#ifndef CONFIG_USBDEV_MAX_BUS
#define CONFIG_USBDEV_MAX_BUS 1 // for now, bus num must be 1 except hpm ip
#endif
#ifndef CONFIG_USBDEV_EP_NUM
#define CONFIG_USBDEV_EP_NUM 8
#endif
/* ---------------- FSDEV Configuration ---------------- */
//#define CONFIG_USBDEV_FSDEV_PMA_ACCESS 2 // maybe 1 or 2, many chips may have a difference
/* ---------------- DWC2 Configuration ---------------- */
/* (5 * number of control endpoints + 8) + ((largest USB packet used / 4) + 1 for
* status information) + (2 * number of OUT endpoints) + 1 for Global NAK
*/
// #define CONFIG_USB_DWC2_RXALL_FIFO_SIZE (1024 / 4)
/* IN Endpoints Max packet Size / 4 */
// #define CONFIG_USB_DWC2_TX0_FIFO_SIZE (64 / 4)
// #define CONFIG_USB_DWC2_TX1_FIFO_SIZE (512 / 4)
// #define CONFIG_USB_DWC2_TX2_FIFO_SIZE (64 / 4)
// #define CONFIG_USB_DWC2_TX3_FIFO_SIZE (64 / 4)
// #define CONFIG_USB_DWC2_TX4_FIFO_SIZE (0 / 4)
// #define CONFIG_USB_DWC2_TX5_FIFO_SIZE (0 / 4)
// #define CONFIG_USB_DWC2_TX6_FIFO_SIZE (0 / 4)
// #define CONFIG_USB_DWC2_TX7_FIFO_SIZE (0 / 4)
// #define CONFIG_USB_DWC2_TX8_FIFO_SIZE (0 / 4)
/* ---------------- MUSB Configuration ---------------- */
// #define CONFIG_USB_MUSB_SUNXI
/* ================ USB Host Port Configuration ==================*/
#ifndef CONFIG_INPUT_MOUSE_WHEEL
#define CONFIG_INPUT_MOUSE_WHEEL
#endif
#ifndef CONFIG_USBHOST_MAX_BUS
#define CONFIG_USBHOST_MAX_BUS 3
#endif
#ifndef CONFIG_USBHOST_PIPE_NUM
#define CONFIG_USBHOST_PIPE_NUM 10
#endif
/* ---------------- XHCI Configuration ---------------- */
#define CONFIG_USB_XHCI_HCCR_OFFSET (0x0)
/* ---------------- PUSB2 Configuration ---------------- */
#define CONFIG_USB_PUSB2_BUS_NUM 3U
#define CONFIG_USB_PUSB2_BUS_ID 0U
#endif

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@ -0,0 +1,89 @@
/*
* Copyright : (C) 2024 Phytium Information Technology, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
* 1.0 zhugengyu 2024/6/26 first commit
*/
#include "rtthread.h"
#include "interrupt.h"
#include "fparameters.h"
#include "usbd_core.h"
void USBD_IRQHandler(uint8_t busid);
void usb_assert(const char *filename, int linenum)
{
rt_assert_handler("", filename, linenum);
}
static void usb_dc_pusb2_interrupt_handler(int irqno, void *param)
{
USBD_IRQHandler(CONFIG_USB_PUSB2_BUS_ID);
}
static void usb_dc_setup_pusb2_interrupt(uint32_t id)
{
uint32_t irq_num = FUSB2_0_VHUB_IRQ_NUM;
rt_hw_interrupt_set_priority(irq_num, 0U);
rt_hw_interrupt_install(irq_num, usb_dc_pusb2_interrupt_handler, NULL, "pusb2-dc");
rt_hw_interrupt_umask(irq_num);
}
static void usb_dc_revoke_pusb2_interrupt(uint32_t id)
{
uint32_t irq_num = FUSB2_0_VHUB_IRQ_NUM;
rt_hw_interrupt_mask(irq_num);
}
unsigned long usb_dc_get_register_base(uint32_t id)
{
USB_ASSERT(id == FUSB2_ID_VHUB_0);
return FUSB2_0_VHUB_BASE_ADDR;
}
void usb_dc_low_level_init()
{
usb_dc_setup_pusb2_interrupt(CONFIG_USB_PUSB2_BUS_ID);
}
void usb_dc_low_level_deinit(void)
{
usb_dc_revoke_pusb2_interrupt(CONFIG_USB_PUSB2_BUS_ID);
}
void *usb_sys_mem_malloc(size_t size)
{
void *buf = rt_malloc(size);
if (buf) {
rt_memset(buf, 0, size);
}
return buf;
}
void usb_sys_mem_free(void *ptr)
{
if (ptr) {
rt_free(ptr);
}
}
void *usb_sys_malloc_align(size_t align, size_t size)
{
void *buf = rt_malloc_align(size, align);
if (buf) {
rt_memset(buf, 0, size);
}
return buf;
}

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@ -0,0 +1,109 @@
/*
* Copyright : (C) 2024 Phytium Information Technology, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
* 1.0 zhugengyu 2024/6/26 first commit
*/
#include "rtthread.h"
#include "interrupt.h"
#include "fparameters.h"
#include "usbh_core.h"
static const uint32_t irq_nums[] = {
FUSB2_0_VHUB_IRQ_NUM, FUSB2_1_IRQ_NUM, FUSB2_2_IRQ_NUM
};
void USBH_IRQHandler(uint8_t busid);
void usb_assert(const char *filename, int linenum)
{
rt_assert_handler("", filename, linenum);
}
static void usb_hc_pusb2_interrupt_handler(int irqno, void *param)
{
if (irqno == FUSB2_0_VHUB_IRQ_NUM) {
USBH_IRQHandler(FUSB2_ID_VHUB_0);
} else if (irqno == FUSB2_1_IRQ_NUM) {
USBH_IRQHandler(FUSB2_ID_1);
} else if (irqno == FUSB2_2_IRQ_NUM) {
USBH_IRQHandler(FUSB2_ID_2);
}
}
static void usb_hc_setup_pusb2_interrupt(uint32_t id)
{
uint32_t irq_num = irq_nums[id];
rt_hw_interrupt_set_priority(irq_num, 0U);
rt_hw_interrupt_install(irq_num, usb_hc_pusb2_interrupt_handler, NULL, "pusb2-hc");
rt_hw_interrupt_umask(irq_num);
USB_LOG_DBG("Enable irq-%d\n", irq_num);
}
static void usb_hc_revoke_pusb2_interrupt(uint32_t id)
{
uint32_t irq_num = irq_nums[id];
rt_hw_interrupt_mask(irq_num);
}
unsigned long usb_hc_get_register_base(uint32_t id)
{
if (id == FUSB2_ID_VHUB_0) {
return FUSB2_0_VHUB_BASE_ADDR;
} else if (id == FUSB2_ID_1) {
return FUSB2_1_BASE_ADDR;
} else if (id == FUSB2_ID_2) {
return FUSB2_2_BASE_ADDR;
} else {
USB_ASSERT(0);
return 0;
}
}
void usb_hc_low_level_init(struct usbh_bus *bus)
{
usb_hc_setup_pusb2_interrupt(bus->busid);
}
void usb_hc_low_level_deinit(struct usbh_bus *bus)
{
usb_hc_revoke_pusb2_interrupt(bus->busid);
}
void *usb_sys_mem_malloc(size_t size)
{
void *buf = rt_malloc(size);
if (buf) {
rt_memset(buf, 0, size);
}
return buf;
}
void usb_sys_mem_free(void *ptr)
{
if (ptr) {
rt_free(ptr);
}
}
void *usb_sys_malloc_align(size_t align, size_t size)
{
void *buf = rt_malloc_align(size, align);
if (buf) {
rt_memset(buf, 0, size);
}
return buf;
}

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@ -81,6 +81,13 @@ SECTIONS
PROVIDE(__rt_ofw_data_end = .);
. = ALIGN(16);
/* section information for usb usbh_class_info */
. = ALIGN(4);
__usbh_class_info_start__ = .;
KEEP(*(.usbh_class_info))
. = ALIGN(4);
__usbh_class_info_end__ = .;
PROVIDE(__text_end = .);
}