From b8db37f53f3546594fe151894024ae15fbcb7904 Mon Sep 17 00:00:00 2001 From: Huang bo Date: Wed, 15 Dec 2021 10:55:24 +0800 Subject: [PATCH] =?UTF-8?q?=E4=BF=AE=E6=94=B9=E6=A0=BC=E5=BC=8F?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- bsp/ti-tms320c6678/applications/board.c | 2 +- bsp/ti-tms320c6678/common/common.c | 146 ++++++++++++------------ 2 files changed, 75 insertions(+), 73 deletions(-) diff --git a/bsp/ti-tms320c6678/applications/board.c b/bsp/ti-tms320c6678/applications/board.c index 0e622765da..bfa4057c1f 100644 --- a/bsp/ti-tms320c6678/applications/board.c +++ b/bsp/ti-tms320c6678/applications/board.c @@ -21,7 +21,7 @@ void rt_hw_board_init(void) { // initial CPU core - keystone_cpu_init(); + keystone_cpu_init(); // initial interrupt controller rt_hw_interrupt_init(); diff --git a/bsp/ti-tms320c6678/common/common.c b/bsp/ti-tms320c6678/common/common.c index 0e026659ed..66826e2183 100644 --- a/bsp/ti-tms320c6678/common/common.c +++ b/bsp/ti-tms320c6678/common/common.c @@ -58,7 +58,7 @@ void reset_timer(int timer_num) { if(gpTimerRegs[timer_num]->TGCR) { - gpTimerRegs[timer_num]->TGCR= 0; + gpTimerRegs[timer_num]->TGCR = 0; gpTimerRegs[timer_num]->TCR= 0; } } @@ -67,135 +67,137 @@ void timer64_init(Timer64_Config * tmrCfg) { reset_timer(tmrCfg->timer_num); - gpTimerRegs[tmrCfg->timer_num]->CNTLO= 0; - gpTimerRegs[tmrCfg->timer_num]->CNTHI= 0; + gpTimerRegs[tmrCfg->timer_num]->CNTLO = 0; + gpTimerRegs[tmrCfg->timer_num]->CNTHI = 0; /*please note, in clock mode, two timer periods generate a clock, one timer period output high voltage level, the other timer period output low voltage level, so, the timer period should be half to the desired output clock period*/ - if(TIMER_PERIODIC_CLOCK==tmrCfg->timerMode) - tmrCfg->period= tmrCfg->period/2; + if(TIMER_PERIODIC_CLOCK == tmrCfg->timerMode) + { + tmrCfg->period = tmrCfg->period/2; + } /*the value written into period register is the expected value minus one*/ - gpTimerRegs[tmrCfg->timer_num]->PRDLO= _loll(tmrCfg->period-1); - gpTimerRegs[tmrCfg->timer_num]->PRDHI= _hill(tmrCfg->period-1); + gpTimerRegs[tmrCfg->timer_num]->PRDLO = _loll(tmrCfg->period-1); + gpTimerRegs[tmrCfg->timer_num]->PRDHI = _hill(tmrCfg->period-1); if(tmrCfg->reload_period>1) { - gpTimerRegs[tmrCfg->timer_num]->RELLO= _loll(tmrCfg->reload_period-1); - gpTimerRegs[tmrCfg->timer_num]->RELHI= _hill(tmrCfg->reload_period-1); + gpTimerRegs[tmrCfg->timer_num]->RELLO = _loll(tmrCfg->reload_period-1); + gpTimerRegs[tmrCfg->timer_num]->RELHI = _hill(tmrCfg->reload_period-1); } - if(TIMER_WATCH_DOG==tmrCfg->timerMode) + if(TIMER_WATCH_DOG == tmrCfg->timerMode) { - gpTimerRegs[tmrCfg->timer_num]->TGCR= + gpTimerRegs[tmrCfg->timer_num]->TGCR = /*Select watch-dog mode*/ - (CSL_TMR_TIMMODE_WDT<timerMode) + else if(TIMER_PERIODIC_WAVE == tmrCfg->timerMode) { - gpTimerRegs[tmrCfg->timer_num]->TGCR= TMR_TGCR_PLUSEN_MASK + gpTimerRegs[tmrCfg->timer_num]->TGCR = TMR_TGCR_PLUSEN_MASK /*for plus featuers, dual 32-bit unchained timer mode should be used*/ - |(CSL_TMR_TIMMODE_DUAL_UNCHAINED<timer_num]->INTCTL_STAT= TMR_INTCTLSTAT_EN_ALL_CLR_ALL; } else { - gpTimerRegs[tmrCfg->timer_num]->TGCR= + gpTimerRegs[tmrCfg->timer_num]->TGCR = /*Select 64-bit general timer mode*/ - (CSL_TMR_TIMMODE_GPT<timer_num]->EMUMGT_CLKSPD = (gpTimerRegs[tmrCfg->timer_num]->EMUMGT_CLKSPD& ~(CSL_TMR_EMUMGT_CLKSPD_FREE_MASK|CSL_TMR_EMUMGT_CLKSPD_SOFT_MASK)); - if(TIMER_WATCH_DOG==tmrCfg->timerMode) + if(TIMER_WATCH_DOG == tmrCfg->timerMode) { /*enable watchdog timer*/ gpTimerRegs[tmrCfg->timer_num]->WDTCR = CSL_TMR_WDTCR_WDEN_MASK - |(CSL_TMR_WDTCR_WDKEY_CMD1<timer_num]->TCR= - (CSL_TMR_CLOCK_INP_NOGATE<pulseWidth<pulseWidth << CSL_TMR_TCR_PWID_LO_SHIFT)&CSL_TMR_TCR_PWID_LO_MASK) /*select pulse mode*/ - |(CSL_TMR_CP_PULSE<timer_num]->WDTCR = CSL_TMR_WDTCR_WDEN_MASK - |(CSL_TMR_WDTCR_WDKEY_CMD2<timerMode) + else if(TIMER_ONE_SHOT_PULSE == tmrCfg->timerMode) { - gpTimerRegs[tmrCfg->timer_num]->TCR= - (CSL_TMR_CLOCK_INP_NOGATE<timer_num]->TCR = + (CSL_TMR_CLOCK_INP_NOGATE << CSL_TMR_TCR_TIEN_LO_SHIFT) + | (CSL_TMR_CLKSRC_INTERNAL << CSL_TMR_TCR_CLKSRC_LO_SHIFT) /*The timer is enabled one-shot*/ - |(CSL_TMR_ENAMODE_ENABLE<pulseWidth<pulseWidth << CSL_TMR_TCR_PWID_LO_SHIFT)&CSL_TMR_TCR_PWID_LO_MASK) /*select pulse mode*/ - |(CSL_TMR_CP_PULSE<timerMode) + else if(TIMER_PERIODIC_CLOCK == tmrCfg->timerMode) { - gpTimerRegs[tmrCfg->timer_num]->TCR= - (CSL_TMR_CLOCK_INP_NOGATE<timer_num]->TCR = + (CSL_TMR_CLOCK_INP_NOGATE << CSL_TMR_TCR_TIEN_LO_SHIFT) + | (CSL_TMR_CLKSRC_INTERNAL << CSL_TMR_TCR_CLKSRC_LO_SHIFT) /*The timer is enabled continuously*/ - |(CSL_TMR_ENAMODE_CONT<pulseWidth<pulseWidth << CSL_TMR_TCR_PWID_LO_SHIFT)&CSL_TMR_TCR_PWID_LO_MASK) /*select clock mode*/ - |(CSL_TMR_CP_CLOCK<timerMode) + else if(TIMER_PERIODIC_WAVE == tmrCfg->timerMode) { - gpTimerRegs[tmrCfg->timer_num]->TCR= - (CSL_TMR_CLOCK_INP_NOGATE<timer_num]->TCR = + (CSL_TMR_CLOCK_INP_NOGATE << CSL_TMR_TCR_TIEN_LO_SHIFT) + | (CSL_TMR_CLKSRC_INTERNAL << CSL_TMR_TCR_CLKSRC_LO_SHIFT) /*The timer is enabled continuously with period reload*/ - |(CSL_TMR_ENAMODE_CONT_RELOAD<pulseWidth<pulseWidth << CSL_TMR_TCR_PWID_LO_SHIFT)&CSL_TMR_TCR_PWID_LO_MASK) /*select clock mode*/ - |(CSL_TMR_CP_CLOCK<timer_num]->TCR= - (CSL_TMR_CLOCK_INP_NOGATE<timer_num]->TCR = + (CSL_TMR_CLOCK_INP_NOGATE << CSL_TMR_TCR_TIEN_LO_SHIFT) + | (CSL_TMR_CLKSRC_INTERNAL << CSL_TMR_TCR_CLKSRC_LO_SHIFT) /*The timer is enabled continuously*/ - |(CSL_TMR_ENAMODE_CONT<pulseWidth<pulseWidth << CSL_TMR_TCR_PWID_LO_SHIFT)&CSL_TMR_TCR_PWID_LO_MASK) /*select clock mode*/ - |(CSL_TMR_CP_PULSE<