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Merge pull request #1714 from xeonxu/fix_pwm 

[STM32 BSP]Fix PWM channel calculate argorithm.
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ZYH 2018-08-12 20:56:30 +08:00 committed by GitHub
parent 68edd04cbb 250de62d5c
commit b571cd8899
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 7 additions and 4 deletions
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9
bsp/stm32f4xx-HAL/drivers/drv_pwm.c
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@ -38,18 +38,21 @@ static struct rt_pwm_ops drv_ops =
static rt_err_t drv_pwm_enable(TIM_HandleTypeDef * htim, struct rt_pwm_configuration *configuration, rt_bool_t enable) static rt_err_t drv_pwm_enable(TIM_HandleTypeDef * htim, struct rt_pwm_configuration *configuration, rt_bool_t enable)
{ {
rt_uint32_t channel = 0x04 * configuration->channel; rt_uint32_t channel = 0x04 * (configuration->channel - 1);
if(!enable) if(!enable)
{ {
HAL_TIM_PWM_Stop(htim, channel); HAL_TIM_PWM_Stop(htim, channel);
} }
else
{
HAL_TIM_PWM_Start(htim, channel); HAL_TIM_PWM_Start(htim, channel);
}
return RT_EOK; return RT_EOK;
} }
static rt_err_t drv_pwm_get(TIM_HandleTypeDef * htim, struct rt_pwm_configuration *configuration) static rt_err_t drv_pwm_get(TIM_HandleTypeDef * htim, struct rt_pwm_configuration *configuration)
{ {
rt_uint32_t channel = 0x04 * configuration->channel; rt_uint32_t channel = 0x04 * (configuration->channel - 1);
rt_uint32_t tim_clock; rt_uint32_t tim_clock;
#if (RT_HSE_HCLK > 100000000UL)//100M #if (RT_HSE_HCLK > 100000000UL)//100M
if(htim->Instance == TIM1 && htim->Instance == TIM8) if(htim->Instance == TIM1 && htim->Instance == TIM8)
@ -81,7 +84,7 @@ static rt_err_t drv_pwm_set(TIM_HandleTypeDef * htim, struct rt_pwm_configuratio
{ {
rt_uint32_t period, pulse; rt_uint32_t period, pulse;
rt_uint32_t tim_clock, psc; rt_uint32_t tim_clock, psc;
rt_uint32_t channel = 0x04 * configuration->channel; rt_uint32_t channel = 0x04 * (configuration->channel - 1);
#if (RT_HSE_HCLK > 100000000UL)//100M #if (RT_HSE_HCLK > 100000000UL)//100M
if(htim->Instance == TIM1 && htim->Instance == TIM8) if(htim->Instance == TIM1 && htim->Instance == TIM8)
{ {