[bsp/at32] update pwm driver
This commit is contained in:
sheltonyu
Meco Man
parent
4203bfeb1d
commit
b4b010f4a3
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@ -6,6 +6,7 @@
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* Change Logs:
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* Date Author Notes
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* 2022-05-16 shelton first version
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* 2024-09-24 shelton update driver
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*/
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#include "drv_common.h"
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@ -19,8 +20,8 @@
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#include <drv_log.h>
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#define MAX_PERIOD 65535
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struct rt_device_pwm pwm_device;
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#define MIN_PERIOD 3
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#define MIN_PULSE 2
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struct at32_pwm
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{
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@ -154,6 +155,54 @@ static void tmr_pclk_get(rt_uint32_t *pclk1_doubler, rt_uint32_t *pclk2_doubler)
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}
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}
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static rt_err_t at32_hw_pwm_init(struct at32_pwm *instance)
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{
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tmr_output_config_type tmr_oc_config_struct;
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tmr_type *tmr_x = instance->tmr_x;
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at32_msp_tmr_init(tmr_x);
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tmr_base_init(tmr_x, 0, 0);
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tmr_clock_source_div_set(tmr_x, TMR_CLOCK_DIV1);
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/* pwm mode configuration */
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tmr_output_default_para_init(&tmr_oc_config_struct);
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/* config pwm mode */
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tmr_oc_config_struct.oc_mode = TMR_OUTPUT_CONTROL_PWM_MODE_A;
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/* config tmr pwm output */
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if(instance->channel & 0x01)
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{
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tmr_output_channel_config(tmr_x, TMR_SELECT_CHANNEL_1, &tmr_oc_config_struct);
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tmr_output_channel_buffer_enable(tmr_x, TMR_SELECT_CHANNEL_1, TRUE);
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}
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if(instance->channel & 0x02)
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{
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tmr_output_channel_config(tmr_x, TMR_SELECT_CHANNEL_2, &tmr_oc_config_struct);
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tmr_output_channel_buffer_enable(tmr_x, TMR_SELECT_CHANNEL_2, TRUE);
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}
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if(instance->channel & 0x04)
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{
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tmr_output_channel_config(tmr_x, TMR_SELECT_CHANNEL_3, &tmr_oc_config_struct);
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tmr_output_channel_buffer_enable(tmr_x, TMR_SELECT_CHANNEL_3, TRUE);
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}
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if(instance->channel & 0x08)
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{
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tmr_output_channel_config(tmr_x, TMR_SELECT_CHANNEL_4, &tmr_oc_config_struct);
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tmr_output_channel_buffer_enable(tmr_x, TMR_SELECT_CHANNEL_4, TRUE);
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}
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/* enable output */
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tmr_output_enable(tmr_x, TRUE);
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/* enable overflow request */
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tmr_overflow_request_source_set(tmr_x, TRUE);
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return RT_EOK;
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}
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static rt_err_t drv_pwm_enable(tmr_type* tmr_x, struct rt_pwm_configuration *configuration, rt_bool_t enable)
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{
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/* get the value of channel */
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@ -243,10 +292,9 @@ static rt_err_t drv_pwm_enable(tmr_type* tmr_x, struct rt_pwm_configuration *con
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static rt_err_t drv_pwm_get(tmr_type* tmr_x, struct rt_pwm_configuration *configuration)
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{
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crm_clocks_freq_type clocks_struct;
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rt_uint32_t pr, div, c1dt, c2dt, c3dt, c4dt;
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rt_uint32_t pr, div, c1dt, c2dt, c3dt, c4dt, tmr_clock;
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rt_uint32_t pclk1_doubler = 0, pclk2_doubler = 0;
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rt_uint32_t channel = configuration->channel;
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rt_uint64_t tmr_clock;
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pr = tmr_x->pr;
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div = tmr_x->div;
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@ -256,7 +304,6 @@ static rt_err_t drv_pwm_get(tmr_type* tmr_x, struct rt_pwm_configuration *config
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c4dt = tmr_x->c4dt;
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tmr_pclk_get(&pclk1_doubler, &pclk2_doubler);
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crm_clocks_freq_get(&clocks_struct);
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if(
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@ -303,17 +350,11 @@ static rt_err_t drv_pwm_get(tmr_type* tmr_x, struct rt_pwm_configuration *config
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static rt_err_t drv_pwm_set(tmr_type* tmr_x, struct rt_pwm_configuration *configuration)
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{
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crm_clocks_freq_type clocks_struct;
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tmr_output_config_type tmr_oc_config_struct;
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tmr_channel_select_type channel_select;
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rt_uint32_t period, pulse, channel, tmr_clock;
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rt_uint32_t period, pulse, channel, psc, tmr_clock;
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rt_uint32_t pclk1_doubler = 0, pclk2_doubler = 0;
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rt_uint64_t psc;
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/* init timer pin and enable clock */
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at32_msp_tmr_init(tmr_x);
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tmr_pclk_get(&pclk1_doubler, &pclk2_doubler);
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crm_clocks_freq_get(&clocks_struct);
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if(
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@ -347,33 +388,161 @@ static rt_err_t drv_pwm_set(tmr_type* tmr_x, struct rt_pwm_configuration *config
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period = (unsigned long long)configuration->period * tmr_clock / 1000ULL;;
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psc = period / MAX_PERIOD + 1;
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period = period / psc;
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tmr_div_value_set(tmr_x, psc - 1);
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if(period < MIN_PERIOD)
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{
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period = MIN_PERIOD;
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}
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tmr_period_value_set(tmr_x, period - 1);
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/* calculate pulse width */
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pulse = (unsigned long long)configuration->pulse * tmr_clock / psc / 1000ULL;
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if(pulse < MIN_PULSE)
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{
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pulse = MIN_PULSE;
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}
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else if(pulse >= period)
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{
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pulse = period + 1;
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}
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/* get channel parameter */
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channel = configuration->channel;
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if(channel == 1)
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{
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channel_select = TMR_SELECT_CHANNEL_1;
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}
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else if(channel == 2)
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{
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channel_select = TMR_SELECT_CHANNEL_2;
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}
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else if(channel == 3)
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{
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channel_select = TMR_SELECT_CHANNEL_3;
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}
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else if(channel == 4)
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{
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channel_select = TMR_SELECT_CHANNEL_4;
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}
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tmr_channel_value_set(tmr_x, channel_select, pulse);
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/* if you want the pwm setting to take effect immediately,
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please uncommon the following code, but it will cause the last pwm cycle not complete. */
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//tmr_counter_value_set(tmr_x, 0);
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//tmr_x->swevt_bit.ovfswtr = TRUE;
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return RT_EOK;
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}
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static rt_err_t drv_pwm_set_period(tmr_type* tmr_x, struct rt_pwm_configuration *configuration)
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{
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crm_clocks_freq_type clocks_struct;
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rt_uint32_t period, psc, tmr_clock;
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rt_uint32_t pclk1_doubler = 0, pclk2_doubler = 0;
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tmr_pclk_get(&pclk1_doubler, &pclk2_doubler);
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crm_clocks_freq_get(&clocks_struct);
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if(
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#if defined (TMR1)
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(tmr_x == TMR1)
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#endif
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#if defined (TMR8)
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|| (tmr_x == TMR8)
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#endif
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#if defined (TMR9)
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|| (tmr_x == TMR9)
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#endif
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#if defined (TMR10)
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|| (tmr_x == TMR10)
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#endif
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#if defined (TMR11)
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|| (tmr_x == TMR11)
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#endif
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)
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{
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tmr_clock = clocks_struct.apb2_freq * pclk2_doubler;
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}
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else
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{
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tmr_clock = clocks_struct.apb1_freq * pclk1_doubler;
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}
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/* convert nanosecond to frequency and duty cycle. */
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tmr_clock /= 1000000UL;
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/* calculate pwm period */
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period = (unsigned long long)configuration->period * tmr_clock / 1000ULL;;
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psc = period / MAX_PERIOD + 1;
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period = period / psc;
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tmr_div_value_set(tmr_x, psc - 1);
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if(period < MIN_PERIOD)
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{
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period = MIN_PERIOD;
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}
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tmr_period_value_set(tmr_x, period - 1);
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return RT_EOK;
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}
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static rt_err_t drv_pwm_set_pulse(tmr_type* tmr_x, struct rt_pwm_configuration *configuration)
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{
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crm_clocks_freq_type clocks_struct;
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tmr_channel_select_type channel_select;
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rt_uint32_t period, pulse, channel, psc, tmr_clock;
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rt_uint32_t pclk1_doubler = 0, pclk2_doubler = 0;
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tmr_pclk_get(&pclk1_doubler, &pclk2_doubler);
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crm_clocks_freq_get(&clocks_struct);
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if(
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#if defined (TMR1)
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(tmr_x == TMR1)
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#endif
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#if defined (TMR8)
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|| (tmr_x == TMR8)
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#endif
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#if defined (TMR9)
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|| (tmr_x == TMR9)
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#endif
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#if defined (TMR10)
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|| (tmr_x == TMR10)
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#endif
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#if defined (TMR11)
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|| (tmr_x == TMR11)
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#endif
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)
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{
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tmr_clock = clocks_struct.apb2_freq * pclk2_doubler;
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}
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else
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{
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tmr_clock = clocks_struct.apb1_freq * pclk1_doubler;
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}
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/* convert nanosecond to frequency and duty cycle. */
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tmr_clock /= 1000000UL;
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/* calculate pwm period */
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period = (unsigned long long)configuration->period * tmr_clock / 1000ULL;;
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psc = period / MAX_PERIOD + 1;
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/* calculate pulse width */
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pulse = (unsigned long long)configuration->pulse * tmr_clock / psc / 1000ULL;
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if(pulse < MIN_PULSE)
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{
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pulse = MIN_PULSE;
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}
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else if(pulse >= period)
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{
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pulse = period + 1;
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}
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/* get channel parameter */
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channel = configuration->channel;
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/* tmr base init */
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tmr_base_init(tmr_x, period - 1, psc - 1);
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tmr_clock_source_div_set(tmr_x, TMR_CLOCK_DIV1);
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/* pwm mode configuration */
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tmr_output_default_para_init(&tmr_oc_config_struct);
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/* config pwm mode */
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tmr_oc_config_struct.oc_mode = TMR_OUTPUT_CONTROL_PWM_MODE_A;
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if (!configuration->complementary)
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{
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tmr_oc_config_struct.oc_idle_state = FALSE;
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tmr_oc_config_struct.oc_output_state = FALSE;
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tmr_oc_config_struct.oc_polarity = TMR_OUTPUT_ACTIVE_HIGH;
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}
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else
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{
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tmr_oc_config_struct.occ_idle_state = FALSE;
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tmr_oc_config_struct.occ_output_state = FALSE;
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tmr_oc_config_struct.occ_polarity = TMR_OUTPUT_ACTIVE_HIGH;
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}
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if(channel == 1)
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{
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channel_select = TMR_SELECT_CHANNEL_1;
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@ -391,14 +560,7 @@ static rt_err_t drv_pwm_set(tmr_type* tmr_x, struct rt_pwm_configuration *config
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channel_select = TMR_SELECT_CHANNEL_4;
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}
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/* config tmr pwm output */
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tmr_output_channel_config(tmr_x, channel_select, &tmr_oc_config_struct);
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tmr_output_channel_buffer_enable(tmr_x, channel_select, TRUE);
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tmr_channel_value_set(tmr_x, channel_select, pulse);
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/* enable tmr period buffer */
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tmr_period_buffer_enable(tmr_x, TRUE);
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/* enable output */
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tmr_output_enable(tmr_x, TRUE);
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return RT_EOK;
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}
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@ -410,16 +572,16 @@ static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg
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switch (cmd)
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{
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case PWMN_CMD_ENABLE:
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configuration->complementary = RT_TRUE;
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case PWM_CMD_ENABLE:
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return drv_pwm_enable(tmr_x, configuration, RT_TRUE);
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case PWMN_CMD_DISABLE:
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configuration->complementary = RT_FALSE;
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case PWM_CMD_DISABLE:
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return drv_pwm_enable(tmr_x, configuration, RT_FALSE);
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case PWM_CMD_SET:
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return drv_pwm_set(tmr_x, configuration);
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case PWM_CMD_SET_PERIOD:
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return drv_pwm_set_period(tmr_x, configuration);
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case PWM_CMD_SET_PULSE:
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return drv_pwm_set_pulse(tmr_x, configuration);
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case PWM_CMD_GET:
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return drv_pwm_get(tmr_x, configuration);
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default:
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@ -430,118 +592,118 @@ static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg
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static void pwm_get_channel(void)
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{
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#ifdef BSP_USING_PWM1_CH1
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at32_pwm_obj[PWM1_INDEX].channel = 1;
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at32_pwm_obj[PWM1_INDEX].channel |= 1 << 0;
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#endif
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#ifdef BSP_USING_PWM1_CH2
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at32_pwm_obj[PWM1_INDEX].channel = 2;
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at32_pwm_obj[PWM1_INDEX].channel |= 1 << 1;
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#endif
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#ifdef BSP_USING_PWM1_CH3
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at32_pwm_obj[PWM1_INDEX].channel = 3;
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at32_pwm_obj[PWM1_INDEX].channel |= 1 << 2;
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#endif
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#ifdef BSP_USING_PWM1_CH4
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at32_pwm_obj[PWM1_INDEX].channel = 4;
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at32_pwm_obj[PWM1_INDEX].channel |= 1 << 3;
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#endif
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#ifdef BSP_USING_PWM2_CH1
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at32_pwm_obj[PWM2_INDEX].channel = 1;
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at32_pwm_obj[PWM2_INDEX].channel |= 1 << 0;
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#endif
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#ifdef BSP_USING_PWM2_CH2
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at32_pwm_obj[PWM2_INDEX].channel = 2;
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at32_pwm_obj[PWM2_INDEX].channel |= 1 << 1;
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#endif
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#ifdef BSP_USING_PWM2_CH3
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at32_pwm_obj[PWM2_INDEX].channel = 3;
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at32_pwm_obj[PWM2_INDEX].channel |= 1 << 2;
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#endif
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#ifdef BSP_USING_PWM2_CH4
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at32_pwm_obj[PWM2_INDEX].channel = 4;
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at32_pwm_obj[PWM2_INDEX].channel |= 1 << 3;
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#endif
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#ifdef BSP_USING_PWM3_CH1
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at32_pwm_obj[PWM3_INDEX].channel = 1;
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at32_pwm_obj[PWM3_INDEX].channel |= 1 << 0;
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#endif
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#ifdef BSP_USING_PWM3_CH2
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at32_pwm_obj[PWM3_INDEX].channel = 2;
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at32_pwm_obj[PWM3_INDEX].channel |= 1 << 1;
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#endif
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#ifdef BSP_USING_PWM3_CH3
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at32_pwm_obj[PWM3_INDEX].channel = 3;
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at32_pwm_obj[PWM3_INDEX].channel |= 1 << 2;
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#endif
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#ifdef BSP_USING_PWM3_CH4
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at32_pwm_obj[PWM3_INDEX].channel = 4;
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at32_pwm_obj[PWM3_INDEX].channel |= 1 << 3;
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#endif
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#ifdef BSP_USING_PWM4_CH1
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at32_pwm_obj[PWM4_INDEX].channel = 1;
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at32_pwm_obj[PWM4_INDEX].channel |= 1 << 0;
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#endif
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#ifdef BSP_USING_PWM4_CH2
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at32_pwm_obj[PWM4_INDEX].channel = 2;
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at32_pwm_obj[PWM4_INDEX].channel |= 1 << 1;
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#endif
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#ifdef BSP_USING_PWM4_CH3
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at32_pwm_obj[PWM4_INDEX].channel = 3;
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at32_pwm_obj[PWM4_INDEX].channel |= 1 << 2;
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#endif
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#ifdef BSP_USING_PWM4_CH4
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at32_pwm_obj[PWM4_INDEX].channel = 4;
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at32_pwm_obj[PWM4_INDEX].channel |= 1 << 3;
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#endif
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#ifdef BSP_USING_PWM5_CH1
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at32_pwm_obj[PWM5_INDEX].channel = 1;
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at32_pwm_obj[PWM5_INDEX].channel |= 1 << 0;
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#endif
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#ifdef BSP_USING_PWM5_CH2
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at32_pwm_obj[PWM5_INDEX].channel = 2;
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at32_pwm_obj[PWM5_INDEX].channel |= 1 << 1;
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#endif
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#ifdef BSP_USING_PWM5_CH3
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at32_pwm_obj[PWM5_INDEX].channel = 3;
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at32_pwm_obj[PWM5_INDEX].channel |= 1 << 2;
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#endif
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#ifdef BSP_USING_PWM5_CH4
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at32_pwm_obj[PWM5_INDEX].channel = 4;
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at32_pwm_obj[PWM5_INDEX].channel |= 1 << 3;
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#endif
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#ifdef BSP_USING_PWM6_CH1
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at32_pwm_obj[PWM6_INDEX].channel = 1;
|
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at32_pwm_obj[PWM6_INDEX].channel |= 1 << 0;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM6_CH2
|
||||
at32_pwm_obj[PWM6_INDEX].channel = 2;
|
||||
at32_pwm_obj[PWM6_INDEX].channel |= 1 << 1;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM6_CH3
|
||||
at32_pwm_obj[PWM6_INDEX].channel = 3;
|
||||
at32_pwm_obj[PWM6_INDEX].channel |= 1 << 2;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM6_CH4
|
||||
at32_pwm_obj[PWM6_INDEX].channel = 4;
|
||||
at32_pwm_obj[PWM6_INDEX].channel |= 1 << 3;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM7_CH1
|
||||
at32_pwm_obj[PWM7_INDEX].channel = 1;
|
||||
at32_pwm_obj[PWM7_INDEX].channel |= 1 << 0;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM7_CH2
|
||||
at32_pwm_obj[PWM7_INDEX].channel = 2;
|
||||
at32_pwm_obj[PWM7_INDEX].channel |= 1 << 1;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM7_CH3
|
||||
at32_pwm_obj[PWM7_INDEX].channel = 3;
|
||||
at32_pwm_obj[PWM7_INDEX].channel |= 1 << 2;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM7_CH4
|
||||
at32_pwm_obj[PWM7_INDEX].channel = 4;
|
||||
at32_pwm_obj[PWM7_INDEX].channel |= 1 << 3;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM8_CH1
|
||||
at32_pwm_obj[PWM8_INDEX].channel = 1;
|
||||
at32_pwm_obj[PWM8_INDEX].channel |= 1 << 0;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM8_CH2
|
||||
at32_pwm_obj[PWM8_INDEX].channel = 2;
|
||||
at32_pwm_obj[PWM8_INDEX].channel |= 1 << 1;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM8_CH3
|
||||
at32_pwm_obj[PWM8_INDEX].channel = 3;
|
||||
at32_pwm_obj[PWM8_INDEX].channel |= 1 << 2;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM8_CH4
|
||||
at32_pwm_obj[PWM8_INDEX].channel = 4;
|
||||
at32_pwm_obj[PWM8_INDEX].channel |= 1 << 3;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM9_CH1
|
||||
at32_pwm_obj[PWM9_INDEX].channel = 1;
|
||||
at32_pwm_obj[PWM9_INDEX].channel |= 1 << 0;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM9_CH2
|
||||
at32_pwm_obj[PWM9_INDEX].channel = 2;
|
||||
at32_pwm_obj[PWM9_INDEX].channel |= 1 << 1;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM9_CH3
|
||||
at32_pwm_obj[PWM9_INDEX].channel = 3;
|
||||
at32_pwm_obj[PWM9_INDEX].channel |= 1 << 2;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM9_CH4
|
||||
at32_pwm_obj[PWM9_INDEX].channel = 4;
|
||||
at32_pwm_obj[PWM9_INDEX].channel |= 1 << 3;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM12_CH1
|
||||
at32_pwm_obj[PWM12_INDEX].channel = 1;
|
||||
at32_pwm_obj[PWM12_INDEX].channel |= 1 << 0;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM12_CH2
|
||||
at32_pwm_obj[PWM12_INDEX].channel = 2;
|
||||
at32_pwm_obj[PWM12_INDEX].channel |= 1 << 1;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
@ -554,17 +716,26 @@ static int rt_hw_pwm_init(void)
|
|||
|
||||
for(i = 0; i < sizeof(at32_pwm_obj) / sizeof(at32_pwm_obj[0]); i++)
|
||||
{
|
||||
if(rt_device_pwm_register(&at32_pwm_obj[i].pwm_device, at32_pwm_obj[i].name, &drv_ops, at32_pwm_obj[i].tmr_x) == RT_EOK)
|
||||
if(at32_hw_pwm_init(&at32_pwm_obj[i]) != RT_EOK)
|
||||
{
|
||||
LOG_D("%s register success", at32_pwm_obj[i].name);
|
||||
LOG_E("%s init failed", at32_pwm_obj[i].name);
|
||||
result = -RT_ERROR;
|
||||
goto __exit;
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG_D("%s register failed", at32_pwm_obj[i].name);
|
||||
result = -RT_ERROR;
|
||||
if(rt_device_pwm_register(&at32_pwm_obj[i].pwm_device, at32_pwm_obj[i].name, &drv_ops, at32_pwm_obj[i].tmr_x) == RT_EOK)
|
||||
{
|
||||
LOG_D("%s register success", at32_pwm_obj[i].name);
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG_D("%s register failed", at32_pwm_obj[i].name);
|
||||
result = -RT_ERROR;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
__exit:
|
||||
return result;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue