update(cherryusb): add config for mcxn947 usbdev and usbhost
This commit is contained in:
sakumisu
Rbb666
parent
679761983d
commit
b462daf57e
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@ -27,7 +27,7 @@ menu "On-chip Peripheral Drivers"
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config BSP_USING_UART4
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config BSP_USING_UART4
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bool "Enable UART4"
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bool "Enable UART4"
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default y
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default y
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config BSP_USING_UART5
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config BSP_USING_UART5
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bool "Enable UART5"
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bool "Enable UART5"
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default n
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default n
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@ -155,7 +155,7 @@ menu "On-chip Peripheral Drivers"
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select RT_USING_LWIP
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select RT_USING_LWIP
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select RT_USING_NETDEV
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select RT_USING_NETDEV
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select RT_USING_SAL
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select RT_USING_SAL
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config BSP_USING_RTC
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config BSP_USING_RTC
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bool "Enable RTC"
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bool "Enable RTC"
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select RT_USING_RTC
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select RT_USING_RTC
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@ -184,6 +184,32 @@ menu "On-chip Peripheral Drivers"
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default y
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default y
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endif
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endif
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menuconfig BSP_USING_USB
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bool "Enable USB"
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default n
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if BSP_USING_USB
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config BSP_USING_USB_DEVICE
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bool "Enable USB Device, default is msc ramdisk"
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default n
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select RT_USING_CHERRYUSB
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select RT_CHERRYUSB_DEVICE
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select RT_CHERRYUSB_DEVICE_SPEED_HS
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select RT_CHERRYUSB_DEVICE_CHIPIDEA_MCX
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select RT_CHERRYUSB_DEVICE_MSC
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select RT_CHERRYUSB_DEVICE_TEMPLATE_MSC
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config BSP_USING_USB_HOST
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bool "Enable USB Host"
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default n
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select RT_USING_CHERRYUSB
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select RT_CHERRYUSB_HOST
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select RT_CHERRYUSB_HOST_EHCI_MCX
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select RT_CHERRYUSB_HOST_CDC_ACM
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select RT_CHERRYUSB_HOST_HID
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select RT_CHERRYUSB_HOST_MSC
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select RT_CHERRYUSB_HOST_CDC_RNDIS
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endif
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endmenu
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endmenu
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@ -5,6 +5,8 @@ cwd = GetCurrentDir()
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# add the general drivers.
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# add the general drivers.
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src = Split("""
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src = Split("""
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board.c
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board.c
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cherryusb_port.c
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usb_phy.c
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MCUX_Config/board/clock_config.c
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MCUX_Config/board/clock_config.c
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MCUX_Config/board/pin_mux.c
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MCUX_Config/board/pin_mux.c
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""")
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""")
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@ -0,0 +1,37 @@
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/*
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* Copyright (c) 2006-2024, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2024/04/23 sakumisu first version
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*/
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#include <rtthread.h>
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#include <board.h>
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/* low level init here, this has implemented in cherryusb */
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/* low level deinit here, this has implemented in cherryusb */
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#ifdef RT_CHERRYUSB_DEVICE_TEMPLATE_MSC
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int cherryusb_devinit(void)
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{
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extern void msc_ram_init(uint8_t busid, uintptr_t reg_base);
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msc_ram_init(0, USBHS1__USBC_BASE);
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return 0;
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}
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INIT_COMPONENT_EXPORT(cherryusb_devinit);
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#endif
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#ifdef RT_CHERRYUSB_HOST
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#include "usbh_core.h"
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int cherryusb_hostinit(void)
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{
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usbh_initialize(0, USBHS1__USBC_BASE);
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return 0;
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}
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INIT_COMPONENT_EXPORT(cherryusb_hostinit);
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#endif
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@ -120,6 +120,13 @@ SECTIONS
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__rt_init_start = .;
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__rt_init_start = .;
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KEEP(*(SORT(.rti_fn*)))
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KEEP(*(SORT(.rti_fn*)))
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__rt_init_end = .;
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__rt_init_end = .;
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/* section information for usbh class */
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. = ALIGN(8);
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__usbh_class_info_start__ = .;
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KEEP(*(.usbh_class_info))
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__usbh_class_info_end__ = .;
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} > m_text
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} > m_text
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.ARM.extab :
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.ARM.extab :
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@ -0,0 +1,127 @@
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/*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* Copyright 2016 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __USB_H__
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#define __USB_H__
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#include <stdint.h>
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#include <stdio.h>
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/*!
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* @addtogroup usb_drv
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* @{
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*/
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*! @brief Defines USB stack major version */
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#define USB_STACK_VERSION_MAJOR (2UL)
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/*! @brief Defines USB stack minor version */
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#define USB_STACK_VERSION_MINOR (10UL)
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/*! @brief Defines USB stack bugfix version */
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#define USB_STACK_VERSION_BUGFIX (0U)
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/*! @brief USB stack version definition */
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#define USB_MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))
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/*! @brief USB stack component version definition, changed with component in yaml together */
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#define USB_STACK_COMPONENT_VERSION \
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MAKE_VERSION(USB_STACK_VERSION_MAJOR, USB_STACK_VERSION_MINOR, USB_STACK_VERSION_BUGFIX)
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/*
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* Component ID used by tools
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*
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* FSL_COMPONENT_ID "middleware.usb.stack_common"
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*/
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/*! @brief USB error code */
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typedef enum _usb_status
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{
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kStatus_USB_Success = 0x00U, /*!< Success */
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kStatus_USB_Error, /*!< Failed */
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kStatus_USB_Busy, /*!< Busy */
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kStatus_USB_InvalidHandle, /*!< Invalid handle */
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kStatus_USB_InvalidParameter, /*!< Invalid parameter */
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kStatus_USB_InvalidRequest, /*!< Invalid request */
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kStatus_USB_ControllerNotFound, /*!< Controller cannot be found */
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kStatus_USB_InvalidControllerInterface, /*!< Invalid controller interface */
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kStatus_USB_NotSupported, /*!< Configuration is not supported */
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kStatus_USB_Retry, /*!< Enumeration get configuration retry */
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kStatus_USB_TransferStall, /*!< Transfer stalled */
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kStatus_USB_TransferFailed, /*!< Transfer failed */
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kStatus_USB_AllocFail, /*!< Allocation failed */
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kStatus_USB_LackSwapBuffer, /*!< Insufficient swap buffer for KHCI */
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kStatus_USB_TransferCancel, /*!< The transfer cancelled */
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kStatus_USB_BandwidthFail, /*!< Allocate bandwidth failed */
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kStatus_USB_MSDStatusFail, /*!< For MSD, the CSW status means fail */
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kStatus_USB_EHCIAttached,
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kStatus_USB_EHCIDetached,
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kStatus_USB_DataOverRun, /*!< The amount of data returned by the endpoint exceeded
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either the size of the maximum data packet allowed
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from the endpoint or the remaining buffer size. */
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} usb_status_t;
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/*! @brief USB host handle type define */
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typedef void *usb_host_handle;
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/*! @brief USB device handle type define. For device stack it is the whole device handle; for host stack it is the
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* attached device instance handle*/
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typedef void *usb_device_handle;
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/*! @brief USB OTG handle type define */
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typedef void *usb_otg_handle;
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/*! @brief USB controller ID */
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typedef enum _usb_controller_index
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{
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kUSB_ControllerKhci0 = 0U, /*!< KHCI 0U */
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kUSB_ControllerKhci1 = 1U, /*!< KHCI 1U, Currently, there are no platforms which have two KHCI IPs, this is reserved
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to be used in the future. */
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kUSB_ControllerEhci0 = 2U, /*!< EHCI 0U */
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kUSB_ControllerEhci1 = 3U, /*!< EHCI 1U */
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kUSB_ControllerLpcIp3511Fs0 = 4U, /*!< LPC USB IP3511 FS controller 0 */
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kUSB_ControllerLpcIp3511Fs1 = 5U, /*!< LPC USB IP3511 FS controller 1, there are no platforms which have two IP3511
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IPs, this is reserved to be used in the future. */
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kUSB_ControllerLpcIp3511Hs0 = 6U, /*!< LPC USB IP3511 HS controller 0 */
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kUSB_ControllerLpcIp3511Hs1 = 7U, /*!< LPC USB IP3511 HS controller 1, there are no platforms which have two IP3511
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IPs, this is reserved to be used in the future. */
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kUSB_ControllerOhci0 = 8U, /*!< OHCI 0U */
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kUSB_ControllerOhci1 = 9U, /*!< OHCI 1U, Currently, there are no platforms which have two OHCI IPs, this is reserved
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to be used in the future. */
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kUSB_ControllerIp3516Hs0 = 10U, /*!< IP3516HS 0U */
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kUSB_ControllerIp3516Hs1 = 11U, /*!< IP3516HS 1U, Currently, there are no platforms which have two IP3516HS IPs,
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this is reserved to be used in the future. */
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kUSB_ControllerDwc30 = 12U, /*!< DWC3 0U */
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kUSB_ControllerDwc31 = 13U, /*!< DWC3 1U Currently, there are no platforms which have two Dwc IPs, this is reserved
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to be used in the future.*/
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} usb_controller_index_t;
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/**
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* @brief USB stack version fields
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*/
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typedef struct _usb_version
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{
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uint8_t major; /*!< Major */
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uint8_t minor; /*!< Minor */
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uint8_t bugfix; /*!< Bug fix */
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} usb_version_t;
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/*******************************************************************************
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* API
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******************************************************************************/
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/*! @} */
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#endif /* __USB_H__ */
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@ -0,0 +1,278 @@
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/*
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* Copyright (c) 2022, sakumisu
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef CHERRYUSB_CONFIG_H
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#define CHERRYUSB_CONFIG_H
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#include <rtthread.h>
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/* ================ USB common Configuration ================ */
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#define CONFIG_USB_PRINTF(...) rt_kprintf(__VA_ARGS__)
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#ifndef CONFIG_USB_DBG_LEVEL
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#define CONFIG_USB_DBG_LEVEL USB_DBG_INFO
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#endif
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/* Enable print with color */
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#define CONFIG_USB_PRINTF_COLOR_ENABLE
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/* data align size when use dma */
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#ifndef CONFIG_USB_ALIGN_SIZE
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#define CONFIG_USB_ALIGN_SIZE 4
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#endif
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/* attribute data into no cache ram */
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#define USB_NOCACHE_RAM_SECTION __attribute__((section(".NonCacheable")))
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/* ================= USB Device Stack Configuration ================ */
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/* Ep0 in and out transfer buffer */
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#ifndef CONFIG_USBDEV_REQUEST_BUFFER_LEN
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#define CONFIG_USBDEV_REQUEST_BUFFER_LEN 512
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#endif
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/* Setup packet log for debug */
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// #define CONFIG_USBDEV_SETUP_LOG_PRINT
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/* Send ep0 in data from user buffer instead of copying into ep0 reqdata
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* Please note that user buffer must be aligned with CONFIG_USB_ALIGN_SIZE
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*/
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// #define CONFIG_USBDEV_EP0_INDATA_NO_COPY
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/* Check if the input descriptor is correct */
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// #define CONFIG_USBDEV_DESC_CHECK
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/* Enable test mode */
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// #define CONFIG_USBDEV_TEST_MODE
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#ifndef CONFIG_USBDEV_MSC_MAX_LUN
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#define CONFIG_USBDEV_MSC_MAX_LUN 1
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#endif
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#ifndef CONFIG_USBDEV_MSC_MAX_BUFSIZE
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#define CONFIG_USBDEV_MSC_MAX_BUFSIZE 512
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#endif
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#ifndef CONFIG_USBDEV_MSC_MANUFACTURER_STRING
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#define CONFIG_USBDEV_MSC_MANUFACTURER_STRING ""
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#endif
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#ifndef CONFIG_USBDEV_MSC_PRODUCT_STRING
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#define CONFIG_USBDEV_MSC_PRODUCT_STRING ""
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#endif
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#ifndef CONFIG_USBDEV_MSC_VERSION_STRING
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#define CONFIG_USBDEV_MSC_VERSION_STRING "0.01"
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#endif
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/* move msc read & write from isr to while(1), you should call usbd_msc_polling in while(1) */
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// #define CONFIG_USBDEV_MSC_POLLING
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/* move msc read & write from isr to thread */
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// #define CONFIG_USBDEV_MSC_THREAD
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#ifndef CONFIG_USBDEV_MSC_PRIO
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#define CONFIG_USBDEV_MSC_PRIO 4
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#endif
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#ifndef CONFIG_USBDEV_MSC_STACKSIZE
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#define CONFIG_USBDEV_MSC_STACKSIZE 2048
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#endif
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#ifndef CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE
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#define CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE 156
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#endif
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/* rndis transfer buffer size, must be a multiple of (1536 + 44)*/
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#ifndef CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE
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#define CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE 1580
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#endif
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#ifndef CONFIG_USBDEV_RNDIS_VENDOR_ID
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#define CONFIG_USBDEV_RNDIS_VENDOR_ID 0x0000ffff
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#endif
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#ifndef CONFIG_USBDEV_RNDIS_VENDOR_DESC
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#define CONFIG_USBDEV_RNDIS_VENDOR_DESC "CherryUSB"
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#endif
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#define CONFIG_USBDEV_RNDIS_USING_LWIP
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/* ================ USB HOST Stack Configuration ================== */
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#define CONFIG_USBHOST_MAX_RHPORTS 1
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#define CONFIG_USBHOST_MAX_EXTHUBS 1
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#define CONFIG_USBHOST_MAX_EHPORTS 4
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#define CONFIG_USBHOST_MAX_INTERFACES 8
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#define CONFIG_USBHOST_MAX_INTF_ALTSETTINGS 8
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#define CONFIG_USBHOST_MAX_ENDPOINTS 4
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#define CONFIG_USBHOST_MAX_CDC_ACM_CLASS 4
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#define CONFIG_USBHOST_MAX_HID_CLASS 4
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#define CONFIG_USBHOST_MAX_MSC_CLASS 2
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#define CONFIG_USBHOST_MAX_AUDIO_CLASS 1
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#define CONFIG_USBHOST_MAX_VIDEO_CLASS 1
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#define CONFIG_USBHOST_DEV_NAMELEN 16
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#ifndef CONFIG_USBHOST_PSC_PRIO
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#define CONFIG_USBHOST_PSC_PRIO 0
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#endif
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#ifndef CONFIG_USBHOST_PSC_STACKSIZE
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#define CONFIG_USBHOST_PSC_STACKSIZE 2048
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#endif
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//#define CONFIG_USBHOST_GET_STRING_DESC
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// #define CONFIG_USBHOST_MSOS_ENABLE
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#ifndef CONFIG_USBHOST_MSOS_VENDOR_CODE
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||||||
|
#define CONFIG_USBHOST_MSOS_VENDOR_CODE 0x00
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Ep0 max transfer buffer */
|
||||||
|
#ifndef CONFIG_USBHOST_REQUEST_BUFFER_LEN
|
||||||
|
#define CONFIG_USBHOST_REQUEST_BUFFER_LEN 512
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT
|
||||||
|
#define CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT 500
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef CONFIG_USBHOST_MSC_TIMEOUT
|
||||||
|
#define CONFIG_USBHOST_MSC_TIMEOUT 5000
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size,
|
||||||
|
* you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow.
|
||||||
|
*/
|
||||||
|
#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE
|
||||||
|
#define CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE (2048)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */
|
||||||
|
#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE
|
||||||
|
#define CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE (2048)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size,
|
||||||
|
* you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow.
|
||||||
|
*/
|
||||||
|
#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE
|
||||||
|
#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE (2048)
|
||||||
|
#endif
|
||||||
|
/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */
|
||||||
|
#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE
|
||||||
|
#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE (2048)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size,
|
||||||
|
* you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow.
|
||||||
|
*/
|
||||||
|
#ifndef CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE
|
||||||
|
#define CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE (2048)
|
||||||
|
#endif
|
||||||
|
/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */
|
||||||
|
#ifndef CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE
|
||||||
|
#define CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE (2048)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size,
|
||||||
|
* you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow.
|
||||||
|
*/
|
||||||
|
#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE
|
||||||
|
#define CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE (2048)
|
||||||
|
#endif
|
||||||
|
/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */
|
||||||
|
#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE
|
||||||
|
#define CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE (2048)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define CONFIG_USBHOST_BLUETOOTH_HCI_H4
|
||||||
|
// #define CONFIG_USBHOST_BLUETOOTH_HCI_LOG
|
||||||
|
|
||||||
|
#ifndef CONFIG_USBHOST_BLUETOOTH_TX_SIZE
|
||||||
|
#define CONFIG_USBHOST_BLUETOOTH_TX_SIZE 2048
|
||||||
|
#endif
|
||||||
|
#ifndef CONFIG_USBHOST_BLUETOOTH_RX_SIZE
|
||||||
|
#define CONFIG_USBHOST_BLUETOOTH_RX_SIZE 2048
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* ================ USB Device Port Configuration ================*/
|
||||||
|
|
||||||
|
#ifndef CONFIG_USBDEV_MAX_BUS
|
||||||
|
#define CONFIG_USBDEV_MAX_BUS 1 // for now, bus num must be 1 except hpm ip
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef CONFIG_USBDEV_EP_NUM
|
||||||
|
#define CONFIG_USBDEV_EP_NUM 6
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* ---------------- FSDEV Configuration ---------------- */
|
||||||
|
//#define CONFIG_USBDEV_FSDEV_PMA_ACCESS 2 // maybe 1 or 2, many chips may have a difference
|
||||||
|
|
||||||
|
/* ---------------- DWC2 Configuration ---------------- */
|
||||||
|
/* (5 * number of control endpoints + 8) + ((largest USB packet used / 4) + 1 for
|
||||||
|
* status information) + (2 * number of OUT endpoints) + 1 for Global NAK
|
||||||
|
*/
|
||||||
|
// #define CONFIG_USB_DWC2_RXALL_FIFO_SIZE (1024 / 4)
|
||||||
|
/* IN Endpoints Max packet Size / 4 */
|
||||||
|
// #define CONFIG_USB_DWC2_TX0_FIFO_SIZE (64 / 4)
|
||||||
|
// #define CONFIG_USB_DWC2_TX1_FIFO_SIZE (512 / 4)
|
||||||
|
// #define CONFIG_USB_DWC2_TX2_FIFO_SIZE (64 / 4)
|
||||||
|
// #define CONFIG_USB_DWC2_TX3_FIFO_SIZE (64 / 4)
|
||||||
|
// #define CONFIG_USB_DWC2_TX4_FIFO_SIZE (0 / 4)
|
||||||
|
// #define CONFIG_USB_DWC2_TX5_FIFO_SIZE (0 / 4)
|
||||||
|
// #define CONFIG_USB_DWC2_TX6_FIFO_SIZE (0 / 4)
|
||||||
|
// #define CONFIG_USB_DWC2_TX7_FIFO_SIZE (0 / 4)
|
||||||
|
// #define CONFIG_USB_DWC2_TX8_FIFO_SIZE (0 / 4)
|
||||||
|
|
||||||
|
/* ---------------- MUSB Configuration ---------------- */
|
||||||
|
// #define CONFIG_USB_MUSB_SUNXI
|
||||||
|
|
||||||
|
/* ================ USB Host Port Configuration ==================*/
|
||||||
|
#ifndef CONFIG_USBHOST_MAX_BUS
|
||||||
|
#define CONFIG_USBHOST_MAX_BUS 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef CONFIG_USBHOST_PIPE_NUM
|
||||||
|
#define CONFIG_USBHOST_PIPE_NUM 10
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* ---------------- EHCI Configuration ---------------- */
|
||||||
|
|
||||||
|
#define CONFIG_USB_EHCI_HCCR_OFFSET (0x100)
|
||||||
|
#define CONFIG_USB_EHCI_FRAME_LIST_SIZE 1024
|
||||||
|
#define CONFIG_USB_EHCI_QH_NUM CONFIG_USBHOST_PIPE_NUM
|
||||||
|
#define CONFIG_USB_EHCI_QTD_NUM 3
|
||||||
|
#define CONFIG_USB_EHCI_ITD_NUM 20
|
||||||
|
// #define CONFIG_USB_EHCI_HCOR_RESERVED_DISABLE
|
||||||
|
// #define CONFIG_USB_EHCI_CONFIGFLAG
|
||||||
|
// #define CONFIG_USB_EHCI_ISO
|
||||||
|
// #define CONFIG_USB_EHCI_WITH_OHCI
|
||||||
|
|
||||||
|
/* ---------------- OHCI Configuration ---------------- */
|
||||||
|
#define CONFIG_USB_OHCI_HCOR_OFFSET (0x0)
|
||||||
|
|
||||||
|
/* ---------------- XHCI Configuration ---------------- */
|
||||||
|
#define CONFIG_USB_XHCI_HCCR_OFFSET (0x0)
|
||||||
|
|
||||||
|
/* ---------------- DWC2 Configuration ---------------- */
|
||||||
|
/* largest non-periodic USB packet used / 4 */
|
||||||
|
// #define CONFIG_USB_DWC2_NPTX_FIFO_SIZE (512 / 4)
|
||||||
|
/* largest periodic USB packet used / 4 */
|
||||||
|
// #define CONFIG_USB_DWC2_PTX_FIFO_SIZE (1024 / 4)
|
||||||
|
/*
|
||||||
|
* (largest USB packet used / 4) + 1 for status information + 1 transfer complete +
|
||||||
|
* 1 location each for Bulk/Control endpoint for handling NAK/NYET scenario
|
||||||
|
*/
|
||||||
|
// #define CONFIG_USB_DWC2_RX_FIFO_SIZE ((1012 - CONFIG_USB_DWC2_NPTX_FIFO_SIZE - CONFIG_USB_DWC2_PTX_FIFO_SIZE) / 4)
|
||||||
|
|
||||||
|
/* ---------------- MUSB Configuration ---------------- */
|
||||||
|
// #define CONFIG_USB_MUSB_SUNXI
|
||||||
|
|
||||||
|
#define CONFIG_USB_EHCI_NXP (1)
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,275 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
|
||||||
|
* Copyright 2016 - 2017 NXP
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "usb.h"
|
||||||
|
#include "fsl_device_registers.h"
|
||||||
|
|
||||||
|
#include "usb_phy.h"
|
||||||
|
|
||||||
|
void *USB_EhciPhyGetBase(uint8_t controllerId)
|
||||||
|
{
|
||||||
|
void *usbPhyBase = NULL;
|
||||||
|
#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U))
|
||||||
|
#if defined(USBPHY_STACK_BASE_ADDRS)
|
||||||
|
uint32_t usbphy_base[] = USBPHY_STACK_BASE_ADDRS;
|
||||||
|
#else
|
||||||
|
uint32_t usbphy_base[] = USBPHY_BASE_ADDRS;
|
||||||
|
#endif
|
||||||
|
uint32_t *temp;
|
||||||
|
if (controllerId < (uint8_t)kUSB_ControllerEhci0)
|
||||||
|
{
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
if ((controllerId == (uint8_t)kUSB_ControllerEhci0) || (controllerId == (uint8_t)kUSB_ControllerEhci1))
|
||||||
|
{
|
||||||
|
controllerId = controllerId - (uint8_t)kUSB_ControllerEhci0;
|
||||||
|
}
|
||||||
|
else if ((controllerId == (uint8_t)kUSB_ControllerLpcIp3511Hs0) ||
|
||||||
|
(controllerId == (uint8_t)kUSB_ControllerLpcIp3511Hs1))
|
||||||
|
{
|
||||||
|
controllerId = controllerId - (uint8_t)kUSB_ControllerLpcIp3511Hs0;
|
||||||
|
}
|
||||||
|
else if ((controllerId == (uint8_t)kUSB_ControllerIp3516Hs0) || (controllerId == (uint8_t)kUSB_ControllerIp3516Hs1))
|
||||||
|
{
|
||||||
|
controllerId = controllerId - (uint8_t)kUSB_ControllerIp3516Hs0;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (controllerId < (sizeof(usbphy_base) / sizeof(usbphy_base[0])))
|
||||||
|
{
|
||||||
|
temp = (uint32_t *)usbphy_base[controllerId];
|
||||||
|
usbPhyBase = (void *)temp;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
return usbPhyBase;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief ehci phy initialization.
|
||||||
|
*
|
||||||
|
* This function initialize ehci phy IP.
|
||||||
|
*
|
||||||
|
* @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t.
|
||||||
|
* @param[in] freq the external input clock.
|
||||||
|
* for example: if the external input clock is 16M, the parameter freq should be 16000000.
|
||||||
|
*
|
||||||
|
* @retval kStatus_USB_Success cancel successfully.
|
||||||
|
* @retval kStatus_USB_Error the freq value is incorrect.
|
||||||
|
*/
|
||||||
|
uint32_t USB_EhciPhyInit(uint8_t controllerId, uint32_t freq, usb_phy_config_struct_t *phyConfig)
|
||||||
|
{
|
||||||
|
#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U))
|
||||||
|
USBPHY_Type *usbPhyBase;
|
||||||
|
|
||||||
|
usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId);
|
||||||
|
if (NULL == usbPhyBase)
|
||||||
|
{
|
||||||
|
return (uint8_t)kStatus_USB_Error;
|
||||||
|
}
|
||||||
|
|
||||||
|
#if ((defined FSL_FEATURE_SOC_ANATOP_COUNT) && (FSL_FEATURE_SOC_ANATOP_COUNT > 0U))
|
||||||
|
ANATOP->HW_ANADIG_REG_3P0.RW =
|
||||||
|
(ANATOP->HW_ANADIG_REG_3P0.RW &
|
||||||
|
(~(ANATOP_HW_ANADIG_REG_3P0_OUTPUT_TRG(0x1F) | ANATOP_HW_ANADIG_REG_3P0_ENABLE_ILIMIT_MASK))) |
|
||||||
|
ANATOP_HW_ANADIG_REG_3P0_OUTPUT_TRG(0x17) | ANATOP_HW_ANADIG_REG_3P0_ENABLE_LINREG_MASK;
|
||||||
|
ANATOP->HW_ANADIG_USB2_CHRG_DETECT.SET =
|
||||||
|
ANATOP_HW_ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B_MASK | ANATOP_HW_ANADIG_USB2_CHRG_DETECT_EN_B_MASK;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (defined USB_ANALOG)
|
||||||
|
USB_ANALOG->INSTANCE[controllerId - (uint8_t)kUSB_ControllerEhci0].CHRG_DETECT_SET =
|
||||||
|
USB_ANALOG_CHRG_DETECT_CHK_CHRG_B(1) | USB_ANALOG_CHRG_DETECT_EN_B(1);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if ((!(defined FSL_FEATURE_SOC_CCM_ANALOG_COUNT)) && (!(defined FSL_FEATURE_SOC_ANATOP_COUNT)))
|
||||||
|
|
||||||
|
usbPhyBase->TRIM_OVERRIDE_EN = 0x001fU; /* override IFR value */
|
||||||
|
#endif
|
||||||
|
usbPhyBase->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK; /* support LS device. */
|
||||||
|
usbPhyBase->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL3_MASK; /* support external FS Hub with LS device connected. */
|
||||||
|
/* PWD register provides overall control of the PHY power state */
|
||||||
|
usbPhyBase->PWD = 0U;
|
||||||
|
if (((uint8_t)kUSB_ControllerIp3516Hs0 == controllerId) || ((uint8_t)kUSB_ControllerIp3516Hs1 == controllerId) ||
|
||||||
|
((uint8_t)kUSB_ControllerLpcIp3511Hs0 == controllerId) ||
|
||||||
|
((uint8_t)kUSB_ControllerLpcIp3511Hs1 == controllerId))
|
||||||
|
{
|
||||||
|
usbPhyBase->CTRL_SET = USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK;
|
||||||
|
usbPhyBase->CTRL_SET = USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK;
|
||||||
|
}
|
||||||
|
if (NULL != phyConfig)
|
||||||
|
{
|
||||||
|
/* Decode to trim the nominal 17.78mA current source for the High Speed TX drivers on USB_DP and USB_DM. */
|
||||||
|
usbPhyBase->TX =
|
||||||
|
((usbPhyBase->TX & (~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK))) |
|
||||||
|
(USBPHY_TX_D_CAL(phyConfig->D_CAL) | USBPHY_TX_TXCAL45DP(phyConfig->TXCAL45DP) |
|
||||||
|
USBPHY_TX_TXCAL45DM(phyConfig->TXCAL45DM)));
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
return (uint8_t)kStatus_USB_Success;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief ehci phy initialization for suspend and resume.
|
||||||
|
*
|
||||||
|
* This function initialize ehci phy IP for suspend and resume.
|
||||||
|
*
|
||||||
|
* @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t.
|
||||||
|
* @param[in] freq the external input clock.
|
||||||
|
* for example: if the external input clock is 16M, the parameter freq should be 16000000.
|
||||||
|
*
|
||||||
|
* @retval kStatus_USB_Success cancel successfully.
|
||||||
|
* @retval kStatus_USB_Error the freq value is incorrect.
|
||||||
|
*/
|
||||||
|
uint32_t USB_EhciLowPowerPhyInit(uint8_t controllerId, uint32_t freq, usb_phy_config_struct_t *phyConfig)
|
||||||
|
{
|
||||||
|
#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U))
|
||||||
|
USBPHY_Type *usbPhyBase;
|
||||||
|
|
||||||
|
usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId);
|
||||||
|
if (NULL == usbPhyBase)
|
||||||
|
{
|
||||||
|
return (uint8_t)kStatus_USB_Error;
|
||||||
|
}
|
||||||
|
|
||||||
|
#if ((!(defined FSL_FEATURE_SOC_CCM_ANALOG_COUNT)) && (!(defined FSL_FEATURE_SOC_ANATOP_COUNT)))
|
||||||
|
usbPhyBase->TRIM_OVERRIDE_EN = 0x001fU; /* override IFR value */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if ((defined USBPHY_CTRL_AUTORESUME_EN_MASK) && (USBPHY_CTRL_AUTORESUME_EN_MASK > 0U))
|
||||||
|
usbPhyBase->CTRL_CLR |= USBPHY_CTRL_AUTORESUME_EN_MASK;
|
||||||
|
#else
|
||||||
|
usbPhyBase->CTRL |= USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK;
|
||||||
|
#endif
|
||||||
|
usbPhyBase->CTRL |= USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK | USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK;
|
||||||
|
usbPhyBase->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK; /* support LS device. */
|
||||||
|
usbPhyBase->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL3_MASK; /* support external FS Hub with LS device connected. */
|
||||||
|
/* PWD register provides overall control of the PHY power state */
|
||||||
|
usbPhyBase->PWD = 0U;
|
||||||
|
#if (defined USBPHY_ANACTRL_PFD_CLKGATE_MASK)
|
||||||
|
/* now the 480MHz USB clock is up, then configure fractional divider after PLL with PFD
|
||||||
|
* pfd clock = 480MHz*18/N, where N=18~35
|
||||||
|
* Please note that USB1PFDCLK has to be less than 180MHz for RUN or HSRUN mode
|
||||||
|
*/
|
||||||
|
usbPhyBase->ANACTRL |= USBPHY_ANACTRL_PFD_FRAC(24); /* N=24 */
|
||||||
|
usbPhyBase->ANACTRL |= USBPHY_ANACTRL_PFD_CLK_SEL(1); /* div by 4 */
|
||||||
|
|
||||||
|
usbPhyBase->ANACTRL &= ~USBPHY_ANACTRL_DEV_PULLDOWN_MASK;
|
||||||
|
usbPhyBase->ANACTRL &= ~USBPHY_ANACTRL_PFD_CLKGATE_MASK;
|
||||||
|
while (0U == (usbPhyBase->ANACTRL & USBPHY_ANACTRL_PFD_STABLE_MASK))
|
||||||
|
{
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
if (NULL != phyConfig)
|
||||||
|
{
|
||||||
|
/* Decode to trim the nominal 17.78mA current source for the High Speed TX drivers on USB_DP and USB_DM. */
|
||||||
|
usbPhyBase->TX =
|
||||||
|
((usbPhyBase->TX & (~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK))) |
|
||||||
|
(USBPHY_TX_D_CAL(phyConfig->D_CAL) | USBPHY_TX_TXCAL45DP(phyConfig->TXCAL45DP) |
|
||||||
|
USBPHY_TX_TXCAL45DM(phyConfig->TXCAL45DM)));
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
return (uint8_t)kStatus_USB_Success;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief ehci phy de-initialization.
|
||||||
|
*
|
||||||
|
* This function de-initialize ehci phy IP.
|
||||||
|
*
|
||||||
|
* @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t.
|
||||||
|
*/
|
||||||
|
void USB_EhciPhyDeinit(uint8_t controllerId)
|
||||||
|
{
|
||||||
|
#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U))
|
||||||
|
USBPHY_Type *usbPhyBase;
|
||||||
|
|
||||||
|
usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId);
|
||||||
|
if (NULL == usbPhyBase)
|
||||||
|
{
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
#if ((!(defined FSL_FEATURE_SOC_CCM_ANALOG_COUNT)) && (!(defined FSL_FEATURE_SOC_ANATOP_COUNT)))
|
||||||
|
usbPhyBase->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_POWER_MASK; /* power down PLL */
|
||||||
|
usbPhyBase->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK; /* disable USB clock output from USB PHY PLL */
|
||||||
|
#endif
|
||||||
|
usbPhyBase->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* set to 1U to gate clocks */
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief ehci phy disconnect detection enable or disable.
|
||||||
|
*
|
||||||
|
* This function enable/disable host ehci disconnect detection.
|
||||||
|
*
|
||||||
|
* @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t.
|
||||||
|
* @param[in] enable
|
||||||
|
* 1U - enable;
|
||||||
|
* 0U - disable;
|
||||||
|
*/
|
||||||
|
void USB_EhcihostPhyDisconnectDetectCmd(uint8_t controllerId, uint8_t enable)
|
||||||
|
{
|
||||||
|
#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U))
|
||||||
|
USBPHY_Type *usbPhyBase;
|
||||||
|
|
||||||
|
usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId);
|
||||||
|
if (NULL == usbPhyBase)
|
||||||
|
{
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (0U != enable)
|
||||||
|
{
|
||||||
|
usbPhyBase->CTRL |= USBPHY_CTRL_ENHOSTDISCONDETECT_MASK;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
usbPhyBase->CTRL &= (~USBPHY_CTRL_ENHOSTDISCONDETECT_MASK);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U))
|
||||||
|
#if ((defined FSL_FEATURE_USBHSD_HAS_EXIT_HS_ISSUE) && (FSL_FEATURE_USBHSD_HAS_EXIT_HS_ISSUE > 0U))
|
||||||
|
void USB_PhyDeviceForceEnterFSMode(uint8_t controllerId, uint8_t enable)
|
||||||
|
{
|
||||||
|
USBPHY_Type *usbPhyBase;
|
||||||
|
|
||||||
|
usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId);
|
||||||
|
if (NULL == usbPhyBase)
|
||||||
|
{
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (0U != enable)
|
||||||
|
{
|
||||||
|
uint32_t delay = 1000000;
|
||||||
|
usbPhyBase->DEBUG0_CLR = USBPHY_DEBUG0_CLKGATE_MASK;
|
||||||
|
while ((0U != (usbPhyBase->USB1_VBUS_DET_STAT & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK)) && (0U != delay))
|
||||||
|
{
|
||||||
|
delay--;
|
||||||
|
}
|
||||||
|
usbPhyBase->USB1_LOOPBACK_SET = USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
usbPhyBase->DEBUG0_CLR = USBPHY_DEBUG0_CLKGATE_MASK;
|
||||||
|
usbPhyBase->USB1_LOOPBACK_CLR = USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,105 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||||
|
* Copyright 2016 - 2017 NXP
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
#ifndef __USB_PHY_H__
|
||||||
|
#define __USB_PHY_H__
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Definitions
|
||||||
|
******************************************************************************/
|
||||||
|
typedef struct _usb_phy_config_struct
|
||||||
|
{
|
||||||
|
uint8_t D_CAL; /* Decode to trim the nominal 17.78mA current source */
|
||||||
|
uint8_t TXCAL45DP; /* Decode to trim the nominal 45-Ohm series termination resistance to the USB_DP output pin */
|
||||||
|
uint8_t TXCAL45DM; /* Decode to trim the nominal 45-Ohm series termination resistance to the USB_DM output pin */
|
||||||
|
} usb_phy_config_struct_t;
|
||||||
|
|
||||||
|
#if defined(__cplusplus)
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* API
|
||||||
|
******************************************************************************/
|
||||||
|
/*!
|
||||||
|
* @brief EHCI PHY get USB phy bass address.
|
||||||
|
*
|
||||||
|
* This function is used to get USB phy bass address.
|
||||||
|
*
|
||||||
|
* @param[in] controllerId EHCI controller ID; See the #usb_controller_index_t.
|
||||||
|
*
|
||||||
|
* @retval USB phy bass address.
|
||||||
|
*/
|
||||||
|
extern void *USB_EhciPhyGetBase(uint8_t controllerId);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief EHCI PHY initialization.
|
||||||
|
*
|
||||||
|
* This function initializes the EHCI PHY IP.
|
||||||
|
*
|
||||||
|
* @param[in] controllerId EHCI controller ID; See the #usb_controller_index_t.
|
||||||
|
* @param[in] freq The external input clock.
|
||||||
|
*
|
||||||
|
* @retval kStatus_USB_Success Cancel successfully.
|
||||||
|
* @retval kStatus_USB_Error The freq value is incorrect.
|
||||||
|
*/
|
||||||
|
extern uint32_t USB_EhciPhyInit(uint8_t controllerId, uint32_t freq, usb_phy_config_struct_t *phyConfig);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief ehci phy initialization for suspend and resume.
|
||||||
|
*
|
||||||
|
* This function initialize ehci phy IP for suspend and resume.
|
||||||
|
*
|
||||||
|
* @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t.
|
||||||
|
* @param[in] freq the external input clock.
|
||||||
|
* for example: if the external input clock is 16M, the parameter freq should be 16000000.
|
||||||
|
*
|
||||||
|
* @retval kStatus_USB_Success cancel successfully.
|
||||||
|
* @retval kStatus_USB_Error the freq value is incorrect.
|
||||||
|
*/
|
||||||
|
extern uint32_t USB_EhciLowPowerPhyInit(uint8_t controllerId, uint32_t freq, usb_phy_config_struct_t *phyConfig);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief EHCI PHY deinitialization.
|
||||||
|
*
|
||||||
|
* This function deinitializes the EHCI PHY IP.
|
||||||
|
*
|
||||||
|
* @param[in] controllerId EHCI controller ID; See #usb_controller_index_t.
|
||||||
|
*/
|
||||||
|
extern void USB_EhciPhyDeinit(uint8_t controllerId);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief EHCI PHY disconnect detection enable or disable.
|
||||||
|
*
|
||||||
|
* This function enable/disable the host EHCI disconnect detection.
|
||||||
|
*
|
||||||
|
* @param[in] controllerId EHCI controller ID; See #usb_controller_index_t.
|
||||||
|
* @param[in] enable
|
||||||
|
* 1U - enable;
|
||||||
|
* 0U - disable;
|
||||||
|
*/
|
||||||
|
extern void USB_EhcihostPhyDisconnectDetectCmd(uint8_t controllerId, uint8_t enable);
|
||||||
|
#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U))
|
||||||
|
#if ((defined FSL_FEATURE_USBHSD_HAS_EXIT_HS_ISSUE) && (FSL_FEATURE_USBHSD_HAS_EXIT_HS_ISSUE > 0U))
|
||||||
|
/*!
|
||||||
|
* @brief Force the PHY enter FS Mode
|
||||||
|
*
|
||||||
|
* on RT500 and RT600, the device doesn't enter FS Mode after vbus is invalide and the controller works as HS.
|
||||||
|
*
|
||||||
|
* @param[in] controllerId EHCI controller ID; See #usb_controller_index_t.
|
||||||
|
* @param[in] enable
|
||||||
|
* 1U - enable;
|
||||||
|
* 0U - disable;
|
||||||
|
*/
|
||||||
|
extern void USB_PhyDeviceForceEnterFSMode(uint8_t controllerId, uint8_t enable);
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
#if defined(__cplusplus)
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __USB_PHY_H__ */
|
||||||
Loading…
Reference in New Issue