diff --git a/bsp/upd70f3454/Backup of upd70f3454.ewp b/bsp/upd70f3454/Backup of upd70f3454.ewp new file mode 100644 index 0000000000..50ed3a04b6 --- /dev/null +++ b/bsp/upd70f3454/Backup of upd70f3454.ewp @@ -0,0 +1,1644 @@ + + + + 2 + + Debug + + V850 + + 1 + + General + 5 + + 5 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCV850 + 3 + + 14 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AV850 + 3 + + 5 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + XLINK + 3 + + 15 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + XAR + 3 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + V850 + + 0 + + General + 5 + + 5 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCV850 + 3 + + 14 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AV850 + 3 + + 5 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + XLINK + 3 + + 15 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + XAR + 3 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + +$PROJ_DIR$\applilet3_src\CG_main.c$PROJ_DIR$\applilet3_src\CG_systeminit.c$PROJ_DIR$\applilet3_src\CG_option.s85$PROJ_DIR$\applilet3_src\CG_system.c$PROJ_DIR$\applilet3_src\CG_system_user.c$PROJ_DIR$\applilet3_src\CG_port.c$PROJ_DIR$\applilet3_src\CG_port_user.c$PROJ_DIR$\applilet3_src\CG_serial.c$PROJ_DIR$\applilet3_src\CG_serial_user.c$PROJ_DIR$\applilet3_src\CG_timer.c$PROJ_DIR$\applilet3_src\CG_timer_user.c diff --git a/bsp/upd70f3454/Debug/Obj/CG_main.r85 b/bsp/upd70f3454/Debug/Obj/CG_main.r85 new file mode 100644 index 0000000000..1764cb9b8d Binary files /dev/null and b/bsp/upd70f3454/Debug/Obj/CG_main.r85 differ diff --git a/bsp/upd70f3454/Debug/Obj/CG_serial.r85 b/bsp/upd70f3454/Debug/Obj/CG_serial.r85 new file mode 100644 index 0000000000..62d0ec7fe9 Binary files /dev/null and b/bsp/upd70f3454/Debug/Obj/CG_serial.r85 differ diff --git a/bsp/upd70f3454/Debug/Obj/CG_serial_user.r85 b/bsp/upd70f3454/Debug/Obj/CG_serial_user.r85 new file mode 100644 index 0000000000..8da1da36c8 Binary files /dev/null and b/bsp/upd70f3454/Debug/Obj/CG_serial_user.r85 differ diff --git a/bsp/upd70f3454/Debug/Obj/upd70f3454.pbd b/bsp/upd70f3454/Debug/Obj/upd70f3454.pbd new file mode 100644 index 0000000000..b759a07eac --- /dev/null +++ b/bsp/upd70f3454/Debug/Obj/upd70f3454.pbd @@ -0,0 +1,43 @@ +This is an internal working file generated by the Source Browser. +10:24 01s +E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\CG_port.pbi +E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\CG_port_user.pbi +E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\CG_system.pbi +E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\CG_system_user.pbi +E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\CG_systeminit.pbi +E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\CG_timer.pbi +E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\CG_timer_user.pbi +E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\application.pbi +E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\board.pbi +E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\clock.pbi +E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\cmd.pbi +E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\device.pbi +E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\finsh_compiler.pbi +E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\finsh_error.pbi +E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\finsh_heap.pbi +E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\finsh_init.pbi +E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\finsh_node.pbi +E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\finsh_ops.pbi +E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\finsh_parser.pbi +E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\finsh_token.pbi +E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\finsh_var.pbi +E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\finsh_vm.pbi +E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\idle.pbi +E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\interrupt.pbi +E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\ipc.pbi +E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\irq.pbi +E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\kservice.pbi +E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\mem.pbi +E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\mempool.pbi +E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\module.pbi +E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\object.pbi +E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\rtm.pbi +E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\scheduler.pbi +E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\shell.pbi +E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\slab.pbi +E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\stack.pbi +E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\startup.pbi +E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\symbol.pbi +E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\thread.pbi +E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\timer.pbi +E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\uart.pbi diff --git a/bsp/upd70f3454/application.c b/bsp/upd70f3454/application.c new file mode 100644 index 0000000000..3901585f2d --- /dev/null +++ b/bsp/upd70f3454/application.c @@ -0,0 +1,62 @@ +/* + * File : application.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2009-01-05 Bernard the first version + * 2010-06-29 lgnq the first version + * + * For : NEC V850E + * Toolchain : IAR Embedded Workbench for V850 v3.71 +*/ + +#include +#include "board.h" +#include "CG_macrodriver.h" +#include "CG_system.h" +#include "CG_port.h" +#include "CG_timer.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "CG_userdefine.h" + +static struct rt_thread led; + +#if defined(__ICCM16C__) || defined(__ICCV850__) +#pragma data_alignment=4 +#endif +static rt_uint8_t led_stack[256]; + +static void rt_thread_entry_led(void* parameter) +{ + while (1) + { + /* led off */ + led_off(); + rt_thread_delay(20); /* sleep 1 second and switch to other thread */ + /* led on */ + led_on(); + rt_thread_delay(40); + } +} + +int rt_application_init(void) +{ + /* create led thread */ + rt_thread_init(&led, + "led", + rt_thread_entry_led, RT_NULL, + &led_stack[0], sizeof(led_stack), + 5, 32); + + if (&led != RT_NULL) + rt_thread_startup(&led); + + return 0; +} diff --git a/bsp/upd70f3454/applilet3_src/CG_macrodriver.h b/bsp/upd70f3454/applilet3_src/CG_macrodriver.h new file mode 100644 index 0000000000..748a140a20 --- /dev/null +++ b/bsp/upd70f3454/applilet3_src/CG_macrodriver.h @@ -0,0 +1,110 @@ +/* +******************************************************************************* +* Copyright(C) NEC Electronics Corporation 2010 +* All rights reserved by NEC Electronics Corporation. +* This program should be used on your own responsibility. +* NEC Electronics Corporation assumes no responsibility for any losses +* incurred by customers or third parties arising from the use of this file. +* +* This device driver was created by Applilet3 for V850ES/Jx3 +* 32-Bit Single-Chip Microcontrollers +* Filename: CG_macrodriver.h +* Abstract: This file implements general head file. +* APIlib: Applilet3 for V850ES/Jx3 V2.01 [20 Apr 2010] +* Device: uPD70F3746 +* Compiler: IAR Systems ICCV850 +* Creation date: 6/26/2010 +******************************************************************************* +*/ + +#ifndef _MDSTATUS_ +#define _MDSTATUS_ +/* +******************************************************************************* +** Include files +******************************************************************************* +*/ +#include +#include "io70f3454.h" +/* +******************************************************************************* +** Register bit define +******************************************************************************* +*/ +/* +******************************************************************************* +** Macro define +******************************************************************************* +*/ +#define DI __disable_interrupt +#define EI __enable_interrupt +#define NOP __no_operation +#define HALT __halt + +/* Data type defintion */ +typedef unsigned long ULONG; +typedef signed long SLONG; + +typedef unsigned int UINT; +typedef signed int SINT; + +typedef unsigned short USHORT; +typedef signed short SHORT; + +typedef unsigned char UCHAR; +typedef signed char SCHAR; + +typedef unsigned char BOOL; +typedef unsigned short MD_STATUS; + +#define MD_ON 1U +#define MD_OFF 0U + +#define MD_TRUE 1U +#define MD_FALSE 0U + +#define MD_SET 1U +#define MD_CLEAR 0U + +/* Status list definition */ +#define MD_STATUSBASE 0x00U +#define MD_OK (MD_STATUSBASE + 0x00U) /* register setting OK */ +#define MD_RESET (MD_STATUSBASE + 0x01U) /* reset input */ +#define MD_SENDCOMPLETE (MD_STATUSBASE + 0x02U) /* send data complete */ +#define MD_ADDRESSMATCH (MD_STATUSBASE + 0x03U) /* IIC slave address match */ +#define MD_OVF (MD_STATUSBASE + 0x04U) /* timer count overflow */ +#define MD_SPT (MD_STATUSBASE + 0x07U) /* IIC stop */ +#define MD_NACK (MD_STATUSBASE + 0x08U) /* IIC no ACK */ +#define MD_SLAVE_SEND_END (MD_STATUSBASE + 0x09U) /* IIC slave send end */ +#define MD_SLAVE_RCV_END (MD_STATUSBASE + 0x0AU) /* IIC slave receive end */ +#define MD_MASTER_SEND_END (MD_STATUSBASE + 0x0BU) /* IIC master send end */ +#define MD_MASTER_RCV_END (MD_STATUSBASE + 0x0CU) /* IIC master receive end */ +#define MD_UNDEREXEC (MD_STATUSBASE + 0x0DU) /* DMA transfer under execute */ +#define MD_COMPLETED (MD_STATUSBASE + 0x0EU) /* DMA transfer completed */ +#define MD_BUSY1 (MD_STATUSBASE + 0x0FU) /* busy 1 */ +#define MD_BUSY2 (MD_STATUSBASE + 0x10U) /* busy 2 */ + +/* Error list definition */ +#define MD_ERRORBASE 0x80U +#define MD_ERROR (MD_ERRORBASE + 0x00U) /* error */ +#define MD_RESOURCEERROR (MD_ERRORBASE + 0x01U) /* no resource available */ +#define MD_PARITYERROR (MD_ERRORBASE + 0x02U) /* UARTn parity error n=0,1,2 */ +#define MD_OVERRUNERROR (MD_ERRORBASE + 0x03U) /* UARTn overrun error n=0,1,2 */ +#define MD_FRAMEERROR (MD_ERRORBASE + 0x04U) /* UARTn frame error n=0,1,2 */ +#define MD_ARGERROR (MD_ERRORBASE + 0x05U) /* Error agrument input error */ +#define MD_TIMINGERROR (MD_ERRORBASE + 0x06U) /* Error timing operation error */ +#define MD_SETPROHIBITED (MD_ERRORBASE + 0x07U) /* setting prohibited */ +#define MD_ODDBUF (MD_ERRORBASE + 0x08U) /* in 16bit transfer mode,buffer size should be even */ +#define MD_DATAEXISTS (MD_ERRORBASE + 0x09U) /* Data to be transferred next exists in TXBn register */ +#define MD_STSERROR (MD_ERRORBASE + 0x0AU) /* CAN status error */ +#define MD_ALRDYSTART (MD_ERRORBASE + 0x0BU) /* CAN-controller is already started error */ +#define MD_NOMSG (MD_ERRORBASE + 0x0CU) /* CAN message not received */ +#define MD_ERROR1 (MD_ERRORBASE + 0x0DU) /* error 1 */ +#define MD_ERROR2 (MD_ERRORBASE + 0x0EU) /* error 2 */ +/* +******************************************************************************* +** Function define +******************************************************************************* +*/ + +#endif diff --git a/bsp/upd70f3454/applilet3_src/CG_port.c b/bsp/upd70f3454/applilet3_src/CG_port.c new file mode 100644 index 0000000000..526f163f5a --- /dev/null +++ b/bsp/upd70f3454/applilet3_src/CG_port.c @@ -0,0 +1,71 @@ +/* +******************************************************************************* +* Copyright(C) NEC Electronics Corporation 2010 +* All rights reserved by NEC Electronics Corporation. +* This program should be used on your own responsibility. +* NEC Electronics Corporation assumes no responsibility for any losses +* incurred by customers or third parties arising from the use of this file. +* +* This device driver was created by Applilet3 for V850ES/Jx3 +* 32-Bit Single-Chip Microcontrollers +* Filename: CG_port.c +* Abstract: This file implements device driver for PORT module. +* APIlib: Applilet3 for V850ES/Jx3 V2.01 [20 Apr 2010] +* Device: uPD70F3746 +* Compiler: IAR Systems ICCV850 +* Creation date: 6/26/2010 +******************************************************************************* +*/ + +/* +******************************************************************************* +** Include files +******************************************************************************* +*/ +#include "CG_macrodriver.h" +#include "CG_port.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "CG_userdefine.h" + +/* +******************************************************************************* +** Global define +******************************************************************************* +*/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/* +**----------------------------------------------------------------------------- +** +** Abstract: +** This function initializes setting for Port I/O. +** +** Parameters: +** None +** +** Returns: +** None +** +**----------------------------------------------------------------------------- +*/ +void PORT_Init(void) +{ + PDLH = _10_Pn4_OUTPUT_1; + PMDLH = _01_PMn0_MODE_UNUSED | _02_PMn1_MODE_UNUSED | _04_PMn2_MODE_UNUSED | _08_PMn3_MODE_UNUSED | _00_PMn4_MODE_OUTPUT | _20_PMn5_MODE_UNUSED | _40_PMn6_MODE_UNUSED | _80_PMn7_MODE_UNUSED; + PMCDLH = _00_PMCn4_OPER_PORT; +} + +void led_on(void) +{ + PDLH = _10_Pn4_OUTPUT_1; +} + +void led_off(void) +{ + PDLH = _00_Pn4_OUTPUT_0; +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/bsp/upd70f3454/applilet3_src/CG_port.h b/bsp/upd70f3454/applilet3_src/CG_port.h new file mode 100644 index 0000000000..91328c9661 --- /dev/null +++ b/bsp/upd70f3454/applilet3_src/CG_port.h @@ -0,0 +1,130 @@ +/* +******************************************************************************* +* Copyright(C) NEC Electronics Corporation 2010 +* All rights reserved by NEC Electronics Corporation. +* This program should be used on your own responsibility. +* NEC Electronics Corporation assumes no responsibility for any losses +* incurred by customers or third parties arising from the use of this file. +* +* This device driver was created by Applilet3 for V850ES/Jx3 +* 32-Bit Single-Chip Microcontrollers +* Filename: CG_port.h +* Abstract: This file implements device driver for PORT module. +* APIlib: Applilet3 for V850ES/Jx3 V2.01 [20 Apr 2010] +* Device: uPD70F3746 +* Compiler: IAR Systems ICCV850 +* Creation date: 6/26/2010 +******************************************************************************* +*/ + +#ifndef _MDPORT_ +#define _MDPORT_ +/* +******************************************************************************* +** Register bit define +******************************************************************************* +*/ +/* Port mode control register (PMCn.7 - PMCn.0) */ +#define _00_PMCn0_OPER_PORT 0x00U /* Pn0 as port mode */ +#define _00_PMCn1_OPER_PORT 0x00U /* Pn1 as port mode */ +#define _00_PMCn2_OPER_PORT 0x00U /* Pn2 as port mode */ +#define _00_PMCn3_OPER_PORT 0x00U /* Pn3 as port mode */ +#define _00_PMCn4_OPER_PORT 0x00U /* Pn4 as port mode */ +#define _00_PMCn5_OPER_PORT 0x00U /* Pn5 as port mode */ +#define _00_PMCn6_OPER_PORT 0x00U /* Pn6 as port mode */ +#define _00_PMCn7_OPER_PORT 0x00U /* Pn7 as port mode */ +#define _01_PMCn0_OPER_ALTER 0x01U /* Pn0 as alternative mode */ +#define _02_PMCn1_OPER_ALTER 0x02U /* Pn1 as alternative mode */ +#define _04_PMCn2_OPER_ALTER 0x04U /* Pn2 as alternative mode */ +#define _08_PMCn3_OPER_ALTER 0x08U /* Pn3 as alternative mode */ +#define _10_PMCn4_OPER_ALTER 0x10U /* Pn4 as alternative mode */ +#define _20_PMCn5_OPER_ALTER 0x20U /* Pn5 as alternative mode */ +#define _40_PMCn6_OPER_ALTER 0x40U /* Pn6 as alternative mode */ +#define _80_PMCn7_OPER_ALTER 0x80U /* Pn7 as alternative mode */ +#define _00_PMCn0_OPER_OCD 0x00U /* PMC0 for MINI2 */ + +/* Port mode register (PMn.7 - PMn.0) */ +#define _01_PMn0_MODE_INPUT 0x01U /* Pn0 as input mode */ +#define _02_PMn1_MODE_INPUT 0x02U /* Pn1 as input mode */ +#define _04_PMn2_MODE_INPUT 0x04U /* Pn2 as input mode */ +#define _08_PMn3_MODE_INPUT 0x08U /* Pn3 as input mode */ +#define _10_PMn4_MODE_INPUT 0x10U /* Pn4 as input mode */ +#define _20_PMn5_MODE_INPUT 0x20U /* Pn5 as input mode */ +#define _40_PMn6_MODE_INPUT 0x40U /* Pn6 as input mode */ +#define _80_PMn7_MODE_INPUT 0x80U /* Pn7 as input mode */ +#define _00_PMn0_MODE_OUTPUT 0x00U /* Pn0 as output mode */ +#define _00_PMn1_MODE_OUTPUT 0x00U /* Pn1 as output mode */ +#define _00_PMn2_MODE_OUTPUT 0x00U /* Pn2 as output mode */ +#define _00_PMn3_MODE_OUTPUT 0x00U /* Pn3 as output mode */ +#define _00_PMn4_MODE_OUTPUT 0x00U /* Pn4 as output mode */ +#define _00_PMn5_MODE_OUTPUT 0x00U /* Pn5 as output mode */ +#define _00_PMn6_MODE_OUTPUT 0x00U /* Pn6 as output mode */ +#define _00_PMn7_MODE_OUTPUT 0x00U /* Pn7 as output mode */ +#define _01_PMn0_MODE_UNUSED 0x01U /* Pn0 as default mode */ +#define _02_PMn1_MODE_UNUSED 0x02U /* Pn1 as default mode */ +#define _04_PMn2_MODE_UNUSED 0x04U /* Pn2 as default mode */ +#define _08_PMn3_MODE_UNUSED 0x08U /* Pn3 as default mode */ +#define _10_PMn4_MODE_UNUSED 0x10U /* Pn4 as default mode */ +#define _20_PMn5_MODE_UNUSED 0x20U /* Pn5 as default mode */ +#define _40_PMn6_MODE_UNUSED 0x40U /* Pn6 as default mode */ +#define _80_PMn7_MODE_UNUSED 0x80U /* Pn7 as default mode */ +#define _00_PMn0_MODE_OCD 0x00U /* PMC0 for MINI2 */ + +/* Port register (Pn.7 - Pn.0) */ +#define _00_Pn0_OUTPUT_0 0x00U /* Pn0 output 0 */ +#define _00_Pn1_OUTPUT_0 0x00U /* Pn1 output 0 */ +#define _00_Pn2_OUTPUT_0 0x00U /* Pn2 output 0 */ +#define _00_Pn3_OUTPUT_0 0x00U /* Pn3 output 0 */ +#define _00_Pn4_OUTPUT_0 0x00U /* Pn4 output 0 */ +#define _00_Pn5_OUTPUT_0 0x00U /* Pn5 output 0 */ +#define _00_Pn6_OUTPUT_0 0x00U /* Pn6 output 0 */ +#define _00_Pn7_OUTPUT_0 0x00U /* Pn7 output 0 */ +#define _01_Pn0_OUTPUT_1 0x01U /* Pn0 output 1 */ +#define _02_Pn1_OUTPUT_1 0x02U /* Pn1 output 1 */ +#define _04_Pn2_OUTPUT_1 0x04U /* Pn2 output 1 */ +#define _08_Pn3_OUTPUT_1 0x08U /* Pn3 output 1 */ +#define _10_Pn4_OUTPUT_1 0x10U /* Pn4 output 1 */ +#define _20_Pn5_OUTPUT_1 0x20U /* Pn5 output 1 */ +#define _40_Pn6_OUTPUT_1 0x40U /* Pn6 output 1 */ +#define _80_Pn7_OUTPUT_1 0x80U /* Pn7 output 1 */ + +/* Function register resistor (PFn.7 - PFn.0) */ +#define _00_PFn0_FUN_NORMAL 0x00U /* Pn0 normal output */ +#define _00_PFn1_FUN_NORMAL 0x00U /* Pn1 normal output */ +#define _00_PFn2_FUN_NORMAL 0x00U /* Pn2 normal output */ +#define _00_PFn3_FUN_NORMAL 0x00U /* Pn3 normal output */ +#define _00_PFn4_FUN_NORMAL 0x00U /* Pn4 normal output */ +#define _00_PFn5_FUN_NORMAL 0x00U /* Pn5 normal output */ +#define _00_PFn6_FUN_NORMAL 0x00U /* Pn6 normal output */ +#define _00_PFn7_FUN_NORMAL 0x00U /* Pn7 normal output */ +#define _01_PFn0_FUN_OPEN 0x01U /* Pn0 open-drain output */ +#define _02_PFn1_FUN_OPEN 0x02U /* Pn1 open-drain output */ +#define _04_PFn2_FUN_OPEN 0x04U /* Pn2 open-drain output */ +#define _08_PFn3_FUN_OPEN 0x08U /* Pn3 open-drain output */ +#define _10_PFn4_FUN_OPEN 0x10U /* Pn4 open-drain output */ +#define _20_PFn5_FUN_OPEN 0x20U /* Pn5 open-drain output */ +#define _40_PFn6_FUN_OPEN 0x40U /* Pn6 open-drain output */ +#define _80_PFn7_FUN_OPEN 0x80U /* Pn7 open-drain output */ +/* +******************************************************************************* +** Macro define +******************************************************************************* +*/ +#define _80_PM0_DEFAULT 0x80U /* PM0 default value */ +#define _FC_PM1_DEFAULT 0xFCU /* PM1 default value */ +#define _FC_PM3H_DEFAULT 0xFCU /* PM3H default value */ +#define _F8_PM4_DEFAULT 0xF8U /* PM4 default value */ +#define _C0_PM5_DEFAULT 0xC0U /* PM5 default value */ +#define _FC_PM8_DEFAULT 0xFCU /* PM8 default value */ +#define _F0_PMCD_DEFAULT 0xF0U /* PMCD default value */ +/* +******************************************************************************* +** Function define +******************************************************************************* +*/ +void PORT_Init(void); +void led_on(void); +void led_off(void); +/* Start user code for function. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#endif diff --git a/bsp/upd70f3454/applilet3_src/CG_port_user.c b/bsp/upd70f3454/applilet3_src/CG_port_user.c new file mode 100644 index 0000000000..d44e5fa283 --- /dev/null +++ b/bsp/upd70f3454/applilet3_src/CG_port_user.c @@ -0,0 +1,41 @@ +/* +******************************************************************************* +* Copyright(C) NEC Electronics Corporation 2010 +* All rights reserved by NEC Electronics Corporation. +* This program should be used on your own responsibility. +* NEC Electronics Corporation assumes no responsibility for any losses +* incurred by customers or third parties arising from the use of this file. +* +* This device driver was created by Applilet3 for V850ES/Jx3 +* 32-Bit Single-Chip Microcontrollers +* Filename: CG_port_user.c +* Abstract: This file implements device driver for PORT module. +* APIlib: Applilet3 for V850ES/Jx3 V2.01 [20 Apr 2010] +* Device: uPD70F3746 +* Compiler: IAR Systems ICCV850 +* Creation date: 6/26/2010 +******************************************************************************* +*/ + +/* +******************************************************************************* +** Include files +******************************************************************************* +*/ +#include "CG_macrodriver.h" +#include "CG_port.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "CG_userdefine.h" + +/* +******************************************************************************* +** Global define +******************************************************************************* +*/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/bsp/upd70f3454/applilet3_src/CG_system.c b/bsp/upd70f3454/applilet3_src/CG_system.c new file mode 100644 index 0000000000..441048a5fa --- /dev/null +++ b/bsp/upd70f3454/applilet3_src/CG_system.c @@ -0,0 +1,113 @@ +/* +******************************************************************************* +* Copyright(C) NEC Electronics Corporation 2010 +* All rights reserved by NEC Electronics Corporation. +* This program should be used on your own responsibility. +* NEC Electronics Corporation assumes no responsibility for any losses +* incurred by customers or third parties arising from the use of this file. +* +* This device driver was created by Applilet3 for V850ES/Jx3 +* 32-Bit Single-Chip Microcontrollers +* Filename: CG_system.c +* Abstract: This file implements device driver for System module. +* APIlib: Applilet3 for V850ES/Jx3 V2.01 [20 Apr 2010] +* Device: uPD70F3746 +* Compiler: IAR Systems ICCV850 +* Creation date: 6/26/2010 +******************************************************************************* +*/ + +/* +******************************************************************************* +** Include files +******************************************************************************* +*/ +#include "CG_macrodriver.h" +#include "CG_system.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "CG_userdefine.h" + +/* +******************************************************************************* +** Global define +******************************************************************************* +*/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +void clock_pll_mode(void) +{ + /* CPU operation clock selection */ + /* Set PLL mode. */ + PLLCTL = 0x03; /* bit 1: CPU clock selection (PLL mode/clock-through mode selection) */ + /* 1: PLL mode, 0: Clock-through mode */ + + __asm("_loop: set1 1,0xF82C[r0]"); //__IO_REG8_BIT( PLLCTL, 0xFFFFF82C, __READ_WRITE ) + __asm(" tst1 1,0xF82C[r0]"); //__IO_REG8_BIT( PLLCTL, 0xFFFFF82C, __READ_WRITE ) + __asm(" bz _loop"); + + return; +} + +void clock_pcc_mode(void) +{ + /* DMA is forcibly terminated in this sample since DMA transfer must be terminated + before data is set to a special register. */ + + if(TC0 == 0 && E00 == 1){ /* DMA0 transfer judgment */ + INIT0 = 1; /* DMA0 forcible termination */ + } + if(TC1 == 0 && E11 == 1){ /* DMA1 transfer judgment */ + INIT1 = 1; /* DMA1 forcible termination */ + } + if(TC2 == 0 && E22 == 1){ /* DMA2 transfer judgment */ + INIT2 = 1; /* DMA2 forcible termination */ + } + if(TC3 == 0 && E33 == 1){ /* DMA3 transfer judgment */ + INIT3 = 1; /* DMA3 forcible termination */ + } + + /* The PCC register is a special register. Data can be written to this register only in a combination of specific sequences. */ + /* bit 1, bit 0: Clock selection, 11: fxx/8, 10: fxx/4, 01: fxx/2, 00: fxx */ + /* Clock selection: fxx */ + __asm("mov 0x00, r10"); /* Set general-purpose register data to be set to special register. */ + __asm("st.b r10, 0xF1FC[r0]"); /* Write to PRCMD register. */ //__IO_REG8(PRCMD, 0xFFFFF1FC, __WRITE) + __asm("st.b r10, 0xF828[r0]"); /* Set PCC register. */ //__IO_REG8_BIT(PCC, 0xFFFFF828, __READ_WRITE) + __asm("nop"); /* Insert five or more NOP instructions. */ + __asm("nop"); + __asm("nop"); + __asm("nop"); + __asm("nop"); + + return; +} + +/* +**----------------------------------------------------------------------------- +** +** Abstract: +** This function initializes the clock generator module. +** +** Parameters: +** None +** +** Returns: +** None +** +**----------------------------------------------------------------------------- +*/ +void CLOCK_Init(void) +{ + DI(); /* Maskable interrupt disabled */ + + do{ + clock_pll_mode(); /* PLL mode setting function */ + + clock_pcc_mode(); /* PCC register setting function */ + + }while(PRERR); /* Written in correct sequence? */ +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/bsp/upd70f3454/applilet3_src/CG_system.h b/bsp/upd70f3454/applilet3_src/CG_system.h new file mode 100644 index 0000000000..0413bb3896 --- /dev/null +++ b/bsp/upd70f3454/applilet3_src/CG_system.h @@ -0,0 +1,172 @@ +/* +******************************************************************************* +* Copyright(C) NEC Electronics Corporation 2010 +* All rights reserved by NEC Electronics Corporation. +* This program should be used on your own responsibility. +* NEC Electronics Corporation assumes no responsibility for any losses +* incurred by customers or third parties arising from the use of this file. +* +* This device driver was created by Applilet3 for V850ES/Jx3 +* 32-Bit Single-Chip Microcontrollers +* Filename: CG_system.h +* Abstract: This file implements device driver for System module. +* APIlib: Applilet3 for V850ES/Jx3 V2.01 [20 Apr 2010] +* Device: uPD70F3746 +* Compiler: IAR Systems ICCV850 +* Creation date: 6/26/2010 +******************************************************************************* +*/ + +#ifndef _MDSYSTEM_ +#define _MDSYSTEM_ +/* +******************************************************************************* +** Register bit define +******************************************************************************* +*/ +/* + Processor clock control register (PCC) +*/ +#define _03_CG_PCC_INITIALVALUE 0x03U +/* Use of subclock on-chip feedback resistor (FRC) */ +#define _00_CG_SUBCLK_FEEDBACK_USE 0x00U /* subclock on-chip feedback resistor connected */ +#define _08_CG_SUBCLK_FEEDBACK_UNUSE 0x80U /* subclock on-chip feedback resistor not connected */ +/* Main clock osillator control (MCK) */ +#define _00_CG_MAINCLK_ENABLE 0x00U /* main clock oscillation enabled */ +#define _04_CG_MAINCLK_STOP 0x40U /* main clock oscillation stopped */ +/* Use of main clock on-chip feedback resistor (MFRC) */ +#define _00_CG_MAINCLK_FEEDBACK_USE 0x00U /* main clock feedback resistor connected */ +#define _20_CG_MAINCLK_FEEDBACK_UNUSE 0x20U /* main clock feedback resistor not connected */ +/* Status of CPU clock fCPU (CLS) */ +#define _00_CG_CPUCLK_MAINCLK 0x00U /* main clock operation */ +#define _10_CG_CPUCLK_SUBCLK 0x10U /* subclock operation */ +/* Clock(fCLK/fCPU) selection (CK3 - CK0) */ +#define _0F_CG_CPUCLK 0x0FU +#define _00_CG_CPUCLK_MAIN0 0x00U /* fCPU = fXX */ +#define _01_CG_CPUCLK_MAIN1 0x01U /* fCPU = fXX/2 */ +#define _02_CG_CPUCLK_MAIN2 0x02U /* fCPU = fXX/2^2 */ +#define _03_CG_CPUCLK_MAIN3 0x03U /* fCPU = fXX/2^3 */ +#define _04_CG_CPUCLK_MAIN4 0x04U /* fCPU = fXX/2^4 */ +#define _05_CG_CPUCLK_MAIN5 0x05U /* fCPU = fXX/2^5 */ +#define _0B_CG_CPUCLK_SUB 0x0BU /* fXT */ + +/* + Internal oscillator mode register (RCM) +*/ +/* Oscillation/stop of internal oscillator (RSTOP) */ +#define _00_CG_INTER_OSC_ON 0x00U /* internal oscillator oscillation */ +#define _01_CG_INTER_OSC_OFF 0x01U /* internal oscillator stopped */ + +/* + CPU operation clock status register (CCLS) +*/ +/* CPU operation clock status (CCLSF) */ +#define _00_CG_CPUCLK_STATUS_MAINORSUB 0x00U /* operating on main clock(fX) or subclock(fXT) */ +#define _01_CG_CPUCLK_STATUS_INTEROSC 0x01U /* operating on internal oscillation clock(fR) */ + +/* + Lock register (LOCKR) +*/ +/* PLL lock status check (LOCK) */ +#define _00_CG_PLLSTATUS_LOCK 0x00U /* locked status */ +#define _01_CG_PLLSTATUS_UNLOCK 0x01U /* unlocked status */ + +/* + PLL control register (PLLCTL) +*/ +#define _01_CG_PLLCTL_INITIALVALUE 0x01U +/* CPU operation clock selection register (SELPLL) */ +#define _00_CG_CPUCLK_CLKTHROUGH 0x00U /* clock-through mode */ +#define _02_CG_CPUCLK_PLL 0x02U /* PLL mode */ +/* PLL operation stop register (PLLON) */ +#define _00_CG_CPUCLK_PLLOFF 0x00U /* PLL stopped */ +#define _01_CG_CPUCLK_PLLON 0x01U /* PLL operating */ + +/* + Clock control register (CKC) +*/ +#define _0A_CG_CKC_INITIALVALUE 0x0AU +/* Internal system clock(fXX) in PLL mode */ +#define _00_CG_CPUCLK_4PLL 0x00U /* fXX = 4* fX (fX = 2.5 to 5.0 MHz) */ +#define _01_CG_CPUCLK_8PLL 0x01U /* fXX = 8* fX (fX = 2.5 to 4.0 MHz) */ + +/* + PLL lockup time specification register (PLLS) +*/ +#define _03_CG_PLLS_INITIALVALUE 0x03U +/* PLL lockup time selection (PLLS2 - PLLS0) */ +#define _00_CG_PLLLOCKUP_SEL0 0x00U /* 2^10/fX */ +#define _01_CG_PLLLOCKUP_SEL1 0x01U /* 2^11/fX*/ +#define _02_CG_PLLLOCKUP_SEL2 0x02U /* 2^12/fX */ +#define _03_CG_PLLLOCKUP_SEL3 0x03U /* 2^13/fX (default value) */ + +/* + Power save control register (PSC) +*/ +/* Stand-by mode release control by occurrence of INTWDT2 signal (NMI1M) */ +#define _00_CG_STANDBY_INTWDT2EN 0x00U /* enable releasing stand-by mode by INTWDT2 signal */ +#define _40_CG_STANDBY_INTWDT2DIS 0x40U /* disable releasing stand-by mode by INTWDT2 signal */ +/* Stand-by mode release control by NMI pin input (NMI0M) */ +#define _00_CG_STANDBY_NMIEN 0x00U /* enable releasing stand-by mode by NMI pin input */ +#define _20_CG_STANDBY_NMIDIS 0x20U /* disable releasing stand-by mode by NMI pin input */ +/* Stand-by mode release control by maskable interrupt request signal (NMI0M) */ +#define _00_CG_STANDBY_MASKIEN 0x00U /* enable releasing stand-by mode by maskable interrupt request signal */ +#define _10_CG_STANDBY_MASKIDIS 0x10U /* disable releasing stand-by mode by maskable interrupt request signal */ +/* Setting of stand-by mode (STP) */ +#define _00_CG_STANDBY_UNUSE 0x00U /* normal mode */ +#define _02_CG_STANDBY_USE 0x02U /* stand-by mode */ + +/* + Power save mode control register (PSMR) +*/ +/* Specification of operation in software stand-by mode (PSM1,PSM0) */ +#define _00_CG_POWERSAVE_IDLE1 0x00U /* IDLE1, sub-IDLE modes */ +#define _01_CG_POWERSAVE_STOP1 0x01U /* STOP, sub-IDLE modes */ +#define _02_CG_POWERSAVE_IDLE2 0x02U /* IDLE2, sub-IDLE modes */ +#define _03_CG_POWERSAVE_STOP2 0x03U /* STOP mode */ + +/* + Clock monitor mode register (CLM) +*/ +/* Clock monitor operation enable or disable (CLME) */ +#define _01_CG_MONITOR_ENABLE 0x01U /* enable clock monitor operation */ +#define _00_CG_MONITOR_DISABLE 0x00U /* disable clock monitor operation */ + +/* + Watchdog Timer 2 mode register (WDTM2) +*/ +/* Selection of operation mode (WDM21, WDM20) */ +#define _00_WDT2_OPERMODE_STOP 0x00U /* stops operation */ +#define _20_WDT2_OPERMODE_NONMASK 0x20U /* non-maskable interrupt request mode (generation of INTWDT2) */ +#define _40_WDT2_OPERMODE_RESET 0x40U /* reset mode (generation of RESWDT2) */ +/* Selection of clock mode (WDCS24,WDCS23) */ +#define _00_WDT2_CLKMODE_INTEROSC 0x00U /* use internal oscillator */ +#define _08_WDT2_CLKMODE_MAINCLK 0x08U /* use Main clock */ +#define _10_WDT2_CLKMODE_SUBCLK 0x10U /* use subclock */ +/* Watchdog Timer 2 clock Selection (WDCS22 - WDCS20) */ +#define _00_WDT2_CLOCK_SEL0 0x00U /* 2^12/fR or 2^18/fXX or 2^9/fXT */ +#define _01_WDT2_CLOCK_SEL1 0x01U /* 2^13/fR or 2^19/fXX or 2^10/fXT */ +#define _02_WDT2_CLOCK_SEL2 0x02U /* 2^14/fR or 2^20/fXX or 2^11/fXT */ +#define _03_WDT2_CLOCK_SEL3 0x03U /* 2^15/fR or 2^21/fXX or 2^12/fXT */ +#define _04_WDT2_CLOCK_SEL4 0x04U /* 2^16/fR or 2^22/fXX or 2^13/fXT */ +#define _05_WDT2_CLOCK_SEL5 0x05U /* 2^17/fR or 2^23/fXX or 2^14/fXT */ +#define _06_WDT2_CLOCK_SEL6 0x06U /* 2^18/fR or 2^24/fXX or 2^15/fXT */ +#define _07_WDT2_CLOCK_SEL7 0x07U /* 2^19/fR or 2^25/fXX or 2^16/fXT */ +/* +******************************************************************************* +** Macro define +******************************************************************************* +*/ +#define _00_CG_VSWC_VALUE 0x00U +/* +******************************************************************************* +** Function define +******************************************************************************* +*/ +void CLOCK_Init(void); +void WDT2_Restart(void); +void CG_ReadResetSource(void); + +/* Start user code for function. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#endif diff --git a/bsp/upd70f3454/applilet3_src/CG_system_user.c b/bsp/upd70f3454/applilet3_src/CG_system_user.c new file mode 100644 index 0000000000..6b64abd79e --- /dev/null +++ b/bsp/upd70f3454/applilet3_src/CG_system_user.c @@ -0,0 +1,62 @@ +/* +******************************************************************************* +* Copyright(C) NEC Electronics Corporation 2010 +* All rights reserved by NEC Electronics Corporation. +* This program should be used on your own responsibility. +* NEC Electronics Corporation assumes no responsibility for any losses +* incurred by customers or third parties arising from the use of this file. +* +* This device driver was created by Applilet3 for V850ES/Jx3 +* 32-Bit Single-Chip Microcontrollers +* Filename: CG_system_user.c +* Abstract: This file implements device driver for System module. +* APIlib: Applilet3 for V850ES/Jx3 V2.01 [20 Apr 2010] +* Device: uPD70F3746 +* Compiler: IAR Systems ICCV850 +* Creation date: 6/26/2010 +******************************************************************************* +*/ + +/* +******************************************************************************* +** Include files +******************************************************************************* +*/ +#include "CG_macrodriver.h" +#include "CG_system.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "CG_userdefine.h" + +/* +******************************************************************************* +** Global define +******************************************************************************* +*/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/* +**----------------------------------------------------------------------------- +** +** Abstract: +** This function processes of Reset. +** +** Parameters: +** None +** +** Returns: +** None +** +**----------------------------------------------------------------------------- +*/ +void CG_ReadResetSource( void ) +{ + UCHAR resetflag = RESF; + + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/bsp/upd70f3454/applilet3_src/CG_systeminit.c b/bsp/upd70f3454/applilet3_src/CG_systeminit.c new file mode 100644 index 0000000000..78b6fba073 --- /dev/null +++ b/bsp/upd70f3454/applilet3_src/CG_systeminit.c @@ -0,0 +1,89 @@ +/* +******************************************************************************* +* Copyright(C) NEC Electronics Corporation 2010 +* All rights reserved by NEC Electronics Corporation. +* This program should be used on your own responsibility. +* NEC Electronics Corporation assumes no responsibility for any losses +* incurred by customers or third parties arising from the use of this file. +* +* This device driver was created by Applilet3 for V850ES/Jx3 +* 32-Bit Single-Chip Microcontrollers +* Filename: CG_systeminit.c +* Abstract: This file implements system initializing function. +* APIlib: Applilet3 for V850ES/Jx3 V2.01 [20 Apr 2010] +* Device: uPD70F3746 +* Compiler: IAR Systems ICCV850 +* Creation date: 6/26/2010 +******************************************************************************* +*/ + +/* +******************************************************************************* +** Include files +******************************************************************************* +*/ +#include "CG_macrodriver.h" +#include "CG_system.h" +#include "CG_port.h" +#include "CG_timer.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "CG_userdefine.h" + +/* +******************************************************************************* +** Global define +******************************************************************************* +*/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +UCHAR __low_level_init(void); +void systeminit(void); +/* +**----------------------------------------------------------------------------- +** +** Abstract: +** This function initializes each macro. +** +** Parameters: +** None +** +** Returns: +** None +** +**----------------------------------------------------------------------------- +*/ +void systeminit(void) +{ + DI(); /* disable interrupt */ + CG_ReadResetSource(); + PORT_Init(); + TAB0_Init(); + EI(); /* enable interrupt */ +} +/* +**----------------------------------------------------------------------------- +** +** Abstract: +** This function initializes hardware setting. +** +** Parameters: +** None +** +** Returns: +** None +** +**----------------------------------------------------------------------------- +*/ +UCHAR __low_level_init(void) +{ + VSWC = 0x13U; + CLOCK_Init(); /* call Clock_Init function */ + systeminit(); + + return MD_TRUE; +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/bsp/upd70f3454/applilet3_src/CG_timer.c b/bsp/upd70f3454/applilet3_src/CG_timer.c new file mode 100644 index 0000000000..bf2c928769 --- /dev/null +++ b/bsp/upd70f3454/applilet3_src/CG_timer.c @@ -0,0 +1,200 @@ +/* +******************************************************************************* +* Copyright(C) NEC Electronics Corporation 2010 +* All rights reserved by NEC Electronics Corporation. +* This program should be used on your own responsibility. +* NEC Electronics Corporation assumes no responsibility for any losses +* incurred by customers or third parties arising from the use of this file. +* +* This device driver was created by Applilet3 for V850ES/Jx3 +* 32-Bit Single-Chip Microcontrollers +* Filename: CG_timer.c +* Abstract: This file implements device driver for Timer module. +* APIlib: Applilet3 for V850ES/Jx3 V2.01 [20 Apr 2010] +* Device: uPD70F3746 +* Compiler: IAR Systems ICCV850 +* Creation date: 6/26/2010 +******************************************************************************* +*/ + +/* +******************************************************************************* +** Include files +******************************************************************************* +*/ +#include "CG_macrodriver.h" +#include "CG_timer.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "CG_userdefine.h" + +/* +******************************************************************************* +** Global define +******************************************************************************* +*/ +/* Count Clock (TABnCTL0) */ +#define TAB_CNT_CLK 0x00 /* Count Clock fxx */ +#define TAB_CNT_CLK_2 0x01 /* Count Clock fxx/2 */ +#define TAB_CNT_CLK_4 0x02 /* Count Clock fxx/4 */ +#define TAB_CNT_CLK_8 0x03 /* Count Clock fxx/8 */ +#define TAB_CNT_CLK_16 0x04 /* Count Clock fxx/16 */ +#define TAB_CNT_CLK_32 0x05 /* Count Clock fxx/32 */ +#define TAB_CNT_CLK_64 0x06 /* Count Clock fxx/64 */ +#define TAB_CNT_CLK_128 0x07 /* Count Clock fxx/128 */ +/* Mode (TABkMD2 + TABkMD1 + TABkMD0) */ +#define TAB_INTERVAL_MODE 0x00 /* Interval Timer Mode */ +/* TAB0I/O Control Register (TABmIOC0) */ +#define TAB_TOB00_DISABLE 0x00 /* TOB00 Output Disable */ +#define TAB_TOB00_ENABLE 0x01 /* TOB00 Output Enable */ +#define TAB_TOB00_HI_LEV_ST 0x00 /* TOB00 Output High Level Start */ +#define TAB_TOB00_LO_LEV_ST 0x02 /* TOB00 Output Low Level Start */ +#define TAB_TOB01_DISABLE 0x00 /* TOB01 Output Disable */ +#define TAB_TOB01_ENABLE 0x04 /* TOB01 Output Enable */ +#define TAB_TOB01_HI_LEV_ST 0x00 /* TOB01 Output High Level Start */ +#define TAB_TOB01_LO_LEV_ST 0x08 /* TOB01 Output Low Level Start */ +#define TAB_TOB02_DISABLE 0x00 /* TOB02 Output Disable */ +#define TAB_TOB02_ENABLE 0x10 /* TOB02 Output Enable */ +#define TAB_TOB02_HI_LEV_ST 0x00 /* TOB02 Output High Level Start */ +#define TAB_TOB02_LO_LEV_ST 0x20 /* TOB02 Output Low Level Start */ +#define TAB_TOB03_DISABLE 0x00 /* TOB03 Output Disable */ +#define TAB_TOB03_ENABLE 0x40 /* TOB03 Output Enable */ +#define TAB_TOB03_HI_LEV_ST 0x00 /* TOB03 Output High Level Start */ +#define TAB_TOB03_LO_LEV_ST 0x80 /* TOB03 Output Low Level Start */ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +void timerab_interval(void) +{ + TAB0CTL0 = TAB_CNT_CLK_32; /* TAB0CKS2 = 1 + TAB0CKS1 = 0 + TAB0CKS0 = 0 */ + /* : Clock Count = fxx/32 */ + TAB0CTL1 = TAB_INTERVAL_MODE; /* TAB0MD2 = 0 + TAB0MD1 = 0 + TAB0MD0 = 0 */ + /* : Interval Timer Mode */ +// TAB0IOC2 = TAB_TOB03_LO_LEV_ST | /* TAB0OL3 = 1 : TOB03 Low Level Start */ +// TAB_TOB03_DISABLE | /* TAB0OE3 = 0 : TOB03 Output Disable */ +// TAB_TOB02_LO_LEV_ST | /* TAB0OL2 = 1 : TOB02 Low Level Start */ +// TAB_TOB02_DISABLE | /* TAB0OE2 = 0 : TOB02 Output Disable */ +// TAB_TOB01_HI_LEV_ST | /* TAB0OL1 = 0 : TOB01 High Level Start */ +// TAB_TOB01_ENABLE | /* TAB0OE1 = 1 : TOB01 Output Enable */ +// TAB_TOB00_HI_LEV_ST | /* TAB0OL0 = 0 : TOB00 High Level Start */ +// TAB_TOB00_ENABLE; /* TAB0OE0 = 1 : TOB00 Output Enable */ + TAB0CCR0 = 19999; /* Compare Register */ + TAB0CCR1 = 0xFFFF; /* Compare Register */ + TAB0CCR2 = 0xFFFF; /* No Use */ + TAB0CCR3 = 0xFFFF; /* No Use */ +} + +/* +**----------------------------------------------------------------------------- +** +** Abstract: +** This function initializes the TAB0 module. +** +** Parameters: +** None +** +** Returns: +** None +** +**----------------------------------------------------------------------------- +*/ +void TAB0_Init(void) +{ + TAB0CE = 0; /* Stop TAB */ + + /* Port Definition */ +// PFC1 = 0x00; /* PFC17 = 0 : TOB00 Output */ + /* PFC10 = 0 : TOB01 Output */ +// PFCE1 = 0x01; /* PFCE10 = 1 : TOB01 Output */ +// PMC1 = 0x81; /* PMC17 = 1 : TOB00 Output/INTP09 Input */ + /* PMC10 = 1 : TOB0T1 Output/TIB01 Input/TOB01 Output */ + + /* Enable Interrupt */ + TB0CCMK0 = 0; /* TB0CCMK0 = 0 : INTTB0CC0 Enable */ + TB0CCMK1 = 1; /* TB0CCMK1 = 0 : INTTB0CC1 Enable */ + TB0CCMK2 = 1; /* TB0CCMK2 = 1 : INTTB0CC2 Disable */ + TB0CCMK3 = 1; /* TB0CCMK3 = 1 : INTTB0CC3 Disable */ + + timerab_interval(); +} +/* +**----------------------------------------------------------------------------- +** +** Abstract: +** This function starts TMP0 counter. +** +** Parameters: +** None +** +** Returns: +** None +** +**----------------------------------------------------------------------------- +*/ +void TAB0_Start(void) +{ + TB0CCIF0 = 0U; /* clear INTTP0CC0 interrupt flag */ + TB0CCMK0 = 0U; /* enable INTTP0CC0 interrupt */ + TAB0CE = 1U; /* enable TMP0 operation */ +} +/* +**----------------------------------------------------------------------------- +** +** Abstract: +** This function stops TMP0 counter. +** +** Parameters: +** None +** +** Returns: +** None +** +**----------------------------------------------------------------------------- +*/ +void TAB0_Stop(void) +{ + TAB0CE = 0U; /* disable TMP0 operation */ + TB0CCMK0 = 1U; /* disable INTTP0CC0 interrupt */ + TB0CCIF0 = 0U; /* clear INTTP0CC0 interrupt flag */ +} +/* +**----------------------------------------------------------------------------- +** +** Abstract: +** This function changes TMP0 register value. +** +** Parameters: +** array_reg: register value buffer +** array_num: register index to be changed +** +** Returns: +** MD_OK +** MD_ARGERROR +** +**----------------------------------------------------------------------------- +*/ +MD_STATUS TAB0_ChangeTimerCondition(USHORT *array_reg, UCHAR array_num) +{ + MD_STATUS status = MD_OK; + + switch (array_num) + { + case 1U: + TAB0CCR0 = array_reg[0U]; + status = MD_OK; + break; + case 2U: + TAB0CCR0 = array_reg[0U]; + TAB0CCR1 = array_reg[1U]; + status = MD_OK; + break; + default: + status = MD_ARGERROR; + break; + } + + return (status); +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/bsp/upd70f3454/applilet3_src/CG_timer.h b/bsp/upd70f3454/applilet3_src/CG_timer.h new file mode 100644 index 0000000000..85c88dddd7 --- /dev/null +++ b/bsp/upd70f3454/applilet3_src/CG_timer.h @@ -0,0 +1,278 @@ +/* +******************************************************************************* +* Copyright(C) NEC Electronics Corporation 2010 +* All rights reserved by NEC Electronics Corporation. +* This program should be used on your own responsibility. +* NEC Electronics Corporation assumes no responsibility for any losses +* incurred by customers or third parties arising from the use of this file. +* +* This device driver was created by Applilet3 for V850ES/Jx3 +* 32-Bit Single-Chip Microcontrollers +* Filename: CG_timer.h +* Abstract: This file implements device driver for Timer module. +* APIlib: Applilet3 for V850ES/Jx3 V2.01 [20 Apr 2010] +* Device: uPD70F3746 +* Compiler: IAR Systems ICCV850 +* Creation date: 6/26/2010 +******************************************************************************* +*/ + +#ifndef _MDTIMER_ +#define _MDTIMER_ +/* +******************************************************************************* +** Register bit define +******************************************************************************* +*/ +/* + TMP control register 0 (TPnCTL0) +*/ +/* TMP operation control (TPnCE) */ +#define _00_TMP_OPERATION_DISABLE 0x00U /* disable internal operating clock operation (asynchronously reset TMPn) */ +#define _80_TMP_OPERATION_ENABLE 0x80U /* enable internal operating clock operation */ +/* Internal count clock selection (TPnCKS2 - TPnCKS0) */ +#define _00_TMP_INTERNAL_CLOCK0 0x00U /* fXX */ +#define _01_TMP_INTERNAL_CLOCK1 0x01U /* fXX/2 */ +#define _02_TMP_INTERNAL_CLOCK2 0x02U /* fXX/2^2 */ +#define _03_TMP_INTERNAL_CLOCK3 0x03U /* fXX/2^3 */ +#define _04_TMP_INTERNAL_CLOCK4 0x04U /* fXX/2^4 */ +#define _05_TMP_INTERNAL_CLOCK5 0x05U /* fXX/2^5 */ +#define _06_TMP_INTERNAL_CLOCK6 0x06U /* fXX/2^6 or fXX/2^8 */ +#define _07_TMP_INTERNAL_CLOCK7 0x07U /* fXX/2^7 or fXX/2^9 */ + +/* + TMP control register 1 (TPnCTL1) +*/ +/* Software trigger control (TPnEST) */ +#define _00_TMP_SOFTTRIGGER_OFF 0x00U /* no operation */ +#define _40_TMP_SOFTTRIGGER_ON 0x40U /* in one-shot pulse mode: One-shot pulse software trigger */ + /* in external trigger pulse output mode: Pulse output software trigger */ +/* Count clock selection (TPnEEE) */ +#define _00_TMP_INTERNAL_CLOCK 0x00U /* use the internal clock (clock selected with bits TPnCKS2 to TPnCKS0) */ +#define _20_TMP_EXTERNAL_CLOCK 0x20U /* use the external clock from the TIPn0 input pin */ +/* Timer mode selection (TPnMD2 - TPnMD0) */ +#define _00_TMP_MODE_INTERVAL 0x00U /* interval timer mode */ +#define _01_TMP_MODE_EXTERNALCOUNT 0x01U /* external event counter mode */ +#define _02_TMP_MODE_EXTERNALTRG 0x02U /* external trigger pulse output mode */ +#define _03_TMP_MODE_ONESHOT 0x03U /* one-shot pulse mode */ +#define _04_TMP_MODE_PWM 0x04U /* PWM mode */ +#define _05_TMP_MODE_FREERUNNING 0x05U /* free-running mode */ +#define _06_TMP_MODE_PULSEMEASURE 0x06U /* pulse width measurement mode */ + +/* + TMP I/O control register 0 (TPnIOC0) +*/ +/* TOPn0 pin output level setting (TPnOL0) */ +#define _00_TMP_OUTPUT0_NORMAL 0x00U /* normal output */ +#define _02_TMP_OUTPUT0_INVERTED 0x02U /* inverted output */ +/* TOPn0 pin output setting (TPnOE0) */ +#define _00_TMP_OUTPUT0_DISABLE 0x00U /* disable timer output */ +#define _01_TMP_OUTPUT0_ENABLE 0x01U /* enable timer output (TOPn0 pin outputs pulses) */ +/* TOPn1 pin output level setting (TPnOL1) */ +#define _00_TMP_OUTPUT1_NORMAL 0x00U /* normal output */ +#define _08_TMP_OUTPUT1_INVERTED 0x08U /* inverted output */ +/* TOPn1 pin output setting (TPnOE1) */ +#define _00_TMP_OUTPUT1_DISABLE 0x00U /* disable timer output */ +#define _04_TMP_OUTPUT1_ENABLE 0x04U /* enable timer output (TOPn1 pin outputs pulses) */ + +/* + TMP I/O control register 1 (TPnIOC1) +*/ +/* Capture trigger input signal (TIPn1 pin) valid edge setting (TPnIS3,TPnIS2) */ +#define _00_TMP_INPUT1_EDGE_NONE 0x00U /* detect no edge (capture operation is invalid) */ +#define _04_TMP_INPUT1_EDGE_RISING 0x04U /* detection of rising edge */ +#define _08_TMP_INPUT1_EDGE_FALLING 0x08U /* detection of falling edge */ +#define _0C_TMP_INPUT1_EDGE_BOTH 0x0CU /* detection of both edges */ +/* Capture trigger input signal (TIPn0 pin) valid edge setting (TPnIS1,TPnIS0) */ +#define _00_TMP_INPUT0_EDGE_NONE 0x00U /* detect no edge (capture operation is invalid) */ +#define _01_TMP_INPUT0_EDGE_RISING 0x01U /* detection of rising edge */ +#define _02_TMP_INPUT0_EDGE_FALLING 0x02U /* detection of falling edge */ +#define _03_TMP_INPUT0_EDGE_BOTH 0x03U /* detection of both edges */ + +/* + TMP I/O control register 2 (TPnIOC2) +*/ +/* External event count input signal (TIPn0 pin) valid edge setting (TPnEES1,TPnEES0) */ +#define _00_TMP_EXTCOUNT_EDGE_NONE 0x00U /* detect no edge (external event count is invalid) */ +#define _04_TMP_EXTCOUNT_EDGE_RISING 0x04U /* detection of rising edge */ +#define _08_TMP_EXTCOUNT_EDGE_FALLING 0x08U /* detection of falling edge */ +#define _0C_TMP_EXTCOUNT_EDGE_BOTH 0x0CU /* detection of both edges */ +/* External trigger input signal (TIPn0 pin) valid edge setting (TPnETS1,TPnETS0) */ +#define _00_TMP_EXTTRIGGER_EDGE_NONE 0x00U /* detect no edge (external trigger is invalid) */ +#define _01_TMP_EXTTRIGGER_EDGE_RISING 0x01U /* detection of rising edge */ +#define _02_TMP_EXTTRIGGER_EDGE_FALLING 0x02U /* detection of falling edge */ +#define _03_TMP_EXTTRIGGER_EDGE_BOTH 0x03U /* detection of both edges */ + +/* + TMP option register 0 (TPnOPT0) +*/ +/* TPnCCR1 register capture/compare selection (TPnCCS1) */ +#define _00_TMP_CCR1_COMPARE 0x00U /* compare register */ +#define _20_TMP_CCR1_CAPTURE 0x20U /* capture register */ +/* TPnCCR0 register capture/compare selection (TPnCCS0) */ +#define _00_TMP_CCR0_COMPARE 0x00U /* compare register */ +#define _10_TMP_CCR0_CAPTURE 0x10U /* capture register */ +/* TMPn overflow detection flag (TPnOVF) */ +#define _01_TMP_OVERFLOW_OCCUR 0x01U /* overflow occurred */ +#define _00_TMP_OVERFLOW_CLEAR 0x00U /* clear overflow */ + +/* + TMQ0 control register 0 (TQ0CTL0) +*/ +/* TMQ operation control (TQ0CE) */ +#define _00_TMQ_OPERATION_DISABLE 0x00U /* disable internal operating clock operation (asynchronously reset TMQ0) */ +#define _80_TMQ_OPERATION_ENABLE 0x80U /* enable internal operating clock operation */ +/* Internal count clock selection (TQ0CKS2 - TQ0CKS0) */ +#define _00_TMQ_INTERNAL_CLOCK0 0x00U /* fXX */ +#define _01_TMQ_INTERNAL_CLOCK1 0x01U /* fXX/2 */ +#define _02_TMQ_INTERNAL_CLOCK2 0x02U /* fXX/2^2 */ +#define _03_TMQ_INTERNAL_CLOCK3 0x03U /* fXX/2^3 */ +#define _04_TMQ_INTERNAL_CLOCK4 0x04U /* fXX/2^4 */ +#define _05_TMQ_INTERNAL_CLOCK5 0x05U /* fXX/2^5 */ +#define _06_TMQ_INTERNAL_CLOCK6 0x06U /* fXX/2^6 */ +#define _07_TMQ_INTERNAL_CLOCK7 0x07U /* fXX/2^7 */ + +/* + TMQ0 control register 1 (TQ0CTL1) +*/ +/* Software trigger control (TQ0EST) */ +#define _00_TMQ_SOFTTRIGGER_OFF 0x00U /* no operation */ +#define _40_TMQ_SOFTTRIGGER_ON 0x40U /* in one-shot pulse mode: One-shot pulse software trigger */ + /* in external trigger pulse output mode: Pulse output software trigger */ +/* Count clock selection (TQ0EEE) */ +#define _00_TMQ_INTERNAL_CLOCK 0x00U /* use the internal clock (clock selected with bits TQ0CKS2 to TQ0CKS0) */ +#define _20_TMQ_EXTERNAL_CLOCK 0x20U /* use the external clock from the TIQ00 input pin */ +/* Timer mode selection (TQ0MD2 - TQ0MD0) */ +#define _00_TMQ_MODE_INTERVAL 0x00U /* interval timer mode */ +#define _01_TMQ_MODE_EXTERNALCOUNT 0x01U /* external event counter mode */ +#define _02_TMQ_MODE_EXTERNALTRG 0x02U /* external trigger pulse output mode */ +#define _03_TMQ_MODE_ONESHOT 0x03U /* one-shot pulse mode */ +#define _04_TMQ_MODE_PWM 0x04U /* PWM mode */ +#define _05_TMQ_MODE_FREERUNNING 0x05U /* free-running mode */ +#define _06_TMQ_MODE_PULSEMEASURE 0x06U /* pulse width measurement mode */ + +/* + TMQ0 I/O control register 0 (TQ0IOC0) +*/ +/* TOQ00 pin output level setting (TQ0OL0) */ +#define _00_TMQ_OUTPUT0_NORMAL 0x00U /* normal output */ +#define _02_TMQ_OUTPUT0_INVERTED 0x02U /* inverted output */ +/* TOQ00 pin output setting (TQ0OE0) */ +#define _00_TMQ_OUTPUT0_DISABLE 0x00U /* disable timer output */ +#define _01_TMQ_OUTPUT0_ENABLE 0x01U /* enable timer output (TOQ00 pin outputs pulses) */ +/* TOQ01 pin output level setting (TQ0OL1) */ +#define _00_TMQ_OUTPUT1_NORMAL 0x00U /* normal output */ +#define _08_TMQ_OUTPUT1_INVERTED 0x08U /* inverted output */ +/* TOQ01 pin output setting (TQ0OE1) */ +#define _00_TMQ_OUTPUT1_DISABLE 0x00U /* disable timer output */ +#define _04_TMQ_OUTPUT1_ENABLE 0x04U /* enable timer output (TOQ01 pin outputs pulses) */ +/* TOQ02 pin output level setting (TQ0OL2) */ +#define _00_TMQ_OUTPUT2_NORMAL 0x00U /* normal output */ +#define _20_TMQ_OUTPUT2_INVERTED 0x20U /* inverted output */ +/* TOQ02 pin output setting (TQ0OE2) */ +#define _00_TMQ_OUTPUT2_DISABLE 0x00U /* disable timer output */ +#define _10_TMQ_OUTPUT2_ENABLE 0x10U /* enable timer output (TOQ02 pin outputs pulses) */ +/* TOQ03 pin output level setting (TQ0OL3) */ +#define _00_TMQ_OUTPUT3_NORMAL 0x00U /* normal output */ +#define _80_TMQ_OUTPUT3_INVERTED 0x80U /* inverted output */ +/* TOQ03 pin output setting (TQ0OE3) */ +#define _00_TMQ_OUTPUT3_DISABLE 0x00U /* disable timer output */ +#define _40_TMQ_OUTPUT3_ENABLE 0x40U /* enable timer output (TOQ03 pin outputs pulses) */ + +/* + TMQ0 I/O control register 1 (TQ0IOC1) +*/ +/* Capture trigger input signal (TIQ00 pin) valid edge setting (TQ0IS1,TQ0IS0) */ +#define _00_TMQ_INPUT0_EDGE_NONE 0x00U /* detect no edge (capture operation is invalid) */ +#define _01_TMQ_INPUT0_EDGE_RISING 0x01U /* detection of rising edge */ +#define _02_TMQ_INPUT0_EDGE_FALLING 0x02U /* detection of falling edge */ +#define _03_TMQ_INPUT0_EDGE_BOTH 0x03U /* detection of both edges */ +/* Capture trigger input signal (TIQ01 pin) valid edge setting (TQ0IS3,TQ0IS2) */ +#define _00_TMQ_INPUT1_EDGE_NONE 0x00U /* detect no edge (capture operation is invalid) */ +#define _04_TMQ_INPUT1_EDGE_RISING 0x04U /* detection of rising edge */ +#define _08_TMQ_INPUT1_EDGE_FALLING 0x08U /* detection of falling edge */ +#define _0C_TMQ_INPUT1_EDGE_BOTH 0x0CU /* detection of both edges */ +/* Capture trigger input signal (TIQ02 pin) valid edge setting (TQ0IS5,TQ0IS4) */ +#define _00_TMQ_INPUT2_EDGE_NONE 0x00U /* detect no edge (capture operation is invalid) */ +#define _10_TMQ_INPUT2_EDGE_RISING 0x10U /* detection of rising edge */ +#define _20_TMQ_INPUT2_EDGE_FALLING 0x20U /* detection of falling edge */ +#define _30_TMQ_INPUT2_EDGE_BOTH 0x30U /* detection of both edges */ +/* Capture trigger input signal (TIQ03 pin) valid edge setting (TQ0IS7,TQ0IS6) */ +#define _00_TMQ_INPUT3_EDGE_NONE 0x00U /* detect no edge (capture operation is invalid) */ +#define _40_TMQ_INPUT3_EDGE_RISING 0x40U /* detection of rising edge */ +#define _80_TMQ_INPUT3_EDGE_FALLING 0x80U /* detection of falling edge */ +#define _C0_TMQ_INPUT3_EDGE_BOTH 0xC0U /* detection of both edges */ + +/* + TMQ0 I/O control register 2 (TQ0IOC2) +*/ +/* External event count input signal (TIQ00 pin) valid edge setting (TQ0EES1,TQ0EES0) */ +#define _00_TMQ_EXTCOUNT_EDGE_NONE 0x00U /* detect no edge (external event count is invalid) */ +#define _04_TMQ_EXTCOUNT_EDGE_RISING 0x04U /* detection of rising edge */ +#define _08_TMQ_EXTCOUNT_EDGE_FALLING 0x08U /* detection of falling edge */ +#define _0C_TMQ_EXTCOUNT_EDGE_BOTH 0x0CU /* detection of both edges */ +/* External trigger input signal (TIQ00 pin) valid edge setting (TQ0ETS1,TQ0ETS0) */ +#define _00_TMQ_EXTTRIGGER_EDGE_NONE 0x00U /* detect no edge (external trigger is invalid) */ +#define _01_TMQ_EXTTRIGGER_EDGE_RISING 0x01U /* detection of rising edge */ +#define _02_TMQ_EXTTRIGGER_EDGE_FALLING 0x02U /* detection of falling edge */ +#define _03_TMQ_EXTTRIGGER_EDGE_BOTH 0x03U /* detection of both edges */ + +/* + TMQ0 option register 0 (TQ0OPT0) +*/ +/* TQ0CCR3 register capture/compare selection (TQ0CCS3) */ +#define _00_TMQ_CCR3_COMPARE 0x00U /* compare register */ +#define _80_TMQ_CCR3_CAPTURE 0x80U /* capture register */ +/* TQ0CCR2 register capture/compare selection (TQ0CCS2) */ +#define _00_TMQ_CCR2_COMPARE 0x00U /* compare register */ +#define _40_TMQ_CCR2_CAPTURE 0x40U /* capture register */ +/* TQ0CCR1 register capture/compare selection (TQ0CCS1) */ +#define _00_TMQ_CCR1_COMPARE 0x00U /* compare register */ +#define _20_TMQ_CCR1_CAPTURE 0x20U /* capture register */ +/* TQ0CCR0 register capture/compare selection (TQ0CCS0) */ +#define _00_TMQ_CCR0_COMPARE 0x00U /* compare register */ +#define _10_TMQ_CCR0_CAPTURE 0x10U /* capture register */ +/* TMQ0 overflow detection flag (TQ0OVF) */ +#define _01_TMQ_OVERFLOW_OCCUR 0x01U /* overflow occurred */ +#define _00_TMQ_OVERFLOW_CLEAR 0x00U /* clear overflow */ + +/* + TMM0 control register 0 (TM0CTL0) +*/ +/* TMM0 operation control (TM0CE) */ +#define _00_TMM_OPERATION_DISABLE 0x00U /* disable internal operating clock operation (asynchronously reset TMM0) */ +#define _80_TMM_OPERATION_ENABLE 0x80U /* enable internal operating clock operation */ +/* Internal count clock selection (TM0CKS2 - TM0CKS0) */ +#define _00_TMM_INTERNAL_CLOCK0 0x00U /* fXX */ +#define _01_TMM_INTERNAL_CLOCK1 0x01U /* fXX/2 */ +#define _02_TMM_INTERNAL_CLOCK2 0x02U /* fXX/4 */ +#define _03_TMM_INTERNAL_CLOCK3 0x03U /* fXX/64 */ +#define _04_TMM_INTERNAL_CLOCK4 0x04U /* fXX/512 */ +#define _05_TMM_INTERNAL_CLOCK5 0x05U /* INTWT */ +#define _06_TMM_INTERNAL_CLOCK6 0x06U /* fR/8 */ +#define _07_TMM_INTERNAL_CLOCK7 0x07U /* fXT */ +/* +******************************************************************************* +** Macro define +******************************************************************************* +*/ +/* TMP0 compare register 0 (TP0CCR0)*/ +#define _9C3F_TMP0_CCR0_VALUE 0x9C3FU +enum TMChannel +{ + TMCHANNEL0, TMCHANNEL1, TMCHANNEL2, TMCHANNEL3 +}; +/* +******************************************************************************* +** Function define +******************************************************************************* +*/ +void TAB0_Init(void); +void TAB0_Start(void); +void TAB0_Stop(void); +MD_STATUS TAB0_ChangeTimerCondition(USHORT *array_reg, UCHAR array_num); +__interrupt void MD_INTTP0CC0(void); + +/* Start user code for function. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#endif diff --git a/bsp/upd70f3454/applilet3_src/CG_timer_user.c b/bsp/upd70f3454/applilet3_src/CG_timer_user.c new file mode 100644 index 0000000000..fabc547b7d --- /dev/null +++ b/bsp/upd70f3454/applilet3_src/CG_timer_user.c @@ -0,0 +1,63 @@ +/* +******************************************************************************* +* Copyright(C) NEC Electronics Corporation 2010 +* All rights reserved by NEC Electronics Corporation. +* This program should be used on your own responsibility. +* NEC Electronics Corporation assumes no responsibility for any losses +* incurred by customers or third parties arising from the use of this file. +* +* This device driver was created by Applilet3 for V850ES/Jx3 +* 32-Bit Single-Chip Microcontrollers +* Filename: CG_timer_user.c +* Abstract: This file implements device driver for Timer module. +* APIlib: Applilet3 for V850ES/Jx3 V2.01 [20 Apr 2010] +* Device: uPD70F3746 +* Compiler: IAR Systems ICCV850 +* Creation date: 6/26/2010 +******************************************************************************* +*/ + +/* +******************************************************************************* +** Include files +******************************************************************************* +*/ +#include "CG_macrodriver.h" +#include "CG_timer.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "CG_userdefine.h" + +/* +******************************************************************************* +** Global define +******************************************************************************* +*/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/* +**----------------------------------------------------------------------------- +** +** Abstract: +** This function is INTTP0CC0 interrupt service routine. +** +** Parameters: +** None +** +** Returns: +** None +** +**----------------------------------------------------------------------------- +*/ + +///#pragma vector = INTTB0CC0_vector +///__interrupt void MD_INTTB0CC0(void) +///{ + /* Start user code. Do not edit comment generated here */ +/// PDLH = ~PDLH; + /* End user code. Do not edit comment generated here */ +///} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/bsp/upd70f3454/applilet3_src/CG_userdefine.h b/bsp/upd70f3454/applilet3_src/CG_userdefine.h new file mode 100644 index 0000000000..33f5b2e773 --- /dev/null +++ b/bsp/upd70f3454/applilet3_src/CG_userdefine.h @@ -0,0 +1,30 @@ +/* +******************************************************************************* +* Copyright(C) NEC Electronics Corporation 2010 +* All rights reserved by NEC Electronics Corporation. +* This program should be used on your own responsibility. +* NEC Electronics Corporation assumes no responsibility for any losses +* incurred by customers or third parties arising from the use of this file. +* +* This device driver was created by Applilet3 for V850ES/Jx3 +* 32-Bit Single-Chip Microcontrollers +* Filename: CG_userdefine.h +* Abstract: This file includes user definition. +* APIlib: Applilet3 for V850ES/Jx3 V2.01 [20 Apr 2010] +* Device: uPD70F3746 +* Compiler: IAR Systems ICCV850 +* Creation date: 6/26/2010 +******************************************************************************* +*/ + +#ifndef _MD_USER_DEF_ +#define _MD_USER_DEF_ +/* +******************************************************************************* +** User define +******************************************************************************* +*/ + +/* Start user code for function. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#endif diff --git a/bsp/upd70f3454/board.c b/bsp/upd70f3454/board.c new file mode 100644 index 0000000000..9209439cb6 --- /dev/null +++ b/bsp/upd70f3454/board.c @@ -0,0 +1,33 @@ +/* + * File : board.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-06-29 lgnq the first version + * + * For : NEC V850E + * Toolchain : IAR Embedded Workbench for V850 v3.71 +*/ + +#include +#include + +#include "uart.h" +#include "board.h" + +void rt_hw_board_init() +{ +#ifdef RT_USING_UART0 + rt_hw_uart_init(); + rt_console_set_device("uart0"); +#endif + + rt_kprintf("\r\n\r\nSystemInit......\r\n"); +} + diff --git a/bsp/upd70f3454/board.h b/bsp/upd70f3454/board.h new file mode 100644 index 0000000000..f2e2cb0724 --- /dev/null +++ b/bsp/upd70f3454/board.h @@ -0,0 +1,38 @@ +/* + * File : board.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2009-09-22 Bernard add board.h to this bsp + * 2010-02-04 Magicoe add board.h to LPC176x bsp + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include "rtdef.h" + +#define LB900 1 +#define LM600 2 +#define LM201R 3 +#define LM201P 4 +#define LM101 5 + +#define PLATFORM LM201R + +#define ENTER_KEY 0x1d +#define UP_KEY 0x1b +#define DOWN_KEY 0x17 +#define LEFT_KEY 0x0f +#define RIGHT_KEY 0x1e + +void rt_hw_board_init(void); +rt_uint8_t get_key(void); + +#endif diff --git a/bsp/upd70f3454/cstartup.s85 b/bsp/upd70f3454/cstartup.s85 new file mode 100644 index 0000000000..fc3d8d9224 --- /dev/null +++ b/bsp/upd70f3454/cstartup.s85 @@ -0,0 +1,839 @@ +;----------------------------------------------------------------------------- +; This file contains the startup code used by the V850 C/C++ compiler. +; +; Copyright (c) 1998-2009 IAR Systems AB. +; +; $Revision: 5028 $ +; +;----------------------------------------------------------------------------- + +; +; Naming covention of labels in this file: +; +; ?xxx - External labels only accessed from assembler. +; __xxx - External labels accessed from or defined in C. +; xxx - Labels local to one module (note: this file contains +; several modules). +; main - The starting point of the user program. +; + +#include "lxx.h" +#include "cfi.h" + + CASEON + +#define A0 R1 +#define A1 R5 +#define A2 R6 + +;---------------------------------------------------------------; +; Call Frame Informatio ; +;---------------------------------------------------------------; + + CFNAMES + CFCOMMON + +;---------------------------------------------------------------; +; Reset Vector ; +;---------------------------------------------------------------; + + MODULE ?RESET + + PUBLIC ?creset + EXTERN __program_start + + COMMON INTVEC:CODE:ROOT(2) + +?creset: + MOV __program_start, R1 + JMP [R1] + + ENDMOD + +;---------------------------------------------------------------; +; Module start. ; +;---------------------------------------------------------------; + + MODULE __program_start + + PUBLIC __program_start + PUBLIC ?cstartup + EXTERN ?creset + REQUIRE ?creset + +;---------------------------------------------------------------; +; Forward declarations of segments used in this module. ; +;---------------------------------------------------------------; + + RSEG CODE:CODE:NOROOT(2) + RSEG CSTACK:DATA(2) + +;---------------------------------------------------------------; +; The startup code. ; +;---------------------------------------------------------------; + + RSEG CSTART:CODE:NOROOT(1) + + ;; + ;; The startup sequence contained in the final linked + ;; application will consist of a mosaic containing + ;; modules and segment parts defined in this file. + ;; + ;; The only part which is required is the call to + ;; the function "main". + ;; + + EXTERN ?cstart_call_main + REQUIRE ?cstart_call_main + + EXTERN __cstart_low_level_init + REQUIRE __cstart_low_level_init + + PUBLIC ?BTT_cstart_begin +?BTT_cstart_begin: + +?cstartup: +__program_start: + +;---------------------------------------------------------------; +; Set up the stack and the global pointer. ; +;---------------------------------------------------------------; + +#if __CORE__ == __CORE_V850__ + ;; If an interrupt is issued beteween the MOVEA and + ;; MOVHI instructions the SP will point into + ;; nowhere. To fix this problem we build the new SP + ;; value in R1 and moves it with an atomic operation + ;; to SP. + MOVE_M SFE CSTACK, R1 + MOV R1, SP +#else + MOVE_M SFE CSTACK, SP +#endif + + EXTERN ?BREL_BASE + MOVE_M ?BREL_BASE + 0x8000, GP + + EXTERN ?BREL_CBASE + MOVE_M ?BREL_CBASE + 0x8000, R25 + +;---------------------------------------------------------------; +; Setup constant registers. ; +;---------------------------------------------------------------; + + RSEG CSTART:CODE:NOROOT(1) + PUBLIC ?INIT_REG + +?INIT_REG: MOV 255, R18 + ORI 65535, zero, R19 + + ENDMOD + + +;---------------------------------------------------------------; +; Initialize the saddr base pointers. ; +;---------------------------------------------------------------; + + MODULE ?INIT_SADDR_BASE + + RTMODEL "__reg_ep", "saddr" + + RSEG CSTART:CODE:NOROOT(1) + PUBLIC ?INIT_SADDR_BASE + +?INIT_SADDR_BASE: + EXTERN ?SADDR_BASE + MOVE_M ?SADDR_BASE, EP + + ENDMOD + + +;---------------------------------------------------------------; +; If hardware must be initialized from C or if watch dog timer ; +; must be handled or if the segment init should not be ; +; performed it can now be done in `__low_level_init'. ; +;---------------------------------------------------------------; +; Call the user function __low_level_init, if defined. ; +; It is the responsibility of __low_level_init to require ; +; __cstart_low_level_init in order to be called by cstartup. ; +;---------------------------------------------------------------; + + MODULE ?CSTART_LOW_LEVEL_INIT + RSEG CSTART:CODE:NOROOT(1) + + PUBLIC __cstart_low_level_init + EXTERN __low_level_init + REQUIRE __low_level_init + EXTERN ?no_seg_init + +__cstart_low_level_init: + CALL_FUNC __low_level_init, LP, R1 + ANDI 0xFF, R1, R1 + BZ ?no_seg_init + + ENDMOD + + +;---------------------------------------------------------------; +; Segment initialization code. Copy initialized ROMmed code to ; +; RAM and ?seg_clear uninitialized variables. ; +;---------------------------------------------------------------; + + MODULE ?INIT_MEMORY + +;---------------------------------------------------------------; +; Zero out NEAR_Z ; +;---------------------------------------------------------------; + PUBLIC ?INIT_NEAR_Z + + RSEG NEAR_Z(2) + RSEG CSTART:CODE:NOROOT(1) + + EXTERN ?seg_clear +?INIT_NEAR_Z: + + MOVE_M SFB NEAR_Z, A0 + MOVE_M SFE NEAR_Z, A1 + JARL ?seg_clear, LP + + +;---------------------------------------------------------------; +; Zero out BREL_Z ; +;---------------------------------------------------------------; + PUBLIC ?INIT_BREL_Z + + RSEG BREL_Z(2) + RSEG CSTART:CODE:NOROOT(1) + + EXTERN ?seg_clear +?INIT_BREL_Z: + + MOVE_M SFB BREL_Z, A0 + MOVE_M SFE BREL_Z, A1 + JARL ?seg_clear, LP + +;---------------------------------------------------------------; +; Zero out SADDR7_Z ; +;---------------------------------------------------------------; + PUBLIC ?INIT_SADDR7_Z + + RSEG SADDR7_Z(2) + + RSEG CSTART:CODE:NOROOT(1) + + EXTERN ?seg_clear +?INIT_SADDR7_Z: + + MOVE_M SFB SADDR7_Z, A0 + MOVE_M SFE SADDR7_Z, A1 + JARL ?seg_clear, LP + + +;---------------------------------------------------------------; +; Zero out SADDR8_Z ; +;---------------------------------------------------------------; + PUBLIC ?INIT_SADDR8_Z + + RSEG SADDR8_Z(2) + + RSEG CSTART:CODE:NOROOT(1) + + EXTERN ?seg_clear +?INIT_SADDR8_Z: + + MOVE_M SFB SADDR8_Z, A0 + MOVE_M SFE SADDR8_Z, A1 + JARL ?seg_clear, LP + + +;---------------------------------------------------------------; +; Zero out BREL23_Z ; +;---------------------------------------------------------------; + +#if __CORE__ >= __CORE_V850E2M__ + + PUBLIC ?INIT_BREL23_Z + + RSEG BREL23_Z(2) + + RSEG CSTART:CODE:NOROOT(1) + + EXTERN ?seg_clear +?INIT_BREL23_Z: + + MOVE_M SFB BREL23_Z, A0 + MOVE_M SFE BREL23_Z, A1 + JARL ?seg_clear, LP +#endif + +;---------------------------------------------------------------; +; Zero out HUGE_Z ; +;---------------------------------------------------------------; + PUBLIC ?INIT_HUGE_Z + + RSEG HUGE_Z(2) + + RSEG CSTART:CODE:NOROOT(1) + + EXTERN ?seg_clear +?INIT_HUGE_Z: + + MOVE_M SFB HUGE_Z, A0 + MOVE_M SFE HUGE_Z, A1 + JARL ?seg_clear, LP + +;---------------------------------------------------------------; +; Copy NEAR_ID into NEAR_I ; +;---------------------------------------------------------------; + PUBLIC ?INIT_NEAR_I + + RSEG NEAR_I(2) + RSEG NEAR_ID(2) + + RSEG CSTART:CODE:NOROOT(1) + + EXTERN ?seg_copy +?INIT_NEAR_I: + + MOVE_M SFB NEAR_ID, A0 + MOVE_M SFE NEAR_ID, A1 + MOVE_M SFB NEAR_I, A2 + JARL ?seg_copy, LP + +;---------------------------------------------------------------; +; Copy BREL_ID into BREL_I ; +;---------------------------------------------------------------; + PUBLIC ?INIT_BREL_I + + RSEG BREL_I(2) + RSEG BREL_ID(2) + + RSEG CSTART:CODE:NOROOT(1) + + EXTERN ?seg_copy +?INIT_BREL_I: + + MOVE_M SFB BREL_ID, A0 + MOVE_M SFE BREL_ID, A1 + MOVE_M SFB BREL_I, A2 + JARL ?seg_copy, LP + +;---------------------------------------------------------------; +; Copy SADDR7_ID into SADDR7_I ; +;---------------------------------------------------------------; + PUBLIC ?INIT_SADDR7_I + + RSEG SADDR7_I(2) + RSEG SADDR7_ID(2) + + RSEG CSTART:CODE:NOROOT(1) + + EXTERN ?seg_copy +?INIT_SADDR7_I: + + MOVE_M SFB SADDR7_ID, A0 + MOVE_M SFE SADDR7_ID, A1 + MOVE_M SFB SADDR7_I, A2 + JARL ?seg_copy, LP + +;---------------------------------------------------------------; +; Copy SADDR8_ID into SADDR8_I ; +;---------------------------------------------------------------; + PUBLIC ?INIT_SADDR8_I + + RSEG SADDR8_I(2) + RSEG SADDR8_ID(2) + + RSEG CSTART:CODE:NOROOT(1) + + EXTERN ?seg_copy +?INIT_SADDR8_I: + + MOVE_M SFB SADDR8_ID, A0 + MOVE_M SFE SADDR8_ID, A1 + MOVE_M SFB SADDR8_I, A2 + JARL ?seg_copy, LP + +;---------------------------------------------------------------; +; Copy BREL23_ID into BREL23_I ; +;---------------------------------------------------------------; + +#if __CORE__ >= __CORE_V850E2M__ + + PUBLIC ?INIT_BREL23_I + + RSEG BREL23_I(1) + RSEG BREL23_ID(1) + + RSEG CSTART:CODE:NOROOT(1) + + EXTERN ?seg_copy + +?INIT_BREL23_I: + + MOVE_M SFB BREL23_ID, A0 + MOVE_M SFE BREL23_ID, A1 + MOVE_M SFB BREL23_I, A2 + JARL ?seg_copy, LP + +#endif + +;---------------------------------------------------------------; +; Copy HUGE_ID into HUGE_I ; +;---------------------------------------------------------------; + PUBLIC ?INIT_HUGE_I + + RSEG HUGE_I(1) + RSEG HUGE_ID(1) + + RSEG CSTART:CODE:NOROOT(1) + + EXTERN ?seg_copy + +?INIT_HUGE_I: + + MOVE_M SFB HUGE_ID, A0 + MOVE_M SFE HUGE_ID, A1 + MOVE_M SFB HUGE_I, A2 + JARL ?seg_copy, LP + + +;---------------------------------------------------------------; +; Destination label when skipping data initialization. ; +;---------------------------------------------------------------; + PUBLIC ?no_seg_init + + RSEG CSTART:CODE:NOROOT(1) + +?no_seg_init: + + ENDMOD + + +;---------------------------------------------------------------; +; Calculate code distance (PIC only). ; +;---------------------------------------------------------------; + + MODULE ?INIT_PIC + PUBLIC ?INIT_PIC + + RSEG CSTART:CODE:NOROOT(1) + + RTMODEL "__code_model", "pic" + + EXTERN ?CODE_DISTANCE + EXTERN_LS_M + +?INIT_PIC: + JARL ref_point, A1 +ref_point: MOVE_M ref_point, A2 + SUB A2, A1 + ;; Expands to correct store instruction/sequence. + STORE_M A1, ?CODE_DISTANCE, A2 + ;; Note: A1 (the value of ?CODE_DISTANCE) is used below! + + ENDMOD + + +#if __CORE__ >= __CORE_V850E2M__ + +;---------------------------------------------------------------; +; Initialize the BSEL system register bank selector. ; +;---------------------------------------------------------------; + + MODULE ?INIT_BSEL + RSEG CSTART:CODE:NOROOT(1) + PUBLIC ?INIT_BSEL + +?INIT_BSEL: + LDSR R0, 31 ; BSEL + + ENDMOD + +#endif + + +#if __CORE__ >= __CORE_V850E__ + +;---------------------------------------------------------------; +; Initialize the CALLT base pointers. ; +;---------------------------------------------------------------; + + + MODULE ?INIT_CALLT + PUBLIC ?INIT_CALLT + EXTERN ?CALLT_BASE + COMMON CLTVEC(2) + RSEG CSTART:CODE:NOROOT(1) + + RTMODEL "__cpu", "v850e" + + REQUIRE ?CALLT_BASE + + ;; The Call table base pointer +?INIT_CALLT: + MOVE_M SFB CLTVEC, A2 +#ifdef CODE_MODEL_PIC + EXTERN ?CODE_DISTANCE + REQUIRE ?CODE_DISTANCE + + ;; Add the value of ?CODE_DISTANCE calculated above + ADD A1, A2 +#endif +#if __CORE__ >= __CORE_V850E2M__ + EXTERN ?INIT_BSEL + REQUIRE ?INIT_BSEL +#endif + LDSR A2, 20 ; CTBP + + ENDMOD +#endif + + +#if __CORE__ >= __CORE_V850E2M__ + +;---------------------------------------------------------------; +; Initialize the SYSCALL base pointers. ; +;---------------------------------------------------------------; + + MODULE ?INIT_SYSCALL + PUBLIC ?INIT_SYSCALL + EXTERN ?INIT_BSEL + EXTERN ?SYSCALL_BASE + COMMON SYSCALLVEC(2) + + RSEG CSTART:CODE:NOROOT(1) + + REQUIRE ?INIT_BSEL + REQUIRE ?SYSCALL_BASE + + ;; The syscall table base pointer +?INIT_SYSCALL: + MOVE_M SFB SYSCALLVEC, A2 +#ifdef CODE_MODEL_PIC + EXTERN ?CODE_DISTANCE + REQUIRE ?CODE_DISTANCE + + ;; Add the value of ?CODE_DISTANCE calculated above + ADD A1, A2 +#endif + LDSR A2, 12 ; SCBP + + MOVE_M ((SFE SYSCALLVEC - SFB SYSCALLVEC)/4) - 1, A2 + LDSR A2, 11 ; SCCFG + + ENDMOD + +#endif + +;---------------------------------------------------------------; +; This segment part is required by the compiler when it is ; +; necessary to call constructors of global objects. ; +;---------------------------------------------------------------; + + MODULE ?CALL_MAIN + RSEG DIFUNCT(2) + RSEG CSTART:CODE:NOROOT(1) + PUBLIC ?cstart_call_ctors + + EXTERN __call_ctors + +?cstart_call_ctors: + MOVE_M SFB DIFUNCT, R1 + MOVE_M SFE DIFUNCT, R5 + + CALL_FUNC __call_ctors, LP, R6 + + +;---------------------------------------------------------------; +; Call C main() with no parameters. ; +;---------------------------------------------------------------; + + RSEG CSTART:CODE:NOROOT(1) + PUBLIC ?cstart_call_main + + EXTERN main + EXTERN exit + EXTERN __exit + +?cstart_call_main: + CALL_FUNC main, LP, R6 + +;---------------------------------------------------------------; +; If we come here we have returned from main with a 'return' ; +; statement, not with a call to exit() or abort(). ; +; In this case we must call exit() here for a nice ending. ; +; Note: The return value of main() is the argument to exit(). ; +;---------------------------------------------------------------; + CALL_FUNC exit, LP, R6 + +;---------------------------------------------------------------; +; We should never come here, but just in case. ; +;---------------------------------------------------------------; + + MOV __exit, LP + JMP [LP] + + PUBLIC ?BTT_cstart_end +?BTT_cstart_end: + + +;---------------------------------------------------------------; +; Copy a chunk of memory. ; +; A0 = Start of from block ; +; A1 = End of from block (+1) ; +; A2 = Start of to block ; +;---------------------------------------------------------------; + + PUBLIC ?seg_copy + PUBLIC ?seg_clear + + RSEG CSTART:CODE:NOROOT(1) + REQUIRE done + +cp_cont: LD.B 0[A0], R7 + ADD 1, A0 + ST.B R7, 0[A2] + ADD 1, A2 + + ;; Note: The entry point is here. +?seg_copy: CMP A0, A1 + BNE cp_cont + + RSEG CSTART:CODE:NOROOT(1) + +done: JMP [LP] + +;---------------------------------------------------------------; +; Clear a chunk of memory. ; +; A0 = Start of block ; +; A1 = End of block (+1) ; +;---------------------------------------------------------------; + + RSEG CSTART:CODE:NOROOT(1) + REQUIRE done + +?seg_clear: CMP A0, A1 + BE done +cl_cont: ST.B zero, 0[A0] + ADD 1, A0 + BR ?seg_clear + + ENDMOD + + +;---------------------------------------------------------------; +; _exit code ; +; ; +; Call destructors (if required), then fall through to __exit. ; +;---------------------------------------------------------------; + + MODULE ?_exit + PUBLIC _exit + PUBLIC ?BTT_exit_begin + EXTERN ?exit_restore2 + RSEG RCODE:CODE:NOROOT(1) + +?BTT_exit_begin: +_exit: + REQUIRE ?exit_restore2 + ;; If any of the two pieces of code "__cstart_call_dtors" + ;; or "__cstart_closeall" is called we need to save the + ;; argument to "_exit". However, since we never will + ;; from this function we can use a permanent register + ;; rather than storing the value on the stack. + + RSEG RCODE:CODE:NOROOT(1) + EXTERN ?exit_restore + PUBLIC ?exit_save +?exit_save: + REQUIRE ?exit_restore + + MOV R1, R29 + + RSEG RCODE:CODE:NOROOT(1) + PUBLIC __cstart_call_dtors + EXTERN __call_dtors + REQUIRE ?exit_save + + ;; This label is required by "__record_needed_destruction". + +__cstart_call_dtors: + CALL_FUNC __call_dtors, LP, R1 + + ENDMOD + + ;; A new module is needed so that a non-terminal-IO program + ;; doesn't include this, which requires __putchar. + + MODULE ?__cstart_closeall + RSEG RCODE:CODE:NOROOT(1) + + ;; When stdio is used, the following piece of code is + ;; required by the _Closreg macro. + + PUBLIC __cstart_closeall + EXTERN ?exit_save + REQUIRE ?exit_save + + ;; This label is required by _Closreg + +__cstart_closeall: + EXTERN _Close_all + CALL_FUNC _Close_all, LP, R1 + + ENDMOD + + ;; Restore the argument previously stored by the "save" section + ;; above. + + MODULE ?_exit_end + RSEG RCODE:CODE:NOROOT(1) + + PUBLIC ?exit_restore + EXTERN ?exit_restore2 + +?exit_restore: + REQUIRE ?exit_restore2 + MOV R29, R1 + + ENDMOD + + MODULE ?_exit_end2 + PUBLIC ?BTT_exit_end + RSEG RCODE:CODE:NOROOT(1) + + PUBLIC ?exit_restore2 + EXTERN __exit +?exit_restore2: + + MOV __exit, LP + JMP [LP] + +?BTT_exit_end: + ENDMOD + + +;---------------------------------------------------------------; +; Define the base of the base relative (brel) data for RAM. ; +; ; +; This empty segment should be places in front of the brel ; +; RAM data segments. ; +;---------------------------------------------------------------; + + MODULE ?BREL_BASE + PUBLIC ?BREL_BASE + + RSEG BREL_BASE:DATA:NOROOT(2) + +?BREL_BASE: + + ENDMOD + + +;---------------------------------------------------------------; +; Define the base of the base relative (brel) data for ROM. ; +; ; +; This empty segment should be places in front of the brel ; +; ROM data segment. ; +;---------------------------------------------------------------; + + MODULE ?BREL_CBASE + PUBLIC ?BREL_CBASE + + RSEG BREL_CBASE:CONST:NOROOT(2) + +?BREL_CBASE: + + ENDMOD + + +;---------------------------------------------------------------; +; Define the base of the short addressing (saddr) data. ; +; ; +; This empty segment should be places in front of the saddr ; +; data segments. ; +;---------------------------------------------------------------; + + MODULE ?SADDR_BASE + + RTMODEL "__reg_ep", "saddr" + + PUBLIC ?SADDR_BASE + RSEG SADDR_BASE:CONST:NOROOT(2) + + EXTERN ?INIT_SADDR_BASE + REQUIRE ?INIT_SADDR_BASE + +?SADDR_BASE: + + ENDMOD + + +;---------------------------------------------------------------; +; The base of the CALLT vector. ; +;---------------------------------------------------------------; + + MODULE ?CALLT_BASE + + PUBLIC ?CALLT_BASE + COMMON CLTVEC:CONST:NOROOT(2) + DATA +?CALLT_BASE: + + ENDMOD + + +#if __CORE__ >= __CORE_V850E2M__ + +;---------------------------------------------------------------; +; The base of the SYSCALL vector. ; +;---------------------------------------------------------------; + + MODULE ?SYSCALL_BASE + + PUBLIC ?SYSCALL_BASE + COMMON SYSCALLVEC:CONST:NOROOT(2) + DATA +?SYSCALL_BASE: + + ENDMOD + +#endif + +;---------------------------------------------------------------; +; The distance the code has been moved when using position ; +; independent code. ; +;---------------------------------------------------------------; + + MODULE ?CODE_DISTANCE + + RTMODEL "__code_model", "pic" + + PUBLIC ?CODE_DISTANCE + RSEG LIBRARY_N:DATA:NOROOT(2) + + EXTERN ?INIT_PIC + REQUIRE ?INIT_PIC + +?CODE_DISTANCE: + DS 4 + + ENDMOD + + +;---------------------------------------------------------------; +; A dummy "low level init" that will be used if the user ; +; hasn't defined this function. ; +;---------------------------------------------------------------; + + MODULE ?__low_level_init_stub + PUBLIC __low_level_init + RSEG RCODE:CODE:NOROOT +__low_level_init: + MOV 1, R1 + JMP [LP] + + ENDMOD + + END diff --git a/bsp/upd70f3454/io70f3454.h b/bsp/upd70f3454/io70f3454.h new file mode 100644 index 0000000000..07d44dca4d --- /dev/null +++ b/bsp/upd70f3454/io70f3454.h @@ -0,0 +1,1587 @@ +/*------------------------------------------------------------------------- + * Declarations of Peripheral I/O registers, I/O register bits, + * Interrupt/Exeption vectors, Trap vectors and, V850E only, Callt + * vectors for V850E microcontroller uPD70F3454. + * + * This header file can be used by both the V850 assembler, AV850, + * and the V850 C/C++ compiler, ICCV850. + * + * This header file is generated from the device file: + * DF3454.800 + * Format version 2.20, File version 1.00 + * + *-------------------------------------------------------------------------*/ + +#ifndef __IO70F3454_H__ +#define __IO70F3454_H__ + +#if ((__TID__ >> 8) & 0x7F) != 85 +#error "IO70F3454.H file for use with AV850 / ICCV850 only" +#endif + +#if ((__TID__ >> 4) & 0x0F) != 1 +#error "IO70F3454.H file for use with AV850 / ICCV850 option -v1 only" +#endif + +#pragma language=extended +#pragma system_include + +/*********************************************** + * I/O register macros + ***********************************************/ + +#include "io_macros.h" + +/*********************************************** + * Peripheral I/O register declarations + ***********************************************/ + + +__IO_REG16( PDL, 0xFFFFF004, __READ_WRITE ) +__IO_REG8_BIT( PDLL, 0xFFFFF004, __READ_WRITE ) +__IO_REG8_BIT( PDLH, 0xFFFFF005, __READ_WRITE ) + +__IO_REG16( PMDL, 0xFFFFF024, __READ_WRITE ) +__IO_REG8_BIT( PMDLL, 0xFFFFF024, __READ_WRITE ) +__IO_REG8_BIT( PMDLH, 0xFFFFF025, __READ_WRITE ) + +__IO_REG16( PMCDL, 0xFFFFF044, __READ_WRITE ) +__IO_REG8_BIT( PMCDLL, 0xFFFFF044, __READ_WRITE ) +__IO_REG8_BIT( PMCDLH, 0xFFFFF045, __READ_WRITE ) + +__IO_REG16( BSC, 0xFFFFF066, __READ_WRITE ) + +__IO_REG8( VSWC, 0xFFFFF06E, __READ_WRITE ) + +__IO_REG16( DSA0L, 0xFFFFF080, __READ_WRITE ) +__IO_REG16( DSA0H, 0xFFFFF082, __READ_WRITE ) +__IO_REG16( DDA0L, 0xFFFFF084, __READ_WRITE ) +__IO_REG16( DDA0H, 0xFFFFF086, __READ_WRITE ) +__IO_REG16( DSA1L, 0xFFFFF088, __READ_WRITE ) +__IO_REG16( DSA1H, 0xFFFFF08A, __READ_WRITE ) +__IO_REG16( DDA1L, 0xFFFFF08C, __READ_WRITE ) +__IO_REG16( DDA1H, 0xFFFFF08E, __READ_WRITE ) +__IO_REG16( DSA2L, 0xFFFFF090, __READ_WRITE ) +__IO_REG16( DSA2H, 0xFFFFF092, __READ_WRITE ) +__IO_REG16( DDA2L, 0xFFFFF094, __READ_WRITE ) +__IO_REG16( DDA2H, 0xFFFFF096, __READ_WRITE ) +__IO_REG16( DSA3L, 0xFFFFF098, __READ_WRITE ) +__IO_REG16( DSA3H, 0xFFFFF09A, __READ_WRITE ) +__IO_REG16( DDA3L, 0xFFFFF09C, __READ_WRITE ) +__IO_REG16( DDA3H, 0xFFFFF09E, __READ_WRITE ) + +__IO_REG16( DBC0, 0xFFFFF0C0, __READ_WRITE ) +__IO_REG16( DBC1, 0xFFFFF0C2, __READ_WRITE ) +__IO_REG16( DBC2, 0xFFFFF0C4, __READ_WRITE ) +__IO_REG16( DBC3, 0xFFFFF0C6, __READ_WRITE ) + +__IO_REG16( DADC0, 0xFFFFF0D0, __READ_WRITE ) +__IO_REG16( DADC1, 0xFFFFF0D2, __READ_WRITE ) +__IO_REG16( DADC2, 0xFFFFF0D4, __READ_WRITE ) +__IO_REG16( DADC3, 0xFFFFF0D6, __READ_WRITE ) + +__IO_REG8_BIT( DCHC0, 0xFFFFF0E0, __READ_WRITE ) +__IO_REG8_BIT( DCHC1, 0xFFFFF0E2, __READ_WRITE ) +__IO_REG8_BIT( DCHC2, 0xFFFFF0E4, __READ_WRITE ) +__IO_REG8_BIT( DCHC3, 0xFFFFF0E6, __READ_WRITE ) + +__IO_REG16( IMR0, 0xFFFFF100, __READ_WRITE ) +__IO_REG8_BIT( IMR0L, 0xFFFFF100, __READ_WRITE ) +__IO_REG8_BIT( IMR0H, 0xFFFFF101, __READ_WRITE ) +__IO_REG16( IMR1, 0xFFFFF102, __READ_WRITE ) +__IO_REG8_BIT( IMR1L, 0xFFFFF102, __READ_WRITE ) +__IO_REG8_BIT( IMR1H, 0xFFFFF103, __READ_WRITE ) +__IO_REG16( IMR2, 0xFFFFF104, __READ_WRITE ) +__IO_REG8_BIT( IMR2L, 0xFFFFF104, __READ_WRITE ) +__IO_REG8_BIT( IMR2H, 0xFFFFF105, __READ_WRITE ) +__IO_REG16( IMR3, 0xFFFFF106, __READ_WRITE ) +__IO_REG8_BIT( IMR3L, 0xFFFFF106, __READ_WRITE ) +__IO_REG8_BIT( IMR3H, 0xFFFFF107, __READ_WRITE ) +__IO_REG16( IMR4, 0xFFFFF108, __READ_WRITE ) +__IO_REG8_BIT( IMR4L, 0xFFFFF108, __READ_WRITE ) +__IO_REG8_BIT( IMR4H, 0xFFFFF109, __READ_WRITE ) +__IO_REG16( IMR5, 0xFFFFF10A, __READ_WRITE ) +__IO_REG8_BIT( IMR5L, 0xFFFFF10A, __READ_WRITE ) +__IO_REG8_BIT( IMR5H, 0xFFFFF10B, __READ_WRITE ) + +__IO_REG8_BIT( LVILIC, 0xFFFFF110, __READ_WRITE ) +__IO_REG8_BIT( LVIHIC, 0xFFFFF112, __READ_WRITE ) +__IO_REG8_BIT( PIC00, 0xFFFFF114, __READ_WRITE ) +__IO_REG8_BIT( PIC01, 0xFFFFF116, __READ_WRITE ) +__IO_REG8_BIT( PIC02, 0xFFFFF118, __READ_WRITE ) +__IO_REG8_BIT( PIC03, 0xFFFFF11A, __READ_WRITE ) +__IO_REG8_BIT( PIC04, 0xFFFFF11C, __READ_WRITE ) +__IO_REG8_BIT( PIC05, 0xFFFFF11E, __READ_WRITE ) +__IO_REG8_BIT( PIC06, 0xFFFFF120, __READ_WRITE ) +__IO_REG8_BIT( PIC07, 0xFFFFF122, __READ_WRITE ) +__IO_REG8_BIT( PIC08, 0xFFFFF124, __READ_WRITE ) +__IO_REG8_BIT( PIC09, 0xFFFFF126, __READ_WRITE ) +__IO_REG8_BIT( PIC10, 0xFFFFF128, __READ_WRITE ) +__IO_REG8_BIT( PIC11, 0xFFFFF12A, __READ_WRITE ) +__IO_REG8_BIT( PIC12, 0xFFFFF12C, __READ_WRITE ) +__IO_REG8_BIT( PIC13, 0xFFFFF12E, __READ_WRITE ) +__IO_REG8_BIT( PIC14, 0xFFFFF130, __READ_WRITE ) +__IO_REG8_BIT( PIC15, 0xFFFFF132, __READ_WRITE ) +__IO_REG8_BIT( PIC16, 0xFFFFF134, __READ_WRITE ) +__IO_REG8_BIT( PIC17, 0xFFFFF136, __READ_WRITE ) +__IO_REG8_BIT( PIC18, 0xFFFFF138, __READ_WRITE ) +__IO_REG8_BIT( CMPIC0L, 0xFFFFF13A, __READ_WRITE ) +__IO_REG8_BIT( CMPIC0F, 0xFFFFF13C, __READ_WRITE ) +__IO_REG8_BIT( CMPIC1L, 0xFFFFF13E, __READ_WRITE ) +__IO_REG8_BIT( CMPIC1F, 0xFFFFF140, __READ_WRITE ) +__IO_REG8_BIT( TB0OVIC, 0xFFFFF142, __READ_WRITE ) +__IO_REG8_BIT( TB0CCIC0, 0xFFFFF144, __READ_WRITE ) +__IO_REG8_BIT( TB0CCIC1, 0xFFFFF146, __READ_WRITE ) +__IO_REG8_BIT( TB0CCIC2, 0xFFFFF148, __READ_WRITE ) +__IO_REG8_BIT( TB0CCIC3, 0xFFFFF14A, __READ_WRITE ) +__IO_REG8_BIT( TB1OVIC, 0xFFFFF14C, __READ_WRITE ) +__IO_REG8_BIT( TB1CCIC0, 0xFFFFF14E, __READ_WRITE ) +__IO_REG8_BIT( TB1CCIC1, 0xFFFFF150, __READ_WRITE ) +__IO_REG8_BIT( TB1CCIC2, 0xFFFFF152, __READ_WRITE ) +__IO_REG8_BIT( TB1CCIC3, 0xFFFFF154, __READ_WRITE ) +__IO_REG8_BIT( TT0OVIC, 0xFFFFF156, __READ_WRITE ) +__IO_REG8_BIT( TT0CCIC0, 0xFFFFF158, __READ_WRITE ) +__IO_REG8_BIT( TT0CCIC1, 0xFFFFF15A, __READ_WRITE ) +__IO_REG8_BIT( TT0IECIC, 0xFFFFF15C, __READ_WRITE ) +__IO_REG8_BIT( TT1OVIC, 0xFFFFF15E, __READ_WRITE ) +__IO_REG8_BIT( TT1CCIC0, 0xFFFFF160, __READ_WRITE ) +__IO_REG8_BIT( TT1CCIC1, 0xFFFFF162, __READ_WRITE ) +__IO_REG8_BIT( TT1IECIC, 0xFFFFF164, __READ_WRITE ) +__IO_REG8_BIT( TA0OVIC, 0xFFFFF166, __READ_WRITE ) +__IO_REG8_BIT( TA0CCIC0, 0xFFFFF168, __READ_WRITE ) +__IO_REG8_BIT( TA0CCIC1, 0xFFFFF16A, __READ_WRITE ) +__IO_REG8_BIT( TA1OVIC, 0xFFFFF16C, __READ_WRITE ) +__IO_REG8_BIT( TA1CCIC0, 0xFFFFF16E, __READ_WRITE ) +__IO_REG8_BIT( TA1CCIC1, 0xFFFFF170, __READ_WRITE ) +__IO_REG8_BIT( TA2OVIC, 0xFFFFF172, __READ_WRITE ) +__IO_REG8_BIT( TA2CCIC0, 0xFFFFF174, __READ_WRITE ) +__IO_REG8_BIT( TA2CCIC1, 0xFFFFF176, __READ_WRITE ) +__IO_REG8_BIT( TA3OVIC, 0xFFFFF178, __READ_WRITE ) +__IO_REG8_BIT( TA3CCIC0, 0xFFFFF17A, __READ_WRITE ) +__IO_REG8_BIT( TA3CCIC1, 0xFFFFF17C, __READ_WRITE ) +__IO_REG8_BIT( TA4OVIC, 0xFFFFF17E, __READ_WRITE ) +__IO_REG8_BIT( TA4CCIC0, 0xFFFFF180, __READ_WRITE ) +__IO_REG8_BIT( TA4CCIC1, 0xFFFFF182, __READ_WRITE ) +__IO_REG8_BIT( DMAIC0, 0xFFFFF184, __READ_WRITE ) +__IO_REG8_BIT( DMAIC1, 0xFFFFF186, __READ_WRITE ) +__IO_REG8_BIT( DMAIC2, 0xFFFFF188, __READ_WRITE ) +__IO_REG8_BIT( DMAIC3, 0xFFFFF18A, __READ_WRITE ) +__IO_REG8_BIT( UREIC, 0xFFFFF18C, __READ_WRITE ) +__IO_REG8_BIT( URIC, 0xFFFFF18E, __READ_WRITE ) +__IO_REG8_BIT( UTIC, 0xFFFFF190, __READ_WRITE ) +__IO_REG8_BIT( UIFIC, 0xFFFFF192, __READ_WRITE ) +__IO_REG8_BIT( UTOIC, 0xFFFFF194, __READ_WRITE ) +__IO_REG8_BIT( UA0REIC, 0xFFFFF196, __READ_WRITE ) +__IO_REG8_BIT( UA0RIC, 0xFFFFF198, __READ_WRITE ) +__IO_REG8_BIT( UA0TIC, 0xFFFFF19A, __READ_WRITE ) +__IO_REG8_BIT( CB0REIC, 0xFFFFF19C, __READ_WRITE ) +__IO_REG8_BIT( CB0RIC, 0xFFFFF19E, __READ_WRITE ) +__IO_REG8_BIT( CB0TIC, 0xFFFFF1A0, __READ_WRITE ) +__IO_REG8_BIT( UA1REIC, 0xFFFFF1A2, __READ_WRITE ) +__IO_REG8_BIT( UA1RIC, 0xFFFFF1A4, __READ_WRITE ) +__IO_REG8_BIT( UA1TIC, 0xFFFFF1A6, __READ_WRITE ) +__IO_REG8_BIT( CB1REIC, 0xFFFFF1A8, __READ_WRITE ) +__IO_REG8_BIT( CB1RIC, 0xFFFFF1AA, __READ_WRITE ) +__IO_REG8_BIT( CB1TIC, 0xFFFFF1AC, __READ_WRITE ) +__IO_REG8_BIT( UA2REIC, 0xFFFFF1AE, __READ_WRITE ) +__IO_REG8_BIT( UA2RIC, 0xFFFFF1B0, __READ_WRITE ) +__IO_REG8_BIT( UA2TIC, 0xFFFFF1B2, __READ_WRITE ) +__IO_REG8_BIT( CB2REIC, 0xFFFFF1B4, __READ_WRITE ) +__IO_REG8_BIT( CB2RIC, 0xFFFFF1B6, __READ_WRITE ) +__IO_REG8_BIT( CB2TIC, 0xFFFFF1B8, __READ_WRITE ) +__IO_REG8_BIT( IICIC, 0xFFFFF1BA, __READ_WRITE ) +__IO_REG8_BIT( AD0IC, 0xFFFFF1BC, __READ_WRITE ) +__IO_REG8_BIT( AD1IC, 0xFFFFF1BE, __READ_WRITE ) +__IO_REG8_BIT( AD2IC, 0xFFFFF1C0, __READ_WRITE ) +__IO_REG8_BIT( TM0EQIC0, 0xFFFFF1C2, __READ_WRITE ) +__IO_REG8_BIT( TM1EQIC0, 0xFFFFF1C4, __READ_WRITE ) +__IO_REG8_BIT( TM2EQIC0, 0xFFFFF1C6, __READ_WRITE ) +__IO_REG8_BIT( TM3EQIC0, 0xFFFFF1C8, __READ_WRITE ) +__IO_REG8_BIT( ADT0IC, 0xFFFFF1CA, __READ_WRITE ) +__IO_REG8_BIT( ADT1IC, 0xFFFFF1CC, __READ_WRITE ) + +__IO_REG8_BIT( ISPR, 0xFFFFF1FA, __READ ) +__IO_REG8( PRCMD, 0xFFFFF1FC, __WRITE ) +__IO_REG8_BIT( PSC, 0xFFFFF1FE, __READ_WRITE ) +__IO_REG16( AD0CR0, 0xFFFFF200, __READ ) +__IO_REG8( AD0CR0H, 0xFFFFF201, __READ ) +__IO_REG16( AD0CR1, 0xFFFFF202, __READ ) +__IO_REG8( AD0CR1H, 0xFFFFF203, __READ ) +__IO_REG16( AD0CR2, 0xFFFFF204, __READ ) +__IO_REG8( AD0CR2H, 0xFFFFF205, __READ ) +__IO_REG16( AD0CR3, 0xFFFFF206, __READ ) +__IO_REG8( AD0CR3H, 0xFFFFF207, __READ ) +__IO_REG16( AD0CR4, 0xFFFFF208, __READ ) +__IO_REG8( AD0CR4H, 0xFFFFF209, __READ ) +__IO_REG16( AD0CR5, 0xFFFFF20A, __READ ) +__IO_REG8( AD0CR5H, 0xFFFFF20B, __READ ) +__IO_REG16( AD0CR6, 0xFFFFF20C, __READ ) +__IO_REG8( AD0CR6H, 0xFFFFF20D, __READ ) +__IO_REG16( AD0CR7, 0xFFFFF20E, __READ ) +__IO_REG8( AD0CR7H, 0xFFFFF20F, __READ ) +__IO_REG16( AD0CR8, 0xFFFFF210, __READ ) +__IO_REG8( AD0CR8H, 0xFFFFF211, __READ ) +__IO_REG16( AD0CR9, 0xFFFFF212, __READ ) +__IO_REG8( AD0CR9H, 0xFFFFF213, __READ ) +__IO_REG16( AD0CR10, 0xFFFFF214, __READ ) +__IO_REG8( AD0CR10H, 0xFFFFF215, __READ ) +__IO_REG16( AD0CR11, 0xFFFFF216, __READ ) +__IO_REG8( AD0CR11H, 0xFFFFF217, __READ ) +__IO_REG16( AD0CR12, 0xFFFFF218, __READ ) +__IO_REG8( AD0CR12H, 0xFFFFF219, __READ ) +__IO_REG16( AD0CR13, 0xFFFFF21A, __READ ) +__IO_REG8( AD0CR13H, 0xFFFFF21B, __READ ) +__IO_REG16( AD0CR14, 0xFFFFF21C, __READ ) +__IO_REG8( AD0CR14H, 0xFFFFF21D, __READ ) +__IO_REG16( AD0CR15, 0xFFFFF21E, __READ ) +__IO_REG8( AD0CR15H, 0xFFFFF21F, __READ ) +__IO_REG16( AD0SCM, 0xFFFFF220, __READ_WRITE ) +__IO_REG8_BIT( AD0SCML, 0xFFFFF220, __READ_WRITE ) +__IO_REG8_BIT( AD0SCMH, 0xFFFFF221, __READ_WRITE ) +__IO_REG8_BIT( AD0CTC, 0xFFFFF222, __READ_WRITE ) +__IO_REG16( AD0CHEN, 0xFFFFF224, __READ_WRITE ) +__IO_REG8_BIT( AD0CHENL, 0xFFFFF224, __READ_WRITE ) +__IO_REG8_BIT( AD0CHENH, 0xFFFFF225, __READ_WRITE ) + +__IO_REG8_BIT( AD0CTL0, 0xFFFFF230, __READ_WRITE ) +__IO_REG8_BIT( AD0TSEL, 0xFFFFF231, __READ_WRITE ) +__IO_REG8_BIT( AD0CH1, 0xFFFFF232, __READ_WRITE ) +__IO_REG8_BIT( AD0CH2, 0xFFFFF233, __READ_WRITE ) + +__IO_REG16( AD0ECR0, 0xFFFFF240, __READ ) +__IO_REG8( AD0ECR0H, 0xFFFFF241, __READ ) +__IO_REG16( AD0ECR1, 0xFFFFF242, __READ ) +__IO_REG8( AD0ECR1H, 0xFFFFF243, __READ ) +__IO_REG16( AD0ECR2, 0xFFFFF244, __READ ) +__IO_REG8( AD0ECR2H, 0xFFFFF245, __READ ) +__IO_REG16( AD0ECR3, 0xFFFFF246, __READ ) +__IO_REG8( AD0ECR3H, 0xFFFFF247, __READ ) +__IO_REG16( AD0ECR4, 0xFFFFF248, __READ ) +__IO_REG8( AD0ECR4H, 0xFFFFF249, __READ ) + +__IO_REG8( AD0FLG, 0xFFFFF254, __READ ) +__IO_REG8( AD0FLGB, 0xFFFFF255, __READ ) + +__IO_REG8( OP0CTL0, 0xFFFFF260, __READ_WRITE ) +__IO_REG8( CMP0CTL0, 0xFFFFF261, __READ_WRITE ) +__IO_REG8( CMP0CTL1, 0xFFFFF262, __READ ) +__IO_REG8( CMP0CTL2, 0xFFFFF263, __READ_WRITE ) +__IO_REG8( CMP0CTL3, 0xFFFFF264, __READ_WRITE ) + +__IO_REG8( AD0OCKS, 0xFFFFF270, __READ_WRITE ) + +__IO_REG8( AD1OCKS, 0xFFFFF274, __READ_WRITE ) + +__IO_REG8( CMPNFC0L, 0xFFFFF278, __READ_WRITE ) +__IO_REG8( CMPNFC0F, 0xFFFFF27A, __READ_WRITE ) +__IO_REG8( CMPNFC1L, 0xFFFFF27C, __READ_WRITE ) +__IO_REG8( CMPNFC1F, 0xFFFFF27E, __READ_WRITE ) +__IO_REG16( AD1CR0, 0xFFFFF280, __READ ) +__IO_REG8( AD1CR0H, 0xFFFFF281, __READ ) +__IO_REG16( AD1CR1, 0xFFFFF282, __READ ) +__IO_REG8( AD1CR1H, 0xFFFFF283, __READ ) +__IO_REG16( AD1CR2, 0xFFFFF284, __READ ) +__IO_REG8( AD1CR2H, 0xFFFFF285, __READ ) +__IO_REG16( AD1CR3, 0xFFFFF286, __READ ) +__IO_REG8( AD1CR3H, 0xFFFFF287, __READ ) +__IO_REG16( AD1CR4, 0xFFFFF288, __READ ) +__IO_REG8( AD1CR4H, 0xFFFFF289, __READ ) +__IO_REG16( AD1CR5, 0xFFFFF28A, __READ ) +__IO_REG8( AD1CR5H, 0xFFFFF28B, __READ ) +__IO_REG16( AD1CR6, 0xFFFFF28C, __READ ) +__IO_REG8( AD1CR6H, 0xFFFFF28D, __READ ) +__IO_REG16( AD1CR7, 0xFFFFF28E, __READ ) +__IO_REG8( AD1CR7H, 0xFFFFF28F, __READ ) +__IO_REG16( AD1CR8, 0xFFFFF290, __READ ) +__IO_REG8( AD1CR8H, 0xFFFFF291, __READ ) +__IO_REG16( AD1CR9, 0xFFFFF292, __READ ) +__IO_REG8( AD1CR9H, 0xFFFFF293, __READ ) +__IO_REG16( AD1CR10, 0xFFFFF294, __READ ) +__IO_REG8( AD1CR10H, 0xFFFFF295, __READ ) +__IO_REG16( AD1CR11, 0xFFFFF296, __READ ) +__IO_REG8( AD1CR11H, 0xFFFFF297, __READ ) +__IO_REG16( AD1CR12, 0xFFFFF298, __READ ) +__IO_REG8( AD1CR12H, 0xFFFFF299, __READ ) +__IO_REG16( AD1CR13, 0xFFFFF29A, __READ ) +__IO_REG8( AD1CR13H, 0xFFFFF29B, __READ ) +__IO_REG16( AD1CR14, 0xFFFFF29C, __READ ) +__IO_REG8( AD1CR14H, 0xFFFFF29D, __READ ) +__IO_REG16( AD1CR15, 0xFFFFF29E, __READ ) +__IO_REG8( AD1CR15H, 0xFFFFF29F, __READ ) +__IO_REG16( AD1SCM, 0xFFFFF2A0, __READ_WRITE ) +__IO_REG8_BIT( AD1SCML, 0xFFFFF2A0, __READ_WRITE ) +__IO_REG8_BIT( AD1SCMH, 0xFFFFF2A1, __READ_WRITE ) +__IO_REG8_BIT( AD1CTC, 0xFFFFF2A2, __READ_WRITE ) +__IO_REG16( AD1CHEN, 0xFFFFF2A4, __READ_WRITE ) +__IO_REG8_BIT( AD1CHENL, 0xFFFFF2A4, __READ_WRITE ) +__IO_REG8_BIT( AD1CHENH, 0xFFFFF2A5, __READ_WRITE ) + +__IO_REG8_BIT( AD1CTL0, 0xFFFFF2B0, __READ_WRITE ) +__IO_REG8_BIT( AD1TSEL, 0xFFFFF2B1, __READ_WRITE ) +__IO_REG8_BIT( AD1CH1, 0xFFFFF2B2, __READ_WRITE ) +__IO_REG8_BIT( AD1CH2, 0xFFFFF2B3, __READ_WRITE ) + +__IO_REG16( AD1ECR0, 0xFFFFF2C0, __READ ) +__IO_REG8( AD1ECR0H, 0xFFFFF2C1, __READ ) +__IO_REG16( AD1ECR1, 0xFFFFF2C2, __READ ) +__IO_REG8( AD1ECR1H, 0xFFFFF2C3, __READ ) +__IO_REG16( AD1ECR2, 0xFFFFF2C4, __READ ) +__IO_REG8( AD1ECR2H, 0xFFFFF2C5, __READ ) +__IO_REG16( AD1ECR3, 0xFFFFF2C6, __READ ) +__IO_REG8( AD1ECR3H, 0xFFFFF2C7, __READ ) +__IO_REG16( AD1ECR4, 0xFFFFF2C8, __READ ) + +__IO_REG8( AD1ECB4H, 0xFFFFF2D3, __READ ) +__IO_REG8( AD1FLG, 0xFFFFF2D4, __READ ) +__IO_REG8( AD1FLGB, 0xFFFFF2D5, __READ ) + +__IO_REG8( OP1CTL0, 0xFFFFF2E0, __READ_WRITE ) +__IO_REG8( CMP1CTL0, 0xFFFFF2E1, __READ_WRITE ) +__IO_REG8( CMP1CTL1, 0xFFFFF2E2, __READ ) +__IO_REG8( CMP1CTL2, 0xFFFFF2E3, __READ_WRITE ) +__IO_REG8( CMP1CTL3, 0xFFFFF2E4, __READ_WRITE ) + +__IO_REG8_BIT( ADTF, 0xFFFFF2F0, __READ_WRITE ) +__IO_REG8_BIT( ADTR, 0xFFFFF2F2, __READ_WRITE ) +__IO_REG8_BIT( CMPOF, 0xFFFFF2F4, __READ_WRITE ) +__IO_REG8_BIT( CMPOR, 0xFFFFF2F6, __READ_WRITE ) +__IO_REG8( ADLTS1, 0xFFFFF2F8, __READ_WRITE ) +__IO_REG8( ADLTS2, 0xFFFFF2FA, __READ_WRITE ) + +__IO_REG8( INTNFC14, 0xFFFFF310, __READ_WRITE ) +__IO_REG8( INTNFC15, 0xFFFFF312, __READ_WRITE ) +__IO_REG8( INTNFC16, 0xFFFFF314, __READ_WRITE ) + +__IO_REG8_BIT( P0, 0xFFFFF400, __READ_WRITE ) +__IO_REG8_BIT( P1, 0xFFFFF402, __READ_WRITE ) +__IO_REG8_BIT( P2, 0xFFFFF404, __READ_WRITE ) +__IO_REG8_BIT( P3, 0xFFFFF406, __READ_WRITE ) +__IO_REG8_BIT( P4, 0xFFFFF408, __READ_WRITE ) + +__IO_REG8_BIT( PM0, 0xFFFFF420, __READ_WRITE ) +__IO_REG8_BIT( PM1, 0xFFFFF422, __READ_WRITE ) +__IO_REG8_BIT( PM2, 0xFFFFF424, __READ_WRITE ) +__IO_REG8_BIT( PM3, 0xFFFFF426, __READ_WRITE ) +__IO_REG8_BIT( PM4, 0xFFFFF428, __READ_WRITE ) + +__IO_REG8_BIT( PMC0, 0xFFFFF440, __READ_WRITE ) +__IO_REG8_BIT( PMC1, 0xFFFFF442, __READ_WRITE ) +__IO_REG8_BIT( PMC2, 0xFFFFF444, __READ_WRITE ) +__IO_REG8_BIT( PMC3, 0xFFFFF446, __READ_WRITE ) +__IO_REG8_BIT( PMC4, 0xFFFFF448, __READ_WRITE ) + +__IO_REG8_BIT( PFC0, 0xFFFFF460, __READ_WRITE ) +__IO_REG8_BIT( PFC1, 0xFFFFF462, __READ_WRITE ) +__IO_REG8_BIT( PFC2, 0xFFFFF464, __READ_WRITE ) +__IO_REG8_BIT( PFC3, 0xFFFFF466, __READ_WRITE ) +__IO_REG8_BIT( PFC4, 0xFFFFF468, __READ_WRITE ) + +__IO_REG16( BCT0, 0xFFFFF480, __READ_WRITE ) + +__IO_REG16( DWC0, 0xFFFFF484, __READ_WRITE ) + +__IO_REG16( AWC, 0xFFFFF488, __READ_WRITE ) +__IO_REG16( BCC, 0xFFFFF48A, __READ_WRITE ) + +__IO_REG8( DVC, 0xFFFFF48E, __READ_WRITE ) + +__IO_REG8_BIT( TM0CTL0, 0xFFFFF540, __READ_WRITE ) + +__IO_REG16( TM0CMP0, 0xFFFFF544, __READ_WRITE ) + +__IO_REG8_BIT( TM1CTL0, 0xFFFFF550, __READ_WRITE ) + +__IO_REG16( TM1CMP0, 0xFFFFF554, __READ_WRITE ) + +__IO_REG8_BIT( TM2CTL0, 0xFFFFF560, __READ_WRITE ) + +__IO_REG16( TM2CMP0, 0xFFFFF564, __READ_WRITE ) + +__IO_REG8_BIT( TM3CTL0, 0xFFFFF570, __READ_WRITE ) + +__IO_REG16( TM3CMP0, 0xFFFFF574, __READ_WRITE ) + +__IO_REG8_BIT( TT0CTL0, 0xFFFFF580, __READ_WRITE ) +__IO_REG8_BIT( TT0CTL1, 0xFFFFF581, __READ_WRITE ) +__IO_REG8_BIT( TT0CTL2, 0xFFFFF582, __READ_WRITE ) +__IO_REG8_BIT( TT0IOC0, 0xFFFFF583, __READ_WRITE ) +__IO_REG8_BIT( TT0IOC1, 0xFFFFF584, __READ_WRITE ) +__IO_REG8_BIT( TT0IOC2, 0xFFFFF585, __READ_WRITE ) +__IO_REG8_BIT( TT0IOC3, 0xFFFFF586, __READ_WRITE ) +__IO_REG8_BIT( TT0OPT0, 0xFFFFF587, __READ_WRITE ) +__IO_REG8_BIT( TT0OPT1, 0xFFFFF588, __READ_WRITE ) +__IO_REG16( TT0CCR0, 0xFFFFF58A, __READ_WRITE ) +__IO_REG16( TT0CCR1, 0xFFFFF58C, __READ_WRITE ) +__IO_REG16( TT0CNT, 0xFFFFF58E, __READ ) +__IO_REG16( TT0TCW, 0xFFFFF590, __READ_WRITE ) + +__IO_REG8( TTNFC0, 0xFFFFF5A0, __READ_WRITE ) +__IO_REG8( TTNFC1, 0xFFFFF5A2, __READ_WRITE ) +__IO_REG8( TTISL0, 0xFFFFF5A4, __READ_WRITE ) +__IO_REG8( TTISL1, 0xFFFFF5A6, __READ_WRITE ) + +__IO_REG8_BIT( TT1CTL0, 0xFFFFF5C0, __READ_WRITE ) +__IO_REG8_BIT( TT1CTL1, 0xFFFFF5C1, __READ_WRITE ) +__IO_REG8_BIT( TT1CTL2, 0xFFFFF5C2, __READ_WRITE ) +__IO_REG8_BIT( TT1IOC0, 0xFFFFF5C3, __READ_WRITE ) +__IO_REG8_BIT( TT1IOC1, 0xFFFFF5C4, __READ_WRITE ) +__IO_REG8_BIT( TT1IOC2, 0xFFFFF5C5, __READ_WRITE ) +__IO_REG8_BIT( TT1IOC3, 0xFFFFF5C6, __READ_WRITE ) +__IO_REG8_BIT( TT1OPT0, 0xFFFFF5C7, __READ_WRITE ) +__IO_REG8_BIT( TT1OPT1, 0xFFFFF5C8, __READ_WRITE ) +__IO_REG16( TT1CCR0, 0xFFFFF5CA, __READ_WRITE ) +__IO_REG16( TT1CCR1, 0xFFFFF5CC, __READ_WRITE ) +__IO_REG16( TT1CNT, 0xFFFFF5CE, __READ ) +__IO_REG16( TT1TCW, 0xFFFFF5D0, __READ_WRITE ) + +__IO_REG8_BIT( TAB0CTL0, 0xFFFFF5E0, __READ_WRITE ) +__IO_REG8_BIT( TAB0CTL1, 0xFFFFF5E1, __READ_WRITE ) +__IO_REG8_BIT( TAB0IOC0, 0xFFFFF5E2, __READ_WRITE ) +__IO_REG8_BIT( TAB0IOC1, 0xFFFFF5E3, __READ_WRITE ) +__IO_REG8_BIT( TAB0IOC2, 0xFFFFF5E4, __READ_WRITE ) +__IO_REG8_BIT( TAB0OPT0, 0xFFFFF5E5, __READ_WRITE ) +__IO_REG16( TAB0CCR0, 0xFFFFF5E6, __READ_WRITE ) +__IO_REG16( TAB0CCR1, 0xFFFFF5E8, __READ_WRITE ) +__IO_REG16( TAB0CCR2, 0xFFFFF5EA, __READ_WRITE ) +__IO_REG16( TAB0CCR3, 0xFFFFF5EC, __READ_WRITE ) +__IO_REG16( TAB0CNT, 0xFFFFF5EE, __READ ) + +__IO_REG8_BIT( TAB0OPT1, 0xFFFFF600, __READ_WRITE ) +__IO_REG8_BIT( TAB0OPT2, 0xFFFFF601, __READ_WRITE ) +__IO_REG8_BIT( TAB0IOC3, 0xFFFFF602, __READ_WRITE ) +__IO_REG8_BIT( TAB0OPT3, 0xFFFFF603, __READ_WRITE ) +__IO_REG16( TAB0DTC, 0xFFFFF604, __READ_WRITE ) + +__IO_REG8_BIT( HZA0CTL0, 0xFFFFF610, __READ_WRITE ) +__IO_REG8_BIT( HZA0CTL1, 0xFFFFF611, __READ_WRITE ) + +__IO_REG8_BIT( HZA1CTL0, 0xFFFFF618, __READ_WRITE ) +__IO_REG8_BIT( HZA1CTL1, 0xFFFFF619, __READ_WRITE ) + +__IO_REG8_BIT( TAB1CTL0, 0xFFFFF620, __READ_WRITE ) +__IO_REG8_BIT( TAB1CTL1, 0xFFFFF621, __READ_WRITE ) +__IO_REG8_BIT( TAB1IOC0, 0xFFFFF622, __READ_WRITE ) +__IO_REG8_BIT( TAB1IOC1, 0xFFFFF623, __READ_WRITE ) +__IO_REG8_BIT( TAB1IOC2, 0xFFFFF624, __READ_WRITE ) +__IO_REG8_BIT( TAB1OPT0, 0xFFFFF625, __READ_WRITE ) +__IO_REG16( TAB1CCR0, 0xFFFFF626, __READ_WRITE ) +__IO_REG16( TAB1CCR1, 0xFFFFF628, __READ_WRITE ) +__IO_REG16( TAB1CCR2, 0xFFFFF62A, __READ_WRITE ) +__IO_REG16( TAB1CCR3, 0xFFFFF62C, __READ_WRITE ) +__IO_REG16( TAB1CNT, 0xFFFFF62E, __READ ) + +__IO_REG8_BIT( TAB1OPT1, 0xFFFFF640, __READ_WRITE ) +__IO_REG8_BIT( TAB1OPT2, 0xFFFFF641, __READ_WRITE ) +__IO_REG8_BIT( TAB1IOC3, 0xFFFFF642, __READ_WRITE ) +__IO_REG8_BIT( TAB1OPT3, 0xFFFFF643, __READ_WRITE ) +__IO_REG16( TAB1DTC, 0xFFFFF644, __READ_WRITE ) + +__IO_REG8_BIT( HZA2CTL0, 0xFFFFF650, __READ_WRITE ) +__IO_REG8_BIT( HZA2CTL1, 0xFFFFF651, __READ_WRITE ) + +__IO_REG8_BIT( HZA3CTL0, 0xFFFFF658, __READ_WRITE ) +__IO_REG8_BIT( HZA3CTL1, 0xFFFFF659, __READ_WRITE ) + +__IO_REG8_BIT( TAA0CTL0, 0xFFFFF660, __READ_WRITE ) +__IO_REG8_BIT( TAA0CTL1, 0xFFFFF661, __READ_WRITE ) + +__IO_REG8_BIT( TAA0OPT0, 0xFFFFF665, __READ_WRITE ) +__IO_REG16( TAA0CCR0, 0xFFFFF666, __READ_WRITE ) +__IO_REG16( TAA0CCR1, 0xFFFFF668, __READ_WRITE ) +__IO_REG16( TAA0CNT, 0xFFFFF66A, __READ ) + +__IO_REG8_BIT( TAA1CTL0, 0xFFFFF680, __READ_WRITE ) +__IO_REG8_BIT( TAA1CTL1, 0xFFFFF681, __READ_WRITE ) + +__IO_REG8_BIT( TAA1OPT0, 0xFFFFF685, __READ_WRITE ) +__IO_REG16( TAA1CCR0, 0xFFFFF686, __READ_WRITE ) +__IO_REG16( TAA1CCR1, 0xFFFFF688, __READ_WRITE ) +__IO_REG16( TAA1CNT, 0xFFFFF68A, __READ ) + +__IO_REG8_BIT( TAA2CTL0, 0xFFFFF6A0, __READ_WRITE ) +__IO_REG8_BIT( TAA2CTL1, 0xFFFFF6A1, __READ_WRITE ) +__IO_REG8_BIT( TAA2IOC0, 0xFFFFF6A2, __READ_WRITE ) +__IO_REG8_BIT( TAA2IOC1, 0xFFFFF6A3, __READ_WRITE ) +__IO_REG8_BIT( TAA2IOC2, 0xFFFFF6A4, __READ_WRITE ) +__IO_REG8_BIT( TAA2OPT0, 0xFFFFF6A5, __READ_WRITE ) +__IO_REG16( TAA2CCR0, 0xFFFFF6A6, __READ_WRITE ) +__IO_REG16( TAA2CCR1, 0xFFFFF6A8, __READ_WRITE ) +__IO_REG16( TAA2CNT, 0xFFFFF6AA, __READ ) + +__IO_REG8( OSTS, 0xFFFFF6C0, __READ_WRITE ) + +__IO_REG8_BIT( WDTM, 0xFFFFF6D0, __READ_WRITE ) +__IO_REG8( WDTE, 0xFFFFF6D1, __READ_WRITE ) + +__IO_REG8_BIT( PFCE0, 0xFFFFF700, __READ_WRITE ) +__IO_REG8_BIT( PFCE1, 0xFFFFF702, __READ_WRITE ) +__IO_REG8_BIT( PFCE2, 0xFFFFF704, __READ_WRITE ) +__IO_REG8_BIT( PFCE3, 0xFFFFF706, __READ_WRITE ) +__IO_REG8_BIT( PFCE4, 0xFFFFF708, __READ_WRITE ) + +__IO_REG8_BIT( SYS, 0xFFFFF802, __READ_WRITE ) + +__IO_REG8_BIT( DTFR0, 0xFFFFF810, __READ_WRITE ) +__IO_REG8_BIT( DTFR1, 0xFFFFF812, __READ_WRITE ) +__IO_REG8_BIT( DTFR2, 0xFFFFF814, __READ_WRITE ) +__IO_REG8_BIT( DTFR3, 0xFFFFF816, __READ_WRITE ) + +__IO_REG8_BIT( PSMR, 0xFFFFF820, __READ_WRITE ) + +__IO_REG8_BIT( PCC, 0xFFFFF828, __READ_WRITE ) + +__IO_REG8_BIT( PLLCTL, 0xFFFFF82C, __READ_WRITE ) + +__IO_REG8_BIT( CLM, 0xFFFFF870, __READ_WRITE ) + +__IO_REG8_BIT( RESF, 0xFFFFF888, __READ_WRITE ) + +__IO_REG8_BIT( LVIM, 0xFFFFF890, __READ_WRITE ) +__IO_REG8( LVIS, 0xFFFFF891, __READ_WRITE ) + +__IO_REG8_BIT( UA0CTL0, 0xFFFFFA00, __READ_WRITE ) +__IO_REG8( UA0CTL1, 0xFFFFFA01, __READ_WRITE ) +__IO_REG8( UA0CTL2, 0xFFFFFA02, __READ_WRITE ) +__IO_REG8_BIT( UA0OPT0, 0xFFFFFA03, __READ_WRITE ) +__IO_REG8_BIT( UA0STR, 0xFFFFFA04, __READ_WRITE ) +__IO_REG8( UA0RX, 0xFFFFFA06, __READ ) +__IO_REG8( UA0TX, 0xFFFFFA07, __READ_WRITE ) + +__IO_REG8_BIT( UA1CTL0, 0xFFFFFA10, __READ_WRITE ) +__IO_REG8( UA1CTL1, 0xFFFFFA11, __READ_WRITE ) +__IO_REG8( UA1CTL2, 0xFFFFFA12, __READ_WRITE ) +__IO_REG8_BIT( UA1OPT0, 0xFFFFFA13, __READ_WRITE ) +__IO_REG8_BIT( UA1STR, 0xFFFFFA14, __READ_WRITE ) +__IO_REG8( UA1RX, 0xFFFFFA16, __READ ) +__IO_REG8( UA1TX, 0xFFFFFA17, __READ_WRITE ) + +__IO_REG8_BIT( UA2CTL0, 0xFFFFFA20, __READ_WRITE ) +__IO_REG8( UA2CTL1, 0xFFFFFA21, __READ_WRITE ) +__IO_REG8( UA2CTL2, 0xFFFFFA22, __READ_WRITE ) +__IO_REG8_BIT( UA2OPT0, 0xFFFFFA23, __READ_WRITE ) +__IO_REG8_BIT( UA2STR, 0xFFFFFA24, __READ_WRITE ) +__IO_REG8( UA2RX, 0xFFFFFA26, __READ ) +__IO_REG8( UA2TX, 0xFFFFFA27, __READ_WRITE ) + +__IO_REG8_BIT( UBCTL0, 0xFFFFFA40, __READ_WRITE ) +__IO_REG16( UBCTL2, 0xFFFFFA42, __READ_WRITE ) +__IO_REG8_BIT( UBSTR, 0xFFFFFA44, __READ_WRITE ) +__IO_REG16( UBRXAP, 0xFFFFFA46, __READ ) +__IO_REG8( UBRX, 0xFFFFFA46, __READ ) +__IO_REG8( UBTX, 0xFFFFFA48, __WRITE ) +__IO_REG8_BIT( UBFIC0, 0xFFFFFA4A, __READ_WRITE ) +__IO_REG8_BIT( UBFIC1, 0xFFFFFA4B, __READ_WRITE ) +__IO_REG16( UBFIC2, 0xFFFFFA4C, __READ_WRITE ) +__IO_REG8( UBFIC2L, 0xFFFFFA4C, __READ_WRITE ) +__IO_REG8( UBFIC2H, 0xFFFFFA4D, __READ_WRITE ) +__IO_REG8( UBFIS0, 0xFFFFFA4E, __READ ) +__IO_REG8( UBFIS1, 0xFFFFFA4F, __READ ) + +__IO_REG8_BIT( TAA3CTL0, 0xFFFFFB00, __READ_WRITE ) +__IO_REG8_BIT( TAA3CTL1, 0xFFFFFB01, __READ_WRITE ) +__IO_REG8_BIT( TAA3IOC0, 0xFFFFFB02, __READ_WRITE ) +__IO_REG8_BIT( TAA3IOC1, 0xFFFFFB03, __READ_WRITE ) +__IO_REG8_BIT( TAA3IOC2, 0xFFFFFB04, __READ_WRITE ) +__IO_REG8_BIT( TAA3OPT0, 0xFFFFFB05, __READ_WRITE ) +__IO_REG16( TAA3CCR0, 0xFFFFFB06, __READ_WRITE ) +__IO_REG16( TAA3CCR1, 0xFFFFFB08, __READ_WRITE ) +__IO_REG16( TAA3CNT, 0xFFFFFB0A, __READ ) + +__IO_REG8_BIT( TAA4CTL0, 0xFFFFFB20, __READ_WRITE ) +__IO_REG8_BIT( TAA4CTL1, 0xFFFFFB21, __READ_WRITE ) +__IO_REG8_BIT( TAA4IOC0, 0xFFFFFB22, __READ_WRITE ) +__IO_REG8_BIT( TAA4IOC1, 0xFFFFFB23, __READ_WRITE ) +__IO_REG8_BIT( TAA4IOC2, 0xFFFFFB24, __READ_WRITE ) +__IO_REG8_BIT( TAA4OPT0, 0xFFFFFB25, __READ_WRITE ) +__IO_REG16( TAA4CCR0, 0xFFFFFB26, __READ_WRITE ) +__IO_REG16( TAA4CCR1, 0xFFFFFB28, __READ_WRITE ) +__IO_REG16( TAA4CNT, 0xFFFFFB2A, __READ ) + +__IO_REG8( TANFC2, 0xFFFFFB40, __READ_WRITE ) +__IO_REG8( TANFC3, 0xFFFFFB42, __READ_WRITE ) +__IO_REG8( TANFC4, 0xFFFFFB44, __READ_WRITE ) + +__IO_REG8_BIT( AD2M0, 0xFFFFFB80, __READ_WRITE ) +__IO_REG8_BIT( AD2M1, 0xFFFFFB81, __READ_WRITE ) +__IO_REG8_BIT( AD2S, 0xFFFFFB82, __READ_WRITE ) + +__IO_REG16( AD2CR0, 0xFFFFFB90, __READ ) +__IO_REG8( AD2CR0H, 0xFFFFFB91, __READ ) +__IO_REG16( AD2CR1, 0xFFFFFB92, __READ ) +__IO_REG8( AD2CR1H, 0xFFFFFB93, __READ ) +__IO_REG16( AD2CR2, 0xFFFFFB94, __READ ) +__IO_REG8( AD2CR2H, 0xFFFFFB95, __READ ) +__IO_REG16( AD2CR3, 0xFFFFFB96, __READ ) +__IO_REG8( AD2CR3H, 0xFFFFFB97, __READ ) +__IO_REG16( AD2CR4, 0xFFFFFB98, __READ ) +__IO_REG8( AD2CR4H, 0xFFFFFB99, __READ ) +__IO_REG16( AD2CR5, 0xFFFFFB9A, __READ ) +__IO_REG8( AD2CR5H, 0xFFFFFB9B, __READ ) +__IO_REG16( AD2CR6, 0xFFFFFB9C, __READ ) +__IO_REG8( AD2CR6H, 0xFFFFFB9D, __READ ) +__IO_REG16( AD2CR7, 0xFFFFFB9E, __READ ) +__IO_REG8( AD2CR7H, 0xFFFFFB9F, __READ ) + +__IO_REG8_BIT( P7, 0xFFFFFBB0, __READ_WRITE ) + +__IO_REG8_BIT( PMC7, 0xFFFFFBB8, __READ_WRITE ) + +__IO_REG8_BIT( INTF0, 0xFFFFFC00, __READ_WRITE ) +__IO_REG8_BIT( INTF1, 0xFFFFFC02, __READ_WRITE ) +__IO_REG8_BIT( INTF2, 0xFFFFFC04, __READ_WRITE ) + +__IO_REG8_BIT( INTR0, 0xFFFFFC20, __READ_WRITE ) +__IO_REG8_BIT( INTR1, 0xFFFFFC22, __READ_WRITE ) +__IO_REG8_BIT( INTR2, 0xFFFFFC24, __READ_WRITE ) + +__IO_REG8_BIT( PU0, 0xFFFFFC40, __READ_WRITE ) +__IO_REG8_BIT( PU1, 0xFFFFFC42, __READ_WRITE ) +__IO_REG8_BIT( PU2, 0xFFFFFC44, __READ_WRITE ) +__IO_REG8_BIT( PU3, 0xFFFFFC46, __READ_WRITE ) +__IO_REG8_BIT( PU4, 0xFFFFFC48, __READ_WRITE ) + +__IO_REG8_BIT( PF3, 0xFFFFFC66, __READ_WRITE ) + +__IO_REG8_BIT( CB0CTL0, 0xFFFFFD00, __READ_WRITE ) +__IO_REG8_BIT( CB0CTL1, 0xFFFFFD01, __READ_WRITE ) +__IO_REG8( CB0CTL2, 0xFFFFFD02, __READ_WRITE ) +__IO_REG8_BIT( CB0STR, 0xFFFFFD03, __READ_WRITE ) +__IO_REG16( CB0RX, 0xFFFFFD04, __READ ) +__IO_REG8( CB0RXL, 0xFFFFFD04, __READ ) +__IO_REG16( CB0TX, 0xFFFFFD06, __READ_WRITE ) +__IO_REG8( CB0TXL, 0xFFFFFD06, __READ_WRITE ) + +__IO_REG8_BIT( CB1CTL0, 0xFFFFFD10, __READ_WRITE ) +__IO_REG8_BIT( CB1CTL1, 0xFFFFFD11, __READ_WRITE ) +__IO_REG8( CB1CTL2, 0xFFFFFD12, __READ_WRITE ) +__IO_REG8_BIT( CB1STR, 0xFFFFFD13, __READ_WRITE ) +__IO_REG16( CB1RX, 0xFFFFFD14, __READ ) +__IO_REG8( CB1RXL, 0xFFFFFD14, __READ ) +__IO_REG16( CB1TX, 0xFFFFFD16, __READ_WRITE ) +__IO_REG8( CB1TXL, 0xFFFFFD16, __READ_WRITE ) + +__IO_REG8_BIT( CB2CTL0, 0xFFFFFD20, __READ_WRITE ) +__IO_REG8_BIT( CB2CTL1, 0xFFFFFD21, __READ_WRITE ) +__IO_REG8( CB2CTL2, 0xFFFFFD22, __READ_WRITE ) +__IO_REG8_BIT( CB2STR, 0xFFFFFD23, __READ_WRITE ) +__IO_REG16( CB2RX, 0xFFFFFD24, __READ ) +__IO_REG8( CB2RXL, 0xFFFFFD24, __READ ) +__IO_REG16( CB2TX, 0xFFFFFD26, __READ_WRITE ) +__IO_REG8( CB2TXL, 0xFFFFFD26, __READ_WRITE ) + +__IO_REG8( IIC0, 0xFFFFFD80, __READ_WRITE ) +__IO_REG8_BIT( IICC0, 0xFFFFFD82, __READ_WRITE ) +__IO_REG8( SVA0, 0xFFFFFD83, __READ_WRITE ) +__IO_REG8_BIT( IICCL0, 0xFFFFFD84, __READ_WRITE ) +__IO_REG8_BIT( IICX0, 0xFFFFFD85, __READ_WRITE ) +__IO_REG8_BIT( IICS0, 0xFFFFFD86, __READ ) + +__IO_REG8_BIT( IICF0, 0xFFFFFD8A, __READ_WRITE ) + +__IO_REG8( IICOCKS, 0xFFFFFD90, __READ_WRITE ) + +__IO_REG16( PUDL, 0xFFFFFF44, __READ_WRITE ) +__IO_REG8_BIT( PUDLL, 0xFFFFFF44, __READ_WRITE ) +__IO_REG8_BIT( PUDLH, 0xFFFFFF45, __READ_WRITE ) + +/*********************************************** + * Peripheral I/O bit declarations + ***********************************************/ + +#ifdef __IAR_SYSTEMS_ICC__ + +#define E00 DCHC0_bit.no0 +#define STG0 DCHC0_bit.no1 +#define INIT0 DCHC0_bit.no2 +#define MLE0 DCHC0_bit.no3 +#define TC0 DCHC0_bit.no7 + +#define E11 DCHC1_bit.no0 +#define STG1 DCHC1_bit.no1 +#define INIT1 DCHC1_bit.no2 +#define MLE1 DCHC1_bit.no3 +#define TC1 DCHC1_bit.no7 + +#define E22 DCHC2_bit.no0 +#define STG2 DCHC2_bit.no1 +#define INIT2 DCHC2_bit.no2 +#define MLE2 DCHC2_bit.no3 +#define TC2 DCHC2_bit.no7 + +#define E33 DCHC3_bit.no0 +#define STG3 DCHC3_bit.no1 +#define INIT3 DCHC3_bit.no2 +#define MLE3 DCHC3_bit.no3 +#define TC3 DCHC3_bit.no7 + +#define LVILMK LVILIC_bit.no6 +#define LVILIF LVILIC_bit.no7 + +#define LVIHMK LVIHIC_bit.no6 +#define LVIHIF LVIHIC_bit.no7 + +#define PMK00 PIC00_bit.no6 +#define PIF00 PIC00_bit.no7 + +#define PMK01 PIC01_bit.no6 +#define PIF01 PIC01_bit.no7 + +#define PMK02 PIC02_bit.no6 +#define PIF02 PIC02_bit.no7 + +#define PMK03 PIC03_bit.no6 +#define PIF03 PIC03_bit.no7 + +#define PMK04 PIC04_bit.no6 +#define PIF04 PIC04_bit.no7 + +#define PMK05 PIC05_bit.no6 +#define PIF05 PIC05_bit.no7 + +#define PMK06 PIC06_bit.no6 +#define PIF06 PIC06_bit.no7 + +#define PMK07 PIC07_bit.no6 +#define PIF07 PIC07_bit.no7 + +#define PMK08 PIC08_bit.no6 +#define PIF08 PIC08_bit.no7 + +#define PMK09 PIC09_bit.no6 +#define PIF09 PIC09_bit.no7 + +#define PMK10 PIC10_bit.no6 +#define PIF10 PIC10_bit.no7 + +#define PMK11 PIC11_bit.no6 +#define PIF11 PIC11_bit.no7 + +#define PMK12 PIC12_bit.no6 +#define PIF12 PIC12_bit.no7 + +#define PMK13 PIC13_bit.no6 +#define PIF13 PIC13_bit.no7 + +#define PMK14 PIC14_bit.no6 +#define PIF14 PIC14_bit.no7 + +#define PMK15 PIC15_bit.no6 +#define PIF15 PIC15_bit.no7 + +#define PMK16 PIC16_bit.no6 +#define PIF16 PIC16_bit.no7 + +#define PMK17 PIC17_bit.no6 +#define PIF17 PIC17_bit.no7 + +#define PMK18 PIC18_bit.no6 +#define PIF18 PIC18_bit.no7 + +#define CMPMK0L CMPIC0L_bit.no6 +#define CMPIF0L CMPIC0L_bit.no7 + +#define CMPMK0F CMPIC0F_bit.no6 +#define CMPIF0F CMPIC0F_bit.no7 + +#define CMPMK1L CMPIC1L_bit.no6 +#define CMPIF1L CMPIC1L_bit.no7 + +#define CMPMK1F CMPIC1F_bit.no6 +#define CMPIF1F CMPIC1F_bit.no7 + +#define TB0OVMK TB0OVIC_bit.no6 +#define TB0OVIF TB0OVIC_bit.no7 + +#define TB0CCMK0 TB0CCIC0_bit.no6 +#define TB0CCIF0 TB0CCIC0_bit.no7 + +#define TB0CCMK1 TB0CCIC1_bit.no6 +#define TB0CCIF1 TB0CCIC1_bit.no7 + +#define TB0CCMK2 TB0CCIC2_bit.no6 +#define TB0CCIF2 TB0CCIC2_bit.no7 + +#define TB0CCMK3 TB0CCIC3_bit.no6 +#define TB0CCIF3 TB0CCIC3_bit.no7 + +#define TB1OVMK TB1OVIC_bit.no6 +#define TB1OVIF TB1OVIC_bit.no7 + +#define TB1CCMK0 TB1CCIC0_bit.no6 +#define TB1CCIF0 TB1CCIC0_bit.no7 + +#define TB1CCMK1 TB1CCIC1_bit.no6 +#define TB1CCIF1 TB1CCIC1_bit.no7 + +#define TB1CCMK2 TB1CCIC2_bit.no6 +#define TB1CCIF2 TB1CCIC2_bit.no7 + +#define TB1CCMK3 TB1CCIC3_bit.no6 +#define TB1CCIF3 TB1CCIC3_bit.no7 + +#define TT0OVMK TT0OVIC_bit.no6 +#define TT0OVIF TT0OVIC_bit.no7 + +#define TT0CCMK0 TT0CCIC0_bit.no6 +#define TT0CCIF0 TT0CCIC0_bit.no7 + +#define TT0CCMK1 TT0CCIC1_bit.no6 +#define TT0CCIF1 TT0CCIC1_bit.no7 + +#define TT0IECMK TT0IECIC_bit.no6 +#define TT0IECIF TT0IECIC_bit.no7 + +#define TT1OVMK TT1OVIC_bit.no6 +#define TT1OVIF TT1OVIC_bit.no7 + +#define TT1CCMK0 TT1CCIC0_bit.no6 +#define TT1CCIF0 TT1CCIC0_bit.no7 + +#define TT1CCMK1 TT1CCIC1_bit.no6 +#define TT1CCIF1 TT1CCIC1_bit.no7 + +#define TT1IECMK TT1IECIC_bit.no6 +#define TT1IECIF TT1IECIC_bit.no7 + +#define TA0OVMK TA0OVIC_bit.no6 +#define TA0OVIF TA0OVIC_bit.no7 + +#define TA0CCMK0 TA0CCIC0_bit.no6 +#define TA0CCIF0 TA0CCIC0_bit.no7 + +#define TA0CCMK1 TA0CCIC1_bit.no6 +#define TA0CCIF1 TA0CCIC1_bit.no7 + +#define TA1OVMK TA1OVIC_bit.no6 +#define TA1OVIF TA1OVIC_bit.no7 + +#define TA1CCMK0 TA1CCIC0_bit.no6 +#define TA1CCIF0 TA1CCIC0_bit.no7 + +#define TA1CCMK1 TA1CCIC1_bit.no6 +#define TA1CCIF1 TA1CCIC1_bit.no7 + +#define TA2OVMK TA2OVIC_bit.no6 +#define TA2OVIF TA2OVIC_bit.no7 + +#define TA2CCMK0 TA2CCIC0_bit.no6 +#define TA2CCIF0 TA2CCIC0_bit.no7 + +#define TA2CCMK1 TA2CCIC1_bit.no6 +#define TA2CCIF1 TA2CCIC1_bit.no7 + +#define TA3OVMK TA3OVIC_bit.no6 +#define TA3OVIF TA3OVIC_bit.no7 + +#define TA3CCMK0 TA3CCIC0_bit.no6 +#define TA3CCIF0 TA3CCIC0_bit.no7 + +#define TA3CCMK1 TA3CCIC1_bit.no6 +#define TA3CCIF1 TA3CCIC1_bit.no7 + +#define TA4OVMK TA4OVIC_bit.no6 +#define TA4OVIF TA4OVIC_bit.no7 + +#define TA4CCMK0 TA4CCIC0_bit.no6 +#define TA4CCIF0 TA4CCIC0_bit.no7 + +#define TA4CCMK1 TA4CCIC1_bit.no6 +#define TA4CCIF1 TA4CCIC1_bit.no7 + +#define DMAMK0 DMAIC0_bit.no6 +#define DMAIF0 DMAIC0_bit.no7 + +#define DMAMK1 DMAIC1_bit.no6 +#define DMAIF1 DMAIC1_bit.no7 + +#define DMAMK2 DMAIC2_bit.no6 +#define DMAIF2 DMAIC2_bit.no7 + +#define DMAMK3 DMAIC3_bit.no6 +#define DMAIF3 DMAIC3_bit.no7 + +#define UREMK UREIC_bit.no6 +#define UREIF UREIC_bit.no7 + +#define URMK URIC_bit.no6 +#define URIF URIC_bit.no7 + +#define UTMK UTIC_bit.no6 +#define UTIF UTIC_bit.no7 + +#define UIFMK UIFIC_bit.no6 +#define UIFIF UIFIC_bit.no7 + +#define UTOMK UTOIC_bit.no6 +#define UTOIF UTOIC_bit.no7 + +#define UA0REMK UA0REIC_bit.no6 +#define UA0REIF UA0REIC_bit.no7 + +#define UA0RMK UA0RIC_bit.no6 +#define UA0RIF UA0RIC_bit.no7 + +#define UA0TMK UA0TIC_bit.no6 +#define UA0TIF UA0TIC_bit.no7 + +#define CB0REMK CB0REIC_bit.no6 +#define CB0REIF CB0REIC_bit.no7 + +#define CB0RMK CB0RIC_bit.no6 +#define CB0RIF CB0RIC_bit.no7 + +#define CB0TMK CB0TIC_bit.no6 +#define CB0TIF CB0TIC_bit.no7 + +#define UA1REMK UA1REIC_bit.no6 +#define UA1REIF UA1REIC_bit.no7 + +#define UA1RMK UA1RIC_bit.no6 +#define UA1RIF UA1RIC_bit.no7 + +#define UA1TMK UA1TIC_bit.no6 +#define UA1TIF UA1TIC_bit.no7 + +#define CB1REMK CB1REIC_bit.no6 +#define CB1REIF CB1REIC_bit.no7 + +#define CB1RMK CB1RIC_bit.no6 +#define CB1RIF CB1RIC_bit.no7 + +#define CB1TMK CB1TIC_bit.no6 +#define CB1TIF CB1TIC_bit.no7 + +#define UA2REMK UA2REIC_bit.no6 +#define UA2REIF UA2REIC_bit.no7 + +#define UA2RMK UA2RIC_bit.no6 +#define UA2RIF UA2RIC_bit.no7 + +#define UA2TMK UA2TIC_bit.no6 +#define UA2TIF UA2TIC_bit.no7 + +#define CB2REMK CB2REIC_bit.no6 +#define CB2REIF CB2REIC_bit.no7 + +#define CB2RMK CB2RIC_bit.no6 +#define CB2RIF CB2RIC_bit.no7 + +#define CB2TMK CB2TIC_bit.no6 +#define CB2TIF CB2TIC_bit.no7 + +#define IICMK IICIC_bit.no6 +#define IICIF IICIC_bit.no7 + +#define AD0MK AD0IC_bit.no6 +#define AD0IF AD0IC_bit.no7 + +#define AD1MK AD1IC_bit.no6 +#define AD1IF AD1IC_bit.no7 + +#define AD2MK AD2IC_bit.no6 +#define AD2IF AD2IC_bit.no7 + +#define TM0EQMK0 TM0EQIC0_bit.no6 +#define TM0EQIF0 TM0EQIC0_bit.no7 + +#define TM1EQMK0 TM1EQIC0_bit.no6 +#define TM1EQIF0 TM1EQIC0_bit.no7 + +#define TM2EQMK0 TM2EQIC0_bit.no6 +#define TM2EQIF0 TM2EQIC0_bit.no7 + +#define TM3EQMK0 TM3EQIC0_bit.no6 +#define TM3EQIF0 TM3EQIC0_bit.no7 + +#define ADT0MK ADT0IC_bit.no6 +#define ADT0IF ADT0IC_bit.no7 + +#define ADT1MK ADT1IC_bit.no6 +#define ADT1IF ADT1IC_bit.no7 + +#define ISPR0 ISPR_bit.no0 +#define ISPR1 ISPR_bit.no1 +#define ISPR2 ISPR_bit.no2 +#define ISPR3 ISPR_bit.no3 +#define ISPR4 ISPR_bit.no4 +#define ISPR5 ISPR_bit.no5 +#define ISPR6 ISPR_bit.no6 +#define ISPR7 ISPR_bit.no7 + +#define STB PSC_bit.no1 +#define INTM PSC_bit.no4 +#define NMI0M PSC_bit.no5 + +#define AD0CE AD0SCMH_bit.no7 + +#define AD1CE AD1SCMH_bit.no7 + +#define TM0CE TM0CTL0_bit.no7 + +#define TM1CE TM1CTL0_bit.no7 + +#define TM2CE TM2CTL0_bit.no7 + +#define TM3CE TM3CTL0_bit.no7 + +#define TT0CE TT0CTL0_bit.no7 + +#define TT0OE0 TT0IOC0_bit.no0 +#define TT0OE1 TT0IOC0_bit.no2 + +#define TT0OVF TT0OPT0_bit.no0 + +#define TT0ESF TT0OPT1_bit.no0 +#define TT0EOF TT0OPT1_bit.no1 +#define TT0EUF TT0OPT1_bit.no2 + +#define TT1CE TT1CTL0_bit.no7 + +#define TT1OE0 TT1IOC0_bit.no0 +#define TT1OE1 TT1IOC0_bit.no2 + +#define TT1OVF TT1OPT0_bit.no0 + +#define TT1ESF TT1OPT1_bit.no0 +#define TT1EOF TT1OPT1_bit.no1 +#define TT1EUF TT1OPT1_bit.no2 + +#define TAB0CE TAB0CTL0_bit.no7 + +#define TAB0OE0 TAB0IOC0_bit.no0 +#define TAB0OE1 TAB0IOC0_bit.no2 +#define TAB0OE2 TAB0IOC0_bit.no4 +#define TAB0OE3 TAB0IOC0_bit.no6 + +#define TAB0OVF TAB0OPT0_bit.no0 +#define TAB0CUF TAB0OPT0_bit.no1 +#define TAB0CMS TAB0OPT0_bit.no2 +#define TAB0CCS0 TAB0OPT0_bit.no4 +#define TAB0CCS1 TAB0OPT0_bit.no5 +#define TAB0CCS2 TAB0OPT0_bit.no6 +#define TAB0CCS3 TAB0OPT0_bit.no7 + +#define TAB0IOE TAB0OPT1_bit.no6 +#define TAB0ICE TAB0OPT1_bit.no7 + +#define TAB0AT0 TAB0OPT2_bit.no0 +#define TAB0AT1 TAB0OPT2_bit.no1 +#define TAB0AT2 TAB0OPT2_bit.no2 +#define TAB0AT3 TAB0OPT2_bit.no3 +#define TAB0ATM2 TAB0OPT2_bit.no4 +#define TAB0ATM3 TAB0OPT2_bit.no5 +#define TAB0DTM TAB0OPT2_bit.no6 +#define TAB0RDE TAB0OPT2_bit.no7 + +#define TAB0OEB1 TAB0IOC3_bit.no2 +#define TAB0OLB1 TAB0IOC3_bit.no3 +#define TAB0OEB2 TAB0IOC3_bit.no4 +#define TAB0OLB2 TAB0IOC3_bit.no5 +#define TAB0OEB3 TAB0IOC3_bit.no6 +#define TAB0OLB3 TAB0IOC3_bit.no7 + +#define TAB0AT4 TAB0OPT3_bit.no0 +#define TAB0AT5 TAB0OPT3_bit.no1 +#define TAB0AT6 TAB0OPT3_bit.no2 +#define TAB0AT7 TAB0OPT3_bit.no3 +#define TAB0ATM6 TAB0OPT3_bit.no4 +#define TAB0ATM7 TAB0OPT3_bit.no5 + +#define HZA0DCF0 HZA0CTL0_bit.no0 +#define HZA0DCC0 HZA0CTL0_bit.no2 +#define HZA0DCT0 HZA0CTL0_bit.no3 +#define HZA0DCM0 HZA0CTL0_bit.no6 +#define HZA0DCE0 HZA0CTL0_bit.no7 + +#define HZA0DCF1 HZA0CTL1_bit.no0 +#define HZA0DCC1 HZA0CTL1_bit.no2 +#define HZA0DCT1 HZA0CTL1_bit.no3 +#define HZA0DCM1 HZA0CTL1_bit.no6 +#define HZA0DCE1 HZA0CTL1_bit.no7 + +#define HZA1DCF0 HZA1CTL0_bit.no0 +#define HZA1DCC0 HZA1CTL0_bit.no2 +#define HZA1DCT0 HZA1CTL0_bit.no3 +#define HZA1DCM0 HZA1CTL0_bit.no6 +#define HZA1DCE0 HZA1CTL0_bit.no7 + +#define HZA1DCF1 HZA1CTL1_bit.no0 +#define HZA1DCC1 HZA1CTL1_bit.no2 +#define HZA1DCT1 HZA1CTL1_bit.no3 +#define HZA1DCM1 HZA1CTL1_bit.no6 +#define HZA1DCE1 HZA1CTL1_bit.no7 + +#define TAB1CE TAB1CTL0_bit.no7 + +#define TAB1OE0 TAB1IOC0_bit.no0 +#define TAB1OE1 TAB1IOC0_bit.no2 +#define TAB1OE2 TAB1IOC0_bit.no4 +#define TAB1OE3 TAB1IOC0_bit.no6 + +#define TAB1OVF TAB1OPT0_bit.no0 +#define TAB1CUF TAB1OPT0_bit.no1 +#define TAB1CMS TAB1OPT0_bit.no2 +#define TAB1CCS0 TAB1OPT0_bit.no4 +#define TAB1CCS1 TAB1OPT0_bit.no5 +#define TAB1CCS2 TAB1OPT0_bit.no6 +#define TAB1CCS3 TAB1OPT0_bit.no7 + +#define TAB1IOE TAB1OPT1_bit.no6 +#define TAB1ICE TAB1OPT1_bit.no7 + +#define TAB1AT0 TAB1OPT2_bit.no0 +#define TAB1AT1 TAB1OPT2_bit.no1 +#define TAB1AT2 TAB1OPT2_bit.no2 +#define TAB1AT3 TAB1OPT2_bit.no3 +#define TAB1ATM2 TAB1OPT2_bit.no4 +#define TAB1ATM3 TAB1OPT2_bit.no5 +#define TAB1DTM TAB1OPT2_bit.no6 +#define TAB1RDE TAB1OPT2_bit.no7 + +#define TAB1OEB1 TAB1IOC3_bit.no2 +#define TAB1OLB1 TAB1IOC3_bit.no3 +#define TAB1OEB2 TAB1IOC3_bit.no4 +#define TAB1OLB2 TAB1IOC3_bit.no5 +#define TAB1OEB3 TAB1IOC3_bit.no6 +#define TAB1OLB3 TAB1IOC3_bit.no7 + +#define TAB1AT4 TAB1OPT3_bit.no0 +#define TAB1AT5 TAB1OPT3_bit.no1 +#define TAB1AT6 TAB1OPT3_bit.no2 +#define TAB1AT7 TAB1OPT3_bit.no3 +#define TAB1ATM6 TAB1OPT3_bit.no4 +#define TAB1ATM7 TAB1OPT3_bit.no5 + +#define HZA2DCF0 HZA2CTL0_bit.no0 +#define HZA2DCC0 HZA2CTL0_bit.no2 +#define HZA2DCT0 HZA2CTL0_bit.no3 +#define HZA2DCM0 HZA2CTL0_bit.no6 +#define HZA2DCE0 HZA2CTL0_bit.no7 + +#define HZA2DCF1 HZA2CTL1_bit.no0 +#define HZA2DCC1 HZA2CTL1_bit.no2 +#define HZA2DCT1 HZA2CTL1_bit.no3 +#define HZA2DCM1 HZA2CTL1_bit.no6 +#define HZA2DCE1 HZA2CTL1_bit.no7 + +#define HZA3DCF0 HZA3CTL0_bit.no0 +#define HZA3DCC0 HZA3CTL0_bit.no2 +#define HZA3DCT0 HZA3CTL0_bit.no3 +#define HZA3DCM0 HZA3CTL0_bit.no6 +#define HZA3DCE0 HZA3CTL0_bit.no7 + +#define HZA3DCF1 HZA3CTL1_bit.no0 +#define HZA3DCC1 HZA3CTL1_bit.no2 +#define HZA3DCT1 HZA3CTL1_bit.no3 +#define HZA3DCM1 HZA3CTL1_bit.no6 +#define HZA3DCE1 HZA3CTL1_bit.no7 + +#define TAA0CE TAA0CTL0_bit.no7 + +#define TAA0OVF TAA0OPT0_bit.no0 + +#define TAA1CE TAA1CTL0_bit.no7 + +#define TAA1OVF TAA1OPT0_bit.no0 + +#define TAA2CE TAA2CTL0_bit.no7 + +#define TAA2OE0 TAA2IOC0_bit.no0 +#define TAA2OE1 TAA2IOC0_bit.no2 + +#define TAA2OVF TAA2OPT0_bit.no0 + +#define PRERR SYS_bit.no0 + +#define DF0 DTFR0_bit.no7 + +#define DF1 DTFR1_bit.no7 + +#define DF2 DTFR2_bit.no7 + +#define DF3 DTFR3_bit.no7 + +#define PSM0 PSMR_bit.no0 + +#define PLLON PLLCTL_bit.no0 +#define SELPLL PLLCTL_bit.no1 + +#define LVIF LVIM_bit.no0 +#define LVIMD LVIM_bit.no1 +#define LVION LVIM_bit.no7 + +#define UA0DIR UA0CTL0_bit.no4 +#define UA0RXE UA0CTL0_bit.no5 +#define UA0TXE UA0CTL0_bit.no6 +#define UA0PWR UA0CTL0_bit.no7 + +#define UA0OVE UA0STR_bit.no0 +#define UA0FE UA0STR_bit.no1 +#define UA0PE UA0STR_bit.no2 +#define UA0TSF UA0STR_bit.no7 + +#define UA1DIR UA1CTL0_bit.no4 +#define UA1RXE UA1CTL0_bit.no5 +#define UA1TXE UA1CTL0_bit.no6 +#define UA1PWR UA1CTL0_bit.no7 + +#define UA1OVE UA1STR_bit.no0 +#define UA1FE UA1STR_bit.no1 +#define UA1PE UA1STR_bit.no2 +#define UA1TSF UA1STR_bit.no7 + +#define UA2DIR UA2CTL0_bit.no4 +#define UA2RXE UA2CTL0_bit.no5 +#define UA2TXE UA2CTL0_bit.no6 +#define UA2PWR UA2CTL0_bit.no7 + +#define UA2OVE UA2STR_bit.no0 +#define UA2FE UA2STR_bit.no1 +#define UA2PE UA2STR_bit.no2 +#define UA2TSF UA2STR_bit.no7 + +#define UBDIR UBCTL0_bit.no4 +#define UBRXE UBCTL0_bit.no5 +#define UBTXE UBCTL0_bit.no6 +#define UBPWR UBCTL0_bit.no7 + +#define UBOVE UBSTR_bit.no0 +#define UBFE UBSTR_bit.no1 +#define UBPE UBSTR_bit.no2 +#define UBTSF UBSTR_bit.no7 + +#define TAA3CE TAA3CTL0_bit.no7 + +#define TAA3OE0 TAA3IOC0_bit.no0 +#define TAA3OE1 TAA3IOC0_bit.no2 + +#define TAA3OVF TAA3OPT0_bit.no0 + +#define TAA4CE TAA4CTL0_bit.no7 + +#define TAA4OE0 TAA4IOC0_bit.no0 +#define TAA4OE1 TAA4IOC0_bit.no2 + +#define TAA4OVF TAA4OPT0_bit.no0 + +#define AD2CE AD2M0_bit.no7 + +#define INTF00 INTF0_bit.no0 +#define INTF01 INTF0_bit.no1 +#define INTF02 INTF0_bit.no2 +#define INTF03 INTF0_bit.no3 +#define INTF04 INTF0_bit.no4 +#define INTF05 INTF0_bit.no5 +#define INTF06 INTF0_bit.no6 +#define INTF07 INTF0_bit.no7 + +#define INTF08 INTF1_bit.no0 +#define INTF09 INTF1_bit.no1 +#define INTF10 INTF1_bit.no2 +#define INTF11 INTF1_bit.no3 +#define INTF12 INTF1_bit.no4 +#define INTF13 INTF1_bit.no5 +#define INTF17 INTF1_bit.no6 +#define INTF18 INTF1_bit.no7 + +#define INTF14 INTF2_bit.no0 +#define INTF15 INTF2_bit.no1 +#define INTF16 INTF2_bit.no2 + +#define INTR00 INTR0_bit.no0 +#define INTR01 INTR0_bit.no1 +#define INTR02 INTR0_bit.no2 +#define INTR03 INTR0_bit.no3 +#define INTR04 INTR0_bit.no4 +#define INTR05 INTR0_bit.no5 +#define INTR06 INTR0_bit.no6 +#define INTR07 INTR0_bit.no7 + +#define INTR08 INTR1_bit.no0 +#define INTR09 INTR1_bit.no1 +#define INTR10 INTR1_bit.no2 +#define INTR11 INTR1_bit.no3 +#define INTR12 INTR1_bit.no4 +#define INTR13 INTR1_bit.no5 +#define INTR17 INTR1_bit.no6 +#define INTR18 INTR1_bit.no7 + +#define INTR14 INTR2_bit.no0 +#define INTR15 INTR2_bit.no1 +#define INTR16 INTR2_bit.no2 + +#define CB0SCE CB0CTL0_bit.no0 +#define CB0DIR CB0CTL0_bit.no4 +#define CB0RXE CB0CTL0_bit.no5 +#define CB0TXE CB0CTL0_bit.no6 +#define CB0PWR CB0CTL0_bit.no7 + +#define CB0OVE CB0STR_bit.no0 +#define CB0TSF CB0STR_bit.no7 + +#define CB1SCE CB1CTL0_bit.no0 +#define CB1DIR CB1CTL0_bit.no4 +#define CB1RXE CB1CTL0_bit.no5 +#define CB1TXE CB1CTL0_bit.no6 +#define CB1PWR CB1CTL0_bit.no7 + +#define CB1OVE CB1STR_bit.no0 +#define CB1TSF CB1STR_bit.no7 + +#define CB2SCE CB2CTL0_bit.no0 +#define CB2DIR CB2CTL0_bit.no4 +#define CB2RXE CB2CTL0_bit.no5 +#define CB2TXE CB2CTL0_bit.no6 +#define CB2PWR CB2CTL0_bit.no7 + +#define CB2OVE CB2STR_bit.no0 +#define CB2TSF CB2STR_bit.no7 + +#define SPT0 IICC0_bit.no0 +#define STT0 IICC0_bit.no1 +#define ACKE0 IICC0_bit.no2 +#define WTIM0 IICC0_bit.no3 +#define SPIE0 IICC0_bit.no4 +#define WREL0 IICC0_bit.no5 +#define LREL0 IICC0_bit.no6 +#define IICE0 IICC0_bit.no7 + +#define DAD0 IICCL0_bit.no4 +#define CLD0 IICCL0_bit.no5 + +#define CLX0 IICX0_bit.no0 + +#define SPD0 IICS0_bit.no0 +#define STD0 IICS0_bit.no1 +#define ACKD0 IICS0_bit.no2 +#define TRC0 IICS0_bit.no3 +#define COI0 IICS0_bit.no4 +#define EXC0 IICS0_bit.no5 +#define ALD0 IICS0_bit.no6 +#define MSTS0 IICS0_bit.no7 + +#define IICRSV0 IICF0_bit.no0 +#define STCEN0 IICF0_bit.no1 +#define IICBSY0 IICF0_bit.no6 +#define STCF0 IICF0_bit.no7 + +#endif /* __IAR_SYSTEMS_ICC__ */ + +/*********************************************** + * Interrupt/Exeption table declarations + ***********************************************/ + +#define RESET_vector (0x0000) +#define INTWDT_vector (0x0010) +#define DBG0_vector (0x0060) +#define ILGOP_vector (0x0060) +#define SECURITY_ID_vector (0x0070) +#define INTLVIL_vector (0x0080) +#define INTLVIH_vector (0x0090) +#define INTP00_vector (0x00A0) +#define INTP01_vector (0x00B0) +#define INTP02_vector (0x00C0) +#define INTP03_vector (0x00D0) +#define INTP04_vector (0x00E0) +#define INTP05_vector (0x00F0) +#define INTP06_vector (0x0100) +#define INTP07_vector (0x0110) +#define INTP08_vector (0x0120) +#define INTP09_vector (0x0130) +#define INTP10_vector (0x0140) +#define INTP11_vector (0x0150) +#define INTP12_vector (0x0160) +#define INTP13_vector (0x0170) +#define INTP14_vector (0x0180) +#define INTP15_vector (0x0190) +#define INTP16_vector (0x01A0) +#define INTP17_vector (0x01B0) +#define INTP18_vector (0x01C0) +#define INTCMP0L_vector (0x01D0) +#define INTCMP0F_vector (0x01E0) +#define INTCMP1L_vector (0x01F0) +#define INTCMP1F_vector (0x0200) +#define INTTB0OV_vector (0x0210) +#define INTTB0CC0_vector (0x0220) +#define INTTB0CC1_vector (0x0230) +#define INTTB0CC2_vector (0x0240) +#define INTTB0CC3_vector (0x0250) +#define INTTB1OV_vector (0x0260) +#define INTTB1CC0_vector (0x0270) +#define INTTB1CC1_vector (0x0280) +#define INTTB1CC2_vector (0x0290) +#define INTTB1CC3_vector (0x02A0) +#define INTTTIOV0_vector (0x02B0) +#define INTTTEQC00_vector (0x02C0) +#define INTTTEQC01_vector (0x02D0) +#define INTTIEC0_vector (0x02E0) +#define INTTTIOV1_vector (0x02F0) +#define INTTTEQC10_vector (0x0300) +#define INTTTEQC11_vector (0x0310) +#define INTTIEC1_vector (0x0320) +#define INTTA0OV_vector (0x0330) +#define INTTA0CC0_vector (0x0340) +#define INTTA0CC1_vector (0x0350) +#define INTTA1OV_vector (0x0360) +#define INTTA1CC0_vector (0x0370) +#define INTTA1CC1_vector (0x0380) +#define INTTA2OV_vector (0x0390) +#define INTTA2CC0_vector (0x03A0) +#define INTTA2CC1_vector (0x03B0) +#define INTTA3OV_vector (0x03C0) +#define INTTA3CC0_vector (0x03D0) +#define INTTA3CC1_vector (0x03E0) +#define INTTA4OV_vector (0x03F0) +#define INTTA4CC0_vector (0x0400) +#define INTTA4CC1_vector (0x0410) +#define INTDMA0_vector (0x0420) +#define INTDMA1_vector (0x0430) +#define INTDMA2_vector (0x0440) +#define INTDMA3_vector (0x0450) +#define INTUBTIRE_vector (0x0460) +#define INTUBTIR_vector (0x0470) +#define INTUBTIT_vector (0x0480) +#define INTUBTIF_vector (0x0490) +#define INTUBTITO_vector (0x04A0) +#define INTUA0RE_vector (0x04B0) +#define INTUA0R_vector (0x04C0) +#define INTUA0T_vector (0x04D0) +#define INTCB0RE_vector (0x04E0) +#define INTCB0R_vector (0x04F0) +#define INTCB0T_vector (0x0500) +#define INTUA1RE_vector (0x0510) +#define INTUA1R_vector (0x0520) +#define INTUA1T_vector (0x0530) +#define INTCB1RE_vector (0x0540) +#define INTCB1R_vector (0x0550) +#define INTCB1T_vector (0x0560) +#define INTUA2RE_vector (0x0570) +#define INTUA2R_vector (0x0580) +#define INTUA2T_vector (0x0590) +#define INTCB2RE_vector (0x05A0) +#define INTCB2R_vector (0x05B0) +#define INTCB2T_vector (0x05C0) +#define INTIIC_vector (0x05D0) +#define INTAD0_vector (0x05E0) +#define INTAD1_vector (0x05F0) +#define INTAD2_vector (0x0600) +#define INTTM0EQ0_vector (0x0610) +#define INTTM1EQ0_vector (0x0620) +#define INTTM2EQ0_vector (0x0630) +#define INTTM3EQ0_vector (0x0640) +#define INTADT0_vector (0x0650) +#define INTADT1_vector (0x0660) +#define INTWARE_vector (0x0790) +#define INTWAR_vector (0x07A0) +#define INTWAT_vector (0x07B0) +#define INTECCER_vector (0x07C0) + +/*********************************************** + * Trap vectors + ***********************************************/ + +#define TRAP00_vector (0x00) +#define TRAP01_vector (0x01) +#define TRAP02_vector (0x02) +#define TRAP03_vector (0x03) +#define TRAP04_vector (0x04) +#define TRAP05_vector (0x05) +#define TRAP06_vector (0x06) +#define TRAP07_vector (0x07) +#define TRAP08_vector (0x08) +#define TRAP09_vector (0x09) +#define TRAP0A_vector (0x0A) +#define TRAP0B_vector (0x0B) +#define TRAP0C_vector (0x0C) +#define TRAP0D_vector (0x0D) +#define TRAP0E_vector (0x0E) +#define TRAP0F_vector (0x0F) +#define TRAP10_vector (0x10) +#define TRAP11_vector (0x11) +#define TRAP12_vector (0x12) +#define TRAP13_vector (0x13) +#define TRAP14_vector (0x14) +#define TRAP15_vector (0x15) +#define TRAP16_vector (0x16) +#define TRAP17_vector (0x17) +#define TRAP18_vector (0x18) +#define TRAP19_vector (0x19) +#define TRAP1A_vector (0x1A) +#define TRAP1B_vector (0x1B) +#define TRAP1C_vector (0x1C) +#define TRAP1D_vector (0x1D) +#define TRAP1E_vector (0x1E) +#define TRAP1F_vector (0x1F) + +/*********************************************** + * Callt vectors + ***********************************************/ + +#define CALLT00_vector (0x00) +#define CALLT01_vector (0x01) +#define CALLT02_vector (0x02) +#define CALLT03_vector (0x03) +#define CALLT04_vector (0x04) +#define CALLT05_vector (0x05) +#define CALLT06_vector (0x06) +#define CALLT07_vector (0x07) +#define CALLT08_vector (0x08) +#define CALLT09_vector (0x09) +#define CALLT0A_vector (0x0A) +#define CALLT0B_vector (0x0B) +#define CALLT0C_vector (0x0C) +#define CALLT0D_vector (0x0D) +#define CALLT0E_vector (0x0E) +#define CALLT0F_vector (0x0F) +#define CALLT10_vector (0x10) +#define CALLT11_vector (0x11) +#define CALLT12_vector (0x12) +#define CALLT13_vector (0x13) +#define CALLT14_vector (0x14) +#define CALLT15_vector (0x15) +#define CALLT16_vector (0x16) +#define CALLT17_vector (0x17) +#define CALLT18_vector (0x18) +#define CALLT19_vector (0x19) +#define CALLT1A_vector (0x1A) +#define CALLT1B_vector (0x1B) +#define CALLT1C_vector (0x1C) +#define CALLT1D_vector (0x1D) +#define CALLT1E_vector (0x1E) +#define CALLT1F_vector (0x1F) +#define CALLT20_vector (0x20) +#define CALLT21_vector (0x21) +#define CALLT22_vector (0x22) +#define CALLT23_vector (0x23) +#define CALLT24_vector (0x24) +#define CALLT25_vector (0x25) +#define CALLT26_vector (0x26) +#define CALLT27_vector (0x27) +#define CALLT28_vector (0x28) +#define CALLT29_vector (0x29) +#define CALLT2A_vector (0x2A) +#define CALLT2B_vector (0x2B) +#define CALLT2C_vector (0x2C) +#define CALLT2D_vector (0x2D) +#define CALLT2E_vector (0x2E) +#define CALLT2F_vector (0x2F) +#define CALLT30_vector (0x30) +#define CALLT31_vector (0x31) +#define CALLT32_vector (0x32) +#define CALLT33_vector (0x33) +#define CALLT34_vector (0x34) +#define CALLT35_vector (0x35) +#define CALLT36_vector (0x36) +#define CALLT37_vector (0x37) +#define CALLT38_vector (0x38) +#define CALLT39_vector (0x39) +#define CALLT3A_vector (0x3A) +#define CALLT3B_vector (0x3B) +#define CALLT3C_vector (0x3C) +#define CALLT3D_vector (0x3D) +#define CALLT3E_vector (0x3E) +#define CALLT3F_vector (0x3F) + +#pragma language=default + +#endif /* __IO70F3454_H__ */ diff --git a/bsp/upd70f3454/lnk70f3454.xcl b/bsp/upd70f3454/lnk70f3454.xcl new file mode 100644 index 0000000000..82f9cd79d7 --- /dev/null +++ b/bsp/upd70f3454/lnk70f3454.xcl @@ -0,0 +1,157 @@ +//------------------------------------------------------------------------- +// XLINK command file template for V850E microcontroller uPD70F3454. +// +// This file can be used to link object files from the V850E +// Assembler, AV850, and the C/C++ compiler ICCV850. +// +// This file is generated from the device file: +// DF3454.800 +// Copyright (C) NEC Corporation 2007 +// Format version 2.20, File version 1.00 +//------------------------------------------------------------------------- + +//------------------------------------------------------------------------- +// The following segments are defined in this template link file: +// +// INTVEC -- Interrupt vectors. +// TRAPVEC -- Trap vector. +// CLTVEC -- Calltable vectors. +// CSTART -- The C/C++ startup code. +// RCODE -- Code used by C/C++ run-time library. +// ICODE -- Code used by interrupt functions. +// CLTCODE -- Code of calltable functions. +// CODE -- Program code. +// DIFUNCT -- Dynamic initialization vector used by C++ +// CSTACK -- The stack used by C/C++ programs. +// HEAP -- The heap used for malloc and free +// SADDR7_x -- Variables used by __saddr (128 byte offset). +// SADDR8_x -- Variables used by __saddr (256 byte offset). +// NEAR_x -- Variables used by __near (must be +- 32KB from address 0). +// BREL_x -- Variables used by __brel. +// HUGE_x -- Variables used by __huge. +// +// Where _x could be one of: +// +// _BASE -- An empty placeholder segment that should be placed +// in front of the other segments (SADDR and BREL). +// _CBASE -- An empty placeholder segment that should be placed +// in front of the other segments (BREL_C). +// _Z -- Initialized data (initvalue = 0 or without init value). +// _I -- Initialized data (initvalue != 0). +// _ID -- The inial values of _I. +// _N -- Uninitialized data, used by __no_init. +// _C -- Constants. +// +// NOTE: Be sure to use end values for the defined addresses. +//------------------------------------------------------------------------- + +//------------------------------------------------------------------------- +// Define CPU +//------------------------------------------------------------------------- +-cv850 + +//------------------------------------------------------------------------- +// Size of the stack. +// Remove comment and modify number if used from command line. +//------------------------------------------------------------------------- +//-D_CSTACK_SIZE=400 + +//------------------------------------------------------------------------- +// Size of the heap. +// Remove comment and modify number if used from command line. +//------------------------------------------------------------------------- +//-D_HEAP_SIZE=400 + +//------------------------------------------------------------------------- +// Define the format functions used by printf/scanf. +// Default is full formatting. +// Remove appropriate comment(s) to get reduced formatting +// if used from command line. +//------------------------------------------------------------------------- +//-e_PrintfTiny=_Printf +//-e_PrintfSmall=_Printf +//-e_PrintfLarge=_Printf + +//-e_ScanfSmall=_Scanf +//-e_ScanfLarge=_Scanf + +//------------------------------------------------------------------------- +// Define if row buffering should be used by terminal output. +// Default is no buffering. +// Remove comment to get buffered terminal output if used from command line. +//------------------------------------------------------------------------- +//-e__write_buffered=__write + +/////////////////////////////////////////////////////////////////////////// +// Allocate the read only segments that are mapped to ROM. +/////////////////////////////////////////////////////////////////////////// + +-Z(CODE)INTVEC=00000000-000007CF +-Z(CONST)SECUID=00000070-00000079 + +//------------------------------------------------------------------------- +// BREL_CBASE is an empty placeholer segment, it should be placed in +// front of the BREL_C segments holding constant data. +//------------------------------------------------------------------------- +-Z(CONST)NEAR_C=000007D0-00007FFF +-Z(CONST)BREL_CBASE,BREL_C=000007D0-0000FFFF +-Z(CONST)HUGE_C=000007D0-0003FFFB +-Z(CODE)CSTART,RCODE,ICODE,TRAPVEC,DIFUNCT=000007D0-0003FFFB +-Z(CONST)SADDR7_ID,SADDR8_ID,NEAR_ID,BREL_ID,HUGE_ID=000007D0-0003FFFB +-Z(CONST)CLTVEC=000007D0-0003FFFB + +-Z(CODE)CLTCODE,CODE=000007D0-0003FFFB + +//------------------------------------------------------------------------- +// The CHECKSUM segment must be defined when ROM checksum should +// be generated. +//------------------------------------------------------------------------- +-Z(CONST)CHECKSUM=0003FFFC-0003FFFF + +/////////////////////////////////////////////////////////////////////////// +// Allocate the read/write segments that are mapped to RAM. +/////////////////////////////////////////////////////////////////////////// + +//------------------------------------------------------------------------- +// Short loads relative from EP with 7 and 8 bit offset. +// +// SADDR_BASE is an empty segment that mark the beginning of the saddr +// data segments. +//------------------------------------------------------------------------- +-Z(DATA)SADDR_BASE=FFFFC000 +-Z(DATA)SADDR7_I,SADDR7_Z,SADDR7_N=FFFFC000-FFFFC07F +-Z(DATA)SADDR8_I,SADDR8_Z,SADDR8_N=FFFFC000-FFFFC0FF + +//------------------------------------------------------------------------- +// 16-bit access from GP. +// BREL_BASE is an empty placeholer segment, it should be placed in +// front of the DATA (i.e. RAM) BREL segments. +//------------------------------------------------------------------------- +-Z(DATA)BREL_BASE,BREL_I,BREL_Z,BREL_N=FFFFC000-FFFFEFFF + +//------------------------------------------------------------------------- +// Global and 32-bit offset from GP. +// The rest of the external memory (all external memory not used +// by BREL segment variables) is addressed with HUGE memory model. +//------------------------------------------------------------------------- +-Z(DATA)HUGE_I,HUGE_Z,HUGE_N=FFFFBFFC-FFFFBFFC // No memory availabale + +//------------------------------------------------------------------------- +// Data relative from zero with 16 bit offset. +// This segment is for TINY data model. All internal memory, SFR, +// and CONST variables in area 0000-7FFF may be accessed. +//------------------------------------------------------------------------- +-Z(DATA)NEAR_Z,NEAR_I,NEAR_N=FFFFC000-FFFFEFFF + +//------------------------------------------------------------------------- +// The stack and the heap. +//------------------------------------------------------------------------- +-Z(DATA)CSTACK+_CSTACK_SIZE,HEAP+_HEAP_SIZE=FFFFC000-FFFFEFFF + +// Set up near RT_HEAP +//fify 20100505 HEAP for RTT +-Z(DATA)RT_HEAP+400=FFFFC000-FFFFEFFF + +//------------------------------------------------------------------------- +// End of File +//------------------------------------------------------------------------- diff --git a/bsp/upd70f3454/rtconfig.h b/bsp/upd70f3454/rtconfig.h new file mode 100644 index 0000000000..01fded1089 --- /dev/null +++ b/bsp/upd70f3454/rtconfig.h @@ -0,0 +1,151 @@ +/* RT-Thread config file */ +#ifndef __RTTHREAD_CFG_H__ +#define __RTTHREAD_CFG_H__ + +/* RT_NAME_MAX*/ +#define RT_NAME_MAX 8 + +/* RT_ALIGN_SIZE*/ +#define RT_ALIGN_SIZE 4 + +/* PRIORITY_MAX */ +#define RT_THREAD_PRIORITY_MAX 32 + +/* Tick per Second */ +#define RT_TICK_PER_SECOND 100 + +/* SECTION: RT_DEBUG */ +/* Thread Debug */ +#define RT_DEBUG +///#define SCHEDULER_DEBUG + +#define RT_USING_OVERFLOW_CHECK + +/* Using Hook */ +///#define RT_USING_HOOK + +/* Using Software Timer */ +/* #define RT_USING_TIMER_SOFT */ +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_TIMER_TICK_PER_SECOND 10 + +/* SECTION: IPC */ +/* Using Semaphore */ +#define RT_USING_SEMAPHORE + +/* Using Mutex */ +#define RT_USING_MUTEX + +/* Using Event */ +#define RT_USING_EVENT + +/* Using MailBox */ +#define RT_USING_MAILBOX + +/* Using Message Queue */ +#define RT_USING_MESSAGEQUEUE + +/* SECTION: Memory Management */ +/* Using Memory Pool Management*/ +#define RT_USING_MEMPOOL + +/* Using Dynamic Heap Management */ +#define RT_USING_HEAP + +/* Using Small MM */ +#define RT_USING_SMALL_MEM + +/* SECTION: Device System */ +/* Using Device System */ +#define RT_USING_DEVICE +/* RT_USING_UART */ +#define RT_USING_UART0 +#define RT_UART_RX_BUFFER_SIZE 64 + +/* SECTION: Console options */ +/* the buffer size of console */ +#define RT_CONSOLEBUF_SIZE 128 + +/* SECTION: finsh, a C-Express shell */ +/* Using FinSH as Shell*/ +#define RT_USING_FINSH +/* Using symbol table */ +///#define FINSH_USING_SYMTAB +///#define FINSH_USING_DESCRIPTION + +/* SECTION: device filesystem support */ +/* #define RT_USING_DFS */ +///#define RT_USING_DFS_ELMFAT + +/* the max number of mounted filesystem */ +///#define DFS_FILESYSTEMS_MAX 2 +/* the max number of opened files */ +///#define DFS_FD_MAX 4 +/* the max number of cached sector */ +///#define DFS_CACHE_MAX_NUM 4 + +/* SECTION: lwip, a lighwight TCP/IP protocol stack */ +//#define RT_USING_LWIP + +/* Enable ICMP protocol*/ +///#define RT_LWIP_ICMP +/* Enable UDP protocol*/ +///#define RT_LWIP_UDP +/* Enable TCP protocol*/ +///#define RT_LWIP_TCP +/* Enable DNS */ +///#define RT_LWIP_DNS + +/* the number of simulatenously active TCP connections*/ +///#define RT_LWIP_TCP_PCB_NUM 5 + +/* ip address of target*/ +///#define RT_LWIP_IPADDR0 192 +///#define RT_LWIP_IPADDR1 168 +///#define RT_LWIP_IPADDR2 1 +///#define RT_LWIP_IPADDR3 30 + +/* gateway address of target*/ +#define RT_LWIP_GWADDR0 192 +#define RT_LWIP_GWADDR1 168 +#define RT_LWIP_GWADDR2 1 +#define RT_LWIP_GWADDR3 1 + +/* mask address of target*/ +#define RT_LWIP_MSKADDR0 255 +#define RT_LWIP_MSKADDR1 255 +#define RT_LWIP_MSKADDR2 255 +#define RT_LWIP_MSKADDR3 0 + +/* tcp thread options */ +#define RT_LWIP_TCPTHREAD_PRIORITY 12 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 4 +#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 + +/* ethernet if thread options */ +#define RT_LWIP_ETHTHREAD_PRIORITY 15 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 4 +#define RT_LWIP_ETHTHREAD_STACKSIZE 512 + +/* SECTION: RT-Thread/GUI */ +/* #define RT_USING_RTGUI */ + +/* name length of RTGUI object */ +#define RTGUI_NAME_MAX 12 +/* support 16 weight font */ +#define RTGUI_USING_FONT16 +/* support Chinese font */ +#define RTGUI_USING_FONTHZ +/* use DFS as file interface */ +#define RTGUI_USING_DFS_FILERW +/* use font file as Chinese font */ +#define RTGUI_USING_HZ_FILE +/* use small size in RTGUI */ +#define RTGUI_USING_SMALL_SIZE +/* use mouse cursor */ +/* #define RTGUI_USING_MOUSE_CURSOR */ +/* default font size in RTGUI */ +#define RTGUI_DEFAULT_FONT_SIZE 16 + +#endif diff --git a/bsp/upd70f3454/settings/upd70f3454.cspy.bat b/bsp/upd70f3454/settings/upd70f3454.cspy.bat new file mode 100644 index 0000000000..d3e9c63e46 --- /dev/null +++ b/bsp/upd70f3454/settings/upd70f3454.cspy.bat @@ -0,0 +1,33 @@ +@REM This bat file has been generated by the IAR Embeddded Workbench +@REM C-SPY interactive debugger,as an aid to preparing a command +@REM line for running the cspybat command line utility with the +@REM appropriate settings. +@REM +@REM After making some adjustments to this file, you can launch cspybat +@REM by typing the name of this file followed by the name of the debug +@REM file (usually an ubrof file). Note that this file is generated +@REM every time a new debug session is initialized, so you may want to +@REM move or rename the file before making changes. +@REM +@REM Note: some command line arguments cannot be properly generated +@REM by this process. Specifically, the plugin which is responsible +@REM for the Terminal I/O window (and other C runtime functionality) +@REM comes in a special version for cspybat, and the name of that +@REM plugin dll is not known when generating this file. It resides in +@REM the $TOOLKIT_DIR$\bin folder and is usually called XXXbat.dll or +@REM XXXlibsupportbat.dll, where XXX is the name of the corresponding +@REM tool chain. Replace the '' parameter +@REM below with the appropriate file name. Other plugins loaded by +@REM C-SPY are usually not needed by, or will not work in, cspybat +@REM but they are listed at the end of this file for reference. + + +"C:\Program Files\IAR Systems\Embedded Workbench 5.4 Evaluation\common\bin\cspybat" "C:\Program Files\IAR Systems\Embedded Workbench 5.4 Evaluation\v850\bin\v850proc.dll" "C:\Program Files\IAR Systems\Embedded Workbench 5.4 Evaluation\v850\bin\v850minicube2.dll" %1 --plugin "C:\Program Files\IAR Systems\Embedded Workbench 5.4 Evaluation\v850\bin\" --backend -B "-v10" "-p" "C:\Program Files\IAR Systems\Embedded Workbench 5.4 Evaluation\v850\CONFIG\DDF\io70f3454.ddf" "-d" "minicube2" + + +@REM Loaded plugins: +@REM v850LibSupport.dll +@REM C:\Program Files\IAR Systems\Embedded Workbench 5.4 Evaluation\common\plugins\CodeCoverage\CodeCoverage.dll +@REM C:\Program Files\IAR Systems\Embedded Workbench 5.4 Evaluation\common\plugins\Profiling\Profiling.dll +@REM C:\Program Files\IAR Systems\Embedded Workbench 5.4 Evaluation\common\plugins\stack\stack.dll +@REM C:\Program Files\IAR Systems\Embedded Workbench 5.4 Evaluation\common\plugins\SymList\SymList.dll diff --git a/bsp/upd70f3454/settings/upd70f3454.dbgdt b/bsp/upd70f3454/settings/upd70f3454.dbgdt new file mode 100644 index 0000000000..e5162bc333 --- /dev/null +++ b/bsp/upd70f3454/settings/upd70f3454.dbgdt @@ -0,0 +1,84 @@ + + + + + + + + + 201381 + + 20 + 1035 + 276 + 69 + + + + + + + + 191272727 + + + 1 + 0 + 0 + + 4 + 254 + 143 + + + + 200 + + + + + + + TabID-7492-12225 + Debug Log + Debug-Log + + + + TabID-6969-12235 + Build + Build + + + + + 0 + + + TabID-18240-12229 + Workspace + Workspace + + + upd70f3454upd70f3454/libcpu + + + + 0 + + + + + + TextEditorE:\RTT\RTTV850\rt-thread\bsp\upd70f3454\applilet3_src\CG_systeminit.c06923422352TextEditorE:\RTT\RTTV850\rt-thread\bsp\upd70f3454\applilet3_src\CG_system.c05923292329TextEditorE:\RTT\RTTV850\rt-thread\bsp\upd70f3454\io70f3454.h05172739627456TextEditorE:\RTT\RTTV850\rt-thread\bsp\upd70f3454\cstartup.s850973377337730100000010000001 + + + + + + + iaridepm.enu1debuggergui.enu1v850minicube21-2-2472265-2-22749334319092361419315185417579462-2-22531442-2-21444255100277831173619092361419315 + + + + diff --git a/bsp/upd70f3454/settings/upd70f3454.dni b/bsp/upd70f3454/settings/upd70f3454.dni new file mode 100644 index 0000000000..0bd8f532ee --- /dev/null +++ b/bsp/upd70f3454/settings/upd70f3454.dni @@ -0,0 +1,124 @@ +[Interrupts] +Enabled=1 +[MemoryMap] +Enabled=0 +Base=0 +UseAuto=0 +TypeViolation=1 +UnspecRange=1 +ActionState=1 +[DataAlign] +Action=1 +Notification=1 +[DebugChecksum] +Checksum=576357238 +[DisAssemblyWindow] +NumStates=_ 1 +State 1=_ 1 +[InstructionProfiling] +Enabled=_ 0 +[CodeCoverage] +Enabled=_ 0 +[Profiling] +Enabled=0 +[StackPlugin] +Enabled=1 +OverflowWarningsEnabled=1 +WarningThreshold=90 +SpWarningsEnabled=1 +WarnHow=0 +UseTrigger=1 +TriggerName=main +LimitSize=0 +ByteLimit=50 +[MINICUBE2] +Map0=0,0,262143,256,3 +Map1=1,268419072,268431359,12,3 +MapEntries=2 +HWsettings=1,33024,8155,0,160,0,0,1 +HWsettings2=0 +HWsettings3=124,1 +NWsettings=0,8000,0,0,FFFFFFFFFFFFFFFFFFFF +NWsettings2=1 +AutoEventEntries=0 +EventEntries=0 +SeqName0= +SeqData0=0,0,0 +SeqEnable10=0,0,0,0,0,0,0,0,0,0 +SeqEnable20=0,0,0,0,0,0,0,0,0,0 +SeqEnable30=0,0,0,0,0,0,0,0,0,0 +SeqEnable40=0,0,0,0,0,0,0,0,0,0 +SeqDisable0=0,0,0,0,0,0,0,0,0,0 +SeqName1= +SeqData1=0,0,0 +SeqEnable11=0,0,0,0,0,0,0,0,0,0 +SeqEnable21=0,0,0,0,0,0,0,0,0,0 +SeqEnable31=0,0,0,0,0,0,0,0,0,0 +SeqEnable41=0,0,0,0,0,0,0,0,0,0 +SeqDisable1=0,0,0,0,0,0,0,0,0,0 +SeqName2= +SeqData2=0,0,0 +SeqEnable12=0,0,0,0,0,0,0,0,0,0 +SeqEnable22=0,0,0,0,0,0,0,0,0,0 +SeqEnable32=0,0,0,0,0,0,0,0,0,0 +SeqEnable42=0,0,0,0,0,0,0,0,0,0 +SeqDisable2=0,0,0,0,0,0,0,0,0,0 +TraceSettings=-1,0,0,0,0,0,0,2298478591,12,11,0,1,1,1,8192,0,4 +DataFlashSettings=0,0,0,0,0,0,0,0,0,0,0,1,0,1,1 +SelfProgrammingSettings=0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 +TraceSave=1,v850trace.txt +TriggerOutSettings=0,0,0,0,0,0,0,0,0,0 +TimerSettings=0,0,0 +Tim2Name1= +Tim2Data1=0,0,0,0,0,0,0,0,0 +Tim2Start1=0,0,0,0,0,0,0,0,0,0 +Tim2Stop1=0,0,0,0,0,0,0,0,0,0 +Tim2Name2= +Tim2Data2=0,0,0,0,0,0,0,0,0 +Tim2Start2=0,0,0,0,0,0,0,0,0,0 +Tim2Stop2=0,0,0,0,0,0,0,0,0,0 +Tim2Name3= +Tim2Data3=0,0,0,0,0,0,0,0,0 +Tim2Start3=0,0,0,0,0,0,0,0,0,0 +Tim2Stop3=0,0,0,0,0,0,0,0,0,0 +Tim2Name4= +Tim2Data4=0,0,0,0,0,0,0,0,0 +Tim2Start4=0,0,0,0,0,0,0,0,0,0 +Tim2Stop4=0,0,0,0,0,0,0,0,0,0 +Tim2Name5= +Tim2Data5=0,0,0,0,0,0,0,0,0 +Tim2Start5=0,0,0,0,0,0,0,0,0,0 +Tim2Stop5=0,0,0,0,0,0,0,0,0,0 +Tim2Name6= +Tim2Data6=0,0,0,0,0,0,0,0,0 +Tim2Start6=0,0,0,0,0,0,0,0,0,0 +Tim2Stop6=0,0,0,0,0,0,0,0,0,0 +Tim2Name7= +Tim2Data7=0,0,0,0,0,0,0,0,0 +Tim2Start7=0,0,0,0,0,0,0,0,0,0 +Tim2Stop7=0,0,0,0,0,0,0,0,0,0 +Tim2Name8= +Tim2Data8=0,0,0,0,0,0,0,0,0 +Tim2Start8=0,0,0,0,0,0,0,0,0,0 +Tim2Stop8=0,0,0,0,0,0,0,0,0,0 +Tim2Name9= +Tim2Data9=0,0,0,0,0,0,0,0,0 +Tim2Start9=0,0,0,0,0,0,0,0,0,0 +Tim2Stop9=0,0,0,0,0,0,0,0,0,0 +CoverSettings=0,1048575,66060288,67108863,0,0,0 +CoverSettings2=0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 +Version=1 +LastDevFile=DF3454.800 +LastSetupFailed=0 +[Log file] +LoggingEnabled=_ 0 +LogFile=_ "" +Category=_ 0 +[TermIOLog] +LoggingEnabled=_ 0 +LogFile=_ "" +[Breakpoints] +Count=0 +[TraceHelper] +Enabled=0 +ShowSource=1 diff --git a/bsp/upd70f3454/settings/upd70f3454.wsdt b/bsp/upd70f3454/settings/upd70f3454.wsdt new file mode 100644 index 0000000000..5635ba6244 --- /dev/null +++ b/bsp/upd70f3454/settings/upd70f3454.wsdt @@ -0,0 +1,66 @@ + + + + + + upd70f3454/Debug + + + + + + + + + 198272727 + + + + + + + 2061516441 + 4967085018823 + + + + + + + TabID-10377-5417 + Workspace + Workspace + + + upd70f3454upd70f3454/Output + + + + 0 + + + TabID-17988-5479 + Build + Build + + + TabID-19670-27945Find in FilesFind-in-FilesTabID-31574-29955Debug LogDebug-Log + + 0 + + + + + + 0100000010000001 + + + + + + + iaridepm.enu1-2-2477272-2-21111694135697190278585575-2-22961442-2-214442981002778364303694135697 + + + + diff --git a/bsp/upd70f3454/startup.c b/bsp/upd70f3454/startup.c new file mode 100644 index 0000000000..d4f856c07a --- /dev/null +++ b/bsp/upd70f3454/startup.c @@ -0,0 +1,110 @@ +/* + * File : startup.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2009-01-05 Bernard first implementation + * 2010-06-29 lgnq for V850 + */ + +#include +#include + +#include "board.h" + +#include "CG_macrodriver.h" +#include "CG_system.h" +#include "CG_port.h" +#include "CG_timer.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "CG_userdefine.h" + +extern int rt_application_init(void); + +#ifdef RT_USING_FINSH +extern void finsh_system_init(void); +extern void finsh_set_device(const char* device); +#endif + +#ifdef RT_USING_HEAP +#ifdef __ICCV850__ +#pragma section="RT_HEAP" +#endif +#endif + +/** + * This function will startup RT-Thread RTOS. + */ +void rtthread_startup(void) +{ + /* init board */ + rt_hw_board_init(); + + /* show version */ + rt_show_version(); + + /* init tick */ + rt_system_tick_init(); + + /* init kernel object */ + rt_system_object_init(); + + /* init timer system */ + rt_system_timer_init(); + +#ifdef RT_USING_HEAP +#ifdef __ICCV850__ + rt_system_heap_init(__segment_begin("RT_HEAP"),__segment_end("RT_HEAP")); +#endif +#endif + + /* init scheduler system */ + rt_system_scheduler_init(); + +#ifdef RT_USING_DEVICE + /* init all device */ + rt_device_init_all(); +#endif + + /* init application */ + rt_application_init(); + +#ifdef RT_USING_FINSH + /* init finsh */ + finsh_system_init(); + finsh_set_device("uart0"); +#endif + + /* init timer thread */ + rt_system_timer_thread_init(); + + /* init idle thread */ + rt_thread_idle_init(); + + /* start scheduler */ + rt_system_scheduler_start(); + + /* never reach here */ + return ; +} + +int main(void) +{ + /* disable interrupt first */ + rt_hw_interrupt_disable(); + + /* init system setting */ + TAB0_Start(); + + /* startup RT-Thread RTOS */ + rtthread_startup(); + + return 0; +} diff --git a/bsp/upd70f3454/uart.c b/bsp/upd70f3454/uart.c new file mode 100644 index 0000000000..d0299438c2 --- /dev/null +++ b/bsp/upd70f3454/uart.c @@ -0,0 +1,247 @@ +/* + * File : board.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009 RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-03-08 Bernard The first version for LPC17xx + * 2010-06-29 lgnq Modified for V850 +*/ + +#include +#include +#include "io70f3454.h" +#include "uart.h" + +#if defined(RT_USING_UART0) && defined(RT_USING_DEVICE) + +struct rt_uart_v850 +{ + struct rt_device parent; + + /* buffer for reception */ + rt_uint8_t read_index, save_index; + rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; +}uart_device; + +void uarta1_receive_handler(void) +{ + rt_ubase_t level; + rt_uint8_t c; + + struct rt_uart_v850* uart = &uart_device; + +// while(ri_u0c1 == 0) +// ; + c = (char) UA1RX; + + /* Receive Data Available */ + uart->rx_buffer[uart->save_index] = c; + + level = rt_hw_interrupt_disable(); + uart->save_index ++; + if (uart->save_index >= RT_UART_RX_BUFFER_SIZE) + uart->save_index = 0; + rt_hw_interrupt_enable(level); + + /* invoke callback */ + if(uart->parent.rx_indicate != RT_NULL) + { + rt_size_t length; + if (uart->read_index > uart->save_index) + length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index; + else + length = uart->save_index - uart->read_index; + + uart->parent.rx_indicate(&uart->parent, length); + } +} + +static rt_err_t rt_uart_init (rt_device_t dev) +{ + UA1TXE = 0U; /* disable UARTA1 transmission operation */ + UA1RXE = 0U; /* disable UARTA1 reception operation */ + UA1PWR = 0U; /* disable UARTA1 operation */ + UA1TMK = 1U; /* disable INTUA1T interrupt */ + UA1TIF = 0U; /* clear INTUA1T interrupt flag */ + UA1RMK = 1U; /* disable INTUA1R interrupt */ + UA1RIF = 0U; /* clear INTUA1R interrupt flag */ + /* Set INTUA1T level low priority */ + UA1TIC |= 0x07U; + /* Set INTUA1R level low priority */ + UA1RIC |= 0x07U; + //BAUDRATE = 9600 + UA1CTL1 = _03_UARTA_BASECLK_FXX_16; + UA1CTL2 = _11_UARTA1_BASECLK_DIVISION; + UA1CTL0 = _10_UARTA_TRANSFDIR_LSB | _00_UARTA_PARITY_NONE | _02_UARTA_DATALENGTH_8BIT | _00_UARTA_STOPLENGTH_1BIT; + UA1OPT0 = _14_UARTA_UAnOPT0_INITIALVALUE | _00_UARTA_TRAN_DATALEVEL_NORMAL | _00_UARTA_REC_DATALEVEL_NORMAL; + UA1PWR = 1U; /* enable UARTA1 operation */ + /* Set TXDA1 pin */ + /* Set RXDA1 pin */ + PFC3_bit.no0 = 0; + PFCE3_bit.no0 = 0; + PMC3_bit.no0 = 1; + + PFC3_bit.no1 = 0; + PFCE3_bit.no1 = 0; + PMC3_bit.no1 = 1; + + return RT_EOK; +} + +static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag) +{ + RT_ASSERT(dev != RT_NULL); + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* Enable the UART Interrupt */ + UA1TIF = 0U; /* clear INTUA1T interrupt flag */ + UA1TMK = 1U; /* disable INTUA1T interrupt */ + UA1RIF = 0U; /* clear INTUA1R interrupt flag */ + UA1RMK = 0U; /* enable INTUA1R interrupt */ + UA1TXE = 1U; /* enable UARTA1 transmission operation */ + UA1RXE = 1U; /* enable UARTA1 reception operation */ + } + + return RT_EOK; +} + +static rt_err_t rt_uart_close(rt_device_t dev) +{ + RT_ASSERT(dev != RT_NULL); + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* Disable the UART Interrupt */ + UA1TXE = 0U; /* disable UARTA1 transmission operation */ + UA1RXE = 0U; /* disable UARTA1 reception operation */ + UA1TMK = 1U; /* disable INTUA1T interrupt */ + UA1TIF = 0U; /* clear INTUA1T interrupt flag */ + UA1RMK = 1U; /* disable INTUA1R interrupt */ + UA1RIF = 0U; /* clear INTUA1R interrupt flag */ + } + + return RT_EOK; +} + +static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) +{ + rt_uint8_t* ptr; + struct rt_uart_v850 *uart = (struct rt_uart_v850*)dev; + RT_ASSERT(uart != RT_NULL); + + /* point to buffer */ + ptr = (rt_uint8_t*) buffer; + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + while (size) + { + /* interrupt receive */ + rt_base_t level; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + if (uart->read_index != uart->save_index) + { + *ptr = uart->rx_buffer[uart->read_index]; + + uart->read_index ++; + if (uart->read_index >= RT_UART_RX_BUFFER_SIZE) + uart->read_index = 0; + } + else + { + /* no data in rx buffer */ + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + break; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + ptr ++; + size --; + } + + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + } + + return 0; +} + +static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) +{ + char *ptr; + ptr = (char*)buffer; + + if (dev->flag & RT_DEVICE_FLAG_STREAM) + { + /* stream mode */ + while (size) + { + if (*ptr == '\n') + { + while(UA1TSF == 1U) + ; + UA1TX = '\r'; + } + + /* THRE status, contain valid data */ + while(UA1TSF == 1U) + ; + UA1TX = *ptr; + + ptr ++; + size --; + } + } + else + { + while ( size != 0 ) + { + /* THRE status, contain valid data */ + while(UA1TSF == 1U) + ; + UA1TX = *ptr; + + ptr++; + size--; + } + } + + return (rt_size_t) ptr - (rt_size_t) buffer; +} + +void rt_hw_uart_init(void) +{ + struct rt_uart_v850* uart; + + /* get uart device */ + uart = &uart_device; + + /* device initialization */ + uart->parent.type = RT_Device_Class_Char; + rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer)); + uart->read_index = uart->save_index = 0; + + /* device interface */ + uart->parent.init = rt_uart_init; + uart->parent.open = rt_uart_open; + uart->parent.close = rt_uart_close; + uart->parent.read = rt_uart_read; + uart->parent.write = rt_uart_write; + uart->parent.control = RT_NULL; + uart->parent.private = RT_NULL; + + rt_device_register(&uart->parent, + "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX); +} +#endif /* end of UART */ + +/*@}*/ diff --git a/bsp/upd70f3454/uart.h b/bsp/upd70f3454/uart.h new file mode 100644 index 0000000000..c7ed52c98e --- /dev/null +++ b/bsp/upd70f3454/uart.h @@ -0,0 +1,296 @@ +#ifndef __UART_H__ +#define __UART_H__ + +#define BAUD_RATE 9600 + +/* + UARTAn control register 0 (UAnCTL0) +*/ +#define _10_UARTA_UAnCTL0_INITIALVALUE 0x10U +/* UARTAn operation control (UAnPWR) */ +#define _00_UARTA_OPERATION_DISABLE 0x00U /* disable UARTAn operation (UARTAn reset asynchronously) */ +#define _80_UARTA_OPERATION_ENABLE 0x80U /* enable UARTAn operation */ +/* Transmission operation enable (UAnTXE) */ +#define _00_UARTA_TRANSMISSION_DISABLE 0x00U /* disable transmission operation */ +#define _40_UARTA_TRANSMISSION_ENABLE 0x40U /* enable transmission operation */ +/* Reception operation enable (UAnRXE) */ +#define _00_UARTA_RECEPTION_DISABLE 0x00U /* disable reception operation */ +#define _20_UARTA_RECEPTION_ENABLE 0x20U /* enable reception operation */ +/* Transfer direction selection (UAnDIR) */ +#define _00_UARTA_TRANSFDIR_MSB 0x00U /* MSB-first transfer */ +#define _10_UARTA_TRANSFDIR_LSB 0x10U /* LSB-first transfer */ +/* Parity selection during transmission/reception (UAnPS1,UAnPS0) */ +#define _00_UARTA_PARITY_NONE 0x00U /* no parity output/reception with no parity */ +#define _04_UARTA_PARITY_ZREO 0x04U /* 0 parity output/reception with 0 parity */ +#define _08_UARTA_PARITY_ODD 0x08U /* odd parity output/odd parity check */ +#define _0C_UARTA_PARITY_EVEN 0x0CU /* even parity output/even parity check */ +/* Specification of data character length of 1 frame of transmit/receive data (UAnCL) */ +#define _00_UARTA_DATALENGTH_7BIT 0x00U /* 7 bits */ +#define _02_UARTA_DATALENGTH_8BIT 0x02U /* 8 bits */ +/* Specification of length of stop bit for transmit data (UAnSL) */ +#define _00_UARTA_STOPLENGTH_1BIT 0x00U /* 1 bit */ +#define _01_UARTA_STOPLENGTH_2BIT 0x01U /* 2 bits */ + +/* + UARTAn base clock selects register (UAnCTL1) +*/ +/* UAnCTL1 register (UAnCKS3 - UAnCKS0) */ +#define _00_UARTA_BASECLK_FXX_2 0x00U /* fXX/2 */ +#define _01_UARTA_BASECLK_FXX_4 0x01U /* fXX/2^2 */ +#define _02_UARTA_BASECLK_FXX_8 0x02U /* fXX/2^3 */ +#define _03_UARTA_BASECLK_FXX_16 0x03U /* fXX/2^4 */ +#define _04_UARTA_BASECLK_FXX_32 0x04U /* fXX/2^5 */ +#define _05_UARTA_BASECLK_FXX_64 0x05U /* fXX/2^6 */ +#define _06_UARTA_BASECLK_FXX_128 0x06U /* fXX/2^7 */ +#define _07_UARTA_BASECLK_FXX_256 0x07U /* fXX/2^8 */ +#define _08_UARTA_BASECLK_FXX_512 0x08U /* fXX/2^9 */ +#define _09_UARTA_BASECLK_FXX_1024 0x09U /* fXX/2^10 */ +#define _0A_UARTA_BASECLK_FXX_2048 0x0AU /* fXX/2^11 */ +#define _0B_UARTA_BASECLK_FXX_4096 0x0BU /* fXX/2^12 */ + +/* + UARTAn option control register 0 (UAnOPT0) +*/ +#define _14_UARTA_UAnOPT0_INITIALVALUE 0x14U +/* Transmit data level bit(UAnTDL) */ +#define _00_UARTA_TRAN_DATALEVEL_NORMAL 0x00U /* normal output of transfer data */ +#define _02_UARTA_TRAN_DATALEVEL_INVERTED 0x02U /* inverted output of transfer data */ +/* Receive data level bit(UAnRDL) */ +#define _00_UARTA_REC_DATALEVEL_NORMAL 0x00U /* normal input of transfer data */ +#define _01_UARTA_REC_DATALEVEL_INVERTED 0x01U /* inverted input of transfer data */ + +/* + CSIBn control register 0 (CBnCTL0) +*/ +/* Specification of CSIBn operation disable/enable (CBnPWR)*/ +#define _00_CSIB_OPERATION_DISABLE 0x00U /* disable CSIBn operation and reset the CBnSTR register */ +#define _80_CSIB_OPERATION_ENABLE 0x80U /* enable CSIBn operation */ +/* Specification of transmit operation disable/enable (CBnTXE)*/ +#define _00_CSIB_TRANSMIT_DISABLE 0x00U /* disable transmit operation */ +#define _40_CSIB_TRANSMIT_ENABLE 0x40U /* enable transmit operation */ +/* Specification of receive operation disable/enable (CBnRXE)*/ +#define _00_CSIB_RECEIVE_DISABLE 0x00U /* disable receive operation */ +#define _20_CSIB_RECEIVE_ENABLE 0x20U /* enable receive operation */ +/* Specification of transfer direction mode (MSB/LSB) (CBnDIR) */ +#define _00_CSIB_DATA_MSB 0x00U /* MSB first */ +#define _10_CSIB_DATA_LSB 0x10U /* LSB first */ +/* Transfer mode specification (CBnTMS) */ +#define _00_CSIB_MODE_SINGLE 0x00U /* single transfer mode */ +#define _02_CSIB_MODE_CONTINUOUS 0x02U /* continuous transfer mode */ +/* Specification of start transfer disable/enable (CBnSCE) */ +#define _00_CSIB_STARTTRG_INVALID 0x00U /* communication start trigger invalid */ +#define _01_CSIB_STARTTRG_VALID 0x01U /* communication start trigger valid */ + +/* + CSIBn control register 1 (CBnCTL1) +*/ +/* Specification of data transmission/reception timing in relation to SCKBn (CBnCKP, CBnDAP) */ +#define _00_CSIB_DATA_TIMING1 0x00U /* communication type 1 */ +#define _08_CSIB_DATA_TIMING2 0x08U /* communication type 2 */ +#define _10_CSIB_DATA_TIMING3 0x10U /* communication type 3 */ +#define _18_CSIB_DATA_TIMING4 0x18U /* communication type 4 */ +/* Specification of input clock (CBnCKS2 - CBnCKS0) */ +#define _00_CSIB_CLOCK_1 0x00U /* fXX /2 */ +#define _01_CSIB_CLOCK_2 0x01U /* fXX/4 */ +#define _02_CSIB_CLOCK_3 0x02U /* fXX /8 */ +#define _03_CSIB_CLOCK_4 0x03U /* fXX /16 */ +#define _04_CSIB_CLOCK_5 0x04U /* fXX /32 */ +#define _05_CSIB_CLOCK_6 0x05U /* fXX /64 */ +#define _06_CSIB_CLOCK_7 0x06U /* fBRGm */ +#define _07_CSIB_CLOCK_EXT 0x07U /* external clock SCKBn */ + +/* + CSIBn control register 2 (CBnCTL2) +*/ +/* Serial register bit length (CBnCL3,CBnCL2,CBnCL1,CBnCL0) */ +#define _00_CSIB_DATA_LENGTH_8 0x00U /* 8 bits */ +#define _01_CSIB_DATA_LENGTH_9 0x01U /* 9 bits */ +#define _02_CSIB_DATA_LENGTH_10 0x02U /* 10 bits */ +#define _03_CSIB_DATA_LENGTH_11 0x03U /* 11 bits */ +#define _04_CSIB_DATA_LENGTH_12 0x04U /* 12 bits */ +#define _05_CSIB_DATA_LENGTH_13 0x05U /* 13 bits */ +#define _06_CSIB_DATA_LENGTH_14 0x06U /* 14 bits */ +#define _07_CSIB_DATA_LENGTH_15 0x07U /* 15 bits */ +#define _08_CSIB_DATA_LENGTH_16 0x08U /* 16 bits */ + +/* + CSIBn status register (CBnSTR) +*/ +/* Communication status flag (CBnTSF) */ +#define _00_CSIB_COMMUNICATION_STOP 0x00U /* communication stopped */ +#define _80_CSIB_COMMUNICATING 0x80U /* communicating */ +/* Overrun error flag (CBnOVE) */ +#define _00_CSIB_OVERRUN_NONE 0x00U /* no overrun */ +#define _01_CSIB_OVERRUN 0x01U /* overrun */ + +/* + BRGm prescaler mode registers (PRSMm) +*/ +/* Baud rate output(BGCEm) */ +#define _00_CSIB_FBRGM_DISABLE 0x00U /* baudrate output disabled */ +#define _10_CSIB_FBRGM_ENABLE 0x10U /* baudrate output enabled */ +/* Input clock selection (BGCSm1,BGCSm0) */ +#define _00_CSIB_FBGCS_0 0x00U /* fXX */ +#define _01_CSIB_FBGCS_1 0x01U /* fXX/2 */ +#define _02_CSIB_FBGCS_2 0x02U /* fXX/4 */ +#define _03_CSIB_FBGCS_3 0x03U /* fXX/8 */ +#define CB4RIC UA0RIC +#define CB4TIC UA0TIC +#define CB0RIC IICIC1 + +/* + IIC control register (IICCn) +*/ +/* IIC operation enable (IICEn) */ +#define _80_IIC_OPERATION 0x80U +#define _00_IIC_OPERATION_DISABLE 0x00U /* stop operation */ +#define _80_IIC_OPERATION_ENABLE 0x80U /* enable operation */ +/* Exit from communications (LRELn) */ +#define _40_IIC_COMMUNICATION 0x40U +#define _00_IIC_COMMUNICATION_NORMAL 0x00U /* normal operation */ +#define _40_IIC_COMMUNICATION_EXIT 0x40U /* exit from current communication */ +/* Wait cancellation (WRELn) */ +#define _20_IIC_WAITCANCEL 0x20U +#define _00_IIC_WAIT_NOTCANCEL 0x00U /* do not cancel wait */ +#define _20_IIC_WAIT_CANCEL 0x20U /* cancel wait */ +/* Generation of interrupt when stop condition (SPIEn) */ +#define _10_IIC_STOPINT 0x10U +#define _00_IIC_STOPINT_DISABLE 0x00U /* disable */ +#define _10_IIC_STOPINT_ENABLE 0x10U /* enable */ +/* Wait and interrupt generation (WTIMn) */ +#define _08_IIC_WAITINT 0x08U +#define _00_IIC_WAITINT_CLK8FALLING 0x00U /* generate at the eighth clock falling edge */ +#define _08_IIC_WAITINT_CLK9FALLING 0x08U /* generated at the ninth clock falling edge */ +/* Acknowledgement control (ACKEn) */ +#define _04_IIC_ACK 0x04 +#define _00_IIC_ACK_DISABLE 0x00U /* disable acknowledgement */ +#define _04_IIC_ACK_ENABLE 0x04U /* enable acknowledgement */ +/* Start condition trigger (STTn) */ +#define _02_IIC_STARTCONDITION 0x02U +#define _00_IIC_START_NOTGENERATE 0x00U /* do not generate start condition */ +#define _02_IIC_START_GENERATE 0x02U /* generate start condition */ +/* Stop condition trigger (SPTn) */ +#define _01_IIC_STOPCONDITION 0x01U +#define _00_IIC_STOP_NOTGENERATE 0x00U /* do not generate stop condition */ +#define _01_IIC_STOP_GENERATE 0x01U /* generate stop condition */ + +/* + IIC Status Register (IICSn) +*/ +/* Master device status (MSTSn) */ +#define _80_IIC_MASTERSTATUS 0x80U +#define _00_IIC_STATUS_NOTMASTER 0x00U /* slave device status or communication standby status */ +#define _80_IIC_STATUS_MASTER 0x80U /* master device communication status */ +/* Detection of arbitration loss (ALDn) */ +#define _40_IIC_ARBITRATION 0x40U +#define _00_IIC_ARBITRATION_NO 0x00U /* arbitration win or no arbitration */ +#define _40_IIC_ARBITRATION_LOSS 0x40U /* arbitration loss */ +/* Detection of extension code reception (EXCn) */ +#define _20_IIC_EXTENSIONCODE 0x20U +#define _00_IIC_EXTCODE_NOT 0x00U /* extension code not received */ +#define _20_IIC_EXTCODE_RECEIVED 0x20U /* extension code received */ +/* Detection of matching addresses (COIn) */ +#define _10_IIC_ADDRESSMATCH 0x10U +#define _00_IIC_ADDRESS_NOTMATCH 0x00U /* addresses do not match */ +#define _10_IIC_ADDRESS_MATCH 0x10U /* addresses match */ +/* Detection of transmit/receive status (TRCn) */ +#define _08_IIC_STATUS 0x08U +#define _00_IIC_STATUS_RECEIVE 0x00U /* receive status */ +#define _08_IIC_STATUS_TRANSMIT 0x08U /* transmit status */ +/* Detection of acknowledge signal (ACKDn) */ +#define _04_IIC_ACKDETECTION 0x04U +#define _00_IIC_ACK_NOTDETECTED 0x00U /* ACK signal was not detected */ +#define _04_IIC_ACK_DETECTED 0x04U /* ACK signal was detected */ +/* Detection of start condition (STDn) */ +#define _02_IIC_STARTDETECTION 0x02U +#define _00_IIC_START_NOTDETECTED 0x00U /* start condition not detected */ +#define _02_IIC_START_DETECTED 0x02U /* start condition detected */ +/* Detection of stop condition (SPDn) */ +#define _01_IIC_STOPDETECTION 0x01U +#define _00_IIC_STOP_NOTDETECTED 0x00U /* stop condition not detected */ +#define _01_IIC_STOP_DETECTED 0x01U /* stop condition detected */ + +/* + IIC Flag Register (IICFn) +*/ +/* STTn clear flag (STCFn) */ +#define _80_IIC_STARTFLAG 0x80U +#define _00_IIC_STARTFLAG_GENERATE 0x00U /* generate start condition */ +#define _80_IIC_STARTFLAG_UNSUCCESSFUL 0x80U /* start condition generation unsuccessful */ +/* IIC bus status flag (IICBSYn) */ +#define _40_IIC_BUSSTATUS 0x40U +#define _00_IIC_BUS_RELEASE 0x00U /* bus release status */ +#define _40_IIC_BUS_COMMUNICATION 0x40U /* bus communication status */ +/* Initial start enable trigger (STCENn) */ +#define _02_IIC_STARTWITHSTOP 0x02U +#define _00_IIC_START_WITHSTOP 0x00U /* generation of a start condition upon detection of a stop condition */ +#define _02_IIC_START_WITHOUTSTOP 0x02U /* generation of a start condition without detecting a stop condition */ +/* Communication reservation function disable bit (IICRSVn) */ +#define _01_IIC_RESERVATION 0x01U +#define _00_IIC_RESERVATION_ENABLE 0x00U /* enable communication reservation */ +#define _01_IIC_RESERVATION_DISABLE 0x01U /* disable communication reservation */ + +/* + IIC clock selection register (IICCLn) +*/ +#define _00_IICCL_INITIALVALUE 0x00U +/* Detection of SCL0n pin level (CLDn) */ +#define _20_IIC_SCLLEVEL 0x20U +#define _00_IIC_SCL_LOW 0x00U /* clock line at low level */ +#define _20_IIC_SCL_HIGH 0x20U /* clock line at high level */ +/* Detection of SDA0 pin level (DADn) */ +#define _10_IIC_SDALEVEL 0x10U +#define _00_IIC_SDA_LOW 0x00U /* data line at low level */ +#define _10_IIC_SDA_HIGH 0x10U /* data line at high level */ +/* Operation mode switching (SMCn) */ +#define _08_IIC_OPERATIONMODE 0x08U +#define _00_IIC_MODE_STANDARD 0x00U /* operates in standard mode */ +#define _08_IIC_MODE_HIGHSPEED 0x08U /* operates in high-speed mode */ +/* Digital filter operation control (DFCn) */ +#define _04_IIC_DIGITALFILTER 0x04U +#define _00_IIC_FILTER_OFF 0x00U /* digital filter off */ +#define _04_IIC_FILTER_ON 0x04U /* digital filter on */ +/* Operation mode switching (CLn1, CLn0) */ +#define _03_IIC_CLOCKSELECTION 0x03U +/* Combine of (CLn1, CLn0)*/ +#define _00_IIC_CLOCK0 0x00U +#define _01_IIC_CLOCK1 0x01U +#define _02_IIC_CLOCK2 0x02U +#define _03_IIC_CLOCK3 0x03U + +/* + IIC division clock select register (OCKSn) +*/ +#define _10_IIC_SELECTED0 0x10U +#define _11_IIC_SELECTED1 0x11U +#define _12_IIC_SELECTED2 0x12U +#define _13_IIC_SELECTED3 0x13U +#define _18_IIC_SELECTED4 0x18U + +/* + IIC function expansion register 0 (IICXn) +*/ +/* IIC clock expension (CLXn) */ +#define _01_IIC_CLOCKEXPENSION 0x01U +#define _00_IIC_EXPENSION0 0x00U +#define _01_IIC_EXPENSION1 0x01U +#define _80_ADDRESS_COMPLETE 0x80U +#define _00_IIC_MASTER_FLAG_CLEAR 0x00U +#define IICIC2 UA1RIC +#define IICIC0 UA2RIC +/* +******************************************************************************* +** Macro define +******************************************************************************* +*/ +/* Selection of 8-bit counter output clock (UA1BRS7~UA1BRS0) */ +#define _D0_UARTA1_BASECLK_DIVISION 0xD0U /* 4 ~ 255 */ //9600 +#define _11_UARTA1_BASECLK_DIVISION 0x11U /* 4 ~ 255 */ //115200 +enum TransferMode +{ + SEND, RECEIVE +}; + +void rt_hw_uart_init(void); + +#endif diff --git a/bsp/upd70f3454/upd70f3454.cgp b/bsp/upd70f3454/upd70f3454.cgp new file mode 100644 index 0000000000..adc9562b68 --- /dev/null +++ b/bsp/upd70f3454/upd70f3454.cgp @@ -0,0 +1,1575 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\..\components\finsh\finsh_token.h + + + $PROJ_DIR$\..\..\components\finsh\finsh_var.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_var.h + + + $PROJ_DIR$\..\..\components\finsh\finsh_vm.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_vm.h + + + $PROJ_DIR$\..\..\components\finsh\shell.c + + + $PROJ_DIR$\..\..\components\finsh\shell.h + + + $PROJ_DIR$\..\..\components\finsh\symbol.c + + + + include + + $PROJ_DIR$\..\..\include\rtdef.h + + + $PROJ_DIR$\..\..\include\rthw.h + + + $PROJ_DIR$\..\..\include\rtm.h + + + $PROJ_DIR$\..\..\include\rtthread.h + + + + kernel + + $PROJ_DIR$\..\..\src\clock.c + + + $PROJ_DIR$\..\..\src\device.c + + + $PROJ_DIR$\..\..\src\idle.c + + + $PROJ_DIR$\..\..\src\ipc.c + + + $PROJ_DIR$\..\..\src\irq.c + + + $PROJ_DIR$\..\..\src\kservice.c + + + $PROJ_DIR$\..\..\src\kservice.h + + + $PROJ_DIR$\..\..\src\mem.c + + + $PROJ_DIR$\..\..\src\mempool.c + + + $PROJ_DIR$\..\..\src\module.c + + + $PROJ_DIR$\..\..\src\module.h + + + $PROJ_DIR$\..\..\src\object.c + + + $PROJ_DIR$\..\..\src\rtm.c + + + $PROJ_DIR$\..\..\src\scheduler.c + + + $PROJ_DIR$\..\..\src\slab.c + + + $PROJ_DIR$\..\..\src\thread.c + + + $PROJ_DIR$\..\..\src\timer.c + + + + libcpu + + $PROJ_DIR$\..\..\libcpu\v850\context.asm + + + $PROJ_DIR$\..\..\libcpu\v850\interrupt.c + + + $PROJ_DIR$\..\..\libcpu\v850\stack.c + + + + $PROJ_DIR$\application.c + + + $PROJ_DIR$\board.c + + + $PROJ_DIR$\applilet3_src\CG_port.c + + + $PROJ_DIR$\applilet3_src\CG_port_user.c + + + $PROJ_DIR$\applilet3_src\CG_system.c + + + $PROJ_DIR$\applilet3_src\CG_system_user.c + + + $PROJ_DIR$\applilet3_src\CG_systeminit.c + + + $PROJ_DIR$\applilet3_src\CG_timer.c + + + $PROJ_DIR$\applilet3_src\CG_timer_user.c + + + $PROJ_DIR$\cstartup.s85 + + + $PROJ_DIR$\startup.c + + + $PROJ_DIR$\uart.c + + + + diff --git a/bsp/upd70f3454/upd70f3454.eww b/bsp/upd70f3454/upd70f3454.eww new file mode 100644 index 0000000000..3fb65b7999 --- /dev/null +++ b/bsp/upd70f3454/upd70f3454.eww @@ -0,0 +1,8 @@ + + + + + $WS_DIR$\upd70f3454.ewp + + + diff --git a/libcpu/v850/context.asm b/libcpu/v850/context.asm new file mode 100644 index 0000000000..7783a94c51 --- /dev/null +++ b/libcpu/v850/context.asm @@ -0,0 +1,218 @@ +#include "macdefs.inc" + + name OS_Core + + COMMON INTVEC:CODE + +;******************************************************************** +; +; function: +; description: Trap 0x10 vector used for context switch +; Right now, all TRAPs to $1x are trated the same way +; + org 50h + jr OSCtxSW + + +;******************************************************************** +; +; function: +; description: Timer 40 compare match interrupt used for system +; tick interrupt +; + org 0x220 + jr OSTickIntr + + org 0x0520 + jr uarta1_int_r + + RSEG CODE(1) + + EXTERN rt_thread_switch_interrput_flag + EXTERN rt_interrupt_from_thread + EXTERN rt_interrupt_to_thread + + EXTERN rt_interrupt_enter + EXTERN rt_interrupt_leave + EXTERN rt_tick_increase + EXTERN uarta1_receive_handler + + PUBLIC rt_hw_interrupt_disable + PUBLIC rt_hw_interrupt_enable + PUBLIC rt_hw_context_switch_to + PUBLIC rt_hw_context_switch + PUBLIC rt_hw_context_switch_interrupt + PUBLIC OSCtxSW + PUBLIC OS_Restore_CPU_Context + +rt_hw_interrupt_disable: + stsr psw, r1 + di + jmp [lp] + +rt_hw_interrupt_enable: + ldsr r1, psw + jmp [lp] + +OS_Restore_CPU_Context: + mov sp, ep + sld.w 4[ep], r2 + sld.w 8[ep], r5 + sld.w 12[ep],r6 + sld.w 16[ep],r7 + sld.w 20[ep],r8 + sld.w 24[ep],r9 + sld.w 28[ep],r10 + sld.w 32[ep],r11 + sld.w 36[ep],r12 + sld.w 40[ep],r13 + sld.w 44[ep],r14 + sld.w 48[ep],r15 + sld.w 52[ep],r16 + + ;See what was the latest interruption (trap or interrupt) + stsr ecr, r17 ;Move ecr to r17 + mov 0x050,r1 + cmp r1, r17 ;If latest break was due to TRAP, set EP + be _SetEP + +_ClrEP: + mov 0x20, r17 ;Set only ID + ldsr r17, psw + + ;Restore caller address + sld.w 56[ep], r1 + ldsr r1, EIPC + ;Restore PSW + sld.w 60[ep], r1 + andi 0xffdf,r1,r1 + ldsr r1, EIPSW + sld.w 0[ep], r1 + dispose (8+(4*14)),{r23,r24,r25,r26,r27,r28,r29,r30,r31} + + ;Return from interrupt starts new task! + reti + +_SetEP: + mov 0x60, r17 ;Set both EIPC and ID bits + ldsr r17, psw + + ;Restore caller address + sld.w 56[ep], r1 + ldsr r1, EIPC + ;Restore PSW + sld.w 60[ep], r1 + andi 0xffdf,r1,r1 + ldsr r1, EIPSW + sld.w 0[ep], r1 + dispose (8+(4*14)),{r23,r24,r25,r26,r27,r28,r29,r30,r31} + + ;Return from interrupt starts new task! + reti + +//rseg CODE:CODE +//public rt_hw_context_switch_to +rt_hw_context_switch_to: + ;Load stack pointer of the task to run + ld.w 0[r1], sp ;load sp from struct + + ;Restore all Processor registers from stack and return from interrupt + jr OS_Restore_CPU_Context + +OSCtxSW: + SAVE_CPU_CTX ;Save all CPU registers + + mov rt_thread_switch_interrput_flag, r1 + ld.w 0[r1],r5 + cmp 0, r5 + be exit + + mov 0, r5 + st.b r5, 0[r1] + + mov rt_interrupt_from_thread, r21 + ld.w 0[r21], r21 + st.w sp, 0[r21] + + mov rt_interrupt_to_thread, r1 + ld.w 0[r1], r1 + ld.w 0[r1], sp + +exit: + ;Restore all Processor registers from stack and return from interrupt + jr OS_Restore_CPU_Context + +;R1 -> rt_interrupt_from_thread +;R5 -> rt_interrupt_to_thread +rt_hw_context_switch: + mov rt_thread_switch_interrput_flag, r8 + ld.w 0[r8],r9 + cmp 1, r9 + be jump1 + ;mov rt_thread_switch_interrput_flag, r1 + mov 1, r9 + st.b r9, 0[r8] + mov rt_interrupt_from_thread, r10 + st.w r1, 0[r10] +jump1 + mov rt_interrupt_to_thread, r11 + st.w r5, 0[r11] + trap 0x10 + jmp [lp] + +rt_hw_context_switch_interrupt: + mov rt_thread_switch_interrput_flag, r8 + ld.w 0[r8],r9 + cmp 1, r9 + be jump2 + ;mov rt_thread_switch_interrput_flag, r1 + mov 1, r9 + st.b r9, 0[r8] + mov rt_interrupt_from_thread, r10 + st.w r1, 0[r10] +jump2 + mov rt_interrupt_to_thread, r11 + st.w r5, 0[r11] + jmp [lp] + +rt_hw_context_switch_interrupt_do + mov rt_thread_switch_interrput_flag, r8 + mov 0, r9 + st.b r9, 0[r8] + + mov rt_interrupt_from_thread, r21 + ld.w 0[r21], r21 + st.w sp, 0[r21] + + mov rt_interrupt_to_thread, r1 + ld.w 0[r1], r1 + ld.w 0[r1], sp + jr OS_Restore_CPU_Context + +OSTickIntr: + SAVE_CPU_CTX ;Save current task's registers + jarl rt_interrupt_enter,lp + jarl rt_tick_increase,lp + jarl rt_interrupt_leave,lp + + mov rt_thread_switch_interrput_flag, r8 + ld.w 0[r8],r9 + cmp 1, r9 + be rt_hw_context_switch_interrupt_do + + jr OS_Restore_CPU_Context + +uarta1_int_r: + SAVE_CPU_CTX ;Save current task's registers + jarl rt_interrupt_enter,lp + jarl uarta1_receive_handler,lp + jarl rt_interrupt_leave,lp + + mov rt_thread_switch_interrput_flag, r8 + ld.w 0[r8],r9 + cmp 1, r9 + be rt_hw_context_switch_interrupt_do + + jr OS_Restore_CPU_Context + + END diff --git a/libcpu/v850/interrupt.c b/libcpu/v850/interrupt.c new file mode 100644 index 0000000000..79fcaae014 --- /dev/null +++ b/libcpu/v850/interrupt.c @@ -0,0 +1,22 @@ +/* + * File : interrupt.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-06-29 lgnq the first version + * + * For : NEC V850E + * Toolchain : IAR Embedded Workbench for V850 v3.71 +*/ + +#include + +rt_uint32_t rt_interrupt_from_thread; +rt_uint32_t rt_interrupt_to_thread; +rt_uint32_t rt_thread_switch_interrput_flag; \ No newline at end of file diff --git a/libcpu/v850/macdefs.inc b/libcpu/v850/macdefs.inc new file mode 100644 index 0000000000..4a0c4d4823 --- /dev/null +++ b/libcpu/v850/macdefs.inc @@ -0,0 +1,125 @@ +; +; These are the macros used by the v850 port of the uCOS/II. +; + + + + + +;******************************************************************** +; function: +; description: +; --- Modifies ---------------------------------------------- +; IO : +; Mem: +; CPU: +; --- Uses -------------------------------------------------- +; IO : +; Mem: +; --- Input ------------------------------------------------- +; --- Output ------------------------------------------------ +; --- Notes ------------------------------------------------- +;==================================================================== + +SAVE_CPU_CTX MACRO + ;Save all registers on entry (r3 is the stack pointer) + prepare {r23,r24,r25,r26,r27,r28,r29,r30,r31},(8+(4*14)) ;Add 8 bytes for 2 more registers + mov sp, ep + sst.w r1, 0[ep] + sst.w r2, 4[ep] + sst.w r5, 8[ep] + sst.w r6, 12[ep] + sst.w r7, 16[ep] + sst.w r8, 20[ep] + sst.w r9, 24[ep] + sst.w r10, 28[ep] + sst.w r11, 32[ep] + sst.w r12, 36[ep] + sst.w r13, 40[ep] + sst.w r14, 44[ep] + sst.w r15, 48[ep] + sst.w r16, 52[ep] + ;Save caller's PC + stsr EIPC, r1 + sst.w r1, 56[ep] + ;Save caller's PSW + stsr EIPSW, r1 + sst.w r1, 60[ep] + + ENDMAC + + + + + +;******************************************************************** +; function: +; description: +; --- Modifies ---------------------------------------------- +; IO : +; Mem: +; CPU: +; --- Uses -------------------------------------------------- +; IO : +; Mem: +; --- Input ------------------------------------------------- +; --- Output ------------------------------------------------ +; --- Notes ------------------------------------------------- +;==================================================================== +SAVE_SP MACRO + ;Save stack pointer on OSTCBCur->OSTCBStkPtr (OSTCBStkPtr=0) + mov OSTCBCur, r21 + ld.w 0[r21], r21 + st.w sp, 0[r21] + ENDMAC + + + +;******************************************************************** +; function: +; description: +; --- Modifies ---------------------------------------------- +; IO : +; Mem: +; CPU: +; --- Uses -------------------------------------------------- +; IO : +; Mem: +; --- Input ------------------------------------------------- +; --- Output ------------------------------------------------ +; --- Notes ------------------------------------------------- +;==================================================================== +ISR_ENTRY MACRO + LOCAL _DontSaveSP + + ;Save all CPU registers according to the standard stack frame + SAVE_CPU_CTX + + mov OSIntNesting, r1 ;Increment OSNesting by one + LD.BU 0[r1],r2 + add 1, r2 + ST.B r2, 0[r1] + cmp 1, r2 ;If OSNesting==1 save SP in current TCB + bne _DontSaveSP + SAVE_SP +_DontSaveSP: + ENDMAC + +;******************************************************************** +; function: +; description: +; --- Modifies ---------------------------------------------- +; IO : +; Mem: +; CPU: +; --- Uses -------------------------------------------------- +; IO : +; Mem: +; --- Input ------------------------------------------------- +; --- Output ------------------------------------------------ +; --- Notes ------------------------------------------------- +;==================================================================== +ISR_EXIT MACRO + jarl OSIntExit, lp ;Call OSIntExit() + jr OS_Restore_CPU_Context ;Restore processors registers and execute RETI + ENDMAC diff --git a/libcpu/v850/stack.c b/libcpu/v850/stack.c new file mode 100644 index 0000000000..2658716485 --- /dev/null +++ b/libcpu/v850/stack.c @@ -0,0 +1,61 @@ +/* + * File : stack.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-06-29 lgnq the first version + * + * For : NEC V850E + * Toolchain : IAR Embedded Workbench for V850 v3.71 +*/ + +#include + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit) +{ + rt_uint32_t *stk; + + stk = (rt_uint32_t *)stack_addr; /* Load stack pointer */ + *(--stk) = (rt_uint32_t) 0x23232323; /* r23 */ + *(--stk) = (rt_uint32_t) 0x24242424; /* r24 */ + *(--stk) = (rt_uint32_t) 0x25252525; /* r25 */ + *(--stk) = (rt_uint32_t) 0x26262626; /* r26 */ + *(--stk) = (rt_uint32_t) 0x27272727; /* r27 */ + *(--stk) = (rt_uint32_t) 0x28282828; /* r28 */ + *(--stk) = (rt_uint32_t) 0x29292929; /* r29 */ + *(--stk) = (rt_uint32_t) 0x30303030; /* r30 */ + *(--stk) = (rt_uint32_t) 0x31313131; /* r31 */ + *(--stk) = (rt_uint32_t) 0x00000000; /* Task PSW = Interrupts enabled */ + *(--stk) = (rt_uint32_t) tentry; /* Task's PC */ + *(--stk) = (rt_uint32_t) 0x16161616; /* r16 */ + *(--stk) = (rt_uint32_t) 0x15151515; /* r15 */ + *(--stk) = (rt_uint32_t) 0x14141414; /* r14 */ + *(--stk) = (rt_uint32_t) 0x13131313; /* r13 */ + *(--stk) = (rt_uint32_t) 0x12121212; /* r12 */ + *(--stk) = (rt_uint32_t) 0x11111111; /* r11 */ + *(--stk) = (rt_uint32_t) 0x10101010; /* r10 */ + *(--stk) = (rt_uint32_t) 0x09090909; /* r9 */ + *(--stk) = (rt_uint32_t) 0x08080808; /* r8 */ + *(--stk) = (rt_uint32_t) 0x07070707; /* r7 */ + *(--stk) = (rt_uint32_t) 0x06060606; /* r6 */ + *(--stk) = (rt_uint32_t) 0x05050505; /* r5 */ + *(--stk) = (rt_uint32_t) 0x02020202; /* r2 */ + *(--stk) = (rt_uint32_t) parameter; /* r1 */ + return ((rt_uint8_t *)stk); +}