libs/rt-thread
libs/rt-thread
4
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

fixed bug: correct cortex-m SCB->VTOR address.

Browse Source
This commit is contained in:
aozima 2013-06-23 18:08:16 +08:00
parent 93b9b28297
commit b045f93b47
3 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
libcpu/arm/cortex-m0/context_gcc.S
View File

@ -22,7 +22,7 @@
.thumb
.text
.equ SCB_VTOR, 0xE000ED04 /* Vector Table Offset Register */
.equ SCB_VTOR, 0xE000ED08 /* Vector Table Offset Register */
.equ ICSR, 0xE000ED04 /* interrupt control state register */
.equ PENDSVSET_BIT, 0x10000000 /* value to trigger PendSV exception */

2
libcpu/arm/cortex-m3/context_gcc.S
View File

@ -22,7 +22,7 @@
.thumb
.text
.equ SCB_VTOR, 0xE000ED04 /* Vector Table Offset Register */
.equ SCB_VTOR, 0xE000ED08 /* Vector Table Offset Register */
.equ ICSR, 0xE000ED04 /* interrupt control state register */
.equ PENDSVSET_BIT, 0x10000000 /* value to trigger PendSV exception */

2
libcpu/arm/cortex-m4/context_gcc.S
View File

@ -24,7 +24,7 @@
.thumb
.text
.equ SCB_VTOR, 0xE000ED04 /* Vector Table Offset Register */
.equ SCB_VTOR, 0xE000ED08 /* Vector Table Offset Register */
.equ NVIC_INT_CTRL, 0xE000ED04 /* interrupt control state register */
.equ NVIC_SYSPRI2, 0xE000ED20 /* system priority register (2) */
.equ NVIC_PENDSV_PRI, 0x00FF0000 /* PendSV priority value (lowest) */