bsp:ls2k:improved implement of shutdown and reboot command
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@ -1,26 +0,0 @@
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/*
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* Copyright (c) 2006-2020, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-09-17 maoxiaochuan first version
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*/
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#include <rtthread.h>
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static void reboot()
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{
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rt_hw_cpu_reset();
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}
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MSH_CMD_EXPORT(reboot, reboot system);
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static void poweroff()
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{
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rt_hw_cpu_shutdown();
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}
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MSH_CMD_EXPORT(poweroff, shutdown system);
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@ -16,6 +16,8 @@
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#include "exception.h"
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#include "drv_uart.h"
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#include "board.h"
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#include "ls2k1000.h"
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/**
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* this function will reset CPU
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*
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@ -28,6 +30,8 @@ void rt_hw_cpu_reset(void)
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rt_kprintf("reboot system...\n");
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while (1);
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}
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MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reboot, reset cpu);
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/**
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* this function will shutdown CPU
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@ -41,6 +45,7 @@ void rt_hw_cpu_shutdown(void)
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while (1);
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}
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MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_shutdown, poweroff, shutdown cpu);
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/**
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@ -12,8 +12,6 @@
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#define BOARD_H__
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#include <stdint.h>
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#include <rthw.h>
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#include "ls2k1000.h"
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extern unsigned char __bss_end;
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@ -21,28 +19,6 @@ extern unsigned char __bss_end;
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#define RT_HW_HEAP_BEGIN (void*)&__bss_end
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#define RT_HW_HEAP_END (void*)(RT_HW_HEAP_BEGIN + 64 * 1024 * 1024)
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/*
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* General PM Configuration Register
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*/
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#define PMCON_BASE (APB_BASE | (0x7 << 12))
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/*
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* Power Management1 Configuration Registers
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*/
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#define PM1_BASE (PMCON_BASE + 0x0C)
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#define PM1_STS HWREG32(PM1_BASE)
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#define PM1_EN HWREG32(PM1_BASE + 0x04)
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#define PM1_CNT HWREG32(PM1_BASE + 0x08)
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/*
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* Watch Dog Configuration Registers
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*/
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#define WDT_BASE (PMCON_BASE + 0x30)
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#define WDT_EN HWREG32(WDT_BASE)
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#define WDT_SET HWREG32(WDT_BASE + 0x04)
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#define WDT_TIMER HWREG32(WDT_BASE + 0x08)
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void rt_hw_board_init(void);
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#endif
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@ -3,6 +3,7 @@
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#include <mips.h>
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#include "interrupt.h"
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#include <rthw.h>
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#define APB_BASE CKSEG1ADDR(0xbfe00000)
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@ -24,6 +25,28 @@
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#define GEN_CONFIG0_REG (0xFFFFFFFFBfe10420)
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/*
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* General PM Configuration Register
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*/
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#define PMCON_BASE (APB_BASE | (0x7 << 12))
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/*
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* Power Management1 Configuration Registers
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*/
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#define PM1_BASE (PMCON_BASE + 0x0C)
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#define PM1_STS HWREG32(PM1_BASE)
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#define PM1_EN HWREG32(PM1_BASE + 0x04)
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#define PM1_CNT HWREG32(PM1_BASE + 0x08)
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/*
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* Watch Dog Configuration Registers
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*/
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#define WDT_BASE (PMCON_BASE + 0x30)
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#define WDT_EN HWREG32(WDT_BASE)
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#define WDT_SET HWREG32(WDT_BASE + 0x04)
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#define WDT_TIMER HWREG32(WDT_BASE + 0x08)
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void rt_hw_timer_handler(void);
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void rt_hw_uart_init(void);
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