bsp:ls2k:improved implement of shutdown and reboot command

This commit is contained in:
michael 2020-09-17 20:22:51 +08:00
parent 623bf0abc9
commit ab78ea1de1
4 changed files with 28 additions and 50 deletions

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@ -1,26 +0,0 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-09-17 maoxiaochuan first version
*/
#include <rtthread.h>
static void reboot()
{
rt_hw_cpu_reset();
}
MSH_CMD_EXPORT(reboot, reboot system);
static void poweroff()
{
rt_hw_cpu_shutdown();
}
MSH_CMD_EXPORT(poweroff, shutdown system);

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@ -16,6 +16,8 @@
#include "exception.h"
#include "drv_uart.h"
#include "board.h"
#include "ls2k1000.h"
/**
* this function will reset CPU
*
@ -28,6 +30,8 @@ void rt_hw_cpu_reset(void)
rt_kprintf("reboot system...\n");
while (1);
}
MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reboot, reset cpu);
/**
* this function will shutdown CPU
@ -41,6 +45,7 @@ void rt_hw_cpu_shutdown(void)
while (1);
}
MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_shutdown, poweroff, shutdown cpu);
/**

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@ -12,8 +12,6 @@
#define BOARD_H__
#include <stdint.h>
#include <rthw.h>
#include "ls2k1000.h"
extern unsigned char __bss_end;
@ -21,28 +19,6 @@ extern unsigned char __bss_end;
#define RT_HW_HEAP_BEGIN (void*)&__bss_end
#define RT_HW_HEAP_END (void*)(RT_HW_HEAP_BEGIN + 64 * 1024 * 1024)
/*
* General PM Configuration Register
*/
#define PMCON_BASE (APB_BASE | (0x7 << 12))
/*
* Power Management1 Configuration Registers
*/
#define PM1_BASE (PMCON_BASE + 0x0C)
#define PM1_STS HWREG32(PM1_BASE)
#define PM1_EN HWREG32(PM1_BASE + 0x04)
#define PM1_CNT HWREG32(PM1_BASE + 0x08)
/*
* Watch Dog Configuration Registers
*/
#define WDT_BASE (PMCON_BASE + 0x30)
#define WDT_EN HWREG32(WDT_BASE)
#define WDT_SET HWREG32(WDT_BASE + 0x04)
#define WDT_TIMER HWREG32(WDT_BASE + 0x08)
void rt_hw_board_init(void);
#endif

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@ -3,6 +3,7 @@
#include <mips.h>
#include "interrupt.h"
#include <rthw.h>
#define APB_BASE CKSEG1ADDR(0xbfe00000)
@ -24,6 +25,28 @@
#define GEN_CONFIG0_REG (0xFFFFFFFFBfe10420)
/*
* General PM Configuration Register
*/
#define PMCON_BASE (APB_BASE | (0x7 << 12))
/*
* Power Management1 Configuration Registers
*/
#define PM1_BASE (PMCON_BASE + 0x0C)
#define PM1_STS HWREG32(PM1_BASE)
#define PM1_EN HWREG32(PM1_BASE + 0x04)
#define PM1_CNT HWREG32(PM1_BASE + 0x08)
/*
* Watch Dog Configuration Registers
*/
#define WDT_BASE (PMCON_BASE + 0x30)
#define WDT_EN HWREG32(WDT_BASE)
#define WDT_SET HWREG32(WDT_BASE + 0x04)
#define WDT_TIMER HWREG32(WDT_BASE + 0x08)
void rt_hw_timer_handler(void);
void rt_hw_uart_init(void);