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add stm32f2xx eth driver 

git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1649 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
wuyangyong 2011-07-21 17:06:41 +00:00
parent aeff05a873
commit a8410acdaa
3 changed files with 1451 additions and 755 deletions
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266
bsp/stm32f20x/stm32f2xx_eth.c
View File

@ -20,10 +20,22 @@
* <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
*/
/*
* Change Logs:
* Date Author Notes
* 2011-07-22 aozima first implementation(stm32f207,dp83848,rmii,MCO)
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f2xx_eth.h"
#include "stm32f2xx_rcc.h"
/* PHY configuration section **************************************************/
/* PHY Reset delay */
#define PHY_RESET_DELAY ((uint32_t)0x000FFFFF)
/* PHY Configuration delay */
#define PHY_CONFIG_DELAY ((uint32_t)0x00FFFFFF)
/** @addtogroup STM32F2XX_ETH_Driver
* @brief ETH driver modules
@ -37,7 +49,7 @@
* @}
*/
#define DP83848_PHY_ADDRESS 0x01 /* Relative to STM3220F-EVAL Board */
#define DP83848_PHY_ADDRESS 0x1F /* Relative to STM3220F-EVAL Board */
/** @defgroup ETH_Private_Defines
* @{
@ -147,6 +159,7 @@ uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress)
RCC_ClocksTypeDef rcc_clocks;
uint32_t hclk = 60000000;
__IO uint32_t timeout = 0;
uint16_t RegRead;
/* Check the parameters */
/* MAC --------------------------*/
assert_param(IS_ETH_AUTONEGOTIATION(ETH_InitStruct->ETH_AutoNegotiation));
@ -168,7 +181,7 @@ uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress)
assert_param(IS_ETH_CONTROL_FRAMES(ETH_InitStruct->ETH_PassControlFrames));
assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(ETH_InitStruct->ETH_BroadcastFramesReception));
assert_param(IS_ETH_DESTINATION_ADDR_FILTER(ETH_InitStruct->ETH_DestinationAddrFilter));
assert_param(IS_ETH_PROMISCUOUS_MODE(ETH_InitStruct->ETH_PromiscuousMode));
assert_param(IS_ETH_PROMISCIOUS_MODE(ETH_InitStruct->ETH_PromiscuousMode));
assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(ETH_InitStruct->ETH_MulticastFramesFilter));
assert_param(IS_ETH_UNICAST_FRAMES_FILTER(ETH_InitStruct->ETH_UnicastFramesFilter));
assert_param(IS_ETH_PAUSE_TIME(ETH_InitStruct->ETH_PauseTime));
@ -215,40 +228,48 @@ uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress)
/* CSR Clock Range between 35-60 MHz */
tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div26;
}
else /* ((hclk >= 60000000)&&(hclk <= 72000000)) */
else if((hclk >= 60000000)&&(hclk < 100000000))
{
/* CSR Clock Range between 60-72 MHz */
/* CSR Clock Range between 60-100 MHz */
tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42;
}
else /* ((hclk >= 100000000)&&(hclk <= 120000000)) */
{
/* CSR Clock Range between 100-120 MHz */
tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div62;
}
/* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
ETH->MACMIIAR = (uint32_t)tmpreg;
/*-------------------- PHY initialization and configuration ----------------*/
/* Put the PHY in reset mode */
if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_Reset)))
{
/* Return ERROR in case of write timeout */
return ETH_ERROR;
}
/* Delay to assure PHY reset */
_eth_delay_(PHY_ResetDelay);
_eth_delay_(PHY_RESET_DELAY);
if(ETH_InitStruct->ETH_AutoNegotiation != ETH_AutoNegotiation_Disable)
{
/* We wait for linked satus... */
/* We wait for linked status... */
do
{
RegRead=ETH_ReadPHYRegister(PHYAddress, PHY_BSR);
timeout++;
} while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_Linked_Status) && (timeout < PHY_READ_TO));
} while (!(RegRead & PHY_Linked_Status) && (timeout < PHY_READ_TO*5));
/* Return ERROR in case of timeout */
if(timeout == PHY_READ_TO)
{
return ETH_ERROR;
}
/* Reset Timeout counter */
timeout = 0;
/* Enable Auto-Negotiation */
if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_AutoNegotiation)))
{
@ -256,44 +277,47 @@ uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress)
return ETH_ERROR;
}
/* Wait until the autonegotiation will be completed */
/* Wait until the auto-negotiation will be completed */
do
{
timeout++;
} while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_AutoNego_Complete) && (timeout < (uint32_t)PHY_READ_TO));
/* Return ERROR in case of timeout */
if(timeout == PHY_READ_TO)
{
return ETH_ERROR;
}
/* Reset Timeout counter */
timeout = 0;
RegValue = ETH_ReadPHYRegister(PHYAddress, 17);
/* Read the result of the autonegotiation */
RegValue = ETH_ReadPHYRegister(PHYAddress, PHY_SR);
/* Configure the MAC with the Duplex Mode fixed by the autonegotiation process */
if((RegValue & PHY_Duplex_Status) != (uint32_t)RESET)
/* 100 FDX*/
if((RegValue & 0x8000) != (uint32_t)RESET)
{
/* Set Ethernet duplex mode to FullDuplex following the autonegotiation */
ETH_InitStruct->ETH_Mode = ETH_Mode_FullDuplex;
ETH_InitStruct->ETH_Speed = ETH_Speed_100M;
}
else
else if((RegValue & 0x4000) != (uint32_t)RESET)//100 HDX
{
/* Set Ethernet duplex mode to HalfDuplex following the autonegotiation */
ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex;
ETH_InitStruct->ETH_Speed = ETH_Speed_100M;
}
/* Configure the MAC with the speed fixed by the autonegotiation process */
if(RegValue & PHY_Speed_Status)
else if((RegValue & 0x2000) != (uint32_t)RESET)//10 FDX
{
/* Set Ethernet speed to 10M following the autonegotiation */
/* Set Ethernet duplex mode to HalfDuplex following the autonegotiation */
ETH_InitStruct->ETH_Mode = ETH_Mode_FullDuplex;
ETH_InitStruct->ETH_Speed = ETH_Speed_10M;
}
else
else if((RegValue & 0x1000) != (uint32_t)RESET)//10 HDX
{
/* Set Ethernet speed to 100M following the autonegotiation */
ETH_InitStruct->ETH_Speed = ETH_Speed_100M;
/* Set Ethernet duplex mode to HalfDuplex following the autonegotiation */
ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex;
ETH_InitStruct->ETH_Speed = ETH_Speed_10M;
}
}
else
@ -305,7 +329,7 @@ uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress)
return ETH_ERROR;
}
/* Delay to assure PHY configuration */
_eth_delay_(PHY_ConfigDelay);
_eth_delay_(PHY_CONFIG_DELAY);
}
/*------------------------ ETHERNET MACCR Configuration --------------------*/
@ -438,66 +462,105 @@ uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress)
/* Enable the Enhanced DMA descriptors */
ETH->DMABMR |= ETH_DMABMR_EDE;
#endif /* USE_ENHANCED_DMA_DESCRIPTORS */
/* Return Ethernet configuration success */
return ETH_SUCCESS;
}
/**
* @brief Fills each ETH_InitStruct member with its default value.
* @param ETH_InitStruct: pointer to a ETH_InitTypeDef structure which will be initialized.
* @retval None
*/
void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct)
{
/* ETH_InitStruct members default value */
/*------------------------ MAC -----------------------------------*/
ETH_InitStruct->ETH_AutoNegotiation = ETH_AutoNegotiation_Disable;
/*------------------------ MAC Configuration ---------------------------*/
/* PHY Auto-negotiation enabled */
ETH_InitStruct->ETH_AutoNegotiation = ETH_AutoNegotiation_Enable;
/* MAC watchdog enabled: cuts-off long frame */
ETH_InitStruct->ETH_Watchdog = ETH_Watchdog_Enable;
/* MAC Jabber enabled in Half-duplex mode */
ETH_InitStruct->ETH_Jabber = ETH_Jabber_Enable;
/* Ethernet interframe gap set to 96 bits */
ETH_InitStruct->ETH_InterFrameGap = ETH_InterFrameGap_96Bit;
/* Carrier Sense Enabled in Half-Duplex mode */
ETH_InitStruct->ETH_CarrierSense = ETH_CarrierSense_Enable;
ETH_InitStruct->ETH_Speed = ETH_Speed_10M;
/* PHY speed configured to 100Mbit/s */
ETH_InitStruct->ETH_Speed = ETH_Speed_100M;
/* Receive own Frames in Half-Duplex mode enabled */
ETH_InitStruct->ETH_ReceiveOwn = ETH_ReceiveOwn_Enable;
/* MAC MII loopback disabled */
ETH_InitStruct->ETH_LoopbackMode = ETH_LoopbackMode_Disable;
ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex;
/* Full-Duplex mode selected */
ETH_InitStruct->ETH_Mode = ETH_Mode_FullDuplex;
/* IPv4 and TCP/UDP/ICMP frame Checksum Offload disabled */
ETH_InitStruct->ETH_ChecksumOffload = ETH_ChecksumOffload_Disable;
/* Retry Transmission enabled for half-duplex mode */
ETH_InitStruct->ETH_RetryTransmission = ETH_RetryTransmission_Enable;
/* Automatic PAD/CRC strip disabled*/
ETH_InitStruct->ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable;
/* half-duplex mode retransmission Backoff time_limit = 10 slot times*/
ETH_InitStruct->ETH_BackOffLimit = ETH_BackOffLimit_10;
/* half-duplex mode Deferral check disabled */
ETH_InitStruct->ETH_DeferralCheck = ETH_DeferralCheck_Disable;
/* Receive all frames disabled */
ETH_InitStruct->ETH_ReceiveAll = ETH_ReceiveAll_Disable;
/* Source address filtering (on the optional MAC addresses) disabled */
ETH_InitStruct->ETH_SourceAddrFilter = ETH_SourceAddrFilter_Disable;
/* Do not forward control frames that do not pass the address filtering */
ETH_InitStruct->ETH_PassControlFrames = ETH_PassControlFrames_BlockAll;
/* Disable reception of Broadcast frames */
ETH_InitStruct->ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable;
/* Normal Destination address filtering (not reverse addressing) */
ETH_InitStruct->ETH_DestinationAddrFilter = ETH_DestinationAddrFilter_Normal;
/* Promiscuous address filtering mode disabled */
ETH_InitStruct->ETH_PromiscuousMode = ETH_PromiscuousMode_Disable;
/* Perfect address filtering for multicast addresses */
ETH_InitStruct->ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect;
/* Perfect address filtering for unicast addresses */
ETH_InitStruct->ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect;
/* Initialize hash table high and low regs */
ETH_InitStruct->ETH_HashTableHigh = 0x0;
ETH_InitStruct->ETH_HashTableLow = 0x0;
/* Flow control config (flow control disabled)*/
ETH_InitStruct->ETH_PauseTime = 0x0;
ETH_InitStruct->ETH_ZeroQuantaPause = ETH_ZeroQuantaPause_Disable;
ETH_InitStruct->ETH_PauseLowThreshold = ETH_PauseLowThreshold_Minus4;
ETH_InitStruct->ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable;
ETH_InitStruct->ETH_ReceiveFlowControl = ETH_ReceiveFlowControl_Disable;
ETH_InitStruct->ETH_TransmitFlowControl = ETH_TransmitFlowControl_Disable;
/* VLANtag config (VLAN field not checked) */
ETH_InitStruct->ETH_VLANTagComparison = ETH_VLANTagComparison_16Bit;
ETH_InitStruct->ETH_VLANTagIdentifier = 0x0;
/*------------------------ DMA -----------------------------------*/
/*---------------------- DMA Configuration -------------------------------*/
/* Drops frames with with TCP/IP checksum errors */
ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable;
/* Store and forward mode enabled for receive */
ETH_InitStruct->ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable;
ETH_InitStruct->ETH_FlushReceivedFrame = ETH_FlushReceivedFrame_Disable;
/* Flush received frame that created FIFO overflow */
ETH_InitStruct->ETH_FlushReceivedFrame = ETH_FlushReceivedFrame_Enable;
/* Store and forward mode enabled for transmit */
ETH_InitStruct->ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;
/* Threshold TXFIFO level set to 64 bytes (used when threshold mode is enabled) */
ETH_InitStruct->ETH_TransmitThresholdControl = ETH_TransmitThresholdControl_64Bytes;
/* Disable forwarding frames with errors (short frames, CRC,...)*/
ETH_InitStruct->ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable;
/* Disable undersized good frames */
ETH_InitStruct->ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable;
/* Threshold RXFIFO level set to 64 bytes (used when Cut-through mode is enabled) */
ETH_InitStruct->ETH_ReceiveThresholdControl = ETH_ReceiveThresholdControl_64Bytes;
/* Disable Operate on second frame (transmit a second frame to FIFO without
waiting status of previous frame*/
ETH_InitStruct->ETH_SecondFrameOperate = ETH_SecondFrameOperate_Disable;
/* DMA works on 32-bit aligned start source and destinations addresses */
ETH_InitStruct->ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;
ETH_InitStruct->ETH_FixedBurst = ETH_FixedBurst_Disable;
ETH_InitStruct->ETH_RxDMABurstLength = ETH_RxDMABurstLength_1Beat;
ETH_InitStruct->ETH_TxDMABurstLength = ETH_TxDMABurstLength_1Beat;
/* Enabled Fixed Burst Mode (mix of INC4, INC8, INC16 and SINGLE DMA transactions */
ETH_InitStruct->ETH_FixedBurst = ETH_FixedBurst_Enable;
/* DMA transfer max burst length = 32 beats = 32 x 32bits */
ETH_InitStruct->ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat;
ETH_InitStruct->ETH_TxDMABurstLength = ETH_TxDMABurstLength_32Beat;
/* DMA Ring mode skip length = 0 */
ETH_InitStruct->ETH_DescriptorSkipLength = 0x0;
/* Equal priority (round-robin) between transmit and receive DMA engines */
ETH_InitStruct->ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_1_1;
}
@ -3322,8 +3385,6 @@ void ETH_IRQHandler(void)
status = ETH->DMASR;
rt_kprintf("ETH ISR\n");
/* Clear received IT */
if ((status & ETH_DMA_IT_NIS) != (u32)RESET)
ETH->DMASR = (u32)ETH_DMA_IT_NIS;
@ -3363,6 +3424,12 @@ static rt_err_t rt_stm32_eth_init(rt_device_t dev)
{
ETH_InitTypeDef ETH_InitStructure;
/* Enable ETHERNET clock */
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_ETH_MAC | RCC_AHB1Periph_ETH_MAC_Tx |
RCC_AHB1Periph_ETH_MAC_Rx, ENABLE);
SYSCFG_ETH_MediaInterfaceConfig(SYSCFG_ETH_MediaInterface_RMII);
/* Reset ETHERNET on AHB Bus */
ETH_DeInit();
@ -3372,13 +3439,16 @@ static rt_err_t rt_stm32_eth_init(rt_device_t dev)
/* Wait for software reset */
while (ETH_GetSoftwareResetStatus() == SET);
/* ETHERNET Configuration ------------------------------------------------------*/
/* ETHERNET Configuration --------------------------------------------------*/
/* Call ETH_StructInit if you don't like to configure all ETH_InitStructure parameter */
ETH_StructInit(&ETH_InitStructure);
/* Fill ETH_InitStructure parametrs */
/*------------------------ MAC -----------------------------------*/
ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Enable;
//ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Disable;
// ETH_InitStructure.ETH_Speed = ETH_Speed_10M;
// ETH_InitStructure.ETH_Mode = ETH_Mode_FullDuplex;
ETH_InitStructure.ETH_LoopbackMode = ETH_LoopbackMode_Disable;
ETH_InitStructure.ETH_RetryTransmission = ETH_RetryTransmission_Disable;
@ -3630,20 +3700,6 @@ struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
return p;
}
static void RCC_Configuration(void)
{
/* Enable GPIOs clocks */
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB |
RCC_AHB1Periph_GPIOC, ENABLE);
/* Enable SYSCFG and ADC3 clocks */
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG | RCC_APB2Periph_ADC3, ENABLE);
/* Enable MAC clocks */
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_ETH_MAC | RCC_AHB1Periph_ETH_MAC_Tx |
RCC_AHB1Periph_ETH_MAC_Rx, ENABLE);
}
static void NVIC_Configuration(void)
{
NVIC_InitTypeDef NVIC_InitStructure;
@ -3662,65 +3718,83 @@ static void NVIC_Configuration(void)
static void GPIO_Configuration(void)
{
GPIO_InitTypeDef GPIO_InitStructure;
__IO int i;
/* Configure PA1, PA2 and PA7 */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_7;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_25MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ;
GPIO_Init(GPIOA, &GPIO_InitStructure);
GPIO_PinAFConfig(GPIOA, GPIO_PinSource1, GPIO_AF_ETH);
GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_ETH);
GPIO_PinAFConfig(GPIOA, GPIO_PinSource7, GPIO_AF_ETH);
/* Enable GPIOs clocks */
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB |
RCC_AHB1Periph_GPIOC
, ENABLE);
/* Configure PB5 and PB8 */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_8;
GPIO_Init(GPIOB, &GPIO_InitStructure);
GPIO_PinAFConfig(GPIOB, GPIO_PinSource5, GPIO_AF_ETH);
GPIO_PinAFConfig(GPIOB, GPIO_PinSource8, GPIO_AF_ETH);
/* Configure PC1, PC2, PC3, PC4 and PC5 */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5;
GPIO_Init(GPIOC, &GPIO_InitStructure);
GPIO_PinAFConfig(GPIOC, GPIO_PinSource1, GPIO_AF_ETH);
GPIO_PinAFConfig(GPIOC, GPIO_PinSource2, GPIO_AF_ETH);
GPIO_PinAFConfig(GPIOC, GPIO_PinSource3, GPIO_AF_ETH);
GPIO_PinAFConfig(GPIOC, GPIO_PinSource4, GPIO_AF_ETH);
GPIO_PinAFConfig(GPIOC, GPIO_PinSource5, GPIO_AF_ETH);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13;
GPIO_Init(GPIOB, &GPIO_InitStructure);
GPIO_PinAFConfig(GPIOB, GPIO_PinSource11, GPIO_AF_ETH);
GPIO_PinAFConfig(GPIOB, GPIO_PinSource12, GPIO_AF_ETH);
GPIO_PinAFConfig(GPIOB, GPIO_PinSource13, GPIO_AF_ETH);
/* for RMII mode you have to set the system clock frequency to 100MHz,
you can do this in system_stm32f2xx.c file */
/* Enable SYSCFG clock */
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
/* Configure MCO (PA8) */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
GPIO_Init(GPIOA, &GPIO_InitStructure);
/* Output PLL clock divided by 2 (50MHz) on MCO pin (PA8) to clock the PHY */
RCC_MCO1Config(RCC_MCO1Source_PLLCLK, RCC_MCO1Div_2);
SYSCFG_ETH_MediaInterfaceConfig(SYSCFG_ETH_MediaInterface_RMII);
/* Ethernet pins configuration ************************************************/
/*
ETH_MDIO -------------------------> PA2
ETH_MDC --------------------------> PC1
ETH_MII_RX_CLK/ETH_RMII_REF_CLK---> PA1
ETH_MII_RX_DV/ETH_RMII_CRS_DV ----> PA7
ETH_MII_RXD0/ETH_RMII_RXD0 -------> PC4
ETH_MII_RXD1/ETH_RMII_RXD1 -------> PC5
ETH_MII_TX_EN/ETH_RMII_TX_EN -----> PB11
ETH_MII_TXD0/ETH_RMII_TXD0 -------> PB12
ETH_MII_TXD1/ETH_RMII_TXD1 -------> PB13
*/
/* Configure PC1, PC2, PC3, PC4 and PC5 */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 |GPIO_Pin_4 | GPIO_Pin_5;
GPIO_Init(GPIOC, &GPIO_InitStructure);
GPIO_PinAFConfig(GPIOC, GPIO_PinSource1, GPIO_AF_ETH);
GPIO_PinAFConfig(GPIOC, GPIO_PinSource4, GPIO_AF_ETH);
GPIO_PinAFConfig(GPIOC, GPIO_PinSource5, GPIO_AF_ETH);
/* Configure PB11, PB14 and PB13 */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13;
GPIO_Init(GPIOB, &GPIO_InitStructure);
GPIO_PinAFConfig(GPIOB, GPIO_PinSource11, GPIO_AF_ETH);
GPIO_PinAFConfig(GPIOB, GPIO_PinSource12, GPIO_AF_ETH);
GPIO_PinAFConfig(GPIOB, GPIO_PinSource13, GPIO_AF_ETH);
/* Configure PA1, PA2 and PA7 */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1|GPIO_Pin_2 | GPIO_Pin_7;
GPIO_Init(GPIOA, &GPIO_InitStructure);
GPIO_PinAFConfig(GPIOA, GPIO_PinSource1, GPIO_AF_ETH);
GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_ETH);
GPIO_WriteBit(GPIOA,GPIO_Pin_7,Bit_RESET);
GPIO_WriteBit(GPIOB,GPIO_Pin_0,Bit_RESET);
i=100000;
while(i--);
GPIO_WriteBit(GPIOB,GPIO_Pin_0,Bit_SET);
GPIO_WriteBit(GPIOA,GPIO_Pin_7,Bit_SET);
GPIO_PinAFConfig(GPIOA, GPIO_PinSource7, GPIO_AF_ETH);
}
void rt_hw_stm32_eth_init(void)
{
RCC_Configuration();
GPIO_Configuration();
NVIC_Configuration();
// OUI 00-80-E1 STMICROELECTRONICS
stm32_eth_device.dev_addr[0] = 0x00;
stm32_eth_device.dev_addr[1] = 0x60;
stm32_eth_device.dev_addr[2] = 0x6E;
stm32_eth_device.dev_addr[3] = 0x11;
stm32_eth_device.dev_addr[4] = 0x22;
stm32_eth_device.dev_addr[5] = 0x33;
stm32_eth_device.dev_addr[1] = 0x80;
stm32_eth_device.dev_addr[2] = 0xE1;
// generate MAC addr from 96bit unique ID (only for test)
stm32_eth_device.dev_addr[3] = *(rt_uint8_t*)(0x1FFF7A10+7);
stm32_eth_device.dev_addr[4] = *(rt_uint8_t*)(0x1FFF7A10+8);
stm32_eth_device.dev_addr[5] = *(rt_uint8_t*)(0x1FFF7A10+9);
stm32_eth_device.parent.parent.init = rt_stm32_eth_init;
stm32_eth_device.parent.parent.open = rt_stm32_eth_open;

536
bsp/stm32f20x/system_stm32f2xx_eth_rmii_mco.c Normal file
View File

@ -0,0 +1,536 @@
/**
******************************************************************************
* @file system_stm32f2xx.c
* @author MCD Application Team
* @version V1.0.0
* @date 18-April-2011
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
* This file contains the system clock configuration for STM32F2xx devices,
* and is generated by the clock configuration tool
* "STM32f2xx_Clock_Configuration_V1.0.0.xls"
*
* 1. This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
* and Divider factors, AHB/APBx prescalers and Flash settings),
* depending on the configuration made in the clock xls tool.
* This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32f2xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
* 2. After each device reset the HSI (16 MHz) is used as system clock source.
* Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to
* configure the system clock before to branch to main program.
*
* 3. If the system clock source selected by user fails to startup, the SystemInit()
* function will do nothing and HSI still used as system clock source. User can
* add some code to deal with this issue inside the SetSysClock() function.
*
* 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define
* in "stm32f2xx.h" file. When HSE is used as system clock source, directly or
* through PLL, and you are using different crystal you have to adapt the HSE
* value to your own configuration.
*
* 5. This file configures the system clock as follows:
*=============================================================================
*=============================================================================
* Supported STM32F2xx device revision | Rev B and Y
*-----------------------------------------------------------------------------
* System Clock source | PLL (HSE)
*-----------------------------------------------------------------------------
* SYSCLK(Hz) | 100000000
*-----------------------------------------------------------------------------
* HCLK(Hz) | 100000000
*-----------------------------------------------------------------------------
* AHB Prescaler | 1
*-----------------------------------------------------------------------------
* APB1 Prescaler | 4
*-----------------------------------------------------------------------------
* APB2 Prescaler | 2
*-----------------------------------------------------------------------------
* HSE Frequency(Hz) | 25000000
*-----------------------------------------------------------------------------
* PLL_M | 25
*-----------------------------------------------------------------------------
* PLL_N | 200
*-----------------------------------------------------------------------------
* PLL_P | 2
*-----------------------------------------------------------------------------
* PLL_Q | 5
*-----------------------------------------------------------------------------
* PLLI2S_N | NA
*-----------------------------------------------------------------------------
* PLLI2S_R | NA
*-----------------------------------------------------------------------------
* I2S input clock | NA
*-----------------------------------------------------------------------------
* VDD(V) | 3.3
*-----------------------------------------------------------------------------
* Flash Latency(WS) | 3
*-----------------------------------------------------------------------------
* Prefetch Buffer | ON
*-----------------------------------------------------------------------------
* Instruction cache | ON
*-----------------------------------------------------------------------------
* Data cache | ON
*-----------------------------------------------------------------------------
* Require 48MHz for USB OTG FS, | Enabled
* SDIO and RNG clock |
*-----------------------------------------------------------------------------
*=============================================================================
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f2xx_system
* @{
*/
/** @addtogroup STM32F2xx_System_Private_Includes
* @{
*/
#include "stm32f2xx.h"
/**
* @}
*/
/** @addtogroup STM32F2xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F2xx_System_Private_Defines
* @{
*/
/*!< Uncomment the following line if you need to use external SRAM mounted
on STM322xG_EVAL board as data memory */
/* #define DATA_IN_ExtSRAM */
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
#define PLL_M 4
#define PLL_N 64
/* SYSCLK = PLL_VCO / PLL_P */
#define PLL_P 4
/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */
#define PLL_Q 5
/**
* @}
*/
/** @addtogroup STM32F2xx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F2xx_System_Private_Variables
* @{
*/
uint32_t SystemCoreClock = 100000000;
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
/**
* @}
*/
/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes
* @{
*/
static void SetSysClock(void);
#ifdef DATA_IN_ExtSRAM
static void SystemInit_ExtMemCtl(void);
#endif /* DATA_IN_ExtSRAM */
/**
* @}
*/
/** @addtogroup STM32F2xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system
* Initialize the Embedded Flash Interface, the PLL and update the
* SystemFrequency variable.
* @param None
* @retval None
*/
void SystemInit(void)
{
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001;
/* Reset CFGR register */
RCC->CFGR = 0x00000000;
/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFF;
/* Reset PLLCFGR register */
RCC->PLLCFGR = 0x24003010;
/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
/* Disable all interrupts */
RCC->CIR = 0x00000000;
#ifdef DATA_IN_ExtSRAM
SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM */
/* Configure the System clock source, PLL Multiplier and Divider factors,
AHB/APBx prescalers and Flash settings ----------------------------------*/
SetSysClock();
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
*
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
*
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
*
* (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value
* 16 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value
* 25 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may
* have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
*
* @param None
* @retval None
*/
void SystemCoreClockUpdate(void)
{
uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
switch (tmp)
{
case 0x00: /* HSI used as system clock source */
SystemCoreClock = HSI_VALUE;
break;
case 0x04: /* HSE used as system clock source */
SystemCoreClock = HSE_VALUE;
break;
case 0x08: /* PLL used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
SYSCLK = PLL_VCO / PLL_P
*/
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
if (pllsource != 0)
{
/* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
}
else
{
/* HSI used as PLL clock source */
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
}
pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
SystemCoreClock = pllvco/pllp;
break;
default:
SystemCoreClock = HSI_VALUE;
break;
}
/* Compute HCLK frequency --------------------------------------------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
/* HCLK frequency */
SystemCoreClock >>= tmp;
}
/**
* @brief Configures the System clock source, PLL Multiplier and Divider factors,
* AHB/APBx prescalers and Flash settings
* @Note This function should be called only once the RCC clock configuration
* is reset to the default reset state (done in SystemInit() function).
* @param None
* @retval None
*/
static void SetSysClock(void)
{
/******************************************************************************/
/* PLL (clocked by HSE) used as System clock source */
/******************************************************************************/
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
/* Enable HSE */
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CR & RCC_CR_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CR & RCC_CR_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
if (HSEStatus == (uint32_t)0x01)
{
/* HCLK = SYSCLK / 1*/
RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
/* PCLK2 = HCLK / 2*/
RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
/* PCLK1 = HCLK / 4*/
RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
/* Configure the main PLL */
RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
(RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
/* Enable the main PLL */
RCC->CR |= RCC_CR_PLLON;
/* Wait till the main PLL is ready */
while((RCC->CR & RCC_CR_PLLRDY) == 0)
{
}
/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS;
/* Select the main PLL as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
RCC->CFGR |= RCC_CFGR_SW_PLL;
/* Wait till the main PLL is used as system clock source */
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
{
}
}
else
{ /* If HSE fails to start-up, the application will have wrong clock
configuration. User can add here some code to deal with this error */
}
}
/**
* @brief Setup the external memory controller. Called in startup_stm32f2xx.s
* before jump to __main
* @param None
* @retval None
*/
#ifdef DATA_IN_ExtSRAM
/**
* @brief Setup the external memory controller.
* Called in startup_stm32f2xx.s before jump to main.
* This function configures the external SRAM mounted on STM322xG_EVAL board
* This SRAM will be used as program data memory (including heap and stack).
* @param None
* @retval None
*/
void SystemInit_ExtMemCtl(void)
{
/*-- GPIOs Configuration -----------------------------------------------------*/
/*
+-------------------+--------------------+------------------+------------------+
+ SRAM pins assignment +
+-------------------+--------------------+------------------+------------------+
| PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 |
| PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 |
| PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 |
| PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 |
| PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 |
| PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 |
| PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 |
| PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+
| PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 |
| PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 |
| PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+
+-------------------+--------------------+
*/
/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
RCC->AHB1ENR = 0x00000078;
/* Connect PDx pins to FSMC Alternate function */
GPIOD->AFR[0] = 0x00cc00cc;
GPIOD->AFR[1] = 0xcc0ccccc;
/* Configure PDx pins in Alternate function mode */
GPIOD->MODER = 0xa2aa0a0a;
/* Configure PDx pins speed to 100 MHz */
GPIOD->OSPEEDR = 0xf3ff0f0f;
/* Configure PDx pins Output type to push-pull */
GPIOD->OTYPER = 0x00000000;
/* No pull-up, pull-down for PDx pins */
GPIOD->PUPDR = 0x00000000;
/* Connect PEx pins to FSMC Alternate function */
GPIOE->AFR[0] = 0xc00000cc;
GPIOE->AFR[1] = 0xcccccccc;
/* Configure PEx pins in Alternate function mode */
GPIOE->MODER = 0xaaaa800a;
/* Configure PEx pins speed to 100 MHz */
GPIOE->OSPEEDR = 0xffffc00f;
/* Configure PEx pins Output type to push-pull */
GPIOE->OTYPER = 0x00000000;
/* No pull-up, pull-down for PEx pins */
GPIOE->PUPDR = 0x00000000;
/* Connect PFx pins to FSMC Alternate function */
GPIOF->AFR[0] = 0x00cccccc;
GPIOF->AFR[1] = 0xcccc0000;
/* Configure PFx pins in Alternate function mode */
GPIOF->MODER = 0xaa000aaa;
/* Configure PFx pins speed to 100 MHz */
GPIOF->OSPEEDR = 0xff000fff;
/* Configure PFx pins Output type to push-pull */
GPIOF->OTYPER = 0x00000000;
/* No pull-up, pull-down for PFx pins */
GPIOF->PUPDR = 0x00000000;
/* Connect PGx pins to FSMC Alternate function */
GPIOG->AFR[0] = 0x00cccccc;
GPIOG->AFR[1] = 0x000000c0;
/* Configure PGx pins in Alternate function mode */
GPIOG->MODER = 0x00080aaa;
/* Configure PGx pins speed to 100 MHz */
GPIOG->OSPEEDR = 0x000c0fff;
/* Configure PGx pins Output type to push-pull */
GPIOG->OTYPER = 0x00000000;
/* No pull-up, pull-down for PGx pins */
GPIOG->PUPDR = 0x00000000;
/*-- FSMC Configuration ------------------------------------------------------*/
/* Enable the FSMC interface clock */
RCC->AHB3ENR = 0x00000001;
/* Configure and enable Bank1_SRAM2 */
FSMC_Bank1->BTCR[2] = 0x00001015;
FSMC_Bank1->BTCR[3] = 0x00010400;
FSMC_Bank1E->BWTR[2] = 0x0fffffff;
/*
Bank1_SRAM2 is configured as follow:
p.FSMC_AddressSetupTime = 0;
p.FSMC_AddressHoldTime = 0;
p.FSMC_DataSetupTime = 4;
p.FSMC_BusTurnAroundDuration = 1;
p.FSMC_CLKDivision = 0;
p.FSMC_DataLatency = 0;
p.FSMC_AccessMode = FSMC_AccessMode_A;
FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM;
FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
*/
}
#endif /* DATA_IN_ExtSRAM */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

86
bsp/stm32f20x/usart.c
View File

@ -45,6 +45,17 @@ struct stm32_serial_device uart1 =
struct rt_device uart1_device;
#endif
#ifdef RT_USING_UART6
struct stm32_serial_int_rx uart6_int_rx;
struct stm32_serial_device uart6 =
{
USART6,
&uart6_int_rx,
RT_NULL
};
struct rt_device uart6_device;
#endif
#ifdef RT_USING_UART2
struct stm32_serial_int_rx uart2_int_rx;
struct stm32_serial_device uart2 =
@ -103,6 +114,14 @@ struct rt_device uart3_device;
#define UART3_TX_DMA DMA1_Channel2
#define UART3_RX_DMA DMA1_Channel3
/* USART6_REMAP = 0 */
#define UART6_GPIO_TX GPIO_Pin_6
#define UART6_GPIO_RX GPIO_Pin_7
#define UART6_GPIO GPIOC
#define RCC_APBPeriph_UART6 RCC_APB2Periph_USART6
//#define UART1_TX_DMA DMA1_Channel?
//#define UART1_RX_DMA DMA1_Channel?
static void RCC_Configuration(void)
{
#ifdef RT_USING_UART1
@ -110,6 +129,12 @@ static void RCC_Configuration(void)
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE);
RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
#endif
#ifdef RT_USING_UART6
/* Enable USART6 and GPIOC clocks */
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOC, ENABLE);
RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART6, ENABLE);
#endif
}
static void GPIO_Configuration(void)
@ -128,6 +153,19 @@ static void GPIO_Configuration(void)
GPIO_PinAFConfig(GPIOA, GPIO_PinSource9, GPIO_AF_USART1);
GPIO_PinAFConfig(GPIOA, GPIO_PinSource10, GPIO_AF_USART1);
#endif
#ifdef RT_USING_UART6
GPIO_InitStruct.GPIO_Mode=GPIO_Mode_AF;
GPIO_InitStruct.GPIO_Speed=GPIO_Speed_50MHz;
GPIO_InitStruct.GPIO_OType=GPIO_OType_PP;
GPIO_InitStruct.GPIO_PuPd=GPIO_PuPd_UP;
GPIO_InitStruct.GPIO_Pin=UART6_GPIO_TX|UART6_GPIO_RX;
GPIO_Init(UART6_GPIO,&GPIO_InitStruct);
GPIO_PinAFConfig(UART6_GPIO, GPIO_PinSource6, GPIO_AF_USART6);
GPIO_PinAFConfig(UART6_GPIO, GPIO_PinSource7, GPIO_AF_USART6);
#endif
}
static void NVIC_Configuration(void)
@ -142,6 +180,15 @@ static void NVIC_Configuration(void)
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
#endif
#ifdef RT_USING_UART6
/* Enable the USART1 Interrupt */
NVIC_InitStructure.NVIC_IRQChannel = USART6_IRQn;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
#endif
}
/*
@ -181,8 +228,33 @@ void rt_hw_usart_init()
USART_Cmd(USART1, ENABLE);
USART_ClearFlag(USART1,USART_FLAG_TXE);
#endif
/* uart init */
#ifdef RT_USING_UART6
USART_DeInit(USART6);
USART_InitStructure.USART_BaudRate = 115200;
USART_InitStructure.USART_WordLength = USART_WordLength_8b;
USART_InitStructure.USART_StopBits = USART_StopBits_1;
USART_InitStructure.USART_Parity = USART_Parity_No ;
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
USART_Init(USART6, &USART_InitStructure);
/* register uart1 */
rt_hw_serial_register(&uart6_device, "uart6",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
&uart6);
/* enable interrupt */
USART_ITConfig(USART6, USART_IT_RXNE, ENABLE);
/* Enable USART6 */
USART_Cmd(USART6, ENABLE);
USART_ClearFlag(USART6,USART_FLAG_TXE);
#endif
}
#ifdef RT_USING_UART1
void USART1_IRQHandler()
{
/* enter interrupt */
@ -193,3 +265,17 @@ void USART1_IRQHandler()
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#ifdef RT_USING_UART6
void USART6_IRQHandler()
{
/* enter interrupt */
rt_interrupt_enter();
rt_hw_serial_isr(&uart6_device);
/* leave interrupt */
rt_interrupt_leave();
}
#endif