diff --git a/bsp/stm32f20x/stm32f2xx_eth.c b/bsp/stm32f20x/stm32f2xx_eth.c index 4bfca3eb74..8a454586dc 100644 --- a/bsp/stm32f20x/stm32f2xx_eth.c +++ b/bsp/stm32f20x/stm32f2xx_eth.c @@ -6,7 +6,7 @@ * @date 10/21/2010 * @brief This file provides all the ETH firmware functions for STM32F2xx devices. * This driver is based on V1.1.0 of "stm32_eth.c" driver, and updated - * to support new feature added in STM32F2xx devices (Enhanced DMA descriptors) + * to support new feature added in STM32F2xx devices (Enhanced DMA descriptors) ****************************************************************************** * @copy * @@ -18,12 +18,24 @@ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * *

© COPYRIGHT 2010 STMicroelectronics

- */ + */ + +/* + * Change Logs: + * Date Author Notes + * 2011-07-22 aozima first implementation(stm32f207,dp83848,rmii,MCO) +*/ /* Includes ------------------------------------------------------------------*/ #include "stm32f2xx_eth.h" #include "stm32f2xx_rcc.h" +/* PHY configuration section **************************************************/ +/* PHY Reset delay */ +#define PHY_RESET_DELAY ((uint32_t)0x000FFFFF) +/* PHY Configuration delay */ +#define PHY_CONFIG_DELAY ((uint32_t)0x00FFFFFF) + /** @addtogroup STM32F2XX_ETH_Driver * @brief ETH driver modules @@ -32,16 +44,16 @@ /** @defgroup ETH_Private_TypesDefinitions * @{ - */ + */ /** * @} - */ + */ -#define DP83848_PHY_ADDRESS 0x01 /* Relative to STM3220F-EVAL Board */ +#define DP83848_PHY_ADDRESS 0x1F /* Relative to STM3220F-EVAL Board */ /** @defgroup ETH_Private_Defines * @{ - */ + */ /* Global pointers on Tx and Rx descriptor used to track transmit and receive descriptors */ ETH_DMADESCTypeDef *DMATxDescToSet; ETH_DMADESCTypeDef *DMARxDescToGet; @@ -54,10 +66,10 @@ ETH_DMADESCTypeDef *DMAPTPRxDescToGet; #define ETH_MAC_ADDR_LBASE (ETH_MAC_BASE + 0x44) /* ETHERNET MAC address low offset */ /* ETHERNET MACMIIAR register Mask */ -#define MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3) +#define MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3) /* ETHERNET MACCR register Mask */ -#define MACCR_CLEAR_MASK ((uint32_t)0xFF20810F) +#define MACCR_CLEAR_MASK ((uint32_t)0xFF20810F) /* ETHERNET MACFCR register Mask */ #define MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41) @@ -92,26 +104,26 @@ ETH_DMADESCTypeDef *DMAPTPRxDescToGet; /** @defgroup ETH_Private_Macros * @{ - */ + */ /** * @} */ /** @defgroup ETH_Private_Variables * @{ - */ + */ /** * @} */ /** @defgroup ETH_Private_FunctionPrototypes * @{ - */ - + */ + #ifndef USE_Delay static void ETH_Delay(__IO uint32_t nCount); #endif /* USE_Delay*/ - + /** * @} */ @@ -122,7 +134,7 @@ static void ETH_Delay(__IO uint32_t nCount); /** * @brief Deinitializes the ETHERNET peripheral registers to their default reset values. - * @param None + * @param None * @retval None */ void ETH_DeInit(void) @@ -136,9 +148,9 @@ void ETH_DeInit(void) * parameters in the ETH_InitStruct . * @param ETH_InitStruct: pointer to a ETH_InitTypeDef structure that contains * the configuration information for the specified ETHERNET peripheral. - * @param PHYAddress: external PHY address + * @param PHYAddress: external PHY address * @retval ETH_ERROR: Ethernet initialization failed - * ETH_SUCCESS: Ethernet successfully initialized + * ETH_SUCCESS: Ethernet successfully initialized */ uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress) { @@ -147,8 +159,9 @@ uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress) RCC_ClocksTypeDef rcc_clocks; uint32_t hclk = 60000000; __IO uint32_t timeout = 0; + uint16_t RegRead; /* Check the parameters */ - /* MAC --------------------------*/ + /* MAC --------------------------*/ assert_param(IS_ETH_AUTONEGOTIATION(ETH_InitStruct->ETH_AutoNegotiation)); assert_param(IS_ETH_WATCHDOG(ETH_InitStruct->ETH_Watchdog)); assert_param(IS_ETH_JABBER(ETH_InitStruct->ETH_Jabber)); @@ -168,8 +181,8 @@ uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress) assert_param(IS_ETH_CONTROL_FRAMES(ETH_InitStruct->ETH_PassControlFrames)); assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(ETH_InitStruct->ETH_BroadcastFramesReception)); assert_param(IS_ETH_DESTINATION_ADDR_FILTER(ETH_InitStruct->ETH_DestinationAddrFilter)); - assert_param(IS_ETH_PROMISCUOUS_MODE(ETH_InitStruct->ETH_PromiscuousMode)); - assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(ETH_InitStruct->ETH_MulticastFramesFilter)); + assert_param(IS_ETH_PROMISCIOUS_MODE(ETH_InitStruct->ETH_PromiscuousMode)); + assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(ETH_InitStruct->ETH_MulticastFramesFilter)); assert_param(IS_ETH_UNICAST_FRAMES_FILTER(ETH_InitStruct->ETH_UnicastFramesFilter)); assert_param(IS_ETH_PAUSE_TIME(ETH_InitStruct->ETH_PauseTime)); assert_param(IS_ETH_ZEROQUANTA_PAUSE(ETH_InitStruct->ETH_ZeroQuantaPause)); @@ -192,10 +205,10 @@ uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress) assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(ETH_InitStruct->ETH_AddressAlignedBeats)); assert_param(IS_ETH_FIXED_BURST(ETH_InitStruct->ETH_FixedBurst)); assert_param(IS_ETH_RXDMA_BURST_LENGTH(ETH_InitStruct->ETH_RxDMABurstLength)); - assert_param(IS_ETH_TXDMA_BURST_LENGTH(ETH_InitStruct->ETH_TxDMABurstLength)); - assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(ETH_InitStruct->ETH_DescriptorSkipLength)); - assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(ETH_InitStruct->ETH_DMAArbitration)); - /*-------------------------------- MAC Config ------------------------------*/ + assert_param(IS_ETH_TXDMA_BURST_LENGTH(ETH_InitStruct->ETH_TxDMABurstLength)); + assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(ETH_InitStruct->ETH_DescriptorSkipLength)); + assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(ETH_InitStruct->ETH_DMAArbitration)); + /*-------------------------------- MAC Config ------------------------------*/ /*---------------------- ETHERNET MACMIIAR Configuration -------------------*/ /* Get the ETHERNET MACMIIAR value */ tmpreg = ETH->MACMIIAR; @@ -212,89 +225,100 @@ uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress) } else if((hclk >= 35000000)&&(hclk < 60000000)) { - /* CSR Clock Range between 35-60 MHz */ - tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div26; - } - else /* ((hclk >= 60000000)&&(hclk <= 72000000)) */ - { - /* CSR Clock Range between 60-72 MHz */ - tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42; + /* CSR Clock Range between 35-60 MHz */ + tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div26; } + else if((hclk >= 60000000)&&(hclk < 100000000)) + { + /* CSR Clock Range between 60-100 MHz */ + tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42; + } + else /* ((hclk >= 100000000)&&(hclk <= 120000000)) */ + { + /* CSR Clock Range between 100-120 MHz */ + tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div62; + } + /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */ - ETH->MACMIIAR = (uint32_t)tmpreg; + ETH->MACMIIAR = (uint32_t)tmpreg; /*-------------------- PHY initialization and configuration ----------------*/ + + /* Put the PHY in reset mode */ if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_Reset))) { /* Return ERROR in case of write timeout */ return ETH_ERROR; } - /* Delay to assure PHY reset */ - _eth_delay_(PHY_ResetDelay); - - + _eth_delay_(PHY_RESET_DELAY); + if(ETH_InitStruct->ETH_AutoNegotiation != ETH_AutoNegotiation_Disable) - { - /* We wait for linked satus... */ + { + /* We wait for linked status... */ do { + RegRead=ETH_ReadPHYRegister(PHYAddress, PHY_BSR); timeout++; - } while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_Linked_Status) && (timeout < PHY_READ_TO)); + } while (!(RegRead & PHY_Linked_Status) && (timeout < PHY_READ_TO*5)); + /* Return ERROR in case of timeout */ if(timeout == PHY_READ_TO) { return ETH_ERROR; } + /* Reset Timeout counter */ timeout = 0; - /* Enable Auto-Negotiation */ if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_AutoNegotiation))) { /* Return ERROR in case of write timeout */ return ETH_ERROR; } - - /* Wait until the autonegotiation will be completed */ + + /* Wait until the auto-negotiation will be completed */ do { timeout++; - } while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_AutoNego_Complete) && (timeout < (uint32_t)PHY_READ_TO)); + } while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_AutoNego_Complete) && (timeout < (uint32_t)PHY_READ_TO)); + /* Return ERROR in case of timeout */ if(timeout == PHY_READ_TO) { return ETH_ERROR; } + /* Reset Timeout counter */ timeout = 0; - - /* Read the result of the autonegotiation */ - RegValue = ETH_ReadPHYRegister(PHYAddress, PHY_SR); - - /* Configure the MAC with the Duplex Mode fixed by the autonegotiation process */ - if((RegValue & PHY_Duplex_Status) != (uint32_t)RESET) + RegValue = ETH_ReadPHYRegister(PHYAddress, 17); + + /* 100 FDX*/ + if((RegValue & 0x8000) != (uint32_t)RESET) { /* Set Ethernet duplex mode to FullDuplex following the autonegotiation */ ETH_InitStruct->ETH_Mode = ETH_Mode_FullDuplex; - + ETH_InitStruct->ETH_Speed = ETH_Speed_100M; + } - else + else if((RegValue & 0x4000) != (uint32_t)RESET)//100 HDX { /* Set Ethernet duplex mode to HalfDuplex following the autonegotiation */ - ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex; + ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex; + ETH_InitStruct->ETH_Speed = ETH_Speed_100M; } - /* Configure the MAC with the speed fixed by the autonegotiation process */ - if(RegValue & PHY_Speed_Status) - { - /* Set Ethernet speed to 10M following the autonegotiation */ - ETH_InitStruct->ETH_Speed = ETH_Speed_10M; + else if((RegValue & 0x2000) != (uint32_t)RESET)//10 FDX + { + /* Set Ethernet duplex mode to HalfDuplex following the autonegotiation */ + ETH_InitStruct->ETH_Mode = ETH_Mode_FullDuplex; + ETH_InitStruct->ETH_Speed = ETH_Speed_10M; + } + else if((RegValue & 0x1000) != (uint32_t)RESET)//10 HDX + { + /* Set Ethernet duplex mode to HalfDuplex following the autonegotiation */ + ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex; + ETH_InitStruct->ETH_Speed = ETH_Speed_10M; } - else - { - /* Set Ethernet speed to 100M following the autonegotiation */ - ETH_InitStruct->ETH_Speed = ETH_Speed_100M; - } } else { @@ -305,44 +329,44 @@ uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress) return ETH_ERROR; } /* Delay to assure PHY configuration */ - _eth_delay_(PHY_ConfigDelay); - + _eth_delay_(PHY_CONFIG_DELAY); + } /*------------------------ ETHERNET MACCR Configuration --------------------*/ - /* Get the ETHERNET MACCR value */ + /* Get the ETHERNET MACCR value */ tmpreg = ETH->MACCR; /* Clear WD, PCE, PS, TE and RE bits */ tmpreg &= MACCR_CLEAR_MASK; /* Set the WD bit according to ETH_Watchdog value */ /* Set the JD: bit according to ETH_Jabber value */ - /* Set the IFG bit according to ETH_InterFrameGap value */ - /* Set the DCRS bit according to ETH_CarrierSense value */ - /* Set the FES bit according to ETH_Speed value */ - /* Set the DO bit according to ETH_ReceiveOwn value */ - /* Set the LM bit according to ETH_LoopbackMode value */ - /* Set the DM bit according to ETH_Mode value */ - /* Set the IPCO bit according to ETH_ChecksumOffload value */ - /* Set the DR bit according to ETH_RetryTransmission value */ - /* Set the ACS bit according to ETH_AutomaticPadCRCStrip value */ - /* Set the BL bit according to ETH_BackOffLimit value */ - /* Set the DC bit according to ETH_DeferralCheck value */ - tmpreg |= (uint32_t)(ETH_InitStruct->ETH_Watchdog | - ETH_InitStruct->ETH_Jabber | + /* Set the IFG bit according to ETH_InterFrameGap value */ + /* Set the DCRS bit according to ETH_CarrierSense value */ + /* Set the FES bit according to ETH_Speed value */ + /* Set the DO bit according to ETH_ReceiveOwn value */ + /* Set the LM bit according to ETH_LoopbackMode value */ + /* Set the DM bit according to ETH_Mode value */ + /* Set the IPCO bit according to ETH_ChecksumOffload value */ + /* Set the DR bit according to ETH_RetryTransmission value */ + /* Set the ACS bit according to ETH_AutomaticPadCRCStrip value */ + /* Set the BL bit according to ETH_BackOffLimit value */ + /* Set the DC bit according to ETH_DeferralCheck value */ + tmpreg |= (uint32_t)(ETH_InitStruct->ETH_Watchdog | + ETH_InitStruct->ETH_Jabber | ETH_InitStruct->ETH_InterFrameGap | ETH_InitStruct->ETH_CarrierSense | - ETH_InitStruct->ETH_Speed | + ETH_InitStruct->ETH_Speed | ETH_InitStruct->ETH_ReceiveOwn | ETH_InitStruct->ETH_LoopbackMode | - ETH_InitStruct->ETH_Mode | - ETH_InitStruct->ETH_ChecksumOffload | - ETH_InitStruct->ETH_RetryTransmission | - ETH_InitStruct->ETH_AutomaticPadCRCStrip | - ETH_InitStruct->ETH_BackOffLimit | + ETH_InitStruct->ETH_Mode | + ETH_InitStruct->ETH_ChecksumOffload | + ETH_InitStruct->ETH_RetryTransmission | + ETH_InitStruct->ETH_AutomaticPadCRCStrip | + ETH_InitStruct->ETH_BackOffLimit | ETH_InitStruct->ETH_DeferralCheck); /* Write to ETHERNET MACCR */ ETH->MACCR = (uint32_t)tmpreg; - - /*----------------------- ETHERNET MACFFR Configuration --------------------*/ + + /*----------------------- ETHERNET MACFFR Configuration --------------------*/ /* Set the RA bit according to ETH_ReceiveAll value */ /* Set the SAF and SAIF bits according to ETH_SourceAddrFilter value */ /* Set the PCF bit according to ETH_PassControlFrames value */ @@ -351,53 +375,53 @@ uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress) /* Set the PR bit according to ETH_PromiscuousMode value */ /* Set the PM, HMC and HPF bits according to ETH_MulticastFramesFilter value */ /* Set the HUC and HPF bits according to ETH_UnicastFramesFilter value */ - /* Write to ETHERNET MACFFR */ - ETH->MACFFR = (uint32_t)(ETH_InitStruct->ETH_ReceiveAll | + /* Write to ETHERNET MACFFR */ + ETH->MACFFR = (uint32_t)(ETH_InitStruct->ETH_ReceiveAll | ETH_InitStruct->ETH_SourceAddrFilter | ETH_InitStruct->ETH_PassControlFrames | - ETH_InitStruct->ETH_BroadcastFramesReception | + ETH_InitStruct->ETH_BroadcastFramesReception | ETH_InitStruct->ETH_DestinationAddrFilter | ETH_InitStruct->ETH_PromiscuousMode | ETH_InitStruct->ETH_MulticastFramesFilter | - ETH_InitStruct->ETH_UnicastFramesFilter); + ETH_InitStruct->ETH_UnicastFramesFilter); /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/ /* Write to ETHERNET MACHTHR */ ETH->MACHTHR = (uint32_t)ETH_InitStruct->ETH_HashTableHigh; /* Write to ETHERNET MACHTLR */ ETH->MACHTLR = (uint32_t)ETH_InitStruct->ETH_HashTableLow; /*----------------------- ETHERNET MACFCR Configuration --------------------*/ - /* Get the ETHERNET MACFCR value */ + /* Get the ETHERNET MACFCR value */ tmpreg = ETH->MACFCR; /* Clear xx bits */ tmpreg &= MACFCR_CLEAR_MASK; - + /* Set the PT bit according to ETH_PauseTime value */ /* Set the DZPQ bit according to ETH_ZeroQuantaPause value */ /* Set the PLT bit according to ETH_PauseLowThreshold value */ /* Set the UP bit according to ETH_UnicastPauseFrameDetect value */ /* Set the RFE bit according to ETH_ReceiveFlowControl value */ - /* Set the TFE bit according to ETH_TransmitFlowControl value */ - tmpreg |= (uint32_t)((ETH_InitStruct->ETH_PauseTime << 16) | + /* Set the TFE bit according to ETH_TransmitFlowControl value */ + tmpreg |= (uint32_t)((ETH_InitStruct->ETH_PauseTime << 16) | ETH_InitStruct->ETH_ZeroQuantaPause | ETH_InitStruct->ETH_PauseLowThreshold | - ETH_InitStruct->ETH_UnicastPauseFrameDetect | + ETH_InitStruct->ETH_UnicastPauseFrameDetect | ETH_InitStruct->ETH_ReceiveFlowControl | - ETH_InitStruct->ETH_TransmitFlowControl); + ETH_InitStruct->ETH_TransmitFlowControl); /* Write to ETHERNET MACFCR */ ETH->MACFCR = (uint32_t)tmpreg; /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/ /* Set the ETV bit according to ETH_VLANTagComparison value */ - /* Set the VL bit according to ETH_VLANTagIdentifier value */ - ETH->MACVLANTR = (uint32_t)(ETH_InitStruct->ETH_VLANTagComparison | - ETH_InitStruct->ETH_VLANTagIdentifier); - + /* Set the VL bit according to ETH_VLANTagIdentifier value */ + ETH->MACVLANTR = (uint32_t)(ETH_InitStruct->ETH_VLANTagComparison | + ETH_InitStruct->ETH_VLANTagIdentifier); + /*-------------------------------- DMA Config ------------------------------*/ /*----------------------- ETHERNET DMAOMR Configuration --------------------*/ - /* Get the ETHERNET DMAOMR value */ + /* Get the ETHERNET DMAOMR value */ tmpreg = ETH->DMAOMR; /* Clear xx bits */ tmpreg &= DMAOMR_CLEAR_MASK; - + /* Set the DT bit according to ETH_DropTCPIPChecksumErrorFrame value */ /* Set the RSF bit according to ETH_ReceiveStoreForward value */ /* Set the DFF bit according to ETH_FlushReceivedFrame value */ @@ -407,118 +431,157 @@ uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress) /* Set the FUF bit according to ETH_ForwardUndersizedGoodFrames value */ /* Set the RTC bit according to ETH_ReceiveThresholdControl value */ /* Set the OSF bit according to ETH_SecondFrameOperate value */ - tmpreg |= (uint32_t)(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame | + tmpreg |= (uint32_t)(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame | ETH_InitStruct->ETH_ReceiveStoreForward | ETH_InitStruct->ETH_FlushReceivedFrame | - ETH_InitStruct->ETH_TransmitStoreForward | + ETH_InitStruct->ETH_TransmitStoreForward | ETH_InitStruct->ETH_TransmitThresholdControl | ETH_InitStruct->ETH_ForwardErrorFrames | ETH_InitStruct->ETH_ForwardUndersizedGoodFrames | - ETH_InitStruct->ETH_ReceiveThresholdControl | - ETH_InitStruct->ETH_SecondFrameOperate); + ETH_InitStruct->ETH_ReceiveThresholdControl | + ETH_InitStruct->ETH_SecondFrameOperate); /* Write to ETHERNET DMAOMR */ ETH->DMAOMR = (uint32_t)tmpreg; - - /*----------------------- ETHERNET DMABMR Configuration --------------------*/ + + /*----------------------- ETHERNET DMABMR Configuration --------------------*/ /* Set the AAL bit according to ETH_AddressAlignedBeats value */ /* Set the FB bit according to ETH_FixedBurst value */ /* Set the RPBL and 4*PBL bits according to ETH_RxDMABurstLength value */ /* Set the PBL and 4*PBL bits according to ETH_TxDMABurstLength value */ /* Set the DSL bit according to ETH_DesciptorSkipLength value */ - /* Set the PR and DA bits according to ETH_DMAArbitration value */ - ETH->DMABMR = (uint32_t)(ETH_InitStruct->ETH_AddressAlignedBeats | + /* Set the PR and DA bits according to ETH_DMAArbitration value */ + ETH->DMABMR = (uint32_t)(ETH_InitStruct->ETH_AddressAlignedBeats | ETH_InitStruct->ETH_FixedBurst | ETH_InitStruct->ETH_RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */ - ETH_InitStruct->ETH_TxDMABurstLength | + ETH_InitStruct->ETH_TxDMABurstLength | (ETH_InitStruct->ETH_DescriptorSkipLength << 2) | ETH_InitStruct->ETH_DMAArbitration | ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */ - + #ifdef USE_ENHANCED_DMA_DESCRIPTORS /* Enable the Enhanced DMA descriptors */ ETH->DMABMR |= ETH_DMABMR_EDE; #endif /* USE_ENHANCED_DMA_DESCRIPTORS */ + /* Return Ethernet configuration success */ return ETH_SUCCESS; } -/** - * @brief Fills each ETH_InitStruct member with its default value. - * @param ETH_InitStruct: pointer to a ETH_InitTypeDef structure which will be initialized. - * @retval None - */ void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct) { /* ETH_InitStruct members default value */ - /*------------------------ MAC -----------------------------------*/ - ETH_InitStruct->ETH_AutoNegotiation = ETH_AutoNegotiation_Disable; - ETH_InitStruct->ETH_Watchdog = ETH_Watchdog_Enable; - ETH_InitStruct->ETH_Jabber = ETH_Jabber_Enable; - ETH_InitStruct->ETH_InterFrameGap = ETH_InterFrameGap_96Bit; - ETH_InitStruct->ETH_CarrierSense = ETH_CarrierSense_Enable; - ETH_InitStruct->ETH_Speed = ETH_Speed_10M; - ETH_InitStruct->ETH_ReceiveOwn = ETH_ReceiveOwn_Enable; - ETH_InitStruct->ETH_LoopbackMode = ETH_LoopbackMode_Disable; - ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex; - ETH_InitStruct->ETH_ChecksumOffload = ETH_ChecksumOffload_Disable; - ETH_InitStruct->ETH_RetryTransmission = ETH_RetryTransmission_Enable; - ETH_InitStruct->ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable; - ETH_InitStruct->ETH_BackOffLimit = ETH_BackOffLimit_10; - ETH_InitStruct->ETH_DeferralCheck = ETH_DeferralCheck_Disable; - ETH_InitStruct->ETH_ReceiveAll = ETH_ReceiveAll_Disable; - ETH_InitStruct->ETH_SourceAddrFilter = ETH_SourceAddrFilter_Disable; - ETH_InitStruct->ETH_PassControlFrames = ETH_PassControlFrames_BlockAll; + /*------------------------ MAC Configuration ---------------------------*/ + + /* PHY Auto-negotiation enabled */ + ETH_InitStruct->ETH_AutoNegotiation = ETH_AutoNegotiation_Enable; + /* MAC watchdog enabled: cuts-off long frame */ + ETH_InitStruct->ETH_Watchdog = ETH_Watchdog_Enable; + /* MAC Jabber enabled in Half-duplex mode */ + ETH_InitStruct->ETH_Jabber = ETH_Jabber_Enable; + /* Ethernet interframe gap set to 96 bits */ + ETH_InitStruct->ETH_InterFrameGap = ETH_InterFrameGap_96Bit; + /* Carrier Sense Enabled in Half-Duplex mode */ + ETH_InitStruct->ETH_CarrierSense = ETH_CarrierSense_Enable; + /* PHY speed configured to 100Mbit/s */ + ETH_InitStruct->ETH_Speed = ETH_Speed_100M; + /* Receive own Frames in Half-Duplex mode enabled */ + ETH_InitStruct->ETH_ReceiveOwn = ETH_ReceiveOwn_Enable; + /* MAC MII loopback disabled */ + ETH_InitStruct->ETH_LoopbackMode = ETH_LoopbackMode_Disable; + /* Full-Duplex mode selected */ + ETH_InitStruct->ETH_Mode = ETH_Mode_FullDuplex; + /* IPv4 and TCP/UDP/ICMP frame Checksum Offload disabled */ + ETH_InitStruct->ETH_ChecksumOffload = ETH_ChecksumOffload_Disable; + /* Retry Transmission enabled for half-duplex mode */ + ETH_InitStruct->ETH_RetryTransmission = ETH_RetryTransmission_Enable; + /* Automatic PAD/CRC strip disabled*/ + ETH_InitStruct->ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable; + /* half-duplex mode retransmission Backoff time_limit = 10 slot times*/ + ETH_InitStruct->ETH_BackOffLimit = ETH_BackOffLimit_10; + /* half-duplex mode Deferral check disabled */ + ETH_InitStruct->ETH_DeferralCheck = ETH_DeferralCheck_Disable; + /* Receive all frames disabled */ + ETH_InitStruct->ETH_ReceiveAll = ETH_ReceiveAll_Disable; + /* Source address filtering (on the optional MAC addresses) disabled */ + ETH_InitStruct->ETH_SourceAddrFilter = ETH_SourceAddrFilter_Disable; + /* Do not forward control frames that do not pass the address filtering */ + ETH_InitStruct->ETH_PassControlFrames = ETH_PassControlFrames_BlockAll; + /* Disable reception of Broadcast frames */ ETH_InitStruct->ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable; - ETH_InitStruct->ETH_DestinationAddrFilter = ETH_DestinationAddrFilter_Normal; - ETH_InitStruct->ETH_PromiscuousMode = ETH_PromiscuousMode_Disable; - ETH_InitStruct->ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect; - ETH_InitStruct->ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect; - ETH_InitStruct->ETH_HashTableHigh = 0x0; - ETH_InitStruct->ETH_HashTableLow = 0x0; - ETH_InitStruct->ETH_PauseTime = 0x0; - ETH_InitStruct->ETH_ZeroQuantaPause = ETH_ZeroQuantaPause_Disable; - ETH_InitStruct->ETH_PauseLowThreshold = ETH_PauseLowThreshold_Minus4; - ETH_InitStruct->ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable; - ETH_InitStruct->ETH_ReceiveFlowControl = ETH_ReceiveFlowControl_Disable; - ETH_InitStruct->ETH_TransmitFlowControl = ETH_TransmitFlowControl_Disable; - ETH_InitStruct->ETH_VLANTagComparison = ETH_VLANTagComparison_16Bit; - ETH_InitStruct->ETH_VLANTagIdentifier = 0x0; - /*------------------------ DMA -----------------------------------*/ - ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable; - ETH_InitStruct->ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable; - ETH_InitStruct->ETH_FlushReceivedFrame = ETH_FlushReceivedFrame_Disable; - ETH_InitStruct->ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable; - ETH_InitStruct->ETH_TransmitThresholdControl = ETH_TransmitThresholdControl_64Bytes; - ETH_InitStruct->ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable; - ETH_InitStruct->ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable; - ETH_InitStruct->ETH_ReceiveThresholdControl = ETH_ReceiveThresholdControl_64Bytes; + /* Normal Destination address filtering (not reverse addressing) */ + ETH_InitStruct->ETH_DestinationAddrFilter = ETH_DestinationAddrFilter_Normal; + /* Promiscuous address filtering mode disabled */ + ETH_InitStruct->ETH_PromiscuousMode = ETH_PromiscuousMode_Disable; + /* Perfect address filtering for multicast addresses */ + ETH_InitStruct->ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect; + /* Perfect address filtering for unicast addresses */ + ETH_InitStruct->ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect; + /* Initialize hash table high and low regs */ + ETH_InitStruct->ETH_HashTableHigh = 0x0; + ETH_InitStruct->ETH_HashTableLow = 0x0; + /* Flow control config (flow control disabled)*/ + ETH_InitStruct->ETH_PauseTime = 0x0; + ETH_InitStruct->ETH_ZeroQuantaPause = ETH_ZeroQuantaPause_Disable; + ETH_InitStruct->ETH_PauseLowThreshold = ETH_PauseLowThreshold_Minus4; + ETH_InitStruct->ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable; + ETH_InitStruct->ETH_ReceiveFlowControl = ETH_ReceiveFlowControl_Disable; + ETH_InitStruct->ETH_TransmitFlowControl = ETH_TransmitFlowControl_Disable; + /* VLANtag config (VLAN field not checked) */ + ETH_InitStruct->ETH_VLANTagComparison = ETH_VLANTagComparison_16Bit; + ETH_InitStruct->ETH_VLANTagIdentifier = 0x0; + + /*---------------------- DMA Configuration -------------------------------*/ + + /* Drops frames with with TCP/IP checksum errors */ + ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable; + /* Store and forward mode enabled for receive */ + ETH_InitStruct->ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable; + /* Flush received frame that created FIFO overflow */ + ETH_InitStruct->ETH_FlushReceivedFrame = ETH_FlushReceivedFrame_Enable; + /* Store and forward mode enabled for transmit */ + ETH_InitStruct->ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable; + /* Threshold TXFIFO level set to 64 bytes (used when threshold mode is enabled) */ + ETH_InitStruct->ETH_TransmitThresholdControl = ETH_TransmitThresholdControl_64Bytes; + /* Disable forwarding frames with errors (short frames, CRC,...)*/ + ETH_InitStruct->ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable; + /* Disable undersized good frames */ + ETH_InitStruct->ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable; + /* Threshold RXFIFO level set to 64 bytes (used when Cut-through mode is enabled) */ + ETH_InitStruct->ETH_ReceiveThresholdControl = ETH_ReceiveThresholdControl_64Bytes; + /* Disable Operate on second frame (transmit a second frame to FIFO without + waiting status of previous frame*/ ETH_InitStruct->ETH_SecondFrameOperate = ETH_SecondFrameOperate_Disable; + /* DMA works on 32-bit aligned start source and destinations addresses */ ETH_InitStruct->ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable; - ETH_InitStruct->ETH_FixedBurst = ETH_FixedBurst_Disable; - ETH_InitStruct->ETH_RxDMABurstLength = ETH_RxDMABurstLength_1Beat; - ETH_InitStruct->ETH_TxDMABurstLength = ETH_TxDMABurstLength_1Beat; + /* Enabled Fixed Burst Mode (mix of INC4, INC8, INC16 and SINGLE DMA transactions */ + ETH_InitStruct->ETH_FixedBurst = ETH_FixedBurst_Enable; + /* DMA transfer max burst length = 32 beats = 32 x 32bits */ + ETH_InitStruct->ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat; + ETH_InitStruct->ETH_TxDMABurstLength = ETH_TxDMABurstLength_32Beat; + /* DMA Ring mode skip length = 0 */ ETH_InitStruct->ETH_DescriptorSkipLength = 0x0; + /* Equal priority (round-robin) between transmit and receive DMA engines */ ETH_InitStruct->ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_1_1; } /** - * @brief Enables ENET MAC and DMA reception/transmission + * @brief Enables ENET MAC and DMA reception/transmission * @param None * @retval None */ void ETH_Start(void) { - /* Enable transmit state machine of the MAC for transmission on the MII */ + /* Enable transmit state machine of the MAC for transmission on the MII */ ETH_MACTransmissionCmd(ENABLE); /* Flush Transmit FIFO */ ETH_FlushTransmitFIFO(); - /* Enable receive state machine of the MAC for reception from the MII */ + /* Enable receive state machine of the MAC for reception from the MII */ ETH_MACReceptionCmd(ENABLE); - + /* Start DMA transmission */ - ETH_DMATransmissionCmd(ENABLE); + ETH_DMATransmissionCmd(ENABLE); /* Start DMA reception */ - ETH_DMAReceptionCmd(ENABLE); + ETH_DMAReceptionCmd(ENABLE); } /** @@ -529,25 +592,25 @@ void ETH_Start(void) * ETH_SUCCESS: for correct transmission */ uint32_t ETH_HandleTxPkt(uint8_t *ppkt, uint16_t FrameLength) -{ +{ uint32_t offset = 0; - + /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET) { /* Return ERROR: OWN bit set */ return ETH_ERROR; } - - /* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */ - for(offset=0; offsetBuffer1Addr) + offset)) = (*(ppkt + offset)); } - + /* Setting the Frame Length: bits[12:0] */ DMATxDescToSet->ControlBufferSize = (FrameLength & ETH_DMATxDesc_TBS1); - /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */ + /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */ DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS; /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ DMATxDescToSet->Status |= ETH_DMATxDesc_OWN; @@ -559,29 +622,29 @@ uint32_t ETH_HandleTxPkt(uint8_t *ppkt, uint16_t FrameLength) /* Resume DMA transmission*/ ETH->DMATPDR = 0; } - - /* Update the ETHERNET DMA global Tx descriptor with next Tx decriptor */ + + /* Update the ETHERNET DMA global Tx descriptor with next Tx decriptor */ /* Chained Mode */ if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (uint32_t)RESET) - { - /* Selects the next DMA Tx descriptor list for next buffer to send */ - DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMATxDescToSet->Buffer2NextDescAddr); + { + /* Selects the next DMA Tx descriptor list for next buffer to send */ + DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMATxDescToSet->Buffer2NextDescAddr); } else /* Ring Mode */ - { + { if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (uint32_t)RESET) { /* Selects the first DMA Tx descriptor for next buffer to send: last Tx descriptor was used */ - DMATxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLAR); + DMATxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLAR); } else - { + { /* Selects the next DMA Tx descriptor list for next buffer to send */ - DMATxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMATxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + DMATxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMATxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); } } /* Return SUCCESS */ - return ETH_SUCCESS; + return ETH_SUCCESS; } /** @@ -591,23 +654,23 @@ uint32_t ETH_HandleTxPkt(uint8_t *ppkt, uint16_t FrameLength) * framelength: received packet size if packet reception is correct */ uint32_t ETH_HandleRxPkt(uint8_t *ppkt) -{ +{ uint32_t offset = 0, framelength = 0; /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET) { /* Return error: OWN bit set */ - return ETH_ERROR; + return ETH_ERROR; } - - if(((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && - ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) && - ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)) - { + + if(((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)) + { /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT) - 4; /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */ - for(offset=0; offsetBuffer1Addr) + offset)); } @@ -618,46 +681,46 @@ uint32_t ETH_HandleRxPkt(uint8_t *ppkt) framelength = ETH_ERROR; } /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */ - DMARxDescToGet->Status = ETH_DMARxDesc_OWN; - + DMARxDescToGet->Status = ETH_DMARxDesc_OWN; + /* When Rx Buffer unavailable flag is set: clear it and resume reception */ - if ((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET) + if ((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET) { /* Clear RBUS ETHERNET DMA flag */ ETH->DMASR = ETH_DMASR_RBUS; /* Resume DMA reception */ ETH->DMARPDR = 0; } - - /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */ + + /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */ /* Chained Mode */ if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET) - { - /* Selects the next DMA Rx descriptor list for next buffer to read */ - DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr); + { + /* Selects the next DMA Rx descriptor list for next buffer to read */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr); } else /* Ring Mode */ - { + { if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET) { /* Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used */ - DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR); + DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR); } else - { + { /* Selects the next DMA Rx descriptor list for next buffer to read */ - DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); } } - + /* Return Frame Length/ERROR */ - return (framelength); + return (framelength); } /** * @brief Get the size of received the received packet. * @param None - * @retval framelength: received packet size + * @retval framelength: received packet size */ uint32_t ETH_GetRxPktSize(void) { @@ -670,8 +733,8 @@ uint32_t ETH_GetRxPktSize(void) /* Get the size of the packet: including 4 bytes of the CRC */ frameLength = ETH_GetDMARxDescFrameLength(DMARxDescToGet); } - - /* Return Frame Length */ + + /* Return Frame Length */ return frameLength; } @@ -683,7 +746,7 @@ uint32_t ETH_GetRxPktSize(void) void ETH_DropRxPkt(void) { /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */ - DMARxDescToGet->Status = ETH_DMARxDesc_OWN; + DMARxDescToGet->Status = ETH_DMARxDesc_OWN; /* Chained Mode */ if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET) { @@ -710,18 +773,18 @@ void ETH_DropRxPkt(void) /** * @brief Enables or disables the Enhanced descriptor structure. * @param NewState: new state of the Enhanced descriptor structure. - * This parameter can be: ENABLE or DISABLE. + * This parameter can be: ENABLE or DISABLE. * @retval None */ void ETH_EnhancedDescriptorCmd(FunctionalState NewState) -{ +{ /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); - + if (NewState != DISABLE) { /* Enable enhanced descriptor structure */ - ETH->DMABMR |= ETH_DMABMR_EDE; + ETH->DMABMR |= ETH_DMABMR_EDE; } else { @@ -733,25 +796,25 @@ void ETH_EnhancedDescriptorCmd(FunctionalState NewState) /*--------------------------------- PHY ------------------------------------*/ /** * @brief Read a PHY register - * @param PHYAddress: PHY device address, is the index of one of supported 32 PHY devices. - * This parameter can be one of the following values: 0,..,31 - * @param PHYReg: PHY register address, is the index of one of the 32 PHY register. - * This parameter can be one of the following values: - * @arg PHY_BCR: Tranceiver Basic Control Register - * @arg PHY_BSR: Tranceiver Basic Status Register - * @arg PHY_SR : Tranceiver Status Register + * @param PHYAddress: PHY device address, is the index of one of supported 32 PHY devices. + * This parameter can be one of the following values: 0,..,31 + * @param PHYReg: PHY register address, is the index of one of the 32 PHY register. + * This parameter can be one of the following values: + * @arg PHY_BCR: Tranceiver Basic Control Register + * @arg PHY_BSR: Tranceiver Basic Status Register + * @arg PHY_SR : Tranceiver Status Register * @arg More PHY register could be read depending on the used PHY * @retval ETH_ERROR: in case of timeout * MAC MIIDR register value: Data read from the selected PHY register (correct read ) */ uint16_t ETH_ReadPHYRegister(uint16_t PHYAddress, uint16_t PHYReg) { - uint32_t tmpreg = 0; + uint32_t tmpreg = 0; __IO uint32_t timeout = 0; /* Check the parameters */ assert_param(IS_ETH_PHY_ADDRESS(PHYAddress)); assert_param(IS_ETH_PHY_REG(PHYReg)); - + /* Get the ETHERNET MACMIIAR value */ tmpreg = ETH->MACMIIAR; /* Keep only the CSR Clock Range CR[2:0] bits value */ @@ -774,18 +837,18 @@ __IO uint32_t timeout = 0; { return (uint16_t)ETH_ERROR; } - + /* Return data register value */ return (uint16_t)(ETH->MACMIIDR); } /** * @brief Write to a PHY register - * @param PHYAddress: PHY device address, is the index of one of supported 32 PHY devices. + * @param PHYAddress: PHY device address, is the index of one of supported 32 PHY devices. * This parameter can be one of the following values: 0,..,31 - * @param PHYReg: PHY register address, is the index of one of the 32 PHY register. - * This parameter can be one of the following values: - * @arg PHY_BCR : Tranceiver Control Register + * @param PHYReg: PHY register address, is the index of one of the 32 PHY register. + * This parameter can be one of the following values: + * @arg PHY_BCR : Tranceiver Control Register * @arg More PHY register could be written depending on the used PHY * @param PHYValue: the value to write * @retval ETH_ERROR: in case of timeout @@ -793,12 +856,12 @@ __IO uint32_t timeout = 0; */ uint32_t ETH_WritePHYRegister(uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHYValue) { - uint32_t tmpreg = 0; + uint32_t tmpreg = 0; __IO uint32_t timeout = 0; /* Check the parameters */ assert_param(IS_ETH_PHY_ADDRESS(PHYAddress)); assert_param(IS_ETH_PHY_REG(PHYReg)); - + /* Get the ETHERNET MACMIIAR value */ tmpreg = ETH->MACMIIAR; /* Keep only the CSR Clock Range CR[2:0] bits value */ @@ -823,19 +886,19 @@ uint32_t ETH_WritePHYRegister(uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHY { return ETH_ERROR; } - + /* Return SUCCESS */ - return ETH_SUCCESS; + return ETH_SUCCESS; } /** * @brief Enables or disables the PHY loopBack mode. * @Note: Don't be confused with ETH_MACLoopBackCmd function which enables internal * loopback at MII level - * @param PHYAddress: PHY device address, is the index of one of supported 32 PHY devices. - * This parameter can be one of the following values: + * @param PHYAddress: PHY device address, is the index of one of supported 32 PHY devices. + * This parameter can be one of the following values: * @param NewState: new state of the PHY loopBack mode. - * This parameter can be: ENABLE or DISABLE. + * This parameter can be: ENABLE or DISABLE. * @retval ETH_ERROR: in case of bad PHY configuration * ETH_SUCCESS: for correct PHY configuration */ @@ -845,14 +908,14 @@ uint32_t ETH_PHYLoopBackCmd(uint16_t PHYAddress, FunctionalState NewState) /* Check the parameters */ assert_param(IS_ETH_PHY_ADDRESS(PHYAddress)); assert_param(IS_FUNCTIONAL_STATE(NewState)); - + /* Get the PHY configuration to update it */ - tmpreg = ETH_ReadPHYRegister(PHYAddress, PHY_BCR); - + tmpreg = ETH_ReadPHYRegister(PHYAddress, PHY_BCR); + if (NewState != DISABLE) { /* Enable the PHY loopback mode */ - tmpreg |= PHY_Loopback; + tmpreg |= PHY_Loopback; } else { @@ -867,8 +930,8 @@ uint32_t ETH_PHYLoopBackCmd(uint16_t PHYAddress, FunctionalState NewState) else { /* Return SUCCESS */ - return ETH_ERROR; - } + return ETH_ERROR; + } } /*--------------------------------- MAC ------------------------------------*/ @@ -879,14 +942,14 @@ uint32_t ETH_PHYLoopBackCmd(uint16_t PHYAddress, FunctionalState NewState) * @retval None */ void ETH_MACTransmissionCmd(FunctionalState NewState) -{ +{ /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); - + if (NewState != DISABLE) { /* Enable the MAC transmission */ - ETH->MACCR |= ETH_MACCR_TE; + ETH->MACCR |= ETH_MACCR_TE; } else { @@ -902,14 +965,14 @@ void ETH_MACTransmissionCmd(FunctionalState NewState) * @retval None */ void ETH_MACReceptionCmd(FunctionalState NewState) -{ +{ /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); - + if (NewState != DISABLE) { /* Enable the MAC reception */ - ETH->MACCR |= ETH_MACCR_RE; + ETH->MACCR |= ETH_MACCR_RE; } else { @@ -943,10 +1006,10 @@ FlagStatus ETH_GetFlowControlBusyStatus(void) * @param None * @retval None */ -void ETH_InitiatePauseControlFrame(void) -{ +void ETH_InitiatePauseControlFrame(void) +{ /* When Set In full duplex MAC initiates pause control frame */ - ETH->MACFCR |= ETH_MACFCR_FCBBPA; + ETH->MACFCR |= ETH_MACFCR_FCBBPA; } /** @@ -955,41 +1018,41 @@ void ETH_InitiatePauseControlFrame(void) * This parameter can be: ENABLE or DISABLE. * @retval None */ -void ETH_BackPressureActivationCmd(FunctionalState NewState) -{ +void ETH_BackPressureActivationCmd(FunctionalState NewState) +{ /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); - + if (NewState != DISABLE) { /* Activate the MAC BackPressure operation */ /* In Half duplex: during backpressure, when the MAC receives a new frame, the transmitter starts sending a JAM pattern resulting in a collision */ - ETH->MACFCR |= ETH_MACFCR_FCBBPA; + ETH->MACFCR |= ETH_MACFCR_FCBBPA; } else { /* Desactivate the MAC BackPressure operation */ - ETH->MACFCR &= ~ETH_MACFCR_FCBBPA; - } + ETH->MACFCR &= ~ETH_MACFCR_FCBBPA; + } } /** * @brief Checks whether the specified ETHERNET MAC flag is set or not. * @param ETH_MAC_FLAG: specifies the flag to check. * This parameter can be one of the following values: - * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag - * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag - * @arg ETH_MAC_FLAG_MMCR : MMC receive flag - * @arg ETH_MAC_FLAG_MMC : MMC flag - * @arg ETH_MAC_FLAG_PMT : PMT flag + * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag + * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag + * @arg ETH_MAC_FLAG_MMCR : MMC receive flag + * @arg ETH_MAC_FLAG_MMC : MMC flag + * @arg ETH_MAC_FLAG_PMT : PMT flag * @retval The new state of ETHERNET MAC flag (SET or RESET). */ FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG) { FlagStatus bitstatus = RESET; /* Check the parameters */ - assert_param(IS_ETH_MAC_GET_FLAG(ETH_MAC_FLAG)); + assert_param(IS_ETH_MAC_GET_FLAG(ETH_MAC_FLAG)); if ((ETH->MACSR & ETH_MAC_FLAG) != (uint32_t)RESET) { bitstatus = SET; @@ -1005,18 +1068,18 @@ FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG) * @brief Checks whether the specified ETHERNET MAC interrupt has occurred or not. * @param ETH_MAC_IT: specifies the interrupt source to check. * This parameter can be one of the following values: - * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt - * @arg ETH_MAC_IT_MMCT : MMC transmit interrupt - * @arg ETH_MAC_IT_MMCR : MMC receive interrupt - * @arg ETH_MAC_IT_MMC : MMC interrupt - * @arg ETH_MAC_IT_PMT : PMT interrupt + * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt + * @arg ETH_MAC_IT_MMCT : MMC transmit interrupt + * @arg ETH_MAC_IT_MMCR : MMC receive interrupt + * @arg ETH_MAC_IT_MMC : MMC interrupt + * @arg ETH_MAC_IT_PMT : PMT interrupt * @retval The new state of ETHERNET MAC interrupt (SET or RESET). */ ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT) { ITStatus bitstatus = RESET; /* Check the parameters */ - assert_param(IS_ETH_MAC_GET_IT(ETH_MAC_IT)); + assert_param(IS_ETH_MAC_GET_IT(ETH_MAC_IT)); if ((ETH->MACSR & ETH_MAC_IT) != (uint32_t)RESET) { bitstatus = SET; @@ -1033,8 +1096,8 @@ ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT) * @param ETH_MAC_IT: specifies the ETHERNET MAC interrupt sources to be * enabled or disabled. * This parameter can be any combination of the following values: - * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt - * @arg ETH_MAC_IT_PMT : PMT interrupt + * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt + * @arg ETH_MAC_IT_PMT : PMT interrupt * @param NewState: new state of the specified ETHERNET MAC interrupts. * This parameter can be: ENABLE or DISABLE. * @retval None @@ -1043,8 +1106,8 @@ void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_ETH_MAC_IT(ETH_MAC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) { /* Enable the selected ETHERNET MAC interrupts */ @@ -1061,8 +1124,8 @@ void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState) * @brief Configures the selected MAC address. * @param MacAddr: The MAC addres to configure. * This parameter can be one of the following values: - * @arg ETH_MAC_Address0 : MAC Address0 - * @arg ETH_MAC_Address1 : MAC Address1 + * @arg ETH_MAC_Address0 : MAC Address0 + * @arg ETH_MAC_Address1 : MAC Address1 * @arg ETH_MAC_Address2 : MAC Address2 * @arg ETH_MAC_Address3 : MAC Address3 * @param Addr: Pointer on MAC address buffer data (6 bytes). @@ -1073,14 +1136,14 @@ void ETH_MACAddressConfig(uint32_t MacAddr, uint8_t *Addr) uint32_t tmpreg; /* Check the parameters */ assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr)); - + /* Calculate the selectecd MAC address high register */ tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4]; /* Load the selectecd MAC address high register */ (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) = tmpreg; /* Calculate the selectecd MAC address low register */ tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0]; - + /* Load the selectecd MAC address low register */ (*(__IO uint32_t *) (ETH_MAC_ADDR_LBASE + MacAddr)) = tmpreg; } @@ -1089,8 +1152,8 @@ void ETH_MACAddressConfig(uint32_t MacAddr, uint8_t *Addr) * @brief Get the selected MAC address. * @param MacAddr: The MAC addres to return. * This parameter can be one of the following values: - * @arg ETH_MAC_Address0 : MAC Address0 - * @arg ETH_MAC_Address1 : MAC Address1 + * @arg ETH_MAC_Address0 : MAC Address0 + * @arg ETH_MAC_Address1 : MAC Address1 * @arg ETH_MAC_Address2 : MAC Address2 * @arg ETH_MAC_Address3 : MAC Address3 * @param Addr: Pointer on MAC address buffer data (6 bytes). @@ -1101,10 +1164,10 @@ void ETH_GetMACAddress(uint32_t MacAddr, uint8_t *Addr) uint32_t tmpreg; /* Check the parameters */ assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr)); - + /* Get the selectecd MAC address high register */ tmpreg =(*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)); - + /* Calculate the selectecd MAC address buffer */ Addr[5] = ((tmpreg >> 8) & (uint8_t)0xFF); Addr[4] = (tmpreg & (uint8_t)0xFF); @@ -1119,10 +1182,10 @@ void ETH_GetMACAddress(uint32_t MacAddr, uint8_t *Addr) /** * @brief Enables or disables the Address filter module uses the specified - * ETHERNET MAC address for perfect filtering + * ETHERNET MAC address for perfect filtering * @param MacAddr: specifies the ETHERNET MAC address to be used for prfect filtering. - * This parameter can be one of the following values: - * @arg ETH_MAC_Address1 : MAC Address1 + * This parameter can be one of the following values: + * @arg ETH_MAC_Address1 : MAC Address1 * @arg ETH_MAC_Address2 : MAC Address2 * @arg ETH_MAC_Address3 : MAC Address3 * @param NewState: new state of the specified ETHERNET MAC address use. @@ -1134,7 +1197,7 @@ void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState) /* Check the parameters */ assert_param(IS_ETH_MAC_ADDRESS123(MacAddr)); assert_param(IS_FUNCTIONAL_STATE(NewState)); - + if (NewState != DISABLE) { /* Enable the selected ETHERNET MAC address for perfect filtering */ @@ -1148,14 +1211,14 @@ void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState) } /** - * @brief Set the filter type for the specified ETHERNET MAC address - * @param MacAddr: specifies the ETHERNET MAC address - * This parameter can be one of the following values: - * @arg ETH_MAC_Address1 : MAC Address1 + * @brief Set the filter type for the specified ETHERNET MAC address + * @param MacAddr: specifies the ETHERNET MAC address + * This parameter can be one of the following values: + * @arg ETH_MAC_Address1 : MAC Address1 * @arg ETH_MAC_Address2 : MAC Address2 * @arg ETH_MAC_Address3 : MAC Address3 - * @param Filter: specifies the used frame received field for comparaison - * This parameter can be one of the following values: + * @param Filter: specifies the used frame received field for comparaison + * This parameter can be one of the following values: * @arg ETH_MAC_AddressFilter_SA : MAC Address is used to compare with the * SA fields of the received frame. * @arg ETH_MAC_AddressFilter_DA : MAC Address is used to compare with the @@ -1167,7 +1230,7 @@ void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter) /* Check the parameters */ assert_param(IS_ETH_MAC_ADDRESS123(MacAddr)); assert_param(IS_ETH_MAC_ADDRESS_FILTER(Filter)); - + if (Filter != ETH_MAC_AddressFilter_DA) { /* The selected ETHERNET MAC address is used to compare with the SA fields of the @@ -1183,14 +1246,14 @@ void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter) } /** - * @brief Set the filter type for the specified ETHERNET MAC address - * @param MacAddr: specifies the ETHERNET MAC address - * This parameter can be one of the following values: - * @arg ETH_MAC_Address1 : MAC Address1 + * @brief Set the filter type for the specified ETHERNET MAC address + * @param MacAddr: specifies the ETHERNET MAC address + * This parameter can be one of the following values: + * @arg ETH_MAC_Address1 : MAC Address1 * @arg ETH_MAC_Address2 : MAC Address2 * @arg ETH_MAC_Address3 : MAC Address3 - * @param MaskByte: specifies the used address bytes for comparaison - * This parameter can be any combination of the following values: + * @param MaskByte: specifies the used address bytes for comparaison + * This parameter can be any combination of the following values: * @arg ETH_MAC_AddressMask_Byte6 : Mask MAC Address high reg bits [15:8]. * @arg ETH_MAC_AddressMask_Byte5 : Mask MAC Address high reg bits [7:0]. * @arg ETH_MAC_AddressMask_Byte4 : Mask MAC Address low reg bits [31:24]. @@ -1204,7 +1267,7 @@ void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte) /* Check the parameters */ assert_param(IS_ETH_MAC_ADDRESS123(MacAddr)); assert_param(IS_ETH_MAC_ADDRESS_MASK(MaskByte)); - + /* Clear MBC bits in the selected MAC address high register */ (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_MBC); /* Set the selected Filetr mask bytes */ @@ -1214,7 +1277,7 @@ void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte) /** * @brief Initializes the DMA Tx descriptors in chain mode. - * @param DMATxDescTab: Pointer on the first Tx desc list + * @param DMATxDescTab: Pointer on the first Tx desc list * @param TxBuff: Pointer on the first TxBuffer list * @param TxBuffCount: Number of the used Tx desc in the list * @retval None @@ -1223,20 +1286,20 @@ void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t* TxBuff, u { uint32_t i = 0; ETH_DMADESCTypeDef *DMATxDesc; - + /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */ DMATxDescToSet = DMATxDescTab; - /* Fill each DMATxDesc descriptor with the right values */ + /* Fill each DMATxDesc descriptor with the right values */ for(i=0; i < TxBuffCount; i++) { /* Get the pointer on the ith member of the Tx Desc list */ DMATxDesc = DMATxDescTab + i; /* Set Second Address Chained bit */ - DMATxDesc->Status = ETH_DMATxDesc_TCH; - + DMATxDesc->Status = ETH_DMATxDesc_TCH; + /* Set Buffer1 address pointer */ DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_MAX_PACKET_SIZE]); - + /* Initialize the next descriptor with the Next Desciptor Polling Enable */ if(i < (TxBuffCount-1)) { @@ -1245,43 +1308,43 @@ void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t* TxBuff, u } else { - /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ - DMATxDesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab; + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + DMATxDesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab; } } - + /* Set Transmit Desciptor List Address Register */ ETH->DMATDLAR = (uint32_t) DMATxDescTab; } /** * @brief Initializes the DMA Tx descriptors in ring mode. - * @param DMATxDescTab: Pointer on the first Tx desc list - * @param TxBuff1: Pointer on the first TxBuffer1 list + * @param DMATxDescTab: Pointer on the first Tx desc list + * @param TxBuff1: Pointer on the first TxBuffer1 list * @param TxBuff2: Pointer on the first TxBuffer2 list * @param TxBuffCount: Number of the used Tx desc in the list * Note: see decriptor skip length defined in ETH_DMA_InitStruct - * for the number of Words to skip between two unchained descriptors. + * for the number of Words to skip between two unchained descriptors. * @retval None */ void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff1, uint8_t *TxBuff2, uint32_t TxBuffCount) { uint32_t i = 0; ETH_DMADESCTypeDef *DMATxDesc; - + /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */ DMATxDescToSet = DMATxDescTab; - /* Fill each DMATxDesc descriptor with the right values */ + /* Fill each DMATxDesc descriptor with the right values */ for(i=0; i < TxBuffCount; i++) { /* Get the pointer on the ith member of the Tx Desc list */ DMATxDesc = DMATxDescTab + i; /* Set Buffer1 address pointer */ DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff1[i*ETH_MAX_PACKET_SIZE]); - + /* Set Buffer2 address pointer */ DMATxDesc->Buffer2NextDescAddr = (uint32_t)(&TxBuff2[i*ETH_MAX_PACKET_SIZE]); - + /* Set Transmit End of Ring bit for last descriptor: The DMA returns to the base address of the list, creating a Desciptor Ring */ if(i == (TxBuffCount-1)) @@ -1290,7 +1353,7 @@ void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff1, u DMATxDesc->Status = ETH_DMATxDesc_TER; } } - + /* Set Transmit Desciptor List Address Register */ ETH->DMATDLAR = (uint32_t) DMATxDescTab; } @@ -1307,7 +1370,7 @@ void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff1, u * @arg ETH_DMATxDesc_DC : Disable CRC * @arg ETH_DMATxDesc_DP : Disable Pad * @arg ETH_DMATxDesc_TTSE: Transmit Time Stamp Enable - * @arg ETH_DMATxDesc_CIC : Checksum insertion control + * @arg ETH_DMATxDesc_CIC : Checksum insertion control * @arg ETH_DMATxDesc_TER : Transmit End of Ring * @arg ETH_DMATxDesc_TCH : Second Address Chained * @arg ETH_DMATxDesc_TTSS: Tx Time Stamp Status @@ -1321,7 +1384,7 @@ void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff1, u * @arg ETH_DMATxDesc_LCO : Late Collision: transmission aborted due to collision * @arg ETH_DMATxDesc_EC : Excessive Collision: transmission aborted after 16 collisions * @arg ETH_DMATxDesc_VF : VLAN Frame - * @arg ETH_DMATxDesc_CC : Collision Count + * @arg ETH_DMATxDesc_CC : Collision Count * @arg ETH_DMATxDesc_ED : Excessive Deferral * @arg ETH_DMATxDesc_UF : Underflow Error: late data arrival from the memory * @arg ETH_DMATxDesc_DB : Deferred Bit @@ -1332,7 +1395,7 @@ FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ET FlagStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_ETH_DMATxDESC_GET_FLAG(ETH_DMATxDescFlag)); - + if ((DMATxDesc->Status & ETH_DMATxDescFlag) != (uint32_t)RESET) { bitstatus = SET; @@ -1346,7 +1409,7 @@ FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ET /** * @brief Returns the specified ETHERNET DMA Tx Desc collision count. - * @param DMATxDesc: pointer on a DMA Tx descriptor + * @param DMATxDesc: pointer on a DMA Tx descriptor * @retval The Transmit descriptor collision counter value. */ uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc) @@ -1370,14 +1433,14 @@ void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc) * @brief Enables or disables the specified DMA Tx Desc Transmit interrupt. * @param DMATxDesc: Pointer on a Tx desc * @param NewState: new state of the DMA Tx Desc transmit interrupt. - * This parameter can be: ENABLE or DISABLE. + * This parameter can be: ENABLE or DISABLE. * @retval None */ void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); - + if (NewState != DISABLE) { /* Enable the DMA Tx Desc Transmit interrupt */ @@ -1395,35 +1458,35 @@ void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalStat * @param DMATxDesc: Pointer on a Tx desc * @param DMATxDesc_FrameSegment: specifies is the actual Tx desc contain last or first segment. * This parameter can be one of the following values: - * @arg ETH_DMATxDesc_LastSegment : actual Tx desc contain last segment - * @arg ETH_DMATxDesc_FirstSegment : actual Tx desc contain first segment + * @arg ETH_DMATxDesc_LastSegment : actual Tx desc contain last segment + * @arg ETH_DMATxDesc_FirstSegment : actual Tx desc contain first segment * @retval None */ void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_FrameSegment) { /* Check the parameters */ assert_param(IS_ETH_DMA_TXDESC_SEGMENT(DMATxDesc_FrameSegment)); - + /* Selects the DMA Tx Desc Frame segment */ DMATxDesc->Status |= DMATxDesc_FrameSegment; } /** * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion. - * @param DMATxDesc: pointer on a DMA Tx descriptor + * @param DMATxDesc: pointer on a DMA Tx descriptor * @param DMATxDesc_Checksum: specifies is the DMA Tx desc checksum insertion. * This parameter can be one of the following values: * @arg ETH_DMATxDesc_ChecksumByPass : Checksum bypass * @arg ETH_DMATxDesc_ChecksumIPV4Header : IPv4 header checksum * @arg ETH_DMATxDesc_ChecksumTCPUDPICMPSegment : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present - * @arg ETH_DMATxDesc_ChecksumTCPUDPICMPFull : TCP/UDP/ICMP checksum fully in hardware including pseudo header + * @arg ETH_DMATxDesc_ChecksumTCPUDPICMPFull : TCP/UDP/ICMP checksum fully in hardware including pseudo header * @retval None */ void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum) { /* Check the parameters */ assert_param(IS_ETH_DMA_TXDESC_CHECKSUM(DMATxDesc_Checksum)); - + /* Set the selected DMA Tx desc checksum insertion control */ DMATxDesc->Status |= DMATxDesc_Checksum; } @@ -1439,7 +1502,7 @@ void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); - + if (NewState != DISABLE) { /* Enable the selected DMA Tx Desc CRC */ @@ -1448,7 +1511,7 @@ void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState else { /* Disable the selected DMA Tx Desc CRC */ - DMATxDesc->Status |= ETH_DMATxDesc_DC; + DMATxDesc->Status |= ETH_DMATxDesc_DC; } } @@ -1463,16 +1526,16 @@ void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState Ne { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); - + if (NewState != DISABLE) { /* Enable the selected DMA Tx Desc end of ring */ - DMATxDesc->Status |= ETH_DMATxDesc_TER; + DMATxDesc->Status |= ETH_DMATxDesc_TER; } else { /* Disable the selected DMA Tx Desc end of ring */ - DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_TER); + DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_TER); } } @@ -1487,16 +1550,16 @@ void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, Functio { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); - + if (NewState != DISABLE) { /* Enable the selected DMA Tx Desc second address chained */ - DMATxDesc->Status |= ETH_DMATxDesc_TCH; + DMATxDesc->Status |= ETH_DMATxDesc_TCH; } else { /* Disable the selected DMA Tx Desc second address chained */ - DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_TCH); + DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_TCH); } } @@ -1511,7 +1574,7 @@ void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, Functional { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); - + if (NewState != DISABLE) { /* Enable the selected DMA Tx Desc padding for frame shorter than 64 bytes */ @@ -1520,7 +1583,7 @@ void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, Functional else { /* Disable the selected DMA Tx Desc padding for frame shorter than 64 bytes*/ - DMATxDesc->Status |= ETH_DMATxDesc_DP; + DMATxDesc->Status |= ETH_DMATxDesc_DP; } } @@ -1535,16 +1598,16 @@ void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState Ne { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); - + if (NewState != DISABLE) { /* Enable the selected DMA Tx Desc time stamp */ - DMATxDesc->Status |= ETH_DMATxDesc_TTSE; + DMATxDesc->Status |= ETH_DMATxDesc_TTSE; } else { /* Disable the selected DMA Tx Desc time stamp */ - DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_TTSE); + DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_TTSE); } } @@ -1560,14 +1623,14 @@ void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t Buffe /* Check the parameters */ assert_param(IS_ETH_DMATxDESC_BUFFER_SIZE(BufferSize1)); assert_param(IS_ETH_DMATxDESC_BUFFER_SIZE(BufferSize2)); - + /* Set the DMA Tx Desc buffer1 and buffer2 sizes values */ DMATxDesc->ControlBufferSize |= (BufferSize1 | (BufferSize2 << ETH_DMATXDESC_BUFFER2_SIZESHIFT)); } /** * @brief Initializes the DMA Rx descriptors in chain mode. - * @param DMARxDescTab: Pointer on the first Rx desc list + * @param DMARxDescTab: Pointer on the first Rx desc list * @param RxBuff: Pointer on the first RxBuffer list * @param RxBuffCount: Number of the used Rx desc in the list * @retval None @@ -1576,9 +1639,9 @@ void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, u { uint32_t i = 0; ETH_DMADESCTypeDef *DMARxDesc; - + /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */ - DMARxDescToGet = DMARxDescTab; + DMARxDescToGet = DMARxDescTab; /* Fill each DMARxDesc descriptor with the right values */ for(i=0; i < RxBuffCount; i++) { @@ -1588,35 +1651,35 @@ void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, u DMARxDesc->Status = ETH_DMARxDesc_OWN; /* Set Buffer1 size and Second Address Chained bit */ - DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_MAX_PACKET_SIZE; + DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_MAX_PACKET_SIZE; /* Set Buffer1 address pointer */ DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_MAX_PACKET_SIZE]); - + /* Initialize the next descriptor with the Next Desciptor Polling Enable */ if(i < (RxBuffCount-1)) { /* Set next descriptor address register with next descriptor base address */ - DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1); + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1); } else { - /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ - DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); } } - + /* Set Receive Desciptor List Address Register */ - ETH->DMARDLAR = (uint32_t) DMARxDescTab; + ETH->DMARDLAR = (uint32_t) DMARxDescTab; } /** * @brief Initializes the DMA Rx descriptors in ring mode. - * @param DMARxDescTab: Pointer on the first Rx desc list - * @param RxBuff1: Pointer on the first RxBuffer1 list + * @param DMARxDescTab: Pointer on the first Rx desc list + * @param RxBuff1: Pointer on the first RxBuffer1 list * @param RxBuff2: Pointer on the first RxBuffer2 list * @param RxBuffCount: Number of the used Rx desc in the list * Note: see decriptor skip length defined in ETH_DMA_InitStruct - * for the number of Words to skip between two unchained descriptors. + * for the number of Words to skip between two unchained descriptors. * @retval None */ void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff1, uint8_t *RxBuff2, uint32_t RxBuffCount) @@ -1624,22 +1687,22 @@ void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff1, u uint32_t i = 0; ETH_DMADESCTypeDef *DMARxDesc; /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */ - DMARxDescToGet = DMARxDescTab; - /* Fill each DMARxDesc descriptor with the right values */ + DMARxDescToGet = DMARxDescTab; + /* Fill each DMARxDesc descriptor with the right values */ for(i=0; i < RxBuffCount; i++) { /* Get the pointer on the ith member of the Rx Desc list */ - DMARxDesc = DMARxDescTab+i; + DMARxDesc = DMARxDescTab+i; /* Set Own bit of the Rx descriptor Status */ - DMARxDesc->Status = ETH_DMARxDesc_OWN; + DMARxDesc->Status = ETH_DMARxDesc_OWN; /* Set Buffer1 size */ - DMARxDesc->ControlBufferSize = ETH_MAX_PACKET_SIZE; + DMARxDesc->ControlBufferSize = ETH_MAX_PACKET_SIZE; /* Set Buffer1 address pointer */ - DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff1[i*ETH_MAX_PACKET_SIZE]); - + DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff1[i*ETH_MAX_PACKET_SIZE]); + /* Set Buffer2 address pointer */ - DMARxDesc->Buffer2NextDescAddr = (uint32_t)(&RxBuff2[i*ETH_MAX_PACKET_SIZE]); - + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(&RxBuff2[i*ETH_MAX_PACKET_SIZE]); + /* Set Receive End of Ring bit for last descriptor: The DMA returns to the base address of the list, creating a Desciptor Ring */ if(i == (RxBuffCount-1)) @@ -1648,9 +1711,9 @@ void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff1, u DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER; } } - + /* Set Receive Desciptor List Address Register */ - ETH->DMARDLAR = (uint32_t) DMARxDescTab; + ETH->DMARDLAR = (uint32_t) DMARxDescTab; } /** @@ -1658,7 +1721,7 @@ void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff1, u * @param DMARxDesc: pointer on a DMA Rx descriptor * @param ETH_DMARxDescFlag: specifies the flag to check. * This parameter can be one of the following values: - * @arg ETH_DMARxDesc_OWN: OWN bit: descriptor is owned by DMA engine + * @arg ETH_DMARxDesc_OWN: OWN bit: descriptor is owned by DMA engine * @arg ETH_DMARxDesc_AFM: DA Filter Fail for the rx frame * @arg ETH_DMARxDesc_ES: Error summary * @arg ETH_DMARxDesc_DE: Desciptor error: no more descriptors for receive frame @@ -1668,7 +1731,7 @@ void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff1, u * @arg ETH_DMARxDesc_VLAN: VLAN Tag: received frame is a VLAN frame * @arg ETH_DMARxDesc_FS: First descriptor of the frame * @arg ETH_DMARxDesc_LS: Last descriptor of the frame - * @arg ETH_DMARxDesc_IPV4HCE: IPC Checksum Error/Giant Frame: Rx Ipv4 header checksum error + * @arg ETH_DMARxDesc_IPV4HCE: IPC Checksum Error/Giant Frame: Rx Ipv4 header checksum error * @arg ETH_DMARxDesc_LC: Late collision occurred during reception * @arg ETH_DMARxDesc_FT: Frame type - Ethernet, otherwise 802.3 * @arg ETH_DMARxDesc_RWT: Receive Watchdog Timeout: watchdog timer expired during reception @@ -1700,15 +1763,15 @@ FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ET * @param DMAPTPRxDesc: pointer on a DMA PTP Rx descriptor * @param ETH_DMAPTPRxDescFlag: specifies the extended flag to check. * This parameter can be one of the following values: - * @arg ETH_DMAPTPRxDesc_PTPV: PTP version + * @arg ETH_DMAPTPRxDesc_PTPV: PTP version * @arg ETH_DMAPTPRxDesc_PTPFT: PTP frame type - * @arg ETH_DMAPTPRxDesc_PTPMT: PTP message type - * @arg ETH_DMAPTPRxDesc_IPV6PR: IPv6 packet received - * @arg ETH_DMAPTPRxDesc_IPV4PR: IPv4 packet received - * @arg ETH_DMAPTPRxDesc_IPCB: IP checksum bypassed + * @arg ETH_DMAPTPRxDesc_PTPMT: PTP message type + * @arg ETH_DMAPTPRxDesc_IPV6PR: IPv6 packet received + * @arg ETH_DMAPTPRxDesc_IPV4PR: IPv4 packet received + * @arg ETH_DMAPTPRxDesc_IPCB: IP checksum bypassed * @arg ETH_DMAPTPRxDesc_IPPE: IP payload error - * @arg ETH_DMAPTPRxDesc_IPHE: IP header error - * @arg ETH_DMAPTPRxDesc_IPPT: IP payload type + * @arg ETH_DMAPTPRxDesc_IPHE: IP header error + * @arg ETH_DMAPTPRxDesc_IPPT: IP payload type * @retval The new state of ETH_DMAPTPRxDescExtendedFlag (SET or RESET). */ FlagStatus ETH_GetDMAPTPRxDescExtendedFlagStatus(ETH_DMADESCTypeDef *DMAPTPRxDesc, uint32_t ETH_DMAPTPRxDescExtendedFlag) @@ -1743,7 +1806,7 @@ void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc) /** * @brief Returns the specified DMA Rx Desc frame length. - * @param DMARxDesc: pointer on a DMA Rx descriptor + * @param DMARxDesc: pointer on a DMA Rx descriptor * @retval The Rx descriptor received frame length. */ uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc) @@ -1756,14 +1819,14 @@ uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc) * @brief Enables or disables the specified DMA Rx Desc receive interrupt. * @param DMARxDesc: Pointer on a Rx desc * @param NewState: new state of the specified DMA Rx Desc interrupt. - * This parameter can be: ENABLE or DISABLE. + * This parameter can be: ENABLE or DISABLE. * @retval None */ void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); - + if (NewState != DISABLE) { /* Enable the DMA Rx Desc receive interrupt */ @@ -1787,16 +1850,16 @@ void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState Ne { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); - + if (NewState != DISABLE) { /* Enable the selected DMA Rx Desc end of ring */ - DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER; + DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER; } else { /* Disable the selected DMA Rx Desc end of ring */ - DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_RER); + DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_RER); } } @@ -1811,42 +1874,42 @@ void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, Functio { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); - + if (NewState != DISABLE) { /* Enable the selected DMA Rx Desc second address chained */ - DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RCH; + DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RCH; } else { /* Disable the selected DMA Rx Desc second address chained */ - DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_RCH); + DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_RCH); } } /** * @brief Returns the specified ETHERNET DMA Rx Desc buffer size. - * @param DMARxDesc: pointer on a DMA Rx descriptor + * @param DMARxDesc: pointer on a DMA Rx descriptor * @param DMARxDesc_Buffer: specifies the DMA Rx Desc buffer. * This parameter can be any one of the following values: * @arg ETH_DMARxDesc_Buffer1 : DMA Rx Desc Buffer1 - * @arg ETH_DMARxDesc_Buffer2 : DMA Rx Desc Buffer2 + * @arg ETH_DMARxDesc_Buffer2 : DMA Rx Desc Buffer2 * @retval The Receive descriptor frame length. */ uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer) { /* Check the parameters */ assert_param(IS_ETH_DMA_RXDESC_BUFFER(DMARxDesc_Buffer)); - + if(DMARxDesc_Buffer != ETH_DMARxDesc_Buffer1) { /* Return the DMA Rx Desc buffer2 size */ - return ((DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS2) >> ETH_DMARXDESC_BUFFER2_SIZESHIFT); + return ((DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS2) >> ETH_DMARXDESC_BUFFER2_SIZESHIFT); } else { /* Return the DMA Rx Desc buffer1 size */ - return (DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS1); + return (DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS1); } } @@ -1887,30 +1950,30 @@ FlagStatus ETH_GetSoftwareResetStatus(void) * @param ETH_DMA_FLAG: specifies the flag to check. * This parameter can be one of the following values: * @arg ETH_DMA_FLAG_TST : Time-stamp trigger flag - * @arg ETH_DMA_FLAG_PMT : PMT flag - * @arg ETH_DMA_FLAG_MMC : MMC flag + * @arg ETH_DMA_FLAG_PMT : PMT flag + * @arg ETH_DMA_FLAG_MMC : MMC flag * @arg ETH_DMA_FLAG_DataTransferError : Error bits 0-data buffer, 1-desc. access * @arg ETH_DMA_FLAG_ReadWriteError : Error bits 0-write trnsf, 1-read transfr * @arg ETH_DMA_FLAG_AccessError : Error bits 0-Rx DMA, 1-Tx DMA * @arg ETH_DMA_FLAG_NIS : Normal interrupt summary flag - * @arg ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag - * @arg ETH_DMA_FLAG_ER : Early receive flag - * @arg ETH_DMA_FLAG_FBE : Fatal bus error flag - * @arg ETH_DMA_FLAG_ET : Early transmit flag - * @arg ETH_DMA_FLAG_RWT : Receive watchdog timeout flag - * @arg ETH_DMA_FLAG_RPS : Receive process stopped flag - * @arg ETH_DMA_FLAG_RBU : Receive buffer unavailable flag - * @arg ETH_DMA_FLAG_R : Receive flag - * @arg ETH_DMA_FLAG_TU : Underflow flag - * @arg ETH_DMA_FLAG_RO : Overflow flag - * @arg ETH_DMA_FLAG_TJT : Transmit jabber timeout flag - * @arg ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag - * @arg ETH_DMA_FLAG_TPS : Transmit process stopped flag - * @arg ETH_DMA_FLAG_T : Transmit flag + * @arg ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag + * @arg ETH_DMA_FLAG_ER : Early receive flag + * @arg ETH_DMA_FLAG_FBE : Fatal bus error flag + * @arg ETH_DMA_FLAG_ET : Early transmit flag + * @arg ETH_DMA_FLAG_RWT : Receive watchdog timeout flag + * @arg ETH_DMA_FLAG_RPS : Receive process stopped flag + * @arg ETH_DMA_FLAG_RBU : Receive buffer unavailable flag + * @arg ETH_DMA_FLAG_R : Receive flag + * @arg ETH_DMA_FLAG_TU : Underflow flag + * @arg ETH_DMA_FLAG_RO : Overflow flag + * @arg ETH_DMA_FLAG_TJT : Transmit jabber timeout flag + * @arg ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag + * @arg ETH_DMA_FLAG_TPS : Transmit process stopped flag + * @arg ETH_DMA_FLAG_T : Transmit flag * @retval The new state of ETH_DMA_FLAG (SET or RESET). */ FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG) -{ +{ FlagStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_ETH_DMA_GET_IT(ETH_DMA_FLAG)); @@ -1930,19 +1993,19 @@ FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG) * @param ETH_DMA_FLAG: specifies the flag to clear. * This parameter can be any combination of the following values: * @arg ETH_DMA_FLAG_NIS : Normal interrupt summary flag - * @arg ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag - * @arg ETH_DMA_FLAG_ER : Early receive flag - * @arg ETH_DMA_FLAG_FBE : Fatal bus error flag - * @arg ETH_DMA_FLAG_ETI : Early transmit flag - * @arg ETH_DMA_FLAG_RWT : Receive watchdog timeout flag - * @arg ETH_DMA_FLAG_RPS : Receive process stopped flag - * @arg ETH_DMA_FLAG_RBU : Receive buffer unavailable flag - * @arg ETH_DMA_FLAG_R : Receive flag - * @arg ETH_DMA_FLAG_TU : Transmit Underflow flag - * @arg ETH_DMA_FLAG_RO : Receive Overflow flag - * @arg ETH_DMA_FLAG_TJT : Transmit jabber timeout flag - * @arg ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag - * @arg ETH_DMA_FLAG_TPS : Transmit process stopped flag + * @arg ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag + * @arg ETH_DMA_FLAG_ER : Early receive flag + * @arg ETH_DMA_FLAG_FBE : Fatal bus error flag + * @arg ETH_DMA_FLAG_ETI : Early transmit flag + * @arg ETH_DMA_FLAG_RWT : Receive watchdog timeout flag + * @arg ETH_DMA_FLAG_RPS : Receive process stopped flag + * @arg ETH_DMA_FLAG_RBU : Receive buffer unavailable flag + * @arg ETH_DMA_FLAG_R : Receive flag + * @arg ETH_DMA_FLAG_TU : Transmit Underflow flag + * @arg ETH_DMA_FLAG_RO : Receive Overflow flag + * @arg ETH_DMA_FLAG_TJT : Transmit jabber timeout flag + * @arg ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag + * @arg ETH_DMA_FLAG_TPS : Transmit process stopped flag * @arg ETH_DMA_FLAG_T : Transmit flag * @retval None */ @@ -1950,7 +2013,7 @@ void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG) { /* Check the parameters */ assert_param(IS_ETH_DMA_FLAG(ETH_DMA_FLAG)); - + /* Clear the selected ETHERNET DMA FLAG */ ETH->DMASR = (uint32_t) ETH_DMA_FLAG; } @@ -1960,27 +2023,27 @@ void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG) * @param ETH_DMA_IT: specifies the interrupt source to check. * This parameter can be one of the following values: * @arg ETH_DMA_IT_TST : Time-stamp trigger interrupt - * @arg ETH_DMA_IT_PMT : PMT interrupt + * @arg ETH_DMA_IT_PMT : PMT interrupt * @arg ETH_DMA_IT_MMC : MMC interrupt - * @arg ETH_DMA_IT_NIS : Normal interrupt summary - * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary - * @arg ETH_DMA_IT_ER : Early receive interrupt - * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt - * @arg ETH_DMA_IT_ET : Early transmit interrupt - * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt - * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt - * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt - * @arg ETH_DMA_IT_R : Receive interrupt - * @arg ETH_DMA_IT_TU : Underflow interrupt - * @arg ETH_DMA_IT_RO : Overflow interrupt - * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt - * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt - * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt - * @arg ETH_DMA_IT_T : Transmit interrupt + * @arg ETH_DMA_IT_NIS : Normal interrupt summary + * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary + * @arg ETH_DMA_IT_ER : Early receive interrupt + * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt + * @arg ETH_DMA_IT_ET : Early transmit interrupt + * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt + * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt + * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt + * @arg ETH_DMA_IT_R : Receive interrupt + * @arg ETH_DMA_IT_TU : Underflow interrupt + * @arg ETH_DMA_IT_RO : Overflow interrupt + * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt + * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt + * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt + * @arg ETH_DMA_IT_T : Transmit interrupt * @retval The new state of ETH_DMA_IT (SET or RESET). */ ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT) -{ +{ ITStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_ETH_DMA_GET_IT(ETH_DMA_IT)); @@ -1999,20 +2062,20 @@ ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT) * @brief Clears the ETHERNET’s DMA IT pending bit. * @param ETH_DMA_IT: specifies the interrupt pending bit to clear. * This parameter can be any combination of the following values: - * @arg ETH_DMA_IT_NIS : Normal interrupt summary - * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary - * @arg ETH_DMA_IT_ER : Early receive interrupt - * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt - * @arg ETH_DMA_IT_ETI : Early transmit interrupt - * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt - * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt - * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt - * @arg ETH_DMA_IT_R : Receive interrupt - * @arg ETH_DMA_IT_TU : Transmit Underflow interrupt - * @arg ETH_DMA_IT_RO : Receive Overflow interrupt - * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt - * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt - * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt + * @arg ETH_DMA_IT_NIS : Normal interrupt summary + * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary + * @arg ETH_DMA_IT_ER : Early receive interrupt + * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt + * @arg ETH_DMA_IT_ETI : Early transmit interrupt + * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt + * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt + * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt + * @arg ETH_DMA_IT_R : Receive interrupt + * @arg ETH_DMA_IT_TU : Transmit Underflow interrupt + * @arg ETH_DMA_IT_RO : Receive Overflow interrupt + * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt + * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt + * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt * @arg ETH_DMA_IT_T : Transmit interrupt * @retval None */ @@ -2020,7 +2083,7 @@ void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT) { /* Check the parameters */ assert_param(IS_ETH_DMA_IT(ETH_DMA_IT)); - + /* Clear the selected ETHERNET DMA IT */ ETH->DMASR = (uint32_t) ETH_DMA_IT; } @@ -2031,15 +2094,15 @@ void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT) * @retval The new ETHERNET DMA Transmit Process State: * This can be one of the following values: * - ETH_DMA_TransmitProcess_Stopped : Stopped - Reset or Stop Tx Command issued - * - ETH_DMA_TransmitProcess_Fetching : Running - fetching the Tx descriptor + * - ETH_DMA_TransmitProcess_Fetching : Running - fetching the Tx descriptor * - ETH_DMA_TransmitProcess_Waiting : Running - waiting for status * - ETH_DMA_TransmitProcess_Reading : unning - reading the data from host memory * - ETH_DMA_TransmitProcess_Suspended : Suspended - Tx Desciptor unavailabe - * - ETH_DMA_TransmitProcess_Closing : Running - closing Rx descriptor + * - ETH_DMA_TransmitProcess_Closing : Running - closing Rx descriptor */ uint32_t ETH_GetTransmitProcessState(void) { - return ((uint32_t)(ETH->DMASR & ETH_DMASR_TS)); + return ((uint32_t)(ETH->DMASR & ETH_DMASR_TS)); } /** @@ -2048,35 +2111,35 @@ uint32_t ETH_GetTransmitProcessState(void) * @retval The new ETHERNET DMA Receive Process State: * This can be one of the following values: * - ETH_DMA_ReceiveProcess_Stopped : Stopped - Reset or Stop Rx Command issued - * - ETH_DMA_ReceiveProcess_Fetching : Running - fetching the Rx descriptor + * - ETH_DMA_ReceiveProcess_Fetching : Running - fetching the Rx descriptor * - ETH_DMA_ReceiveProcess_Waiting : Running - waiting for packet * - ETH_DMA_ReceiveProcess_Suspended : Suspended - Rx Desciptor unavailable * - ETH_DMA_ReceiveProcess_Closing : Running - closing descriptor - * - ETH_DMA_ReceiveProcess_Queuing : Running - queuing the recieve frame into host memory + * - ETH_DMA_ReceiveProcess_Queuing : Running - queuing the recieve frame into host memory */ uint32_t ETH_GetReceiveProcessState(void) { - return ((uint32_t)(ETH->DMASR & ETH_DMASR_RS)); + return ((uint32_t)(ETH->DMASR & ETH_DMASR_RS)); } /** * @brief Clears the ETHERNET transmit FIFO. - * @param None + * @param None * @retval None */ void ETH_FlushTransmitFIFO(void) { /* Set the Flush Transmit FIFO bit */ - ETH->DMAOMR |= ETH_DMAOMR_FTF; + ETH->DMAOMR |= ETH_DMAOMR_FTF; } /** * @brief Checks whether the ETHERNET transmit FIFO bit is cleared or not. - * @param None + * @param None * @retval The new state of ETHERNET flush transmit FIFO bit (SET or RESET). */ FlagStatus ETH_GetFlushTransmitFIFOStatus(void) -{ +{ FlagStatus bitstatus = RESET; if ((ETH->DMAOMR & ETH_DMAOMR_FTF) != (uint32_t)RESET) { @@ -2086,7 +2149,7 @@ FlagStatus ETH_GetFlushTransmitFIFOStatus(void) { bitstatus = RESET; } - return bitstatus; + return bitstatus; } /** @@ -2096,14 +2159,14 @@ FlagStatus ETH_GetFlushTransmitFIFOStatus(void) * @retval None */ void ETH_DMATransmissionCmd(FunctionalState NewState) -{ +{ /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); - + if (NewState != DISABLE) { /* Enable the DMA transmission */ - ETH->DMAOMR |= ETH_DMAOMR_ST; + ETH->DMAOMR |= ETH_DMAOMR_ST; } else { @@ -2119,14 +2182,14 @@ void ETH_DMATransmissionCmd(FunctionalState NewState) * @retval None */ void ETH_DMAReceptionCmd(FunctionalState NewState) -{ +{ /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); - + if (NewState != DISABLE) { /* Enable the DMA reception */ - ETH->DMAOMR |= ETH_DMAOMR_SR; + ETH->DMAOMR |= ETH_DMAOMR_SR; } else { @@ -2140,20 +2203,20 @@ void ETH_DMAReceptionCmd(FunctionalState NewState) * @param ETH_DMA_IT: specifies the ETHERNET DMA interrupt sources to be * enabled or disabled. * This parameter can be any combination of the following values: - * @arg ETH_DMA_IT_NIS : Normal interrupt summary - * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary - * @arg ETH_DMA_IT_ER : Early receive interrupt - * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt - * @arg ETH_DMA_IT_ET : Early transmit interrupt - * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt - * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt - * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt - * @arg ETH_DMA_IT_R : Receive interrupt - * @arg ETH_DMA_IT_TU : Underflow interrupt - * @arg ETH_DMA_IT_RO : Overflow interrupt - * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt - * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt - * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt + * @arg ETH_DMA_IT_NIS : Normal interrupt summary + * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary + * @arg ETH_DMA_IT_ER : Early receive interrupt + * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt + * @arg ETH_DMA_IT_ET : Early transmit interrupt + * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt + * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt + * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt + * @arg ETH_DMA_IT_R : Receive interrupt + * @arg ETH_DMA_IT_TU : Underflow interrupt + * @arg ETH_DMA_IT_RO : Overflow interrupt + * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt + * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt + * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt * @arg ETH_DMA_IT_T : Transmit interrupt * @param NewState: new state of the specified ETHERNET DMA interrupts. * This parameter can be: ENABLE or DISABLE. @@ -2163,8 +2226,8 @@ void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_ETH_DMA_IT(ETH_DMA_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) { /* Enable the selected ETHERNET DMA interrupts */ @@ -2190,7 +2253,7 @@ FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow) FlagStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_ETH_DMA_GET_OVERFLOW(ETH_DMA_Overflow)); - + if ((ETH->DMAMFBOCR & ETH_DMA_Overflow) != (uint32_t)RESET) { bitstatus = SET; @@ -2286,7 +2349,7 @@ void ETH_ResumeDMAReception(void) /** * @brief Set the DMA Receive status watchdog timer register value - * @param Value: DMA Receive status watchdog timer register value + * @param Value: DMA Receive status watchdog timer register value * @retval None */ void ETH_SetReceiveWatchdogTimer(uint8_t Value) @@ -2302,9 +2365,9 @@ void ETH_SetReceiveWatchdogTimer(uint8_t Value) * @retval None */ void ETH_ResetWakeUpFrameFilterRegisterPointer(void) -{ +{ /* Resets the Remote Wake-up Frame Filter register pointer to 0x0000 */ - ETH->MACPMTCSR |= ETH_MACPMTCSR_WFFRPR; + ETH->MACPMTCSR |= ETH_MACPMTCSR_WFFRPR; } /** @@ -2315,11 +2378,11 @@ void ETH_ResetWakeUpFrameFilterRegisterPointer(void) void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer) { uint32_t i = 0; - + /* Fill Remote Wake-up Frame Filter register with Buffer data */ for(i =0; iMACRWUFFR = Buffer[i]; } } @@ -2332,18 +2395,18 @@ void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer) * @retval None */ void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState) -{ +{ /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); - + if (NewState != DISABLE) { /* Enable the MAC Global Unicast Wake-Up */ - ETH->MACPMTCSR |= ETH_MACPMTCSR_GU; + ETH->MACPMTCSR |= ETH_MACPMTCSR_GU; } else { - /* Disable the MAC Global Unicast Wake-Up */ + /* Disable the MAC Global Unicast Wake-Up */ ETH->MACPMTCSR &= ~ETH_MACPMTCSR_GU; } } @@ -2352,8 +2415,8 @@ void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState) * @brief Checks whether the specified ETHERNET PMT flag is set or not. * @param ETH_PMT_FLAG: specifies the flag to check. * This parameter can be one of the following values: - * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Poniter Reset - * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received + * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Poniter Reset + * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received * @arg ETH_PMT_FLAG_MPR : Magic Packet Received * @retval The new state of ETHERNET PMT Flag (SET or RESET). */ @@ -2362,7 +2425,7 @@ FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG) FlagStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_ETH_PMT_GET_FLAG(ETH_PMT_FLAG)); - + if ((ETH->MACPMTCSR & ETH_PMT_FLAG) != (uint32_t)RESET) { bitstatus = SET; @@ -2381,18 +2444,18 @@ FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG) * @retval None */ void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState) -{ +{ /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); - + if (NewState != DISABLE) { /* Enable the MAC Wake-Up Frame Detection */ - ETH->MACPMTCSR |= ETH_MACPMTCSR_WFE; + ETH->MACPMTCSR |= ETH_MACPMTCSR_WFE; } else { - /* Disable the MAC Wake-Up Frame Detection */ + /* Disable the MAC Wake-Up Frame Detection */ ETH->MACPMTCSR &= ~ETH_MACPMTCSR_WFE; } } @@ -2404,18 +2467,18 @@ void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState) * @retval None */ void ETH_MagicPacketDetectionCmd(FunctionalState NewState) -{ +{ /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); - + if (NewState != DISABLE) { /* Enable the MAC Magic Packet Detection */ - ETH->MACPMTCSR |= ETH_MACPMTCSR_MPE; + ETH->MACPMTCSR |= ETH_MACPMTCSR_MPE; } else { - /* Disable the MAC Magic Packet Detection */ + /* Disable the MAC Magic Packet Detection */ ETH->MACPMTCSR &= ~ETH_MACPMTCSR_MPE; } } @@ -2427,26 +2490,26 @@ void ETH_MagicPacketDetectionCmd(FunctionalState NewState) * @retval None */ void ETH_PowerDownCmd(FunctionalState NewState) -{ +{ /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); - + if (NewState != DISABLE) { /* Enable the MAC Power Down */ /* This puts the MAC in power down mode */ - ETH->MACPMTCSR |= ETH_MACPMTCSR_PD; + ETH->MACPMTCSR |= ETH_MACPMTCSR_PD; } else { - /* Disable the MAC Power Down */ + /* Disable the MAC Power Down */ ETH->MACPMTCSR &= ~ETH_MACPMTCSR_PD; } } /*--------------------------------- MMC ------------------------------------*/ /** - * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16) + * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16) * @param None * @retval None */ @@ -2457,7 +2520,7 @@ void ETH_MMCCounterFullPreset(void) } /** - * @brief Preset and Initialize the MMC counters to almost-hal value: 0x7FFF_FFF0 (half - 16). + * @brief Preset and Initialize the MMC counters to almost-hal value: 0x7FFF_FFF0 (half - 16). * @param None * @retval None */ @@ -2479,7 +2542,7 @@ void ETH_MMCCounterFreezeCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); - + if (NewState != DISABLE) { /* Enable the MMC Counter Freeze */ @@ -2502,11 +2565,11 @@ void ETH_MMCResetOnReadCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); - + if (NewState != DISABLE) { /* Enable the MMC Counter reset on read */ - ETH->MMCCR |= ETH_MMCCR_ROR; + ETH->MMCCR |= ETH_MMCCR_ROR; } else { @@ -2525,7 +2588,7 @@ void ETH_MMCCounterRolloverCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); - + if (NewState != DISABLE) { /* Disable the MMC Counter Stop Rollover */ @@ -2534,7 +2597,7 @@ void ETH_MMCCounterRolloverCmd(FunctionalState NewState) else { /* Enable the MMC Counter Stop Rollover */ - ETH->MMCCR |= ETH_MMCCR_CSR; + ETH->MMCCR |= ETH_MMCCR_CSR; } } @@ -2546,35 +2609,35 @@ void ETH_MMCCounterRolloverCmd(FunctionalState NewState) void ETH_MMCCountersReset(void) { /* Resets the MMC Counters */ - ETH->MMCCR |= ETH_MMCCR_CR; + ETH->MMCCR |= ETH_MMCCR_CR; } /** * @brief Enables or disables the specified ETHERNET MMC interrupts. * @param ETH_MMC_IT: specifies the ETHERNET MMC interrupt sources to be enabled or disabled. - * This parameter can be any combination of Tx interrupt or - * any combination of Rx interrupt (but not both)of the following values: - * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value - * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value - * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value - * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value - * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value + * This parameter can be any combination of Tx interrupt or + * any combination of Rx interrupt (but not both)of the following values: + * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value + * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value + * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value + * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value + * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value * @param NewState: new state of the specified ETHERNET MMC interrupts. * This parameter can be: ENABLE or DISABLE. * @retval None */ void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState) -{ +{ /* Check the parameters */ - assert_param(IS_ETH_MMC_IT(ETH_MMC_IT)); + assert_param(IS_ETH_MMC_IT(ETH_MMC_IT)); assert_param(IS_FUNCTIONAL_STATE(NewState)); - + if ((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET) { /* Remove register mak from IT */ ETH_MMC_IT &= 0xEFFFFFFF; - + /* ETHERNET MMC Rx interrupts selected */ if (NewState != DISABLE) { @@ -2584,7 +2647,7 @@ void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState) else { /* Disable the selected ETHERNET MMC interrupts */ - ETH->MMCRIMR |= ETH_MMC_IT; + ETH->MMCRIMR |= ETH_MMC_IT; } } else @@ -2598,8 +2661,8 @@ void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState) else { /* Disable the selected ETHERNET MMC interrupts */ - ETH->MMCTIMR |= ETH_MMC_IT; - } + ETH->MMCTIMR |= ETH_MMC_IT; + } } } @@ -2607,24 +2670,24 @@ void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState) * @brief Checks whether the specified ETHERNET MMC IT is set or not. * @param ETH_MMC_IT: specifies the ETHERNET MMC interrupt. * This parameter can be one of the following values: - * @arg ETH_MMC_IT_TxFCGC: When Tx good frame counter reaches half the maximum value - * @arg ETH_MMC_IT_TxMCGC: When Tx good multi col counter reaches half the maximum value - * @arg ETH_MMC_IT_TxSCGC: When Tx good single col counter reaches half the maximum value - * @arg ETH_MMC_IT_RxUGFC: When Rx good unicast frames counter reaches half the maximum value - * @arg ETH_MMC_IT_RxAEC : When Rx alignment error counter reaches half the maximum value - * @arg ETH_MMC_IT_RxCEC : When Rx crc error counter reaches half the maximum value + * @arg ETH_MMC_IT_TxFCGC: When Tx good frame counter reaches half the maximum value + * @arg ETH_MMC_IT_TxMCGC: When Tx good multi col counter reaches half the maximum value + * @arg ETH_MMC_IT_TxSCGC: When Tx good single col counter reaches half the maximum value + * @arg ETH_MMC_IT_RxUGFC: When Rx good unicast frames counter reaches half the maximum value + * @arg ETH_MMC_IT_RxAEC : When Rx alignment error counter reaches half the maximum value + * @arg ETH_MMC_IT_RxCEC : When Rx crc error counter reaches half the maximum value * @retval The value of ETHERNET MMC IT (SET or RESET). */ ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT) { ITStatus bitstatus = RESET; /* Check the parameters */ - assert_param(IS_ETH_MMC_GET_IT(ETH_MMC_IT)); - + assert_param(IS_ETH_MMC_GET_IT(ETH_MMC_IT)); + if ((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET) { /* ETHERNET MMC Rx interrupts selected */ - /* Check if the ETHERNET MMC Rx selected interrupt is enabled and occured */ + /* Check if the ETHERNET MMC Rx selected interrupt is enabled and occured */ if ((((ETH->MMCRIR & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRIMR & ETH_MMC_IT) == (uint32_t)RESET)) { bitstatus = SET; @@ -2637,7 +2700,7 @@ ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT) else { /* ETHERNET MMC Tx interrupts selected */ - /* Check if the ETHERNET MMC Tx selected interrupt is enabled and occured */ + /* Check if the ETHERNET MMC Tx selected interrupt is enabled and occured */ if ((((ETH->MMCTIR & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCTIMR & ETH_MMC_IT) == (uint32_t)RESET)) { bitstatus = SET; @@ -2645,9 +2708,9 @@ ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT) else { bitstatus = RESET; - } - } - + } + } + return bitstatus; } @@ -2655,24 +2718,24 @@ ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT) * @brief Get the specified ETHERNET MMC register value. * @param ETH_MMCReg: specifies the ETHERNET MMC register. * This parameter can be one of the following values: - * @arg ETH_MMCCR : MMC CR register - * @arg ETH_MMCRIR : MMC RIR register - * @arg ETH_MMCTIR : MMC TIR register - * @arg ETH_MMCRIMR : MMC RIMR register - * @arg ETH_MMCTIMR : MMC TIMR register - * @arg ETH_MMCTGFSCCR : MMC TGFSCCR register - * @arg ETH_MMCTGFMSCCR: MMC TGFMSCCR register + * @arg ETH_MMCCR : MMC CR register + * @arg ETH_MMCRIR : MMC RIR register + * @arg ETH_MMCTIR : MMC TIR register + * @arg ETH_MMCRIMR : MMC RIMR register + * @arg ETH_MMCTIMR : MMC TIMR register + * @arg ETH_MMCTGFSCCR : MMC TGFSCCR register + * @arg ETH_MMCTGFMSCCR: MMC TGFMSCCR register * @arg ETH_MMCTGFCR : MMC TGFCR register - * @arg ETH_MMCRFCECR : MMC RFCECR register - * @arg ETH_MMCRFAECR : MMC RFAECR register - * @arg ETH_MMCRGUFCR : MMC RGUFCRregister + * @arg ETH_MMCRFCECR : MMC RFCECR register + * @arg ETH_MMCRFAECR : MMC RFAECR register + * @arg ETH_MMCRGUFCR : MMC RGUFCRregister * @retval The value of ETHERNET MMC Register value. */ uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg) { /* Check the parameters */ assert_param(IS_ETH_MMC_REGISTER(ETH_MMCReg)); - + /* Return the selected register value */ return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_MMCReg)); } @@ -2681,34 +2744,34 @@ uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg) * @brief Sets the PTP node clock type. * @param ClockType: specifies the PTP node clock type. * This parameter can be one of the following values: - * @arg ETH_PTP_OrdinaryClock : Ordinary Clock. + * @arg ETH_PTP_OrdinaryClock : Ordinary Clock. * @arg ETH_PTP_BoundaryClock : Boundary Clock. - * @arg ETH_PTP_EndToEndTransparentClock : End To End Transparent Clock. - * @arg ETH_PTP_PeerToPeerTransparentClock : Peer To Peer Transparent Clock. + * @arg ETH_PTP_EndToEndTransparentClock : End To End Transparent Clock. + * @arg ETH_PTP_PeerToPeerTransparentClock : Peer To Peer Transparent Clock. * @retval None */ void ETH_PTPNodeClockTypeConfig(uint32_t ClockType) { /* Check the parameters */ - assert_param(IS_ETH_PTP_TYPE_CLOCK(ClockType)); + assert_param(IS_ETH_PTP_TYPE_CLOCK(ClockType)); /* Clear the PTP node clock type */ - ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSCR_TSCNT); - + ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSCR_TSCNT); + /* Set the new PTP node clock type */ - ETH->PTPTSCR |= ClockType; + ETH->PTPTSCR |= ClockType; } /** * @brief Enables or disables the selected PTP snapshot method. * @param SnapshotMethod: specifies the PTP snapshot method. * This parameter can be one of the following values: - * @arg ETH_PTP_SnapshotMasterMessage : snapshot for message relevant to master. + * @arg ETH_PTP_SnapshotMasterMessage : snapshot for message relevant to master. * @arg ETH_PTP_SnapshotEventMessage : snapshot for event message. - * @arg ETH_PTP_SnapshotIPV4Frames : snapshot for IPv4 frames. + * @arg ETH_PTP_SnapshotIPV4Frames : snapshot for IPv4 frames. * @arg ETH_PTP_SnapshotIPV6Frames : snapshot for IPv6 frames. - * @arg ETH_PTP_SnapshotPTPOverEthernetFrames : snapshot for PTP over ethernet frames. - * @arg ETH_PTP_SnapshotAllReceivedFrames : snapshot for all received frames. + * @arg ETH_PTP_SnapshotPTPOverEthernetFrames : snapshot for PTP over ethernet frames. + * @arg ETH_PTP_SnapshotAllReceivedFrames : snapshot for all received frames. * @param NewState: new state of the PTP snapshot method * This parameter can be: ENABLE or DISABLE. * @retval None @@ -2717,8 +2780,8 @@ void ETH_PTPSnapshotCmd(uint32_t SnapshotMethod, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_ETH_PTP_SNAPSHOT(SnapshotMethod)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) { /* Enable the selected PTP snapshot method */ @@ -2734,14 +2797,14 @@ void ETH_PTPSnapshotCmd(uint32_t SnapshotMethod, FunctionalState NewState) /** * @brief Enables or disables the PTP packet snooping version 2 format. * @param NewState: new state of the PTP packet snooping version 2 format - * This parameter can be: ENABLE or DISABLE. + * This parameter can be: ENABLE or DISABLE. * @retval None */ void ETH_PTPPacketSnoopingV2FormatCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); - + if (NewState != DISABLE) { /* Enable the PTP packet snooping version 2 format */ @@ -2757,14 +2820,14 @@ void ETH_PTPPacketSnoopingV2FormatCmd(FunctionalState NewState) /** * @brief Enables or disables the PTP Subsecond rollover. * @param NewState: new state of the PTP Subsecond rollover - * This parameter can be: ENABLE or DISABLE. + * This parameter can be: ENABLE or DISABLE. * @retval None */ void ETH_PTPSubSecondRolloverCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); - + if (NewState != DISABLE) { /* Enable the PTP Subsecond rollover */ @@ -2785,7 +2848,7 @@ void ETH_PTPSubSecondRolloverCmd(FunctionalState NewState) void ETH_EnablePTPTimeStampAddend(void) { /* Enable the PTP block update with the Time Stamp Addend register value */ - ETH->PTPTSCR |= ETH_PTPTSCR_TSARU; + ETH->PTPTSCR |= ETH_PTPTSCR_TSARU; } /** @@ -2796,7 +2859,7 @@ void ETH_EnablePTPTimeStampAddend(void) void ETH_EnablePTPTimeStampInterruptTrigger(void) { /* Enable the PTP target time interrupt */ - ETH->PTPTSCR |= ETH_PTPTSCR_TSITE; + ETH->PTPTSCR |= ETH_PTPTSCR_TSITE; } /** @@ -2807,7 +2870,7 @@ void ETH_EnablePTPTimeStampInterruptTrigger(void) void ETH_EnablePTPTimeStampUpdate(void) { /* Enable the PTP system time update with the Time Stamp Update register value */ - ETH->PTPTSCR |= ETH_PTPTSCR_TSSTU; + ETH->PTPTSCR |= ETH_PTPTSCR_TSSTU; } /** @@ -2818,22 +2881,22 @@ void ETH_EnablePTPTimeStampUpdate(void) void ETH_InitializePTPTimeStamp(void) { /* Initialize the PTP Time Stamp */ - ETH->PTPTSCR |= ETH_PTPTSCR_TSSTI; + ETH->PTPTSCR |= ETH_PTPTSCR_TSSTI; } /** * @brief Selects the PTP Update method * @param UpdateMethod: the PTP Update method * This parameter can be one of the following values: - * @arg ETH_PTP_FineUpdate : Fine Update method - * @arg ETH_PTP_CoarseUpdate : Coarse Update method + * @arg ETH_PTP_FineUpdate : Fine Update method + * @arg ETH_PTP_CoarseUpdate : Coarse Update method * @retval None */ void ETH_PTPUpdateMethodConfig(uint32_t UpdateMethod) { /* Check the parameters */ assert_param(IS_ETH_PTP_UPDATE(UpdateMethod)); - + if (UpdateMethod != ETH_PTP_CoarseUpdate) { /* Enable the PTP Fine Update method */ @@ -2843,7 +2906,7 @@ void ETH_PTPUpdateMethodConfig(uint32_t UpdateMethod) { /* Disable the PTP Coarse Update method */ ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSCR_TSFCU); - } + } } /** @@ -2856,7 +2919,7 @@ void ETH_PTPTimeStampCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); - + if (NewState != DISABLE) { /* Enable the PTP time stamp for transmit and receive frames */ @@ -2873,10 +2936,10 @@ void ETH_PTPTimeStampCmd(FunctionalState NewState) * @brief Checks whether the specified ETHERNET PTP flag is set or not. * @param ETH_PTP_FLAG: specifies the flag to check. * This parameter can be one of the following values: - * @arg ETH_PTP_FLAG_TSARU : Addend Register Update - * @arg ETH_PTP_FLAG_TSITE : Time Stamp Interrupt Trigger Enable - * @arg ETH_PTP_FLAG_TSSTU : Time Stamp Update - * @arg ETH_PTP_FLAG_TSSTI : Time Stamp Initialize + * @arg ETH_PTP_FLAG_TSARU : Addend Register Update + * @arg ETH_PTP_FLAG_TSITE : Time Stamp Interrupt Trigger Enable + * @arg ETH_PTP_FLAG_TSSTU : Time Stamp Update + * @arg ETH_PTP_FLAG_TSSTI : Time Stamp Initialize * @retval The new state of ETHERNET PTP Flag (SET or RESET). */ FlagStatus ETH_GetPTPFlagStatus(uint32_t ETH_PTP_FLAG) @@ -2902,7 +2965,7 @@ FlagStatus ETH_GetPTPFlagStatus(uint32_t ETH_PTP_FLAG) { flagpos &= ETH->PTPTSSR; } - + if (flagpos != (uint32_t)RESET) { bitstatus = SET; @@ -2925,16 +2988,16 @@ void ETH_SetPTPSubSecondIncrement(uint32_t SubSecondValue) /* Check the parameters */ assert_param(IS_ETH_PTP_SUBSECOND_INCREMENT(SubSecondValue)); /* Set the PTP Sub-Second Increment Register */ - ETH->PTPSSIR = SubSecondValue; + ETH->PTPSSIR = SubSecondValue; } /** * @brief Sets the Time Stamp update sign and values. * @param Sign: specifies the PTP Time update value sign. * This parameter can be one of the following values: - * @arg ETH_PTP_PositiveTime : positive time value. - * @arg ETH_PTP_NegativeTime : negative time value. - * @param SecondValue: specifies the PTP Time update second value. + * @arg ETH_PTP_PositiveTime : positive time value. + * @arg ETH_PTP_NegativeTime : negative time value. + * @param SecondValue: specifies the PTP Time update second value. * @param SubSecondValue: specifies the PTP Time update sub-second value. * This parameter is a 31 bit value, bit32 correspond to the sign. * @retval None @@ -2942,13 +3005,13 @@ void ETH_SetPTPSubSecondIncrement(uint32_t SubSecondValue) void ETH_SetPTPTimeStampUpdate(uint32_t Sign, uint32_t SecondValue, uint32_t SubSecondValue) { /* Check the parameters */ - assert_param(IS_ETH_PTP_TIME_SIGN(Sign)); - assert_param(IS_ETH_PTP_TIME_STAMP_UPDATE_SUBSECOND(SubSecondValue)); + assert_param(IS_ETH_PTP_TIME_SIGN(Sign)); + assert_param(IS_ETH_PTP_TIME_STAMP_UPDATE_SUBSECOND(SubSecondValue)); /* Set the PTP Time Update High Register */ ETH->PTPTSHUR = SecondValue; - + /* Set the PTP Time Update Low Register with sign */ - ETH->PTPTSLUR = Sign | SubSecondValue; + ETH->PTPTSLUR = Sign | SubSecondValue; } /** @@ -2959,7 +3022,7 @@ void ETH_SetPTPTimeStampUpdate(uint32_t Sign, uint32_t SecondValue, uint32_t Sub void ETH_SetPTPTimeStampAddend(uint32_t Value) { /* Set the PTP Time Stamp Addend Register */ - ETH->PTPTSAR = Value; + ETH->PTPTSAR = Value; } /** @@ -2973,29 +3036,29 @@ void ETH_SetPTPTargetTime(uint32_t HighValue, uint32_t LowValue) /* Set the PTP Target Time High Register */ ETH->PTPTTHR = HighValue; /* Set the PTP Target Time Low Register */ - ETH->PTPTTLR = LowValue; + ETH->PTPTTLR = LowValue; } /** * @brief Get the specified ETHERNET PTP register value. * @param ETH_PTPReg: specifies the ETHERNET PTP register. * This parameter can be one of the following values: - * @arg ETH_PTPTSCR : Sub-Second Increment Register - * @arg ETH_PTPSSIR : Sub-Second Increment Register + * @arg ETH_PTPTSCR : Sub-Second Increment Register + * @arg ETH_PTPSSIR : Sub-Second Increment Register * @arg ETH_PTPTSHR : Time Stamp High Register - * @arg ETH_PTPTSLR : Time Stamp Low Register - * @arg ETH_PTPTSHUR : Time Stamp High Update Register + * @arg ETH_PTPTSLR : Time Stamp Low Register + * @arg ETH_PTPTSHUR : Time Stamp High Update Register * @arg ETH_PTPTSLUR : Time Stamp Low Update Register * @arg ETH_PTPTSAR : Time Stamp Addend Register - * @arg ETH_PTPTTHR : Target Time High Register - * @arg ETH_PTPTTLR : Target Time Low Register + * @arg ETH_PTPTTHR : Target Time High Register + * @arg ETH_PTPTTLR : Target Time Low Register * @retval The value of ETHERNET PTP Register value. */ uint32_t ETH_GetPTPRegister(uint32_t ETH_PTPReg) { /* Check the parameters */ assert_param(IS_ETH_PTP_REGISTER(ETH_PTPReg)); - + /* Return the selected register value */ return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_PTPReg)); } @@ -3003,7 +3066,7 @@ uint32_t ETH_GetPTPRegister(uint32_t ETH_PTPReg) #ifdef USE_ENHANCED_DMA_DESCRIPTORS /** * @brief Initializes the DMA Tx descriptors in chain mode with PTP. - * @param DMAPTPTxDescTab: Pointer on the first Tx desc list + * @param DMAPTPTxDescTab: Pointer on the first Tx desc list * @param TxBuff: Pointer on the first TxBuffer list * @param TxBuffCount: Number of the used Tx desc in the list * @retval None @@ -3012,22 +3075,22 @@ void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMAPTPTxDescTab, uint8_t* TxB { uint32_t i = 0; ETH_DMADESCTypeDef *DMAPTPTxDesc; - + /* Set the DMAPTPTxDescToSet pointer with the first one of the DMAPTPTxDescTab list */ DMAPTPTxDescToSet = DMAPTPTxDescTab; - /* Fill each DMAPTPTxDesc descriptor with the right values */ + /* Fill each DMAPTPTxDesc descriptor with the right values */ for(i=0; i < TxBuffCount; i++) { /* Get the pointer on the ith member of the Tx Desc list */ DMAPTPTxDesc = DMAPTPTxDescTab + i; /* Set Second Address Chained bit */ - DMAPTPTxDesc->Status = ETH_DMATxDesc_TCH | ETH_DMATxDesc_TTSE; - + DMAPTPTxDesc->Status = ETH_DMATxDesc_TCH | ETH_DMATxDesc_TTSE; + /* Set Buffer1 address pointer */ DMAPTPTxDesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_MAX_PACKET_SIZE]); - + /* Initialize the next descriptor with the Next Desciptor Polling Enable */ if(i < (TxBuffCount-1)) { @@ -3036,13 +3099,13 @@ void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMAPTPTxDescTab, uint8_t* TxB } else { - /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ - DMAPTPTxDesc->Buffer2NextDescAddr = (uint32_t) DMAPTPTxDescTab; + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + DMAPTPTxDesc->Buffer2NextDescAddr = (uint32_t) DMAPTPTxDescTab; } } - + /* Set Transmit Desciptor List Address Register */ - ETH->DMATDLAR = (uint32_t) DMAPTPTxDescTab; + ETH->DMATDLAR = (uint32_t) DMAPTPTxDescTab; } /** @@ -3056,9 +3119,9 @@ void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMAPTPRxDescTab, uint8_t *RxB { uint32_t i = 0; ETH_DMADESCTypeDef *DMAPTPRxDesc; - + /* Set the DMAPTPRxDescToGet pointer with the first one of the DMAPTPRxDescTab list */ - DMAPTPRxDescToGet = DMAPTPRxDescTab; + DMAPTPRxDescToGet = DMAPTPRxDescTab; /* Fill each DMAPTPRxDesc descriptor with the right values */ for(i=0; i < RxBuffCount; i++) @@ -3068,28 +3131,28 @@ void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMAPTPRxDescTab, uint8_t *RxB /* Set Own bit of the Rx descriptor Status */ DMAPTPRxDesc->Status = ETH_DMARxDesc_OWN; - + /* Set Buffer1 size and Second Address Chained bit */ - DMAPTPRxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_MAX_PACKET_SIZE; + DMAPTPRxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_MAX_PACKET_SIZE; /* Set Buffer1 address pointer */ DMAPTPRxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_MAX_PACKET_SIZE]); - + /* Initialize the next descriptor with the Next Desciptor Polling Enable */ if(i < (RxBuffCount-1)) { /* Set next descriptor address register with next descriptor base address */ - DMAPTPRxDesc->Buffer2NextDescAddr = (uint32_t)(DMAPTPRxDescTab+i+1); + DMAPTPRxDesc->Buffer2NextDescAddr = (uint32_t)(DMAPTPRxDescTab+i+1); } else { - /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ - DMAPTPRxDesc->Buffer2NextDescAddr = (uint32_t)(DMAPTPRxDescTab); + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + DMAPTPRxDesc->Buffer2NextDescAddr = (uint32_t)(DMAPTPRxDescTab); } } - + /* Set Receive Desciptor List Address Register */ - ETH->DMARDLAR = (uint32_t) DMAPTPRxDescTab; + ETH->DMARDLAR = (uint32_t) DMAPTPRxDescTab; } #endif /* USE_ENHANCED_DMA_DESCRIPTORS */ @@ -3102,26 +3165,26 @@ void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMAPTPRxDescTab, uint8_t *RxB * ETH_SUCCESS: for correct transmission */ uint32_t ETH_HandlePTPTxPkt(uint8_t *ppkt, uint16_t FrameLength, uint32_t *PTPTxTab) -{ +{ uint32_t offset = 0, timeout = 0; - + /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ if((DMAPTPTxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET) { /* Return ERROR: OWN bit set */ return ETH_ERROR; } - - /* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */ - for(offset=0; offsetBuffer1Addr) + offset)) = (*(ppkt + offset)); } - + /* Setting the Frame Length: bits[12:0] */ DMAPTPTxDescToSet->ControlBufferSize = (FrameLength & ETH_DMATxDesc_TBS1); - /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */ + /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */ DMAPTPTxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS; /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ @@ -3150,65 +3213,65 @@ uint32_t ETH_HandlePTPTxPkt(uint8_t *ppkt, uint16_t FrameLength, uint32_t *PTPTx /* Clear the DMATxDescToSet status register TTSS flag */ DMATxDescToSet->Status &= ~ETH_DMATxDesc_TTSS; - + *PTPTxTab++ = DMAPTPTxDescToSet->TimeStampLow; *PTPTxTab = DMAPTPTxDescToSet->TimeStampHigh; - - /* Update the ETHERNET DMA global Tx descriptor with next Tx decriptor */ + + /* Update the ETHERNET DMA global Tx descriptor with next Tx decriptor */ /* Chained Mode */ if((DMAPTPTxDescToSet->Status & ETH_DMATxDesc_TCH) != (uint32_t)RESET) - { - /* Selects the next DMA Tx descriptor list for next buffer to send */ - DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) (DMAPTPTxDescToSet->Buffer2NextDescAddr); + { + /* Selects the next DMA Tx descriptor list for next buffer to send */ + DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) (DMAPTPTxDescToSet->Buffer2NextDescAddr); } else /* Ring Mode */ - { + { if((DMAPTPTxDescToSet->Status & ETH_DMATxDesc_TER) != (uint32_t)RESET) { /* Selects the first DMA Tx descriptor for next buffer to send: last Tx descriptor was used */ - DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLAR); + DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLAR); } else - { + { /* Selects the next DMA Tx descriptor list for next buffer to send */ - DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMAPTPTxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMAPTPTxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); } } /* Return SUCCESS */ - return ETH_SUCCESS; + return ETH_SUCCESS; } /** * @brief Receives a packet and copies it to memory pointed by ppkt with Time Stamp values. - * @param ppkt: pointer to application packet receive buffer. + * @param ppkt: pointer to application packet receive buffer. * @param PTPRxTab: Pointer on the first PTP Rx table to store Time stamp values. * @retval ETH_ERROR: if there is error in reception * framelength: received packet size if packet reception is correct */ uint32_t ETH_HandlePTPRxPkt(uint8_t *ppkt, uint32_t *PTPRxTab) -{ +{ uint32_t offset = 0, framelength = 0; /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ if((DMAPTPRxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET) { /* Return error: OWN bit set */ - return ETH_ERROR; + return ETH_ERROR; } - - if(((DMAPTPRxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && - ((DMAPTPRxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) && - ((DMAPTPRxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)) - { - /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ - framelength = ((DMAPTPRxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT) - 4; - /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */ - for(offset=0; offsetStatus & ETH_DMARxDesc_ES) == (uint32_t)RESET) && + ((DMAPTPRxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) && + ((DMAPTPRxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)) + { + /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ + framelength = ((DMAPTPRxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT) - 4; + + /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */ + for(offset=0; offsetBuffer1Addr) + offset)); - } + } } else { @@ -3218,42 +3281,42 @@ uint32_t ETH_HandlePTPRxPkt(uint8_t *ppkt, uint32_t *PTPRxTab) *PTPRxTab++ = DMAPTPRxDescToGet->TimeStampLow; *PTPRxTab = DMAPTPRxDescToGet->TimeStampHigh; - + /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */ - DMAPTPRxDescToGet->Status = ETH_DMARxDesc_OWN; - + DMAPTPRxDescToGet->Status = ETH_DMARxDesc_OWN; + /* When Rx Buffer unavailable flag is set: clear it and resume reception */ - if ((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET) + if ((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET) { /* Clear RBUS ETHERNET DMA flag */ ETH->DMASR = ETH_DMASR_RBUS; /* Resume DMA reception */ ETH->DMARPDR = 0; } - - /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */ + + /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */ /* Chained Mode */ if((DMAPTPRxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET) - { - /* Selects the next DMA Rx descriptor list for next buffer to read */ - DMAPTPRxDescToGet = (ETH_DMADESCTypeDef*) (DMAPTPRxDescToGet->Buffer2NextDescAddr); + { + /* Selects the next DMA Rx descriptor list for next buffer to read */ + DMAPTPRxDescToGet = (ETH_DMADESCTypeDef*) (DMAPTPRxDescToGet->Buffer2NextDescAddr); } else /* Ring Mode */ - { + { if((DMAPTPRxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET) { /* Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used */ - DMAPTPRxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR); + DMAPTPRxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR); } else - { + { /* Selects the next DMA Rx descriptor list for next buffer to read */ - DMAPTPRxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMAPTPRxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + DMAPTPRxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMAPTPRxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); } } - + /* Return Frame Length/ERROR */ - return (framelength); + return (framelength); } #ifndef USE_Delay @@ -3264,7 +3327,7 @@ uint32_t ETH_HandlePTPRxPkt(uint8_t *ppkt, uint32_t *PTPRxTab) */ static void ETH_Delay(__IO uint32_t nCount) { - __IO uint32_t index = 0; + __IO uint32_t index = 0; for(index = nCount; index != 0; index--) { } @@ -3322,8 +3385,6 @@ void ETH_IRQHandler(void) status = ETH->DMASR; - rt_kprintf("ETH ISR\n"); - /* Clear received IT */ if ((status & ETH_DMA_IT_NIS) != (u32)RESET) ETH->DMASR = (u32)ETH_DMA_IT_NIS; @@ -3363,6 +3424,12 @@ static rt_err_t rt_stm32_eth_init(rt_device_t dev) { ETH_InitTypeDef ETH_InitStructure; + /* Enable ETHERNET clock */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_ETH_MAC | RCC_AHB1Periph_ETH_MAC_Tx | + RCC_AHB1Periph_ETH_MAC_Rx, ENABLE); + + SYSCFG_ETH_MediaInterfaceConfig(SYSCFG_ETH_MediaInterface_RMII); + /* Reset ETHERNET on AHB Bus */ ETH_DeInit(); @@ -3372,13 +3439,16 @@ static rt_err_t rt_stm32_eth_init(rt_device_t dev) /* Wait for software reset */ while (ETH_GetSoftwareResetStatus() == SET); - /* ETHERNET Configuration ------------------------------------------------------*/ + /* ETHERNET Configuration --------------------------------------------------*/ /* Call ETH_StructInit if you don't like to configure all ETH_InitStructure parameter */ ETH_StructInit(Ð_InitStructure); /* Fill ETH_InitStructure parametrs */ /*------------------------ MAC -----------------------------------*/ ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Enable; + //ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Disable; + // ETH_InitStructure.ETH_Speed = ETH_Speed_10M; + // ETH_InitStructure.ETH_Mode = ETH_Mode_FullDuplex; ETH_InitStructure.ETH_LoopbackMode = ETH_LoopbackMode_Disable; ETH_InitStructure.ETH_RetryTransmission = ETH_RetryTransmission_Disable; @@ -3392,40 +3462,40 @@ static rt_err_t rt_stm32_eth_init(rt_device_t dev) ETH_InitStructure.ETH_ChecksumOffload = ETH_ChecksumOffload_Enable; #endif - /*------------------------ DMA -----------------------------------*/ - - /* When we use the Checksum offload feature, we need to enable the Store and Forward mode: - the store and forward guarantee that a whole frame is stored in the FIFO, so the MAC can insert/verify the checksum, + /*------------------------ DMA -----------------------------------*/ + + /* When we use the Checksum offload feature, we need to enable the Store and Forward mode: + the store and forward guarantee that a whole frame is stored in the FIFO, so the MAC can insert/verify the checksum, if the checksum is OK the DMA can handle the frame otherwise the frame is dropped */ - ETH_InitStructure.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Enable; - ETH_InitStructure.ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable; - ETH_InitStructure.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable; - - ETH_InitStructure.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable; - ETH_InitStructure.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable; + ETH_InitStructure.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Enable; + ETH_InitStructure.ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable; + ETH_InitStructure.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable; + + ETH_InitStructure.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable; + ETH_InitStructure.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable; ETH_InitStructure.ETH_SecondFrameOperate = ETH_SecondFrameOperate_Enable; - ETH_InitStructure.ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable; - ETH_InitStructure.ETH_FixedBurst = ETH_FixedBurst_Enable; - ETH_InitStructure.ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat; + ETH_InitStructure.ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable; + ETH_InitStructure.ETH_FixedBurst = ETH_FixedBurst_Enable; + ETH_InitStructure.ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat; ETH_InitStructure.ETH_TxDMABurstLength = ETH_TxDMABurstLength_32Beat; ETH_InitStructure.ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_2_1; /* Configure Ethernet */ ETH_Init(Ð_InitStructure, DP83848_PHY_ADDRESS); - /* Enable DMA Receive interrupt (need to enable in this case Normal interrupt) */ - ETH_DMAITConfig(ETH_DMA_IT_NIS | ETH_DMA_IT_R, ENABLE); + /* Enable DMA Receive interrupt (need to enable in this case Normal interrupt) */ + ETH_DMAITConfig(ETH_DMA_IT_NIS | ETH_DMA_IT_R, ENABLE); - /* Initialize Tx Descriptors list: Chain Mode */ - ETH_DMATxDescChainInit(DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB); - /* Initialize Rx Descriptors list: Chain Mode */ - ETH_DMARxDescChainInit(DMARxDscrTab, &Rx_Buff[0][0], ETH_RXBUFNB); + /* Initialize Tx Descriptors list: Chain Mode */ + ETH_DMATxDescChainInit(DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB); + /* Initialize Rx Descriptors list: Chain Mode */ + ETH_DMARxDescChainInit(DMARxDscrTab, &Rx_Buff[0][0], ETH_RXBUFNB); - /* MAC address configuration */ - ETH_MACAddressConfig(ETH_MAC_Address0, (u8*)&stm32_eth_device.dev_addr[0]); + /* MAC address configuration */ + ETH_MACAddressConfig(ETH_MAC_Address0, (u8*)&stm32_eth_device.dev_addr[0]); - /* Enable MAC and DMA transmission and reception */ - ETH_Start(); + /* Enable MAC and DMA transmission and reception */ + ETH_Start(); return RT_EOK; } @@ -3630,20 +3700,6 @@ struct pbuf *rt_stm32_eth_rx(rt_device_t dev) return p; } -static void RCC_Configuration(void) -{ - /* Enable GPIOs clocks */ - RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB | - RCC_AHB1Periph_GPIOC, ENABLE); - - /* Enable SYSCFG and ADC3 clocks */ - RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG | RCC_APB2Periph_ADC3, ENABLE); - - /* Enable MAC clocks */ - RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_ETH_MAC | RCC_AHB1Periph_ETH_MAC_Tx | - RCC_AHB1Periph_ETH_MAC_Rx, ENABLE); -} - static void NVIC_Configuration(void) { NVIC_InitTypeDef NVIC_InitStructure; @@ -3653,7 +3709,7 @@ static void NVIC_Configuration(void) NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2; NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - NVIC_Init(&NVIC_InitStructure); + NVIC_Init(&NVIC_InitStructure); } /* @@ -3662,65 +3718,83 @@ static void NVIC_Configuration(void) static void GPIO_Configuration(void) { GPIO_InitTypeDef GPIO_InitStructure; + __IO int i; - /* Configure PA1, PA2 and PA7 */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_7; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_25MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ; - GPIO_Init(GPIOA, &GPIO_InitStructure); - GPIO_PinAFConfig(GPIOA, GPIO_PinSource1, GPIO_AF_ETH); - GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_ETH); - GPIO_PinAFConfig(GPIOA, GPIO_PinSource7, GPIO_AF_ETH); + /* Enable GPIOs clocks */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB | + RCC_AHB1Periph_GPIOC + , ENABLE); - /* Configure PB5 and PB8 */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_8; - GPIO_Init(GPIOB, &GPIO_InitStructure); - GPIO_PinAFConfig(GPIOB, GPIO_PinSource5, GPIO_AF_ETH); - GPIO_PinAFConfig(GPIOB, GPIO_PinSource8, GPIO_AF_ETH); - - /* Configure PC1, PC2, PC3, PC4 and PC5 */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5; - GPIO_Init(GPIOC, &GPIO_InitStructure); - GPIO_PinAFConfig(GPIOC, GPIO_PinSource1, GPIO_AF_ETH); - GPIO_PinAFConfig(GPIOC, GPIO_PinSource2, GPIO_AF_ETH); - GPIO_PinAFConfig(GPIOC, GPIO_PinSource3, GPIO_AF_ETH); - GPIO_PinAFConfig(GPIOC, GPIO_PinSource4, GPIO_AF_ETH); - GPIO_PinAFConfig(GPIOC, GPIO_PinSource5, GPIO_AF_ETH); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13; - GPIO_Init(GPIOB, &GPIO_InitStructure); - - GPIO_PinAFConfig(GPIOB, GPIO_PinSource11, GPIO_AF_ETH); - GPIO_PinAFConfig(GPIOB, GPIO_PinSource12, GPIO_AF_ETH); - GPIO_PinAFConfig(GPIOB, GPIO_PinSource13, GPIO_AF_ETH); - - /* for RMII mode you have to set the system clock frequency to 100MHz, - you can do this in system_stm32f2xx.c file */ + /* Enable SYSCFG clock */ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); /* Configure MCO (PA8) */ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; GPIO_Init(GPIOA, &GPIO_InitStructure); /* Output PLL clock divided by 2 (50MHz) on MCO pin (PA8) to clock the PHY */ RCC_MCO1Config(RCC_MCO1Source_PLLCLK, RCC_MCO1Div_2); - SYSCFG_ETH_MediaInterfaceConfig(SYSCFG_ETH_MediaInterface_RMII); +/* Ethernet pins configuration ************************************************/ + + /* + ETH_MDIO -------------------------> PA2 + ETH_MDC --------------------------> PC1 + ETH_MII_RX_CLK/ETH_RMII_REF_CLK---> PA1 + ETH_MII_RX_DV/ETH_RMII_CRS_DV ----> PA7 + ETH_MII_RXD0/ETH_RMII_RXD0 -------> PC4 + ETH_MII_RXD1/ETH_RMII_RXD1 -------> PC5 + ETH_MII_TX_EN/ETH_RMII_TX_EN -----> PB11 + ETH_MII_TXD0/ETH_RMII_TXD0 -------> PB12 + ETH_MII_TXD1/ETH_RMII_TXD1 -------> PB13 + */ + /* Configure PC1, PC2, PC3, PC4 and PC5 */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 |GPIO_Pin_4 | GPIO_Pin_5; + GPIO_Init(GPIOC, &GPIO_InitStructure); + GPIO_PinAFConfig(GPIOC, GPIO_PinSource1, GPIO_AF_ETH); + GPIO_PinAFConfig(GPIOC, GPIO_PinSource4, GPIO_AF_ETH); + GPIO_PinAFConfig(GPIOC, GPIO_PinSource5, GPIO_AF_ETH); + + /* Configure PB11, PB14 and PB13 */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_PinAFConfig(GPIOB, GPIO_PinSource11, GPIO_AF_ETH); + GPIO_PinAFConfig(GPIOB, GPIO_PinSource12, GPIO_AF_ETH); + GPIO_PinAFConfig(GPIOB, GPIO_PinSource13, GPIO_AF_ETH); + + /* Configure PA1, PA2 and PA7 */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1|GPIO_Pin_2 | GPIO_Pin_7; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_PinAFConfig(GPIOA, GPIO_PinSource1, GPIO_AF_ETH); + GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_ETH); + GPIO_WriteBit(GPIOA,GPIO_Pin_7,Bit_RESET); + + GPIO_WriteBit(GPIOB,GPIO_Pin_0,Bit_RESET); + i=100000; + while(i--); + GPIO_WriteBit(GPIOB,GPIO_Pin_0,Bit_SET); + GPIO_WriteBit(GPIOA,GPIO_Pin_7,Bit_SET); + + GPIO_PinAFConfig(GPIOA, GPIO_PinSource7, GPIO_AF_ETH); } void rt_hw_stm32_eth_init(void) { - RCC_Configuration(); GPIO_Configuration(); NVIC_Configuration(); + // OUI 00-80-E1 STMICROELECTRONICS stm32_eth_device.dev_addr[0] = 0x00; - stm32_eth_device.dev_addr[1] = 0x60; - stm32_eth_device.dev_addr[2] = 0x6E; - stm32_eth_device.dev_addr[3] = 0x11; - stm32_eth_device.dev_addr[4] = 0x22; - stm32_eth_device.dev_addr[5] = 0x33; + stm32_eth_device.dev_addr[1] = 0x80; + stm32_eth_device.dev_addr[2] = 0xE1; + // generate MAC addr from 96bit unique ID (only for test) + stm32_eth_device.dev_addr[3] = *(rt_uint8_t*)(0x1FFF7A10+7); + stm32_eth_device.dev_addr[4] = *(rt_uint8_t*)(0x1FFF7A10+8); + stm32_eth_device.dev_addr[5] = *(rt_uint8_t*)(0x1FFF7A10+9); stm32_eth_device.parent.parent.init = rt_stm32_eth_init; stm32_eth_device.parent.parent.open = rt_stm32_eth_open; diff --git a/bsp/stm32f20x/system_stm32f2xx_eth_rmii_mco.c b/bsp/stm32f20x/system_stm32f2xx_eth_rmii_mco.c new file mode 100644 index 0000000000..caeedbf05c --- /dev/null +++ b/bsp/stm32f20x/system_stm32f2xx_eth_rmii_mco.c @@ -0,0 +1,536 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.0.0 + * @date 18-April-2011 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 100000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 100000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 200 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 4 +#define PLL_N 64 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 4 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 100000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f20x/usart.c b/bsp/stm32f20x/usart.c index 9a4c035bb0..7687a9831c 100644 --- a/bsp/stm32f20x/usart.c +++ b/bsp/stm32f20x/usart.c @@ -45,6 +45,17 @@ struct stm32_serial_device uart1 = struct rt_device uart1_device; #endif +#ifdef RT_USING_UART6 +struct stm32_serial_int_rx uart6_int_rx; +struct stm32_serial_device uart6 = +{ + USART6, + &uart6_int_rx, + RT_NULL +}; +struct rt_device uart6_device; +#endif + #ifdef RT_USING_UART2 struct stm32_serial_int_rx uart2_int_rx; struct stm32_serial_device uart2 = @@ -103,6 +114,14 @@ struct rt_device uart3_device; #define UART3_TX_DMA DMA1_Channel2 #define UART3_RX_DMA DMA1_Channel3 +/* USART6_REMAP = 0 */ +#define UART6_GPIO_TX GPIO_Pin_6 +#define UART6_GPIO_RX GPIO_Pin_7 +#define UART6_GPIO GPIOC +#define RCC_APBPeriph_UART6 RCC_APB2Periph_USART6 +//#define UART1_TX_DMA DMA1_Channel? +//#define UART1_RX_DMA DMA1_Channel? + static void RCC_Configuration(void) { #ifdef RT_USING_UART1 @@ -110,6 +129,12 @@ static void RCC_Configuration(void) RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE); RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE); #endif + +#ifdef RT_USING_UART6 + /* Enable USART6 and GPIOC clocks */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOC, ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART6, ENABLE); +#endif } static void GPIO_Configuration(void) @@ -120,13 +145,26 @@ static void GPIO_Configuration(void) GPIO_InitStruct.GPIO_Mode=GPIO_Mode_AF; GPIO_InitStruct.GPIO_Speed=GPIO_Speed_50MHz; GPIO_InitStruct.GPIO_OType=GPIO_OType_PP; - GPIO_InitStruct.GPIO_PuPd=GPIO_PuPd_UP; + GPIO_InitStruct.GPIO_PuPd=GPIO_PuPd_UP; GPIO_InitStruct.GPIO_Pin=GPIO_Pin_9|GPIO_Pin_10; GPIO_Init(GPIOA,&GPIO_InitStruct); - GPIO_PinAFConfig(GPIOA, GPIO_PinSource9, GPIO_AF_USART1); - GPIO_PinAFConfig(GPIOA, GPIO_PinSource10, GPIO_AF_USART1); + GPIO_PinAFConfig(GPIOA, GPIO_PinSource9, GPIO_AF_USART1); + GPIO_PinAFConfig(GPIOA, GPIO_PinSource10, GPIO_AF_USART1); +#endif + +#ifdef RT_USING_UART6 + GPIO_InitStruct.GPIO_Mode=GPIO_Mode_AF; + GPIO_InitStruct.GPIO_Speed=GPIO_Speed_50MHz; + GPIO_InitStruct.GPIO_OType=GPIO_OType_PP; + GPIO_InitStruct.GPIO_PuPd=GPIO_PuPd_UP; + + GPIO_InitStruct.GPIO_Pin=UART6_GPIO_TX|UART6_GPIO_RX; + GPIO_Init(UART6_GPIO,&GPIO_InitStruct); + + GPIO_PinAFConfig(UART6_GPIO, GPIO_PinSource6, GPIO_AF_USART6); + GPIO_PinAFConfig(UART6_GPIO, GPIO_PinSource7, GPIO_AF_USART6); #endif } @@ -142,6 +180,15 @@ static void NVIC_Configuration(void) NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; NVIC_Init(&NVIC_InitStructure); #endif + +#ifdef RT_USING_UART6 + /* Enable the USART1 Interrupt */ + NVIC_InitStructure.NVIC_IRQChannel = USART6_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); +#endif } /* @@ -160,7 +207,7 @@ void rt_hw_usart_init() /* uart init */ #ifdef RT_USING_UART1 - USART_DeInit(USART1); + USART_DeInit(USART1); USART_InitStructure.USART_BaudRate = 115200; USART_InitStructure.USART_WordLength = USART_WordLength_8b; USART_InitStructure.USART_StopBits = USART_StopBits_1; @@ -181,8 +228,33 @@ void rt_hw_usart_init() USART_Cmd(USART1, ENABLE); USART_ClearFlag(USART1,USART_FLAG_TXE); #endif + + /* uart init */ +#ifdef RT_USING_UART6 + USART_DeInit(USART6); + USART_InitStructure.USART_BaudRate = 115200; + USART_InitStructure.USART_WordLength = USART_WordLength_8b; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No ; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + + USART_Init(USART6, &USART_InitStructure); + + /* register uart1 */ + rt_hw_serial_register(&uart6_device, "uart6", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart6); + + /* enable interrupt */ + USART_ITConfig(USART6, USART_IT_RXNE, ENABLE); + /* Enable USART6 */ + USART_Cmd(USART6, ENABLE); + USART_ClearFlag(USART6,USART_FLAG_TXE); +#endif } +#ifdef RT_USING_UART1 void USART1_IRQHandler() { /* enter interrupt */ @@ -193,3 +265,17 @@ void USART1_IRQHandler() /* leave interrupt */ rt_interrupt_leave(); } +#endif + +#ifdef RT_USING_UART6 +void USART6_IRQHandler() +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_hw_serial_isr(&uart6_device); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif