add stm32f2xx eth driver
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1649 bbd45198-f89e-11dd-88c7-29a3b14d5316
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wuyangyong
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aeff05a873
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/**
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******************************************************************************
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* @file system_stm32f2xx.c
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* @author MCD Application Team
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* @version V1.0.0
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* @date 18-April-2011
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* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
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* This file contains the system clock configuration for STM32F2xx devices,
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* and is generated by the clock configuration tool
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* "STM32f2xx_Clock_Configuration_V1.0.0.xls"
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*
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* 1. This file provides two functions and one global variable to be called from
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* user application:
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* - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
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* and Divider factors, AHB/APBx prescalers and Flash settings),
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* depending on the configuration made in the clock xls tool.
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* This function is called at startup just after reset and
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* before branch to main program. This call is made inside
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* the "startup_stm32f2xx.s" file.
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*
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* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
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* by the user application to setup the SysTick
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* timer or configure other parameters.
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*
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* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
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* be called whenever the core clock is changed
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* during program execution.
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*
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* 2. After each device reset the HSI (16 MHz) is used as system clock source.
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* Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to
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* configure the system clock before to branch to main program.
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*
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* 3. If the system clock source selected by user fails to startup, the SystemInit()
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* function will do nothing and HSI still used as system clock source. User can
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* add some code to deal with this issue inside the SetSysClock() function.
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*
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* 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define
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* in "stm32f2xx.h" file. When HSE is used as system clock source, directly or
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* through PLL, and you are using different crystal you have to adapt the HSE
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* value to your own configuration.
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*
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* 5. This file configures the system clock as follows:
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*=============================================================================
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*=============================================================================
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* Supported STM32F2xx device revision | Rev B and Y
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*-----------------------------------------------------------------------------
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* System Clock source | PLL (HSE)
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*-----------------------------------------------------------------------------
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* SYSCLK(Hz) | 100000000
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*-----------------------------------------------------------------------------
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* HCLK(Hz) | 100000000
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*-----------------------------------------------------------------------------
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* AHB Prescaler | 1
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*-----------------------------------------------------------------------------
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* APB1 Prescaler | 4
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*-----------------------------------------------------------------------------
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* APB2 Prescaler | 2
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*-----------------------------------------------------------------------------
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* HSE Frequency(Hz) | 25000000
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*-----------------------------------------------------------------------------
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* PLL_M | 25
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*-----------------------------------------------------------------------------
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* PLL_N | 200
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*-----------------------------------------------------------------------------
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* PLL_P | 2
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*-----------------------------------------------------------------------------
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* PLL_Q | 5
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*-----------------------------------------------------------------------------
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* PLLI2S_N | NA
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*-----------------------------------------------------------------------------
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* PLLI2S_R | NA
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*-----------------------------------------------------------------------------
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* I2S input clock | NA
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*-----------------------------------------------------------------------------
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* VDD(V) | 3.3
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*-----------------------------------------------------------------------------
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* Flash Latency(WS) | 3
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*-----------------------------------------------------------------------------
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* Prefetch Buffer | ON
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*-----------------------------------------------------------------------------
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* Instruction cache | ON
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*-----------------------------------------------------------------------------
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* Data cache | ON
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*-----------------------------------------------------------------------------
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* Require 48MHz for USB OTG FS, | Enabled
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* SDIO and RNG clock |
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*-----------------------------------------------------------------------------
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*=============================================================================
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******************************************************************************
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* @attention
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*
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*
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* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
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******************************************************************************
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*/
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup stm32f2xx_system
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* @{
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*/
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/** @addtogroup STM32F2xx_System_Private_Includes
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* @{
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*/
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#include "stm32f2xx.h"
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/**
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* @}
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*/
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/** @addtogroup STM32F2xx_System_Private_TypesDefinitions
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32F2xx_System_Private_Defines
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* @{
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*/
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/*!< Uncomment the following line if you need to use external SRAM mounted
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on STM322xG_EVAL board as data memory */
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/* #define DATA_IN_ExtSRAM */
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/*!< Uncomment the following line if you need to relocate your vector Table in
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Internal SRAM. */
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/* #define VECT_TAB_SRAM */
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#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
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This value must be a multiple of 0x200. */
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/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
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#define PLL_M 4
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#define PLL_N 64
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/* SYSCLK = PLL_VCO / PLL_P */
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#define PLL_P 4
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/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */
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#define PLL_Q 5
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/**
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* @}
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*/
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/** @addtogroup STM32F2xx_System_Private_Macros
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32F2xx_System_Private_Variables
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* @{
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*/
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uint32_t SystemCoreClock = 100000000;
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__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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/**
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* @}
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*/
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/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes
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* @{
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*/
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static void SetSysClock(void);
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#ifdef DATA_IN_ExtSRAM
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static void SystemInit_ExtMemCtl(void);
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#endif /* DATA_IN_ExtSRAM */
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/**
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* @}
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*/
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/** @addtogroup STM32F2xx_System_Private_Functions
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* @{
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*/
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/**
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* @brief Setup the microcontroller system
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* Initialize the Embedded Flash Interface, the PLL and update the
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* SystemFrequency variable.
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* @param None
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* @retval None
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*/
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void SystemInit(void)
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{
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/* Reset the RCC clock configuration to the default reset state ------------*/
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/* Set HSION bit */
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RCC->CR |= (uint32_t)0x00000001;
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/* Reset CFGR register */
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RCC->CFGR = 0x00000000;
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/* Reset HSEON, CSSON and PLLON bits */
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RCC->CR &= (uint32_t)0xFEF6FFFF;
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/* Reset PLLCFGR register */
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RCC->PLLCFGR = 0x24003010;
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/* Reset HSEBYP bit */
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RCC->CR &= (uint32_t)0xFFFBFFFF;
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/* Disable all interrupts */
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RCC->CIR = 0x00000000;
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#ifdef DATA_IN_ExtSRAM
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SystemInit_ExtMemCtl();
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#endif /* DATA_IN_ExtSRAM */
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/* Configure the System clock source, PLL Multiplier and Divider factors,
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AHB/APBx prescalers and Flash settings ----------------------------------*/
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SetSysClock();
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/* Configure the Vector Table location add offset address ------------------*/
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#ifdef VECT_TAB_SRAM
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SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
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#else
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SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
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#endif
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}
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/**
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* @brief Update SystemCoreClock variable according to Clock Register Values.
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* The SystemCoreClock variable contains the core clock (HCLK), it can
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* be used by the user application to setup the SysTick timer or configure
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* other parameters.
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*
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* @note Each time the core clock (HCLK) changes, this function must be called
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* to update SystemCoreClock variable value. Otherwise, any configuration
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* based on this variable will be incorrect.
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*
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* @note - The system frequency computed by this function is not the real
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* frequency in the chip. It is calculated based on the predefined
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* constant and the selected clock source:
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*
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* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
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*
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* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
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*
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* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
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* or HSI_VALUE(*) multiplied/divided by the PLL factors.
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*
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* (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value
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* 16 MHz) but the real value may vary depending on the variations
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* in voltage and temperature.
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*
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* (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value
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* 25 MHz), user has to ensure that HSE_VALUE is same as the real
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* frequency of the crystal used. Otherwise, this function may
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* have wrong result.
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*
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* - The result of this function could be not correct when using fractional
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* value for HSE crystal.
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*
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* @param None
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* @retval None
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*/
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void SystemCoreClockUpdate(void)
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{
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uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
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/* Get SYSCLK source -------------------------------------------------------*/
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tmp = RCC->CFGR & RCC_CFGR_SWS;
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switch (tmp)
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{
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case 0x00: /* HSI used as system clock source */
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SystemCoreClock = HSI_VALUE;
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break;
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case 0x04: /* HSE used as system clock source */
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SystemCoreClock = HSE_VALUE;
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break;
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case 0x08: /* PLL used as system clock source */
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/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
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SYSCLK = PLL_VCO / PLL_P
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*/
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pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
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pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
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if (pllsource != 0)
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{
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/* HSE used as PLL clock source */
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pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
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}
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else
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{
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/* HSI used as PLL clock source */
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pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
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}
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pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
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SystemCoreClock = pllvco/pllp;
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break;
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default:
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SystemCoreClock = HSI_VALUE;
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break;
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}
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/* Compute HCLK frequency --------------------------------------------------*/
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/* Get HCLK prescaler */
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tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
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/* HCLK frequency */
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SystemCoreClock >>= tmp;
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}
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/**
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* @brief Configures the System clock source, PLL Multiplier and Divider factors,
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* AHB/APBx prescalers and Flash settings
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* @Note This function should be called only once the RCC clock configuration
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* is reset to the default reset state (done in SystemInit() function).
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* @param None
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* @retval None
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*/
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static void SetSysClock(void)
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{
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/******************************************************************************/
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/* PLL (clocked by HSE) used as System clock source */
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/******************************************************************************/
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__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
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/* Enable HSE */
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RCC->CR |= ((uint32_t)RCC_CR_HSEON);
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/* Wait till HSE is ready and if Time out is reached exit */
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do
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{
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HSEStatus = RCC->CR & RCC_CR_HSERDY;
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StartUpCounter++;
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} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
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if ((RCC->CR & RCC_CR_HSERDY) != RESET)
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{
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HSEStatus = (uint32_t)0x01;
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}
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else
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{
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HSEStatus = (uint32_t)0x00;
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}
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if (HSEStatus == (uint32_t)0x01)
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{
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/* HCLK = SYSCLK / 1*/
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RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
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/* PCLK2 = HCLK / 2*/
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RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
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/* PCLK1 = HCLK / 4*/
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RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
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/* Configure the main PLL */
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RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
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(RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
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/* Enable the main PLL */
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RCC->CR |= RCC_CR_PLLON;
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/* Wait till the main PLL is ready */
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while((RCC->CR & RCC_CR_PLLRDY) == 0)
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{
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}
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/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
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FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS;
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/* Select the main PLL as system clock source */
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RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
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RCC->CFGR |= RCC_CFGR_SW_PLL;
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/* Wait till the main PLL is used as system clock source */
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while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
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{
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}
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}
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else
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{ /* If HSE fails to start-up, the application will have wrong clock
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configuration. User can add here some code to deal with this error */
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}
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}
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/**
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* @brief Setup the external memory controller. Called in startup_stm32f2xx.s
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* before jump to __main
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* @param None
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* @retval None
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*/
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#ifdef DATA_IN_ExtSRAM
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/**
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* @brief Setup the external memory controller.
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* Called in startup_stm32f2xx.s before jump to main.
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* This function configures the external SRAM mounted on STM322xG_EVAL board
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* This SRAM will be used as program data memory (including heap and stack).
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* @param None
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* @retval None
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*/
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void SystemInit_ExtMemCtl(void)
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{
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/*-- GPIOs Configuration -----------------------------------------------------*/
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/*
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+-------------------+--------------------+------------------+------------------+
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+ SRAM pins assignment +
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+-------------------+--------------------+------------------+------------------+
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| PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 |
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| PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 |
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| PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 |
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| PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 |
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| PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 |
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| PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 |
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| PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 |
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| PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+
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| PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 |
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| PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 |
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| PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+
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+-------------------+--------------------+
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*/
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/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
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RCC->AHB1ENR = 0x00000078;
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/* Connect PDx pins to FSMC Alternate function */
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GPIOD->AFR[0] = 0x00cc00cc;
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GPIOD->AFR[1] = 0xcc0ccccc;
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/* Configure PDx pins in Alternate function mode */
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GPIOD->MODER = 0xa2aa0a0a;
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/* Configure PDx pins speed to 100 MHz */
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GPIOD->OSPEEDR = 0xf3ff0f0f;
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/* Configure PDx pins Output type to push-pull */
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GPIOD->OTYPER = 0x00000000;
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/* No pull-up, pull-down for PDx pins */
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GPIOD->PUPDR = 0x00000000;
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/* Connect PEx pins to FSMC Alternate function */
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GPIOE->AFR[0] = 0xc00000cc;
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GPIOE->AFR[1] = 0xcccccccc;
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/* Configure PEx pins in Alternate function mode */
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GPIOE->MODER = 0xaaaa800a;
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/* Configure PEx pins speed to 100 MHz */
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GPIOE->OSPEEDR = 0xffffc00f;
|
||||
/* Configure PEx pins Output type to push-pull */
|
||||
GPIOE->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PEx pins */
|
||||
GPIOE->PUPDR = 0x00000000;
|
||||
|
||||
/* Connect PFx pins to FSMC Alternate function */
|
||||
GPIOF->AFR[0] = 0x00cccccc;
|
||||
GPIOF->AFR[1] = 0xcccc0000;
|
||||
/* Configure PFx pins in Alternate function mode */
|
||||
GPIOF->MODER = 0xaa000aaa;
|
||||
/* Configure PFx pins speed to 100 MHz */
|
||||
GPIOF->OSPEEDR = 0xff000fff;
|
||||
/* Configure PFx pins Output type to push-pull */
|
||||
GPIOF->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PFx pins */
|
||||
GPIOF->PUPDR = 0x00000000;
|
||||
|
||||
/* Connect PGx pins to FSMC Alternate function */
|
||||
GPIOG->AFR[0] = 0x00cccccc;
|
||||
GPIOG->AFR[1] = 0x000000c0;
|
||||
/* Configure PGx pins in Alternate function mode */
|
||||
GPIOG->MODER = 0x00080aaa;
|
||||
/* Configure PGx pins speed to 100 MHz */
|
||||
GPIOG->OSPEEDR = 0x000c0fff;
|
||||
/* Configure PGx pins Output type to push-pull */
|
||||
GPIOG->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PGx pins */
|
||||
GPIOG->PUPDR = 0x00000000;
|
||||
|
||||
/*-- FSMC Configuration ------------------------------------------------------*/
|
||||
/* Enable the FSMC interface clock */
|
||||
RCC->AHB3ENR = 0x00000001;
|
||||
|
||||
/* Configure and enable Bank1_SRAM2 */
|
||||
FSMC_Bank1->BTCR[2] = 0x00001015;
|
||||
FSMC_Bank1->BTCR[3] = 0x00010400;
|
||||
FSMC_Bank1E->BWTR[2] = 0x0fffffff;
|
||||
/*
|
||||
Bank1_SRAM2 is configured as follow:
|
||||
|
||||
p.FSMC_AddressSetupTime = 0;
|
||||
p.FSMC_AddressHoldTime = 0;
|
||||
p.FSMC_DataSetupTime = 4;
|
||||
p.FSMC_BusTurnAroundDuration = 1;
|
||||
p.FSMC_CLKDivision = 0;
|
||||
p.FSMC_DataLatency = 0;
|
||||
p.FSMC_AccessMode = FSMC_AccessMode_A;
|
||||
|
||||
FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
|
||||
FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM;
|
||||
FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
|
||||
FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
|
||||
*/
|
||||
|
||||
}
|
||||
#endif /* DATA_IN_ExtSRAM */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -45,6 +45,17 @@ struct stm32_serial_device uart1 =
|
|||
struct rt_device uart1_device;
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_UART6
|
||||
struct stm32_serial_int_rx uart6_int_rx;
|
||||
struct stm32_serial_device uart6 =
|
||||
{
|
||||
USART6,
|
||||
&uart6_int_rx,
|
||||
RT_NULL
|
||||
};
|
||||
struct rt_device uart6_device;
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_UART2
|
||||
struct stm32_serial_int_rx uart2_int_rx;
|
||||
struct stm32_serial_device uart2 =
|
||||
|
|
@ -103,6 +114,14 @@ struct rt_device uart3_device;
|
|||
#define UART3_TX_DMA DMA1_Channel2
|
||||
#define UART3_RX_DMA DMA1_Channel3
|
||||
|
||||
/* USART6_REMAP = 0 */
|
||||
#define UART6_GPIO_TX GPIO_Pin_6
|
||||
#define UART6_GPIO_RX GPIO_Pin_7
|
||||
#define UART6_GPIO GPIOC
|
||||
#define RCC_APBPeriph_UART6 RCC_APB2Periph_USART6
|
||||
//#define UART1_TX_DMA DMA1_Channel?
|
||||
//#define UART1_RX_DMA DMA1_Channel?
|
||||
|
||||
static void RCC_Configuration(void)
|
||||
{
|
||||
#ifdef RT_USING_UART1
|
||||
|
|
@ -110,6 +129,12 @@ static void RCC_Configuration(void)
|
|||
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE);
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_UART6
|
||||
/* Enable USART6 and GPIOC clocks */
|
||||
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOC, ENABLE);
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART6, ENABLE);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void GPIO_Configuration(void)
|
||||
|
|
@ -120,13 +145,26 @@ static void GPIO_Configuration(void)
|
|||
GPIO_InitStruct.GPIO_Mode=GPIO_Mode_AF;
|
||||
GPIO_InitStruct.GPIO_Speed=GPIO_Speed_50MHz;
|
||||
GPIO_InitStruct.GPIO_OType=GPIO_OType_PP;
|
||||
GPIO_InitStruct.GPIO_PuPd=GPIO_PuPd_UP;
|
||||
GPIO_InitStruct.GPIO_PuPd=GPIO_PuPd_UP;
|
||||
|
||||
GPIO_InitStruct.GPIO_Pin=GPIO_Pin_9|GPIO_Pin_10;
|
||||
GPIO_Init(GPIOA,&GPIO_InitStruct);
|
||||
|
||||
GPIO_PinAFConfig(GPIOA, GPIO_PinSource9, GPIO_AF_USART1);
|
||||
GPIO_PinAFConfig(GPIOA, GPIO_PinSource10, GPIO_AF_USART1);
|
||||
GPIO_PinAFConfig(GPIOA, GPIO_PinSource9, GPIO_AF_USART1);
|
||||
GPIO_PinAFConfig(GPIOA, GPIO_PinSource10, GPIO_AF_USART1);
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_UART6
|
||||
GPIO_InitStruct.GPIO_Mode=GPIO_Mode_AF;
|
||||
GPIO_InitStruct.GPIO_Speed=GPIO_Speed_50MHz;
|
||||
GPIO_InitStruct.GPIO_OType=GPIO_OType_PP;
|
||||
GPIO_InitStruct.GPIO_PuPd=GPIO_PuPd_UP;
|
||||
|
||||
GPIO_InitStruct.GPIO_Pin=UART6_GPIO_TX|UART6_GPIO_RX;
|
||||
GPIO_Init(UART6_GPIO,&GPIO_InitStruct);
|
||||
|
||||
GPIO_PinAFConfig(UART6_GPIO, GPIO_PinSource6, GPIO_AF_USART6);
|
||||
GPIO_PinAFConfig(UART6_GPIO, GPIO_PinSource7, GPIO_AF_USART6);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
@ -142,6 +180,15 @@ static void NVIC_Configuration(void)
|
|||
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
|
||||
NVIC_Init(&NVIC_InitStructure);
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_UART6
|
||||
/* Enable the USART1 Interrupt */
|
||||
NVIC_InitStructure.NVIC_IRQChannel = USART6_IRQn;
|
||||
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
|
||||
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
|
||||
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
|
||||
NVIC_Init(&NVIC_InitStructure);
|
||||
#endif
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -160,7 +207,7 @@ void rt_hw_usart_init()
|
|||
|
||||
/* uart init */
|
||||
#ifdef RT_USING_UART1
|
||||
USART_DeInit(USART1);
|
||||
USART_DeInit(USART1);
|
||||
USART_InitStructure.USART_BaudRate = 115200;
|
||||
USART_InitStructure.USART_WordLength = USART_WordLength_8b;
|
||||
USART_InitStructure.USART_StopBits = USART_StopBits_1;
|
||||
|
|
@ -181,8 +228,33 @@ void rt_hw_usart_init()
|
|||
USART_Cmd(USART1, ENABLE);
|
||||
USART_ClearFlag(USART1,USART_FLAG_TXE);
|
||||
#endif
|
||||
|
||||
/* uart init */
|
||||
#ifdef RT_USING_UART6
|
||||
USART_DeInit(USART6);
|
||||
USART_InitStructure.USART_BaudRate = 115200;
|
||||
USART_InitStructure.USART_WordLength = USART_WordLength_8b;
|
||||
USART_InitStructure.USART_StopBits = USART_StopBits_1;
|
||||
USART_InitStructure.USART_Parity = USART_Parity_No ;
|
||||
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
|
||||
USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
|
||||
|
||||
USART_Init(USART6, &USART_InitStructure);
|
||||
|
||||
/* register uart1 */
|
||||
rt_hw_serial_register(&uart6_device, "uart6",
|
||||
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
|
||||
&uart6);
|
||||
|
||||
/* enable interrupt */
|
||||
USART_ITConfig(USART6, USART_IT_RXNE, ENABLE);
|
||||
/* Enable USART6 */
|
||||
USART_Cmd(USART6, ENABLE);
|
||||
USART_ClearFlag(USART6,USART_FLAG_TXE);
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef RT_USING_UART1
|
||||
void USART1_IRQHandler()
|
||||
{
|
||||
/* enter interrupt */
|
||||
|
|
@ -193,3 +265,17 @@ void USART1_IRQHandler()
|
|||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_UART6
|
||||
void USART6_IRQHandler()
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
rt_hw_serial_isr(&uart6_device);
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue