diff --git a/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/.mxproject b/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/.mxproject
new file mode 100644
index 0000000000..3091fc7182
--- /dev/null
+++ b/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/.mxproject
@@ -0,0 +1,42 @@
+[CortexM7:PreviousGenFiles]
+HeaderPath=F:/git_repositories/rt-thread/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CM7/Inc
+HeaderFiles=stm32h7xx_it.h;stm32h7xx_hal_conf.h;main.h;
+SourcePath=F:/git_repositories/rt-thread/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CM7/Src
+SourceFiles=stm32h7xx_it.c;stm32h7xx_hal_msp.c;main.c;
+
+[CortexM7:PreviousLibFiles]
+LibFiles=Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h;Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h;Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h;Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h747xx.h;Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h;Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h;Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx.c;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/tz_context.h;
+
+[CortexM7:PreviousUsedKeilFiles]
+SourceFiles=..\CM7\Src\main.c;..\CM7\Src\stm32h7xx_it.c;..\CM7\Src\stm32h7xx_hal_msp.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c;..\Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx.c;;
+HeaderPath=..\Drivers\STM32H7xx_HAL_Driver\Inc;..\Drivers\STM32H7xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32H7xx\Include;..\Drivers\CMSIS\Include;..\CM7\Inc;
+CDefines=CORE_CM7;USE_HAL_DRIVER;STM32H747xx;USE_HAL_DRIVER;USE_HAL_DRIVER;
+
+[CortexM4:PreviousGenFiles]
+HeaderPath=F:/git_repositories/rt-thread/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CM4/Inc
+HeaderFiles=stm32h7xx_it.h;stm32h7xx_hal_conf.h;main.h;
+SourcePath=F:/git_repositories/rt-thread/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CM4/Src
+SourceFiles=stm32h7xx_it.c;stm32h7xx_hal_msp.c;main.c;
+
+[CortexM4:PreviousLibFiles]
+LibFiles=Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h;Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h;Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h;Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h747xx.h;Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h;Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h;Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx.c;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/tz_context.h;
+
+[CortexM4:PreviousUsedKeilFiles]
+SourceFiles=..\CM4\Src\main.c;..\CM4\Src\stm32h7xx_it.c;..\CM4\Src\stm32h7xx_hal_msp.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c;..\Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx.c;;
+HeaderPath=..\Drivers\STM32H7xx_HAL_Driver\Inc;..\Drivers\STM32H7xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32H7xx\Include;..\Drivers\CMSIS\Include;..\CM4\Inc;
+CDefines=CORE_CM4;USE_HAL_DRIVER;STM32H747xx;USE_HAL_DRIVER;USE_HAL_DRIVER;
+
+[PreviousGenFiles]
+HeaderPath=F:/git_repositories/rt-thread/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CM7/Inc
+HeaderFiles=stm32h7xx_it.h;stm32h7xx_hal_conf.h;main.h;
+SourcePath=F:/git_repositories/rt-thread/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CM7/Src
+SourceFiles=stm32h7xx_it.c;stm32h7xx_hal_msp.c;main.c;
+
+[PreviousLibFiles]
+LibFiles=Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h;Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h;Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h;Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h;Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h;Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h747xx.h;Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h;Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h;Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_boot_cm4_cm7.c;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/tz_context.h;
+
+[PreviousUsedKeilFiles]
+SourceFiles=..\CM4\Src\main.c;..\CM7\Src\main.c;..\CM7\Src\stm32h7xx_it.c;..\CM7\Src\stm32h7xx_hal_msp.c;..\CM4\Src\stm32h7xx_it.c;..\CM4\Src\stm32h7xx_hal_msp.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c;..\Common/Src/system_stm32h7xx_dualcore_boot_cm4_cm7.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c;..\Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c;..\Common/Src/system_stm32h7xx_dualcore_boot_cm4_cm7.c;..\Common/Src/system_stm32h7xx_dualcore_boot_cm4_cm7.c;..\Common/Src/system_stm32h7xx_dualcore_boot_cm4_cm7.c;..\Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx.c;;
+HeaderPath=..\Drivers\STM32H7xx_HAL_Driver\Inc;..\Drivers\STM32H7xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32H7xx\Include;..\Drivers\CMSIS\Include;..\CM7\Inc;..\CM4\Inc;
+CDefines=CORE_CM4;CORE_CM7;CORE_CM7;USE_HAL_DRIVER;STM32H747xx;USE_HAL_DRIVER;USE_HAL_DRIVER;CORE_CM4;CORE_CM4;USE_HAL_DRIVER;STM32H747xx;USE_HAL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER;
+
diff --git a/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CM4/Inc/main.h b/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CM4/Inc/main.h
new file mode 100644
index 0000000000..4677beb2d9
--- /dev/null
+++ b/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CM4/Inc/main.h
@@ -0,0 +1,71 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : main.h
+  * @brief          : Header for main.c file.
+  *                   This file contains the common defines of the application.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CM4/Inc/stm32h7xx_hal_conf.h b/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CM4/Inc/stm32h7xx_hal_conf.h
new file mode 100644
index 0000000000..a45889b175
--- /dev/null
+++ b/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CM4/Inc/stm32h7xx_hal_conf.h
@@ -0,0 +1,493 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32H7xx_HAL_CONF_H
+#define __STM32H7xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver 
+  */
+#define HAL_MODULE_ENABLED  
+
+  /* #define HAL_ADC_MODULE_ENABLED   */
+/* #define HAL_FDCAN_MODULE_ENABLED   */
+/* #define HAL_CEC_MODULE_ENABLED   */
+/* #define HAL_COMP_MODULE_ENABLED   */
+/* #define HAL_CRC_MODULE_ENABLED   */
+/* #define HAL_CRYP_MODULE_ENABLED   */
+/* #define HAL_DAC_MODULE_ENABLED   */
+/* #define HAL_DCMI_MODULE_ENABLED   */
+/* #define HAL_DMA2D_MODULE_ENABLED   */
+/* #define HAL_ETH_MODULE_ENABLED   */
+/* #define HAL_NAND_MODULE_ENABLED   */
+/* #define HAL_NOR_MODULE_ENABLED   */
+/* #define HAL_OTFDEC_MODULE_ENABLED   */
+/* #define HAL_SRAM_MODULE_ENABLED   */
+/* #define HAL_SDRAM_MODULE_ENABLED   */
+/* #define HAL_HASH_MODULE_ENABLED   */
+/* #define HAL_HRTIM_MODULE_ENABLED   */
+/* #define HAL_HSEM_MODULE_ENABLED   */
+/* #define HAL_GFXMMU_MODULE_ENABLED   */
+/* #define HAL_JPEG_MODULE_ENABLED   */
+/* #define HAL_OPAMP_MODULE_ENABLED   */
+/* #define HAL_OSPI_MODULE_ENABLED   */
+/* #define HAL_OSPI_MODULE_ENABLED   */
+/* #define HAL_I2S_MODULE_ENABLED   */
+/* #define HAL_SMBUS_MODULE_ENABLED   */
+/* #define HAL_IWDG_MODULE_ENABLED   */
+/* #define HAL_LPTIM_MODULE_ENABLED   */
+/* #define HAL_LTDC_MODULE_ENABLED   */
+/* #define HAL_QSPI_MODULE_ENABLED   */
+/* #define HAL_RNG_MODULE_ENABLED   */
+/* #define HAL_RTC_MODULE_ENABLED   */
+/* #define HAL_SAI_MODULE_ENABLED   */
+/* #define HAL_SD_MODULE_ENABLED   */
+/* #define HAL_MMC_MODULE_ENABLED   */
+/* #define HAL_SPDIFRX_MODULE_ENABLED   */
+/* #define HAL_SPI_MODULE_ENABLED   */
+/* #define HAL_SWPMI_MODULE_ENABLED   */
+/* #define HAL_TIM_MODULE_ENABLED   */
+/* #define HAL_UART_MODULE_ENABLED   */
+/* #define HAL_USART_MODULE_ENABLED   */
+/* #define HAL_IRDA_MODULE_ENABLED   */
+/* #define HAL_SMARTCARD_MODULE_ENABLED   */
+/* #define HAL_WWDG_MODULE_ENABLED   */
+/* #define HAL_PCD_MODULE_ENABLED   */
+/* #define HAL_HCD_MODULE_ENABLED   */
+/* #define HAL_DFSDM_MODULE_ENABLED   */
+/* #define HAL_DSI_MODULE_ENABLED   */
+/* #define HAL_JPEG_MODULE_ENABLED   */
+/* #define HAL_MDIOS_MODULE_ENABLED   */
+/* #define HAL_PSSI_MODULE_ENABLED   */
+/* #define HAL_DTS_MODULE_ENABLED   */
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_MDMA_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_HSEM_MODULE_ENABLED
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).  
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal  oscillator (CSI) default value.
+  *        This value is the default CSI value after Reset.
+  */
+#if !defined  (CSI_VALUE)
+  #define CSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* CSI_VALUE */
+   
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL). 
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+#if !defined  (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for I2S peripheral
+  *        This value is used by the I2S HAL module to compute the I2S clock source 
+  *        frequency, this source is inserted directly through I2S_CKIN pad. 
+  */
+#if !defined  (EXTERNAL_CLOCK_VALUE)
+  #define EXTERNAL_CLOCK_VALUE    12288000U /*!< Value of the External clock in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+#define  VDD_VALUE                    ((uint32_t)3300U) /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            ((uint32_t)0U) /*!< tick interrupt priority */
+#define  USE_RTOS                     0U
+#define  USE_SD_TRANSCEIVER           0U               /*!< use uSD Transceiver */
+
+#define  USE_HAL_ADC_REGISTER_CALLBACKS     0U /* ADC register callback disabled     */
+#define  USE_HAL_CEC_REGISTER_CALLBACKS     0U /* CEC register callback disabled     */
+#define  USE_HAL_COMP_REGISTER_CALLBACKS    0U /* COMP register callback disabled    */
+#define  USE_HAL_CRYP_REGISTER_CALLBACKS    0U /* CRYP register callback disabled    */
+#define  USE_HAL_DAC_REGISTER_CALLBACKS     0U /* DAC register callback disabled     */
+#define  USE_HAL_DCMI_REGISTER_CALLBACKS    0U /* DCMI register callback disabled    */
+#define  USE_HAL_DFSDM_REGISTER_CALLBACKS   0U /* DFSDM register callback disabled   */
+#define  USE_HAL_DMA2D_REGISTER_CALLBACKS   0U /* DMA2D register callback disabled   */
+#define  USE_HAL_DSI_REGISTER_CALLBACKS     0U /* DSI register callback disabled     */
+#define  USE_HAL_DTS_REGISTER_CALLBACKS     0U /* DTS register callback disabled     */
+#define  USE_HAL_ETH_REGISTER_CALLBACKS     0U /* ETH register callback disabled     */
+#define  USE_HAL_FDCAN_REGISTER_CALLBACKS   0U /* FDCAN register callback disabled   */
+#define  USE_HAL_NAND_REGISTER_CALLBACKS    0U /* NAND register callback disabled    */
+#define  USE_HAL_NOR_REGISTER_CALLBACKS     0U /* NOR register callback disabled     */
+#define  USE_HAL_SDRAM_REGISTER_CALLBACKS   0U /* SDRAM register callback disabled   */
+#define  USE_HAL_SRAM_REGISTER_CALLBACKS    0U /* SRAM register callback disabled    */
+#define  USE_HAL_HASH_REGISTER_CALLBACKS    0U /* HASH register callback disabled    */
+#define  USE_HAL_HCD_REGISTER_CALLBACKS     0U /* HCD register callback disabled     */
+#define  USE_HAL_GFXMMU_REGISTER_CALLBACKS  0U /* GFXMMU register callback disabled  */
+#define  USE_HAL_HRTIM_REGISTER_CALLBACKS   0U /* HRTIM register callback disabled   */
+#define  USE_HAL_I2C_REGISTER_CALLBACKS     0U /* I2C register callback disabled     */
+#define  USE_HAL_I2S_REGISTER_CALLBACKS     0U /* I2S register callback disabled     */
+#define  USE_HAL_IRDA_REGISTER_CALLBACKS    0U /* IRDA register callback disabled    */
+#define  USE_HAL_JPEG_REGISTER_CALLBACKS    0U /* JPEG register callback disabled    */
+#define  USE_HAL_LPTIM_REGISTER_CALLBACKS   0U /* LPTIM register callback disabled   */
+#define  USE_HAL_LTDC_REGISTER_CALLBACKS    0U /* LTDC register callback disabled    */
+#define  USE_HAL_MDIOS_REGISTER_CALLBACKS   0U /* MDIO register callback disabled    */
+#define  USE_HAL_MMC_REGISTER_CALLBACKS     0U /* MMC register callback disabled     */
+#define  USE_HAL_OPAMP_REGISTER_CALLBACKS   0U /* MDIO register callback disabled    */
+#define  USE_HAL_OSPI_REGISTER_CALLBACKS    0U /* OSPI register callback disabled    */
+#define  USE_HAL_OTFDEC_REGISTER_CALLBACKS  0U /* OTFDEC register callback disabled  */
+#define  USE_HAL_PCD_REGISTER_CALLBACKS     0U /* PCD register callback disabled     */
+#define  USE_HAL_QSPI_REGISTER_CALLBACKS    0U /* QSPI register callback disabled    */
+#define  USE_HAL_RNG_REGISTER_CALLBACKS     0U /* RNG register callback disabled     */
+#define  USE_HAL_RTC_REGISTER_CALLBACKS     0U /* RTC register callback disabled     */
+#define  USE_HAL_SAI_REGISTER_CALLBACKS     0U /* SAI register callback disabled     */
+#define  USE_HAL_SD_REGISTER_CALLBACKS      0U /* SD register callback disabled      */
+#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS  0U /* SMARTCARD register callback disabled */
+#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */
+#define  USE_HAL_SMBUS_REGISTER_CALLBACKS   0U /* SMBUS register callback disabled   */
+#define  USE_HAL_SPI_REGISTER_CALLBACKS     0U /* SPI register callback disabled     */
+#define  USE_HAL_SWPMI_REGISTER_CALLBACKS   0U /* SWPMI register callback disabled   */
+#define  USE_HAL_TIM_REGISTER_CALLBACKS     0U /* TIM register callback disabled     */
+#define  USE_HAL_UART_REGISTER_CALLBACKS    0U /* UART register callback disabled    */
+#define  USE_HAL_USART_REGISTER_CALLBACKS   0U /* USART register callback disabled   */
+#define  USE_HAL_WWDG_REGISTER_CALLBACKS    0U /* WWDG register callback disabled    */
+
+/* ########################### Ethernet Configuration ######################### */
+#define ETH_TX_DESC_CNT         4  /* number of Ethernet Tx DMA descriptors */
+#define ETH_RX_DESC_CNT         4  /* number of Ethernet Rx DMA descriptors */
+
+#define ETH_MAC_ADDR0    ((uint8_t)0x02)
+#define ETH_MAC_ADDR1    ((uint8_t)0x00)
+#define ETH_MAC_ADDR2    ((uint8_t)0x00)
+#define ETH_MAC_ADDR3    ((uint8_t)0x00)
+#define ETH_MAC_ADDR4    ((uint8_t)0x00)
+#define ETH_MAC_ADDR5    ((uint8_t)0x00)
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */ 
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file 
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32h7xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32h7xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32h7xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_MDMA_MODULE_ENABLED
+ #include "stm32h7xx_hal_mdma.h"
+#endif /* HAL_MDMA_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+  #include "stm32h7xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+  #include "stm32h7xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+  #include "stm32h7xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DSI_MODULE_ENABLED
+  #include "stm32h7xx_hal_dsi.h"
+#endif /* HAL_DSI_MODULE_ENABLED */
+
+#ifdef HAL_DFSDM_MODULE_ENABLED
+  #include "stm32h7xx_hal_dfsdm.h"
+#endif /* HAL_DFSDM_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+  #include "stm32h7xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32h7xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32h7xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32h7xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_FDCAN_MODULE_ENABLED
+  #include "stm32h7xx_hal_fdcan.h"
+#endif /* HAL_FDCAN_MODULE_ENABLED */
+
+#ifdef HAL_CEC_MODULE_ENABLED
+  #include "stm32h7xx_hal_cec.h"
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32h7xx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32h7xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32h7xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+  #include "stm32h7xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32h7xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GFXMMU_MODULE_ENABLED
+  #include "stm32h7xx_hal_gfxmmu.h"
+#endif /* HAL_GFXMMU_MODULE_ENABLED */
+
+#ifdef HAL_HRTIM_MODULE_ENABLED
+  #include "stm32h7xx_hal_hrtim.h"
+#endif /* HAL_HRTIM_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32h7xx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+  #include "stm32h7xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+  #include "stm32h7xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+  #include "stm32h7xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32h7xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32h7xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32h7xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_JPEG_MODULE_ENABLED
+ #include "stm32h7xx_hal_jpeg.h"
+#endif /* HAL_JPEG_MODULE_ENABLED */
+
+#ifdef HAL_MDIOS_MODULE_ENABLED
+ #include "stm32h7xx_hal_mdios.h"
+#endif /* HAL_MDIOS_MODULE_ENABLED */
+
+#ifdef HAL_MMC_MODULE_ENABLED
+ #include "stm32h7xx_hal_mmc.h"
+#endif /* HAL_MMC_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+#include "stm32h7xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+#include "stm32h7xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_OPAMP_MODULE_ENABLED
+#include "stm32h7xx_hal_opamp.h"
+#endif /* HAL_OPAMP_MODULE_ENABLED */
+
+#ifdef HAL_OSPI_MODULE_ENABLED
+  #include "stm32h7xx_hal_ospi.h"
+#endif /* HAL_OSPI_MODULE_ENABLED */
+   
+#ifdef HAL_OTFDEC_MODULE_ENABLED
+#include "stm32h7xx_hal_otfdec.h"
+#endif /* HAL_OTFDEC_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32h7xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32h7xx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RAMECC_MODULE_ENABLED
+ #include "stm32h7xx_hal_ramecc.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32h7xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32h7xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32h7xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32h7xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+ #include "stm32h7xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32h7xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_SPDIFRX_MODULE_ENABLED
+ #include "stm32h7xx_hal_spdifrx.h"
+#endif /* HAL_SPDIFRX_MODULE_ENABLED */
+
+#ifdef HAL_SWPMI_MODULE_ENABLED
+ #include "stm32h7xx_hal_swpmi.h"
+#endif /* HAL_SWPMI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32h7xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32h7xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32h7xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32h7xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32h7xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32h7xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32h7xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32h7xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32h7xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_PSSI_MODULE_ENABLED
+  #include "stm32h7xx_hal_pssi.h"
+#endif /* HAL_PSSI_MODULE_ENABLED */
+
+#ifdef HAL_DTS_MODULE_ENABLED
+  #include "stm32h7xx_hal_dts.h"
+#endif /* HAL_DTS_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed. 
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32H7xx_HAL_CONF_H */
+ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CM4/Inc/stm32h7xx_it.h b/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CM4/Inc/stm32h7xx_it.h
new file mode 100644
index 0000000000..dbb600a213
--- /dev/null
+++ b/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CM4/Inc/stm32h7xx_it.h
@@ -0,0 +1,69 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_it.h
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+ ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32H7xx_IT_H
+#define __STM32H7xx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32H7xx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CM4/Src/main.c b/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CM4/Src/main.c
new file mode 100644
index 0000000000..9d3aa22fc2
--- /dev/null
+++ b/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CM4/Src/main.c
@@ -0,0 +1,151 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : main.c
+  * @brief          : Main program body
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+#define HSEM_ID_0 (0U) /* HW semaphore 0*/
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* USER CODE END 1 */
+  
+
+/* USER CODE BEGIN Boot_Mode_Sequence_1 */
+  /*HW semaphore Clock enable*/
+  __HAL_RCC_HSEM_CLK_ENABLE();
+  /* Activate HSEM notification for Cortex-M4*/
+  HAL_HSEM_ActivateNotification(__HAL_HSEM_SEMID_TO_MASK(HSEM_ID_0));
+  /*
+  Domain D2 goes to STOP mode (Cortex-M4 in deep-sleep) waiting for Cortex-M7 to
+  perform system initialization (system clock config, external memory configuration.. )
+  */
+  HAL_PWREx_ClearPendingEvent();
+  HAL_PWREx_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_STOPENTRY_WFE, PWR_D2_DOMAIN);
+  /* Clear HSEM flag */
+  __HAL_HSEM_CLEAR_FLAG(__HAL_HSEM_SEMID_TO_MASK(HSEM_ID_0));
+
+/* USER CODE END Boot_Mode_Sequence_1 */
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  /* USER CODE BEGIN 2 */
+
+  /* USER CODE END 2 */
+ 
+ 
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/* USER CODE BEGIN 4 */
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CM4/Src/stm32h7xx_hal_msp.c b/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CM4/Src/stm32h7xx_hal_msp.c
new file mode 100644
index 0000000000..858912e780
--- /dev/null
+++ b/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CM4/Src/stm32h7xx_hal_msp.c
@@ -0,0 +1,83 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * File Name          : stm32h7xx_hal_msp.c
+  * Description        : This file provides code for the MSP Initialization 
+  *                      and de-Initialization codes.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CM4/Src/stm32h7xx_it.c b/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CM4/Src/stm32h7xx_it.c
new file mode 100644
index 0000000000..e955dd71b2
--- /dev/null
+++ b/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CM4/Src/stm32h7xx_it.c
@@ -0,0 +1,203 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_it.c
+  * @brief   Interrupt Service Routines.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32h7xx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Pre-fetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32H7xx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32h7xx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CM7/Inc/main.h b/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CM7/Inc/main.h
new file mode 100644
index 0000000000..4677beb2d9
--- /dev/null
+++ b/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CM7/Inc/main.h
@@ -0,0 +1,71 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : main.h
+  * @brief          : Header for main.c file.
+  *                   This file contains the common defines of the application.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CM7/Inc/stm32h7xx_hal_conf.h b/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CM7/Inc/stm32h7xx_hal_conf.h
new file mode 100644
index 0000000000..3842eda139
--- /dev/null
+++ b/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CM7/Inc/stm32h7xx_hal_conf.h
@@ -0,0 +1,493 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32H7xx_HAL_CONF_H
+#define __STM32H7xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver 
+  */
+#define HAL_MODULE_ENABLED  
+
+  /* #define HAL_ADC_MODULE_ENABLED   */
+/* #define HAL_FDCAN_MODULE_ENABLED   */
+/* #define HAL_CEC_MODULE_ENABLED   */
+/* #define HAL_COMP_MODULE_ENABLED   */
+/* #define HAL_CRC_MODULE_ENABLED   */
+/* #define HAL_CRYP_MODULE_ENABLED   */
+/* #define HAL_DAC_MODULE_ENABLED   */
+/* #define HAL_DCMI_MODULE_ENABLED   */
+/* #define HAL_DMA2D_MODULE_ENABLED   */
+/* #define HAL_ETH_MODULE_ENABLED   */
+/* #define HAL_NAND_MODULE_ENABLED   */
+/* #define HAL_NOR_MODULE_ENABLED   */
+/* #define HAL_OTFDEC_MODULE_ENABLED   */
+/* #define HAL_SRAM_MODULE_ENABLED   */
+/* #define HAL_SDRAM_MODULE_ENABLED   */
+/* #define HAL_HASH_MODULE_ENABLED   */
+/* #define HAL_HRTIM_MODULE_ENABLED   */
+/* #define HAL_HSEM_MODULE_ENABLED   */
+/* #define HAL_GFXMMU_MODULE_ENABLED   */
+/* #define HAL_JPEG_MODULE_ENABLED   */
+/* #define HAL_OPAMP_MODULE_ENABLED   */
+/* #define HAL_OSPI_MODULE_ENABLED   */
+/* #define HAL_OSPI_MODULE_ENABLED   */
+/* #define HAL_I2S_MODULE_ENABLED   */
+/* #define HAL_SMBUS_MODULE_ENABLED   */
+/* #define HAL_IWDG_MODULE_ENABLED   */
+/* #define HAL_LPTIM_MODULE_ENABLED   */
+/* #define HAL_LTDC_MODULE_ENABLED   */
+/* #define HAL_QSPI_MODULE_ENABLED   */
+/* #define HAL_RNG_MODULE_ENABLED   */
+/* #define HAL_RTC_MODULE_ENABLED   */
+/* #define HAL_SAI_MODULE_ENABLED   */
+/* #define HAL_SD_MODULE_ENABLED   */
+/* #define HAL_MMC_MODULE_ENABLED   */
+/* #define HAL_SPDIFRX_MODULE_ENABLED   */
+/* #define HAL_SPI_MODULE_ENABLED   */
+/* #define HAL_SWPMI_MODULE_ENABLED   */
+/* #define HAL_TIM_MODULE_ENABLED   */
+#define HAL_UART_MODULE_ENABLED
+/* #define HAL_USART_MODULE_ENABLED   */
+/* #define HAL_IRDA_MODULE_ENABLED   */
+/* #define HAL_SMARTCARD_MODULE_ENABLED   */
+/* #define HAL_WWDG_MODULE_ENABLED   */
+/* #define HAL_PCD_MODULE_ENABLED   */
+/* #define HAL_HCD_MODULE_ENABLED   */
+/* #define HAL_DFSDM_MODULE_ENABLED   */
+/* #define HAL_DSI_MODULE_ENABLED   */
+/* #define HAL_JPEG_MODULE_ENABLED   */
+/* #define HAL_MDIOS_MODULE_ENABLED   */
+/* #define HAL_PSSI_MODULE_ENABLED   */
+/* #define HAL_DTS_MODULE_ENABLED   */
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_MDMA_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_HSEM_MODULE_ENABLED
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).  
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal  oscillator (CSI) default value.
+  *        This value is the default CSI value after Reset.
+  */
+#if !defined  (CSI_VALUE)
+  #define CSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* CSI_VALUE */
+   
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL). 
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+#if !defined  (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for I2S peripheral
+  *        This value is used by the I2S HAL module to compute the I2S clock source 
+  *        frequency, this source is inserted directly through I2S_CKIN pad. 
+  */
+#if !defined  (EXTERNAL_CLOCK_VALUE)
+  #define EXTERNAL_CLOCK_VALUE    12288000U /*!< Value of the External clock in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+#define  VDD_VALUE                    ((uint32_t)3300U) /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            ((uint32_t)0U) /*!< tick interrupt priority */
+#define  USE_RTOS                     0U
+#define  USE_SD_TRANSCEIVER           0U               /*!< use uSD Transceiver */
+
+#define  USE_HAL_ADC_REGISTER_CALLBACKS     0U /* ADC register callback disabled     */
+#define  USE_HAL_CEC_REGISTER_CALLBACKS     0U /* CEC register callback disabled     */
+#define  USE_HAL_COMP_REGISTER_CALLBACKS    0U /* COMP register callback disabled    */
+#define  USE_HAL_CRYP_REGISTER_CALLBACKS    0U /* CRYP register callback disabled    */
+#define  USE_HAL_DAC_REGISTER_CALLBACKS     0U /* DAC register callback disabled     */
+#define  USE_HAL_DCMI_REGISTER_CALLBACKS    0U /* DCMI register callback disabled    */
+#define  USE_HAL_DFSDM_REGISTER_CALLBACKS   0U /* DFSDM register callback disabled   */
+#define  USE_HAL_DMA2D_REGISTER_CALLBACKS   0U /* DMA2D register callback disabled   */
+#define  USE_HAL_DSI_REGISTER_CALLBACKS     0U /* DSI register callback disabled     */
+#define  USE_HAL_DTS_REGISTER_CALLBACKS     0U /* DTS register callback disabled     */
+#define  USE_HAL_ETH_REGISTER_CALLBACKS     0U /* ETH register callback disabled     */
+#define  USE_HAL_FDCAN_REGISTER_CALLBACKS   0U /* FDCAN register callback disabled   */
+#define  USE_HAL_NAND_REGISTER_CALLBACKS    0U /* NAND register callback disabled    */
+#define  USE_HAL_NOR_REGISTER_CALLBACKS     0U /* NOR register callback disabled     */
+#define  USE_HAL_SDRAM_REGISTER_CALLBACKS   0U /* SDRAM register callback disabled   */
+#define  USE_HAL_SRAM_REGISTER_CALLBACKS    0U /* SRAM register callback disabled    */
+#define  USE_HAL_HASH_REGISTER_CALLBACKS    0U /* HASH register callback disabled    */
+#define  USE_HAL_HCD_REGISTER_CALLBACKS     0U /* HCD register callback disabled     */
+#define  USE_HAL_GFXMMU_REGISTER_CALLBACKS  0U /* GFXMMU register callback disabled  */
+#define  USE_HAL_HRTIM_REGISTER_CALLBACKS   0U /* HRTIM register callback disabled   */
+#define  USE_HAL_I2C_REGISTER_CALLBACKS     0U /* I2C register callback disabled     */
+#define  USE_HAL_I2S_REGISTER_CALLBACKS     0U /* I2S register callback disabled     */
+#define  USE_HAL_IRDA_REGISTER_CALLBACKS    0U /* IRDA register callback disabled    */
+#define  USE_HAL_JPEG_REGISTER_CALLBACKS    0U /* JPEG register callback disabled    */
+#define  USE_HAL_LPTIM_REGISTER_CALLBACKS   0U /* LPTIM register callback disabled   */
+#define  USE_HAL_LTDC_REGISTER_CALLBACKS    0U /* LTDC register callback disabled    */
+#define  USE_HAL_MDIOS_REGISTER_CALLBACKS   0U /* MDIO register callback disabled    */
+#define  USE_HAL_MMC_REGISTER_CALLBACKS     0U /* MMC register callback disabled     */
+#define  USE_HAL_OPAMP_REGISTER_CALLBACKS   0U /* MDIO register callback disabled    */
+#define  USE_HAL_OSPI_REGISTER_CALLBACKS    0U /* OSPI register callback disabled    */
+#define  USE_HAL_OTFDEC_REGISTER_CALLBACKS  0U /* OTFDEC register callback disabled  */
+#define  USE_HAL_PCD_REGISTER_CALLBACKS     0U /* PCD register callback disabled     */
+#define  USE_HAL_QSPI_REGISTER_CALLBACKS    0U /* QSPI register callback disabled    */
+#define  USE_HAL_RNG_REGISTER_CALLBACKS     0U /* RNG register callback disabled     */
+#define  USE_HAL_RTC_REGISTER_CALLBACKS     0U /* RTC register callback disabled     */
+#define  USE_HAL_SAI_REGISTER_CALLBACKS     0U /* SAI register callback disabled     */
+#define  USE_HAL_SD_REGISTER_CALLBACKS      0U /* SD register callback disabled      */
+#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS  0U /* SMARTCARD register callback disabled */
+#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */
+#define  USE_HAL_SMBUS_REGISTER_CALLBACKS   0U /* SMBUS register callback disabled   */
+#define  USE_HAL_SPI_REGISTER_CALLBACKS     0U /* SPI register callback disabled     */
+#define  USE_HAL_SWPMI_REGISTER_CALLBACKS   0U /* SWPMI register callback disabled   */
+#define  USE_HAL_TIM_REGISTER_CALLBACKS     0U /* TIM register callback disabled     */
+#define  USE_HAL_UART_REGISTER_CALLBACKS    0U /* UART register callback disabled    */
+#define  USE_HAL_USART_REGISTER_CALLBACKS   0U /* USART register callback disabled   */
+#define  USE_HAL_WWDG_REGISTER_CALLBACKS    0U /* WWDG register callback disabled    */
+
+/* ########################### Ethernet Configuration ######################### */
+#define ETH_TX_DESC_CNT         4  /* number of Ethernet Tx DMA descriptors */
+#define ETH_RX_DESC_CNT         4  /* number of Ethernet Rx DMA descriptors */
+
+#define ETH_MAC_ADDR0    ((uint8_t)0x02)
+#define ETH_MAC_ADDR1    ((uint8_t)0x00)
+#define ETH_MAC_ADDR2    ((uint8_t)0x00)
+#define ETH_MAC_ADDR3    ((uint8_t)0x00)
+#define ETH_MAC_ADDR4    ((uint8_t)0x00)
+#define ETH_MAC_ADDR5    ((uint8_t)0x00)
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */ 
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file 
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32h7xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32h7xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32h7xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_MDMA_MODULE_ENABLED
+ #include "stm32h7xx_hal_mdma.h"
+#endif /* HAL_MDMA_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+  #include "stm32h7xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+  #include "stm32h7xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+  #include "stm32h7xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DSI_MODULE_ENABLED
+  #include "stm32h7xx_hal_dsi.h"
+#endif /* HAL_DSI_MODULE_ENABLED */
+
+#ifdef HAL_DFSDM_MODULE_ENABLED
+  #include "stm32h7xx_hal_dfsdm.h"
+#endif /* HAL_DFSDM_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+  #include "stm32h7xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32h7xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32h7xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32h7xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_FDCAN_MODULE_ENABLED
+  #include "stm32h7xx_hal_fdcan.h"
+#endif /* HAL_FDCAN_MODULE_ENABLED */
+
+#ifdef HAL_CEC_MODULE_ENABLED
+  #include "stm32h7xx_hal_cec.h"
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32h7xx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32h7xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32h7xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+  #include "stm32h7xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32h7xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GFXMMU_MODULE_ENABLED
+  #include "stm32h7xx_hal_gfxmmu.h"
+#endif /* HAL_GFXMMU_MODULE_ENABLED */
+
+#ifdef HAL_HRTIM_MODULE_ENABLED
+  #include "stm32h7xx_hal_hrtim.h"
+#endif /* HAL_HRTIM_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32h7xx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+  #include "stm32h7xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+  #include "stm32h7xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+  #include "stm32h7xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32h7xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32h7xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32h7xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_JPEG_MODULE_ENABLED
+ #include "stm32h7xx_hal_jpeg.h"
+#endif /* HAL_JPEG_MODULE_ENABLED */
+
+#ifdef HAL_MDIOS_MODULE_ENABLED
+ #include "stm32h7xx_hal_mdios.h"
+#endif /* HAL_MDIOS_MODULE_ENABLED */
+
+#ifdef HAL_MMC_MODULE_ENABLED
+ #include "stm32h7xx_hal_mmc.h"
+#endif /* HAL_MMC_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+#include "stm32h7xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+#include "stm32h7xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_OPAMP_MODULE_ENABLED
+#include "stm32h7xx_hal_opamp.h"
+#endif /* HAL_OPAMP_MODULE_ENABLED */
+
+#ifdef HAL_OSPI_MODULE_ENABLED
+  #include "stm32h7xx_hal_ospi.h"
+#endif /* HAL_OSPI_MODULE_ENABLED */
+   
+#ifdef HAL_OTFDEC_MODULE_ENABLED
+#include "stm32h7xx_hal_otfdec.h"
+#endif /* HAL_OTFDEC_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32h7xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32h7xx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RAMECC_MODULE_ENABLED
+ #include "stm32h7xx_hal_ramecc.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32h7xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32h7xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32h7xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32h7xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+ #include "stm32h7xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32h7xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_SPDIFRX_MODULE_ENABLED
+ #include "stm32h7xx_hal_spdifrx.h"
+#endif /* HAL_SPDIFRX_MODULE_ENABLED */
+
+#ifdef HAL_SWPMI_MODULE_ENABLED
+ #include "stm32h7xx_hal_swpmi.h"
+#endif /* HAL_SWPMI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32h7xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32h7xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32h7xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32h7xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32h7xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32h7xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32h7xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32h7xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32h7xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_PSSI_MODULE_ENABLED
+  #include "stm32h7xx_hal_pssi.h"
+#endif /* HAL_PSSI_MODULE_ENABLED */
+
+#ifdef HAL_DTS_MODULE_ENABLED
+  #include "stm32h7xx_hal_dts.h"
+#endif /* HAL_DTS_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed. 
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32H7xx_HAL_CONF_H */
+ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CM7/Inc/stm32h7xx_it.h b/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CM7/Inc/stm32h7xx_it.h
new file mode 100644
index 0000000000..dbb600a213
--- /dev/null
+++ b/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CM7/Inc/stm32h7xx_it.h
@@ -0,0 +1,69 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_it.h
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+ ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32H7xx_IT_H
+#define __STM32H7xx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32H7xx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CM7/Src/main.c b/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CM7/Src/main.c
new file mode 100644
index 0000000000..fe51ccdc34
--- /dev/null
+++ b/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CM7/Src/main.c
@@ -0,0 +1,290 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : main.c
+  * @brief          : Main program body
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+#define HSEM_ID_0 (0U) /* HW semaphore 0*/
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+UART_HandleTypeDef huart1;
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_USART1_UART_Init(void);
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* USER CODE END 1 */
+   
+  /* USER CODE BEGIN Boot_Mode_Sequence_0 */
+    int32_t timeout; 
+  /* USER CODE END Boot_Mode_Sequence_0 */
+
+/* USER CODE BEGIN Boot_Mode_Sequence_1 */
+  /* Wait until CPU2 boots and enters in stop mode or timeout*/
+  timeout = 0xFFFF;
+  while((__HAL_RCC_GET_FLAG(RCC_FLAG_D2CKRDY) != RESET) && (timeout-- > 0));
+  if ( timeout < 0 )
+  {
+  Error_Handler();
+  }
+/* USER CODE END Boot_Mode_Sequence_1 */
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+/* USER CODE BEGIN Boot_Mode_Sequence_2 */
+/* When system initialization is finished, Cortex-M7 will release Cortex-M4 by means of
+HSEM notification */
+/*HW semaphore Clock enable*/
+__HAL_RCC_HSEM_CLK_ENABLE();
+/*Take HSEM */
+HAL_HSEM_FastTake(HSEM_ID_0);
+/*Release HSEM in order to notify the CPU2(CM4)*/
+HAL_HSEM_Release(HSEM_ID_0,0);
+/* wait until CPU2 wakes up from stop mode */
+timeout = 0xFFFF;
+while((__HAL_RCC_GET_FLAG(RCC_FLAG_D2CKRDY) == RESET) && (timeout-- > 0));
+if ( timeout < 0 )
+{
+Error_Handler();
+}
+/* USER CODE END Boot_Mode_Sequence_2 */
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_USART1_UART_Init();
+  /* USER CODE BEGIN 2 */
+
+  /* USER CODE END 2 */
+ 
+ 
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+  /** Supply configuration update enable 
+  */
+  HAL_PWREx_ConfigSupply(PWR_DIRECT_SMPS_SUPPLY);
+  /** Configure the main internal regulator output voltage 
+  */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.HSIState = RCC_HSI_DIV1;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
+                              |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
+  RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV1;
+  RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1;
+  PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2;
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+}
+
+/**
+  * @brief USART1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_USART1_UART_Init(void)
+{
+
+  /* USER CODE BEGIN USART1_Init 0 */
+
+  /* USER CODE END USART1_Init 0 */
+
+  /* USER CODE BEGIN USART1_Init 1 */
+
+  /* USER CODE END USART1_Init 1 */
+  huart1.Instance = USART1;
+  huart1.Init.BaudRate = 115200;
+  huart1.Init.WordLength = UART_WORDLENGTH_8B;
+  huart1.Init.StopBits = UART_STOPBITS_1;
+  huart1.Init.Parity = UART_PARITY_NONE;
+  huart1.Init.Mode = UART_MODE_TX_RX;
+  huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  huart1.Init.OverSampling = UART_OVERSAMPLING_16;
+  huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+  huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+  huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+  if (HAL_UART_Init(&huart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN USART1_Init 2 */
+
+  /* USER CODE END USART1_Init 2 */
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOH_CLK_ENABLE();
+
+}
+
+/* USER CODE BEGIN 4 */
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CM7/Src/stm32h7xx_hal_msp.c b/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CM7/Src/stm32h7xx_hal_msp.c
new file mode 100644
index 0000000000..b2f1998e9b
--- /dev/null
+++ b/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CM7/Src/stm32h7xx_hal_msp.c
@@ -0,0 +1,148 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * File Name          : stm32h7xx_hal_msp.c
+  * Description        : This file provides code for the MSP Initialization 
+  *                      and de-Initialization codes.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief UART MSP Initialization
+* This function configures the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspInit(UART_HandleTypeDef* huart)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(huart->Instance==USART1)
+  {
+  /* USER CODE BEGIN USART1_MspInit 0 */
+
+  /* USER CODE END USART1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_USART1_CLK_ENABLE();
+  
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**USART1 GPIO Configuration    
+    PA10     ------> USART1_RX
+    PA9     ------> USART1_TX 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_9;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN USART1_MspInit 1 */
+
+  /* USER CODE END USART1_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief UART MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
+{
+  if(huart->Instance==USART1)
+  {
+  /* USER CODE BEGIN USART1_MspDeInit 0 */
+
+  /* USER CODE END USART1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_USART1_CLK_DISABLE();
+  
+    /**USART1 GPIO Configuration    
+    PA10     ------> USART1_RX
+    PA9     ------> USART1_TX 
+    */
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_10|GPIO_PIN_9);
+
+  /* USER CODE BEGIN USART1_MspDeInit 1 */
+
+  /* USER CODE END USART1_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CM7/Src/stm32h7xx_it.c b/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CM7/Src/stm32h7xx_it.c
new file mode 100644
index 0000000000..e955dd71b2
--- /dev/null
+++ b/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CM7/Src/stm32h7xx_it.c
@@ -0,0 +1,203 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_it.c
+  * @brief   Interrupt Service Routines.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32h7xx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Pre-fetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32H7xx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32h7xx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/Common/Src/system_stm32h7xx_dualcore_boot_cm4_cm7.c b/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/Common/Src/system_stm32h7xx_dualcore_boot_cm4_cm7.c
new file mode 100644
index 0000000000..e5b799374d
--- /dev/null
+++ b/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/Common/Src/system_stm32h7xx_dualcore_boot_cm4_cm7.c
@@ -0,0 +1,368 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32h7xx_dualcore_boot_cm4_cm7.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-Mx Device Peripheral Access Layer System Source File.
+  *          This provides system initialization template function is case of
+  *          an application using a dual core STM32H7 device where
+  *          Cortex-M7 and Cortex-M4 boot are enabled at the FLASH option bytes
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32h7xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32h7xx_system
+  * @{
+  */
+
+/** @addtogroup STM32H7xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32h7xx.h"
+#include <math.h>
+
+#if !defined  (HSE_VALUE)
+#define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (CSI_VALUE)
+  #define CSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* CSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Private_Defines
+  * @{
+  */
+
+/************************* Miscellaneous Configuration ************************/
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00000000UL /*!< Vector Table base offset field.
+                                      This value must be a multiple of 0x200. */
+/******************************************************************************/
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Private_Variables
+  * @{
+  */
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock = 64000000;
+  uint32_t SystemD2Clock = 64000000;
+  const  uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the FPU setting and  vector table location
+  *         configuration.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2)));  /* set CP10 and CP11 Full Access */
+  #endif
+
+    /*SEVONPEND enabled so that an interrupt coming from the CPU(n) interrupt signal is
+     detectable by the CPU after a WFI/WFE instruction.*/
+ SCB->SCR |= SCB_SCR_SEVONPEND_Pos;
+
+#ifdef CORE_CM7
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set HSION bit */
+  RCC->CR |= RCC_CR_HSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00000000;
+
+  /* Reset HSEON, CSSON , CSION,RC48ON, CSIKERON PLL1ON, PLL2ON and PLL3ON bits */
+  RCC->CR &= 0xEAF6ED7FU;
+
+  /* Reset D1CFGR register */
+  RCC->D1CFGR = 0x00000000;
+
+  /* Reset D2CFGR register */
+  RCC->D2CFGR = 0x00000000;
+
+  /* Reset D3CFGR register */
+  RCC->D3CFGR = 0x00000000;
+
+  /* Reset PLLCKSELR register */
+  RCC->PLLCKSELR = 0x00000000;
+
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x00000000;
+  /* Reset PLL1DIVR register */
+  RCC->PLL1DIVR = 0x00000000;
+  /* Reset PLL1FRACR register */
+  RCC->PLL1FRACR = 0x00000000;
+
+  /* Reset PLL2DIVR register */
+  RCC->PLL2DIVR = 0x00000000;
+
+  /* Reset PLL2FRACR register */
+
+  RCC->PLL2FRACR = 0x00000000;
+  /* Reset PLL3DIVR register */
+  RCC->PLL3DIVR = 0x00000000;
+
+  /* Reset PLL3FRACR register */
+  RCC->PLL3FRACR = 0x00000000;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+
+  /* Enable CortexM7 HSEM EXTI line (line 78)*/
+  EXTI_D2->EMR3 |= 0x4000UL;
+
+
+  if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
+  {
+    /* if stm32h7 revY*/
+    /* Change  the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
+    *((__IO uint32_t*)0x51008108) = 0x000000001U;
+  }
+
+#endif /* CORE_CM7*/
+
+#ifdef CORE_CM4
+
+  /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = D2_AHBSRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+  SCB->VTOR = FLASH_BANK2_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+#else
+#ifdef CORE_CM7
+
+  /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = D1_AXISRAM_BASE  | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM */
+#else
+  SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET;       /* Vector Table Relocation in Internal FLASH */
+#endif
+
+#else
+#error Please #define CORE_CM4 or CORE_CM7
+#endif
+#endif
+
+}
+
+/**
+   * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock , it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*)
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*),
+  *             HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
+  *
+  *         (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *         (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
+  *             64 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value
+  *              25 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
+  float_t fracn1, pllvco;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+  case RCC_CFGR_SWS_HSI:  /* HSI used as system clock source */
+   SystemCoreClock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
+
+    break;
+
+  case RCC_CFGR_SWS_CSI:  /* CSI used as system clock  source */
+    SystemCoreClock = CSI_VALUE;
+    break;
+
+  case RCC_CFGR_SWS_HSE:  /* HSE used as system clock  source */
+    SystemCoreClock = HSE_VALUE;
+    break;
+
+  case RCC_CFGR_SWS_PLL1:  /* PLL1 used as system clock  source */
+
+    /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
+    SYSCLK = PLL_VCO / PLLR
+    */
+    pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
+    pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4)  ;
+    pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos);
+    fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
+
+    if (pllm != 0U)
+    {
+      switch (pllsource)
+      {
+        case RCC_PLLCKSELR_PLLSRC_HSI:  /* HSI used as PLL clock source */
+
+        hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
+        pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+
+        break;
+
+        case RCC_PLLCKSELR_PLLSRC_CSI:  /* CSI used as PLL clock source */
+          pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+        break;
+
+        case RCC_PLLCKSELR_PLLSRC_HSE:  /* HSE used as PLL clock source */
+          pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+        break;
+
+      default:
+          pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+        break;
+      }
+      pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
+      SystemCoreClock =  (uint32_t)(float_t)(pllvco/(float_t)pllp);
+    }
+    else
+    {
+      SystemCoreClock = 0U;
+    }
+    break;
+
+  default:
+    SystemCoreClock = CSI_VALUE;
+    break;
+  }
+
+  /* Compute SystemClock frequency --------------------------------------------------*/
+  tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos];
+
+  /* SystemCoreClock frequency : CM7 CPU frequency  */
+  SystemCoreClock >>= tmp;
+
+  /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency  */
+  SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CubeMX_Config.ioc
new file mode 100644
index 0000000000..7e5db8c6e6
--- /dev/null
+++ b/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/CubeMX_Config.ioc
@@ -0,0 +1,190 @@
+#MicroXplorer Configuration settings - do not modify
+CortexM4.IPs=DEBUG,FATFS_M4\:I,FREERTOS_M4\:I,IWDG2\:I,PDM2PCM_M4\:I,PWR,RCC,RESMGR_UTILITY,SYS_M4\:I,USB_DEVICE_M4\:I,USB_HOST_M4\:I,WWDG2\:I,DMA,BDMA,MDMA,NVIC2\:I
+CortexM7.IPs=CORTEX_M7\:I,DEBUG\:I,FATFS_M7\:I,FREERTOS_M7\:I,IWDG1\:I,PDM2PCM_M7\:I,PWR\:I,RCC\:I,RESMGR_UTILITY\:I,SYS\:I,USB_DEVICE_M7\:I,USB_HOST_M7\:I,WWDG1\:I,DMA\:I,BDMA\:I,MDMA\:I,NVIC1\:I,USART1\:I
+File.Version=6
+GPIO.groupedBy=Group By Peripherals
+KeepUserPlacement=false
+Mcu.Context0=CortexM7
+Mcu.Context1=CortexM4
+Mcu.ContextNb=2
+Mcu.Family=STM32H7
+Mcu.IP0=CORTEX_M7
+Mcu.IP1=NVIC1
+Mcu.IP2=NVIC2
+Mcu.IP3=RCC
+Mcu.IP4=SYS
+Mcu.IP5=SYS_M4
+Mcu.IP6=USART1
+Mcu.IPNb=7
+Mcu.Name=STM32H747XIHx
+Mcu.Package=TFBGA240
+Mcu.Pin0=PA10
+Mcu.Pin1=PA9
+Mcu.Pin2=PH1-OSC_OUT (PH1)
+Mcu.Pin3=PH0-OSC_IN (PH0)
+Mcu.Pin4=VP_SYS_VS_Systick
+Mcu.Pin5=VP_SYS_M4_VS_Systick
+Mcu.PinsNb=6
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32H747XIHx
+MxCube.Version=5.5.0
+MxDb.Version=DB.5.0.50
+NVIC1.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC1.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC1.ForceEnableDMAVector=true
+NVIC1.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC1.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC1.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC1.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC1.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC1.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC1.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC1.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC2.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC2.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC2.ForceEnableDMAVector=true
+NVIC2.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC2.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC2.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC2.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC2.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC2.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC2.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC2.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PA10.GPIOParameters=PinAttribute
+PA10.Locked=true
+PA10.Mode=Asynchronous
+PA10.PinAttribute=CortexM7
+PA10.Signal=USART1_RX
+PA9.GPIOParameters=PinAttribute
+PA9.Locked=true
+PA9.Mode=Asynchronous
+PA9.PinAttribute=CortexM7
+PA9.Signal=USART1_TX
+PCC.Checker=true
+PCC.Line=STM32H747/757
+PCC.MCU=STM32H747XIHx
+PCC.PartNumber=STM32H747XIHx
+PCC.Seq0=0
+PCC.Series=STM32H7
+PCC.Temperature=25
+PCC.Vdd=3.0
+PH0-OSC_IN\ (PH0).GPIOParameters=PinAttribute
+PH0-OSC_IN\ (PH0).Mode=HSE-External-Oscillator
+PH0-OSC_IN\ (PH0).PinAttribute=CortexM7
+PH0-OSC_IN\ (PH0).Signal=RCC_OSC_IN
+PH1-OSC_OUT\ (PH1).GPIOParameters=PinAttribute
+PH1-OSC_OUT\ (PH1).Mode=HSE-External-Oscillator
+PH1-OSC_OUT\ (PH1).PinAttribute=CortexM7
+PH1-OSC_OUT\ (PH1).Signal=RCC_OSC_OUT
+PinOutPanel.CurrentBGAView=Top
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.BootMode=boot0
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.CustomerFirmwarePackage=
+ProjectManager.DefaultFWLocation=true
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32H747XIHx
+ProjectManager.FirmwarePackage=STM32Cube FW_H7 V1.6.0
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=0
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=CubeMX_Config.ioc
+ProjectManager.ProjectName=CubeMX_Config
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=MDK-ARM V5
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true-CortexM7,2-SystemClock_Config-RCC-false-HAL-false-CortexM7,3-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true-CortexM7,4-MX_USART1_UART_Init-USART1-false-HAL-true-CortexM7
+RCC.ADCFreq_Value=129000000
+RCC.AHB12Freq_Value=64000000
+RCC.AHB4Freq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB3Freq_Value=64000000
+RCC.APB4Freq_Value=64000000
+RCC.AXIClockFreq_Value=64000000
+RCC.CECFreq_Value=32000
+RCC.CKPERFreq_Value=64000000
+RCC.CPU2Freq_Value=64000000
+RCC.CPU2SystikFreq_Value=64000000
+RCC.CortexFreq_Value=64000000
+RCC.CpuClockFreq_Value=64000000
+RCC.D1CPREFreq_Value=64000000
+RCC.DFSDMACLkFreq_Value=129000000
+RCC.DFSDMFreq_Value=64000000
+RCC.DIVP1Freq_Value=129000000
+RCC.DIVP2Freq_Value=129000000
+RCC.DIVP3Freq_Value=129000000
+RCC.DIVQ1Freq_Value=129000000
+RCC.DIVQ2Freq_Value=129000000
+RCC.DIVQ3Freq_Value=129000000
+RCC.DIVR1Freq_Value=129000000
+RCC.DIVR2Freq_Value=129000000
+RCC.DIVR3Freq_Value=129000000
+RCC.DSIFreq_Value=62500000
+RCC.DSITXEscFreq_Value=15625000
+RCC.FDCANFreq_Value=129000000
+RCC.FMCFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK3ClockFreq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.HRTIMFreq_Value=64000000
+RCC.I2C123Freq_Value=64000000
+RCC.I2C4Freq_Value=64000000
+RCC.IPParameters=ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CECFreq_Value,CKPERFreq_Value,CPU2Freq_Value,CPU2SystikFreq_Value,CortexFreq_Value,CpuClockFreq_Value,D1CPREFreq_Value,DFSDMACLkFreq_Value,DFSDMFreq_Value,DIVP1Freq_Value,DIVP2Freq_Value,DIVP3Freq_Value,DIVQ1Freq_Value,DIVQ2Freq_Value,DIVQ3Freq_Value,DIVR1Freq_Value,DIVR2Freq_Value,DIVR3Freq_Value,DSIFreq_Value,DSITXEscFreq_Value,FDCANFreq_Value,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,HRTIMFreq_Value,I2C123Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM345Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,PLLDSIVCOFreq_Value,PWR_Regulator_Voltage_Scale,QSPIFreq_Value,RNGFreq_Value,RTCFreq_Value,SAI1Freq_Value,SAI23Freq_Value,SAI4AFreq_Value,SAI4BFreq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI123Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SupplySource,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16Freq_Value,USART234578Freq_Value,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPTIM345Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LTDCFreq_Value=129000000
+RCC.MCO1PinFreq_Value=64000000
+RCC.MCO2PinFreq_Value=64000000
+RCC.PLLDSIVCOFreq_Value=1000000000
+RCC.PWR_Regulator_Voltage_Scale=PWR_REGULATOR_VOLTAGE_SCALE1
+RCC.QSPIFreq_Value=64000000
+RCC.RNGFreq_Value=48000000
+RCC.RTCFreq_Value=32000
+RCC.SAI1Freq_Value=129000000
+RCC.SAI23Freq_Value=129000000
+RCC.SAI4AFreq_Value=129000000
+RCC.SAI4BFreq_Value=129000000
+RCC.SDMMCFreq_Value=129000000
+RCC.SPDIFRXFreq_Value=129000000
+RCC.SPI123Freq_Value=129000000
+RCC.SPI45Freq_Value=64000000
+RCC.SPI6Freq_Value=64000000
+RCC.SWPMI1Freq_Value=64000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SupplySource=PWR_DIRECT_SMPS_SUPPLY
+RCC.Tim1OutputFreq_Value=64000000
+RCC.Tim2OutputFreq_Value=64000000
+RCC.TraceFreq_Value=64000000
+RCC.USART16Freq_Value=64000000
+RCC.USART234578Freq_Value=64000000
+RCC.USBFreq_Value=129000000
+RCC.VCO1OutputFreq_Value=258000000
+RCC.VCO2OutputFreq_Value=258000000
+RCC.VCO3OutputFreq_Value=258000000
+RCC.VCOInput1Freq_Value=2000000
+RCC.VCOInput2Freq_Value=2000000
+RCC.VCOInput3Freq_Value=2000000
+USART1.IPParameters=VirtualMode-Asynchronous
+USART1.VirtualMode-Asynchronous=VM_ASYNC
+VP_SYS_M4_VS_Systick.Mode=SysTick
+VP_SYS_M4_VS_Systick.Signal=SYS_M4_VS_Systick
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/MDK-ARM/CubeMX_Config.uvoptx b/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/MDK-ARM/CubeMX_Config.uvoptx
new file mode 100644
index 0000000000..73cfc44f35
--- /dev/null
+++ b/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/MDK-ARM/CubeMX_Config.uvoptx
@@ -0,0 +1,262 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+	<Target>
+		<TargetName>CubeMX_Config_CM4</TargetName>
+		<ToolsetNumber>0x4</ToolsetNumber>
+		<ToolsetName>ARM-ADS</ToolsetName>
+		<TargetOption>
+			<CLKADS>64000000</CLKADS>
+			<OPTTT>
+				<gFlags>1</gFlags>
+				<BeepAtEnd>1</BeepAtEnd>
+				<RunSim>0</RunSim>
+				<RunTarget>1</RunTarget>
+			</OPTTT>
+			<OPTHX>
+				<HexSelection>1</HexSelection>
+				<FlashByte>65535</FlashByte>
+				<HexRangeLowAddress>0</HexRangeLowAddress>
+				<HexRangeHighAddress>0</HexRangeHighAddress>
+				<HexOffset>0</HexOffset>
+			</OPTHX>
+			<OPTLEX>
+				<PageWidth>79</PageWidth>
+				<PageLength>66</PageLength>
+				<TabStop>8</TabStop>
+				<ListingPath />
+			</OPTLEX>
+			<ListingPage>
+				<CreateCListing>1</CreateCListing>
+				<CreateAListing>1</CreateAListing>
+				<CreateLListing>1</CreateLListing>
+				<CreateIListing>0</CreateIListing>
+				<AsmCond>1</AsmCond>
+				<AsmSymb>1</AsmSymb>
+				<AsmXref>0</AsmXref>
+				<CCond>1</CCond>
+				<CCode>0</CCode>
+				<CListInc>0</CListInc>
+				<CSymb>0</CSymb>
+				<LinkerCodeListing>0</LinkerCodeListing>
+			</ListingPage>
+			<OPTXL>
+				<LMap>1</LMap>
+				<LComments>1</LComments>
+				<LGenerateSymbols>1</LGenerateSymbols>
+				<LLibSym>1</LLibSym>
+				<LLines>1</LLines>
+				<LLocSym>1</LLocSym>
+				<LPubSym>1</LPubSym>
+				<LXref>0</LXref>
+				<LExpSel>0</LExpSel>
+			</OPTXL>
+			<OPTFL>
+				<tvExp>0</tvExp>
+				<tvExpOptDlg>0</tvExpOptDlg>
+				<IsCurrentTarget>1</IsCurrentTarget>
+			</OPTFL>
+			<CpuCode>0</CpuCode>
+			<DebugOpt>
+				<uSim>0</uSim>
+				<uTrg>1</uTrg>
+				<sLdApp>1</sLdApp>
+				<sGomain>1</sGomain>
+				<sRbreak>1</sRbreak>
+				<sRwatch>1</sRwatch>
+				<sRmem>1</sRmem>
+				<sRfunc>1</sRfunc>
+				<sRbox>1</sRbox>
+				<tLdApp>1</tLdApp>
+				<tGomain>1</tGomain>
+				<tRbreak>1</tRbreak>
+				<tRwatch>1</tRwatch>
+				<tRmem>1</tRmem>
+				<tRfunc>1</tRfunc>
+				<tRbox>1</tRbox>
+				<sRunDeb>0</sRunDeb>
+				<sLrtime>0</sLrtime>
+				<nTsel>13</nTsel>
+				<sDll />
+				<sDllPa />
+				<sDlgDll />
+				<sDlgPa />
+				<sIfile />
+				<tDll />
+				<tDllPa />
+				<tDlgDll />
+				<tDlgPa />
+				<tIfile />
+				<pMon>STLink\ST-LINKIII-KEIL_SWO.dll</pMon>
+			</DebugOpt>
+			<TargetDriverDllRegistry>
+				<SetRegEntry>
+					<Number>0</Number>
+					<Key>ST-LINKIII-KEIL_SWO</Key>
+					<Name>-U-O142 -O2254 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(5BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32H7xx.FLM -FS08000000 -FL0200000 -FP0($$Device:STM32H747XI$Flash\STM32H7xx.FLM)</Name>
+				</SetRegEntry>
+				<SetRegEntry>
+					<Number>0</Number>
+					<Key />
+					<Name>-U-O142 -O2254 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(5BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32H7xx.FLM -FS08000000 -FL0200000 -FP0($$Device:STM32H747XI$Flash\STM32H7xx.FLM)</Name>
+				</SetRegEntry>
+			</TargetDriverDllRegistry>
+			<DebugFlag>
+				<trace>0</trace>
+				<periodic>1</periodic>
+				<aLwin>0</aLwin>
+				<aCover>0</aCover>
+				<aSer1>0</aSer1>
+				<aSer2>0</aSer2>
+				<aPa>0</aPa>
+				<viewmode>0</viewmode>
+				<vrSel>0</vrSel>
+				<aSym>0</aSym>
+				<aTbox>0</aTbox>
+				<AscS1>0</AscS1>
+				<AscS2>0</AscS2>
+				<AscS3>0</AscS3>
+				<aSer3>0</aSer3>
+				<eProf>0</eProf>
+				<aLa>0</aLa>
+				<aPa1>0</aPa1>
+				<AscS4>0</AscS4>
+				<aSer4>0</aSer4>
+				<StkLoc>0</StkLoc>
+				<TrcWin>0</TrcWin>
+				<newCpu>0</newCpu>
+				<uProt>0</uProt>
+			</DebugFlag>
+			<LintExecutable />
+			<LintConfigFile />
+		</TargetOption>
+	</Target>
+<Target>
+		<TargetName>CubeMX_Config_CM7</TargetName>
+		<ToolsetNumber>0x4</ToolsetNumber>
+		<ToolsetName>ARM-ADS</ToolsetName>
+		<TargetOption>
+			<CLKADS>64000000</CLKADS>
+			<OPTTT>
+				<gFlags>1</gFlags>
+				<BeepAtEnd>1</BeepAtEnd>
+				<RunSim>0</RunSim>
+				<RunTarget>1</RunTarget>
+			</OPTTT>
+			<OPTHX>
+				<HexSelection>1</HexSelection>
+				<FlashByte>65535</FlashByte>
+				<HexRangeLowAddress>0</HexRangeLowAddress>
+				<HexRangeHighAddress>0</HexRangeHighAddress>
+				<HexOffset>0</HexOffset>
+			</OPTHX>
+			<OPTLEX>
+				<PageWidth>79</PageWidth>
+				<PageLength>66</PageLength>
+				<TabStop>8</TabStop>
+				<ListingPath />
+			</OPTLEX>
+			<ListingPage>
+				<CreateCListing>1</CreateCListing>
+				<CreateAListing>1</CreateAListing>
+				<CreateLListing>1</CreateLListing>
+				<CreateIListing>0</CreateIListing>
+				<AsmCond>1</AsmCond>
+				<AsmSymb>1</AsmSymb>
+				<AsmXref>0</AsmXref>
+				<CCond>1</CCond>
+				<CCode>0</CCode>
+				<CListInc>0</CListInc>
+				<CSymb>0</CSymb>
+				<LinkerCodeListing>0</LinkerCodeListing>
+			</ListingPage>
+			<OPTXL>
+				<LMap>1</LMap>
+				<LComments>1</LComments>
+				<LGenerateSymbols>1</LGenerateSymbols>
+				<LLibSym>1</LLibSym>
+				<LLines>1</LLines>
+				<LLocSym>1</LLocSym>
+				<LPubSym>1</LPubSym>
+				<LXref>0</LXref>
+				<LExpSel>0</LExpSel>
+			</OPTXL>
+			<OPTFL>
+				<tvExp>0</tvExp>
+				<tvExpOptDlg>0</tvExpOptDlg>
+				<IsCurrentTarget>1</IsCurrentTarget>
+			</OPTFL>
+			<CpuCode>0</CpuCode>
+			<DebugOpt>
+				<uSim>0</uSim>
+				<uTrg>1</uTrg>
+				<sLdApp>1</sLdApp>
+				<sGomain>1</sGomain>
+				<sRbreak>1</sRbreak>
+				<sRwatch>1</sRwatch>
+				<sRmem>1</sRmem>
+				<sRfunc>1</sRfunc>
+				<sRbox>1</sRbox>
+				<tLdApp>1</tLdApp>
+				<tGomain>1</tGomain>
+				<tRbreak>1</tRbreak>
+				<tRwatch>1</tRwatch>
+				<tRmem>1</tRmem>
+				<tRfunc>1</tRfunc>
+				<tRbox>1</tRbox>
+				<sRunDeb>0</sRunDeb>
+				<sLrtime>0</sLrtime>
+				<nTsel>13</nTsel>
+				<sDll />
+				<sDllPa />
+				<sDlgDll />
+				<sDlgPa />
+				<sIfile />
+				<tDll />
+				<tDllPa />
+				<tDlgDll />
+				<tDlgPa />
+				<tIfile />
+				<pMon>STLink\ST-LINKIII-KEIL_SWO.dll</pMon>
+			</DebugOpt>
+			<TargetDriverDllRegistry>
+				<SetRegEntry>
+					<Number>0</Number>
+					<Key>ST-LINKIII-KEIL_SWO</Key>
+					<Name>-U-O142 -O2254 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(5BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32H7x_2048.FLM -FS08000000 -FL0200000 -FP0($$Device:STM32H747XI$Flash\STM32H7x_2048.FLM)</Name>
+				</SetRegEntry>
+				<SetRegEntry>
+					<Number>0</Number>
+					<Key />
+					<Name>-U-O142 -O2254 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(5BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32H7x_2048.FLM -FS08000000 -FL0200000 -FP0($$Device:STM32H747XI$Flash\STM32H7x_2048.FLM)</Name>
+				</SetRegEntry>
+			</TargetDriverDllRegistry>
+			<DebugFlag>
+				<trace>0</trace>
+				<periodic>1</periodic>
+				<aLwin>0</aLwin>
+				<aCover>0</aCover>
+				<aSer1>0</aSer1>
+				<aSer2>0</aSer2>
+				<aPa>0</aPa>
+				<viewmode>0</viewmode>
+				<vrSel>0</vrSel>
+				<aSym>0</aSym>
+				<aTbox>0</aTbox>
+				<AscS1>0</AscS1>
+				<AscS2>0</AscS2>
+				<AscS3>0</AscS3>
+				<aSer3>0</aSer3>
+				<eProf>0</eProf>
+				<aLa>0</aLa>
+				<aPa1>0</aPa1>
+				<AscS4>0</AscS4>
+				<aSer4>0</aSer4>
+				<StkLoc>0</StkLoc>
+				<TrcWin>0</TrcWin>
+				<newCpu>0</newCpu>
+				<uProt>0</uProt>
+			</DebugFlag>
+			<LintExecutable />
+			<LintConfigFile />
+		</TargetOption>
+	</Target></ProjectOpt>
diff --git a/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/MDK-ARM/CubeMX_Config.uvprojx b/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/MDK-ARM/CubeMX_Config.uvprojx
new file mode 100644
index 0000000000..587dc54143
--- /dev/null
+++ b/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/MDK-ARM/CubeMX_Config.uvprojx
@@ -0,0 +1,1386 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?><Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" noNamespaceSchemaLocation="project_proj.xsd">
+
+	<SchemaVersion>1.1</SchemaVersion>
+
+	<Header>### uVision Project, (C) Keil Software</Header>
+
+	<Targets>
+		<Target> 
+			<TargetName>CubeMX_Config_CM4</TargetName>
+			<ToolsetNumber>0x4</ToolsetNumber>
+			<ToolsetName>ARM-ADS</ToolsetName>
+			<TargetOption>
+				<TargetCommonOption>
+					<Device>STM32H747XIHx:CM4</Device>
+					<Vendor>STMicroelectronics</Vendor>
+					<Cpu>IRAM(0x10000000-0x10047FFF) IROM(0x8100000-0x81FFFFF) CLOCK(12000000) FPU2 CPUTYPE("Cortex-M4")</Cpu>
+					<FlashUtilSpec/>
+					<StartupFile/>
+					<FlashDriverDll/>
+					<DeviceId/>
+					<RegisterFile/>
+					<MemoryEnv/>
+					<Cmp/>
+					<Asm/>
+					<Linker/>
+					<OHString/>
+					<InfinionOptionDll/>
+					<SLE66CMisc/>
+					<SLE66AMisc/>
+					<SLE66LinkerMisc/>
+					<SFDFile/>
+					<bCustSvd>0</bCustSvd>
+					<UseEnv>0</UseEnv>
+					<BinPath/>
+					<IncludePath/>
+					<LibPath/>
+					<RegisterFilePath/>
+					<DBRegisterFilePath/>
+					<TargetStatus>
+						<Error>0</Error>
+						<ExitCodeStop>0</ExitCodeStop>
+						<ButtonStop>0</ButtonStop>
+						<NotGenerated>0</NotGenerated>
+						<InvalidFlash>1</InvalidFlash>
+					</TargetStatus>
+					<OutputDirectory>CubeMX_Config_CM4\</OutputDirectory>
+					<OutputName>CubeMX_Config_CM4</OutputName>
+					<CreateExecutable>1</CreateExecutable>
+					<CreateLib>0</CreateLib>
+					<CreateHexFile>1</CreateHexFile>
+					<DebugInformation>1</DebugInformation>
+					<BrowseInformation>1</BrowseInformation>
+					<ListingPath>./CubeMX_Config_CM4/</ListingPath>
+					<HexFormatSelection>1</HexFormatSelection>
+					<Merge32K>0</Merge32K>
+					<CreateBatchFile>0</CreateBatchFile>
+					<BeforeCompile>
+						<RunUserProg1>0</RunUserProg1>
+						<RunUserProg2>0</RunUserProg2>
+						<UserProg1Name/>
+						<UserProg2Name/>
+						<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+						<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+					</BeforeCompile>
+					<BeforeMake>
+						<RunUserProg1>0</RunUserProg1>
+						<RunUserProg2>0</RunUserProg2>
+						<UserProg1Name/>
+						<UserProg2Name/>
+						<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+						<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+						<nStopB1X>0</nStopB1X>
+						<nStopB2X>0</nStopB2X>
+					</BeforeMake>
+					<AfterMake>
+						<RunUserProg1>0</RunUserProg1>
+						<RunUserProg2>0</RunUserProg2>
+						<UserProg1Name/>
+						<UserProg2Name/>
+						<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+						<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+					</AfterMake>
+					<SelectedForBatchBuild>0</SelectedForBatchBuild>
+					<SVCSIdString/>
+				</TargetCommonOption>
+				<CommonProperty>
+					<UseCPPCompiler>0</UseCPPCompiler>
+					<RVCTCodeConst>0</RVCTCodeConst>
+					<RVCTZI>0</RVCTZI>
+					<RVCTOtherData>0</RVCTOtherData>
+					<ModuleSelection>0</ModuleSelection>
+					<IncludeInBuild>1</IncludeInBuild>
+					<AlwaysBuild>0</AlwaysBuild>
+					<GenerateAssemblyFile>0</GenerateAssemblyFile>
+					<AssembleAssemblyFile>0</AssembleAssemblyFile>
+					<PublicsOnly>0</PublicsOnly>
+					<StopOnExitCode>3</StopOnExitCode>
+					<CustomArgument/>
+					<IncludeLibraryModules/>
+					<ComprImg/>
+				</CommonProperty>
+				<DllOption>
+					<SimDllName>SARMCM3.DLL</SimDllName>
+					<SimDllArguments>-REMAP -MPU</SimDllArguments>
+					<SimDlgDll>DCM.DLL</SimDlgDll>
+					<SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+					<TargetDllName>SARMCM3.DLL</TargetDllName>
+					<TargetDllArguments>-MPU</TargetDllArguments>
+					<TargetDlgDll>TCM.DLL</TargetDlgDll>
+					<TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+				</DllOption>
+				<DebugOption>
+					<OPTHX>
+						<HexSelection>1</HexSelection>
+						<HexRangeLowAddress>0</HexRangeLowAddress>
+						<HexRangeHighAddress>0</HexRangeHighAddress>
+						<HexOffset>0</HexOffset>
+						<Oh166RecLen>16</Oh166RecLen>
+					</OPTHX>
+					<Simulator>
+						<UseSimulator>0</UseSimulator>
+						<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+						<RunToMain>1</RunToMain>
+						<RestoreBreakpoints>1</RestoreBreakpoints>
+						<RestoreWatchpoints>1</RestoreWatchpoints>
+						<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+						<RestoreFunctions>1</RestoreFunctions>
+						<RestoreToolbox>1</RestoreToolbox>
+						<LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+						<RestoreSysVw>1</RestoreSysVw>
+					</Simulator>
+					<Target>
+						<UseTarget>1</UseTarget>
+						<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+						<RunToMain>1</RunToMain>
+						<RestoreBreakpoints>1</RestoreBreakpoints>
+						<RestoreWatchpoints>1</RestoreWatchpoints>
+						<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+						<RestoreFunctions>0</RestoreFunctions>
+						<RestoreToolbox>1</RestoreToolbox>
+						<RestoreTracepoints>1</RestoreTracepoints> 
+						<RestoreSysVw>1</RestoreSysVw>
+					</Target>
+					<RunDebugAfterBuild>0</RunDebugAfterBuild>
+					<TargetSelection>13</TargetSelection>
+					<SimDlls>
+						<CpuDll/>
+						<CpuDllArguments/>
+						<PeripheralDll/>
+						<PeripheralDllArguments/>
+						<InitializationFile/>
+					</SimDlls>
+					<TargetDlls>
+						<CpuDll/>
+						<CpuDllArguments/>
+						<PeripheralDll/>
+						<PeripheralDllArguments/>
+						<InitializationFile/>
+						<Driver>STLink\ST-LINKIII-KEIL_SWO.dll</Driver>
+					</TargetDlls>
+				</DebugOption>
+				<Utilities>
+					<Flash1>
+						<UseTargetDll>1</UseTargetDll>
+						<UseExternalTool>0</UseExternalTool>
+						<RunIndependent>0</RunIndependent>
+						<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+						<Capability>1</Capability>
+						<DriverSelection>4107</DriverSelection>
+					</Flash1>
+					<bUseTDR>1</bUseTDR>
+					<Flash2>STLink\ST-LINKIII-KEIL_SWO.dll</Flash2>
+					<Flash3/>
+					<Flash4/>
+					<pFcarmOut/>
+					<pFcarmGrp/>
+					<pFcArmRoot/>
+					<FcArmLst>0</FcArmLst>
+				</Utilities>
+				<TargetArmAds>
+					<ArmAdsMisc>
+						<GenerateListings>0</GenerateListings>
+						<asHll>1</asHll>
+						<asAsm>1</asAsm>
+						<asMacX>1</asMacX>
+						<asSyms>1</asSyms>
+						<asFals>1</asFals>
+						<asDbgD>1</asDbgD>
+						<asForm>1</asForm>
+						<ldLst>0</ldLst>
+						<ldmm>1</ldmm>
+						<ldXref>1</ldXref>
+						<BigEnd>0</BigEnd>
+						<AdsALst>1</AdsALst>
+						<AdsACrf>1</AdsACrf>
+						<AdsANop>0</AdsANop>
+						<AdsANot>0</AdsANot>
+						<AdsLLst>1</AdsLLst>
+						<AdsLmap>1</AdsLmap>
+						<AdsLcgr>1</AdsLcgr>
+						<AdsLsym>1</AdsLsym>
+						<AdsLszi>1</AdsLszi>
+						<AdsLtoi>1</AdsLtoi>
+						<AdsLsun>1</AdsLsun>
+						<AdsLven>1</AdsLven>
+						<AdsLsxf>1</AdsLsxf>
+						<RvctClst>0</RvctClst>
+						<GenPPlst>0</GenPPlst>
+						<AdsCpuType>"Cortex-M4"</AdsCpuType>
+						<RvctDeviceName/>
+						<mOS>0</mOS>
+						<uocRom>0</uocRom>
+						<uocRam>0</uocRam>
+						<hadIROM>1</hadIROM>
+						<hadIRAM>1</hadIRAM>
+						<hadXRAM>0</hadXRAM>
+						<uocXRam>0</uocXRam>
+						<RvdsVP>2</RvdsVP>
+						<hadIRAM2>0</hadIRAM2>
+						<hadIROM2>0</hadIROM2>
+						<StupSel>8</StupSel>
+						<useUlib>1</useUlib>
+						<EndSel>0</EndSel>
+						<uLtcg>0</uLtcg>
+						<RoSelD>3</RoSelD>
+						<RwSelD>3</RwSelD>
+						<CodeSel>0</CodeSel>
+						<OptFeed>0</OptFeed>
+						<NoZi1>0</NoZi1>
+						<NoZi2>0</NoZi2>
+						<NoZi3>0</NoZi3>
+						<NoZi4>0</NoZi4>
+						<NoZi5>0</NoZi5>
+						<Ro1Chk>0</Ro1Chk>
+						<Ro2Chk>0</Ro2Chk>
+						<Ro3Chk>0</Ro3Chk>
+						<Ir1Chk>1</Ir1Chk>
+						<Ir2Chk>0</Ir2Chk>
+						<Ra1Chk>0</Ra1Chk>
+						<Ra2Chk>0</Ra2Chk>
+						<Ra3Chk>0</Ra3Chk>
+						<Im1Chk>1</Im1Chk>
+						<Im2Chk>0</Im2Chk>
+						<OnChipMemories>
+							<Ocm1>
+								<Type>0</Type>
+								<StartAddress>0x0</StartAddress>
+								<Size>0x0</Size>
+							</Ocm1>
+							<Ocm2>
+								<Type>0</Type>
+								<StartAddress>0x0</StartAddress>
+								<Size>0x0</Size>
+							</Ocm2>
+							<Ocm3>
+								<Type>0</Type>
+								<StartAddress>0x0</StartAddress>
+								<Size>0x0</Size>
+							</Ocm3>
+							<Ocm4>
+								<Type>0</Type>
+								<StartAddress>0x0</StartAddress>
+								<Size>0x0</Size>
+							</Ocm4>
+							<Ocm5>
+								<Type>0</Type>
+								<StartAddress>0x0</StartAddress>
+								<Size>0x0</Size>
+							</Ocm5>
+							<Ocm6>
+								<Type>0</Type>
+								<StartAddress>0x0</StartAddress>
+								<Size>0x0</Size>
+							</Ocm6>
+							<IRAM>
+								<Type>0</Type>
+								<StartAddress/>
+								<Size/>
+							</IRAM>
+							<IROM>
+								<Type>1</Type>
+								<StartAddress/>
+								<Size/>
+							</IROM>
+							<XRAM>
+								<Type>0</Type>
+								<StartAddress>0x0</StartAddress>
+								<Size>0x0</Size>
+							</XRAM>
+							<OCR_RVCT1>
+								<Type>1</Type>
+								<StartAddress>0x0</StartAddress>
+								<Size>0x0</Size>
+							</OCR_RVCT1>
+							<OCR_RVCT2>
+								<Type>1</Type>
+								<StartAddress>0x0</StartAddress>
+								<Size>0x0</Size>
+							</OCR_RVCT2>
+							<OCR_RVCT3>
+								<Type>1</Type>
+								<StartAddress>0x0</StartAddress>
+								<Size>0x0</Size>
+							</OCR_RVCT3>
+							<OCR_RVCT4>
+								<Type>1</Type>
+								<StartAddress/>
+								<Size/>
+							</OCR_RVCT4>
+							<OCR_RVCT5>
+								<Type>1</Type>
+								<StartAddress>0x0</StartAddress>
+								<Size>0x0</Size>
+							</OCR_RVCT5>
+							<OCR_RVCT6>
+								<Type>0</Type>
+								<StartAddress>0x0</StartAddress>
+								<Size>0x0</Size>
+							</OCR_RVCT6>
+							<OCR_RVCT7>
+								<Type>0</Type>
+								<StartAddress>0x0</StartAddress>
+								<Size>0x0</Size>
+							</OCR_RVCT7>
+							<OCR_RVCT8>
+								<Type>0</Type>
+								<StartAddress>0x0</StartAddress>
+								<Size>0x0</Size>
+							</OCR_RVCT8>
+							<OCR_RVCT9>
+								<Type>0</Type>
+								<StartAddress/>
+								<Size/>
+							</OCR_RVCT9>
+							<OCR_RVCT10>
+								<Type>0</Type>
+								<StartAddress>0x0</StartAddress>
+								<Size>0x0</Size>
+							</OCR_RVCT10>
+						</OnChipMemories>
+						<RvctStartVector/>
+					</ArmAdsMisc>
+					<Cads>
+						<interw>1</interw>
+						<Optim>4</Optim>
+						<oTime>0</oTime>
+						<SplitLS>0</SplitLS>
+						<OneElfS>1</OneElfS>
+						<Strict>0</Strict>
+						<EnumInt>0</EnumInt>
+						<PlainCh>0</PlainCh>
+						<Ropi>0</Ropi>
+						<Rwpi>0</Rwpi>
+						<wLevel>2</wLevel>
+						<uThumb>0</uThumb>
+						<uSurpInc>0</uSurpInc>
+						<uC99>1</uC99>
+						<useXO>0</useXO>
+						<VariousControls>
+							<MiscControls/>
+							<Define>CORE_CM4,USE_HAL_DRIVER,STM32H747xx</Define>
+							<Undefine/>
+							<IncludePath>../CM4/Inc;../Drivers/STM32H7xx_HAL_Driver/Inc;../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy;../Drivers/CMSIS/Device/ST/STM32H7xx/Include;../Drivers/CMSIS/Include</IncludePath>
+						</VariousControls>
+					</Cads>
+					<Aads>
+						<interw>1</interw>
+						<Ropi>0</Ropi>
+						<Rwpi>0</Rwpi>
+						<thumb>0</thumb>
+						<SplitLS>0</SplitLS>
+						<SwStkChk>0</SwStkChk>
+						<NoWarn>0</NoWarn>
+						<VariousControls>
+							<MiscControls/>
+							<Define/>
+							<Undefine/>
+							<IncludePath/>
+						</VariousControls>
+					</Aads>
+					<LDads>
+						<umfTarg>0</umfTarg>
+						<Ropi>0</Ropi>
+						<Rwpi>0</Rwpi>
+						<noStLib>0</noStLib>
+						<RepFail>1</RepFail>
+						<useFile>0</useFile>
+						<TextAddressRange>0x08000000</TextAddressRange>
+						<DataAddressRange>0x20000000</DataAddressRange>
+						<pXoBase/>
+						<ScatterFile>stm32h747xx_flash_CM4.sct</ScatterFile>
+						<IncludeLibs/>
+						<IncludeLibsPath/>
+						<Misc/>
+						<LinkerInputFile/>
+						<DisabledWarnings/>
+					</LDads>
+				</TargetArmAds>
+			</TargetOption>     
+			<Groups>
+        <Group>
+					<GroupName>Application/MDK-ARM</GroupName>
+				<Files>
+            <File>
+              <FileName>startup_stm32h747xx_CM4.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>startup_stm32h747xx_CM4.s</FilePath>
+            </File>
+            <File>
+              <FileName>startup_stm32h747xx_CM7.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>startup_stm32h747xx_CM7.s</FilePath>
+              <FileOption>
+                <CommonProperty>
+                  <UseCPPCompiler>2</UseCPPCompiler>
+                  <RVCTCodeConst>0</RVCTCodeConst>
+                  <RVCTZI>0</RVCTZI>
+                  <RVCTOtherData>0</RVCTOtherData>
+                  <ModuleSelection>0</ModuleSelection>
+                  <IncludeInBuild>0</IncludeInBuild>
+                  <AlwaysBuild>2</AlwaysBuild>
+                  <GenerateAssemblyFile>2</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>2</AssembleAssemblyFile>
+                  <PublicsOnly>2</PublicsOnly>
+                  <StopOnExitCode>11</StopOnExitCode>
+                </CommonProperty>
+                <FileArmAds>
+                  <Cads>
+                    <interw>2</interw>
+                    <Optim>0</Optim>
+                    <oTime>2</oTime>
+                    <SplitLS>2</SplitLS>
+                    <OneElfS>2</OneElfS>
+                    <Strict>2</Strict>
+                    <EnumInt>2</EnumInt>
+                    <PlainCh>2</PlainCh>
+                    <Ropi>2</Ropi>
+                    <Rwpi>2</Rwpi>
+                    <wLevel>0</wLevel>
+                    <uThumb>2</uThumb>
+                    <uSurpInc>2</uSurpInc>
+                    <uC99>2</uC99>
+                    <useXO>2</useXO>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+            </File>
+          </Files>
+        </Group>
+				
+				<Group>
+					<GroupName>::CMSIS</GroupName>
+				</Group>
+			<Group>
+          <GroupName>Application/User/CM4</GroupName>
+          <Files>
+            <File>
+              <FileName>main.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../CM4/Src/main.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_it.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../CM4/Src/stm32h7xx_it.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_msp.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../CM4/Src/stm32h7xx_hal_msp.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Application/User/CM7</GroupName>
+          <GroupOption>
+            <CommonProperty>
+              <UseCPPCompiler>0</UseCPPCompiler>
+              <RVCTCodeConst>0</RVCTCodeConst>
+              <RVCTZI>0</RVCTZI>
+              <RVCTOtherData>0</RVCTOtherData>
+              <ModuleSelection>0</ModuleSelection>
+              <IncludeInBuild>0</IncludeInBuild>
+              <AlwaysBuild>2</AlwaysBuild>
+              <GenerateAssemblyFile>2</GenerateAssemblyFile>
+              <AssembleAssemblyFile>2</AssembleAssemblyFile>
+              <PublicsOnly>2</PublicsOnly>
+              <StopOnExitCode>11</StopOnExitCode>
+            </CommonProperty>
+            <GroupArmAds>
+              <Cads>
+                <interw>2</interw>
+                <Optim>2</Optim>
+                <oTime>1</oTime>
+                <SplitLS>2</SplitLS>
+                <OneElfS>2</OneElfS>
+                <Strict>2</Strict>
+                <EnumInt>2</EnumInt>
+                <PlainCh>2</PlainCh>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <wLevel>0</wLevel>
+                <uThumb>2</uThumb>
+                <uSurpInc>2</uSurpInc>
+                <uC99>2</uC99>
+                <useXO>2</useXO>
+              </Cads>
+              <Aads>
+                <interw>2</interw>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <thumb>2</thumb>
+                <SplitLS>2</SplitLS>
+                <SwStkChk>2</SwStkChk>
+                <NoWarn>2</NoWarn>
+                <uSurpInc>2</uSurpInc>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+          <Files>
+            <File>
+              <FileName>main.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../CM7/Src/main.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_it.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../CM7/Src/stm32h7xx_it.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_msp.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../CM7/Src/stm32h7xx_hal_msp.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Drivers/STM32H7xx_HAL_Driver</GroupName>
+          <Files>
+            <File>
+              <FileName>stm32h7xx_hal_cortex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_tim.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_tim_ex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_uart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c</FilePath>
+              <FileOption>
+                <CommonProperty>
+                  <UseCPPCompiler>2</UseCPPCompiler>
+                  <RVCTCodeConst>0</RVCTCodeConst>
+                  <RVCTZI>0</RVCTZI>
+                  <RVCTOtherData>0</RVCTOtherData>
+                  <ModuleSelection>0</ModuleSelection>
+                  <IncludeInBuild>0</IncludeInBuild>
+                  <AlwaysBuild>2</AlwaysBuild>
+                  <GenerateAssemblyFile>2</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>2</AssembleAssemblyFile>
+                  <PublicsOnly>2</PublicsOnly>
+                  <StopOnExitCode>11</StopOnExitCode>
+                </CommonProperty>
+                <FileArmAds>
+                  <Cads>
+                    <interw>2</interw>
+                    <Optim>0</Optim>
+                    <oTime>2</oTime>
+                    <SplitLS>2</SplitLS>
+                    <OneElfS>2</OneElfS>
+                    <Strict>2</Strict>
+                    <EnumInt>2</EnumInt>
+                    <PlainCh>2</PlainCh>
+                    <Ropi>2</Ropi>
+                    <Rwpi>2</Rwpi>
+                    <wLevel>0</wLevel>
+                    <uThumb>2</uThumb>
+                    <uSurpInc>2</uSurpInc>
+                    <uC99>2</uC99>
+                    <useXO>2</useXO>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_uart_ex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c</FilePath>
+              <FileOption>
+                <CommonProperty>
+                  <UseCPPCompiler>2</UseCPPCompiler>
+                  <RVCTCodeConst>0</RVCTCodeConst>
+                  <RVCTZI>0</RVCTZI>
+                  <RVCTOtherData>0</RVCTOtherData>
+                  <ModuleSelection>0</ModuleSelection>
+                  <IncludeInBuild>0</IncludeInBuild>
+                  <AlwaysBuild>2</AlwaysBuild>
+                  <GenerateAssemblyFile>2</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>2</AssembleAssemblyFile>
+                  <PublicsOnly>2</PublicsOnly>
+                  <StopOnExitCode>11</StopOnExitCode>
+                </CommonProperty>
+                <FileArmAds>
+                  <Cads>
+                    <interw>2</interw>
+                    <Optim>0</Optim>
+                    <oTime>2</oTime>
+                    <SplitLS>2</SplitLS>
+                    <OneElfS>2</OneElfS>
+                    <Strict>2</Strict>
+                    <EnumInt>2</EnumInt>
+                    <PlainCh>2</PlainCh>
+                    <Ropi>2</Ropi>
+                    <Rwpi>2</Rwpi>
+                    <wLevel>0</wLevel>
+                    <uThumb>2</uThumb>
+                    <uSurpInc>2</uSurpInc>
+                    <uC99>2</uC99>
+                    <useXO>2</useXO>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_rcc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_rcc_ex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_flash.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_flash_ex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_gpio.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_hsem.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_dma.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_dma_ex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_mdma.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_pwr.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_pwr_ex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_i2c.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_i2c_ex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_exti.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Drivers/CMSIS</GroupName>
+          <Files>
+            <File>
+              <FileName>system_stm32h7xx_dualcore_boot_cm4_cm7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../Common/Src/system_stm32h7xx_dualcore_boot_cm4_cm7.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+      </Groups>
+
+		</Target>
+	<Target> 
+			<TargetName>CubeMX_Config_CM7</TargetName>
+			<ToolsetNumber>0x4</ToolsetNumber>
+			<ToolsetName>ARM-ADS</ToolsetName>
+			<TargetOption>
+				<TargetCommonOption>
+					<Device>STM32H747XIHx:CM7</Device>
+					<Vendor>STMicroelectronics</Vendor>
+					<Cpu>IRAM(0x20000000-0x2001FFFF) IRAM2(0x24000000-0x2407FFFF) IROM(0x8000000-0x80FFFFF) CLOCK(12000000) FPU3(DFPU) CPUTYPE("Cortex-M7") ELITTLE</Cpu>
+					<FlashUtilSpec/>
+					<StartupFile/>
+					<FlashDriverDll/>
+					<DeviceId/>
+					<RegisterFile/>
+					<MemoryEnv/>
+					<Cmp/>
+					<Asm/>
+					<Linker/>
+					<OHString/>
+					<InfinionOptionDll/>
+					<SLE66CMisc/>
+					<SLE66AMisc/>
+					<SLE66LinkerMisc/>
+					<SFDFile/>
+					<bCustSvd>0</bCustSvd>
+					<UseEnv>0</UseEnv>
+					<BinPath/>
+					<IncludePath/>
+					<LibPath/>
+					<RegisterFilePath/>
+					<DBRegisterFilePath/>
+					<TargetStatus>
+						<Error>0</Error>
+						<ExitCodeStop>0</ExitCodeStop>
+						<ButtonStop>0</ButtonStop>
+						<NotGenerated>0</NotGenerated>
+						<InvalidFlash>1</InvalidFlash>
+					</TargetStatus>
+					<OutputDirectory>CubeMX_Config_CM7\</OutputDirectory>
+					<OutputName>CubeMX_Config_CM7</OutputName>
+					<CreateExecutable>1</CreateExecutable>
+					<CreateLib>0</CreateLib>
+					<CreateHexFile>0</CreateHexFile>
+					<DebugInformation>1</DebugInformation>
+					<BrowseInformation>1</BrowseInformation>
+					<ListingPath>./CubeMX_Config_CM7/</ListingPath>
+					<HexFormatSelection>1</HexFormatSelection>
+					<Merge32K>0</Merge32K>
+					<CreateBatchFile>0</CreateBatchFile>
+					<BeforeCompile>
+						<RunUserProg1>0</RunUserProg1>
+						<RunUserProg2>0</RunUserProg2>
+						<UserProg1Name/>
+						<UserProg2Name/>
+						<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+						<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+					</BeforeCompile>
+					<BeforeMake>
+						<RunUserProg1>0</RunUserProg1>
+						<RunUserProg2>0</RunUserProg2>
+						<UserProg1Name/>
+						<UserProg2Name/>
+						<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+						<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+						<nStopB1X>0</nStopB1X>
+						<nStopB2X>0</nStopB2X>
+					</BeforeMake>
+					<AfterMake>
+						<RunUserProg1>0</RunUserProg1>
+						<RunUserProg2>0</RunUserProg2>
+						<UserProg1Name/>
+						<UserProg2Name/>
+						<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+						<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+					</AfterMake>
+					<SelectedForBatchBuild>0</SelectedForBatchBuild>
+					<SVCSIdString/>
+				</TargetCommonOption>
+				<CommonProperty>
+					<UseCPPCompiler>0</UseCPPCompiler>
+					<RVCTCodeConst>0</RVCTCodeConst>
+					<RVCTZI>0</RVCTZI>
+					<RVCTOtherData>0</RVCTOtherData>
+					<ModuleSelection>0</ModuleSelection>
+					<IncludeInBuild>1</IncludeInBuild>
+					<AlwaysBuild>0</AlwaysBuild>
+					<GenerateAssemblyFile>0</GenerateAssemblyFile>
+					<AssembleAssemblyFile>0</AssembleAssemblyFile>
+					<PublicsOnly>0</PublicsOnly>
+					<StopOnExitCode>3</StopOnExitCode>
+					<CustomArgument/>
+					<IncludeLibraryModules/>
+					<ComprImg/>
+				</CommonProperty>
+				<DllOption>
+					<SimDllName>SARMCM3.DLL</SimDllName>
+					<SimDllArguments>-REMAP -MPU</SimDllArguments>
+					<SimDlgDll>DCM.DLL</SimDlgDll>
+					<SimDlgDllArguments>-pCM7</SimDlgDllArguments>
+					<TargetDllName>SARMCM3.DLL</TargetDllName>
+					<TargetDllArguments>-MPU</TargetDllArguments>
+					<TargetDlgDll>TCM.DLL</TargetDlgDll>
+					<TargetDlgDllArguments>-pCM7</TargetDlgDllArguments>
+				</DllOption>
+				<DebugOption>
+					<OPTHX>
+						<HexSelection>1</HexSelection>
+						<HexRangeLowAddress>0</HexRangeLowAddress>
+						<HexRangeHighAddress>0</HexRangeHighAddress>
+						<HexOffset>0</HexOffset>
+						<Oh166RecLen>16</Oh166RecLen>
+					</OPTHX>
+					<Simulator>
+						<UseSimulator>0</UseSimulator>
+						<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+						<RunToMain>1</RunToMain>
+						<RestoreBreakpoints>1</RestoreBreakpoints>
+						<RestoreWatchpoints>1</RestoreWatchpoints>
+						<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+						<RestoreFunctions>1</RestoreFunctions>
+						<RestoreToolbox>1</RestoreToolbox>
+						<LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+						<RestoreSysVw>1</RestoreSysVw>
+					</Simulator>
+					<Target>
+						<UseTarget>1</UseTarget>
+						<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+						<RunToMain>1</RunToMain>
+						<RestoreBreakpoints>1</RestoreBreakpoints>
+						<RestoreWatchpoints>1</RestoreWatchpoints>
+						<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+						<RestoreFunctions>0</RestoreFunctions>
+						<RestoreToolbox>1</RestoreToolbox>
+						<RestoreTracepoints>1</RestoreTracepoints> 
+						<RestoreSysVw>1</RestoreSysVw>
+					</Target>
+					<RunDebugAfterBuild>0</RunDebugAfterBuild>
+					<TargetSelection>13</TargetSelection>
+					<SimDlls>
+						<CpuDll/>
+						<CpuDllArguments/>
+						<PeripheralDll/>
+						<PeripheralDllArguments/>
+						<InitializationFile/>
+					</SimDlls>
+					<TargetDlls>
+						<CpuDll/>
+						<CpuDllArguments/>
+						<PeripheralDll/>
+						<PeripheralDllArguments/>
+						<InitializationFile/>
+						<Driver>STLink\ST-LINKIII-KEIL_SWO.dll</Driver>
+					</TargetDlls>
+				</DebugOption>
+				<Utilities>
+					<Flash1>
+						<UseTargetDll>1</UseTargetDll>
+						<UseExternalTool>0</UseExternalTool>
+						<RunIndependent>0</RunIndependent>
+						<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+						<Capability>1</Capability>
+						<DriverSelection>4107</DriverSelection>
+					</Flash1>
+					<bUseTDR>1</bUseTDR>
+					<Flash2>STLink\ST-LINKIII-KEIL_SWO.dll</Flash2>
+					<Flash3/>
+					<Flash4/>
+					<pFcarmOut/>
+					<pFcarmGrp/>
+					<pFcArmRoot/>
+					<FcArmLst>0</FcArmLst>
+				</Utilities>
+				<TargetArmAds>
+					<ArmAdsMisc>
+						<GenerateListings>0</GenerateListings>
+						<asHll>1</asHll>
+						<asAsm>1</asAsm>
+						<asMacX>1</asMacX>
+						<asSyms>1</asSyms>
+						<asFals>1</asFals>
+						<asDbgD>1</asDbgD>
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+						<ldmm>1</ldmm>
+						<ldXref>1</ldXref>
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+						<AdsALst>1</AdsALst>
+						<AdsACrf>1</AdsACrf>
+						<AdsANop>0</AdsANop>
+						<AdsANot>0</AdsANot>
+						<AdsLLst>1</AdsLLst>
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+						<AdsLcgr>1</AdsLcgr>
+						<AdsLsym>1</AdsLsym>
+						<AdsLszi>1</AdsLszi>
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+						<AdsLsun>1</AdsLsun>
+						<AdsLven>1</AdsLven>
+						<AdsLsxf>1</AdsLsxf>
+						<RvctClst>0</RvctClst>
+						<GenPPlst>0</GenPPlst>
+						<AdsCpuType>"Cortex-M7"</AdsCpuType>
+						<RvctDeviceName/>
+						<mOS>0</mOS>
+						<uocRom>0</uocRom>
+						<uocRam>0</uocRam>
+						<hadIROM>1</hadIROM>
+						<hadIRAM>1</hadIRAM>
+						<hadXRAM>0</hadXRAM>
+						<uocXRam>0</uocXRam>
+						<RvdsVP>3</RvdsVP>
+						<hadIRAM2>0</hadIRAM2>
+						<hadIROM2>0</hadIROM2>
+						<StupSel>8</StupSel>
+						<useUlib>1</useUlib>
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+						<uLtcg>0</uLtcg>
+						<RoSelD>3</RoSelD>
+						<RwSelD>3</RwSelD>
+						<CodeSel>0</CodeSel>
+						<OptFeed>0</OptFeed>
+						<NoZi1>0</NoZi1>
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+						<NoZi3>0</NoZi3>
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+						<Ro1Chk>0</Ro1Chk>
+						<Ro2Chk>0</Ro2Chk>
+						<Ro3Chk>0</Ro3Chk>
+						<Ir1Chk>1</Ir1Chk>
+						<Ir2Chk>0</Ir2Chk>
+						<Ra1Chk>0</Ra1Chk>
+						<Ra2Chk>0</Ra2Chk>
+						<Ra3Chk>0</Ra3Chk>
+						<Im1Chk>1</Im1Chk>
+						<Im2Chk>0</Im2Chk>
+						<OnChipMemories>
+							<Ocm1>
+								<Type>0</Type>
+								<StartAddress>0x0</StartAddress>
+								<Size>0x0</Size>
+							</Ocm1>
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+								<Type>0</Type>
+								<StartAddress>0x0</StartAddress>
+								<Size>0x0</Size>
+							</Ocm2>
+							<Ocm3>
+								<Type>0</Type>
+								<StartAddress>0x0</StartAddress>
+								<Size>0x0</Size>
+							</Ocm3>
+							<Ocm4>
+								<Type>0</Type>
+								<StartAddress>0x0</StartAddress>
+								<Size>0x0</Size>
+							</Ocm4>
+							<Ocm5>
+								<Type>0</Type>
+								<StartAddress>0x0</StartAddress>
+								<Size>0x0</Size>
+							</Ocm5>
+							<Ocm6>
+								<Type>0</Type>
+								<StartAddress>0x0</StartAddress>
+								<Size>0x0</Size>
+							</Ocm6>
+							<IRAM>
+								<Type>0</Type>
+								<StartAddress/>
+								<Size/>
+							</IRAM>
+							<IROM>
+								<Type>1</Type>
+								<StartAddress/>
+								<Size/>
+							</IROM>
+							<XRAM>
+								<Type>0</Type>
+								<StartAddress>0x0</StartAddress>
+								<Size>0x0</Size>
+							</XRAM>
+							<OCR_RVCT1>
+								<Type>1</Type>
+								<StartAddress>0x0</StartAddress>
+								<Size>0x0</Size>
+							</OCR_RVCT1>
+							<OCR_RVCT2>
+								<Type>1</Type>
+								<StartAddress>0x0</StartAddress>
+								<Size>0x0</Size>
+							</OCR_RVCT2>
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+								<Type>1</Type>
+								<StartAddress>0x0</StartAddress>
+								<Size>0x0</Size>
+							</OCR_RVCT3>
+							<OCR_RVCT4>
+								<Type>1</Type>
+								<StartAddress/>
+								<Size/>
+							</OCR_RVCT4>
+							<OCR_RVCT5>
+								<Type>1</Type>
+								<StartAddress>0x0</StartAddress>
+								<Size>0x0</Size>
+							</OCR_RVCT5>
+							<OCR_RVCT6>
+								<Type>0</Type>
+								<StartAddress>0x0</StartAddress>
+								<Size>0x0</Size>
+							</OCR_RVCT6>
+							<OCR_RVCT7>
+								<Type>0</Type>
+								<StartAddress>0x0</StartAddress>
+								<Size>0x0</Size>
+							</OCR_RVCT7>
+							<OCR_RVCT8>
+								<Type>0</Type>
+								<StartAddress>0x0</StartAddress>
+								<Size>0x0</Size>
+							</OCR_RVCT8>
+							<OCR_RVCT9>
+								<Type>0</Type>
+								<StartAddress/>
+								<Size/>
+							</OCR_RVCT9>
+							<OCR_RVCT10>
+								<Type>0</Type>
+								<StartAddress>0x0</StartAddress>
+								<Size>0x0</Size>
+							</OCR_RVCT10>
+						</OnChipMemories>
+						<RvctStartVector/>
+					</ArmAdsMisc>
+					<Cads>
+						<interw>1</interw>
+						<Optim>4</Optim>
+						<oTime>0</oTime>
+						<SplitLS>0</SplitLS>
+						<OneElfS>1</OneElfS>
+						<Strict>0</Strict>
+						<EnumInt>0</EnumInt>
+						<PlainCh>0</PlainCh>
+						<Ropi>0</Ropi>
+						<Rwpi>0</Rwpi>
+						<wLevel>2</wLevel>
+						<uThumb>0</uThumb>
+						<uSurpInc>0</uSurpInc>
+						<uC99>1</uC99>
+						<useXO>0</useXO>
+						<VariousControls>
+							<MiscControls/>
+							<Define>CORE_CM7,USE_HAL_DRIVER,STM32H747xx</Define>
+							<Undefine/>
+							<IncludePath>../CM7/Inc;../Drivers/STM32H7xx_HAL_Driver/Inc;../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy;../Drivers/CMSIS/Device/ST/STM32H7xx/Include;../Drivers/CMSIS/Include</IncludePath>
+						</VariousControls>
+					</Cads>
+					<Aads>
+						<interw>1</interw>
+						<Ropi>0</Ropi>
+						<Rwpi>0</Rwpi>
+						<thumb>0</thumb>
+						<SplitLS>0</SplitLS>
+						<SwStkChk>0</SwStkChk>
+						<NoWarn>0</NoWarn>
+						<VariousControls>
+							<MiscControls/>
+							<Define/>
+							<Undefine/>
+							<IncludePath/>
+						</VariousControls>
+					</Aads>
+					<LDads>
+						<umfTarg>0</umfTarg>
+						<Ropi>0</Ropi>
+						<Rwpi>0</Rwpi>
+						<noStLib>0</noStLib>
+						<RepFail>1</RepFail>
+						<useFile>0</useFile>
+						<TextAddressRange>0x08000000</TextAddressRange>
+						<DataAddressRange>0x20000000</DataAddressRange>
+						<pXoBase/>
+						<ScatterFile>stm32h747xx_flash_CM7.sct</ScatterFile>
+						<IncludeLibs/>
+						<IncludeLibsPath/>
+						<Misc/>
+						<LinkerInputFile/>
+						<DisabledWarnings/>
+					</LDads>
+				</TargetArmAds>
+			</TargetOption>     
+			<Groups>
+        <Group>
+					<GroupName>Application/MDK-ARM</GroupName>
+				<Files>
+            <File>
+              <FileName>startup_stm32h747xx_CM4.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>startup_stm32h747xx_CM4.s</FilePath>
+              <FileOption>
+                <CommonProperty>
+                  <UseCPPCompiler>2</UseCPPCompiler>
+                  <RVCTCodeConst>0</RVCTCodeConst>
+                  <RVCTZI>0</RVCTZI>
+                  <RVCTOtherData>0</RVCTOtherData>
+                  <ModuleSelection>0</ModuleSelection>
+                  <IncludeInBuild>0</IncludeInBuild>
+                  <AlwaysBuild>2</AlwaysBuild>
+                  <GenerateAssemblyFile>2</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>2</AssembleAssemblyFile>
+                  <PublicsOnly>2</PublicsOnly>
+                  <StopOnExitCode>11</StopOnExitCode>
+                </CommonProperty>
+                <FileArmAds>
+                  <Cads>
+                    <interw>2</interw>
+                    <Optim>0</Optim>
+                    <oTime>2</oTime>
+                    <SplitLS>2</SplitLS>
+                    <OneElfS>2</OneElfS>
+                    <Strict>2</Strict>
+                    <EnumInt>2</EnumInt>
+                    <PlainCh>2</PlainCh>
+                    <Ropi>2</Ropi>
+                    <Rwpi>2</Rwpi>
+                    <wLevel>0</wLevel>
+                    <uThumb>2</uThumb>
+                    <uSurpInc>2</uSurpInc>
+                    <uC99>2</uC99>
+                    <useXO>2</useXO>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+            </File>
+            <File>
+              <FileName>startup_stm32h747xx_CM7.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>startup_stm32h747xx_CM7.s</FilePath>
+            </File>
+          </Files>
+        </Group>
+				
+				<Group>
+					<GroupName>::CMSIS</GroupName>
+				</Group>
+			<Group>
+          <GroupName>Application/User/CM4</GroupName>
+          <GroupOption>
+            <CommonProperty>
+              <UseCPPCompiler>0</UseCPPCompiler>
+              <RVCTCodeConst>0</RVCTCodeConst>
+              <RVCTZI>0</RVCTZI>
+              <RVCTOtherData>0</RVCTOtherData>
+              <ModuleSelection>0</ModuleSelection>
+              <IncludeInBuild>0</IncludeInBuild>
+              <AlwaysBuild>2</AlwaysBuild>
+              <GenerateAssemblyFile>2</GenerateAssemblyFile>
+              <AssembleAssemblyFile>2</AssembleAssemblyFile>
+              <PublicsOnly>2</PublicsOnly>
+              <StopOnExitCode>11</StopOnExitCode>
+            </CommonProperty>
+            <GroupArmAds>
+              <Cads>
+                <interw>2</interw>
+                <Optim>2</Optim>
+                <oTime>1</oTime>
+                <SplitLS>2</SplitLS>
+                <OneElfS>2</OneElfS>
+                <Strict>2</Strict>
+                <EnumInt>2</EnumInt>
+                <PlainCh>2</PlainCh>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <wLevel>0</wLevel>
+                <uThumb>2</uThumb>
+                <uSurpInc>2</uSurpInc>
+                <uC99>2</uC99>
+                <useXO>2</useXO>
+              </Cads>
+              <Aads>
+                <interw>2</interw>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <thumb>2</thumb>
+                <SplitLS>2</SplitLS>
+                <SwStkChk>2</SwStkChk>
+                <NoWarn>2</NoWarn>
+                <uSurpInc>2</uSurpInc>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+          <Files>
+            <File>
+              <FileName>main.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../CM4/Src/main.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_it.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../CM4/Src/stm32h7xx_it.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_msp.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../CM4/Src/stm32h7xx_hal_msp.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Application/User/CM7</GroupName>
+          <Files>
+            <File>
+              <FileName>main.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../CM7/Src/main.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_it.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../CM7/Src/stm32h7xx_it.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_msp.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../CM7/Src/stm32h7xx_hal_msp.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Drivers/STM32H7xx_HAL_Driver</GroupName>
+          <Files>
+            <File>
+              <FileName>stm32h7xx_hal_cortex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_tim.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_tim_ex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_uart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_uart_ex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_rcc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_rcc_ex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_flash.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_flash_ex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_gpio.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_hsem.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_dma.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_dma_ex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_mdma.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_pwr.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_pwr_ex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_i2c.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_i2c_ex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_exti.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Drivers/CMSIS</GroupName>
+          <Files>
+            <File>
+              <FileName>system_stm32h7xx_dualcore_boot_cm4_cm7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../Common/Src/system_stm32h7xx_dualcore_boot_cm4_cm7.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+      </Groups>
+
+		</Target>
+  </Targets>
+	<RTE>
+		<apis/>
+		<components>
+			<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="4.3.0" condition="CMSIS Core">
+				<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="4.5.0"/>
+				<targetInfos>
+					<targetInfo name="CubeMX_Config_CM4"/>
+				<targetInfo name="CubeMX_Config_CM7"/>
+        </targetInfos>
+			</component>
+		</components>
+		<files/>
+	</RTE>
+</Project>
diff --git a/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/MDK-ARM/startup_stm32h747xx_CM4.s b/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/MDK-ARM/startup_stm32h747xx_CM4.s
new file mode 100644
index 0000000000..16330097a4
--- /dev/null
+++ b/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/MDK-ARM/startup_stm32h747xx_CM4.s
@@ -0,0 +1,623 @@
+;******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
+;* File Name          : startup_stm32h747xx.s
+;* @author  MCD Application Team
+;* Description        : STM32H7xx devices vector table for MDK-ARM toolchain. 
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp                      ; Top of Stack
+                DCD     Reset_Handler                     ; Reset Handler
+                DCD     NMI_Handler                       ; NMI Handler
+                DCD     HardFault_Handler                 ; Hard Fault Handler
+                DCD     MemManage_Handler                 ; MPU Fault Handler
+                DCD     BusFault_Handler                  ; Bus Fault Handler
+                DCD     UsageFault_Handler                ; Usage Fault Handler
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     SVC_Handler                       ; SVCall Handler
+                DCD     DebugMon_Handler                  ; Debug Monitor Handler
+                DCD     0                                 ; Reserved
+                DCD     PendSV_Handler                    ; PendSV Handler
+                DCD     SysTick_Handler                   ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog interrupt ( wwdg1_it, wwdg2_it)                                         
+                DCD     PVD_AVD_IRQHandler                ; PVD/AVD through EXTI Line detection                        
+                DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line            
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line                       
+                DCD     FLASH_IRQHandler                  ; FLASH                                           
+                DCD     RCC_IRQHandler                    ; RCC                                             
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0                                             
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1                                             
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2                                             
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3                                             
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4 
+                DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0
+                DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1                                   
+                DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2                                   
+                DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3                                   
+                DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4                                   
+                DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5                                   
+                DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6  
+                DCD     ADC_IRQHandler                    ; ADC1, ADC2                             
+                DCD     FDCAN1_IT0_IRQHandler             ; FDCAN1 interrupt line 0                        
+                DCD     FDCAN2_IT0_IRQHandler             ; FDCAN2 interrupt line 0                               
+                DCD     FDCAN1_IT1_IRQHandler             ; FDCAN1 interrupt line 1                        
+                DCD     FDCAN2_IT1_IRQHandler             ; FDCAN2 interrupt line 1                                               
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s                                    
+                DCD     TIM1_BRK_IRQHandler               ; TIM1 Break interrupt                   
+                DCD     TIM1_UP_IRQHandler                ; TIM1 Update Interrupt                 
+                DCD     TIM1_TRG_COM_IRQHandler           ; TIM1 Trigger and Commutation Interrupt 
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare                                   
+                DCD     TIM2_IRQHandler                   ; TIM2                                            
+                DCD     TIM3_IRQHandler                   ; TIM3                                            
+                DCD     TIM4_IRQHandler                   ; TIM4                                            
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event                                             
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error                                             
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event                                             
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error                                               
+                DCD     SPI1_IRQHandler                   ; SPI1                                            
+                DCD     SPI2_IRQHandler                   ; SPI2                                            
+                DCD     USART1_IRQHandler                 ; USART1                                          
+                DCD     USART2_IRQHandler                 ; USART2                                          
+                DCD     USART3_IRQHandler                 ; USART3                                          
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]  
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+                DCD     0                                 ; Reserved                                          
+                DCD     TIM8_BRK_TIM12_IRQHandler         ; TIM8 Break Interrupt and TIM12 global interrupt                 
+                DCD     TIM8_UP_TIM13_IRQHandler          ; TIM8 Update Interrupt and TIM13 global interrupt
+                DCD     TIM8_TRG_COM_TIM14_IRQHandler     ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
+                DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare Interrupt
+                DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7                                           
+                DCD     FMC_IRQHandler                    ; FMC                             
+                DCD     SDMMC1_IRQHandler                 ; SDMMC1                            
+                DCD     TIM5_IRQHandler                   ; TIM5                            
+                DCD     SPI3_IRQHandler                   ; SPI3                            
+                DCD     UART4_IRQHandler                  ; UART4                           
+                DCD     UART5_IRQHandler                  ; UART5                           
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors           
+                DCD     TIM7_IRQHandler                   ; TIM7           
+                DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0                   
+                DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1                   
+                DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2                   
+                DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3                   
+                DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4                   
+                DCD     ETH_IRQHandler                    ; Ethernet                        
+                DCD     ETH_WKUP_IRQHandler               ; Ethernet Wakeup through EXTI line              
+                DCD     FDCAN_CAL_IRQHandler              ; FDCAN calibration unit interrupt                        
+                DCD     CM7_SEV_IRQHandler                ; CM7 Send event interrupt for CM4                              
+                DCD     CM4_SEV_IRQHandler                ; CM4 Send event interrupt for CM7 
+                DCD     0                                 ; Reserved 
+                DCD     0                                 ; Reserved                      
+                DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5                   
+                DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6                   
+                DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7                   
+                DCD     USART6_IRQHandler                 ; USART6                           
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event                             
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error                             
+                DCD     OTG_HS_EP1_OUT_IRQHandler         ; USB OTG HS End Point 1 Out                      
+                DCD     OTG_HS_EP1_IN_IRQHandler          ; USB OTG HS End Point 1 In                       
+                DCD     OTG_HS_WKUP_IRQHandler            ; USB OTG HS Wakeup through EXTI                         
+                DCD     OTG_HS_IRQHandler                 ; USB OTG HS                    
+                DCD     DCMI_IRQHandler                   ; DCMI                            
+                DCD     0                                 ; Reserved                                     
+                DCD     RNG_IRQHandler                    ; Rng
+                DCD     FPU_IRQHandler                    ; FPU
+                DCD     UART7_IRQHandler                  ; UART7
+                DCD     UART8_IRQHandler                  ; UART8
+                DCD     SPI4_IRQHandler                   ; SPI4
+                DCD     SPI5_IRQHandler                   ; SPI5
+                DCD     SPI6_IRQHandler                   ; SPI6
+                DCD     SAI1_IRQHandler                   ; SAI1
+                DCD     LTDC_IRQHandler                   ; LTDC
+                DCD     LTDC_ER_IRQHandler                ; LTDC error
+                DCD     DMA2D_IRQHandler                  ; DMA2D
+                DCD     SAI2_IRQHandler                   ; SAI2
+                DCD     QUADSPI_IRQHandler                ; QUADSPI
+                DCD     LPTIM1_IRQHandler                 ; LPTIM1
+                DCD     CEC_IRQHandler                    ; HDMI_CEC
+                DCD     I2C4_EV_IRQHandler                ; I2C4 Event                             
+                DCD     I2C4_ER_IRQHandler                ; I2C4 Error 
+                DCD     SPDIF_RX_IRQHandler               ; SPDIF_RX
+                DCD     OTG_FS_EP1_OUT_IRQHandler         ; USB OTG FS End Point 1 Out                      
+                DCD     OTG_FS_EP1_IN_IRQHandler          ; USB OTG FS End Point 1 In                       
+                DCD     OTG_FS_WKUP_IRQHandler            ; USB OTG FS Wakeup through EXTI                         
+                DCD     OTG_FS_IRQHandler                 ; USB OTG FS                 
+                DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX1 Overrun interrupt  
+                DCD     HRTIM1_Master_IRQHandler          ;  HRTIM Master Timer global Interrupts                              
+                DCD     HRTIM1_TIMA_IRQHandler            ;  HRTIM Timer A global Interrupt                                    
+                DCD     HRTIM1_TIMB_IRQHandler            ;  HRTIM Timer B global Interrupt                                    
+                DCD     HRTIM1_TIMC_IRQHandler            ;  HRTIM Timer C global Interrupt                                    
+                DCD     HRTIM1_TIMD_IRQHandler            ;  HRTIM Timer D global Interrupt                                    
+                DCD     HRTIM1_TIME_IRQHandler            ;  HRTIM Timer E global Interrupt                                    
+                DCD     HRTIM1_FLT_IRQHandler             ;  HRTIM Fault global Interrupt 
+                DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM Filter0 Interrupt   
+                DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM Filter1 Interrupt                                            
+                DCD     DFSDM1_FLT2_IRQHandler            ; DFSDM Filter2 Interrupt                                            
+                DCD     DFSDM1_FLT3_IRQHandler            ; DFSDM Filter3 Interrupt                                                                                    
+                DCD     SAI3_IRQHandler                   ;  SAI3 global Interrupt                                             
+                DCD     SWPMI1_IRQHandler                 ;  Serial Wire Interface 1 global interrupt                          
+                DCD     TIM15_IRQHandler                  ;  TIM15 global Interrupt                                            
+                DCD     TIM16_IRQHandler                  ;  TIM16 global Interrupt                                            
+                DCD     TIM17_IRQHandler                  ;  TIM17 global Interrupt                                            
+                DCD     MDIOS_WKUP_IRQHandler             ;  MDIOS Wakeup  Interrupt                                           
+                DCD     MDIOS_IRQHandler                  ;  MDIOS global Interrupt                                            
+                DCD     JPEG_IRQHandler                   ;  JPEG global Interrupt                                             
+                DCD     MDMA_IRQHandler                   ;  MDMA global Interrupt                                             
+                DCD     DSI_IRQHandler                    ;  DSI global Interrupt                                              
+                DCD     SDMMC2_IRQHandler                 ;  SDMMC2 global Interrupt                                           
+                DCD     HSEM1_IRQHandler                  ;  HSEM1 global Interrupt                                             
+                DCD     HSEM2_IRQHandler                  ;  HSEM2 global Interrupt                                             
+                DCD     ADC3_IRQHandler                   ;  ADC3 global Interrupt                                              
+                DCD     DMAMUX2_OVR_IRQHandler            ; DMAMUX Overrun interrupt                                           
+                DCD     BDMA_Channel0_IRQHandler          ;  BDMA Channel 0 global Interrupt                                    
+                DCD     BDMA_Channel1_IRQHandler          ;  BDMA Channel 1 global Interrupt                                    
+                DCD     BDMA_Channel2_IRQHandler          ;  BDMA Channel 2 global Interrupt                                    
+                DCD     BDMA_Channel3_IRQHandler          ;  BDMA Channel 3 global Interrupt                                    
+                DCD     BDMA_Channel4_IRQHandler          ;  BDMA Channel 4 global Interrupt                                    
+                DCD     BDMA_Channel5_IRQHandler          ;  BDMA Channel 5 global Interrupt                                    
+                DCD     BDMA_Channel6_IRQHandler          ;  BDMA Channel 6 global Interrupt                                    
+                DCD     BDMA_Channel7_IRQHandler          ;  BDMA Channel 7 global Interrupt                                    
+                DCD     COMP1_IRQHandler                  ;  COMP1 global Interrupt                                            
+                DCD     LPTIM2_IRQHandler                 ;  LP TIM2 global interrupt                                          
+                DCD     LPTIM3_IRQHandler                 ;  LP TIM3 global interrupt                                          
+                DCD     LPTIM4_IRQHandler                 ;  LP TIM4 global interrupt                                          
+                DCD     LPTIM5_IRQHandler                 ;  LP TIM5 global interrupt                                          
+                DCD     LPUART1_IRQHandler                ;  LP UART1 interrupt                                                
+                DCD     WWDG_RST_IRQHandler               ; Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it)                                
+                DCD     CRS_IRQHandler                    ;  Clock Recovery Global Interrupt                                   
+                DCD     ECC_IRQHandler                    ; ECC diagnostic Global Interrupt                                              
+                DCD     SAI4_IRQHandler                   ;  SAI4 global interrupt                                                
+                DCD     0                                 ; Reserved                                
+                DCD     HOLD_CORE_IRQHandler              ;  Hold core interrupt                                   
+                DCD     WAKEUP_PIN_IRQHandler             ;  Interrupt for all 6 wake-up pins 
+                
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                    [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                      [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler                [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler                [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler                 [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler               [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                      [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler                  [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                    [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                   [WEAK]
+                B       .
+                ENDP                                     
+                                                          
+Default_Handler PROC                                      
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]                                       
+                EXPORT  PVD_AVD_IRQHandler                [WEAK]                         
+                EXPORT  TAMP_STAMP_IRQHandler             [WEAK]   
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]             
+                EXPORT  FLASH_IRQHandler                  [WEAK]                                        
+                EXPORT  RCC_IRQHandler                    [WEAK]                                          
+                EXPORT  EXTI0_IRQHandler                  [WEAK]                                            
+                EXPORT  EXTI1_IRQHandler                  [WEAK]                                           
+                EXPORT  EXTI2_IRQHandler                  [WEAK]                                            
+                EXPORT  EXTI3_IRQHandler                  [WEAK]                                            
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Stream0_IRQHandler           [WEAK] 
+                EXPORT  DMA1_Stream1_IRQHandler           [WEAK]                        
+                EXPORT  DMA1_Stream2_IRQHandler           [WEAK]                     
+                EXPORT  DMA1_Stream3_IRQHandler           [WEAK]                    
+                EXPORT  DMA1_Stream4_IRQHandler           [WEAK]                        
+                EXPORT  DMA1_Stream5_IRQHandler           [WEAK]                          
+                EXPORT  DMA1_Stream6_IRQHandler           [WEAK]
+                EXPORT  DMA1_Stream7_IRQHandler           [WEAK]
+                EXPORT  ADC_IRQHandler                    [WEAK]                          
+                EXPORT  FDCAN1_IT0_IRQHandler             [WEAK]                                            
+                EXPORT  FDCAN2_IT0_IRQHandler             [WEAK] 
+                EXPORT  FDCAN1_IT1_IRQHandler             [WEAK]                                            
+                EXPORT  FDCAN2_IT1_IRQHandler             [WEAK]   
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]                                    
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]                  
+                EXPORT  TIM1_UP_IRQHandler                [WEAK]                
+                EXPORT  TIM1_TRG_COM_IRQHandler           [WEAK] 
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]                                   
+                EXPORT  TIM2_IRQHandler                   [WEAK]                                            
+                EXPORT  TIM3_IRQHandler                   [WEAK]                                            
+                EXPORT  TIM4_IRQHandler                   [WEAK]                                            
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]                                             
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]                                             
+                EXPORT  I2C2_EV_IRQHandler                [WEAK]                                            
+                EXPORT  I2C2_ER_IRQHandler                [WEAK]                                               
+                EXPORT  SPI1_IRQHandler                   [WEAK]                                           
+                EXPORT  SPI2_IRQHandler                   [WEAK]                                            
+                EXPORT  USART1_IRQHandler                 [WEAK]                                          
+                EXPORT  USART2_IRQHandler                 [WEAK]                                          
+                EXPORT  USART3_IRQHandler                 [WEAK]                                         
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]                                  
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]                                       
+                EXPORT  TIM8_BRK_TIM12_IRQHandler         [WEAK]                 
+                EXPORT  TIM8_UP_TIM13_IRQHandler          [WEAK]                 
+                EXPORT  TIM8_TRG_COM_TIM14_IRQHandler     [WEAK] 
+                EXPORT  TIM8_CC_IRQHandler                [WEAK]                                   
+                EXPORT  DMA1_Stream7_IRQHandler           [WEAK]                                          
+                EXPORT  FMC_IRQHandler                    [WEAK]                                             
+                EXPORT  SDMMC1_IRQHandler                 [WEAK]                                             
+                EXPORT  TIM5_IRQHandler                   [WEAK]                                             
+                EXPORT  SPI3_IRQHandler                   [WEAK]                                             
+                EXPORT  UART4_IRQHandler                  [WEAK]                                            
+                EXPORT  UART5_IRQHandler                  [WEAK]                                            
+                EXPORT  TIM6_DAC_IRQHandler               [WEAK]                   
+                EXPORT  TIM7_IRQHandler                   [WEAK]                    
+                EXPORT  DMA2_Stream0_IRQHandler           [WEAK]                                  
+                EXPORT  DMA2_Stream1_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream2_IRQHandler           [WEAK]                                    
+                EXPORT  DMA2_Stream3_IRQHandler           [WEAK]                                    
+                EXPORT  DMA2_Stream4_IRQHandler           [WEAK]                                 
+                EXPORT  ETH_IRQHandler                    [WEAK]                                         
+                EXPORT  ETH_WKUP_IRQHandler               [WEAK]                     
+                EXPORT  FDCAN_CAL_IRQHandler              [WEAK]                                                                                                                                                                              
+                EXPORT  CM7_SEV_IRQHandler                [WEAK]                                                                                                                                                                              
+                EXPORT  CM4_SEV_IRQHandler                [WEAK]                                                                                                                                                                              
+                EXPORT  DMA2_Stream5_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream6_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream7_IRQHandler           [WEAK]                                   
+                EXPORT  USART6_IRQHandler                 [WEAK]                                           
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]                                              
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]                                              
+                EXPORT  OTG_HS_EP1_OUT_IRQHandler         [WEAK]                      
+                EXPORT  OTG_HS_EP1_IN_IRQHandler          [WEAK]                      
+                EXPORT  OTG_HS_WKUP_IRQHandler            [WEAK]                        
+                EXPORT  OTG_HS_IRQHandler                 [WEAK]                                      
+                EXPORT  DCMI_IRQHandler                   [WEAK]                                             
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  UART7_IRQHandler                  [WEAK]
+                EXPORT  UART8_IRQHandler                  [WEAK]
+                EXPORT  SPI4_IRQHandler                   [WEAK]
+                EXPORT  SPI5_IRQHandler                   [WEAK]
+                EXPORT  SPI6_IRQHandler                   [WEAK]
+                EXPORT  SAI1_IRQHandler                   [WEAK]
+                EXPORT  LTDC_IRQHandler                   [WEAK]
+                EXPORT  LTDC_ER_IRQHandler                [WEAK]
+                EXPORT  DMA2D_IRQHandler                  [WEAK]
+                EXPORT  SAI2_IRQHandler                   [WEAK]   
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  CEC_IRQHandler                    [WEAK]   
+                EXPORT  I2C4_EV_IRQHandler                [WEAK]
+                EXPORT  I2C4_ER_IRQHandler                [WEAK] 
+                EXPORT  SPDIF_RX_IRQHandler               [WEAK]
+                EXPORT  OTG_FS_EP1_OUT_IRQHandler         [WEAK]
+                EXPORT  OTG_FS_EP1_IN_IRQHandler          [WEAK]                      
+                EXPORT  OTG_FS_WKUP_IRQHandler            [WEAK]                      
+                EXPORT  OTG_FS_IRQHandler                 [WEAK]                        
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+                EXPORT  HRTIM1_Master_IRQHandler          [WEAK] 
+                EXPORT  HRTIM1_TIMA_IRQHandler            [WEAK]                                      
+                EXPORT  HRTIM1_TIMB_IRQHandler            [WEAK]                                      
+                EXPORT  HRTIM1_TIMC_IRQHandler            [WEAK]                                      
+                EXPORT  HRTIM1_TIMD_IRQHandler            [WEAK]                                      
+                EXPORT  HRTIM1_TIME_IRQHandler            [WEAK]                                      
+                EXPORT  HRTIM1_FLT_IRQHandler             [WEAK]
+                EXPORT  DFSDM1_FLT0_IRQHandler            [WEAK] 
+                EXPORT  DFSDM1_FLT1_IRQHandler            [WEAK]                                             
+                EXPORT  DFSDM1_FLT2_IRQHandler            [WEAK]                                             
+                EXPORT  DFSDM1_FLT3_IRQHandler            [WEAK]                                                                                        
+                EXPORT  SAI3_IRQHandler                   [WEAK]                                             
+                EXPORT  SWPMI1_IRQHandler                 [WEAK]                            
+                EXPORT  TIM15_IRQHandler                  [WEAK]                                             
+                EXPORT  TIM16_IRQHandler                  [WEAK]                                              
+                EXPORT  TIM17_IRQHandler                  [WEAK]                                            
+                EXPORT  MDIOS_WKUP_IRQHandler             [WEAK]                                             
+                EXPORT  MDIOS_IRQHandler                  [WEAK]                                              
+                EXPORT  JPEG_IRQHandler                   [WEAK]                                               
+                EXPORT  MDMA_IRQHandler                   [WEAK]                                               
+                EXPORT  DSI_IRQHandler                    [WEAK]                                               
+                EXPORT  SDMMC2_IRQHandler                 [WEAK]                                             
+                EXPORT  HSEM1_IRQHandler                  [WEAK]                                               
+                EXPORT  HSEM2_IRQHandler                  [WEAK]                                               
+                EXPORT  ADC3_IRQHandler                   [WEAK]                                                
+                EXPORT  DMAMUX2_OVR_IRQHandler            [WEAK]                                            
+                EXPORT  BDMA_Channel0_IRQHandler          [WEAK]                                      
+                EXPORT  BDMA_Channel1_IRQHandler          [WEAK]                                      
+                EXPORT  BDMA_Channel2_IRQHandler          [WEAK]                                      
+                EXPORT  BDMA_Channel3_IRQHandler          [WEAK]                                      
+                EXPORT  BDMA_Channel4_IRQHandler          [WEAK]                                     
+                EXPORT  BDMA_Channel5_IRQHandler          [WEAK]                                      
+                EXPORT  BDMA_Channel6_IRQHandler          [WEAK]                                      
+                EXPORT  BDMA_Channel7_IRQHandler          [WEAK]                                     
+                EXPORT  COMP1_IRQHandler                  [WEAK]                                              
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]                                           
+                EXPORT  LPTIM3_IRQHandler                 [WEAK]                                            
+                EXPORT  LPTIM4_IRQHandler                 [WEAK]                                            
+                EXPORT  LPTIM5_IRQHandler                 [WEAK]                                            
+                EXPORT  LPUART1_IRQHandler                [WEAK]                                                  
+                EXPORT  WWDG_RST_IRQHandler               [WEAK]                                
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  ECC_IRQHandler                    [WEAK]				
+                EXPORT  SAI4_IRQHandler                   [WEAK]                                                  
+                EXPORT  HOLD_CORE_IRQHandler              [WEAK]                                   
+                EXPORT  WAKEUP_PIN_IRQHandler             [WEAK] 
+
+
+WWDG_IRQHandler                                                          
+PVD_AVD_IRQHandler                                             
+TAMP_STAMP_IRQHandler                
+RTC_WKUP_IRQHandler                            
+FLASH_IRQHandler                                                          
+RCC_IRQHandler                                                              
+EXTI0_IRQHandler                                                              
+EXTI1_IRQHandler                                                             
+EXTI2_IRQHandler                                                              
+EXTI3_IRQHandler                                                              
+EXTI4_IRQHandler 
+DMA1_Stream0_IRQHandler
+DMA1_Stream1_IRQHandler                                  
+DMA1_Stream2_IRQHandler                               
+DMA1_Stream3_IRQHandler                              
+DMA1_Stream4_IRQHandler                                  
+DMA1_Stream5_IRQHandler                                    
+DMA1_Stream6_IRQHandler                   
+ADC_IRQHandler                                           
+FDCAN1_IT0_IRQHandler
+FDCAN2_IT0_IRQHandler
+FDCAN1_IT1_IRQHandler
+FDCAN2_IT1_IRQHandler
+EXTI9_5_IRQHandler                                                
+TIM1_BRK_IRQHandler                        
+TIM1_UP_IRQHandler                      
+TIM1_TRG_COM_IRQHandler  
+TIM1_CC_IRQHandler                                               
+TIM2_IRQHandler                                                           
+TIM3_IRQHandler                                                           
+TIM4_IRQHandler                                                           
+I2C1_EV_IRQHandler                                                         
+I2C1_ER_IRQHandler                                                         
+I2C2_EV_IRQHandler                                                        
+I2C2_ER_IRQHandler                                                           
+SPI1_IRQHandler                                                          
+SPI2_IRQHandler                                                           
+USART1_IRQHandler                                                       
+USART2_IRQHandler                                                       
+USART3_IRQHandler                                                      
+EXTI15_10_IRQHandler                                            
+RTC_Alarm_IRQHandler                                                           
+TIM8_BRK_TIM12_IRQHandler                      
+TIM8_UP_TIM13_IRQHandler                       
+TIM8_TRG_COM_TIM14_IRQHandler  
+TIM8_CC_IRQHandler                                               
+DMA1_Stream7_IRQHandler                                                 
+FMC_IRQHandler                                                            
+SDMMC1_IRQHandler                                                            
+TIM5_IRQHandler                                                            
+SPI3_IRQHandler                                                            
+UART4_IRQHandler                                                          
+UART5_IRQHandler                                                          
+TIM6_DAC_IRQHandler                            
+TIM7_IRQHandler                              
+DMA2_Stream0_IRQHandler                                         
+DMA2_Stream1_IRQHandler                                          
+DMA2_Stream2_IRQHandler                                           
+DMA2_Stream3_IRQHandler                                           
+DMA2_Stream4_IRQHandler                                        
+ETH_IRQHandler                                                         
+ETH_WKUP_IRQHandler                                
+FDCAN_CAL_IRQHandler
+CM7_SEV_IRQHandler
+CM4_SEV_IRQHandler                                                                                                                                                                                                                             
+DMA2_Stream5_IRQHandler                                          
+DMA2_Stream6_IRQHandler                                          
+DMA2_Stream7_IRQHandler                                          
+USART6_IRQHandler                                                        
+I2C3_EV_IRQHandler                                                          
+I2C3_ER_IRQHandler                                                          
+OTG_HS_EP1_OUT_IRQHandler 
+OTG_HS_EP1_IN_IRQHandler 
+OTG_HS_WKUP_IRQHandler   
+OTG_HS_IRQHandler        
+DCMI_IRQHandler                                                            
+RNG_IRQHandler
+FPU_IRQHandler  
+UART7_IRQHandler                  
+UART8_IRQHandler                  
+SPI4_IRQHandler                   
+SPI5_IRQHandler                   
+SPI6_IRQHandler                   
+SAI1_IRQHandler                   
+LTDC_IRQHandler                   
+LTDC_ER_IRQHandler                 
+DMA2D_IRQHandler   
+SAI2_IRQHandler        
+QUADSPI_IRQHandler
+LPTIM1_IRQHandler
+CEC_IRQHandler
+I2C4_EV_IRQHandler
+I2C4_ER_IRQHandler
+SPDIF_RX_IRQHandler
+OTG_FS_EP1_OUT_IRQHandler
+OTG_FS_EP1_IN_IRQHandler 
+OTG_FS_WKUP_IRQHandler   
+OTG_FS_IRQHandler        
+DMAMUX1_OVR_IRQHandler
+HRTIM1_Master_IRQHandler               
+HRTIM1_TIMA_IRQHandler                                                      
+HRTIM1_TIMB_IRQHandler                                                      
+HRTIM1_TIMC_IRQHandler                                                      
+HRTIM1_TIMD_IRQHandler                                                      
+HRTIM1_TIME_IRQHandler                                                      
+HRTIM1_FLT_IRQHandler 
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler                                                                
+DFSDM1_FLT2_IRQHandler                                                                
+DFSDM1_FLT3_IRQHandler                                                                                                                                
+SAI3_IRQHandler                                                                    
+SWPMI1_IRQHandler                                                 
+TIM15_IRQHandler                                                                   
+TIM16_IRQHandler                                                                    
+TIM17_IRQHandler                                                                  
+MDIOS_WKUP_IRQHandler                                                              
+MDIOS_IRQHandler                                                                    
+JPEG_IRQHandler                                                                      
+MDMA_IRQHandler                                                                      
+DSI_IRQHandler                                                                       
+SDMMC2_IRQHandler                                                                  
+HSEM1_IRQHandler                                                                     
+HSEM2_IRQHandler                                                                     
+ADC3_IRQHandler                                                                       
+DMAMUX2_OVR_IRQHandler                                                            
+BDMA_Channel0_IRQHandler                                                     
+BDMA_Channel1_IRQHandler                                                     
+BDMA_Channel2_IRQHandler                                                     
+BDMA_Channel3_IRQHandler                                                     
+BDMA_Channel4_IRQHandler                                                    
+BDMA_Channel5_IRQHandler                                                     
+BDMA_Channel6_IRQHandler                                                     
+BDMA_Channel7_IRQHandler                                                    
+COMP1_IRQHandler                                                                    
+LPTIM2_IRQHandler                                                                
+LPTIM3_IRQHandler                                                                 
+LPTIM4_IRQHandler                                                                 
+LPTIM5_IRQHandler                                                                 
+LPUART1_IRQHandler                                                                      
+WWDG_RST_IRQHandler                                                   
+CRS_IRQHandler
+ECC_IRQHandler                                                           
+SAI4_IRQHandler      
+HOLD_CORE_IRQHandler 
+WAKEUP_PIN_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+                
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+                
+                 ELSE
+                
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+                 
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/MDK-ARM/startup_stm32h747xx_CM7.s b/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/MDK-ARM/startup_stm32h747xx_CM7.s
new file mode 100644
index 0000000000..16330097a4
--- /dev/null
+++ b/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/MDK-ARM/startup_stm32h747xx_CM7.s
@@ -0,0 +1,623 @@
+;******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
+;* File Name          : startup_stm32h747xx.s
+;* @author  MCD Application Team
+;* Description        : STM32H7xx devices vector table for MDK-ARM toolchain. 
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp                      ; Top of Stack
+                DCD     Reset_Handler                     ; Reset Handler
+                DCD     NMI_Handler                       ; NMI Handler
+                DCD     HardFault_Handler                 ; Hard Fault Handler
+                DCD     MemManage_Handler                 ; MPU Fault Handler
+                DCD     BusFault_Handler                  ; Bus Fault Handler
+                DCD     UsageFault_Handler                ; Usage Fault Handler
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     SVC_Handler                       ; SVCall Handler
+                DCD     DebugMon_Handler                  ; Debug Monitor Handler
+                DCD     0                                 ; Reserved
+                DCD     PendSV_Handler                    ; PendSV Handler
+                DCD     SysTick_Handler                   ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog interrupt ( wwdg1_it, wwdg2_it)                                         
+                DCD     PVD_AVD_IRQHandler                ; PVD/AVD through EXTI Line detection                        
+                DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line            
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line                       
+                DCD     FLASH_IRQHandler                  ; FLASH                                           
+                DCD     RCC_IRQHandler                    ; RCC                                             
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0                                             
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1                                             
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2                                             
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3                                             
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4 
+                DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0
+                DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1                                   
+                DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2                                   
+                DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3                                   
+                DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4                                   
+                DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5                                   
+                DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6  
+                DCD     ADC_IRQHandler                    ; ADC1, ADC2                             
+                DCD     FDCAN1_IT0_IRQHandler             ; FDCAN1 interrupt line 0                        
+                DCD     FDCAN2_IT0_IRQHandler             ; FDCAN2 interrupt line 0                               
+                DCD     FDCAN1_IT1_IRQHandler             ; FDCAN1 interrupt line 1                        
+                DCD     FDCAN2_IT1_IRQHandler             ; FDCAN2 interrupt line 1                                               
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s                                    
+                DCD     TIM1_BRK_IRQHandler               ; TIM1 Break interrupt                   
+                DCD     TIM1_UP_IRQHandler                ; TIM1 Update Interrupt                 
+                DCD     TIM1_TRG_COM_IRQHandler           ; TIM1 Trigger and Commutation Interrupt 
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare                                   
+                DCD     TIM2_IRQHandler                   ; TIM2                                            
+                DCD     TIM3_IRQHandler                   ; TIM3                                            
+                DCD     TIM4_IRQHandler                   ; TIM4                                            
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event                                             
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error                                             
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event                                             
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error                                               
+                DCD     SPI1_IRQHandler                   ; SPI1                                            
+                DCD     SPI2_IRQHandler                   ; SPI2                                            
+                DCD     USART1_IRQHandler                 ; USART1                                          
+                DCD     USART2_IRQHandler                 ; USART2                                          
+                DCD     USART3_IRQHandler                 ; USART3                                          
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]  
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+                DCD     0                                 ; Reserved                                          
+                DCD     TIM8_BRK_TIM12_IRQHandler         ; TIM8 Break Interrupt and TIM12 global interrupt                 
+                DCD     TIM8_UP_TIM13_IRQHandler          ; TIM8 Update Interrupt and TIM13 global interrupt
+                DCD     TIM8_TRG_COM_TIM14_IRQHandler     ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
+                DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare Interrupt
+                DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7                                           
+                DCD     FMC_IRQHandler                    ; FMC                             
+                DCD     SDMMC1_IRQHandler                 ; SDMMC1                            
+                DCD     TIM5_IRQHandler                   ; TIM5                            
+                DCD     SPI3_IRQHandler                   ; SPI3                            
+                DCD     UART4_IRQHandler                  ; UART4                           
+                DCD     UART5_IRQHandler                  ; UART5                           
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors           
+                DCD     TIM7_IRQHandler                   ; TIM7           
+                DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0                   
+                DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1                   
+                DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2                   
+                DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3                   
+                DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4                   
+                DCD     ETH_IRQHandler                    ; Ethernet                        
+                DCD     ETH_WKUP_IRQHandler               ; Ethernet Wakeup through EXTI line              
+                DCD     FDCAN_CAL_IRQHandler              ; FDCAN calibration unit interrupt                        
+                DCD     CM7_SEV_IRQHandler                ; CM7 Send event interrupt for CM4                              
+                DCD     CM4_SEV_IRQHandler                ; CM4 Send event interrupt for CM7 
+                DCD     0                                 ; Reserved 
+                DCD     0                                 ; Reserved                      
+                DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5                   
+                DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6                   
+                DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7                   
+                DCD     USART6_IRQHandler                 ; USART6                           
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event                             
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error                             
+                DCD     OTG_HS_EP1_OUT_IRQHandler         ; USB OTG HS End Point 1 Out                      
+                DCD     OTG_HS_EP1_IN_IRQHandler          ; USB OTG HS End Point 1 In                       
+                DCD     OTG_HS_WKUP_IRQHandler            ; USB OTG HS Wakeup through EXTI                         
+                DCD     OTG_HS_IRQHandler                 ; USB OTG HS                    
+                DCD     DCMI_IRQHandler                   ; DCMI                            
+                DCD     0                                 ; Reserved                                     
+                DCD     RNG_IRQHandler                    ; Rng
+                DCD     FPU_IRQHandler                    ; FPU
+                DCD     UART7_IRQHandler                  ; UART7
+                DCD     UART8_IRQHandler                  ; UART8
+                DCD     SPI4_IRQHandler                   ; SPI4
+                DCD     SPI5_IRQHandler                   ; SPI5
+                DCD     SPI6_IRQHandler                   ; SPI6
+                DCD     SAI1_IRQHandler                   ; SAI1
+                DCD     LTDC_IRQHandler                   ; LTDC
+                DCD     LTDC_ER_IRQHandler                ; LTDC error
+                DCD     DMA2D_IRQHandler                  ; DMA2D
+                DCD     SAI2_IRQHandler                   ; SAI2
+                DCD     QUADSPI_IRQHandler                ; QUADSPI
+                DCD     LPTIM1_IRQHandler                 ; LPTIM1
+                DCD     CEC_IRQHandler                    ; HDMI_CEC
+                DCD     I2C4_EV_IRQHandler                ; I2C4 Event                             
+                DCD     I2C4_ER_IRQHandler                ; I2C4 Error 
+                DCD     SPDIF_RX_IRQHandler               ; SPDIF_RX
+                DCD     OTG_FS_EP1_OUT_IRQHandler         ; USB OTG FS End Point 1 Out                      
+                DCD     OTG_FS_EP1_IN_IRQHandler          ; USB OTG FS End Point 1 In                       
+                DCD     OTG_FS_WKUP_IRQHandler            ; USB OTG FS Wakeup through EXTI                         
+                DCD     OTG_FS_IRQHandler                 ; USB OTG FS                 
+                DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX1 Overrun interrupt  
+                DCD     HRTIM1_Master_IRQHandler          ;  HRTIM Master Timer global Interrupts                              
+                DCD     HRTIM1_TIMA_IRQHandler            ;  HRTIM Timer A global Interrupt                                    
+                DCD     HRTIM1_TIMB_IRQHandler            ;  HRTIM Timer B global Interrupt                                    
+                DCD     HRTIM1_TIMC_IRQHandler            ;  HRTIM Timer C global Interrupt                                    
+                DCD     HRTIM1_TIMD_IRQHandler            ;  HRTIM Timer D global Interrupt                                    
+                DCD     HRTIM1_TIME_IRQHandler            ;  HRTIM Timer E global Interrupt                                    
+                DCD     HRTIM1_FLT_IRQHandler             ;  HRTIM Fault global Interrupt 
+                DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM Filter0 Interrupt   
+                DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM Filter1 Interrupt                                            
+                DCD     DFSDM1_FLT2_IRQHandler            ; DFSDM Filter2 Interrupt                                            
+                DCD     DFSDM1_FLT3_IRQHandler            ; DFSDM Filter3 Interrupt                                                                                    
+                DCD     SAI3_IRQHandler                   ;  SAI3 global Interrupt                                             
+                DCD     SWPMI1_IRQHandler                 ;  Serial Wire Interface 1 global interrupt                          
+                DCD     TIM15_IRQHandler                  ;  TIM15 global Interrupt                                            
+                DCD     TIM16_IRQHandler                  ;  TIM16 global Interrupt                                            
+                DCD     TIM17_IRQHandler                  ;  TIM17 global Interrupt                                            
+                DCD     MDIOS_WKUP_IRQHandler             ;  MDIOS Wakeup  Interrupt                                           
+                DCD     MDIOS_IRQHandler                  ;  MDIOS global Interrupt                                            
+                DCD     JPEG_IRQHandler                   ;  JPEG global Interrupt                                             
+                DCD     MDMA_IRQHandler                   ;  MDMA global Interrupt                                             
+                DCD     DSI_IRQHandler                    ;  DSI global Interrupt                                              
+                DCD     SDMMC2_IRQHandler                 ;  SDMMC2 global Interrupt                                           
+                DCD     HSEM1_IRQHandler                  ;  HSEM1 global Interrupt                                             
+                DCD     HSEM2_IRQHandler                  ;  HSEM2 global Interrupt                                             
+                DCD     ADC3_IRQHandler                   ;  ADC3 global Interrupt                                              
+                DCD     DMAMUX2_OVR_IRQHandler            ; DMAMUX Overrun interrupt                                           
+                DCD     BDMA_Channel0_IRQHandler          ;  BDMA Channel 0 global Interrupt                                    
+                DCD     BDMA_Channel1_IRQHandler          ;  BDMA Channel 1 global Interrupt                                    
+                DCD     BDMA_Channel2_IRQHandler          ;  BDMA Channel 2 global Interrupt                                    
+                DCD     BDMA_Channel3_IRQHandler          ;  BDMA Channel 3 global Interrupt                                    
+                DCD     BDMA_Channel4_IRQHandler          ;  BDMA Channel 4 global Interrupt                                    
+                DCD     BDMA_Channel5_IRQHandler          ;  BDMA Channel 5 global Interrupt                                    
+                DCD     BDMA_Channel6_IRQHandler          ;  BDMA Channel 6 global Interrupt                                    
+                DCD     BDMA_Channel7_IRQHandler          ;  BDMA Channel 7 global Interrupt                                    
+                DCD     COMP1_IRQHandler                  ;  COMP1 global Interrupt                                            
+                DCD     LPTIM2_IRQHandler                 ;  LP TIM2 global interrupt                                          
+                DCD     LPTIM3_IRQHandler                 ;  LP TIM3 global interrupt                                          
+                DCD     LPTIM4_IRQHandler                 ;  LP TIM4 global interrupt                                          
+                DCD     LPTIM5_IRQHandler                 ;  LP TIM5 global interrupt                                          
+                DCD     LPUART1_IRQHandler                ;  LP UART1 interrupt                                                
+                DCD     WWDG_RST_IRQHandler               ; Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it)                                
+                DCD     CRS_IRQHandler                    ;  Clock Recovery Global Interrupt                                   
+                DCD     ECC_IRQHandler                    ; ECC diagnostic Global Interrupt                                              
+                DCD     SAI4_IRQHandler                   ;  SAI4 global interrupt                                                
+                DCD     0                                 ; Reserved                                
+                DCD     HOLD_CORE_IRQHandler              ;  Hold core interrupt                                   
+                DCD     WAKEUP_PIN_IRQHandler             ;  Interrupt for all 6 wake-up pins 
+                
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                    [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                      [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler                [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler                [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler                 [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler               [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                      [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler                  [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                    [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                   [WEAK]
+                B       .
+                ENDP                                     
+                                                          
+Default_Handler PROC                                      
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]                                       
+                EXPORT  PVD_AVD_IRQHandler                [WEAK]                         
+                EXPORT  TAMP_STAMP_IRQHandler             [WEAK]   
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]             
+                EXPORT  FLASH_IRQHandler                  [WEAK]                                        
+                EXPORT  RCC_IRQHandler                    [WEAK]                                          
+                EXPORT  EXTI0_IRQHandler                  [WEAK]                                            
+                EXPORT  EXTI1_IRQHandler                  [WEAK]                                           
+                EXPORT  EXTI2_IRQHandler                  [WEAK]                                            
+                EXPORT  EXTI3_IRQHandler                  [WEAK]                                            
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Stream0_IRQHandler           [WEAK] 
+                EXPORT  DMA1_Stream1_IRQHandler           [WEAK]                        
+                EXPORT  DMA1_Stream2_IRQHandler           [WEAK]                     
+                EXPORT  DMA1_Stream3_IRQHandler           [WEAK]                    
+                EXPORT  DMA1_Stream4_IRQHandler           [WEAK]                        
+                EXPORT  DMA1_Stream5_IRQHandler           [WEAK]                          
+                EXPORT  DMA1_Stream6_IRQHandler           [WEAK]
+                EXPORT  DMA1_Stream7_IRQHandler           [WEAK]
+                EXPORT  ADC_IRQHandler                    [WEAK]                          
+                EXPORT  FDCAN1_IT0_IRQHandler             [WEAK]                                            
+                EXPORT  FDCAN2_IT0_IRQHandler             [WEAK] 
+                EXPORT  FDCAN1_IT1_IRQHandler             [WEAK]                                            
+                EXPORT  FDCAN2_IT1_IRQHandler             [WEAK]   
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]                                    
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]                  
+                EXPORT  TIM1_UP_IRQHandler                [WEAK]                
+                EXPORT  TIM1_TRG_COM_IRQHandler           [WEAK] 
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]                                   
+                EXPORT  TIM2_IRQHandler                   [WEAK]                                            
+                EXPORT  TIM3_IRQHandler                   [WEAK]                                            
+                EXPORT  TIM4_IRQHandler                   [WEAK]                                            
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]                                             
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]                                             
+                EXPORT  I2C2_EV_IRQHandler                [WEAK]                                            
+                EXPORT  I2C2_ER_IRQHandler                [WEAK]                                               
+                EXPORT  SPI1_IRQHandler                   [WEAK]                                           
+                EXPORT  SPI2_IRQHandler                   [WEAK]                                            
+                EXPORT  USART1_IRQHandler                 [WEAK]                                          
+                EXPORT  USART2_IRQHandler                 [WEAK]                                          
+                EXPORT  USART3_IRQHandler                 [WEAK]                                         
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]                                  
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]                                       
+                EXPORT  TIM8_BRK_TIM12_IRQHandler         [WEAK]                 
+                EXPORT  TIM8_UP_TIM13_IRQHandler          [WEAK]                 
+                EXPORT  TIM8_TRG_COM_TIM14_IRQHandler     [WEAK] 
+                EXPORT  TIM8_CC_IRQHandler                [WEAK]                                   
+                EXPORT  DMA1_Stream7_IRQHandler           [WEAK]                                          
+                EXPORT  FMC_IRQHandler                    [WEAK]                                             
+                EXPORT  SDMMC1_IRQHandler                 [WEAK]                                             
+                EXPORT  TIM5_IRQHandler                   [WEAK]                                             
+                EXPORT  SPI3_IRQHandler                   [WEAK]                                             
+                EXPORT  UART4_IRQHandler                  [WEAK]                                            
+                EXPORT  UART5_IRQHandler                  [WEAK]                                            
+                EXPORT  TIM6_DAC_IRQHandler               [WEAK]                   
+                EXPORT  TIM7_IRQHandler                   [WEAK]                    
+                EXPORT  DMA2_Stream0_IRQHandler           [WEAK]                                  
+                EXPORT  DMA2_Stream1_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream2_IRQHandler           [WEAK]                                    
+                EXPORT  DMA2_Stream3_IRQHandler           [WEAK]                                    
+                EXPORT  DMA2_Stream4_IRQHandler           [WEAK]                                 
+                EXPORT  ETH_IRQHandler                    [WEAK]                                         
+                EXPORT  ETH_WKUP_IRQHandler               [WEAK]                     
+                EXPORT  FDCAN_CAL_IRQHandler              [WEAK]                                                                                                                                                                              
+                EXPORT  CM7_SEV_IRQHandler                [WEAK]                                                                                                                                                                              
+                EXPORT  CM4_SEV_IRQHandler                [WEAK]                                                                                                                                                                              
+                EXPORT  DMA2_Stream5_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream6_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream7_IRQHandler           [WEAK]                                   
+                EXPORT  USART6_IRQHandler                 [WEAK]                                           
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]                                              
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]                                              
+                EXPORT  OTG_HS_EP1_OUT_IRQHandler         [WEAK]                      
+                EXPORT  OTG_HS_EP1_IN_IRQHandler          [WEAK]                      
+                EXPORT  OTG_HS_WKUP_IRQHandler            [WEAK]                        
+                EXPORT  OTG_HS_IRQHandler                 [WEAK]                                      
+                EXPORT  DCMI_IRQHandler                   [WEAK]                                             
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  UART7_IRQHandler                  [WEAK]
+                EXPORT  UART8_IRQHandler                  [WEAK]
+                EXPORT  SPI4_IRQHandler                   [WEAK]
+                EXPORT  SPI5_IRQHandler                   [WEAK]
+                EXPORT  SPI6_IRQHandler                   [WEAK]
+                EXPORT  SAI1_IRQHandler                   [WEAK]
+                EXPORT  LTDC_IRQHandler                   [WEAK]
+                EXPORT  LTDC_ER_IRQHandler                [WEAK]
+                EXPORT  DMA2D_IRQHandler                  [WEAK]
+                EXPORT  SAI2_IRQHandler                   [WEAK]   
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  CEC_IRQHandler                    [WEAK]   
+                EXPORT  I2C4_EV_IRQHandler                [WEAK]
+                EXPORT  I2C4_ER_IRQHandler                [WEAK] 
+                EXPORT  SPDIF_RX_IRQHandler               [WEAK]
+                EXPORT  OTG_FS_EP1_OUT_IRQHandler         [WEAK]
+                EXPORT  OTG_FS_EP1_IN_IRQHandler          [WEAK]                      
+                EXPORT  OTG_FS_WKUP_IRQHandler            [WEAK]                      
+                EXPORT  OTG_FS_IRQHandler                 [WEAK]                        
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+                EXPORT  HRTIM1_Master_IRQHandler          [WEAK] 
+                EXPORT  HRTIM1_TIMA_IRQHandler            [WEAK]                                      
+                EXPORT  HRTIM1_TIMB_IRQHandler            [WEAK]                                      
+                EXPORT  HRTIM1_TIMC_IRQHandler            [WEAK]                                      
+                EXPORT  HRTIM1_TIMD_IRQHandler            [WEAK]                                      
+                EXPORT  HRTIM1_TIME_IRQHandler            [WEAK]                                      
+                EXPORT  HRTIM1_FLT_IRQHandler             [WEAK]
+                EXPORT  DFSDM1_FLT0_IRQHandler            [WEAK] 
+                EXPORT  DFSDM1_FLT1_IRQHandler            [WEAK]                                             
+                EXPORT  DFSDM1_FLT2_IRQHandler            [WEAK]                                             
+                EXPORT  DFSDM1_FLT3_IRQHandler            [WEAK]                                                                                        
+                EXPORT  SAI3_IRQHandler                   [WEAK]                                             
+                EXPORT  SWPMI1_IRQHandler                 [WEAK]                            
+                EXPORT  TIM15_IRQHandler                  [WEAK]                                             
+                EXPORT  TIM16_IRQHandler                  [WEAK]                                              
+                EXPORT  TIM17_IRQHandler                  [WEAK]                                            
+                EXPORT  MDIOS_WKUP_IRQHandler             [WEAK]                                             
+                EXPORT  MDIOS_IRQHandler                  [WEAK]                                              
+                EXPORT  JPEG_IRQHandler                   [WEAK]                                               
+                EXPORT  MDMA_IRQHandler                   [WEAK]                                               
+                EXPORT  DSI_IRQHandler                    [WEAK]                                               
+                EXPORT  SDMMC2_IRQHandler                 [WEAK]                                             
+                EXPORT  HSEM1_IRQHandler                  [WEAK]                                               
+                EXPORT  HSEM2_IRQHandler                  [WEAK]                                               
+                EXPORT  ADC3_IRQHandler                   [WEAK]                                                
+                EXPORT  DMAMUX2_OVR_IRQHandler            [WEAK]                                            
+                EXPORT  BDMA_Channel0_IRQHandler          [WEAK]                                      
+                EXPORT  BDMA_Channel1_IRQHandler          [WEAK]                                      
+                EXPORT  BDMA_Channel2_IRQHandler          [WEAK]                                      
+                EXPORT  BDMA_Channel3_IRQHandler          [WEAK]                                      
+                EXPORT  BDMA_Channel4_IRQHandler          [WEAK]                                     
+                EXPORT  BDMA_Channel5_IRQHandler          [WEAK]                                      
+                EXPORT  BDMA_Channel6_IRQHandler          [WEAK]                                      
+                EXPORT  BDMA_Channel7_IRQHandler          [WEAK]                                     
+                EXPORT  COMP1_IRQHandler                  [WEAK]                                              
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]                                           
+                EXPORT  LPTIM3_IRQHandler                 [WEAK]                                            
+                EXPORT  LPTIM4_IRQHandler                 [WEAK]                                            
+                EXPORT  LPTIM5_IRQHandler                 [WEAK]                                            
+                EXPORT  LPUART1_IRQHandler                [WEAK]                                                  
+                EXPORT  WWDG_RST_IRQHandler               [WEAK]                                
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  ECC_IRQHandler                    [WEAK]				
+                EXPORT  SAI4_IRQHandler                   [WEAK]                                                  
+                EXPORT  HOLD_CORE_IRQHandler              [WEAK]                                   
+                EXPORT  WAKEUP_PIN_IRQHandler             [WEAK] 
+
+
+WWDG_IRQHandler                                                          
+PVD_AVD_IRQHandler                                             
+TAMP_STAMP_IRQHandler                
+RTC_WKUP_IRQHandler                            
+FLASH_IRQHandler                                                          
+RCC_IRQHandler                                                              
+EXTI0_IRQHandler                                                              
+EXTI1_IRQHandler                                                             
+EXTI2_IRQHandler                                                              
+EXTI3_IRQHandler                                                              
+EXTI4_IRQHandler 
+DMA1_Stream0_IRQHandler
+DMA1_Stream1_IRQHandler                                  
+DMA1_Stream2_IRQHandler                               
+DMA1_Stream3_IRQHandler                              
+DMA1_Stream4_IRQHandler                                  
+DMA1_Stream5_IRQHandler                                    
+DMA1_Stream6_IRQHandler                   
+ADC_IRQHandler                                           
+FDCAN1_IT0_IRQHandler
+FDCAN2_IT0_IRQHandler
+FDCAN1_IT1_IRQHandler
+FDCAN2_IT1_IRQHandler
+EXTI9_5_IRQHandler                                                
+TIM1_BRK_IRQHandler                        
+TIM1_UP_IRQHandler                      
+TIM1_TRG_COM_IRQHandler  
+TIM1_CC_IRQHandler                                               
+TIM2_IRQHandler                                                           
+TIM3_IRQHandler                                                           
+TIM4_IRQHandler                                                           
+I2C1_EV_IRQHandler                                                         
+I2C1_ER_IRQHandler                                                         
+I2C2_EV_IRQHandler                                                        
+I2C2_ER_IRQHandler                                                           
+SPI1_IRQHandler                                                          
+SPI2_IRQHandler                                                           
+USART1_IRQHandler                                                       
+USART2_IRQHandler                                                       
+USART3_IRQHandler                                                      
+EXTI15_10_IRQHandler                                            
+RTC_Alarm_IRQHandler                                                           
+TIM8_BRK_TIM12_IRQHandler                      
+TIM8_UP_TIM13_IRQHandler                       
+TIM8_TRG_COM_TIM14_IRQHandler  
+TIM8_CC_IRQHandler                                               
+DMA1_Stream7_IRQHandler                                                 
+FMC_IRQHandler                                                            
+SDMMC1_IRQHandler                                                            
+TIM5_IRQHandler                                                            
+SPI3_IRQHandler                                                            
+UART4_IRQHandler                                                          
+UART5_IRQHandler                                                          
+TIM6_DAC_IRQHandler                            
+TIM7_IRQHandler                              
+DMA2_Stream0_IRQHandler                                         
+DMA2_Stream1_IRQHandler                                          
+DMA2_Stream2_IRQHandler                                           
+DMA2_Stream3_IRQHandler                                           
+DMA2_Stream4_IRQHandler                                        
+ETH_IRQHandler                                                         
+ETH_WKUP_IRQHandler                                
+FDCAN_CAL_IRQHandler
+CM7_SEV_IRQHandler
+CM4_SEV_IRQHandler                                                                                                                                                                                                                             
+DMA2_Stream5_IRQHandler                                          
+DMA2_Stream6_IRQHandler                                          
+DMA2_Stream7_IRQHandler                                          
+USART6_IRQHandler                                                        
+I2C3_EV_IRQHandler                                                          
+I2C3_ER_IRQHandler                                                          
+OTG_HS_EP1_OUT_IRQHandler 
+OTG_HS_EP1_IN_IRQHandler 
+OTG_HS_WKUP_IRQHandler   
+OTG_HS_IRQHandler        
+DCMI_IRQHandler                                                            
+RNG_IRQHandler
+FPU_IRQHandler  
+UART7_IRQHandler                  
+UART8_IRQHandler                  
+SPI4_IRQHandler                   
+SPI5_IRQHandler                   
+SPI6_IRQHandler                   
+SAI1_IRQHandler                   
+LTDC_IRQHandler                   
+LTDC_ER_IRQHandler                 
+DMA2D_IRQHandler   
+SAI2_IRQHandler        
+QUADSPI_IRQHandler
+LPTIM1_IRQHandler
+CEC_IRQHandler
+I2C4_EV_IRQHandler
+I2C4_ER_IRQHandler
+SPDIF_RX_IRQHandler
+OTG_FS_EP1_OUT_IRQHandler
+OTG_FS_EP1_IN_IRQHandler 
+OTG_FS_WKUP_IRQHandler   
+OTG_FS_IRQHandler        
+DMAMUX1_OVR_IRQHandler
+HRTIM1_Master_IRQHandler               
+HRTIM1_TIMA_IRQHandler                                                      
+HRTIM1_TIMB_IRQHandler                                                      
+HRTIM1_TIMC_IRQHandler                                                      
+HRTIM1_TIMD_IRQHandler                                                      
+HRTIM1_TIME_IRQHandler                                                      
+HRTIM1_FLT_IRQHandler 
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler                                                                
+DFSDM1_FLT2_IRQHandler                                                                
+DFSDM1_FLT3_IRQHandler                                                                                                                                
+SAI3_IRQHandler                                                                    
+SWPMI1_IRQHandler                                                 
+TIM15_IRQHandler                                                                   
+TIM16_IRQHandler                                                                    
+TIM17_IRQHandler                                                                  
+MDIOS_WKUP_IRQHandler                                                              
+MDIOS_IRQHandler                                                                    
+JPEG_IRQHandler                                                                      
+MDMA_IRQHandler                                                                      
+DSI_IRQHandler                                                                       
+SDMMC2_IRQHandler                                                                  
+HSEM1_IRQHandler                                                                     
+HSEM2_IRQHandler                                                                     
+ADC3_IRQHandler                                                                       
+DMAMUX2_OVR_IRQHandler                                                            
+BDMA_Channel0_IRQHandler                                                     
+BDMA_Channel1_IRQHandler                                                     
+BDMA_Channel2_IRQHandler                                                     
+BDMA_Channel3_IRQHandler                                                     
+BDMA_Channel4_IRQHandler                                                    
+BDMA_Channel5_IRQHandler                                                     
+BDMA_Channel6_IRQHandler                                                     
+BDMA_Channel7_IRQHandler                                                    
+COMP1_IRQHandler                                                                    
+LPTIM2_IRQHandler                                                                
+LPTIM3_IRQHandler                                                                 
+LPTIM4_IRQHandler                                                                 
+LPTIM5_IRQHandler                                                                 
+LPUART1_IRQHandler                                                                      
+WWDG_RST_IRQHandler                                                   
+CRS_IRQHandler
+ECC_IRQHandler                                                           
+SAI4_IRQHandler      
+HOLD_CORE_IRQHandler 
+WAKEUP_PIN_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+                
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+                
+                 ELSE
+                
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+                 
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/MDK-ARM/stm32h747xx_flash_CM4.sct b/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/MDK-ARM/stm32h747xx_flash_CM4.sct
new file mode 100644
index 0000000000..83f7f34290
--- /dev/null
+++ b/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/MDK-ARM/stm32h747xx_flash_CM4.sct
@@ -0,0 +1,14 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08100000 0x00100000  {    ; load region size_region
+  ER_IROM1 0x08100000 0x00100000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1 0x10000000 0x10048000{  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
diff --git a/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/MDK-ARM/stm32h747xx_flash_CM7.sct b/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/MDK-ARM/stm32h747xx_flash_CM7.sct
new file mode 100644
index 0000000000..5381dfedfe
--- /dev/null
+++ b/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/MDK-ARM/stm32h747xx_flash_CM7.sct
@@ -0,0 +1,14 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00100000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00100000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1 0x20000000 0x20020000{  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
diff --git a/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/MDK-ARM/stm32h747xx_sram1_CM7.sct b/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/MDK-ARM/stm32h747xx_sram1_CM7.sct
new file mode 100644
index 0000000000..a40e3572ab
--- /dev/null
+++ b/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/MDK-ARM/stm32h747xx_sram1_CM7.sct
@@ -0,0 +1,14 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x24000000 0x00040000  {    ; load region size_region
+  ER_IROM1 0x24000000 0x00040000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1 0x24040000 0x24080000{  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
diff --git a/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/MDK-ARM/stm32h747xx_sram2_CM4.sct b/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/MDK-ARM/stm32h747xx_sram2_CM4.sct
new file mode 100644
index 0000000000..081f153c1e
--- /dev/null
+++ b/bsp/stm32/stm32h747-st-discovery/board/CubeMX_Config/MDK-ARM/stm32h747xx_sram2_CM4.sct
@@ -0,0 +1,14 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x10000000 0x00020000  {    ; load region size_region
+  ER_IROM1 0x10000000 0x00020000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1 0x10020000 0x10048000{  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
diff --git a/bsp/stm32/stm32h747-st-discovery/board/Kconfig b/bsp/stm32/stm32h747-st-discovery/board/Kconfig
new file mode 100644
index 0000000000..e1f1d01aba
--- /dev/null
+++ b/bsp/stm32/stm32h747-st-discovery/board/Kconfig
@@ -0,0 +1,40 @@
+menu "Hardware Drivers Config"
+
+config SOC_STM32H747XI
+    bool
+    select SOC_SERIES_STM32H7
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y
+
+menu "Onboard Peripheral Drivers"
+
+endmenu
+
+menu "On-chip Peripheral Drivers"
+
+    config BSP_USING_GPIO
+        bool "Enable GPIO"
+        select RT_USING_PIN
+        default y
+
+    menuconfig BSP_USING_UART
+        bool "Enable UART"
+        default y
+        select RT_USING_SERIAL
+        if BSP_USING_UART
+            config BSP_USING_UART1
+                bool "Enable UART1"
+                default y
+
+        endif
+
+    source "../libraries/HAL_Drivers/Kconfig"
+    
+endmenu
+
+menu "Board extended module Drivers"
+
+endmenu
+ 
+endmenu
diff --git a/bsp/stm32/stm32h747-st-discovery/board/SConscript b/bsp/stm32/stm32h747-st-discovery/board/SConscript
new file mode 100644
index 0000000000..afeb09be64
--- /dev/null
+++ b/bsp/stm32/stm32h747-st-discovery/board/SConscript
@@ -0,0 +1,25 @@
+import rtconfig
+from building import *
+
+cwd = GetCurrentDir()
+
+# add the general drivers.
+src = Glob('board.c')
+src += Glob('CubeMX_Config/CM7/Src/stm32h7xx_hal_msp.c')
+
+path = [cwd]
+path += [cwd + '/CubeMX_Config/CM7/Inc']
+
+if rtconfig.CROSS_TOOL == 'gcc':
+    src += [cwd + '/../../libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h747xx.s']
+elif rtconfig.CROSS_TOOL == 'keil':
+    src += [cwd + '/../../libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h747xx.s']
+elif rtconfig.CROSS_TOOL == 'iar':
+    src += [cwd + '/../../libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h747xx.s']
+
+# STM32H743xx || STM32H750xx || STM32F753xx
+# You can select chips from the list above
+CPPDEFINES = ['STM32H747xx']
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+
+Return('group')
diff --git a/bsp/stm32/stm32h747-st-discovery/board/board.c b/bsp/stm32/stm32h747-st-discovery/board/board.c
new file mode 100644
index 0000000000..a7af6b13f8
--- /dev/null
+++ b/bsp/stm32/stm32h747-st-discovery/board/board.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-06     SummerGift   first version
+ */
+
+#include "board.h"
+
+/**
+  * @brief  System Clock Configuration
+  *         The system Clock is configured as follow :
+  *            System Clock source            = PLL (HSE)
+  *            SYSCLK(Hz)                     = 400000000 (Cortex-M7 CPU Clock)
+  *            HCLK(Hz)                       = 200000000 (Cortex-M4 CPU, Bus matrix Clocks)
+  *            AHB Prescaler                  = 2
+  *            D1 APB3 Prescaler              = 2 (APB3 Clock  100MHz)
+  *            D2 APB1 Prescaler              = 2 (APB1 Clock  100MHz)
+  *            D2 APB2 Prescaler              = 2 (APB2 Clock  100MHz)
+  *            D3 APB4 Prescaler              = 2 (APB4 Clock  100MHz)
+  *            HSE Frequency(Hz)              = 25000000
+  *            PLL_M                          = 5
+  *            PLL_N                          = 160
+  *            PLL_P                          = 2
+  *            PLL_Q                          = 4
+  *            PLL_R                          = 2
+  *            VDD(V)                         = 3.3
+  *            Flash Latency(WS)              = 4
+  * @param  None
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_ClkInitTypeDef RCC_ClkInitStruct;
+  RCC_OscInitTypeDef RCC_OscInitStruct;
+  HAL_StatusTypeDef ret = HAL_OK;
+
+  /*!< Supply configuration update enable */
+  HAL_PWREx_ConfigSupply(PWR_DIRECT_SMPS_SUPPLY);
+
+  /* The voltage scaling allows optimizing the power consumption when the device is
+     clocked below the maximum system frequency, to update the voltage scaling value
+     regarding system frequency refer to product datasheet.  */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
+
+  /* Enable HSE Oscillator and activate PLL with HSE as source */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
+  RCC_OscInitStruct.CSIState = RCC_CSI_OFF;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+
+  RCC_OscInitStruct.PLL.PLLM = 5;
+  RCC_OscInitStruct.PLL.PLLN = 160;
+  RCC_OscInitStruct.PLL.PLLFRACN = 0;
+  RCC_OscInitStruct.PLL.PLLP = 2;
+  RCC_OscInitStruct.PLL.PLLR = 2;
+  RCC_OscInitStruct.PLL.PLLQ = 4;
+
+  RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
+  RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
+  ret = HAL_RCC_OscConfig(&RCC_OscInitStruct);
+  if(ret != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+/* Select PLL as system clock source and configure  bus clocks dividers */
+  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | \
+                                 RCC_CLOCKTYPE_PCLK2  | RCC_CLOCKTYPE_D3PCLK1);
+
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
+  RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
+  RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
+  ret = HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
+  if(ret != HAL_OK)
+  {
+    Error_Handler();
+  }
+}
diff --git a/bsp/stm32/stm32h747-st-discovery/board/board.h b/bsp/stm32/stm32h747-st-discovery/board/board.h
new file mode 100644
index 0000000000..c3441d01b1
--- /dev/null
+++ b/bsp/stm32/stm32h747-st-discovery/board/board.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-5      SummerGift   first version
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include <rtthread.h>
+#include <stm32h7xx.h>
+#include "drv_common.h"
+#include "drv_gpio.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define STM32_FLASH_START_ADRESS     ((uint32_t)0x8000000)
+#define STM32_FLASH_SIZE             (2048 * 1024)
+#define STM32_FLASH_END_ADDRESS      ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE))
+
+#define STM32_SRAM_SIZE              (128)
+#define STM32_SRAM_END               (0x20000000 + STM32_SRAM_SIZE * 1024)
+
+#if defined(__CC_ARM) || defined(__CLANG_ARM)
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define HEAP_BEGIN      (&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section="CSTACK"
+#define HEAP_BEGIN      (__segment_end("CSTACK"))
+#else
+extern int __bss_end;
+#define HEAP_BEGIN      (&__bss_end)
+#endif
+
+#define HEAP_END        STM32_SRAM_END
+
+void SystemClock_Config(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/stm32/stm32h747-st-discovery/board/linker_scripts/link.icf b/bsp/stm32/stm32h747-st-discovery/board/linker_scripts/link.icf
new file mode 100644
index 0000000000..8c0c0b8ffb
--- /dev/null
+++ b/bsp/stm32/stm32h747-st-discovery/board/linker_scripts/link.icf
@@ -0,0 +1,28 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x08100000;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20020000;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x800;
+define symbol __ICFEDIT_size_heap__   = 0x400;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite, last block CSTACK};
diff --git a/bsp/stm32/stm32h747-st-discovery/board/linker_scripts/link.lds b/bsp/stm32/stm32h747-st-discovery/board/linker_scripts/link.lds
new file mode 100644
index 0000000000..da8bb21a76
--- /dev/null
+++ b/bsp/stm32/stm32h747-st-discovery/board/linker_scripts/link.lds
@@ -0,0 +1,157 @@
+/*
+ * linker script for STM32H7xx with GNU ld
+ * SummerGift 2020.2.24
+ */
+
+/* Program Entry, set to mark it as "used" and avoid gc */
+MEMORY
+{
+    ROM (rx) : ORIGIN = 0x08000000, LENGTH = 1024k /* 1024KB flash */
+    RAM (rw) : ORIGIN = 0x20000000, LENGTH =  128k /* 512K sram */
+}
+ENTRY(Reset_Handler)
+_system_stack_size = 0x200;
+
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _stext = .;
+        KEEP(*(.isr_vector))            /* Startup code */
+
+        . = ALIGN(4);
+        *(.text)                        /* remaining code */
+        *(.text.*)                      /* remaining code */
+        *(.rodata)                      /* read-only data (constants) */
+        *(.rodata*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.gnu.linkonce.t*)
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+
+        /* section information for initial. */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+
+        . = ALIGN(4);
+
+        PROVIDE(__ctors_start__ = .);
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        PROVIDE(__ctors_end__ = .);
+
+        . = ALIGN(4);
+
+        _etext = .;
+    } > ROM = 0
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+
+        /* This is used by the startup in order to initialize the .data secion */
+        _sidata = .;
+    } > ROM
+    __exidx_end = .;
+
+    /* .data section which is used for initialized data */
+
+    .data : AT (_sidata)
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _sdata = . ;
+
+        *(.data)
+        *(.data.*)
+        *(.gnu.linkonce.d*)
+
+        PROVIDE(__dtors_start__ = .);
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+        PROVIDE(__dtors_end__ = .);
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _edata = . ;
+    } >RAM
+
+    .stack : 
+    {
+        . = ALIGN(4);
+        _sstack = .;
+        . = . + _system_stack_size;
+        . = ALIGN(4);
+        _estack = .;
+    } >RAM
+
+    __bss_start = .;
+    .bss :
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _sbss = .;
+
+        *(.bss)
+        *(.bss.*)
+        *(COMMON)
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _ebss = . ;
+        
+        *(.bss.init)
+    } > RAM
+    __bss_end = .;
+
+    _end = .;
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}
diff --git a/bsp/stm32/stm32h747-st-discovery/board/linker_scripts/link.sct b/bsp/stm32/stm32h747-st-discovery/board/linker_scripts/link.sct
new file mode 100644
index 0000000000..2866134d54
--- /dev/null
+++ b/bsp/stm32/stm32h747-st-discovery/board/linker_scripts/link.sct
@@ -0,0 +1,14 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00100000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00100000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1 0x20000000 0x20020000{  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
\ No newline at end of file