This commit is contained in:
toasun 2015-05-12 15:44:57 +08:00
parent bd59276640
commit a58078d18a
9 changed files with 8945 additions and 8758 deletions

File diff suppressed because it is too large Load Diff

@ -43,7 +43,12 @@
#define _TIM #define _TIM
#define _UART #define _UART
#define _USB #define _USB
#define _WDG #define _WDG
//#define _MARVELL
//#define _IP1826D
#define _M7NORFLASH
#define _ME_6095_F
#define USE_FULL_ASSERT 1 #define USE_FULL_ASSERT 1
@ -71,7 +76,9 @@ typedef enum _BOOL {FALSE = 0, TRUE = 1} BOOL;
/** /**
* System clock frequency, unit is Hz. * System clock frequency, unit is Hz.
*/ */
#define SYSTEM_CLOCK_FREQ 200000000 #define SYSTEM_CLOCK_FREQ 300000000
//250000000
//300000000
/** /**
* @brief usecond delay * @brief usecond delay

@ -1,382 +1,417 @@
/** /**
***************************************************************************** *****************************************************************************
* @file cmem7_eth.h * @file cmem7_eth.h
* *
* @brief CMEM7 ethernet header file * @brief CMEM7 ethernet header file
* *
* *
* @version V1.0 * @version V1.0
* @date 3. September 2013 * @date 3. September 2013
* *
* @note * @note
* *
***************************************************************************** *****************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
* *
* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2> * <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
***************************************************************************** *****************************************************************************
*/ */
#ifndef __CMEM7_ETH_H #ifndef __CMEM7_ETH_H
#define __CMEM7_ETH_H #define __CMEM7_ETH_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
#include "cmem7.h" #include "cmem7.h"
#include "cmem7_conf.h" #include "cmem7_conf.h"
/** @defgroup ETH_SPEED /** @defgroup ETH_SPEED
* @{ * @{
*/ */
#define ETH_SPEED_10M 0x0 #define ETH_SPEED_10M 0x0
#define ETH_SPEED_100M 0x1 #define ETH_SPEED_100M 0x1
#define ETH_SPEED_1000M 0x2 #define ETH_SPEED_1000M 0x2
#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \ #define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \
((SPEED) == ETH_SPEED_100M) || \ ((SPEED) == ETH_SPEED_100M) || \
((SPEED) == ETH_SPEED_1000M)) ((SPEED) == ETH_SPEED_1000M))
/** /**
* @} * @}
*/ */
/** @defgroup ETH_DUPLEX /** @defgroup ETH_DUPLEX
* @{ * @{
*/ */
#define ETH_DUPLEX_HALF 0x0 #define ETH_DUPLEX_HALF 0x0
#define ETH_DUPLEX_FULL 0x1 #define ETH_DUPLEX_FULL 0x1
#define IS_ETH_DUPLEX(DUPLEX) (((DUPLEX) == ETH_DUPLEX_HALF) || \ #define IS_ETH_DUPLEX(DUPLEX) (((DUPLEX) == ETH_DUPLEX_HALF) || \
((DUPLEX) == ETH_DUPLEX_FULL)) ((DUPLEX) == ETH_DUPLEX_FULL))
/** /**
* @} * @}
*/ */
/** @defgroup ETH_INT /** @defgroup ETH_INT
* @{ * @{
*/ */
#define ETH_INT_TX_COMPLETE_FRAME 0x0001 #define ETH_INT_TX_COMPLETE_FRAME 0x0001
#define ETH_INT_TX_STOP 0x0002 #define ETH_INT_TX_STOP 0x0002
#define ETH_INT_TX_BUF_UNAVAI 0x0004 #define ETH_INT_TX_BUF_UNAVAI 0x0004
#define ETH_INT_RX_OVERFLOW 0x0010 #define ETH_INT_RX_OVERFLOW 0x0010
#define ETH_INT_TX_UNDERFLOW 0x0020 #define ETH_INT_TX_UNDERFLOW 0x0020
#define ETH_INT_RX_COMPLETE_FRAME 0x0040 #define ETH_INT_RX_COMPLETE_FRAME 0x0040
#define ETH_INT_RX_BUF_UNAVAI 0x0080 #define ETH_INT_RX_BUF_UNAVAI 0x0080
#define ETH_INT_RX_STOP 0x0100 #define ETH_INT_RX_STOP 0x0100
#define ETH_INT_BUS_FATAL_ERROR 0x2000 #define ETH_INT_BUS_FATAL_ERROR 0x2000
#define ETH_INT_ALL (ETH_INT_TX_COMPLETE_FRAME | \ #define ETH_INT_ALL (ETH_INT_TX_COMPLETE_FRAME | \
ETH_INT_TX_STOP | \ ETH_INT_TX_STOP | \
ETH_INT_TX_BUF_UNAVAI | \ ETH_INT_TX_BUF_UNAVAI | \
ETH_INT_RX_OVERFLOW | \ ETH_INT_RX_OVERFLOW | \
ETH_INT_TX_UNDERFLOW | \ ETH_INT_TX_UNDERFLOW | \
ETH_INT_RX_COMPLETE_FRAME | \ ETH_INT_RX_COMPLETE_FRAME | \
ETH_INT_RX_BUF_UNAVAI | \ ETH_INT_RX_BUF_UNAVAI | \
ETH_INT_RX_STOP | \ ETH_INT_RX_STOP | \
ETH_INT_BUS_FATAL_ERROR) ETH_INT_BUS_FATAL_ERROR)
#define IS_ETH_INT(INT) (((INT) != 0) && (((INT) & ~ETH_INT_ALL) == 0)) #define IS_ETH_INT(INT) (((INT) != 0) && (((INT) & ~ETH_INT_ALL) == 0))
/** /**
* @} * @}
*/ */
/**
/** * @brief EFUSE receive filter structure
* @brief EFUSE receive filter structure */
*/ typedef struct
typedef struct {
{ BOOL ETH_BroadcastFilterEnable; /*!< Broadcast is dropped or passed */
BOOL ETH_BroadcastFilterEnable; /*!< Broadcast is dropped or passed */ BOOL ETH_OwnFilterEnable; /*!< source address filter is on or off */
BOOL ETH_OwnFilterEnable; /*!< source address filter is on or off */ BOOL ETH_SelfDrop; /*!< Only own address is dropped or passed */
BOOL ETH_SelfDrop; /*!< Only own address is dropped or passed */ BOOL ETH_SourceFilterEnable; /*!< source address filter is on or off */
BOOL ETH_SourceFilterEnable; /*!< source address filter is on or off */ BOOL ETH_SourceDrop; /*!< Only specific source address is dropped or passed */
BOOL ETH_SourceDrop; /*!< Only specific source address is dropped or passed */ uint8_t ETH_SourceMacAddr[6]; /*!< Source MAC address */
uint8_t ETH_SourceMacAddr[6]; /*!< Source MAC address */ } ETH_FrameFilter;
} ETH_FrameFilter;
/**
/** * @brief Ethernet initialization structure
* @brief Ethernet initialization structure */
*/ typedef struct
typedef struct {
{ BOOL ETH_LinkUp; /*!< If ETH is linked up and it can be retrieved from PHY */
BOOL ETH_LinkUp; /*!< If ETH is linked up and it can be retrieved from PHY */ uint8_t ETH_Speed; /*!< speed of ETH, refer as @ref ETH_SPEED */
uint8_t ETH_Speed; /*!< speed of ETH, refer as @ref ETH_SPEED */ uint8_t ETH_Duplex; /*!< duplex mode of ETH, refer as @ref ETH_DUPLEX */
uint8_t ETH_Duplex; /*!< duplex mode of ETH, refer as @ref ETH_DUPLEX */ BOOL ETH_RxEn; /*!< Rx enable */
BOOL ETH_RxEn; /*!< Rx enable */ BOOL ETH_TxEn; /*!< Tx enable */
BOOL ETH_TxEn; /*!< Tx enable */ BOOL ETH_ChecksumOffload; /*!< Checksum offload enable */
BOOL ETH_ChecksumOffload; /*!< Checksum offload enable */ BOOL ETH_JumboFrame; /*!< Jumbo Frame Enable */
BOOL ETH_JumboFrame; /*!< Jumbo Frame Enable */ uint8_t ETH_MacAddr[6]; /*!< MAC address */
uint8_t ETH_MacAddr[6]; /*!< MAC address */ ETH_FrameFilter *ETH_Filter; /*!< Received frame address filter, receive all if null */
ETH_FrameFilter *ETH_Filter; /*!< Received frame address filter, receive all if null */ } ETH_InitTypeDef;
} ETH_InitTypeDef;
/**
/** * @brief Ethernet Tx descriptor structure
* @brief Ethernet Tx descriptor structure */
*/ typedef struct {
typedef struct { union {
union { uint32_t TX0;
uint32_t TX0;
struct {
struct { uint32_t : 1;
uint32_t : 1; uint32_t UNDERFLOW_ERR : 1; /*!< [OUT] Underflow error */
uint32_t UNDERFLOW_ERR : 1; /*!< [OUT] Underflow error */ uint32_t : 1;
uint32_t : 1; uint32_t COLLISION_CNT : 4; /*!< [OUT] Collision count */
uint32_t COLLISION_CNT : 4; /*!< [OUT] Collision count */ uint32_t : 1;
uint32_t : 1; uint32_t EX_COLLISION : 1; /*!< [OUT] Excessive collision error */
uint32_t EX_COLLISION : 1; /*!< [OUT] Excessive collision error */ uint32_t LATE_COLLISION : 1; /*!< [OUT] Late collision error */
uint32_t LATE_COLLISION : 1; /*!< [OUT] Late collision error */ uint32_t NO_CARRIER : 1; /*!< [OUT] No carrier error */
uint32_t NO_CARRIER : 1; /*!< [OUT] No carrier error */ uint32_t LOSS_CARRIER : 1; /*!< [OUT] loss of carrier error */
uint32_t LOSS_CARRIER : 1; /*!< [OUT] loss of carrier error */ uint32_t PAYLOAD_ERR : 1; /*!< [OUT] IP payload error */
uint32_t PAYLOAD_ERR : 1; /*!< [OUT] IP payload error */ uint32_t : 2;
uint32_t : 2; uint32_t ERR_SUM : 1; /*!< [OUT] Error summary */
uint32_t ERR_SUM : 1; /*!< [OUT] Error summary */ uint32_t HEADER_ERR : 1; /*!< [OUT] IP header error */
uint32_t HEADER_ERR : 1; /*!< [OUT] IP header error */ uint32_t : 8;
uint32_t : 8; uint32_t TTSE : 1; /*!< enables IEEE1588 hardware timestamping in first segment */
uint32_t TTSE : 1; /*!< enables IEEE1588 hardware timestamping in first segment */ uint32_t : 2;
uint32_t : 2; uint32_t FS : 1; /*!< first segment flag */
uint32_t FS : 1; /*!< first segment flag */ uint32_t LS : 1; /*!< last segment flag */
uint32_t LS : 1; /*!< last segment flag */ uint32_t : 2;
uint32_t : 2; } TX0_b;
} TX0_b; } TX_0;
} TX_0;
union {
union { uint32_t TX1;
uint32_t TX1;
struct {
struct { uint32_t SIZE : 13; /*!< buffer size */
uint32_t SIZE : 13; /*!< buffer size */ uint32_t : 19;
uint32_t : 19; } TX1_b;
} TX1_b; } TX_1;
} TX_1;
uint32_t bufAddr; /*!< address of buffer */
uint32_t bufAddr; /*!< address of buffer */ uint32_t nextDescAddr; /*!< address of next descriptor */
uint32_t nextDescAddr; /*!< address of next descriptor */ uint64_t reserved;
uint64_t reserved; uint64_t timeStamp; /*!< time stamp while last segment */
uint64_t timeStamp; /*!< time stamp while last segment */ } ETH_TX_DESC;
} ETH_TX_DESC;
/**
/** * @brief Ethernet Rx descriptor structure
* @brief Ethernet Rx descriptor structure */
*/ typedef struct {
typedef struct { union {
union { uint32_t RX0;
uint32_t RX0;
struct {
struct { uint32_t : 1;
uint32_t : 1; uint32_t CRC_ERR : 1; /*!< [OUT] CRC error while last segment */
uint32_t CRC_ERR : 1; /*!< [OUT] CRC error while last segment */ uint32_t : 5;
uint32_t : 5; uint32_t TTSE : 1; /*!< timestamp available while last segment */
uint32_t TTSE : 1; /*!< timestamp available while last segment */ uint32_t LS : 1; /*!< [OUT] last segment flag */
uint32_t LS : 1; /*!< last segment flag */ uint32_t FS : 1; /*!< [OUT] first segment flag */
uint32_t FS : 1; /*!< first segment flag */ uint32_t : 1;
uint32_t : 1; uint32_t OVERFLOW_ERR : 1; /*!< [OUT] FIFO overflow while last segment */
uint32_t OVERFLOW_ERR : 1; /*!< [OUT] FIFO overflow while last segment */ uint32_t LENGTH_ERR : 1; /*!< [OUT] length error while last segment */
uint32_t LENGTH_ERR : 1; /*!< [OUT] length error while last segment */ uint32_t : 2;
uint32_t : 2; uint32_t ERR_SUM : 1; /*!< [OUT] Error summary while last segment */
uint32_t ERR_SUM : 1; /*!< [OUT] Error summary while last segment */ uint32_t FL : 14; /*!< [OUT] frame length while last segment */
uint32_t FL : 14; /*!< frame length while last segment */ uint32_t : 2;
uint32_t : 2; } RX0_b;
} RX0_b; } RX_0;
} RX_0;
union {
union { uint32_t RX1;
uint32_t RX1;
struct {
struct { uint32_t SIZE : 13; /*!< buffer size */
uint32_t SIZE : 13; /*!< buffer size */ uint32_t : 19;
uint32_t : 19; } RX1_b;
} RX1_b; } RX_1;
} RX_1;
uint32_t bufAddr; /*!< buffer address */
uint32_t bufAddr; /*!< buffer address */ uint32_t nextDescAddr; /*!< address of next descriptor */
uint32_t nextDescAddr; /*!< address of next descriptor */ uint64_t reserved;
uint64_t reserved; uint64_t timeStamp; /*!< time stamp while the last segment */
uint64_t timeStamp; /*!< time stamp while the last segment */ } ETH_RX_DESC;
} ETH_RX_DESC;
/**
/** * @brief Read data from phy chip
* @brief Read data from phy chip * @param[in] phyAddr Address of phy chip
* @param[in] phyAddr Address of phy chip * @param[in] phyReg Address of phy's register to be read
* @param[in] phyReg Address of phy's register to be read * @retval uint32_t value of phy's register
* @retval uint32_t value of phy's register */
*/ uint32_t ETH_PhyRead(uint32_t phyAddr, uint32_t phyReg);
uint32_t ETH_PhyRead(uint32_t phyAddr, uint32_t phyReg);
/**
/** * @brief Write data to phy chip
* @brief Write data to phy chip * @param[in] phyAddr Address of phy chip
* @param[in] phyAddr Address of phy chip * @param[in] phyReg Address of phy's register to be written
* @param[in] phyReg Address of phy's register to be written * @param[in] data Data to be written
* @param[in] data Data to be written * @retval None
* @retval None */
*/ void ETH_PhyWrite(uint32_t phyAddr, uint32_t phyReg, uint32_t data);
void ETH_PhyWrite(uint32_t phyAddr, uint32_t phyReg, uint32_t data); /**
* @brief Fills each ETH_InitStruct member with its default value.
/** * @param ETH_InitStruct: pointer to a ETH_InitTypeDef structure
* @brief Ethernet initialization * which will be initialized.
* @note This function should be called at first before any other interfaces. * @retval : None
* @param[in] init A pointer to structure ETH_InitTypeDef */
* @retval BOOL The bit indicates if ethernet is initialized successfully void ETH_StructInit(ETH_InitTypeDef* init);
*/ /**
BOOL ETH_Init(ETH_InitTypeDef *init); * @brief Ethernet initialization
* @note This function should be called at first before any other interfaces.
/** * @param[in] init A pointer to structure ETH_InitTypeDef
* @brief Enable or disable ethernet interrupt. * @retval BOOL The bit indicates if ethernet is initialized successfully
* @param[in] Int interrupt mask bits, which can be the combination of @ref ETH_INT */
* @param[in] Enable The bit indicates if specific interrupts are enable or not BOOL ETH_Init(ETH_InitTypeDef *init);
* @retval None
*/ /**
void ETH_EnableInt(uint32_t Int, BOOL enable); * @brief Enable or disable ethernet interrupt.
* @param[in] Int interrupt mask bits, which can be the combination of @ref ETH_INT
/** * @param[in] Enable The bit indicates if specific interrupts are enable or not
* @brief Check specific interrupts are set or not * @retval None
* @param[in] Int interrupt mask bits, which can be the combination of @ref ETH_INT */
* @retval BOOL The bit indicates if specific interrupts are set or not void ETH_ITConfig(uint32_t Int, BOOL enable);
*/
BOOL ETH_GetIntStatus(uint32_t Int); /**
* @brief Check specific interrupts are set or not
/** * @param[in] Int interrupt mask bits, which can be the combination of @ref ETH_INT
* @brief Clear specific interrupts * @retval BOOL The bit indicates if specific interrupts are set or not
* @param[in] Int interrupt mask bits, which can be the combination of @ref ETH_INT */
* @retval None BOOL ETH_GetITStatus(uint32_t Int);
*/
void ETH_ClearInt(uint32_t Int); /**
* @brief Clear specific interrupts
/** * @param[in] Int interrupt mask bits, which can be the combination of @ref ETH_INT
* @brief Get ethernte MAC address * @retval None
* @param[in] mac A user-allocated buffer to fetch MAC to be read, 6 bytes. */
* @retval None void ETH_ClearITPendingBit(uint32_t Int);
*/
void ETH_GetMacAddr(uint8_t *mac); /**
* @brief Get ethernte MAC address
/** * @param[in] mac A user-allocated buffer to fetch MAC to be read, 6 bytes.
* @brief Set ethernet transmission descriptor ring * @retval None
* @note Make sure that memory occupied by descriptors should be in physical */
* memory and keep valid before ethernet transmission is finished. void ETH_GetMacAddr(uint8_t *mac);
* @param[in] ring A pointer to header of ETH_TX_DESC ring, whose last node
* has a 'nextDescAddr' pointed to first node. /**
* @retval BOOL The bit indicates if valid ring is set * @brief Set ethernet transmission descriptor ring
*/ * @note Make sure that memory occupied by descriptors should be in physical
BOOL ETH_SetTxDescRing(ETH_TX_DESC *ring); * memory and keep valid before ethernet transmission is finished.
* @param[in] ring A pointer to header of ETH_TX_DESC ring, whose last node
/** * has a 'nextDescAddr' pointed to first node.
* @brief Start ethernet transmission * @retval BOOL The bit indicates if valid ring is set
* @param None */
* @retval None BOOL ETH_SetTxDescRing(ETH_TX_DESC *ring);
*/
void ETH_StartTx(void); /**
* @brief Start ethernet transmission
/** * @param None
* @brief Stop ethernet transmission * @retval None
* @param None */
* @retval None void ETH_StartTx(void);
*/
void ETH_StopTx(void); /**
* @brief Stop ethernet transmission
/** * @param None
* @brief Resume ethernet transmission\n * @retval None
* While ethernet doesn't have enough buffer to transmit data, it will */
* pause and inform users by interrupt 'ETH_INT_TX_BUF_UNAVAI'. Users void ETH_StopTx(void);
* must call this function to start ethernet again after new buffer
* prepared. /**
* @param None * @brief Resume ethernet transmission\n
* @retval None * While ethernet doesn't have enough buffer to transmit data, it will
*/ * pause and inform users by interrupt 'ETH_INT_TX_BUF_UNAVAI'. Users
void ETH_ResumeTx(void); * must call this function to start ethernet again after new buffer
* prepared.
/** * @param None
* @brief Get free transmission descriptor\n * @retval None
* @param None */
* @retval ETH_TX_DESC* A pointer of free transmission descriptor, void ETH_ResumeTx(void);
* NULL if no free descriptor
*/ /**
ETH_TX_DESC *ETH_AcquireFreeTxDesc(void); * @brief Get free transmission descriptor\n
* @param None
/** * @retval ETH_TX_DESC* A pointer of free transmission descriptor,
* @brief Check if a transmission descriptor is free or not * NULL if no free descriptor
* @param desc A pointer of a transmission descriptor */
* @retval BOOL True if the transmission descriptor is free, or flase. ETH_TX_DESC *ETH_AcquireFreeTxDesc(void);
*/
BOOL ETH_IsFreeTxDesc(ETH_TX_DESC *desc); /**
* @brief Check if a transmission descriptor is free or not
/** * @param[in] desc A pointer of a transmission descriptor
* @brief Release a transmission descriptor to ethernet\n * @retval BOOL True if the transmission descriptor is free, or flase.
* After users prepared data in the buffer of a free descriptor, */
* They must call this function to change ownership of the BOOL ETH_IsFreeTxDesc(ETH_TX_DESC *desc);
* descriptor to hardware.
* @param desc A pointer of a transmission descriptor /**
* @retval None * @brief Release a transmission descriptor to ethernet\n
*/ * After users prepared data in the buffer of a free descriptor,
void ETH_ReleaseTxDesc(ETH_TX_DESC *desc); * They must call this function to change ownership of the
* descriptor to hardware.
/** * @param[in] desc A pointer of a transmission descriptor
* @brief Set ethernet receive descriptor ring * @retval None
* @note Make sure that memory occupied by descriptors should be in physical */
* memory and keep valid before ethernet receive is finished. void ETH_ReleaseTxDesc(ETH_TX_DESC *desc);
* @param[in] ring A pointer to header of ETH_TX_DESC ring, whose last node
* has a 'nextDescAddr' pointed to first node. /**
* @retval BOOL The bit indicates if valid ring is set * @brief Set buffer address of the specific TX descriptor
*/ * @param[in] desc A pointer of a transmission descriptor
BOOL ETH_SetRxDescRing(ETH_RX_DESC *ring); * @param[in] bufAddr buffer address to be sent
* @retval None
/** */
* @brief Start ethernet receive void ETH_SetTxDescBufAddr(ETH_TX_DESC *desc, uint32_t bufAddr);
* @param None
* @retval None /**
*/ * @brief Get buffer address of the specific TX descriptor
void ETH_StartRx(void); * @param[in] desc A pointer of a transmission descriptor
* @retval uint32_t buffer address to be gotten
/** */
* @brief Stop ethernet receive uint32_t ETH_GetTxDescBufAddr(ETH_TX_DESC *desc);
* @param None
* @retval None /**
*/ * @brief Set ethernet receive descriptor ring
void ETH_StopRx(void); * @note Make sure that memory occupied by descriptors should be in physical
* memory and keep valid before ethernet receive is finished.
/** * @param[in] ring A pointer to header of ETH_TX_DESC ring, whose last node
* @brief Resume ethernet receive\n * has a 'nextDescAddr' pointed to first node.
* While ethernet doesn't have enough buffer to receive data, it will * @retval BOOL The bit indicates if valid ring is set
* pause and inform users by interrupt 'ETH_INT_RX_BUF_UNAVAI'. Users */
* must call this function to start ethernet again after new buffer BOOL ETH_SetRxDescRing(ETH_RX_DESC *ring);
* prepared.
* @param None /**
* @retval None * @brief Start ethernet receive
*/ * @param None
void ETH_ResumeRx(void); * @retval None
*/
/** void ETH_StartRx(void);
* @brief Get the free descriptor which contains received data\n
* @param None /**
* @retval ETH_RX_DESC* A pointer of free receive descriptor, * @brief Stop ethernet receive
* NULL if no free descriptor * @param None
*/ * @retval None
ETH_RX_DESC *ETH_AcquireFreeRxDesc(void); */
void ETH_StopRx(void);
/**
* @brief Check if a receive descriptor is free or not /**
* @param desc A pointer of a receive descriptor * @brief Resume ethernet receive\n
* @retval BOOL True if the receive descriptor is free, or flase. * While ethernet doesn't have enough buffer to receive data, it will
*/ * pause and inform users by interrupt 'ETH_INT_RX_BUF_UNAVAI'. Users
BOOL ETH_IsFreeRxDesc(ETH_RX_DESC *desc); * must call this function to start ethernet again after new buffer
* prepared.
/** * @param None
* @brief Release a receive descriptor to ethernet\n * @retval None
* After users handled data in the buffer of a free descriptor, */
* They must call this function to change ownership of the void ETH_ResumeRx(void);
* descriptor to hardware.
* @param desc A pointer of a transmission descriptor /**
* @retval None * @brief Get the free descriptor which contains received data\n
*/ * @param None
void ETH_ReleaseRxDesc(ETH_RX_DESC *desc); * @retval ETH_RX_DESC* A pointer of free receive descriptor,
* NULL if no free descriptor
#ifdef __cplusplus */
} ETH_RX_DESC *ETH_AcquireFreeRxDesc(void);
#endif
/**
#endif /* __CMEM7_ETH_H */ * @brief Check if a receive descriptor is free or not
* @param[in] desc A pointer of a receive descriptor
* @retval BOOL True if the receive descriptor is free, or flase.
*/
BOOL ETH_IsFreeRxDesc(ETH_RX_DESC *desc);
/**
* @brief Release a receive descriptor to ethernet\n
* After users handled data in the buffer of a free descriptor,
* They must call this function to change ownership of the
* descriptor to hardware.
* @param[in] desc A pointer of a transmission descriptor
* @retval None
*/
void ETH_ReleaseRxDesc(ETH_RX_DESC *desc);
/**
* @brief Set buffer address of the specific RX descriptor
* @param[in] desc A pointer of a receive descriptor
* @param[in] bufAddr buffer address to be received
* @retval None
*/
void ETH_SetRxDescBufAddr(ETH_RX_DESC *desc, uint32_t bufAddr);
/**
* @brief Get buffer address of the specific RX descriptor
* @param[in] desc A pointer of a receive descriptor
* @retval uint32_t buffer address to be gotten
*/
uint32_t ETH_GetRxDescBufAddr(ETH_RX_DESC *desc);
#ifdef __cplusplus
}
#endif
#endif /* __CMEM7_ETH_H */

@ -200,7 +200,15 @@ void FLASH_Read(uint8_t ReadMode, uint32_t addr, uint16_t size, uint8_t* data);
* @param[out] data A pointer to the data to be written * @param[out] data A pointer to the data to be written
* @retval None * @retval None
*/ */
void FLASH_Write(uint32_t addr, uint16_t size, uint8_t* data); void FLASH_Write(uint32_t addr, uint16_t size, uint8_t* data);
void flash_WaitInWritting(void) ;
void flash_WaitReadFifoNotEmpty(void);
uint16_t flash_ReadFifo(uint16_t size, uint8_t* data) ;
#ifdef __cplusplus #ifdef __cplusplus
} }

@ -139,6 +139,17 @@ void GPIO_InitPwm(uint8_t Channel, uint32_t HighLevelNanoSecond, uint32_t LowLev
* @retval None * @retval None
*/ */
void GPIO_EnablePwm(uint8_t Channel, BOOL Enable); void GPIO_EnablePwm(uint8_t Channel, BOOL Enable);
/**
xjf 20150324
**/
void GPIO_SetBits(uint32_t mask);
void GPIO_clrBits(uint32_t mask);
uint32_t GPIO_getBits(uint32_t mask);
#ifdef __cplusplus #ifdef __cplusplus
} }

@ -101,6 +101,16 @@
#ifdef _WDG #ifdef _WDG
#include "cmem7_wdg.h" #include "cmem7_wdg.h"
#endif #endif
#ifdef _MARVELL
#include <marvel_98dx242.h>
#include <s24g_i2c.h>
#endif
#ifdef _IP1826D
#include <ip1826d_v00.h>
#endif
#ifdef __cplusplus #ifdef __cplusplus
} }

@ -1,236 +1,276 @@
/** /**
***************************************************************************** *****************************************************************************
* @file cmem7_misc.h * @file cmem7_misc.h
* *
* @brief CMEM7 miscellaneous header file * @brief CMEM7 miscellaneous header file
* *
* *
* @version V1.0 * @version V1.0
* @date 3. September 2013 * @date 3. September 2013
* *
* @note * @note
* *
***************************************************************************** *****************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
* *
* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2> * <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
***************************************************************************** *****************************************************************************
*/ */
#ifndef __CMEM7_MISC_H #ifndef __CMEM7_MISC_H
#define __CMEM7_MISC_H #define __CMEM7_MISC_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
#include "cmem7.h" #include "cmem7.h"
#include "cmem7_conf.h" #include "cmem7_conf.h"
/** /**
* @brief NVIC initialization structure * @brief NVIC initialization structure
*/ */
/** /**
@code @code
The table below gives the allowed values of the pre-emption priority and subpriority according The table below gives the allowed values of the pre-emption priority and subpriority according
to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
============================================================================================================================ ============================================================================================================================
NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
============================================================================================================================ ============================================================================================================================
NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority
| | | 4 bits for subpriority | | | 4 bits for subpriority
---------------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------------
NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
| | | 3 bits for subpriority | | | 3 bits for subpriority
---------------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------------
NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
| | | 2 bits for subpriority | | | 2 bits for subpriority
---------------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------------
NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
| | | 1 bits for subpriority | | | 1 bits for subpriority
---------------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------------
NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority
| | | 0 bits for subpriority | | | 0 bits for subpriority
============================================================================================================================ ============================================================================================================================
@endcode @endcode
*/ */
typedef struct typedef struct
{ {
uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
This parameter can be a value of @ref IRQn_Type This parameter can be a value of @ref IRQn_Type
(For the complete Capital-micro Devices IRQ Channels list, please (For the complete Capital-micro Devices IRQ Channels list, please
refer to cmem7.h file) */ refer to cmem7.h file) */
uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
specified in NVIC_IRQChannel. This parameter can be a value specified in NVIC_IRQChannel. This parameter can be a value
between 0 and 15 as described in the table @ref NVIC_Priority_Table */ between 0 and 15 as described in the table @ref NVIC_Priority_Table */
uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
in NVIC_IRQChannel. This parameter can be a value in NVIC_IRQChannel. This parameter can be a value
between 0 and 15 as described in the table @ref NVIC_Priority_Table */ between 0 and 15 as described in the table @ref NVIC_Priority_Table */
BOOL NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel BOOL NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
will be enabled or disabled. will be enabled or disabled.
This parameter can be set either to ENABLE or DISABLE */ This parameter can be set either to ENABLE or DISABLE */
} NVIC_InitTypeDef; } NVIC_InitTypeDef;
/** @defgroup NVIC_VectTab /** @defgroup NVIC_VectTab
* @{ * @{
*/ */
#define NVIC_VectTab_RAM ((uint32_t)0x20000000) #define NVIC_VectTab_CME_CODE ((uint32_t)0x00000000)
#define NVIC_VectTab_FLASH ((uint32_t)0x08000000) #define NVIC_VectTab_RAM ((uint32_t)0x20000000)
#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ #define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
((VECTTAB) == NVIC_VectTab_FLASH)) #define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_CME_CODE) || \
/** ((VECTTAB) == NVIC_VectTab_RAM) || \
* @} ((VECTTAB) == NVIC_VectTab_FLASH))
*/ /**
* @}
/** @defgroup NVIC_LP */
* @{
*/ /** @defgroup NVIC_LP
#define NVIC_LP_SEVONPEND ((uint8_t)0x10) * @{
#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) */
#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) #define NVIC_LP_SEVONPEND ((uint8_t)0x10)
#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ #define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
((LP) == NVIC_LP_SLEEPDEEP) || \ #define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
((LP) == NVIC_LP_SLEEPONEXIT)) #define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
/** ((LP) == NVIC_LP_SLEEPDEEP) || \
* @} ((LP) == NVIC_LP_SLEEPONEXIT))
*/ /**
* @}
/** @defgroup NVIC_PriorityGroup */
* @{
*/ /** @defgroup NVIC_PriorityGroup
#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority * @{
4 bits for subpriority */ */
#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority #define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
3 bits for subpriority */ 4 bits for subpriority */
#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority #define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
2 bits for subpriority */ 3 bits for subpriority */
#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority #define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
1 bits for subpriority */ 2 bits for subpriority */
#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority #define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
0 bits for subpriority */ 1 bits for subpriority */
#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ 0 bits for subpriority */
((GROUP) == NVIC_PriorityGroup_1) || \
((GROUP) == NVIC_PriorityGroup_2) || \ #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
((GROUP) == NVIC_PriorityGroup_3) || \ ((GROUP) == NVIC_PriorityGroup_1) || \
((GROUP) == NVIC_PriorityGroup_4)) ((GROUP) == NVIC_PriorityGroup_2) || \
/** ((GROUP) == NVIC_PriorityGroup_3) || \
* @} ((GROUP) == NVIC_PriorityGroup_4))
*/ /**
* @}
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) */
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
/** #define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
* @brief Configures the priority grouping: pre-emption priority and subpriority.
* @param NVIC_PriorityGroup: specifies the priority grouping bits length. /**
* This parameter can be one of the following values, ref as @ref NVIC_PriorityGroup: * @brief Configures the priority grouping: pre-emption priority and subpriority.
* @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority * @param NVIC_PriorityGroup: specifies the priority grouping bits length.
* 4 bits for subpriority * This parameter can be one of the following values, ref as @ref NVIC_PriorityGroup:
* @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
* 3 bits for subpriority * 4 bits for subpriority
* @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority
* 2 bits for subpriority * 3 bits for subpriority
* @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority
* 1 bits for subpriority * 2 bits for subpriority
* @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority
* 0 bits for subpriority * 1 bits for subpriority
* @retval None * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority
*/ * 0 bits for subpriority
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); * @retval None
*/
/** void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
* @brief Initializes the NVIC peripheral according to the specified
* parameters in the NVIC_InitStruct. /**
* @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains * @brief Initializes the NVIC peripheral according to the specified
* the configuration information for the specified NVIC peripheral. * parameters in the NVIC_InitStruct.
* @retval None * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
*/ * the configuration information for the specified NVIC peripheral.
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); * @retval None
*/
/** void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
* @brief Sets the vector table location and Offset.
* @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory. /**
* This parameter can be one of the following values, ref as @ref NVIC_VectTab: * @brief Sets the vector table location and Offset.
* @arg NVIC_VectTab_RAM * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
* @arg NVIC_VectTab_FLASH * This parameter can be one of the following values, ref as @ref NVIC_VectTab:
* @param Offset: Vector Table base offset field. This value must be a multiple * @arg NVIC_VectTab_RAM
* of 0x200. * @arg NVIC_VectTab_FLASH
* @retval None * @param Offset: Vector Table base offset field. This value must be a multiple
*/ * of 0x200.
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); * @retval None
*/
/** void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
* @brief Selects the condition for the system to enter low power mode.
* @param LowPowerMode: Specifies the new mode for the system to enter low power mode. /**
* This parameter can be one of the following values, ref as @ref NVIC_LP: * @brief Selects the condition for the system to enter low power mode.
* @arg NVIC_LP_SEVONPEND * @param LowPowerMode: Specifies the new mode for the system to enter low power mode.
* @arg NVIC_LP_SLEEPDEEP * This parameter can be one of the following values, ref as @ref NVIC_LP:
* @arg NVIC_LP_SLEEPONEXIT * @arg NVIC_LP_SEVONPEND
* @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE. * @arg NVIC_LP_SLEEPDEEP
* @retval None * @arg NVIC_LP_SLEEPONEXIT
*/ * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
void NVIC_SystemLPConfig(uint8_t LowPowerMode, BOOL NewState); * @retval None
*/
/** void NVIC_SystemLPConfig(uint8_t LowPowerMode, BOOL NewState);
* @brief Memory map from address 'from' to 'address 'to' and open icache or not
* @param[in] from address to be mapped from /**
* @param[in] to address to be mapped to * @brief Memory map from address 'from' to 'address 'to' and open icache or not
* @param[in] isIcacheOn icache is on or off * @param[in] from address to be mapped from
* @retval None * @param[in] to address to be mapped to
*/ * @param[in] isIcacheOn icache is on or off
void GLB_MMAP(uint32_t from, uint32_t to, BOOL isIcacheOn); * @retval None
*/
/** void GLB_MMAP(uint32_t from, uint32_t to, BOOL isIcacheOn);
* @brief Set NMI irq number, it should be one of @ref IRQn_Type.
* @Note You can assign any valid IRQn_Type to NMI. After that, you will enter NMI /**
* interrupt routine if the specific 'irq' occurs. By default, NMI irq number * @brief Convert the mapping destination address to source address
* is 0, same as ETH_INT_IRQn * @param[in] to address to be mapped to
* @param[in] irq irq number * @retval uint32_t address to be mapped from
* @retval None */
*/ uint32_t GLB_ConvertToMappingFromAddr(uint32_t to);
void GLB_SetNmiIrqNum(uint32_t irq);
/**
/** @defgroup SYS_CLK_SEL * @brief Convert the mapping source address to destination address
* @{ * @param[in] from address to be mapped from
*/ * @retval uint32_t address to be mapped to
#define SYS_CLK_SEL_OSC 0x0 */
#define SYS_CLK_SEL_DLL 0x1 uint32_t GLB_ConvertToMappingToAddr(uint32_t from);
#define SYS_CLK_SEL_CRYSTAL 0x2
#define SYS_CLK_SEL_EXTERNAL 0x3 /**
/** * @brief Set NMI irq number, it should be one of @ref IRQn_Type.
* @} * @Note You can assign any valid IRQn_Type to NMI. After that, you will enter NMI
*/ * interrupt routine if the specific 'irq' occurs. By default, NMI irq number
* is 0, same as ETH_INT_IRQn
/** * @param[in] irq irq number
* @brief Select system clock source, it should be one of @ref SYS_CLK_SEL. * @retval None
* @Note You MUST make sure externel clock has been stabled if clock */
* source is external before call this function. void GLB_SetNmiIrqNum(uint32_t irq);
* Default value is SYS_CLK_SEL_OSC
* @param[in] irq irq number /** @defgroup SYS_CLK_SEL
* @retval None * @{
*/ */
void GLB_SelectSysClkSource(uint8_t source); #define SYS_CLK_SEL_OSC 0x0
#define SYS_CLK_SEL_DLL 0x1
#ifdef __cplusplus #define SYS_CLK_SEL_CRYSTAL 0x2
} #define SYS_CLK_SEL_EXTERNAL 0x3
#endif /**
* @}
#endif /* __CMEM7_MISC_H */ */
/**
* @brief Select system clock source, it should be one of @ref SYS_CLK_SEL.
* @Note You MUST make sure externel clock has been stabled if clock
* source is external before call this function.
* Default value is SYS_CLK_SEL_OSC
* @param[in] irq irq number
* @retval None
*/
void GLB_SelectSysClkSource(uint8_t source);
/**
* @brief Simulate instruction 'STRB' or 'STRH' with 'BFI'
* @Note In M7, you have to write a register in 32-bit alignment,
* not in 8-bit or 16-bit.
* @param[in] addr register address to be written
* @param[in] value value to be written
* @param[in] lsb LSB in register to be written
* @param[in] len bit length to be written
* @retval None
*/
//#define aaaa(len) __asm("LDR len, 11")
#define CMEM7_BFI(addr, value, lsb, len) \
do { \
unsigned long tmp; \
unsigned long tmp1 = (unsigned long)addr; \
\
__asm("LDR tmp, [tmp1]\n" \
"BFI tmp, "#value", "#lsb", "#len" \n" \
"STR tmp, [tmp1]\n"); \
} while (0)
#ifdef __cplusplus
}
#endif
#endif /* __CMEM7_MISC_H */

@ -1,89 +1,89 @@
/** /**
***************************************************************************** *****************************************************************************
* @file cmem7_rtc.h * @file cmem7_rtc.h
* *
* @brief CMEM7 RTC header file * @brief CMEM7 RTC header file
* *
* *
* @version V1.0 * @version V1.0
* @date 3. September 2013 * @date 3. September 2013
* *
* @note * @note
* *
***************************************************************************** *****************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
* *
* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2> * <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
***************************************************************************** *****************************************************************************
*/ */
#ifndef __CMEM7_RTC_H #ifndef __CMEM7_RTC_H
#define __CMEM7_RTC_H #define __CMEM7_RTC_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
#include "cmem7.h" #include "cmem7.h"
#include "cmem7_conf.h" #include "cmem7_conf.h"
/** @defgroup RTC_Int /** @defgroup RTC_Int
* @{ * @{
*/ */
#define RTC_Int_Second ((uint32_t)0x00000001) #define RTC_Int_Second ((uint32_t)0x00000001)
#define RTC_Int_Microsecond ((uint32_t)0x00000002) #define RTC_Int_Millsecond ((uint32_t)0x00000002)
#define RTC_Int_All ((uint32_t)0x00000003) #define RTC_Int_All ((uint32_t)0x00000003)
#define IS_RTC_INT(INT) (((INT) != 0) && (((INT) & ~RTC_Int_All) == 0)) #define IS_RTC_INT(INT) (((INT) != 0) && (((INT) & ~RTC_Int_All) == 0))
/** /**
* @} * @}
*/ */
/** /**
* @brief Enable or disable RTC interrupt. * @brief Enable or disable RTC interrupt.
* @param[in] Int interrupt mask bits, which can be the combination of @ref RTC_Int * @param[in] Int interrupt mask bits, which can be the combination of @ref RTC_Int
* @param[in] Enable The bit indicates if specific interrupts are enable or not * @param[in] Enable The bit indicates if specific interrupts are enable or not
* @retval None * @retval None
*/ */
void RTC_EnableInt(uint32_t Int, BOOL Enable); void RTC_ITConfig(uint32_t Int, BOOL Enable);
/** /**
* @brief Check specific interrupts are set or not * @brief Check specific interrupts are set or not
* @param[in] Int interrupt mask bits, which can be the combination of @ref RTC_Int * @param[in] Int interrupt mask bits, which can be the combination of @ref RTC_Int
* @retval BOOL The bit indicates if specific interrupts are set or not * @retval BOOL The bit indicates if specific interrupts are set or not
*/ */
BOOL RTC_GetIntStatus(uint32_t Int); BOOL RTC_GetITStatus(uint32_t Int);
/** /**
* @brief Clear specific interrupts * @brief Clear specific interrupts
* @param[in] Int interrupt mask bits, which can be the combination of @ref RTC_Int * @param[in] Int interrupt mask bits, which can be the combination of @ref RTC_Int
* @retval None * @retval None
*/ */
void RTC_ClearInt(uint32_t Int); void RTC_ClearITPendingBit(uint32_t Int);
/** /**
* @brief Get seconds since power up * @brief Get seconds since power up
* @param None * @param None
* @retval uint32_t Seconds since power up * @retval uint32_t Seconds since power up
*/ */
uint32_t RTC_GetSecond(void); uint32_t RTC_GetSecond(void);
/** /**
* @brief Get current micro-seconds * @brief Get current millseconds
* @param None * @param None
* @retval uint32_t Current micro-seconds * @retval uint32_t Current millseconds
*/ */
uint16_t RTC_GetMicroSecond(void); uint16_t RTC_GetMillSecond(void);
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif /* __CMEM7_RTC_H */ #endif /* __CMEM7_RTC_H */

@ -1,103 +1,110 @@
/** /**
***************************************************************************** *****************************************************************************
* @file cmem7_wdg.h * @file cmem7_wdg.h
* *
* @brief CMEM7 watchdog header file * @brief CMEM7 watchdog header file
* *
* *
* @version V1.0 * @version V1.0
* @date 3. September 2013 * @date 3. September 2013
* *
* @note * @note
* *
***************************************************************************** *****************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
* *
* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2> * <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
***************************************************************************** *****************************************************************************
*/ */
#ifndef __CMEM7_WDG_H #ifndef __CMEM7_WDG_H
#define __CMEM7_WDG_H #define __CMEM7_WDG_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
#include "cmem7.h" #include "cmem7.h"
#include "cmem7_conf.h" #include "cmem7_conf.h"
/** @defgroup WDG_INT /** @defgroup WDG_INT
* @{ * @{
*/ */
#define WDG_INT_QUARTER 0 #define WDG_INT_QUARTER 0
#define WDG_INT_HALF 1 #define WDG_INT_HALF 1
#define IS_WDG_INT(INT) (((INT) == WDG_INT_QUARTER) || \ #define IS_WDG_INT(INT) (((INT) == WDG_INT_QUARTER) || \
((INT) == WDG_INT_HALF)) ((INT) == WDG_INT_HALF))
/** /**
* @} * @}
*/ */
/** @defgroup WDG_TRIGGER_MODE /** @defgroup WDG_TRIGGER_MODE
* @{ * @{
*/ */
#define WDG_TRIGGER_MODE_EDGE 0 #define WDG_TRIGGER_MODE_EDGE 0
#define WDG_TRIGGER_MODE_LEVEL 1 #define WDG_TRIGGER_MODE_LEVEL 1
#define IS_WDG_TRIGGER_MODE(TRI) (((TRI) == WDG_TRIGGER_MODE_EDGE) || \ #define IS_WDG_TRIGGER_MODE(TRI) (((TRI) == WDG_TRIGGER_MODE_EDGE) || \
((TRI) == WDG_TRIGGER_MODE_LEVEL)) ((TRI) == WDG_TRIGGER_MODE_LEVEL))
/** /**
* @} * @}
*/ */
/** /**
* @brief Watchdog initialization * @brief Deinitializes the Watchdog peripheral registers to their default reset values.
* @note This function should be called at first before any other interfaces. * @param[in] None
* @param[in] trigger Watchdog interrupt trigger mode, which is a value of @ref WDG_TRIGGER_MODE * @retval None
* @param[in] ResetMicroSecond MicroSeconds lasts before global reset */
* @retval None void WDG_DeInit(void);
*/
void WDG_Init(uint8_t trigger, uint16_t ResetMicroSecond); /**
* @brief Watchdog initialization
/** * @note This function should be called at first before any other interfaces.
* @brief Enable or disable watchdog interrupt. * @param[in] trigger Watchdog interrupt trigger mode, which is a value of @ref WDG_TRIGGER_MODE
* @param[in] Int interrupt mask bits, which is a value of @ref WDG_INT * @param[in] ResetMillSecond MillSeconds lasts before global reset
* @param[in] Enable The bit indicates if the specific interrupt are enable or not * @retval None
* @retval None */
*/ void WDG_Init(uint8_t trigger, uint16_t ResetMillSecond);
void WDG_EnableInt(uint8_t Int, BOOL Enable);
/**
/** * @brief Enable or disable watchdog interrupt.
* @brief Check the specific interrupt are set or not * @param[in] Int interrupt mask bits, which is a value of @ref WDG_INT
* @param None * @param[in] Enable The bit indicates if the specific interrupt are enable or not
* @retval BOOL The bit indicates if the specific interrupt are set or not * @retval None
*/ */
BOOL WDG_GetIntStatus(void); void WDG_ITConfig(uint8_t Int, BOOL Enable);
/** /**
* @brief Clear the specific interrupt * @brief Check the specific interrupt are set or not
* @param None * @param None
* @retval None * @retval BOOL The bit indicates if the specific interrupt are set or not
*/ */
void WDG_ClearInt(void); BOOL WDG_GetITStatus(void);
/** /**
* @brief Enable or disable watchdog. * @brief Clear the specific interrupt
* @param[in] Enable The bit indicates if watchdog is enable or not * @param None
* @retval None * @retval None
*/ */
void WDG_Enable(BOOL Enable); void WDG_ClearITPendingBit(void);
/**
#ifdef __cplusplus * @brief Enable or disable watchdog.
} * @param[in] Enable The bit indicates if watchdog is enable or not
#endif * @retval None
*/
#endif /* __CMEM7_WDG_H */ void WDG_Cmd(BOOL Enable);
#ifdef __cplusplus
}
#endif
#endif /* __CMEM7_WDG_H */