diff --git a/libcpu/arm/am335x/mmu.c b/libcpu/arm/am335x/mmu.c
index d3e505e76a..bec934ef1d 100644
--- a/libcpu/arm/am335x/mmu.c
+++ b/libcpu/arm/am335x/mmu.c
@@ -48,13 +48,13 @@ void mmu_setttbase(rt_uint32_t i)
     * set by page table entry
     */
 	value = 0;
-    __asm
+    __asm volatile
     {
         mcr p15, 0, value, c8, c7, 0
 	}
 
 	value = 0x55555555;
-	__asm
+	__asm volatile
 	{
         mcr p15, 0, value, c3, c0, 0
         mcr p15, 0, i, c2, c0, 0
@@ -63,7 +63,7 @@ void mmu_setttbase(rt_uint32_t i)
 
 void mmu_set_domain(rt_uint32_t i)
 {
-    __asm
+    __asm volatile
     {
         mcr p15,0, i, c3, c0,  0
     }
@@ -73,7 +73,7 @@ void mmu_enable()
 {
     register rt_uint32_t value;
 
-    __asm
+    __asm volatile
     {
         mrc p15, 0, value, c1, c0, 0
         orr value, value, #0x01
@@ -85,7 +85,7 @@ void mmu_disable()
 {
     register rt_uint32_t value;
 
-    __asm
+    __asm volatile
     {
         mrc p15, 0, value, c1, c0, 0
         bic value, value, #0x01
@@ -97,7 +97,7 @@ void mmu_enable_icache()
 {
     register rt_uint32_t value;
 
-    __asm
+    __asm volatile
     {
         mrc p15, 0, value, c1, c0, 0
         orr value, value, #0x1000
@@ -109,7 +109,7 @@ void mmu_enable_dcache()
 {
     register rt_uint32_t value;
 
-    __asm
+    __asm volatile
     {
         mrc p15, 0, value, c1, c0, 0
         orr value, value, #0x04
@@ -121,7 +121,7 @@ void mmu_disable_icache()
 {
     register rt_uint32_t value;
 
-    __asm
+    __asm volatile
     {
         mrc p15, 0, value, c1, c0, 0
         bic value, value, #0x1000
@@ -133,7 +133,7 @@ void mmu_disable_dcache()
 {
     register rt_uint32_t value;
 
-    __asm
+    __asm volatile
     {
         mrc p15, 0, value, c1, c0, 0
         bic value, value, #0x04
@@ -145,7 +145,7 @@ void mmu_enable_alignfault()
 {
     register rt_uint32_t value;
 
-    __asm
+    __asm volatile
     {
         mrc p15, 0, value, c1, c0, 0
         orr value, value, #0x02
@@ -157,7 +157,7 @@ void mmu_disable_alignfault()
 {
     register rt_uint32_t value;
 
-    __asm
+    __asm volatile
     {
         mrc p15, 0, value, c1, c0, 0
         bic value, value, #0x02
@@ -167,7 +167,7 @@ void mmu_disable_alignfault()
 
 void mmu_clean_invalidated_cache_index(int index)
 {
-    __asm
+    __asm volatile
     {
         mcr p15, 0, index, c7, c14, 2
     }
@@ -181,7 +181,7 @@ void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size)
 
     while(ptr < buffer + size)
     {
-    	__asm
+    	__asm volatile
     	{
     		MCR p15, 0, ptr, c7, c14, 1
     	}
@@ -197,7 +197,7 @@ void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size)
 
 	while (ptr < buffer + size)
 	{
-		__asm
+		__asm volatile
 		{
 			MCR p15, 0, ptr, c7, c10, 1
 		}
@@ -213,7 +213,7 @@ void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size)
 
 	while (ptr < buffer + size)
 	{
-		__asm
+		__asm volatile
 		{
 			MCR p15, 0, ptr, c7, c6, 1
 		}
@@ -226,7 +226,7 @@ void mmu_invalidate_tlb()
     register rt_uint32_t value;
 
     value = 0;
-    __asm
+    __asm volatile
     {
         mcr p15, 0, value, c8, c7, 0
     }
@@ -238,7 +238,7 @@ void mmu_invalidate_icache()
 
     value = 0;
 
-    __asm
+    __asm volatile
     {
         mcr p15, 0, value, c7, c5, 0
     }
@@ -255,16 +255,16 @@ void mmu_setttbase(register rt_uint32_t i)
     * set by page table entry
     */
 	value = 0;
-	asm ("mcr p15, 0, %0, c8, c7, 0"::"r"(value));
+	asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value));
 
 	value = 0x55555555;
-	asm ("mcr p15, 0, %0, c3, c0, 0"::"r"(value));
-	asm ("mcr p15, 0, %0, c2, c0, 0"::"r"(i));
+	asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value));
+	asm volatile ("mcr p15, 0, %0, c2, c0, 0"::"r"(i));
 }
 
 void mmu_set_domain(register rt_uint32_t i)
 {
-	asm ("mcr p15,0, %0, c3, c0,  0": :"r" (i));
+	asm volatile ("mcr p15,0, %0, c3, c0,  0": :"r" (i));
 }
 
 void mmu_enable()
@@ -272,12 +272,12 @@ void mmu_enable()
 	register rt_uint32_t i;
 
 	/* read control register */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
 	i |= 0x1;
 
 	/* write back to control register */
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_disable()
@@ -285,12 +285,12 @@ void mmu_disable()
 	register rt_uint32_t i;
 
 	/* read control register */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
 	i &= ~0x1;
 
 	/* write back to control register */
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_enable_icache()
@@ -298,12 +298,12 @@ void mmu_enable_icache()
 	register rt_uint32_t i;
 
 	/* read control register */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
 	i |= (1 << 12);
 
 	/* write back to control register */
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_enable_dcache()
@@ -311,12 +311,12 @@ void mmu_enable_dcache()
 	register rt_uint32_t i;
 
 	/* read control register */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
 	i |= (1 << 2);
 
 	/* write back to control register */
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_disable_icache()
@@ -324,12 +324,12 @@ void mmu_disable_icache()
 	register rt_uint32_t i;
 
 	/* read control register */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
 	i &= ~(1 << 12);
 
 	/* write back to control register */
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_disable_dcache()
@@ -337,12 +337,12 @@ void mmu_disable_dcache()
 	register rt_uint32_t i;
 
 	/* read control register */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
 	i &= ~(1 << 2);
 
 	/* write back to control register */
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_enable_alignfault()
@@ -350,12 +350,12 @@ void mmu_enable_alignfault()
 	register rt_uint32_t i;
 
 	/* read control register */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
 	i |= (1 << 1);
 
 	/* write back to control register */
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_disable_alignfault()
@@ -363,17 +363,17 @@ void mmu_disable_alignfault()
 	register rt_uint32_t i;
 
 	/* read control register */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
 	i &= ~(1 << 1);
 
 	/* write back to control register */
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_clean_invalidated_cache_index(int index)
 {
-	asm ("mcr p15, 0, %0, c7, c14, 2": :"r" (index));
+	asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index));
 }
 
 void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size)
@@ -384,7 +384,7 @@ void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size)
 
 	while (ptr < buffer + size)
 	{
-		asm ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr));
+		asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr));
 		ptr += 32;
 	}
 }
@@ -397,19 +397,19 @@ void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size)
 
 	while (ptr < buffer + size)
 	{
-		asm ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr));
+		asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr));
 		ptr += 32;
 	}
 }
 
 void mmu_invalidate_tlb()
 {
-	asm ("mcr p15, 0, %0, c8, c7, 0": :"r" (0));
+	asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0));
 }
 
 void mmu_invalidate_icache()
 {
-	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
+	asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
 }
 #endif
 
diff --git a/libcpu/arm/armv6/mmu.c b/libcpu/arm/armv6/mmu.c
index 9a6ebd4e6f..2d47e999ce 100644
--- a/libcpu/arm/armv6/mmu.c
+++ b/libcpu/arm/armv6/mmu.c
@@ -34,13 +34,13 @@ void mmu_setttbase(rt_uint32_t i)
 	 * set by page table entry
 	 */
 	value = 0;
-	__asm
+	__asm volatile
 	{
 		mcr p15, 0, value, c8, c7, 0
 	}
 
 	value = 0x55555555;
-	__asm
+	__asm volatile
 	{
 		mcr p15, 0, value, c3, c0, 0
 			mcr p15, 0, i, c2, c0, 0
@@ -49,7 +49,7 @@ void mmu_setttbase(rt_uint32_t i)
 
 void mmu_set_domain(rt_uint32_t i)
 {
-	__asm
+	__asm volatile
 	{
 		mcr p15,0, i, c3, c0,  0
 	}
@@ -59,7 +59,7 @@ void mmu_enable()
 {
 	register rt_uint32_t value;
 
-	__asm
+	__asm volatile
 	{
 		mrc p15, 0, value, c1, c0, 0
 			orr value, value, #0x01
@@ -71,7 +71,7 @@ void mmu_disable()
 {
 	register rt_uint32_t value;
 
-	__asm
+	__asm volatile
 	{
 		mrc p15, 0, value, c1, c0, 0
 			bic value, value, #0x01
@@ -83,7 +83,7 @@ void mmu_enable_icache()
 {
 	register rt_uint32_t value;
 
-	__asm
+	__asm volatile
 	{
 		mrc p15, 0, value, c1, c0, 0
 			orr value, value, #0x1000
@@ -95,7 +95,7 @@ void mmu_enable_dcache()
 {
 	register rt_uint32_t value;
 
-	__asm
+	__asm volatile
 	{
 		mrc p15, 0, value, c1, c0, 0
 			orr value, value, #0x04
@@ -107,7 +107,7 @@ void mmu_disable_icache()
 {
 	register rt_uint32_t value;
 
-	__asm
+	__asm volatile
 	{
 		mrc p15, 0, value, c1, c0, 0
 			bic value, value, #0x1000
@@ -119,7 +119,7 @@ void mmu_disable_dcache()
 {
 	register rt_uint32_t value;
 
-	__asm
+	__asm volatile
 	{
 		mrc p15, 0, value, c1, c0, 0
 			bic value, value, #0x04
@@ -131,7 +131,7 @@ void mmu_enable_alignfault()
 {
 	register rt_uint32_t value;
 
-	__asm
+	__asm volatile
 	{
 		mrc p15, 0, value, c1, c0, 0
 			orr value, value, #0x02
@@ -143,7 +143,7 @@ void mmu_disable_alignfault()
 {
 	register rt_uint32_t value;
 
-	__asm
+	__asm volatile
 	{
 		mrc p15, 0, value, c1, c0, 0
 			bic value, value, #0x02
@@ -153,7 +153,7 @@ void mmu_disable_alignfault()
 
 void mmu_clean_invalidated_cache_index(int index)
 {
-	__asm
+	__asm volatile
 	{
 		mcr p15, 0, index, c7, c14, 2
 	}
@@ -167,7 +167,7 @@ void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size)
 
 	while(ptr < buffer + size)
 	{
-		__asm
+		__asm volatile
 		{
 			MCR p15, 0, ptr, c7, c14, 1
 		}
@@ -183,7 +183,7 @@ void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size)
 
 	while (ptr < buffer + size)
 	{
-		__asm
+		__asm volatile
 		{
 			MCR p15, 0, ptr, c7, c10, 1
 		}
@@ -199,7 +199,7 @@ void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size)
 
 	while (ptr < buffer + size)
 	{
-		__asm
+		__asm volatile
 		{
 			MCR p15, 0, ptr, c7, c6, 1
 		}
@@ -212,7 +212,7 @@ void mmu_invalidate_tlb()
 	register rt_uint32_t value;
 
 	value = 0;
-	__asm
+	__asm volatile
 	{
 		mcr p15, 0, value, c8, c7, 0
 	}
@@ -224,7 +224,7 @@ void mmu_invalidate_icache()
 
 	value = 0;
 
-	__asm
+	__asm volatile
 	{
 		mcr p15, 0, value, c7, c5, 0
 	}
@@ -237,7 +237,7 @@ void mmu_invalidate_dcache_all()
 
 	value = 0;
 
-	__asm
+	__asm volatile
 	{
 		mcr p15, 0, value, c7, c6, 0
 	}
@@ -253,16 +253,16 @@ void mmu_setttbase(register rt_uint32_t i)
 	 * set by page table entry
 	 */
 	value = 0;
-	asm ("mcr p15, 0, %0, c8, c7, 0"::"r"(value));
+	asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value));
 
 	value = 0x55555555;
-	asm ("mcr p15, 0, %0, c3, c0, 0"::"r"(value));
-	asm ("mcr p15, 0, %0, c2, c0, 0"::"r"(i));
+	asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value));
+	asm volatile ("mcr p15, 0, %0, c2, c0, 0"::"r"(i));
 }
 
 void mmu_set_domain(register rt_uint32_t i)
 {
-	asm ("mcr p15,0, %0, c3, c0,  0": :"r" (i));
+	asm volatile ("mcr p15,0, %0, c3, c0,  0": :"r" (i));
 }
 
 void mmu_enable()
@@ -270,7 +270,7 @@ void mmu_enable()
 	register rt_uint32_t i;
 
 	/* read control register */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
 	i |= 0x1;
 	/* Enables the extended page tables to be configured for
@@ -279,7 +279,7 @@ void mmu_enable()
 	i |= (1 << 13); /* High exception vectors selected, address range = 0xFFFF0000-0xFFFF001C */
 
 	/* write back to control register */
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_disable()
@@ -287,12 +287,12 @@ void mmu_disable()
 	register rt_uint32_t i;
 
 	/* read control register */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
 	i &= ~0x1;
 
 	/* write back to control register */
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_enable_icache()
@@ -300,12 +300,12 @@ void mmu_enable_icache()
 	register rt_uint32_t i;
 
 	/* read control register */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
 	i |= (1 << 12);
 
 	/* write back to control register */
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_enable_dcache()
@@ -313,12 +313,12 @@ void mmu_enable_dcache()
 	register rt_uint32_t i;
 
 	/* read control register */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
 	i |= (1 << 2);
 
 	/* write back to control register */
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_disable_icache()
@@ -326,12 +326,12 @@ void mmu_disable_icache()
 	register rt_uint32_t i;
 
 	/* read control register */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
 	i &= ~(1 << 12);
 
 	/* write back to control register */
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_disable_dcache()
@@ -339,12 +339,12 @@ void mmu_disable_dcache()
 	register rt_uint32_t i;
 
 	/* read control register */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
 	i &= ~(1 << 2);
 
 	/* write back to control register */
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_enable_alignfault()
@@ -352,12 +352,12 @@ void mmu_enable_alignfault()
 	register rt_uint32_t i;
 
 	/* read control register */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
 	i |= (1 << 1);
 
 	/* write back to control register */
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_disable_alignfault()
@@ -365,17 +365,17 @@ void mmu_disable_alignfault()
 	register rt_uint32_t i;
 
 	/* read control register */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
 	i &= ~(1 << 1);
 
 	/* write back to control register */
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_clean_invalidated_cache_index(int index)
 {
-	asm ("mcr p15, 0, %0, c7, c14, 2": :"r" (index));
+	asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index));
 }
 
 void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size)
@@ -386,7 +386,7 @@ void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size)
 
 	while(ptr < buffer + size)
 	{
-		asm ("mcr p15, 0, %0, c7, c14, 1": :"r" (ptr));
+		asm volatile ("mcr p15, 0, %0, c7, c14, 1": :"r" (ptr));
 		ptr += CACHE_LINE_SIZE;
 	}
 }
@@ -400,7 +400,7 @@ void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size)
 
 	while (ptr < buffer + size)
 	{
-		asm ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr));
+		asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr));
 		ptr += CACHE_LINE_SIZE;
 	}
 }
@@ -413,24 +413,24 @@ void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size)
 
 	while (ptr < buffer + size)
 	{
-		asm ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr));
+		asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr));
 		ptr += CACHE_LINE_SIZE;
 	}
 }
 
 void mmu_invalidate_tlb()
 {
-	asm ("mcr p15, 0, %0, c8, c7, 0": :"r" (0));
+	asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0));
 }
 
 void mmu_invalidate_icache()
 {
-	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
+	asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
 }
 
 void mmu_invalidate_dcache_all()
 {
-	asm ("mcr p15, 0, %0, c7, c6, 0": :"r" (0));
+	asm volatile ("mcr p15, 0, %0, c7, c6, 0": :"r" (0));
 }
 #endif
 
diff --git a/libcpu/arm/dm36x/mmu.c b/libcpu/arm/dm36x/mmu.c
index 643f6bc3de..8c3100659c 100644
--- a/libcpu/arm/dm36x/mmu.c
+++ b/libcpu/arm/dm36x/mmu.c
@@ -34,13 +34,13 @@ void mmu_setttbase(rt_uint32_t i)
     * set by page table entry
     */
 	value = 0;
-    __asm
+    __asm volatile
     {
         mcr p15, 0, value, c8, c7, 0
 	}
 
 	value = 0x55555555;
-	__asm
+	__asm volatile
 	{
         mcr p15, 0, value, c3, c0, 0
         mcr p15, 0, i, c2, c0, 0
@@ -49,7 +49,7 @@ void mmu_setttbase(rt_uint32_t i)
 
 void mmu_set_domain(rt_uint32_t i)
 {
-    __asm
+    __asm volatile
     {
         mcr p15,0, i, c3, c0,  0
     }
@@ -59,7 +59,7 @@ void mmu_enable()
 {
     register rt_uint32_t value;
 
-    __asm
+    __asm volatile
     {
         mrc p15, 0, value, c1, c0, 0
         orr value, value, #0x01
@@ -71,7 +71,7 @@ void mmu_disable()
 {
     register rt_uint32_t value;
 
-    __asm
+    __asm volatile
     {
         mrc p15, 0, value, c1, c0, 0
         bic value, value, #0x01
@@ -83,7 +83,7 @@ void mmu_enable_icache()
 {
     register rt_uint32_t value;
 
-    __asm
+    __asm volatile
     {
         mrc p15, 0, value, c1, c0, 0
         orr value, value, #0x1000
@@ -95,7 +95,7 @@ void mmu_enable_dcache()
 {
     register rt_uint32_t value;
 
-    __asm
+    __asm volatile
     {
         mrc p15, 0, value, c1, c0, 0
         orr value, value, #0x04
@@ -107,7 +107,7 @@ void mmu_disable_icache()
 {
     register rt_uint32_t value;
 
-    __asm
+    __asm volatile
     {
         mrc p15, 0, value, c1, c0, 0
         bic value, value, #0x1000
@@ -119,7 +119,7 @@ void mmu_disable_dcache()
 {
     register rt_uint32_t value;
 
-    __asm
+    __asm volatile
     {
         mrc p15, 0, value, c1, c0, 0
         bic value, value, #0x04
@@ -131,7 +131,7 @@ void mmu_enable_alignfault()
 {
     register rt_uint32_t value;
 
-    __asm
+    __asm volatile
     {
         mrc p15, 0, value, c1, c0, 0
         orr value, value, #0x02
@@ -143,7 +143,7 @@ void mmu_disable_alignfault()
 {
     register rt_uint32_t value;
 
-    __asm
+    __asm volatile
     {
         mrc p15, 0, value, c1, c0, 0
         bic value, value, #0x02
@@ -153,7 +153,7 @@ void mmu_disable_alignfault()
 
 void mmu_clean_invalidated_cache_index(int index)
 {
-    __asm
+    __asm volatile
     {
         mcr p15, 0, index, c7, c14, 2
     }
@@ -167,7 +167,7 @@ void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size)
 
     while(ptr < buffer + size)
     {
-    	__asm
+    	__asm volatile
     	{
     		MCR p15, 0, ptr, c7, c14, 1
     	}
@@ -183,7 +183,7 @@ void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size)
 
 	while (ptr < buffer + size)
 	{
-		__asm
+		__asm volatile
 		{
 			MCR p15, 0, ptr, c7, c10, 1
 		}
@@ -199,7 +199,7 @@ void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size)
 
 	while (ptr < buffer + size)
 	{
-		__asm
+		__asm volatile
 		{
 			MCR p15, 0, ptr, c7, c6, 1
 		}
@@ -212,7 +212,7 @@ void mmu_invalidate_tlb()
     register rt_uint32_t value;
 
     value = 0;
-    __asm
+    __asm volatile
     {
         mcr p15, 0, value, c8, c7, 0
     }
@@ -224,7 +224,7 @@ void mmu_invalidate_icache()
 
     value = 0;
 
-    __asm
+    __asm volatile
     {
         mcr p15, 0, value, c7, c5, 0
     }
@@ -237,7 +237,7 @@ void mmu_invalidate_dcache_all()
 
     value = 0;
 
-    __asm
+    __asm volatile
     {
         mcr p15, 0, value, c7, c6, 0
     }
@@ -253,16 +253,16 @@ void mmu_setttbase(register rt_uint32_t i)
     * set by page table entry
     */
 	value = 0;
-	asm ("mcr p15, 0, %0, c8, c7, 0"::"r"(value));
+	asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value));
 
 	value = 0x55555555;
-	asm ("mcr p15, 0, %0, c3, c0, 0"::"r"(value));
-	asm ("mcr p15, 0, %0, c2, c0, 0"::"r"(i));
+	asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value));
+	asm volatile ("mcr p15, 0, %0, c2, c0, 0"::"r"(i));
 }
 
 void mmu_set_domain(register rt_uint32_t i)
 {
-	asm ("mcr p15,0, %0, c3, c0,  0": :"r" (i));
+	asm volatile ("mcr p15,0, %0, c3, c0,  0": :"r" (i));
 }
 
 void mmu_enable()
@@ -270,7 +270,7 @@ void mmu_enable()
 	register rt_uint32_t i;
 
 	/* read control register */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
 	i |= 0x1;
 	i |= (1 << 13); /* High exception vectors selected, address range = 0xFFFF0000-0xFFFF001C */
@@ -279,7 +279,7 @@ void mmu_enable()
 	i &= ~(1 << 9);
 
 	/* write back to control register */
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_disable()
@@ -287,12 +287,12 @@ void mmu_disable()
 	register rt_uint32_t i;
 
 	/* read control register */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
 	i &= ~0x1;
 
 	/* write back to control register */
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_enable_icache()
@@ -300,12 +300,12 @@ void mmu_enable_icache()
 	register rt_uint32_t i;
 
 	/* read control register */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
 	i |= (1 << 12);
 
 	/* write back to control register */
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_enable_dcache()
@@ -313,12 +313,12 @@ void mmu_enable_dcache()
 	register rt_uint32_t i;
 
 	/* read control register */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
 	i |= (1 << 2);
 
 	/* write back to control register */
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_disable_icache()
@@ -326,12 +326,12 @@ void mmu_disable_icache()
 	register rt_uint32_t i;
 
 	/* read control register */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
 	i &= ~(1 << 12);
 
 	/* write back to control register */
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_disable_dcache()
@@ -339,12 +339,12 @@ void mmu_disable_dcache()
 	register rt_uint32_t i;
 
 	/* read control register */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
 	i &= ~(1 << 2);
 
 	/* write back to control register */
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_enable_alignfault()
@@ -352,12 +352,12 @@ void mmu_enable_alignfault()
 	register rt_uint32_t i;
 
 	/* read control register */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
 	i |= (1 << 1);
 
 	/* write back to control register */
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_disable_alignfault()
@@ -365,17 +365,17 @@ void mmu_disable_alignfault()
 	register rt_uint32_t i;
 
 	/* read control register */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
 	i &= ~(1 << 1);
 
 	/* write back to control register */
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_clean_invalidated_cache_index(int index)
 {
-	asm ("mcr p15, 0, %0, c7, c14, 2": :"r" (index));
+	asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index));
 }
 
 void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size)
@@ -386,7 +386,7 @@ void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size)
 
     while(ptr < buffer + size)
     {
-    	asm ("mcr p15, 0, %0, c7, c14, 1": :"r" (ptr));
+    	asm volatile ("mcr p15, 0, %0, c7, c14, 1": :"r" (ptr));
         ptr += CACHE_LINE_SIZE;
     }
 }
@@ -400,7 +400,7 @@ void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size)
 
 	while (ptr < buffer + size)
 	{
-		asm ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr));
+		asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr));
 		ptr += CACHE_LINE_SIZE;
 	}
 }
@@ -413,24 +413,24 @@ void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size)
 
 	while (ptr < buffer + size)
 	{
-		asm ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr));
+		asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr));
 		ptr += CACHE_LINE_SIZE;
 	}
 }
 
 void mmu_invalidate_tlb()
 {
-	asm ("mcr p15, 0, %0, c8, c7, 0": :"r" (0));
+	asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0));
 }
 
 void mmu_invalidate_icache()
 {
-	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
+	asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
 }
 
 void mmu_invalidate_dcache_all()
 {
-    asm ("mcr p15, 0, %0, c7, c6, 0": :"r" (0));
+    asm volatile ("mcr p15, 0, %0, c7, c6, 0": :"r" (0));
 }
 #endif
 
diff --git a/libcpu/arm/s3c24x0/mmu.c b/libcpu/arm/s3c24x0/mmu.c
index 2bc79deca6..662ec3d50a 100644
--- a/libcpu/arm/s3c24x0/mmu.c
+++ b/libcpu/arm/s3c24x0/mmu.c
@@ -43,12 +43,12 @@
 #ifdef __GNUC__
 void mmu_setttbase(register rt_uint32_t i)
 {
-	asm ("mcr p15, 0, %0, c2, c0, 0": :"r" (i));
+	asm volatile ("mcr p15, 0, %0, c2, c0, 0": :"r" (i));
 }
 
 void mmu_set_domain(register rt_uint32_t i)
 {
-	asm ("mcr p15,0, %0, c3, c0,  0": :"r" (i));
+	asm volatile ("mcr p15,0, %0, c3, c0,  0": :"r" (i));
 }
 
 void mmu_enable()
@@ -56,12 +56,12 @@ void mmu_enable()
 	register rt_uint32_t i;
 
 	/* read control register */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
 	i |= 0x1;
 
 	/* write back to control register */
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_disable()
@@ -69,12 +69,12 @@ void mmu_disable()
 	register rt_uint32_t i;
 
 	/* read control register */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
 	i &= ~0x1;
 
 	/* write back to control register */
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_enable_icache()
@@ -82,12 +82,12 @@ void mmu_enable_icache()
 	register rt_uint32_t i;
 
 	/* read control register */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
 	i |= (1 << 12);
 
 	/* write back to control register */
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_enable_dcache()
@@ -95,12 +95,12 @@ void mmu_enable_dcache()
 	register rt_uint32_t i;
 
 	/* read control register */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
 	i |= (1 << 2);
 
 	/* write back to control register */
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_disable_icache()
@@ -108,12 +108,12 @@ void mmu_disable_icache()
 	register rt_uint32_t i;
 
 	/* read control register */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
 	i &= ~(1 << 12);
 
 	/* write back to control register */
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_disable_dcache()
@@ -121,12 +121,12 @@ void mmu_disable_dcache()
 	register rt_uint32_t i;
 
 	/* read control register */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
 	i &= ~(1 << 2);
 
 	/* write back to control register */
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_enable_alignfault()
@@ -134,12 +134,12 @@ void mmu_enable_alignfault()
 	register rt_uint32_t i;
 
 	/* read control register */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
 	i |= (1 << 1);
 
 	/* write back to control register */
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_disable_alignfault()
@@ -147,34 +147,34 @@ void mmu_disable_alignfault()
 	register rt_uint32_t i;
 
 	/* read control register */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
 	i &= ~(1 << 1);
 
 	/* write back to control register */
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_clean_invalidated_cache_index(int index)
 {
-	asm ("mcr p15, 0, %0, c7, c14, 2": :"r" (index));
+	asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index));
 }
 
 void mmu_invalidate_tlb()
 {
-	asm ("mcr p15, 0, %0, c8, c7, 0": :"r" (0));
+	asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0));
 }
 
 void mmu_invalidate_icache()
 {
-	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
+	asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
 }
 #endif
 
 #ifdef __CC_ARM
 void mmu_setttbase(rt_uint32_t i)
 {
-    __asm
+    __asm volatile
     {
         mcr p15, 0, i, c2, c0, 0
     }
@@ -182,7 +182,7 @@ void mmu_setttbase(rt_uint32_t i)
 
 void mmu_set_domain(rt_uint32_t i)
 {
-    __asm
+    __asm volatile
     {
         mcr p15,0, i, c3, c0,  0
     }
@@ -192,7 +192,7 @@ void mmu_enable()
 {
     register rt_uint32_t value;
 
-    __asm
+    __asm volatile
     {
         mrc p15, 0, value, c1, c0, 0
         orr value, value, #0x01
@@ -204,7 +204,7 @@ void mmu_disable()
 {
     register rt_uint32_t value;
 
-    __asm
+    __asm volatile
     {
         mrc p15, 0, value, c1, c0, 0
         bic value, value, #0x01
@@ -216,7 +216,7 @@ void mmu_enable_icache()
 {
     register rt_uint32_t value;
 
-    __asm
+    __asm volatile
     {
         mrc p15, 0, value, c1, c0, 0
         orr value, value, #0x1000
@@ -228,7 +228,7 @@ void mmu_enable_dcache()
 {
     register rt_uint32_t value;
 
-    __asm
+    __asm volatile
     {
         mrc p15, 0, value, c1, c0, 0
         orr value, value, #0x04
@@ -240,7 +240,7 @@ void mmu_disable_icache()
 {
     register rt_uint32_t value;
 
-    __asm
+    __asm volatile
     {
         mrc p15, 0, value, c1, c0, 0
         bic value, value, #0x1000
@@ -252,7 +252,7 @@ void mmu_disable_dcache()
 {
     register rt_uint32_t value;
 
-    __asm
+    __asm volatile
     {
         mrc p15, 0, value, c1, c0, 0
         bic value, value, #0x04
@@ -264,7 +264,7 @@ void mmu_enable_alignfault()
 {
     register rt_uint32_t value;
 
-    __asm
+    __asm volatile
     {
         mrc p15, 0, value, c1, c0, 0
         orr value, value, #0x02
@@ -276,7 +276,7 @@ void mmu_disable_alignfault()
 {
     register rt_uint32_t value;
 
-    __asm
+    __asm volatile
     {
         mrc p15, 0, value, c1, c0, 0
         bic value, value, #0x02
@@ -286,7 +286,7 @@ void mmu_disable_alignfault()
 
 void mmu_clean_invalidated_cache_index(int index)
 {
-    __asm
+    __asm volatile
     {
         mcr p15, 0, index, c7, c14, 2
     }
@@ -297,7 +297,7 @@ void mmu_invalidate_tlb()
     register rt_uint32_t value;
 
     value = 0;
-    __asm
+    __asm volatile
     {
         mcr p15, 0, value, c8, c7, 0
     }
@@ -309,7 +309,7 @@ void mmu_invalidate_icache()
 
     value = 0;
 
-    __asm
+    __asm volatile
     {
         mcr p15, 0, value, c7, c5, 0
     }