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update libcpu/arm/cortex-m0: restore MSP.

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aozima 2013-06-18 11:34:54 +08:00
parent 4d421cad73
commit a2ff85c03f
3 changed files with 27 additions and 0 deletions
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9
libcpu/arm/cortex-m0/context_gcc.S
View File

@ -13,6 +13,7 @@
* 2012-06-01 aozima set pendsv priority to 0xFF. * 2012-06-01 aozima set pendsv priority to 0xFF.
* 2012-08-17 aozima fixed bug: store r8 - r11. * 2012-08-17 aozima fixed bug: store r8 - r11.
* 2013-02-20 aozima port to gcc. * 2013-02-20 aozima port to gcc.
* 2013-06-18 aozima add restore MSP feature.
*/ */
.cpu cortex-m3 .cpu cortex-m3
@ -21,6 +22,7 @@
.thumb .thumb
.text .text
.equ SCB_VTOR, 0xE000ED04 /* Vector Table Offset Register */
.equ ICSR, 0xE000ED04 /* interrupt control state register */ .equ ICSR, 0xE000ED04 /* interrupt control state register */
.equ PENDSVSET_BIT, 0x10000000 /* value to trigger PendSV exception */ .equ PENDSVSET_BIT, 0x10000000 /* value to trigger PendSV exception */
@ -152,6 +154,13 @@ rt_hw_context_switch_to:
LDR R1, =PENDSVSET_BIT LDR R1, =PENDSVSET_BIT
STR R1, [R0] STR R1, [R0]
/* restore MSP */
LDR r0, =SCB_VTOR
LDR r0, [r0]
LDR r0, [r0]
NOP
MSR msp, r0
CPSIE I /* enable interrupts at processor level */ CPSIE I /* enable interrupts at processor level */
/* never reach here! */ /* never reach here! */

9
libcpu/arm/cortex-m0/context_iar.S
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@ -12,6 +12,7 @@
; * 2010-01-25 Bernard first version ; * 2010-01-25 Bernard first version
; * 2012-06-01 aozima set pendsv priority to 0xFF. ; * 2012-06-01 aozima set pendsv priority to 0xFF.
; * 2012-08-17 aozima fixed bug: store r8 - r11. ; * 2012-08-17 aozima fixed bug: store r8 - r11.
; * 2013-06-18 aozima add restore MSP feature.
; */ ; */
;/** ;/**
@ -19,6 +20,7 @@
; */ ; */
;/*@{*/ ;/*@{*/
SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register
NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
NVIC_SHPR3 EQU 0xE000ED20 ; system priority register (2) NVIC_SHPR3 EQU 0xE000ED20 ; system priority register (2)
NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest)
@ -178,6 +180,13 @@ rt_hw_context_switch_to:
STR r1, [r0] STR r1, [r0]
NOP NOP
; restore MSP
LDR r0, =SCB_VTOR
LDR r0, [r0]
LDR r0, [r0]
NOP
MSR msp, r0
; enable interrupts at processor level ; enable interrupts at processor level
CPSIE I CPSIE I

9
libcpu/arm/cortex-m0/context_rvds.S
View File

@ -12,6 +12,7 @@
; * 2010-01-25 Bernard first version ; * 2010-01-25 Bernard first version
; * 2012-06-01 aozima set pendsv priority to 0xFF. ; * 2012-06-01 aozima set pendsv priority to 0xFF.
; * 2012-08-17 aozima fixed bug: store r8 - r11. ; * 2012-08-17 aozima fixed bug: store r8 - r11.
; * 2013-06-18 aozima add restore MSP feature.
; */ ; */
;/** ;/**
@ -19,6 +20,7 @@
; */ ; */
;/*@{*/ ;/*@{*/
SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register
NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
NVIC_SHPR3 EQU 0xE000ED20 ; system priority register (2) NVIC_SHPR3 EQU 0xE000ED20 ; system priority register (2)
NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest)
@ -183,6 +185,13 @@ rt_hw_context_switch_to PROC
STR r1, [r0] STR r1, [r0]
NOP NOP
; restore MSP
LDR r0, =SCB_VTOR
LDR r0, [r0]
LDR r0, [r0]
NOP
MSR msp, r0
; enable interrupts at processor level ; enable interrupts at processor level
CPSIE I CPSIE I