libs/rt-thread
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rt-thread
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Merge remote-tracking branch 'upstream/master'

This commit is contained in:
JasonJiaJie 2017-12-14 09:12:01 +08:00
parent bd4c90f619 b0f4ae246a
commit a2a8e2eee0
375 changed files with 5788 additions and 6205 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
.travis.yml
View File

@ -70,6 +70,7 @@ env:
- RTT_BSP='stm32f4xx-HAL' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32f411-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32f429-apollo' RTT_TOOL_CHAIN='sourcery-arm'
# - RTT_BSP='stm32f429-armfly' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32f429-disco' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32l475-iot-disco' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32l476-nucleo' RTT_TOOL_CHAIN='sourcery-arm'

70
bsp/imxrt1052-evk/.config
View File

@ -8,12 +8,15 @@
#
CONFIG_RT_NAME_MAX=8
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32=y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=100
CONFIG_RT_DEBUG=y
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_DEBUG_INIT=0
# CONFIG_RT_DEBUG_THREAD is not set
CONFIG_RT_DEBUG_THREAD=0
CONFIG_RT_USING_HOOK=y
CONFIG_IDLE_THREAD_STACK_SIZE=256
# CONFIG_RT_USING_TIMER_SOFT is not set
@ -32,15 +35,18 @@ CONFIG_RT_USING_MESSAGEQUEUE=y
# Memory Management
#
# CONFIG_RT_USING_MEMPOOL is not set
# CONFIG_RT_USING_MEMHEAP is not set
CONFIG_RT_USING_HEAP=y
CONFIG_RT_USING_SMALL_MEM=y
CONFIG_RT_USING_MEMHEAP=y
# CONFIG_RT_USING_NOHEAP is not set
# CONFIG_RT_USING_SMALL_MEM is not set
# CONFIG_RT_USING_SLAB is not set
CONFIG_RT_USING_MEMHEAP_AS_HEAP=y
CONFIG_RT_USING_HEAP=y
#
# Kernel Device Object
#
CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
@ -78,8 +84,13 @@ CONFIG_FINSH_USING_MSH_DEFAULT=y
CONFIG_RT_USING_DFS=y
CONFIG_DFS_USING_WORKDIR=y
CONFIG_DFS_FILESYSTEMS_MAX=2
CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
CONFIG_DFS_FD_MAX=4
CONFIG_RT_USING_DFS_ELMFAT=y
#
# elm-chan's FatFs, Generic FAT Filesystem Module
#
CONFIG_RT_DFS_ELM_CODE_PAGE=437
CONFIG_RT_DFS_ELM_WORD_ACCESS=y
CONFIG_RT_DFS_ELM_USE_LFN_0=y
@ -94,6 +105,9 @@ CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512
CONFIG_RT_DFS_ELM_REENTRANT=y
CONFIG_RT_USING_DFS_DEVFS=y
# CONFIG_RT_USING_DFS_NET is not set
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_RAMFS is not set
# CONFIG_RT_USING_DFS_UFFS is not set
# CONFIG_RT_USING_DFS_NFS is not set
#
@ -111,6 +125,11 @@ CONFIG_RT_USING_SERIAL=y
CONFIG_RT_USING_SDIO=y
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_WIFI is not set
#
# Using USB
#
# CONFIG_RT_USING_USB_HOST is not set
# CONFIG_RT_USING_USB_DEVICE is not set
@ -118,10 +137,8 @@ CONFIG_RT_USING_SDIO=y
# POSIX layer and C standard library
#
CONFIG_RT_USING_LIBC=y
CONFIG_RT_USING_PTHREADS=y
CONFIG_RT_USING_POSIX=y
# CONFIG_RT_USING_POSIX_MMAP is not set
# CONFIG_RT_USING_POSIX_TERMIOS is not set
# CONFIG_RT_USING_PTHREADS is not set
# CONFIG_RT_USING_POSIX is not set
#
# Network stack
@ -141,6 +158,13 @@ CONFIG_RT_LWIP_DHCP=y
CONFIG_IP_SOF_BROADCAST=1
CONFIG_IP_SOF_BROADCAST_RECV=1
# CONFIG_LWIP_USING_DHCPD is not set
#
# Static IPv4 Address
#
CONFIG_RT_LWIP_IPADDR="192.168.1.30"
CONFIG_RT_LWIP_GWADDR="192.168.1.1"
CONFIG_RT_LWIP_MSKADDR="255.255.255.0"
CONFIG_RT_LWIP_UDP=y
CONFIG_RT_LWIP_TCP=y
# CONFIG_RT_LWIP_RAW is not set
@ -178,6 +202,17 @@ CONFIG_LWIP_SO_RCVBUF=1
#
# CONFIG_RT_USING_GUIENGINE is not set
#
# VBUS(Virtual Software BUS)
#
# CONFIG_RT_USING_VBUS is not set
#
# Utilities
#
# CONFIG_RT_USING_LOGTRACE is not set
# CONFIG_RT_USING_RYM is not set
#
# RT-Thread online packages
#
@ -187,24 +222,30 @@ CONFIG_LWIP_SO_RCVBUF=1
#
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
#
# IoT - internet of things
#
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_WEB_TERMINAL is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_EZXML is not set
# CONFIG_PKG_USING_NANOPB is not set
#
# security packages
#
# CONFIG_PKG_USING_MBEDTLS is not set
# CONFIG_PKG_USING_libsodium is not set
#
# language packages
#
# CONFIG_PKG_USING_JERRYSCRIPT is not set
# CONFIG_PKG_USING_MICROPYTHON is not set
#
# multimedia packages
@ -214,15 +255,18 @@ CONFIG_LWIP_SO_RCVBUF=1
# tools packages
#
# CONFIG_PKG_USING_CMBACKTRACE is not set
# CONFIG_PKG_USING_ELOG is not set
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
#
# miscellaneous packages
#
# CONFIG_PKG_USING_HELLO is not set
# CONFIG_PKG_USING_FASTLZ is not set
# CONFIG_PKG_USING_MINILZO is not set
#
# BSP_SPECIAL CONFIG
# example package: hello
#
# CONFIG_PKG_USING_HELLO is not set
CONFIG_RT_USING_UART=y
CONFIG_RT_USING_UART1=y

30
bsp/imxrt1052-evk/Libraries/arm/MIMXRT1052xxxxx_flexspi_nor.scf
View File

@ -45,20 +45,20 @@
** ###################################################################
*/
#define m_interrupts_start 0x60002000
#define m_interrupts_size 0x00000400
#define m_text_start 0x60002400
#define m_text_size 0x1F7FDC00
#define m_text_start 0x60002000
#define m_text_size 0x1F7FE000
#define m_data_start 0x20000000
#define m_data_size 0x00020000
#define m_ncache_start 0x81E00000
#define m_ncache_size 0x00200000
/* Sizes */
#if (defined(__stack_size__))
#define Stack_Size __stack_size__
#else
#define Stack_Size 0x0400
#define Stack_Size 0x1000
#endif
#if (defined(__heap_size__))
@ -67,25 +67,29 @@
#define Heap_Size 0x0400
#endif
#define RTT_HEAP_SIZE \
(m_data_size - ImageLength(RW_m_data) - ImageLength(ARM_LIB_HEAP) - ImageLength(ARM_LIB_STACK))
LR_m_text m_text_start m_text_size { ; load region size_region
ER_m_text m_text_start m_text_size { ; load address = execution address
* (RESET,+FIRST)
* (InRoot$$Sections)
.ANY (+RO)
}
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
.ANY (+RW +ZI)
* (NonCacheable.init)
* (NonCacheable)
}
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
}
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
ARM_LIB_STACK +0 EMPTY Stack_Size { ; Stack region growing down
}
RTT_HEAP +0 EMPTY RTT_HEAP_SIZE {
}
}
LR_m_interrupts m_interrupts_start m_interrupts_size {
VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
* (RESET,+FIRST)
RW_m_ncache m_ncache_start m_ncache_size { ; ncache RW data
* (NonCacheable.init)
* (NonCacheable)
}
}

45
bsp/imxrt1052-evk/Libraries/arm/evkmimxrt1050_flexspi_nor.ini Normal file
View File

@ -0,0 +1,45 @@
/*
* Copyright 2017 NXP
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
FUNC void Setup (void) {
SP = _RDWORD(0x60002000); // Setup Stack Pointer
PC = _RDWORD(0x60002004); // Setup Program Counter
_WDWORD(0xE000ED08, 0x60002000); // Setup Vector Table Offset Register
}
FUNC void OnResetExec (void) { // executes upon software RESET
Setup(); // Setup for Running
}
LOAD %L INCREMENTAL // Download
Setup(); // Setup for Running
// g, main

74
bsp/imxrt1052-evk/Libraries/gcc/MIMXRT1052xxxxx_flexspi_nor.ld
View File

@ -53,14 +53,33 @@ STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
/* Specify the memory areas */
MEMORY
{
m_boot_data (RX) : ORIGIN = 0x60000000, LENGTH = 0x00000400
m_image_vertor_table (RX) : ORIGIN = 0x60001000, LENGTH = 0x00000400
m_interrupts (RX) : ORIGIN = 0x60002000, LENGTH = 0x00000400
m_text (RX) : ORIGIN = 0x60002400, LENGTH = 0x1F7FDC00
m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
m_itcm (RW) : ORIGIN = 0x00000000, LENGTH = 0x00020000
m_dtcm (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
m_ocram (RW) : ORIGIN = 0x20200000, LENGTH = 0x00040000
m_sdram (RW) : ORIGIN = 0x80000000, LENGTH = 0x01E00000
m_nocache (RW) : ORIGIN = 0x81E00000, LENGTH = 0x00200000
}
/* Define output sections */
SECTIONS
{
.boot_data :
{
KEEP(*(.bootdata))
} > m_boot_data
.image_vertor_table :
{
KEEP(*(.ivt))
} > m_image_vertor_table
/* The startup code goes first into internal RAM */
.interrupts :
{
@ -87,6 +106,23 @@ SECTIONS
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(4);
/* section information for initial. */
. = ALIGN(4);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
} > m_text
.ARM.extab :
@ -173,7 +209,7 @@ SECTIONS
KEEP(*(.jcr*))
. = ALIGN(4);
__data_end__ = .; /* define a global symbol at data end */
} > m_data
} > m_dtcm
__NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__);
.ncache.init : AT(__NDATA_ROM)
@ -182,14 +218,14 @@ SECTIONS
*(NonCacheable.init)
. = ALIGN(4);
__noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
} > m_data
} > m_dtcm
. = __noncachedata_init_end__;
.ncache :
{
*(NonCacheable)
. = ALIGN(4);
__noncachedata_end__ = .; /* define a global symbol at ncache data end */
} > m_data
} > m_dtcm
__DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__);
text_end = ORIGIN(m_text) + LENGTH(m_text);
@ -209,32 +245,26 @@ SECTIONS
. = ALIGN(4);
__bss_end__ = .;
__END_BSS = .;
} > m_data
.heap :
{
. = ALIGN(8);
__end__ = .;
PROVIDE(end = .);
__HeapBase = .;
. += HEAP_SIZE;
__HeapLimit = .;
__heap_limit = .; /* Add for _sbrk */
} > m_data
} > m_dtcm
.stack :
{
. = ALIGN(8);
stack_start = .;
. += STACK_SIZE;
} > m_data
stack_end = .;
__StackTop = .;
} > m_dtcm
/* Initializes stack on the end of block */
__StackTop = ORIGIN(m_data) + LENGTH(m_data);
__StackLimit = __StackTop - STACK_SIZE;
PROVIDE(__stack = __StackTop);
.RTT_HEAP :
{
heap_start = .;
. = ALIGN(8);
} > m_dtcm
PROVIDE(heap_end = ORIGIN(m_dtcm) + LENGTH(m_dtcm));
.ARM.attributes 0 : { *(.ARM.attributes) }
ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
}

56
bsp/imxrt1052-evk/Libraries/gcc/MIMXRT1052xxxxx_ram.ld
View File

@ -54,8 +54,14 @@ STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
MEMORY
{
m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000400
m_text (RX) : ORIGIN = 0x00000400, LENGTH = 0x0001FC00
m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
m_text (RX) : ORIGIN = 0x00000400, LENGTH = 0x00020000
/* m_itcm (RW) : ORIGIN = 0x00000000, LENGTH = 0x00020000 */
m_dtcm (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
/* m_ocram (RW) : ORIGIN = 0x20200000, LENGTH = 0x00040000 */
/* m_sdram (RW) : ORIGIN = 0x80000000, LENGTH = 0x01E00000 */
/* m_nocache (RW) : ORIGIN = 0x81E00000, LENGTH = 0x00200000 */
}
/* Define output sections */
@ -87,6 +93,23 @@ SECTIONS
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(4);
/* section information for initial. */
. = ALIGN(4);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
} > m_text
.ARM.extab :
@ -173,7 +196,7 @@ SECTIONS
KEEP(*(.jcr*))
. = ALIGN(4);
__data_end__ = .; /* define a global symbol at data end */
} > m_data
} > m_dtcm
__NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__);
.ncache.init : AT(__NDATA_ROM)
@ -182,14 +205,14 @@ SECTIONS
*(NonCacheable.init)
. = ALIGN(4);
__noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
} > m_data
} > m_dtcm
. = __noncachedata_init_end__;
.ncache :
{
*(NonCacheable)
. = ALIGN(4);
__noncachedata_end__ = .; /* define a global symbol at ncache data end */
} > m_data
} > m_dtcm
__DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__);
text_end = ORIGIN(m_text) + LENGTH(m_text);
@ -209,32 +232,21 @@ SECTIONS
. = ALIGN(4);
__bss_end__ = .;
__END_BSS = .;
} > m_data
.heap :
{
. = ALIGN(8);
__end__ = .;
PROVIDE(end = .);
__HeapBase = .;
. += HEAP_SIZE;
__HeapLimit = .;
__heap_limit = .; /* Add for _sbrk */
} > m_data
} > m_dtcm
.stack :
{
. = ALIGN(8);
stack_start = .;
. += STACK_SIZE;
} > m_data
stack_end = .;
heap_start = .;
} > m_dtcm
/* Initializes stack on the end of block */
__StackTop = ORIGIN(m_data) + LENGTH(m_data);
__StackLimit = __StackTop - STACK_SIZE;
__StackTop = stack_end;
PROVIDE(__stack = __StackTop);
.ARM.attributes 0 : { *(.ARM.attributes) }
ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
}

4
bsp/imxrt1052-evk/Libraries/gcc/startup_MIMXRT1052.S
View File

@ -36,6 +36,10 @@
/*****************************************************************************/
/* Version: GCC for ARM Embedded Processors */
/*****************************************************************************/
#define __STARTUP_INITIALIZE_NONCACHEDATA
#define __STARTUP_CLEAR_BSS
.syntax unified
.arch armv7-m

48
bsp/imxrt1052-evk/Libraries/iar/MIMXRT1052xxxxx_flexspi_nor.icf
View File

@ -47,14 +47,23 @@
define symbol m_interrupts_start = 0x60002000;
define symbol m_interrupts_end = 0x600023FF;
define symbol m_text_start = 0x60002400;
define symbol m_text_end = 0x7F7FFFFF;
define symbol m_itcm_start = 0x00000000;
define symbol m_itcm_end = 0x0001FFFF;
define symbol m_data_start = 0x20000000;
define symbol m_data_end = 0x2001FFFF;
define symbol m_spiflash_start = 0x60002400;
define symbol m_spiflash_end = 0x7F7FFFFF;
define symbol m_data2_start = 0x20200000;
define symbol m_data2_end = 0x2023FFFF;
define symbol m_dtcm_start = 0x20000000;
define symbol m_dtcm_end = 0x2001FFFF;
define symbol m_ocram_start = 0x20200000;
define symbol m_ocram_end = 0x2023FFFF;
define symbol m_sdram_start = 0x80000000;
define symbol m_sdram_end = 0x81DFFFFF;
define symbol m_ncache_start = 0x81E00000;
define symbol m_ncache_end = 0x81FFFFFF;
/* Sizes */
if (isdefinedsymbol(__stack_size__)) {
@ -72,14 +81,17 @@ if (isdefinedsymbol(__heap_size__)) {
define exported symbol __VECTOR_TABLE = m_interrupts_start;
define exported symbol __VECTOR_RAM = m_interrupts_start;
define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0;
define exported symbol __RTT_HEAP_END = m_dtcm_end;
define memory mem with size = 4G;
define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
| mem:[from m_text_start to m_text_end];
| mem:[from m_spiflash_start to m_spiflash_end];
define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
define region DATA2_region = mem:[from m_data2_start to m_data2_end];
define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
define region ITCM_region = mem:[from m_itcm_start to m_itcm_end];
define region DTCM_region = mem:[from m_dtcm_start to m_dtcm_end];
define region OCRAM_region = mem:[from m_ocram_start to m_ocram_end];
define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end];
define region SDRAM_region = mem:[from m_sdram_start to m_sdram_end];
define block CSTACK with alignment = 8, size = __size_cstack__ { };
define block HEAP with alignment = 8, size = __size_heap__ { };
@ -92,10 +104,14 @@ do not initialize { section .noinit };
place at address mem: m_interrupts_start { readonly section .intvec };
place in TEXT_region { readonly };
place in DATA_region { block RW };
place in DATA_region { block ZI };
place in DATA_region { last block HEAP };
place in DATA_region { block NCACHE_VAR };
place in CSTACK_region { block CSTACK };
keep { section FSymTab };
keep { section VSymTab };
keep { section .rti_fn* };
place in TEXT_region { readonly };
place in DTCM_region { block RW };
place in DTCM_region { block ZI };
place in DTCM_region { last block HEAP };
place in DTCM_region { block CSTACK };
place in NCACHE_region { block NCACHE_VAR };

2
bsp/imxrt1052-evk/Libraries/system_MIMXRT1052.c
View File

@ -116,6 +116,8 @@ void SystemInit (void) {
SCB_EnableDCache();
#endif
extern void rt_lowlevel_init(void);
rt_lowlevel_init();
}
/* ----------------------------------------------------------------------------

89
bsp/imxrt1052-evk/applications/main.c
View File

@ -30,13 +30,13 @@
#include <dfs_file.h>
#endif
#ifdef RT_USING_DEVICE
#include <rtdevice.h>
#endif
#include <board.h>
RT_USED MPU_Type *mpu = MPU;
RT_USED IOMUXC_GPR_Type *iomuxc_gpr = IOMUXC_GPR;
static void dump_clock(void)
void dump_clock(void)
{
rt_kprintf("CPU clock: %d\n", CLOCK_GetFreq(kCLOCK_CpuClk));
rt_kprintf("AHB clock : %d\n", CLOCK_GetFreq(kCLOCK_AhbClk));
@ -63,29 +63,82 @@ static void dump_clock(void)
rt_kprintf("Video PLLCLK : %d\n", CLOCK_GetFreq(kCLOCK_VideoPllClk));
}
void dump_tcm(void)
void dump_cc_info(void)
{
#define DUMP_REG(__REG) \
rt_kprintf("%s(%08p): %08x\n", #__REG, &(__REG), __REG)
#if defined(__CC_ARM)
rt_kprintf("using armcc, version: %d\n", __ARMCC_VERSION);
#elif defined(__ICCARM__)
rt_kprintf("using iccarm, version: %d\n", __VER__);
#elif defined(__GNUC__)
rt_kprintf("using gcc, version: %d.%d\n", __GNUC__, __GNUC_MINOR__);
#endif
}
DUMP_REG(IOMUXC_GPR->GPR14);
DUMP_REG(IOMUXC_GPR->GPR16);
DUMP_REG(IOMUXC_GPR->GPR17);
void dump_link_info(void)
{
#if defined(__CC_ARM)
#elif defined(__ICCARM__)
#elif defined(__GNUC__)
#define DUMP_SYMBOL(__SYM) \
extern int __SYM; \
rt_kprintf("%s: %p\n", #__SYM, &__SYM)
DUMP_SYMBOL(__fsymtab_start);
DUMP_SYMBOL(__fsymtab_end);
DUMP_SYMBOL(__vsymtab_start);
DUMP_SYMBOL(__vsymtab_end);
DUMP_SYMBOL(__rt_init_start);
DUMP_SYMBOL(__rt_init_end);
DUMP_SYMBOL(__exidx_start);
DUMP_SYMBOL(__exidx_end);
DUMP_SYMBOL(__etext);
DUMP_SYMBOL(__data_start__);
DUMP_SYMBOL(__data_end__);
DUMP_SYMBOL(__noncachedata_start__);
DUMP_SYMBOL(__noncachedata_init_end__);
DUMP_SYMBOL(__noncachedata_end__);
DUMP_SYMBOL(__bss_start__);
DUMP_SYMBOL(__bss_end__);
DUMP_SYMBOL(stack_start);
DUMP_SYMBOL(stack_end);
DUMP_SYMBOL(heap_start);
#endif
}
int main(void)
{
rt_uint32_t result;
//dump_clock();
//dump_tcm();
dump_cc_info();
dump_link_info();
rt_thread_delay(RT_TICK_PER_SECOND * 2);
rt_kprintf("build time: %s %s\n", __DATE__, __TIME__);
/* mount sd card fat partition 1 as root directory */
if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
rt_kprintf("File System initialized!\n");
#if defined(RT_USING_DFS) && defined(RT_USING_SDIO)
result = mmcsd_wait_cd_changed(RT_TICK_PER_SECOND);
if (result == MMCSD_HOST_PLUGED)
{
/* mount sd card fat partition 1 as root directory */
if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
rt_kprintf("File System initialized!\n");
else
rt_kprintf("File System init failed!\n");
}
else
rt_kprintf("File System init failed!\n");
{
rt_kprintf("sdcard init fail or timeout: %d!\n", result);
}
#endif
while (1)
{

50
bsp/imxrt1052-evk/applications/mem_dump.c Normal file
View File

@ -0,0 +1,50 @@
/*
* File : clock.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2017-12-05 Tanek first version
*/
#include <rtthread.h>
static void mem_dump(uint32_t buffer, uint32_t length)
{
uint32_t *buf = (uint32_t *)buffer;
int i;
for (i = 0; i < length / 4; i++)
{
rt_kprintf("0x%08X,", buf[i]);
if (i % 8 == 7)
{
rt_kprintf("\n");
}
else
{
rt_kprintf(" ");
}
}
}
#ifdef RT_USING_FINSH
#include <finsh.h>
FINSH_FUNCTION_EXPORT(mem_dump, dump memory);
#endif

95
bsp/imxrt1052-evk/bsp/imxrt/imxrt1052_sdram.icf
View File

@ -1,95 +0,0 @@
/*
** ###################################################################
** Processor: MIMXRT1052DVL6A
** Compiler: IAR ANSI C/C++ Compiler for ARM
** Reference manual: i.MX 6RT for ROM
** Version: rev. 0.1, 2017-01-10
** Build: b170608
**
** Abstract:
** Linker file for the IAR ANSI C/C++ Compiler for ARM
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2017 NXP
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** 1. Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** 2. Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** 3. Neither the name of the copyright holder nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.nxp.com
** mail: support@nxp.com
**
** ###################################################################
*/
define symbol m_interrupts_start = 0x00000000;
define symbol m_interrupts_end = 0x000003FF;
define symbol m_text_start = 0x00000400;
define symbol m_text_end = 0x0001FFFF;
define symbol m_data_start = 0x80020000;
define symbol m_data_end = 0x800FFFFF;
/* Sizes */
if (isdefinedsymbol(__stack_size__)) {
define symbol __size_cstack__ = __stack_size__;
} else {
define symbol __size_cstack__ = 0x0400;
}
if (isdefinedsymbol(__heap_size__)) {
define symbol __size_heap__ = __heap_size__;
} else {
define symbol __size_heap__ = 0x0400;
}
define exported symbol __VECTOR_TABLE = m_interrupts_start;
define exported symbol __VECTOR_RAM = m_interrupts_start;
define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0;
define memory mem with size = 4G;
define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
| mem:[from m_text_start to m_text_end];
define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
define block CSTACK with alignment = 8, size = __size_cstack__ { };
define block HEAP with alignment = 8, size = __size_heap__ { };
define block RW { readwrite };
define block ZI { zi };
define block RTT_INIT_FUNC with fixed order { readonly section .rti_fn* };
initialize by copy { readwrite, section .textrw };
do not initialize { section .noinit };
keep { section FSymTab };
keep { section VSymTab };
keep { section .rti_fn* };
place at address mem: m_interrupts_start { readonly section .intvec };
place in TEXT_region { readonly, block RTT_INIT_FUNC };
place in DATA_region { block RW };
place in DATA_region { block ZI };
place in DATA_region { last block HEAP };
place in CSTACK_region { block CSTACK };

2
bsp/imxrt1052-evk/drivers/SConscript
View File

@ -8,6 +8,8 @@ cwd = os.path.join(str(Dir('#')), 'drivers')
src = Split("""
board.c
usart.c
hyper_flash_boot.c
drv_sdram.c
""")
CPPPATH = [cwd]

94
bsp/imxrt1052-evk/drivers/board.c
View File

@ -18,6 +18,8 @@
#include "board.h"
#include "usart.h"
static struct rt_memheap system_heap;
/* ARM PLL configuration for RUN mode */
const clock_arm_pll_config_t armPllConfig = { .loopDivider = 100U };
@ -29,14 +31,14 @@ const clock_usb_pll_config_t usb1PllConfig = { .loopDivider = 0U };
static void BOARD_BootClockGate(void)
{
/* Disable all unused peripheral clock */
CCM->CCGR0 = 0x00C0000FU;
CCM->CCGR1 = 0x30000000U;
CCM->CCGR2 = 0x003F0030U;
CCM->CCGR3 = 0xF0000330U;
CCM->CCGR4 = 0x0000FF3CU;
CCM->CCGR5 = 0xF000330FU;
CCM->CCGR6 = 0x00FC0300U;
// /* Disable all unused peripheral clock */
// CCM->CCGR0 = 0x00C0000FU;
// CCM->CCGR1 = 0x30000000U;
// CCM->CCGR2 = 0x003F0030U;
// CCM->CCGR3 = 0xF0000330U;
// CCM->CCGR4 = 0x0000FF3CU;
// CCM->CCGR5 = 0xF000330FU;
// CCM->CCGR6 = 0x00FC0300U;
}
static void BOARD_BootClockRUN(void)
@ -83,6 +85,64 @@ static void BOARD_BootClockRUN(void)
}
/* MPU configuration. */
static void BOARD_ConfigMPU(void)
{
/* Disable I cache and D cache */
SCB_DisableICache();
SCB_DisableDCache();
/* Disable MPU */
ARM_MPU_Disable();
/* Region 0 setting */
MPU->RBAR = ARM_MPU_RBAR(0, 0xC0000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
/* Region 1 setting */
MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
/* Region 2 setting */
// spi flash: normal type, cacheable, no bufferable, no shareable
MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_512MB);
/* Region 3 setting */
MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
/* Region 4 setting */
MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
/* Region 5 setting */
MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
/* Region 6 setting */
MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
#if defined(SDRAM_MPU_INIT)
/* Region 7 setting */
MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
/* Region 8 setting */
MPU->RBAR = ARM_MPU_RBAR(8, 0x81E00000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 1, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB);
#endif
/* Enable MPU */
ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
/* Enable I cache and D cache */
SCB_EnableDCache();
SCB_EnableICache();
}
/**
* This is the timer interrupt service routine.
*
@ -98,6 +158,14 @@ void SysTick_Handler(void)
rt_interrupt_leave();
}
void rt_lowlevel_init(void)
{
BOARD_ConfigMPU();
extern int imxrt_sdram_init(void);
imxrt_sdram_init();
}
/**
* This function will initial LPC8XX board.
*/
@ -105,10 +173,8 @@ void rt_hw_board_init()
{
BOARD_BootClockRUN();
SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
extern int imxrt_hw_usart_init(void);
imxrt_hw_usart_init();
SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
@ -119,7 +185,11 @@ void rt_hw_board_init()
#endif
#ifdef RT_USING_HEAP
rt_system_heap_init((void*)HEAP_BEGIN, (void*)HEAP_END);
rt_kprintf("sdram heap, begin: 0x%p, end: 0x%p\n", SDRAM_BEGIN, SDRAM_END);
rt_system_heap_init((void*)SDRAM_BEGIN, (void*)SDRAM_END);
rt_kprintf("sram heap, begin: 0x%p, end: 0x%p\n", HEAP_BEGIN, HEAP_END);
rt_memheap_init(&system_heap, "sram", (void *)HEAP_BEGIN, HEAP_SIZE);
#endif
}

25
bsp/imxrt1052-evk/drivers/board.h
View File

@ -21,18 +21,29 @@
#include <fsl_iomuxc.h>
#ifdef __CC_ARM
extern int Image$$RW_m_data$$ZI$$Limit;
#define HEAP_BEGIN (&Image$$RW_m_data$$ZI$$Limit)
extern int Image$$RTT_HEAP$$ZI$$Base;
extern int Image$$RTT_HEAP$$ZI$$Limit;
#define HEAP_BEGIN (&Image$$RTT_HEAP$$ZI$$Base)
#define HEAP_END (&Image$$RTT_HEAP$$ZI$$Limit)
#elif __ICCARM__
#pragma section="HEAP"
#define HEAP_BEGIN (__segment_end("HEAP"))
#define HEAP_BEGIN (__segment_end("HEAP"))
extern void __RTT_HEAP_END;
#define HEAP_END (&__RTT_HEAP_END)
#else
extern int __data_end__;
#define HEAP_BEGIN (&__data_end__)
extern int heap_start;
extern int heap_end;
#define HEAP_BEGIN (&heap_start)
#define HEAP_END (&heap_end)
#endif
#define HEAP_END 0x81DFFFFF
//#define HEAP_END 0x2001FFFF
#define HEAP_SIZE ((uint32_t)HEAP_END - (uint32_t)HEAP_BEGIN)
#define SDRAM_MPU_INIT
#define SDRAM_BEGIN (0x80000000u)
#define SDRAM_END (0x81E00000u)
void rt_hw_board_init(void);

87
bsp/imxrt1052-evk/drivers/drv_eth.c
View File

@ -36,16 +36,17 @@
#define PHY_ADDRESS 0x02u
/* debug option */
//#define DEBUG
//#define ETH_RX_DUMP
//#define ETH_TX_DUMP
#ifdef DEBUG
#define ETH_PRINTF rt_kprintf
#else
#define ETH_PRINTF(...)
#endif
#define DBG_ENABLE
#define DBG_SECTION_NAME "[ETH]"
#define DBG_COLOR
#define DBG_LEVEL DBG_INFO
#include <rtdbg.h>
#define MAX_ADDR_LEN 6
@ -380,21 +381,31 @@ static void _enet_config(void)
/* Set SMI to get PHY link status. */
sysClock = CLOCK_GetFreq(kCLOCK_AhbClk);
status = PHY_Init(imxrt_eth_device.enet_base, PHY_ADDRESS, sysClock);
while (status != kStatus_Success)
{
ETH_PRINTF("\r\nPHY Auto-negotiation failed. Please check the cable connection and link partner setting.\r\n");
status = PHY_Init(imxrt_eth_device.enet_base, PHY_ADDRESS, sysClock);
}
PHY_GetLinkStatus(imxrt_eth_device.enet_base, PHY_ADDRESS, &link);
if (link)
status = PHY_Init(imxrt_eth_device.enet_base, PHY_ADDRESS, sysClock);
if (status == kStatus_Success)
{
/* Get the actual PHY link speed. */
PHY_GetLinkSpeedDuplex(imxrt_eth_device.enet_base, PHY_ADDRESS, &speed, &duplex);
/* Change the MII speed and duplex for actual link status. */
config.miiSpeed = (enet_mii_speed_t)speed;
config.miiDuplex = (enet_mii_duplex_t)duplex;
PHY_GetLinkStatus(imxrt_eth_device.enet_base, PHY_ADDRESS, &link);
if (link)
{
/* Get the actual PHY link speed. */
PHY_GetLinkSpeedDuplex(imxrt_eth_device.enet_base, PHY_ADDRESS, &speed, &duplex);
/* Change the MII speed and duplex for actual link status. */
config.miiSpeed = (enet_mii_speed_t)speed;
config.miiDuplex = (enet_mii_duplex_t)duplex;
}
dbg_log(DBG_LOG, "PHY Auto-negotiation success.\n");
eth_device_linkchange(&imxrt_eth_device.parent, RT_TRUE);
}
else
{
config.miiSpeed = kENET_MiiSpeed10M;
config.miiDuplex = kENET_MiiHalfDuplex;
dbg_log(DBG_WARNING, "PHY Auto-negotiation failed. Please check the cable connection and link partner setting.\n");
eth_device_linkchange(&imxrt_eth_device.parent, RT_FALSE);
}
ENET_Init(imxrt_eth_device.enet_base, &imxrt_eth_device.enet_handle, &config, &buffConfig, &imxrt_eth_device.dev_addr[0], sysClock);
@ -416,33 +427,33 @@ static rt_err_t rt_imxrt_eth_init(rt_device_t dev)
static rt_err_t rt_imxrt_eth_open(rt_device_t dev, rt_uint16_t oflag)
{
ETH_PRINTF("rt_imxrt_eth_open...\n");
dbg_log(DBG_LOG, "rt_imxrt_eth_open...\n");
return RT_EOK;
}
static rt_err_t rt_imxrt_eth_close(rt_device_t dev)
{
ETH_PRINTF("rt_imxrt_eth_close...\n");
dbg_log(DBG_LOG, "rt_imxrt_eth_close...\n");
return RT_EOK;
}
static rt_size_t rt_imxrt_eth_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
{
ETH_PRINTF("rt_imxrt_eth_read...\n");
dbg_log(DBG_LOG, "rt_imxrt_eth_read...\n");
rt_set_errno(-RT_ENOSYS);
return 0;
}
static rt_size_t rt_imxrt_eth_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
{
ETH_PRINTF("rt_imxrt_eth_write...\n");
dbg_log(DBG_LOG, "rt_imxrt_eth_write...\n");
rt_set_errno(-RT_ENOSYS);
return 0;
}
static rt_err_t rt_imxrt_eth_control(rt_device_t dev, int cmd, void *args)
{
ETH_PRINTF("rt_imxrt_eth_control...\n");
dbg_log(DBG_LOG, "rt_imxrt_eth_control...\n");
switch(cmd)
{
case NIOCTL_GADDR:
@ -468,7 +479,7 @@ rt_err_t rt_imxrt_eth_tx( rt_device_t dev, struct pbuf* p)
RT_ASSERT(p != NULL);
RT_ASSERT(enet_handle != RT_NULL);
ETH_PRINTF("rt_imxrt_eth_tx: %d\n", p->len);
dbg_log(DBG_LOG, "rt_imxrt_eth_tx: %d\n", p->len);
#ifdef ETH_TX_DUMP
{
@ -477,11 +488,11 @@ rt_err_t rt_imxrt_eth_tx( rt_device_t dev, struct pbuf* p)
buf = (uint8_t *)p->payload;
for (i = 0; i < p->len; i++)
{
ETH_PRINTF("%02X ", buf[i]);
dbg_log(DBG_LOG, "%02X ", buf[i]);
if (i % 16 == 15)
ETH_PRINTF("\n");
dbg_log(DBG_LOG, "\n");
}
ETH_PRINTF("\n");
dbg_log(DBG_LOG, "\n");
}
#endif
@ -532,28 +543,28 @@ struct pbuf *rt_imxrt_eth_rx(rt_device_t dev)
buf = (uint8_t *)p->payload;
for (i = 0; i < p->len; i++)
{
ETH_PRINTF("%02X ", buf[i]);
dbg_log(DBG_LOG, "%02X ", buf[i]);
if (i % 16 == 15)
ETH_PRINTF("\n");
dbg_log(DBG_LOG, "\n");
}
ETH_PRINTF("\n");
dbg_log(DBG_LOG, "\n");
#endif
return p;
}
else
{
ETH_PRINTF(" A frame read failed\n");
dbg_log(DBG_LOG, " A frame read failed\n");
pbuf_free(p);
}
}
else
{
ETH_PRINTF(" pbuf_alloc faild\n");
dbg_log(DBG_LOG, " pbuf_alloc faild\n");
}
}
else if (status == kStatus_ENET_RxFrameError)
{
ETH_PRINTF("ENET_GetRxFrameSize: kStatus_ENET_RxFrameError\n");
dbg_log(DBG_WARNING, "ENET_GetRxFrameSize: kStatus_ENET_RxFrameError\n");
/* Update the received buffer when error happened. */
/* Get the error information of the received g_frame. */
ENET_GetRxErrBeforeReadFrame(enet_handle, error_statistic);
@ -591,20 +602,20 @@ static int rt_hw_imxrt_eth_init(void)
imxrt_eth_device.parent.eth_rx = rt_imxrt_eth_rx;
imxrt_eth_device.parent.eth_tx = rt_imxrt_eth_tx;
ETH_PRINTF("sem init: tx_wait\r\n");
dbg_log(DBG_LOG, "sem init: tx_wait\r\n");
/* init tx semaphore */
rt_sem_init(&imxrt_eth_device.tx_wait, "tx_wait", 0, RT_IPC_FLAG_FIFO);
/* register eth device */
ETH_PRINTF("eth_device_init start\r\n");
dbg_log(DBG_LOG, "eth_device_init start\r\n");
state = eth_device_init(&(imxrt_eth_device.parent), "e0");
if (RT_EOK == state)
{
ETH_PRINTF("eth_device_init success\r\n");
dbg_log(DBG_LOG, "eth_device_init success\r\n");
}
else
{
ETH_PRINTF("eth_device_init faild: %d\r\n", state);
dbg_log(DBG_LOG, "eth_device_init faild: %d\r\n", state);
}
return state;
}

195
bsp/imxrt1052-evk/drivers/drv_sdram.c Normal file
View File

@ -0,0 +1,195 @@
/*
* File : board.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009 RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2017-12-04 Tanek first implementation
*/
#include <stdint.h>
#include <rthw.h>
#include <rtthread.h>
static uint32_t _RDWORD(uint32_t address)
{
return *((uint32_t *)address);
}
static void _WDWORD(uint32_t address, uint32_t value)
{
*((uint32_t *)address) = value;
}
static void SDRAM_WaitIpCmdDone(void)
{
unsigned long reg;
do
{
reg = _RDWORD(0x402F003C);
}while((reg & 0x3) == 0);
}
static void _clock_init(void)
{
// Enable all clocks
_WDWORD(0x400FC068,0xffffffff);
_WDWORD(0x400FC06C,0xffffffff);
_WDWORD(0x400FC070,0xffffffff);
_WDWORD(0x400FC074,0xffffffff);
_WDWORD(0x400FC078,0xffffffff);
_WDWORD(0x400FC07C,0xffffffff);
_WDWORD(0x400FC080,0xffffffff);
_WDWORD(0x400D8030,0x00002001);
_WDWORD(0x400D8100,0x001d0000);
_WDWORD(0x400FC014,0x00010D40);
}
static void _sdr_Init(void)
{
// Config IOMUX
_WDWORD(0x401F8014, 0x00000000);
_WDWORD(0x401F8018, 0x00000000);
_WDWORD(0x401F801C, 0x00000000);
_WDWORD(0x401F8020, 0x00000000);
_WDWORD(0x401F8024, 0x00000000);
_WDWORD(0x401F8028, 0x00000000);
_WDWORD(0x401F802C, 0x00000000);
_WDWORD(0x401F8030, 0x00000000);
_WDWORD(0x401F8034, 0x00000000);
_WDWORD(0x401F8038, 0x00000000);
_WDWORD(0x401F803C, 0x00000000);
_WDWORD(0x401F8040, 0x00000000);
_WDWORD(0x401F8044, 0x00000000);
_WDWORD(0x401F8048, 0x00000000);
_WDWORD(0x401F804C, 0x00000000);
_WDWORD(0x401F8050, 0x00000000);
_WDWORD(0x401F8054, 0x00000000);
_WDWORD(0x401F8058, 0x00000000);
_WDWORD(0x401F805C, 0x00000000);
_WDWORD(0x401F8060, 0x00000000);
_WDWORD(0x401F8064, 0x00000000);
_WDWORD(0x401F8068, 0x00000000);
_WDWORD(0x401F806C, 0x00000000);
_WDWORD(0x401F8070, 0x00000000);
_WDWORD(0x401F8074, 0x00000000);
_WDWORD(0x401F8078, 0x00000000);
_WDWORD(0x401F807C, 0x00000000);
_WDWORD(0x401F8080, 0x00000000);
_WDWORD(0x401F8084, 0x00000000);
_WDWORD(0x401F8088, 0x00000000);
_WDWORD(0x401F808C, 0x00000000);
_WDWORD(0x401F8090, 0x00000000);
_WDWORD(0x401F8094, 0x00000000);
_WDWORD(0x401F8098, 0x00000000);
_WDWORD(0x401F809C, 0x00000000);
_WDWORD(0x401F80A0, 0x00000000);
_WDWORD(0x401F80A4, 0x00000000);
_WDWORD(0x401F80A8, 0x00000000);
_WDWORD(0x401F80AC, 0x00000000);
_WDWORD(0x401F80B0, 0x00000010); // EMC_39, DQS PIN, enable SION
_WDWORD(0x401F80B4, 0x00000000);
_WDWORD(0x401F80B8, 0x00000000);
// PAD ctrl
// drive strength = 0x7 to increase drive strength
// otherwise the data7 bit may fail.
_WDWORD(0x401F8204, 0x000110F9);
_WDWORD(0x401F8208, 0x000110F9);
_WDWORD(0x401F820C, 0x000110F9);
_WDWORD(0x401F8210, 0x000110F9);
_WDWORD(0x401F8214, 0x000110F9);
_WDWORD(0x401F8218, 0x000110F9);
_WDWORD(0x401F821C, 0x000110F9);
_WDWORD(0x401F8220, 0x000110F9);
_WDWORD(0x401F8224, 0x000110F9);
_WDWORD(0x401F8228, 0x000110F9);
_WDWORD(0x401F822C, 0x000110F9);
_WDWORD(0x401F8230, 0x000110F9);
_WDWORD(0x401F8234, 0x000110F9);
_WDWORD(0x401F8238, 0x000110F9);
_WDWORD(0x401F823C, 0x000110F9);
_WDWORD(0x401F8240, 0x000110F9);
_WDWORD(0x401F8244, 0x000110F9);
_WDWORD(0x401F8248, 0x000110F9);
_WDWORD(0x401F824C, 0x000110F9);
_WDWORD(0x401F8250, 0x000110F9);
_WDWORD(0x401F8254, 0x000110F9);
_WDWORD(0x401F8258, 0x000110F9);
_WDWORD(0x401F825C, 0x000110F9);
_WDWORD(0x401F8260, 0x000110F9);
_WDWORD(0x401F8264, 0x000110F9);
_WDWORD(0x401F8268, 0x000110F9);
_WDWORD(0x401F826C, 0x000110F9);
_WDWORD(0x401F8270, 0x000110F9);
_WDWORD(0x401F8274, 0x000110F9);
_WDWORD(0x401F8278, 0x000110F9);
_WDWORD(0x401F827C, 0x000110F9);
_WDWORD(0x401F8280, 0x000110F9);
_WDWORD(0x401F8284, 0x000110F9);
_WDWORD(0x401F8288, 0x000110F9);
_WDWORD(0x401F828C, 0x000110F9);
_WDWORD(0x401F8290, 0x000110F9);
_WDWORD(0x401F8294, 0x000110F9);
_WDWORD(0x401F8298, 0x000110F9);
_WDWORD(0x401F829C, 0x000110F9);
_WDWORD(0x401F82A0, 0x000110F9);
_WDWORD(0x401F82A4, 0x000110F9);
_WDWORD(0x401F82A8, 0x000110F9);
// Config SDR Controller Registers/
_WDWORD(0x402F0000,0x10000004); // MCR
_WDWORD(0x402F0008,0x00030524); // BMCR0
_WDWORD(0x402F000C,0x06030524); // BMCR1
_WDWORD(0x402F0010,0x8000001B); // BR0, 32MB
_WDWORD(0x402F0014,0x8200001B); // BR1, 32MB
_WDWORD(0x402F0018,0x8400001B); // BR2, 32MB
_WDWORD(0x402F001C,0x8600001B); // BR3, 32MB
_WDWORD(0x402F0020,0x90000021); // BR4,
_WDWORD(0x402F0024,0xA0000019); // BR5,
_WDWORD(0x402F0028,0xA8000017); // BR6,
_WDWORD(0x402F002C,0xA900001B); // BR7,
_WDWORD(0x402F0030,0x00000021); // BR8,
_WDWORD(0x402F0004,0x000079A8); //IOCR,SEMC_CCSX0 as NOR CE, SEMC_CSX1 as PSRAM CE, SEMC_CSX2 as NAND CE, SEMC_CSX3 as DBI CE.
// _WDWORD(0x402F0004,0x00000008); // IOCR, SEMC_CCSX0 as SDRAM_CS1
_WDWORD(0x402F0040,0x00000F31); // SDRAMCR0
_WDWORD(0x402F0044,0x00652922); // SDRAMCR1
_WDWORD(0x402F0048,0x00010920); // SDRAMCR2
_WDWORD(0x402F004C,0x50210A08); // SDRAMCR3
_WDWORD(0x402F0080,0x00000021); // DBICR0
_WDWORD(0x402F0084,0x00888888); // DBICR1
_WDWORD(0x402F0094,0x00000002); // IPCR1
_WDWORD(0x402F0098,0x00000000); // IPCR2
_WDWORD(0x402F0090,0x80000000); // IPCR0
_WDWORD(0x402F009C,0xA55A000F); // IPCMD, SD_CC_IPREA
SDRAM_WaitIpCmdDone();
_WDWORD(0x402F0090,0x80000000); // IPCR0
_WDWORD(0x402F009C,0xA55A000C); // SD_CC_IAF
SDRAM_WaitIpCmdDone();
_WDWORD(0x402F0090,0x80000000); // IPCR0
_WDWORD(0x402F009C,0xA55A000C); // SD_CC_IAF
SDRAM_WaitIpCmdDone();
_WDWORD(0x402F00A0,0x00000033); // IPTXDAT
_WDWORD(0x402F0090,0x80000000); // IPCR0
_WDWORD(0x402F009C,0xA55A000A); // SD_CC_IMS
SDRAM_WaitIpCmdDone();
_WDWORD(0x402F004C,0x50210A09 ); // enable sdram self refresh again after initialization done.
}
int imxrt_sdram_init(void)
{
_clock_init();
_sdr_Init();
return 0;
}
/*@}*/

8
bsp/imxrt1052-evk/drivers/fsl_phy.c
View File

@ -29,12 +29,13 @@
*/
#include "fsl_phy.h"
#include <rtthread.h>
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief Defines the timeout macro. */
#define PHY_TIMEOUT_COUNT 0x3FFFFFFU
#define PHY_TIMEOUT_COUNT 0xFFFFU
/*******************************************************************************
* Prototypes
@ -90,7 +91,7 @@ status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz)
}
/* Reset PHY. */
counter = PHY_TIMEOUT_COUNT;
counter = 6;
result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK);
if (result == kStatus_Success)
{
@ -137,6 +138,9 @@ status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz)
}
}
rt_kprintf("[PHY] wait autonegotiation complete...\n");
rt_thread_delay(RT_TICK_PER_SECOND);
if (!counter)
{
return kStatus_PHY_AutoNegotiateFail;

66
bsp/imxrt1052-evk/drivers/hyper_flash_boot.c Normal file
View File

@ -0,0 +1,66 @@
/*
* File : clock.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2017-12-05 Tanek first version
*/
#include <rtthread.h>
// enter serial download mode, and run command:
// finsh /> mem_dump(0x60000000, 512)
#if defined (__ICCARM__ )
RT_USED static const uint32_t boot_data[] @(0x60000000u) =
#elif defined ( __GNUC__ )
RT_USED static const uint32_t boot_data[] __attribute__((section (".bootdata"))) =
#elif defined ( __CC_ARM )
RT_USED static const uint32_t boot_data[] __attribute__((at(0x60000000u))) =
#endif
{
0x42464346, 0x56010400, 0x00000000, 0x03030303, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000059, 0x01080800, 0x00000000, 0x00000000, 0x04000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000000F, 0x0001000F,
0x8B1887A0, 0xA7048F10, 0x00000000, 0x00000000, 0x87008700, 0x87AA8700, 0x87058700, 0x87708700,
0x8B1887A0, 0xB70B8F10, 0x0000A704, 0x00000000, 0x87008700, 0x87AA8700, 0x87058700, 0x87AA8700,
0x87008700, 0x87558700, 0x87028700, 0x87558700, 0x87008700, 0x87AA8700, 0x87058700, 0x87808700,
0x87008700, 0x87AA8700, 0x87058700, 0x87AA8700, 0x87008700, 0x87558700, 0x87028700, 0x87558700,
0x8B188700, 0x87008F10, 0x00008730, 0x00000000, 0x87008700, 0x87AA8700, 0x87058700, 0x87A08700,
0x8B188700, 0xA3808F10, 0x00000000, 0x00000000, 0x87008700, 0x87AA8700, 0x87058700, 0x87808700,
0x87008700, 0x87AA8700, 0x87058700, 0x87AA8700, 0x87008700, 0x87558700, 0x87028700, 0x87558700,
0x87008700, 0x87AA8700, 0x87058700, 0x87108700, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000102, 0x00000302, 0x00000504, 0x00000902, 0x00000B04, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000200, 0x00040000, 0x00000008, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
};
// finsh /> mem_dump(0x60001000, 16)
#if defined (__ICCARM__ )
RT_USED static const uint32_t image_vector_table[] @(0x60001000u) =
#elif defined ( __GNUC__ )
RT_USED static const uint32_t image_vector_table[] __attribute__((section (".ivt"))) =
#elif defined ( __CC_ARM )
RT_USED static const uint32_t image_vector_table[] __attribute__((at(0x60001000u))) =
#endif
{
0x412000D1, 0x60002000, 0x00000000, 0x00000000, 0x60001020, 0x60001000, 0x00000000, 0x00000000,
0x60000000, 0x00800000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
};

19
bsp/imxrt1052-evk/drivers/usart.c
View File

@ -320,19 +320,33 @@ static int imxrt_getc(struct rt_serial_device *serial)
*/
static void uart_isr(struct rt_serial_device *serial)
{
struct imxrt_uart *uart = (struct imxrt_uart *) serial->parent.user_data;
struct imxrt_uart *uart;
LPUART_Type *base;
RT_ASSERT(serial != RT_NULL);
uart = (struct imxrt_uart *) serial->parent.user_data;
RT_ASSERT(uart != RT_NULL);
base = uart->uart_base;
RT_ASSERT(base != RT_NULL);
/* enter interrupt */
rt_interrupt_enter();
/* UART in mode Receiver -------------------------------------------------*/
if (LPUART_GetStatusFlags(uart->uart_base) & kLPUART_RxDataRegFullFlag)
if (LPUART_GetStatusFlags(base) & kLPUART_RxDataRegFullFlag)
{
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
}
/* If RX overrun. */
if (LPUART_STAT_OR_MASK & base->STAT)
{
/* Clear overrun flag, otherwise the RX does not work. */
base->STAT = ((base->STAT & 0x3FE00000U) | LPUART_STAT_OR_MASK);
}
/* leave interrupt */
rt_interrupt_leave();
}
@ -350,7 +364,6 @@ int imxrt_hw_usart_init(void)
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
int i;
for (i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++)
{
uarts[i].serial->ops = &imxrt_uart_ops;

103
bsp/imxrt1052-evk/imxrt1052_sdram.icf
View File

@ -1,103 +0,0 @@
/*
** ###################################################################
** Processor: MIMXRT1052DVL6A
** Compiler: IAR ANSI C/C++ Compiler for ARM
** Reference manual: i.MX 6RT for ROM
** Version: rev. 0.1, 2017-01-10
** Build: b170608
**
** Abstract:
** Linker file for the IAR ANSI C/C++ Compiler for ARM
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2017 NXP
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** 1. Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** 2. Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** 3. Neither the name of the copyright holder nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.nxp.com
** mail: support@nxp.com
**
** ###################################################################
*/
define symbol m_base_addr = 0x00000000;
define symbol m_interrupts_start = 0x00000000 + m_base_addr;
define symbol m_interrupts_end = 0x000003FF + m_base_addr;
define symbol m_text_start = 0x00000400 + m_base_addr;
define symbol m_text_end = 0x0007FFFF + m_base_addr;
define symbol m_data_start = 0x80000000;
define symbol m_data_end = 0x81DFFFFF;
define symbol m_ncache_start = 0x81E00000;
define symbol m_ncache_end = 0x81FFFFFF;
/* Sizes */
if (isdefinedsymbol(__stack_size__)) {
define symbol __size_cstack__ = __stack_size__;
} else {
define symbol __size_cstack__ = 0x0400;
}
if (isdefinedsymbol(__heap_size__)) {
define symbol __size_heap__ = __heap_size__;
} else {
define symbol __size_heap__ = 0x0400;
}
define exported symbol __VECTOR_TABLE = m_interrupts_start;
define exported symbol __VECTOR_RAM = m_interrupts_start;
define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0;
define memory mem with size = 4G;
define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
| mem:[from m_text_start to m_text_end];
define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end];
define block CSTACK with alignment = 8, size = __size_cstack__ { };
define block HEAP with alignment = 8, size = __size_heap__ { };
define block RW { readwrite };
define block ZI { zi };
define block RTT_INIT_FUNC with fixed order { readonly section .rti_fn* };
define block NCACHE_VAR with size = 0x200000 , alignment = 0x100000 { section NonCacheable , section NonCacheable.init };
initialize by copy { readwrite, section .textrw };
do not initialize { section .noinit };
keep { section FSymTab };
keep { section VSymTab };
keep { section .rti_fn* };
place at address mem: m_interrupts_start { readonly section .intvec };
place in TEXT_region { readonly, block RTT_INIT_FUNC };
place in DATA_region { block RW };
place in DATA_region { block ZI };
place in DATA_region { last block HEAP };
place in CSTACK_region { block CSTACK };
place in NCACHE_region { block NCACHE_VAR };

259
bsp/imxrt1052-evk/imxrt1052_sdram.ld
View File

@ -1,259 +0,0 @@
/*
** ###################################################################
** Processors: MIMXRT1052CVL5A
** MIMXRT1052DVL6A
**
** Compiler: GNU C Compiler
** Reference manual: IMXRT1050RM Rev.C, 08/2017
** Version: rev. 0.1, 2017-01-10
** Build: b170927
**
** Abstract:
** Linker file for the GNU C Compiler
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2017 NXP
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** 1. Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** 2. Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** 3. Neither the name of the copyright holder nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.nxp.com
** mail: support@nxp.com
**
** ###################################################################
*/
/* Entry Point */
ENTRY(Reset_Handler)
HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
/* Specify the memory areas */
MEMORY
{
m_interrupts (RX) : ORIGIN = 0x80000000, LENGTH = 0x80000400
m_text (RX) : ORIGIN = 0x80000400, LENGTH = 0x8007FC00
m_data (RW) : ORIGIN = 0x80000000, LENGTH = 0x01600000
m_ncache (RW) : ORIGIN = 0x81E00000, LENGTH = 0x00200000
}
/* Define output sections */
SECTIONS
{
/* The startup code goes first into internal RAM */
.interrupts :
{
__VECTOR_TABLE = .;
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
} > m_interrupts
__VECTOR_RAM = __VECTOR_TABLE;
__RAM_VECTOR_TABLE_SIZE_BYTES = 0x0;
/* The program code and other data goes into internal RAM */
.text :
{
. = ALIGN(4);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
*(.glue_7) /* glue arm to thumb code */
*(.glue_7t) /* glue thumb to arm code */
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(4);
/* section information for initial. */
. = ALIGN(4);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
. = ALIGN(4);
} > m_text
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > m_text
.ARM :
{
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} > m_text
.ctors :
{
__CTOR_LIST__ = .;
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
KEEP (*crtbegin?.o(.ctors))
/* We don't want to include the .ctor section from
from the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
__CTOR_END__ = .;
} > m_text
.dtors :
{
__DTOR_LIST__ = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*crtbegin?.o(.dtors))
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
__DTOR_END__ = .;
} > m_text
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
} > m_text
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} > m_text
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
} > m_text
__etext = .; /* define a global symbol at end of code */
__DATA_ROM = .; /* Symbol is used by startup for data initialization */
.data : AT(__DATA_ROM)
{
. = ALIGN(4);
__DATA_RAM = .;
__data_start__ = .; /* create a global symbol at data start */
*(m_usb_dma_init_data)
*(.data) /* .data sections */
*(.data*) /* .data* sections */
KEEP(*(.jcr*))
. = ALIGN(4);
__data_end__ = .; /* define a global symbol at data end */
} > m_data
__NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__);
.ncache.init : AT(__NDATA_ROM)
{
__noncachedata_start__ = .; /* create a global symbol at ncache data start */
*(NonCacheable.init)
. = ALIGN(4);
__noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
} > m_ncache
. = __noncachedata_init_end__;
.ncache :
{
*(NonCacheable)
. = ALIGN(4);
__noncachedata_end__ = .; /* define a global symbol at ncache data end */
} > m_ncache
__DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__);
text_end = ORIGIN(m_text) + LENGTH(m_text);
ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
/* Uninitialized data section */
.bss :
{
/* This is used by the startup in order to initialize the .bss section */
. = ALIGN(4);
__START_BSS = .;
__bss_start__ = .;
*(m_usb_dma_noninit_data)
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
__END_BSS = .;
} > m_data
.heap :
{
. = ALIGN(8);
__end__ = .;
PROVIDE(end = .);
__HeapBase = .;
. += HEAP_SIZE;
__HeapLimit = .;
__heap_limit = .; /* Add for _sbrk */
} > m_data
.stack :
{
. = ALIGN(8);
. += STACK_SIZE;
} > m_data
/* Initializes stack on the end of block */
__StackTop = ORIGIN(m_data) + LENGTH(m_data);
__StackLimit = __StackTop - STACK_SIZE;
PROVIDE(__stack = __StackTop);
.ARM.attributes 0 : { *(.ARM.attributes) }
ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
}

99
bsp/imxrt1052-evk/imxrt1052_sdram.sct
View File

@ -1,99 +0,0 @@
#! armcc -E
/*
** ###################################################################
** Processors: MIMXRT1052CVL5A
** MIMXRT1052DVL6A
**
** Compiler: Keil ARM C/C++ Compiler
** Reference manual: IMXRT1050RM Rev.C, 08/2017
** Version: rev. 0.1, 2017-01-10
** Build: b170927
**
** Abstract:
** Linker file for the Keil ARM C/C++ Compiler
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2017 NXP
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** 1. Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** 2. Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** 3. Neither the name of the copyright holder nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.nxp.com
** mail: support@nxp.com
**
** ###################################################################
*/
#define m_start_address 0x00000000
#define m_interrupts_start (0x00000000 + m_start_address)
#define m_interrupts_size 0x00000400
#define m_text_start (m_interrupts_start + m_interrupts_size)
#define m_text_size 0x0001FC00
#define m_data_start 0x80000000
#define m_data_size 0x01E00000
#define m_ncache_start 0x81E00000
#define m_ncache_size 0x00200000
/* Sizes */
#if (defined(__stack_size__))
#define Stack_Size __stack_size__
#else
#define Stack_Size 0x0400
#endif
#if (defined(__heap_size__))
#define Heap_Size __heap_size__
#else
#define Heap_Size 0x0400
#endif
LR_m_text m_text_start m_text_size { ; load region size_region
ER_m_text m_text_start m_text_size { ; load address = execution address
* (InRoot$$Sections)
.ANY (+RO)
}
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
.ANY (+RW +ZI)
}
RW_m_ncache m_ncache_start m_ncache_size { ; ncache RW data
* (NonCacheable.init)
* (NonCacheable)
}
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
}
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
}
}
LR_m_interrupts m_interrupts_start m_interrupts_size {
VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
* (RESET,+FIRST)
}
}

58
bsp/imxrt1052-evk/project.ewd
View File

@ -11,7 +11,7 @@
<name>C-SPY</name>
<archiveVersion>2</archiveVersion>
<data>
<version>28</version>
<version>29</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
@ -48,7 +48,7 @@
</option>
<option>
<name>RunToEnable</name>
<state>1</state>
<state>0</state>
</option>
<option>
<name>RunToName</name>
@ -76,7 +76,7 @@
</option>
<option>
<name>OCDownloadVerifyAll</name>
<state>0</state>
<state>1</state>
</option>
<option>
<name>OCProductVersion</name>
@ -84,15 +84,15 @@
</option>
<option>
<name>OCDynDriverList</name>
<state>ARMSIM_ID</state>
<state>JLINK_ID</state>
</option>
<option>
<name>OCLastSavedByProductVersion</name>
<state>8.11.2.13604</state>
<state>8.20.1.14181</state>
</option>
<option>
<name>UseFlashLoader</name>
<state>0</state>
<state>1</state>
</option>
<option>
<name>CLowLevel</name>
@ -112,7 +112,7 @@
</option>
<option>
<name>FlashLoadersV3</name>
<state>$TOOLKIT_DIR$\config\flashloader\</state>
<state>$TOOLKIT_DIR$\config\flashloader\NXP\FlashIMXRT1050_EVK_FlexSPI.board</state>
</option>
<option>
<name>OCImagesSuppressCheck1</name>
@ -210,6 +210,10 @@
<name>OCAttachSlave</name>
<state>0</state>
</option>
<option>
<name>MassEraseBeforeFlashing</name>
<state>0</state>
</option>
</data>
</settings>
<settings>
@ -288,7 +292,7 @@
<option>
<name>CMSISDAPResetList</name>
<version>1</version>
<state>10</state>
<state>4</state>
</option>
<option>
<name>CMSISDAPHWResetDuration</name>
@ -308,7 +312,7 @@
</option>
<option>
<name>CMSISDAPInterfaceRadio</name>
<state>0</state>
<state>1</state>
</option>
<option>
<name>CMSISDAPInterfaceCmdLine</name>
@ -373,31 +377,31 @@
</option>
<option>
<name>CatchMMERR</name>
<state>1</state>
<state>0</state>
</option>
<option>
<name>CatchNOCPERR</name>
<state>1</state>
<state>0</state>
</option>
<option>
<name>CatchCHKERR</name>
<state>1</state>
<state>0</state>
</option>
<option>
<name>CatchSTATERR</name>
<state>1</state>
<state>0</state>
</option>
<option>
<name>CatchBUSERR</name>
<state>1</state>
<state>0</state>
</option>
<option>
<name>CatchINTERR</name>
<state>1</state>
<state>0</state>
</option>
<option>
<name>CatchHARDERR</name>
<state>1</state>
<state>0</state>
</option>
<option>
<name>CatchDummy</name>
@ -425,7 +429,7 @@
</option>
<option>
<name>CMSISDAPSelectedCPUBehaviour</name>
<state>0</state>
<state></state>
</option>
<option>
<name>ICpuName</name>
@ -721,7 +725,7 @@
<debug>1</debug>
<option>
<name>CCCatchSFERR</name>
<state>0</state>
<state>1</state>
</option>
<option>
<name>JLinkSpeed</name>
@ -822,12 +826,12 @@
</option>
<option>
<name>CCJLinkInterfaceRadio</name>
<state>0</state>
<state>1</state>
</option>
<option>
<name>CCJLinkResetList</name>
<version>6</version>
<state>5</state>
<state>8</state>
</option>
<option>
<name>CCJLinkInterfaceCmdLine</name>
@ -1402,6 +1406,10 @@
<file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
<loadFlag>0</loadFlag>
@ -1418,7 +1426,7 @@
<name>C-SPY</name>
<archiveVersion>2</archiveVersion>
<data>
<version>28</version>
<version>29</version>
<wantNonLocal>1</wantNonLocal>
<debug>0</debug>
<option>
@ -1617,6 +1625,10 @@
<name>OCAttachSlave</name>
<state>0</state>
</option>
<option>
<name>MassEraseBeforeFlashing</name>
<state>0</state>
</option>
</data>
</settings>
<settings>
@ -2809,6 +2821,10 @@
<file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
<loadFlag>0</loadFlag>

219
bsp/imxrt1052-evk/project.ewp
View File

@ -171,7 +171,6 @@
<state>FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1</state>
<state>RT_USING_DLIBC</state>
<state>_DLIB_FILE_DESCRIPTOR</state>
<state>_DLIB_THREAD_SUPPORT</state>
</option>
<option>
<name>CCPreprocFile</name>
@ -301,31 +300,27 @@
<option>
<name>CCIncludePath2</name>
<state />
<state>$PROJ_DIR$\..\..\components\libc\compilers\dlib</state>
<state>$PROJ_DIR$\Libraries</state>
<state>$PROJ_DIR$\..\..\include</state>
<state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\include\netif</state>
<state>$PROJ_DIR$\..\..\libcpu\arm\common</state>
<state>$PROJ_DIR$\..\..\components\dfs\filesystems\net</state>
<state>$PROJ_DIR$\..\..\components\drivers\include</state>
<state>$PROJ_DIR$\Libraries\drivers</state>
<state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\include</state>
<state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src</state>
<state>$PROJ_DIR$\drivers</state>
<state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\include\ipv4</state>
<state>$PROJ_DIR$\.</state>
<state>$PROJ_DIR$\..\..\libcpu\arm\cortex-m7</state>
<state>$PROJ_DIR$\..\..\components\dfs\include</state>
<state>$PROJ_DIR$\..\..\components\dfs\filesystems\devfs</state>
<state>$PROJ_DIR$\..\..\components\dfs\filesystems\net\socket</state>
<state>$PROJ_DIR$\..\..\components\net\lwip-1.4.1\src</state>
<state>$PROJ_DIR$\Libraries\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\include</state>
<state>$PROJ_DIR$\drivers</state>
<state>$PROJ_DIR$\..\..\components\libc\compilers\dlib</state>
<state>$PROJ_DIR$\..\..\components\net\lwip-1.4.1\src\include\netif</state>
<state>$PROJ_DIR$\..\..\libcpu\arm\cortex-m7</state>
<state>$PROJ_DIR$\Libraries\utilities</state>
<state>$PROJ_DIR$\.</state>
<state>$PROJ_DIR$\Libraries</state>
<state>$PROJ_DIR$\applications</state>
<state>$PROJ_DIR$\..\..\components\dfs\filesystems\net\select</state>
<state>$PROJ_DIR$\..\..\components\finsh</state>
<state>$PROJ_DIR$\..\..\components\net\lwip-1.4.1\src\include</state>
<state>$PROJ_DIR$\..\..\components\dfs\include</state>
<state>$PROJ_DIR$\..\..\components\net\lwip-1.4.1\src\include\ipv4</state>
<state>$PROJ_DIR$\..\..\components\drivers\include</state>
<state>$PROJ_DIR$\..\..\components\dfs\filesystems\elmfat</state>
<state>$PROJ_DIR$\..\..\components\libc\pthreads</state>
<state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\arch\include</state>
<state>$PROJ_DIR$\..\..\libcpu\arm\common</state>
<state>$PROJ_DIR$\..\..\components\net\lwip-1.4.1\src\arch\include</state>
<state>$PROJ_DIR$\..\..\components\finsh</state>
<state>$PROJ_DIR$\Libraries\drivers</state>
<state>$PROJ_DIR$\..\..\components\dfs\filesystems\devfs</state>
</option>
<option>
<name>CCStdIncCheck</name>
@ -722,7 +717,7 @@
</option>
<option>
<name>IlinkIcfFile</name>
<state>$PROJ_DIR$\imxrt1052_sdram.icf</state>
<state>$PROJ_DIR$\Libraries\iar\MIMXRT1052xxxxx_flexspi_nor.icf</state>
</option>
<option>
<name>IlinkIcfFileSlave</name>
@ -1245,31 +1240,27 @@
<option>
<name>CCIncludePath2</name>
<state />
<state>$PROJ_DIR$\..\..\components\libc\compilers\dlib</state>
<state>$PROJ_DIR$\Libraries</state>
<state>$PROJ_DIR$\..\..\include</state>
<state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\include\netif</state>
<state>$PROJ_DIR$\..\..\libcpu\arm\common</state>
<state>$PROJ_DIR$\..\..\components\dfs\filesystems\net</state>
<state>$PROJ_DIR$\..\..\components\drivers\include</state>
<state>$PROJ_DIR$\Libraries\drivers</state>
<state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\include</state>
<state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src</state>
<state>$PROJ_DIR$\drivers</state>
<state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\include\ipv4</state>
<state>$PROJ_DIR$\.</state>
<state>$PROJ_DIR$\..\..\libcpu\arm\cortex-m7</state>
<state>$PROJ_DIR$\..\..\components\dfs\include</state>
<state>$PROJ_DIR$\..\..\components\dfs\filesystems\devfs</state>
<state>$PROJ_DIR$\..\..\components\dfs\filesystems\net\socket</state>
<state>$PROJ_DIR$\..\..\components\net\lwip-1.4.1\src</state>
<state>$PROJ_DIR$\Libraries\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\include</state>
<state>$PROJ_DIR$\drivers</state>
<state>$PROJ_DIR$\..\..\components\libc\compilers\dlib</state>
<state>$PROJ_DIR$\..\..\components\net\lwip-1.4.1\src\include\netif</state>
<state>$PROJ_DIR$\..\..\libcpu\arm\cortex-m7</state>
<state>$PROJ_DIR$\Libraries\utilities</state>
<state>$PROJ_DIR$\.</state>
<state>$PROJ_DIR$\Libraries</state>
<state>$PROJ_DIR$\applications</state>
<state>$PROJ_DIR$\..\..\components\dfs\filesystems\net\select</state>
<state>$PROJ_DIR$\..\..\components\finsh</state>
<state>$PROJ_DIR$\..\..\components\net\lwip-1.4.1\src\include</state>
<state>$PROJ_DIR$\..\..\components\dfs\include</state>
<state>$PROJ_DIR$\..\..\components\net\lwip-1.4.1\src\include\ipv4</state>
<state>$PROJ_DIR$\..\..\components\drivers\include</state>
<state>$PROJ_DIR$\..\..\components\dfs\filesystems\elmfat</state>
<state>$PROJ_DIR$\..\..\components\libc\pthreads</state>
<state>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\arch\include</state>
<state>$PROJ_DIR$\..\..\libcpu\arm\common</state>
<state>$PROJ_DIR$\..\..\components\net\lwip-1.4.1\src\arch\include</state>
<state>$PROJ_DIR$\..\..\components\finsh</state>
<state>$PROJ_DIR$\Libraries\drivers</state>
<state>$PROJ_DIR$\..\..\components\dfs\filesystems\devfs</state>
</option>
<option>
<name>CCStdIncCheck</name>
@ -1892,6 +1883,9 @@
<file>
<name>$PROJ_DIR$\applications\main.c</name>
</file>
<file>
<name>$PROJ_DIR$\applications\mem_dump.c</name>
</file>
<file>
<name>$PROJ_DIR$\applications\mem_test.c</name>
</file>
@ -1907,6 +1901,12 @@
<file>
<name>$PROJ_DIR$\drivers\usart.c</name>
</file>
<file>
<name>$PROJ_DIR$\drivers\hyper_flash_boot.c</name>
</file>
<file>
<name>$PROJ_DIR$\drivers\drv_sdram.c</name>
</file>
<file>
<name>$PROJ_DIR$\drivers\drv_eth.c</name>
</file>
@ -2127,7 +2127,7 @@
<name>$PROJ_DIR$\..\..\src\kservice.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\src\mem.c</name>
<name>$PROJ_DIR$\..\..\src\memheap.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\src\object.c</name>
@ -2177,12 +2177,6 @@
<file>
<name>$PROJ_DIR$\..\..\components\dfs\src\dfs_posix.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\components\dfs\src\poll.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\components\dfs\src\select.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\components\dfs\filesystems\devfs\devfs.c</name>
</file>
@ -2192,15 +2186,6 @@
<file>
<name>$PROJ_DIR$\..\..\components\dfs\filesystems\elmfat\ff.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\components\dfs\filesystems\net\dfs_net.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\components\dfs\filesystems\net\net_netdb.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\components\dfs\filesystems\net\net_sockets.c</name>
</file>
</group>
<group>
<name>DeviceDrivers</name>
@ -2329,153 +2314,111 @@
</file>
</group>
<group>
<name>pthreads</name>
<name>LwIP</name>
<file>
<name>$PROJ_DIR$\..\..\components\libc\pthreads\clock_time.c</name>
<name>$PROJ_DIR$\..\..\components\net\lwip-1.4.1\src\api\api_lib.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\components\libc\pthreads\mqueue.c</name>
<name>$PROJ_DIR$\..\..\components\net\lwip-1.4.1\src\api\api_msg.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\components\libc\pthreads\pthread.c</name>
<name>$PROJ_DIR$\..\..\components\net\lwip-1.4.1\src\api\err.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\components\libc\pthreads\pthread_attr.c</name>
<name>$PROJ_DIR$\..\..\components\net\lwip-1.4.1\src\api\netbuf.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\components\libc\pthreads\pthread_barrier.c</name>
<name>$PROJ_DIR$\..\..\components\net\lwip-1.4.1\src\api\netdb.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\components\libc\pthreads\pthread_cond.c</name>
<name>$PROJ_DIR$\..\..\components\net\lwip-1.4.1\src\api\netifapi.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\components\libc\pthreads\pthread_mutex.c</name>
<name>$PROJ_DIR$\..\..\components\net\lwip-1.4.1\src\api\sockets.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\components\libc\pthreads\pthread_rwlock.c</name>
<name>$PROJ_DIR$\..\..\components\net\lwip-1.4.1\src\api\tcpip.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\components\libc\pthreads\pthread_spin.c</name>
<name>$PROJ_DIR$\..\..\components\net\lwip-1.4.1\src\arch\sys_arch.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\components\libc\pthreads\pthread_tls.c</name>
<name>$PROJ_DIR$\..\..\components\net\lwip-1.4.1\src\core\def.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\components\libc\pthreads\sched.c</name>
<name>$PROJ_DIR$\..\..\components\net\lwip-1.4.1\src\core\dhcp.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\components\libc\pthreads\semaphore.c</name>
</file>
</group>
<group>
<name>lwIP</name>
<file>
<name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\arch\sys_arch.c</name>
<name>$PROJ_DIR$\..\..\components\net\lwip-1.4.1\src\core\dns.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\api\api_lib.c</name>
<name>$PROJ_DIR$\..\..\components\net\lwip-1.4.1\src\core\init.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\api\api_msg.c</name>
<name>$PROJ_DIR$\..\..\components\net\lwip-1.4.1\src\core\memp.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\api\err.c</name>
<name>$PROJ_DIR$\..\..\components\net\lwip-1.4.1\src\core\netif.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\api\netbuf.c</name>
<name>$PROJ_DIR$\..\..\components\net\lwip-1.4.1\src\core\pbuf.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\api\netdb.c</name>
<name>$PROJ_DIR$\..\..\components\net\lwip-1.4.1\src\core\raw.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\api\netifapi.c</name>
<name>$PROJ_DIR$\..\..\components\net\lwip-1.4.1\src\core\stats.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\api\sockets.c</name>
<name>$PROJ_DIR$\..\..\components\net\lwip-1.4.1\src\core\sys.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\api\tcpip.c</name>
<name>$PROJ_DIR$\..\..\components\net\lwip-1.4.1\src\core\tcp.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\def.c</name>
<name>$PROJ_DIR$\..\..\components\net\lwip-1.4.1\src\core\tcp_in.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\dns.c</name>
<name>$PROJ_DIR$\..\..\components\net\lwip-1.4.1\src\core\tcp_out.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\inet_chksum.c</name>
<name>$PROJ_DIR$\..\..\components\net\lwip-1.4.1\src\core\timers.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\init.c</name>
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<name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\tcp.c</name>
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</project>

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bsp/imxrt1052-evk/project.ewt
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bsp/imxrt1052-evk/project.uvoptx Normal file
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366
bsp/imxrt1052-evk/project.uvprojx
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@ -10,13 +10,14 @@
<TargetName>RT-Thread IMXRT1052</TargetName>
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<ToolsetName>ARM-ADS</ToolsetName>
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@ -48,12 +49,12 @@
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@ -79,9 +80,9 @@
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<UserProg1Name></UserProg1Name>
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@ -332,10 +333,10 @@
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@ -366,10 +367,10 @@
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<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc> --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab) </Misc>
<Misc>--keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab)</Misc>
<LinkerInputFile></LinkerInputFile>
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@ -389,6 +390,11 @@
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@ -414,6 +420,16 @@
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<File>
<FileName>autoip.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\net\lwip-1.4.1\src\core\ipv4\autoip.c</FilePath>
</File>
<File>
<FileName>icmp.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\net\lwip-2.0.2\src\core\ipv4\icmp.c</FilePath>
<FilePath>..\..\components\net\lwip-1.4.1\src\core\ipv4\icmp.c</FilePath>
</File>
<File>
<FileName>igmp.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\net\lwip-2.0.2\src\core\ipv4\igmp.c</FilePath>
<FilePath>..\..\components\net\lwip-1.4.1\src\core\ipv4\igmp.c</FilePath>
</File>
<File>
<FileName>ip4.c</FileName>
<FileName>inet.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4.c</FilePath>
<FilePath>..\..\components\net\lwip-1.4.1\src\core\ipv4\inet.c</FilePath>
</File>
<File>
<FileName>ip4_addr.c</FileName>
<FileName>inet_chksum.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4_addr.c</FilePath>
<FilePath>..\..\components\net\lwip-1.4.1\src\core\ipv4\inet_chksum.c</FilePath>
</File>
<File>
<FileName>ip4_frag.c</FileName>
<FileName>ip.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4_frag.c</FilePath>
<FilePath>..\..\components\net\lwip-1.4.1\src\core\ipv4\ip.c</FilePath>
</File>
<File>
<FileName>ip_addr.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\net\lwip-1.4.1\src\core\ipv4\ip_addr.c</FilePath>
</File>
<File>
<FileName>ip_frag.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\net\lwip-1.4.1\src\core\ipv4\ip_frag.c</FilePath>
</File>
<File>
<FileName>etharp.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\net\lwip-1.4.1\src\netif\etharp.c</FilePath>
</File>
<File>
<FileName>ethernetif.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\net\lwip-1.4.1\src\netif\ethernetif.c</FilePath>
</File>
<File>
<FileName>slipif.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\net\lwip-1.4.1\src\netif\slipif.c</FilePath>
</File>
</Files>
</Group>

92
bsp/imxrt1052-evk/rtconfig.h
View File

@ -8,12 +8,15 @@
#define RT_NAME_MAX 8
#define RT_ALIGN_SIZE 4
/* RT_THREAD_PRIORITY_8 is not set */
#define RT_THREAD_PRIORITY_32
/* RT_THREAD_PRIORITY_256 is not set */
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 100
#define RT_DEBUG
#define RT_USING_OVERFLOW_CHECK
#define RT_DEBUG_INIT 1
/* RT_DEBUG_THREAD is not set */
#define RT_DEBUG_INIT 0
#define RT_DEBUG_THREAD 0
#define RT_USING_HOOK
#define IDLE_THREAD_STACK_SIZE 256
/* RT_USING_TIMER_SOFT is not set */
@ -30,14 +33,17 @@
/* Memory Management */
/* RT_USING_MEMPOOL is not set */
/* RT_USING_MEMHEAP is not set */
#define RT_USING_HEAP
#define RT_USING_SMALL_MEM
#define RT_USING_MEMHEAP
/* RT_USING_NOHEAP is not set */
/* RT_USING_SMALL_MEM is not set */
/* RT_USING_SLAB is not set */
#define RT_USING_MEMHEAP_AS_HEAP
#define RT_USING_HEAP
/* Kernel Device Object */
#define RT_USING_DEVICE
/* RT_USING_INTERRUPT_INFO is not set */
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
@ -63,16 +69,20 @@
#define FINSH_CMD_SIZE 80
/* FINSH_USING_AUTH is not set */
#define FINSH_USING_MSH
//#define FINSH_USING_MSH_DEFAULT
//#define FINSH_USING_MSH_ONLY
#define FINSH_USING_MSH_DEFAULT
/* FINSH_USING_MSH_ONLY is not set */
/* Device virtual file system */
#define RT_USING_DFS
#define DFS_USING_WORKDIR
#define DFS_FILESYSTEMS_MAX 2
#define DFS_FILESYSTEM_TYPES_MAX 2
#define DFS_FD_MAX 4
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_0
@ -86,7 +96,10 @@
/* RT_DFS_ELM_USE_ERASE is not set */
#define RT_DFS_ELM_REENTRANT
#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_NET
/* RT_USING_DFS_NET is not set */
/* RT_USING_DFS_ROMFS is not set */
/* RT_USING_DFS_RAMFS is not set */
/* RT_USING_DFS_UFFS is not set */
/* RT_USING_DFS_NFS is not set */
/* Device Drivers */
@ -101,27 +114,27 @@
/* RT_USING_MTD_NAND is not set */
/* RT_USING_RTC is not set */
#define RT_USING_SDIO
//#define RT_MMCSD_DBG
/* RT_USING_SPI is not set */
/* RT_USING_WDT is not set */
/* RT_USING_WIFI is not set */
/* Using USB */
/* RT_USING_USB_HOST is not set */
/* RT_USING_USB_DEVICE is not set */
/* POSIX layer and C standard library */
#define RT_USING_LIBC
#define RT_USING_PTHREADS
#define RT_USING_POSIX
/* RT_USING_POSIX_MMAP is not set */
/* RT_USING_POSIX_TERMIOS is not set */
/* RT_USING_PTHREADS is not set */
/* RT_USING_POSIX is not set */
/* Network stack */
/* light weight TCP/IP stack */
#define RT_USING_LWIP
#define RT_USING_LWIP202
//#define RT_LWIP_DEBUG
#define RT_USING_LWIP141
/* RT_USING_LWIP202 is not set */
/* RT_LWIP_IGMP is not set */
#define RT_LWIP_ICMP
@ -131,6 +144,12 @@
#define IP_SOF_BROADCAST 1
#define IP_SOF_BROADCAST_RECV 1
/* LWIP_USING_DHCPD is not set */
/* Static IPv4 Address */
#define RT_LWIP_IPADDR "192.168.1.30"
#define RT_LWIP_GWADDR "192.168.1.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
#define RT_LWIP_UDP
#define RT_LWIP_TCP
/* RT_LWIP_RAW is not set */
@ -156,18 +175,6 @@
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
#define RT_LWIP_IPADDR0 192
#define RT_LWIP_IPADDR1 168
#define RT_LWIP_IPADDR2 10
#define RT_LWIP_IPADDR3 30
#define RT_LWIP_GWADDR0 192
#define RT_LWIP_GWADDR1 168
#define RT_LWIP_GWADDR2 10
#define RT_LWIP_GWADDR3 1
#define RT_LWIP_MSKADDR0 255
#define RT_LWIP_MSKADDR1 255
#define RT_LWIP_MSKADDR2 255
#define RT_LWIP_MSKADDR3 0
/* Modbus master and slave stack */
@ -178,40 +185,59 @@
/* RT_USING_GUIENGINE is not set */
/* VBUS(Virtual Software BUS) */
/* RT_USING_VBUS is not set */
/* Utilities */
/* RT_USING_LOGTRACE is not set */
/* RT_USING_RYM is not set */
/* RT-Thread online packages */
/* system packages */
/* PKG_USING_PARTITION is not set */
/* PKG_USING_SQLITE is not set */
/* PKG_USING_RTI is not set */
/* IoT - internet of things */
/* PKG_USING_CJSON is not set */
/* PKG_USING_PAHOMQTT is not set */
/* PKG_USING_WEBCLIENT is not set */
/* PKG_USING_MONGOOSE is not set */
/* PKG_USING_WEB_TERMINAL is not set */
/* PKG_USING_WEBTERMINAL is not set */
/* PKG_USING_CJSON is not set */
/* PKG_USING_EZXML is not set */
/* PKG_USING_NANOPB is not set */
/* security packages */
/* PKG_USING_MBEDTLS is not set */
/* PKG_USING_libsodium is not set */
/* language packages */
/* PKG_USING_JERRYSCRIPT is not set */
/* PKG_USING_MICROPYTHON is not set */
/* multimedia packages */
/* tools packages */
/* PKG_USING_CMBACKTRACE is not set */
/* PKG_USING_ELOG is not set */
/* PKG_USING_EASYLOGGER is not set */
/* PKG_USING_SYSTEMVIEW is not set */
/* miscellaneous packages */
/* PKG_USING_FASTLZ is not set */
/* PKG_USING_MINILZO is not set */
/* example package: hello */
/* PKG_USING_HELLO is not set */
/* BSP_SPECIAL CONFIG */
#define RT_USING_UART
#define RT_USING_UART1

14
bsp/imxrt1052-evk/rtconfig.py
View File

@ -41,16 +41,18 @@ if PLATFORM == 'gcc':
STRIP = PREFIX + 'strip'
DEVICE = ' -std=c99 -mcpu=cortex-m7 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -ffunction-sections -fdata-sections'
CFLAGS = DEVICE + ' -g -Wall -DUSE_HAL_DRIVER -D__ASSEMBLY__ -D__FPU_USED -eentry'
CFLAGS = DEVICE + ' -g -Wall -DUSE_HAL_DRIVER -D__ASSEMBLY__ -D__FPU_PRESENT -eentry'
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles -Wl,--gc-sections,-Map=imxrt1052_sdram.map,-cref,-u,Reset_Handler -T imxrt1052_sdram.ld'
LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles -Wl,--gc-sections,-Map=imxrt1052_sdram.map,-cref,-u,Reset_Handler -T ./Libraries/gcc/MIMXRT1052xxxxx_flexspi_nor.ld'
CPATH = ''
LPATH = ''
CFLAGS += ' -gdwarf-2'
AFLAGS += ' -gdwarf-2'
if BUILD == 'debug':
CFLAGS += ' -O0 -gdwarf-2'
AFLAGS += ' -gdwarf-2'
CFLAGS += ' -O0'
else:
CFLAGS += ' -O2 -Os'
@ -75,7 +77,7 @@ elif PLATFORM == 'armcc':
DEVICE = ' --cpu Cortex-M7.fp.sp'
CFLAGS = DEVICE + ' --apcs=interwork'
AFLAGS = DEVICE
LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-imxrt.map --scatter imxrt1052_sdram.sct'
LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-imxrt.map --scatter ./Libraries/arm/MIMXRT1052xxxxx_flexspi_nor.scf'
CFLAGS += ' --c99 --diag_suppress=66,1296,186'
CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
@ -126,7 +128,7 @@ elif PLATFORM == 'iar':
AFLAGS += ' --cpu Cortex-M7'
AFLAGS += ' --fpu None'
LFLAGS = ' --config imxrt1052_sdram.icf'
LFLAGS = ' --config ./Libraries/iar/MIMXRT1052xxxxx_flexspi_nor.icf'
LFLAGS += ' --redirect _Printf=_PrintfTiny'
LFLAGS += ' --redirect _Scanf=_ScanfSmall'
LFLAGS += ' --entry __iar_program_start'

311
bsp/imxrt1052-evk/sdram_init.jlinkscript
View File

@ -1,311 +0,0 @@
/*********************************************************************
* SEGGER MICROCONTROLLER GmbH & Co. K.G. *
* Solutions for real time microcontroller applications *
**********************************************************************
* *
* (c) 2011-2015 SEGGER Microcontroller GmbH & Co. KG *
* *
* Internet: www.segger.com Support: support@segger.com *
* *
**********************************************************************
----------------------------------------------------------------------
Purpose :
---------------------------END-OF-HEADER------------------------------
*/
void Clock_Init() {
// Enable all clocks
MEM_WriteU32(0x400FC068,0xffffffff);
MEM_WriteU32(0x400FC06C,0xffffffff);
MEM_WriteU32(0x400FC070,0xffffffff);
MEM_WriteU32(0x400FC074,0xffffffff);
MEM_WriteU32(0x400FC078,0xffffffff);
MEM_WriteU32(0x400FC07C,0xffffffff);
MEM_WriteU32(0x400FC080,0xffffffff);
MEM_WriteU32(0x400D8030,0x00002001);
MEM_WriteU32(0x400D8100,0x00100000);
MEM_WriteU32(0x400FC014,0x00050D40);
Report("Clock Init Done");
}
void SDRAM_WaitIpCmdDone(void)
{
unsigned int reg;
do
{
reg = MEM_ReadU32(0x402F003C);
}while((reg & 0x3) == 0);
}
void SDRAM_Init() {
// Config IOMUX for SDRAM
MEM_WriteU32(0x401F8014,0x00000000);
MEM_WriteU32(0x401F8018,0x00000000);
MEM_WriteU32(0x401F801C,0x00000000);
MEM_WriteU32(0x401F8020,0x00000000);
MEM_WriteU32(0x401F8024,0x00000000);
MEM_WriteU32(0x401F8028,0x00000000);
MEM_WriteU32(0x401F802C,0x00000000);
MEM_WriteU32(0x401F8030,0x00000000);
MEM_WriteU32(0x401F8034,0x00000000);
MEM_WriteU32(0x401F8038,0x00000000);
MEM_WriteU32(0x401F803C,0x00000000);
MEM_WriteU32(0x401F8040,0x00000000);
MEM_WriteU32(0x401F8044,0x00000000);
MEM_WriteU32(0x401F8048,0x00000000);
MEM_WriteU32(0x401F804C,0x00000000);
MEM_WriteU32(0x401F8050,0x00000000);
MEM_WriteU32(0x401F8054,0x00000000);
MEM_WriteU32(0x401F8058,0x00000000);
MEM_WriteU32(0x401F805C,0x00000000);
MEM_WriteU32(0x401F8060,0x00000000);
MEM_WriteU32(0x401F8064,0x00000000);
MEM_WriteU32(0x401F8068,0x00000000);
MEM_WriteU32(0x401F806C,0x00000000);
MEM_WriteU32(0x401F8070,0x00000000);
MEM_WriteU32(0x401F8074,0x00000000);
MEM_WriteU32(0x401F8078,0x00000000);
MEM_WriteU32(0x401F807C,0x00000000);
MEM_WriteU32(0x401F8080,0x00000000);
MEM_WriteU32(0x401F8084,0x00000000);
MEM_WriteU32(0x401F8088,0x00000000);
MEM_WriteU32(0x401F808C,0x00000000);
MEM_WriteU32(0x401F8090,0x00000000);
MEM_WriteU32(0x401F8094,0x00000000);
MEM_WriteU32(0x401F8098,0x00000000);
MEM_WriteU32(0x401F809C,0x00000000);
MEM_WriteU32(0x401F80A0,0x00000000);
MEM_WriteU32(0x401F80A4,0x00000000);
MEM_WriteU32(0x401F80A8,0x00000000);
MEM_WriteU32(0x401F80AC,0x00000000);
MEM_WriteU32(0x401F80B0,0x00000000);
MEM_WriteU32(0x401F80B4,0x00000000);
MEM_WriteU32(0x401F80B8,0x00000000);
// PAD ctrl
MEM_WriteU32(0x401F8204,0x000000F1);
MEM_WriteU32(0x401F8208,0x000000F1);
MEM_WriteU32(0x401F820C,0x000000F1);
MEM_WriteU32(0x401F8210,0x000000F1);
MEM_WriteU32(0x401F8214,0x000000F1);
MEM_WriteU32(0x401F8218,0x000000F1);
MEM_WriteU32(0x401F821C,0x000000F1);
MEM_WriteU32(0x401F8220,0x000000F1);
MEM_WriteU32(0x401F8224,0x000000F1);
MEM_WriteU32(0x401F8228,0x000000F1);
MEM_WriteU32(0x401F822C,0x000000F1);
MEM_WriteU32(0x401F8230,0x000000F1);
MEM_WriteU32(0x401F8234,0x000000F1);
MEM_WriteU32(0x401F8238,0x000000F1);
MEM_WriteU32(0x401F823C,0x000000F1);
MEM_WriteU32(0x401F8240,0x000000F1);
MEM_WriteU32(0x401F8244,0x000000F1);
MEM_WriteU32(0x401F8248,0x000000F1);
MEM_WriteU32(0x401F824C,0x000000F1);
MEM_WriteU32(0x401F8250,0x000000F1);
MEM_WriteU32(0x401F8254,0x000000F1);
MEM_WriteU32(0x401F8258,0x000000F1);
MEM_WriteU32(0x401F825C,0x000000F1);
MEM_WriteU32(0x401F8260,0x000000F1);
MEM_WriteU32(0x401F8264,0x000000F1);
MEM_WriteU32(0x401F8268,0x000000F1);
MEM_WriteU32(0x401F826C,0x000000F1);
MEM_WriteU32(0x401F8270,0x000000F1);
MEM_WriteU32(0x401F8274,0x000000F1);
MEM_WriteU32(0x401F8278,0x000000F1);
MEM_WriteU32(0x401F827C,0x000000F1);
MEM_WriteU32(0x401F8280,0x000000F1);
MEM_WriteU32(0x401F8284,0x000000F1);
MEM_WriteU32(0x401F8288,0x000000F1);
MEM_WriteU32(0x401F828C,0x000000F1);
MEM_WriteU32(0x401F8290,0x000000F1);
MEM_WriteU32(0x401F8294,0x000000F1);
MEM_WriteU32(0x401F8298,0x000000F1);
MEM_WriteU32(0x401F829C,0x000000F1);
MEM_WriteU32(0x401F82A0,0x000000F1);
MEM_WriteU32(0x401F82A4,0x000000F1);
MEM_WriteU32(0x401F82A8,0x000000F1);
// Config SEMC
MEM_WriteU32(0x402F0000,0x1000E000);
MEM_WriteU32(0x402F0008,0x00030524);
MEM_WriteU32(0x402F000C,0x06030524);
MEM_WriteU32(0x402F0010,0x8000001B);
MEM_WriteU32(0x402F0014,0x90000021);
MEM_WriteU32(0x402F0004,0x00000008);
MEM_WriteU32(0x402F0040,0x00000B27);
MEM_WriteU32(0x402F0044,0x00100100);
MEM_WriteU32(0x402F0048,0x00020201);
MEM_WriteU32(0x402F004C,0x08193D0E);
MEM_WriteU32(0x402F0080,0x00000021);
MEM_WriteU32(0x402F0084,0x00888888);
MEM_WriteU32(0x402F0094,0x00000002);
MEM_WriteU32(0x402F0098,0x00000000);
MEM_WriteU32(0x402F0090,0x80000000);
MEM_WriteU32(0x402F009C,0xA55A000F);
SDRAM_WaitIpCmdDone();
MEM_WriteU32(0x402F0090,0x80000000);
MEM_WriteU32(0x402F009C,0xA55A000C);
SDRAM_WaitIpCmdDone();
MEM_WriteU32(0x402F0090,0x80000000);
MEM_WriteU32(0x402F009C,0xA55A000C);
SDRAM_WaitIpCmdDone();
MEM_WriteU32(0x402F00A0,0x00000022);
MEM_WriteU32(0x402F0090,0x80000000);
MEM_WriteU32(0x402F009C,0xA55A000A);
SDRAM_WaitIpCmdDone();
Report("SDRAM Init Done");
}
/* MPU configuration */
void MPU_Init()
{
unsigned int rbar0;
unsigned int rbar1;
unsigned int rbar2;
unsigned int rbar3;
unsigned int rbar4;
unsigned int rbar5;
unsigned int rbar6;
unsigned int rasr0;
unsigned int rasr1;
unsigned int rasr2;
unsigned int rasr3;
unsigned int rasr4;
unsigned int rasr5;
unsigned int rasr6;
unsigned int ctrl;
rbar0 = ((0xC0000000 & ((0x7FFFFFF << 5))) | (1 << 4) | (0 << 0));
rbar1 = ((0x80000000 & ((0x7FFFFFF << 5))) | (1 << 4) | (1 << 0));
rbar2 = ((0x60000000 & ((0x7FFFFFF << 5))) | (1 << 4) | (2 << 0));
rbar3 = ((0x10000000 & ((0x7FFFFFF << 5))) | (1 << 4) | (3 << 0));
rbar4 = ((0x08000000 & ((0x7FFFFFF << 5))) | (1 << 4) | (4 << 0));
rbar5 = ((0x80000000 & ((0x7FFFFFF << 5))) | (1 << 4) | (5 << 0));
rbar6 = ((0x81E00000 & ((0x7FFFFFF << 5))) | (1 << 4) | (6 << 0));
rasr0 = (0x3 << 24) | (2 << 19) | (0xC0 << 8) | (28 << 1) | (1 << 0);
rasr1 = (0x3 << 24) | (2 << 19) | (0xC0 << 8) | (29 << 1) | (1 << 0);
rasr2 = (0x3 << 24) | (2 << 19) | (0xC0 << 8) | (28 << 1) | (1 << 0);
rasr3 = (0x3 << 24) | (2 << 19) | (0xC0 << 8) | (27 << 1) | (1 << 0);
rasr4 = (0x3 << 24) | (2 << 19) | (0xC0 << 8) | (26 << 1) | (1 << 0);
rasr5 = (0x3 << 24) | (3 << 16) | (0xC0 << 8) | (25 << 1) | (1 << 0);
rasr6 = (0x3 << 24) | (1 << 19) | (0xC0 << 8) | (20 << 1) | (1 << 0);
ctrl = (0x1 << 0) | (1 << 2);
/* MPU_CTRL. */
MEM_WriteU32(0xE000ED94, 0x0);
/* MPU_RBAR. */
MEM_WriteU32(0xE000ED9C, rbar6);
/* MPU_RASR. */
MEM_WriteU32(0xE000EDA0, rasr6);
/* MPU_RBAR. */
MEM_WriteU32(0xE000ED9C, rbar5);
/* MPU_RASR. */
MEM_WriteU32(0xE000EDA0, rasr5);
/* MPU_RBAR. */
MEM_WriteU32(0xE000ED9C, rbar4);
/* MPU_RASR. */
MEM_WriteU32(0xE000EDA0, rasr4);
/* MPU_RBAR. */
MEM_WriteU32(0xE000ED9C, rbar3);
/* MPU_RASR. */
MEM_WriteU32(0xE000EDA0, rasr3);
/* MPU_RBAR. */
MEM_WriteU32(0xE000ED9C, rbar2);
/* MPU_RASR. */
MEM_WriteU32(0xE000EDA0, rasr2);
/* MPU_RBAR. */
MEM_WriteU32(0xE000ED9C, rbar1);
/* MPU_RASR. */
MEM_WriteU32(0xE000EDA0, rasr1);
/* MPU_RBAR. */
MEM_WriteU32(0xE000ED9C, rbar0);
/* MPU_RASR. */
MEM_WriteU32(0xE000EDA0, rasr0);
/* MPU_CTRL. */
MEM_WriteU32(0xE000ED94, ctrl);
}
void flexram_init(void)
{
Report("flexram init\n");
MEM_WriteU32(0x400AC040, 0x80000000); //IOMUXC_GPR_GPR16
//MEM_WriteU32(0x400AC044, 0xFFFFAA55); //IOMUXC_GPR_GPR17: 256K ITCM, 128K DTCM, 128K OCRAM
MEM_WriteU32(0x400AC044, 0xFFFFFFFF); //IOMUXC_GPR_GPR17: 512K ITCM
MEM_WriteU32(0x400AC038, 0x00890000); //IOMUXC_GPR_GPR14
MEM_WriteU32(0x400AC040, 0x80000007); //IOMUXC_GPR_GPR16
}
/* ConfigTarget */
void ConfigTargetSettings(void)
{
Report("Config JTAG Speed to 4000kHz");
JTAG_Speed = 4000;
}
/* SetupTarget */
void SetupTarget(void) {
Report("Enabling i.MXRT SDRAM");
Clock_Init();
flexram_init();
SDRAM_Init();
MPU_Init();
}
/* ResetTarget */
void ResetTarget(void) {
unsigned int v;
unsigned int Tmp;
//
// J-Link DLL expects CPU to be reset and halted when leaving this function
//
Report("J-Link script: ResetTarget()");
//issue a software reset
//Tmp = MEM_ReadU32(0xE000ED0C);
//Tmp = (Tmp&0x0000ffff)|0x05fa0000|(1<<2);
//MEM_WriteU32(0xE000ED0C,Tmp);
//SYS_Sleep(10);
// Read IDCODE
v=JLINK_CORESIGHT_ReadDP(0);
Report1("DP0: ", v);
// Power up Debugger
JLINK_CORESIGHT_WriteDP(1, 0x50000000);
v=JLINK_CORESIGHT_ReadDP(1);
Report1("DP1: ", v);
JLINK_CORESIGHT_WriteAP(0, 0x23000042);
v=JLINK_CORESIGHT_ReadAP(0);
Report1("AHB-AP0: ", v);
JLINK_CORESIGHT_WriteAP(1, 0xE000EDF0);
v=JLINK_CORESIGHT_ReadAP(1);
Report1("AHB-AP1: ", v);
v=JLINK_CORESIGHT_ReadAP(3);
Report1("AHB-AP3: ", v);
JLINK_CORESIGHT_WriteAP(3, 0xa05f0003);
v=JLINK_CORESIGHT_ReadAP(3);
Report1("AHB-AP3: ", v);
Clock_Init();
SDRAM_Init();
MPU_Init();
}

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@ -1,236 +0,0 @@
FUNC void SDRAM_WaitIpCmdDone(void)
{
unsigned long reg;
do
{
reg = _RDWORD(0x402F003C);
}while((reg & 0x3) == 0);
}
FUNC void _clock_init(void)
{
// Enable all clocks
_WDWORD(0x400FC068, 0xffffffff);
_WDWORD(0x400FC06C, 0xffffffff);
_WDWORD(0x400FC070, 0xffffffff);
_WDWORD(0x400FC074, 0xffffffff);
_WDWORD(0x400FC078, 0xffffffff);
_WDWORD(0x400FC07C, 0xffffffff);
_WDWORD(0x400FC080, 0xffffffff);
_WDWORD(0x400D8030, 0x00002001);
_WDWORD(0x400D8100, 0x00100000);
_WDWORD(0x400FC014, 0x00050D40);
}
FUNC void _sdr_Init(void)
{
// Config IOMUX
_WDWORD(0x401F8014, 0x00000000);
_WDWORD(0x401F8018, 0x00000000);
_WDWORD(0x401F801C, 0x00000000);
_WDWORD(0x401F8020, 0x00000000);
_WDWORD(0x401F8024, 0x00000000);
_WDWORD(0x401F8028, 0x00000000);
_WDWORD(0x401F802C, 0x00000000);
_WDWORD(0x401F8030, 0x00000000);
_WDWORD(0x401F8034, 0x00000000);
_WDWORD(0x401F8038, 0x00000000);
_WDWORD(0x401F803C, 0x00000000);
_WDWORD(0x401F8040, 0x00000000);
_WDWORD(0x401F8044, 0x00000000);
_WDWORD(0x401F8048, 0x00000000);
_WDWORD(0x401F804C, 0x00000000);
_WDWORD(0x401F8050, 0x00000000);
_WDWORD(0x401F8054, 0x00000000);
_WDWORD(0x401F8058, 0x00000000);
_WDWORD(0x401F805C, 0x00000000);
_WDWORD(0x401F8060, 0x00000000);
_WDWORD(0x401F8064, 0x00000000);
_WDWORD(0x401F8068, 0x00000000);
_WDWORD(0x401F806C, 0x00000000);
_WDWORD(0x401F8070, 0x00000000);
_WDWORD(0x401F8074, 0x00000000);
_WDWORD(0x401F8078, 0x00000000);
_WDWORD(0x401F807C, 0x00000000);
_WDWORD(0x401F8080, 0x00000000);
_WDWORD(0x401F8084, 0x00000000);
_WDWORD(0x401F8088, 0x00000000);
_WDWORD(0x401F808C, 0x00000000);
_WDWORD(0x401F8090, 0x00000000);
_WDWORD(0x401F8094, 0x00000000);
_WDWORD(0x401F8098, 0x00000000);
_WDWORD(0x401F809C, 0x00000000);
_WDWORD(0x401F80A0, 0x00000000);
_WDWORD(0x401F80A4, 0x00000000);
_WDWORD(0x401F80A8, 0x00000000);
_WDWORD(0x401F80AC, 0x00000000);
_WDWORD(0x401F80B0, 0x00000000);
_WDWORD(0x401F80B4, 0x00000000);
_WDWORD(0x401F80B8, 0x00000000);
// PAD ctrl
_WDWORD(0x401F8204, 0x000000F1);
_WDWORD(0x401F8208, 0x000000F1);
_WDWORD(0x401F820C, 0x000000F1);
_WDWORD(0x401F8210, 0x000000F1);
_WDWORD(0x401F8214, 0x000000F1);
_WDWORD(0x401F8218, 0x000000F1);
_WDWORD(0x401F821C, 0x000000F1);
_WDWORD(0x401F8220, 0x000000F1);
_WDWORD(0x401F8224, 0x000000F1);
_WDWORD(0x401F8228, 0x000000F1);
_WDWORD(0x401F822C, 0x000000F1);
_WDWORD(0x401F8230, 0x000000F1);
_WDWORD(0x401F8234, 0x000000F1);
_WDWORD(0x401F8238, 0x000000F1);
_WDWORD(0x401F823C, 0x000000F1);
_WDWORD(0x401F8240, 0x000000F1);
_WDWORD(0x401F8244, 0x000000F1);
_WDWORD(0x401F8248, 0x000000F1);
_WDWORD(0x401F824C, 0x000000F1);
_WDWORD(0x401F8250, 0x000000F1);
_WDWORD(0x401F8254, 0x000000F1);
_WDWORD(0x401F8258, 0x000000F1);
_WDWORD(0x401F825C, 0x000000F1);
_WDWORD(0x401F8260, 0x000000F1);
_WDWORD(0x401F8264, 0x000000F1);
_WDWORD(0x401F8268, 0x000000F1);
_WDWORD(0x401F826C, 0x000000F1);
_WDWORD(0x401F8270, 0x000000F1);
_WDWORD(0x401F8274, 0x000000F1);
_WDWORD(0x401F8278, 0x000000F1);
_WDWORD(0x401F827C, 0x000000F1);
_WDWORD(0x401F8280, 0x000000F1);
_WDWORD(0x401F8284, 0x000000F1);
_WDWORD(0x401F8288, 0x000000F1);
_WDWORD(0x401F828C, 0x000000F1);
_WDWORD(0x401F8290, 0x000000F1);
_WDWORD(0x401F8294, 0x000000F1);
_WDWORD(0x401F8298, 0x000000F1);
_WDWORD(0x401F829C, 0x000000F1);
_WDWORD(0x401F82A0, 0x000000F1);
_WDWORD(0x401F82A4, 0x000000F1);
_WDWORD(0x401F82A8, 0x000000F1);
_WDWORD(0x402F0000, 0x1000E000);
_WDWORD(0x402F0008, 0x00030524);
_WDWORD(0x402F000C, 0x06030524);
_WDWORD(0x402F0010, 0x8000001B);
_WDWORD(0x402F0014, 0x90000021);
_WDWORD(0x402F0004, 0x00000008);
_WDWORD(0x402F0040, 0x00000B27);
_WDWORD(0x402F0044, 0x00100100);
_WDWORD(0x402F0048, 0x00020201);
_WDWORD(0x402F004C, 0x08193D0E);
_WDWORD(0x402F0080, 0x00000021);
_WDWORD(0x402F0084, 0x00888888);
_WDWORD(0x402F0094, 0x00000002);
_WDWORD(0x402F0098, 0x00000000);
_WDWORD(0x402F0090, 0x80000000);
_WDWORD(0x402F009C, 0xA55A000F);
SDRAM_WaitIpCmdDone();
_WDWORD(0x402F0090, 0x80000000);
_WDWORD(0x402F009C, 0xA55A000C);
SDRAM_WaitIpCmdDone();
_WDWORD(0x402F0090, 0x80000000);
_WDWORD(0x402F009C, 0xA55A000C);
SDRAM_WaitIpCmdDone();
_WDWORD(0x402F00A0, 0x00000022);
_WDWORD(0x402F0090, 0x80000000);
_WDWORD(0x402F009C, 0xA55A000A);
SDRAM_WaitIpCmdDone();
}
FUNC void _mpu_Init()
{
unsigned long rbar0, rbar1, rbar2, rbar3, rbar4, rbar5, rbar6;
unsigned long rasr0, rasr1, rasr2, rasr3, rasr4, rasr5, rasr6;
unsigned long ctrl;
rbar0 = ((0xC0000000U & ((0x7FFFFFFUL << 5U))) | (1UL << 4U) | (0U << 0U));
rbar1 = ((0x80000000U & ((0x7FFFFFFUL << 5U))) | (1UL << 4U) | (1U << 0U));
rbar2 = ((0x60000000U & ((0x7FFFFFFUL << 5U))) | (1UL << 4U) | (2U << 0U));
rbar3 = ((0x10000000U & ((0x7FFFFFFUL << 5U))) | (1UL << 4U) | (3U << 0U));
rbar4 = ((0x08000000U & ((0x7FFFFFFUL << 5U))) | (1UL << 4U) | (4U << 0U));
rbar5 = ((0x80000000U & ((0x7FFFFFFUL << 5U))) | (1UL << 4U) | (5U << 0U));
rbar6 = ((0x81E00000U & ((0x7FFFFFFUL << 5U))) | (1UL << 4U) | (6U << 0U));
rasr0 = (0x3U << 24U) | (2UL << 19U) | (0xC0U << 8U) | (28U << 1U) | (1U << 0U);
rasr1 = (0x3U << 24U) | (2UL << 19U) | (0xC0U << 8U) | (29U << 1U) | (1U << 0U);
rasr2 = (0x3U << 24U) | (2UL << 19U) | (0xC0U << 8U) | (28U << 1U) | (1U << 0U);
rasr3 = (0x3U << 24U) | (2UL << 19U) | (0xC0U << 8U) | (27U << 1U) | (1U << 0U);
rasr4 = (0x3U << 24U) | (2UL << 19U) | (0xC0U << 8U) | (26U << 1U) | (1U << 0U);
rasr5 = (0x3U << 24U) | (3UL << 16U) | (0xC0U << 8U) | (25U << 1U) | (1U << 0U);
rasr6 = (0x3U << 24U) | (1UL << 19U) | (0xC0U << 8U) | (20U << 1U) | (1U << 0U);
/* Enable Privileged default memory map and the MPU. */
ctrl = (0x1U << 0) | (1U << 2U);
/* MPU_CTRL. */
_WDWORD(0xE000ED94, 0x0);
/* MPU_RBAR. */
_WDWORD(0xE000ED9C, rbar6);
/* MPU_RASR. */
_WDWORD(0xE000EDA0, rasr6);
/* MPU_RBAR. */
_WDWORD(0xE000ED9C, rbar5);
/* MPU_RASR. */
_WDWORD(0xE000EDA0, rasr5);
_WDWORD(0xE000ED9C, rbar4);
/* MPU_RASR. */
_WDWORD(0xE000EDA0, rasr4);
_WDWORD(0xE000ED9C, rbar3);
/* MPU_RASR. */
_WDWORD(0xE000EDA0, rasr3);
/* MPU_RBAR. */
_WDWORD(0xE000ED9C, rbar2);
/* MPU_RASR. */
_WDWORD(0xE000EDA0, rasr2);
_WDWORD(0xE000ED9C, rbar1);
/* MPU_RASR. */
_WDWORD(0xE000EDA0, rasr1);
_WDWORD(0xE000ED9C, rbar0);
/* MPU_RASR. */
_WDWORD(0xE000EDA0, rasr0);
/* MPU_CTRL. */
_WDWORD(0xE000ED94, ctrl);
}
FUNC void _flexram_init(void)
{
_WDWORD(0x400AC040, 0x80000000); //IOMUXC_GPR_GPR16
//_WDWORD(0x400AC044, 0xFFFFAA55); //IOMUXC_GPR_GPR17
_WDWORD(0x400AC044, 0xFFFFFFFF); //IOMUXC_GPR_GPR17
_WDWORD(0x400AC038, 0x00890000); //IOMUXC_GPR_GPR14
_WDWORD(0x400AC040, 0x80000007); //IOMUXC_GPR_GPR16
}
FUNC void Setup (void) {
_clock_init();
//_flexram_init();
_sdr_Init();
_mpu_Init();
SP = _RDWORD(0x00000000); // Setup Stack Pointer
PC = _RDWORD(0x00000004); // Setup Program Counter
_WDWORD(0xE000ED08, 0x00000000); // Setup Vector Table Offset Register
}
FUNC void OnResetExec (void) { // executes upon software RESET
Setup(); // Setup for Running
}
LOAD %L INCREMENTAL // Download
Setup(); // Setup for Running
// g, main

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/*****************************************************************************/
SDRAM_WaitIpCmdDone()
{
__var reg;
do
{
reg = __readMemory32(0x402F003C, "Memory");
}while((reg & 0x3) == 0);
}
_clock_init()
{
// Enable all clocks
__writeMemory32(0xffffffff, 0x400FC068, "Memory");
__writeMemory32(0xffffffff, 0x400FC06C, "Memory");
__writeMemory32(0xffffffff, 0x400FC070, "Memory");
__writeMemory32(0xffffffff, 0x400FC074, "Memory");
__writeMemory32(0xffffffff, 0x400FC078, "Memory");
__writeMemory32(0xffffffff, 0x400FC07C, "Memory");
__writeMemory32(0xffffffff, 0x400FC080, "Memory");
__writeMemory32(0x00002001, 0x400D8030, "Memory");
__writeMemory32(0x00100000, 0x400D8100, "Memory");
__writeMemory32(0x00050D40, 0x400FC014, "Memory");
}
_sdr_Init()
{
// Config IOMUX
__writeMemory32(0x00000000, 0x401F8014, "Memory");
__writeMemory32(0x00000000, 0x401F8018, "Memory");
__writeMemory32(0x00000000, 0x401F801C, "Memory");
__writeMemory32(0x00000000, 0x401F8020, "Memory");
__writeMemory32(0x00000000, 0x401F8024, "Memory");
__writeMemory32(0x00000000, 0x401F8028, "Memory");
__writeMemory32(0x00000000, 0x401F802C, "Memory");
__writeMemory32(0x00000000, 0x401F8030, "Memory");
__writeMemory32(0x00000000, 0x401F8034, "Memory");
__writeMemory32(0x00000000, 0x401F8038, "Memory");
__writeMemory32(0x00000000, 0x401F803C, "Memory");
__writeMemory32(0x00000000, 0x401F8040, "Memory");
__writeMemory32(0x00000000, 0x401F8044, "Memory");
__writeMemory32(0x00000000, 0x401F8048, "Memory");
__writeMemory32(0x00000000, 0x401F804C, "Memory");
__writeMemory32(0x00000000, 0x401F8050, "Memory");
__writeMemory32(0x00000000, 0x401F8054, "Memory");
__writeMemory32(0x00000000, 0x401F8058, "Memory");
__writeMemory32(0x00000000, 0x401F805C, "Memory");
__writeMemory32(0x00000000, 0x401F8060, "Memory");
__writeMemory32(0x00000000, 0x401F8064, "Memory");
__writeMemory32(0x00000000, 0x401F8068, "Memory");
__writeMemory32(0x00000000, 0x401F806C, "Memory");
__writeMemory32(0x00000000, 0x401F8070, "Memory");
__writeMemory32(0x00000000, 0x401F8074, "Memory");
__writeMemory32(0x00000000, 0x401F8078, "Memory");
__writeMemory32(0x00000000, 0x401F807C, "Memory");
__writeMemory32(0x00000000, 0x401F8080, "Memory");
__writeMemory32(0x00000000, 0x401F8084, "Memory");
__writeMemory32(0x00000000, 0x401F8088, "Memory");
__writeMemory32(0x00000000, 0x401F808C, "Memory");
__writeMemory32(0x00000000, 0x401F8090, "Memory");
__writeMemory32(0x00000000, 0x401F8094, "Memory");
__writeMemory32(0x00000000, 0x401F8098, "Memory");
__writeMemory32(0x00000000, 0x401F809C, "Memory");
__writeMemory32(0x00000000, 0x401F80A0, "Memory");
__writeMemory32(0x00000000, 0x401F80A4, "Memory");
__writeMemory32(0x00000000, 0x401F80A8, "Memory");
__writeMemory32(0x00000000, 0x401F80AC, "Memory");
__writeMemory32(0x00000000, 0x401F80B0, "Memory");
__writeMemory32(0x00000000, 0x401F80B4, "Memory");
__writeMemory32(0x00000000, 0x401F80B8, "Memory");
// PAD ctrl
__writeMemory32(0x000000F1, 0x401F8204, "Memory");
__writeMemory32(0x000000F1, 0x401F8208, "Memory");
__writeMemory32(0x000000F1, 0x401F820C, "Memory");
__writeMemory32(0x000000F1, 0x401F8210, "Memory");
__writeMemory32(0x000000F1, 0x401F8214, "Memory");
__writeMemory32(0x000000F1, 0x401F8218, "Memory");
__writeMemory32(0x000000F1, 0x401F821C, "Memory");
__writeMemory32(0x000000F1, 0x401F8220, "Memory");
__writeMemory32(0x000000F1, 0x401F8224, "Memory");
__writeMemory32(0x000000F1, 0x401F8228, "Memory");
__writeMemory32(0x000000F1, 0x401F822C, "Memory");
__writeMemory32(0x000000F1, 0x401F8230, "Memory");
__writeMemory32(0x000000F1, 0x401F8234, "Memory");
__writeMemory32(0x000000F1, 0x401F8238, "Memory");
__writeMemory32(0x000000F1, 0x401F823C, "Memory");
__writeMemory32(0x000000F1, 0x401F8240, "Memory");
__writeMemory32(0x000000F1, 0x401F8244, "Memory");
__writeMemory32(0x000000F1, 0x401F8248, "Memory");
__writeMemory32(0x000000F1, 0x401F824C, "Memory");
__writeMemory32(0x000000F1, 0x401F8250, "Memory");
__writeMemory32(0x000000F1, 0x401F8254, "Memory");
__writeMemory32(0x000000F1, 0x401F8258, "Memory");
__writeMemory32(0x000000F1, 0x401F825C, "Memory");
__writeMemory32(0x000000F1, 0x401F8260, "Memory");
__writeMemory32(0x000000F1, 0x401F8264, "Memory");
__writeMemory32(0x000000F1, 0x401F8268, "Memory");
__writeMemory32(0x000000F1, 0x401F826C, "Memory");
__writeMemory32(0x000000F1, 0x401F8270, "Memory");
__writeMemory32(0x000000F1, 0x401F8274, "Memory");
__writeMemory32(0x000000F1, 0x401F8278, "Memory");
__writeMemory32(0x000000F1, 0x401F827C, "Memory");
__writeMemory32(0x000000F1, 0x401F8280, "Memory");
__writeMemory32(0x000000F1, 0x401F8284, "Memory");
__writeMemory32(0x000000F1, 0x401F8288, "Memory");
__writeMemory32(0x000000F1, 0x401F828C, "Memory");
__writeMemory32(0x000000F1, 0x401F8290, "Memory");
__writeMemory32(0x000000F1, 0x401F8294, "Memory");
__writeMemory32(0x000000F1, 0x401F8298, "Memory");
__writeMemory32(0x000000F1, 0x401F829C, "Memory");
__writeMemory32(0x000000F1, 0x401F82A0, "Memory");
__writeMemory32(0x000000F1, 0x401F82A4, "Memory");
__writeMemory32(0x000000F1, 0x401F82A8, "Memory");
__writeMemory32(0x1000E000, 0x402F0000, "Memory");
__writeMemory32(0x00030524, 0x402F0008, "Memory");
__writeMemory32(0x06030524, 0x402F000C, "Memory");
__writeMemory32(0x8000001B, 0x402F0010, "Memory");
__writeMemory32(0x90000021, 0x402F0014, "Memory");
__writeMemory32(0x00000008, 0x402F0004, "Memory");
__writeMemory32(0x00000B27, 0x402F0040, "Memory");
__writeMemory32(0x00100100, 0x402F0044, "Memory");
__writeMemory32(0x00020201, 0x402F0048, "Memory");
__writeMemory32(0x08193D0E, 0x402F004C, "Memory");
__writeMemory32(0x00000021, 0x402F0080, "Memory");
__writeMemory32(0x00888888, 0x402F0084, "Memory");
__writeMemory32(0x00000002, 0x402F0094, "Memory");
__writeMemory32(0x00000000, 0x402F0098, "Memory");
__writeMemory32(0x80000000, 0x402F0090, "Memory");
__writeMemory32(0xA55A000F, 0x402F009C, "Memory");
SDRAM_WaitIpCmdDone();
__writeMemory32(0x80000000, 0x402F0090, "Memory");
__writeMemory32(0xA55A000C, 0x402F009C, "Memory");
SDRAM_WaitIpCmdDone();
__writeMemory32(0x80000000, 0x402F0090, "Memory");
__writeMemory32(0xA55A000C, 0x402F009C, "Memory");
SDRAM_WaitIpCmdDone();
__writeMemory32(0x00000022, 0x402F00A0, "Memory");
__writeMemory32(0x80000000, 0x402F0090, "Memory");
__writeMemory32(0xA55A000A, 0x402F009C, "Memory");
SDRAM_WaitIpCmdDone();
__message "SDRAM init done\n";
}
_mpu_Init()
{
__var rbar0, rbar1, rbar2, rbar3, rbar4, rbar5, rbar6;
rbar0 = ((0xC0000000U & ((0x7FFFFFFUL << 5U))) | (1UL << 4U) | (0U << 0U));
rbar1 = ((0x80000000U & ((0x7FFFFFFUL << 5U))) | (1UL << 4U) | (1U << 0U));
rbar2 = ((0x60000000U & ((0x7FFFFFFUL << 5U))) | (1UL << 4U) | (2U << 0U));
rbar3 = ((0x10000000U & ((0x7FFFFFFUL << 5U))) | (1UL << 4U) | (3U << 0U));
rbar4 = ((0x08000000U & ((0x7FFFFFFUL << 5U))) | (1UL << 4U) | (4U << 0U));
rbar5 = ((0x80000000U & ((0x7FFFFFFUL << 5U))) | (1UL << 4U) | (5U << 0U));
rbar6 = ((0x81E00000U & ((0x7FFFFFFUL << 5U))) | (1UL << 4U) | (6U << 0U));
__var rasr0, rasr1, rasr2, rasr3, rasr4, rasr5, rasr6;
rasr0 = (0x3U << 24U) | (2UL << 19U) | (0xC0U << 8U) | (28U << 1U) | (1U << 0U);
rasr1 = (0x3U << 24U) | (2UL << 19U) | (0xC0U << 8U) | (29U << 1U) | (1U << 0U);
rasr2 = (0x3U << 24U) | (2UL << 19U) | (0xC0U << 8U) | (28U << 1U) | (1U << 0U);
rasr3 = (0x3U << 24U) | (2UL << 19U) | (0xC0U << 8U) | (27U << 1U) | (1U << 0U);
rasr4 = (0x3U << 24U) | (2UL << 19U) | (0xC0U << 8U) | (26U << 1U) | (1U << 0U);
rasr5 = (0x3U << 24U) | (3UL << 16U) | (0xC0U << 8U) | (25U << 1U) | (1U << 0U);
rasr6 = (0x3U << 24U) | (1UL << 19U) | (0xC0U << 8U) | (20U << 1U) | (1U << 0U);
/* Enable Privileged default memory map and the MPU. */
__var ctrl;
ctrl = (0x1U << 0) | (1U << 2U);
/* MPU_CTRL. */
__writeMemory32(0x0, 0xE000ED94, "Memory");
/* MPU_RBAR. */
__writeMemory32(rbar6, 0xE000ED9C, "Memory");
/* MPU_RASR. */
__writeMemory32(rasr6, 0xE000EDA0, "Memory");
/* MPU_RBAR. */
__writeMemory32(rbar5, 0xE000ED9C, "Memory");
/* MPU_RASR. */
__writeMemory32(rasr5, 0xE000EDA0, "Memory");
/* MPU_RBAR. */
__writeMemory32(rbar4, 0xE000ED9C, "Memory");
/* MPU_RASR. */
__writeMemory32(rasr4, 0xE000EDA0, "Memory");
/* MPU_RBAR. */
__writeMemory32(rbar3, 0xE000ED9C, "Memory");
/* MPU_RASR. */
__writeMemory32(rasr3, 0xE000EDA0, "Memory");
/* MPU_RBAR. */
__writeMemory32(rbar2, 0xE000ED9C, "Memory");
/* MPU_RASR. */
__writeMemory32(rasr2, 0xE000EDA0, "Memory");
/* MPU_RBAR. */
__writeMemory32(rbar1, 0xE000ED9C, "Memory");
/* MPU_RASR. */
__writeMemory32(rasr1, 0xE000EDA0, "Memory");
/* MPU_RBAR. */
__writeMemory32(rbar0, 0xE000ED9C, "Memory");
/* MPU_RASR. */
__writeMemory32(rasr0, 0xE000EDA0, "Memory");
/* MPU_CTRL. */
__writeMemory32(ctrl, 0xE000ED94, "Memory");
}
_flexram_init()
{
__message "flexram init\n";
__writeMemory32(0x80000000, 0x400AC040, "Memory"); //IOMUXC_GPR_GPR16
//__writeMemory32(0xFFFFAA55, 0x400AC044, "Memory"); //IOMUXC_GPR_GPR17
__writeMemory32(0xFFFFFFFF, 0x400AC044, "Memory"); //IOMUXC_GPR_GPR17
__writeMemory32(0x00890000, 0x400AC038, "Memory"); //IOMUXC_GPR_GPR14
__writeMemory32(0x80000007, 0x400AC040, "Memory"); //IOMUXC_GPR_GPR16
}
execUserPreload()
{
__message "execUserPreload() start.\n";
_clock_init();
_flexram_init();
_sdr_Init();
_mpu_Init();
__message "execUserPreload() done.\n";
}
execUserReset()
{
__message "execUserReset() start.\n";
_clock_init();
_flexram_init();
_sdr_Init();
_mpu_Init();
__message "execUserReset() done.\n";
}

2
bsp/imxrt1052-evk/template.ewp
View File

@ -690,7 +690,7 @@
</option>
<option>
<name>IlinkIcfFile</name>
<state>$PROJ_DIR$\imxrt1052_sdram.icf</state>
<state>$PROJ_DIR$\Libraries\iar\MIMXRT1052xxxxx_flexspi_nor.icf</state>
</option>
<option>
<name>IlinkIcfFileSlave</name>

190
bsp/imxrt1052-evk/template.uvoptx Normal file
View File

@ -0,0 +1,190 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>RT-Thread IMXRT1052</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>12000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\build\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>8</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
<tGomain>1</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>1</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>4</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile>.\Libraries\arm\evkmimxrt1050_flexspi_nor.ini</tIfile>
<pMon>Segger\JL2CM3.dll</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>JL2CM3</Key>
<Name>-U30000299 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST1 -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FCF000 -FN1 -FF0MIMXRT105x_HYPER_256KB_SEC.FLM -FS060000000 -FL04000000 -FP0($$Device:MIMXRT1052$Flash\MIMXRT105x_HYPER_256KB_SEC.FLM)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>CMSIS_AGDI</Key>
<Name>-X"" -O974 -S0 -C0 -P00 -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FCF000 -FN1 -FF0MIMXRT105x_HYPER_256KB_SEC.FLM -FS060000000 -FL04000000 -FP0($$Device:MIMXRT1052$Flash\MIMXRT105x_HYPER_256KB_SEC.FLM)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2CM3</Key>
<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FCF000 -FN1 -FF0MIMXRT105x_HYPER_256KB_SEC -FS060000000 -FL04000000 -FP0($$Device:MIMXRT1052$Flash\MIMXRT105x_HYPER_256KB_SEC.FLM))</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
<trace>0</trace>
<periodic>0</periodic>
<aLwin>0</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>0</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>0</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>0</bLintAuto>
<bAutoGenD>0</bAutoGenD>
<LntExFlags>0</LntExFlags>
<pMisraName></pMisraName>
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
<Group>
<GroupName>::CMSIS</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>1</RteFlg>
</Group>
</ProjectOpt>

13
bsp/imxrt1052-evk/template.uvprojx
View File

@ -16,7 +16,8 @@
<TargetCommonOption>
<Device>MIMXRT1052:M7</Device>
<Vendor>NXP</Vendor>
<PackID>NXP.iMXRT_DFP.1.0.1</PackID>
<PackID>NXP.iMXRT_DFP.1.0.2</PackID>
<PackURL>http://mcuxpresso.nxp.com/cmsis_pack/repo/</PackURL>
<Cpu>IRAM(0x20000000,0x00060000) IRAM2(0x00000000,0x00020000) CPUTYPE("Cortex-M7") FPU3(SFPU) CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
@ -48,12 +49,12 @@
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\build\</OutputDirectory>
<OutputName>rtthread-lpc</OutputName>
<OutputName>rtthread-imxrt</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>0</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>1</BrowseInformation>
<BrowseInformation>0</BrowseInformation>
<ListingPath>.\build\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
@ -79,9 +80,9 @@
<nStopB2X>0</nStopB2X>
</BeforeMake>
<AfterMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg1>1</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg1Name>fromelf --bin !L --output rtthread-mdk.bin</UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
@ -366,7 +367,7 @@
<TextAddressRange>0x00000000</TextAddressRange>
<DataAddressRange>0x10000000</DataAddressRange>
<pXoBase></pXoBase>
<ScatterFile>.\imxrt1052_sdram.sct</ScatterFile>
<ScatterFile>.\Libraries\arm\MIMXRT1052xxxxx_flexspi_nor.scf</ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc></Misc>

10
bsp/lpc178x/applications/application.c
View File

@ -35,6 +35,11 @@
#include <rtgui/driver.h>
#endif
#ifdef RT_USING_FINSH
#include <shell.h>
#include <finsh.h>
#endif
/* thread phase init */
void rt_init_thread_entry(void *parameter)
{
@ -97,6 +102,11 @@ void rt_init_thread_entry(void *parameter)
}
}
#endif
#ifdef RT_USING_FINSH
/* initialize finsh */
finsh_system_init();
#endif
}
// init led

10
bsp/lpc178x/applications/startup.c
View File

@ -20,10 +20,6 @@
#include "board.h"
extern int rt_application_init(void);
#ifdef RT_USING_FINSH
extern int finsh_system_init(void);
extern void finsh_set_device(const char* device);
#endif
#ifdef __CC_ARM
extern int Image$$RW_IRAM1$$ZI$$Limit;
@ -81,12 +77,6 @@ void rtthread_startup(void)
/* initialize application */
rt_application_init();
#ifdef RT_USING_FINSH
/* initialize finsh */
finsh_system_init();
finsh_set_device( FINSH_DEVICE_NAME );
#endif
/* initialize timer */
rt_system_timer_init();

54
bsp/lpc2148/applications/application.c
View File

@ -19,6 +19,11 @@
*/
/*@{*/
#ifdef RT_USING_FINSH
#include <shell.h>
#include <finsh.h>
#endif
#ifdef RT_USING_DFS
/* dfs init */
#include <dfs.h>
@ -41,16 +46,31 @@
/* thread phase init */
void rt_init_thread_entry(void *parameter)
{
#ifdef RT_USING_DEVICE
#ifdef RT_USING_DFS
/* init sd card */
rt_hw_sdcard_init();
#endif
#ifdef RT_USING_LWIP
eth_system_device_init();
/* init ethernetif device */
rt_hw_dm9000_init();
#endif
/* init hardware serial device */
rt_hw_serial_init();
#endif
/* Filesystem Initialization */
#ifdef RT_USING_DFS
{
/* init the device filesystem */
dfs_init();
/* init the efsl filesystam*/
efsl_init();
elm_init();
/* mount sd card fat partition 1 as root directory */
if (dfs_mount("sd0", "/", "efs", 0, 0) == 0)
if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
rt_kprintf("File System initialized!\n");
else
rt_kprintf("File System init failed!\n");
@ -67,6 +87,10 @@ void rt_init_thread_entry(void *parameter)
rt_kprintf("TCP/IP initialized!\n");
}
#endif
#ifdef RT_USING_FINSH
finsh_system_init();
#endif
}
/************** LED BLINK *******************/
@ -78,53 +102,53 @@ void rt_init_thread_entry(void *parameter)
ALIGN(4) char thread_led1_stack[512];
struct rt_thread thread_led1;
void thread_led1_entry(void* parameter)
void thread_led1_entry(void *parameter)
{
unsigned int count=0;
unsigned int count = 0;
IO1DIR |= LED1;
while(1)
while (1)
{
/* led1 on */
IO1CLR = LED1;
#ifndef RT_USING_FINSH
rt_kprintf("led1 on, count : %d\r\n",count);
rt_kprintf("led1 on, count : %d\r\n", count);
#endif
count++;
rt_thread_delay( RT_TICK_PER_SECOND/3 ); /* delay 0.3s */
rt_thread_delay(RT_TICK_PER_SECOND / 3); /* delay 0.3s */
/* led1 off */
IO1SET = LED1;
#ifndef RT_USING_FINSH
rt_kprintf("led1 off\r\n");
#endif
rt_thread_delay( RT_TICK_PER_SECOND/3 );
rt_thread_delay(RT_TICK_PER_SECOND / 3);
}
}
ALIGN(4) char thread_led2_stack[512];
struct rt_thread thread_led2;
void thread_led2_entry(void* parameter)
void thread_led2_entry(void *parameter)
{
unsigned int count=0;
unsigned int count = 0;
IO1DIR |= LED2;
while(1)
while (1)
{
/* led2 on */
IO1CLR = LED2;
#ifndef RT_USING_FINSH
rt_kprintf("led2 on, count : %d\r\n",count);
rt_kprintf("led2 on, count : %d\r\n", count);
#endif
count++;
rt_thread_delay( RT_TICK_PER_SECOND/2 ); /* delay 0.5s */
rt_thread_delay(RT_TICK_PER_SECOND / 2); /* delay 0.5s */
/* led2 off */
IO1SET = LED2;
#ifndef RT_USING_FINSH
rt_kprintf("led1 off\r\n");
#endif
rt_thread_delay( RT_TICK_PER_SECOND/2 );
rt_thread_delay(RT_TICK_PER_SECOND / 2);
}
}
/************** LED BLINK *******************/

35
bsp/lpc2148/applications/startup.c
View File

@ -33,18 +33,11 @@
/*@{*/
#ifdef RT_USING_FINSH
extern int finsh_system_init(void);
#endif
extern int rt_application_init(void);
extern void rt_show_version(void);
#ifdef RT_USING_DEVICE
extern rt_err_t rt_hw_serial_init(void);
#endif
#ifdef RT_USING_FINSH
extern int finsh_system_init(void);
#endif
#ifdef __CC_ARM
extern int Image$$RW_IRAM1$$ZI$$Limit;
@ -76,41 +69,19 @@ void rtthread_startup(void)
#ifdef RT_USING_HEAP
#ifdef __CC_ARM
rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x40008000);
rt_system_heap_init((void *)&Image$$RW_IRAM1$$ZI$$Limit, (void *)0x40008000);
#else
/* init memory system */
rt_system_heap_init((void*)&__bss_end, (void*)0x40008000);
rt_system_heap_init((void *)&__bss_end, (void *)0x40008000);
#endif
#endif
/* init scheduler system */
rt_system_scheduler_init();
#ifdef RT_USING_DEVICE
#ifdef RT_USING_DFS
/* init sd card */
rt_hw_sdcard_init();
#endif
#ifdef RT_USING_LWIP
eth_system_device_init();
/* init ethernetif device */
rt_hw_dm9000_init();
#endif
/* init hardware serial device */
rt_hw_serial_init();
#endif
/* init application */
rt_application_init();
#ifdef RT_USING_FINSH
/* init finsh */
finsh_system_init();
finsh_set_device("uart1");
#endif
/* init idle thread */
rt_thread_idle_init();
@ -121,7 +92,7 @@ void rtthread_startup(void)
return ;
}
int main (void)
int main(void)
{
/* invoke rtthread_startup */
rtthread_startup();

12
bsp/lpc2478/applications/application.c
View File

@ -14,13 +14,23 @@
#include <rtthread.h>
#ifdef RT_USING_FINSH
#include <shell.h>
#include <finsh.h>
#endif
/**
* @addtogroup LPC2478
*/
/*@{*/
int rt_application_init()
{
return 0;
#ifdef RT_USING_FINSH
/* init finsh */
finsh_system_init();
#endif
return 0;
}
/*@}*/

77
bsp/lpc2478/applications/startup.c
View File

@ -16,13 +16,7 @@
#include <rthw.h>
#include <rtthread.h>
#ifdef RT_USING_FINSH
#include <finsh.h>
extern int finsh_system_init(void);
#endif
#include <LPC24xx.h>
#include <board.h>
/**
* @addtogroup LPC2478
@ -30,9 +24,6 @@ extern int finsh_system_init(void);
/*@{*/
extern int rt_application_init(void);
#ifdef RT_USING_DEVICE
extern rt_err_t rt_hw_serial_init(void);
#endif
#ifdef __CC_ARM
extern int Image$$RW_IRAM1$$ZI$$Limit;
@ -45,67 +36,61 @@ extern int __bss_end;
*/
void rtthread_startup(void)
{
/* init hardware interrupt */
rt_hw_interrupt_init();
/* init hardware interrupt */
rt_hw_interrupt_init();
/* init board */
rt_hw_board_init();
/* init board */
rt_hw_board_init();
/* init tick */
rt_system_tick_init();
/* init tick */
rt_system_tick_init();
/* init kernel object */
rt_system_object_init();
/* init kernel object */
rt_system_object_init();
rt_show_version();
rt_show_version();
/* init timer system */
rt_system_timer_init();
/* init timer system */
rt_system_timer_init();
/* init memory system */
/* init memory system */
#ifdef RT_USING_HEAP
#ifdef __CC_ARM
rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x40010000);
rt_system_heap_init((void *)&Image$$RW_IRAM1$$ZI$$Limit, (void *)0x40010000);
#else
rt_system_heap_init((void*)&__bss_end, (void*)0x40010000);
rt_system_heap_init((void *)&__bss_end, (void *)0x40010000);
#endif
#endif
/* init scheduler system */
rt_system_scheduler_init();
/* init scheduler system */
rt_system_scheduler_init();
/* init application */
rt_application_init();
/* init application */
rt_application_init();
#ifdef RT_USING_FINSH
/* init finsh */
finsh_system_init();
finsh_set_device("uart1");
#endif
/* init soft timer thread */
rt_system_timer_thread_init();
/* init soft timer thread */
rt_system_timer_thread_init();
/* init idle thread */
rt_thread_idle_init();
/* init idle thread */
rt_thread_idle_init();
/* start scheduler */
rt_system_scheduler_start();
/* start scheduler */
rt_system_scheduler_start();
/* never reach here */
return ;
/* never reach here */
return ;
}
#ifdef __CC_ARM
int main(void)
{
/* disable interrupt first */
rt_hw_interrupt_disable();
/* disable interrupt first */
rt_hw_interrupt_disable();
/* invoke rtthread_startup */
rtthread_startup();
/* invoke rtthread_startup */
rtthread_startup();
return 0;
return 0;
}
#endif

4
bsp/lpc5410x/applications/application.c
View File

@ -18,16 +18,16 @@
#include <shell.h>
#endif
extern int demo_init(void);
void rt_init_thread_entry(void* parameter)
{
#ifdef RT_USING_FINSH
/* initialization finsh shell Component */
finsh_system_init();
#endif
demo_init();
}
int rt_application_init()

2
bsp/lpc5410x/applications/startup.c
View File

@ -5,7 +5,7 @@
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://openlab.rt-thread.com/license/LICENSE
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes

2
bsp/lpc54608-LPCXpresso/drivers/board.c
View File

@ -80,7 +80,7 @@ void rt_hw_board_init()
#endif
}
#ifdef RT_USING_RTGUI
#ifdef RT_USING_GUIENGINE
#include <rtgui/driver.h>
#include "drv_lcd.h"

8
bsp/lpc824/applications/startup.c
View File

@ -26,11 +26,6 @@
/*@{*/
extern int rt_application_init(void);
#ifdef RT_USING_FINSH
extern int finsh_system_init(void);
extern void finsh_set_device(const char* device);
#endif
/*******************************************************************************
* Function Name : assert_failed
@ -87,8 +82,7 @@ void rtthread_startup(void)
rt_thread_idle_init();
/* start scheduler */
rt_system_scheduler_start();
rt_system_scheduler_start();
/* never reach here */
return ;

252
bsp/simulator/.config Normal file
View File

@ -0,0 +1,252 @@
#
# Automatically generated file; DO NOT EDIT.
# RT-Thread Configuration
#
#
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=8
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32=y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=100
CONFIG_RT_DEBUG=y
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_DEBUG_INIT=0
CONFIG_RT_DEBUG_THREAD=0
CONFIG_RT_USING_HOOK=y
CONFIG_IDLE_THREAD_STACK_SIZE=256
# CONFIG_RT_USING_TIMER_SOFT is not set
#
# Inter-Thread communication
#
CONFIG_RT_USING_SEMAPHORE=y
CONFIG_RT_USING_MUTEX=y
CONFIG_RT_USING_EVENT=y
CONFIG_RT_USING_MAILBOX=y
CONFIG_RT_USING_MESSAGEQUEUE=y
# CONFIG_RT_USING_SIGNALS is not set
#
# Memory Management
#
CONFIG_RT_USING_MEMPOOL=y
# CONFIG_RT_USING_MEMHEAP is not set
# CONFIG_RT_USING_NOHEAP is not set
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
CONFIG_RT_USING_HEAP=y
#
# Kernel Device Object
#
CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="console"
# CONFIG_RT_USING_MODULE is not set
#
# RT-Thread Components
#
# CONFIG_RT_USING_COMPONENTS_INIT is not set
#
# C++ features
#
CONFIG_RT_USING_CPLUSPLUS=y
#
# Command shell
#
CONFIG_RT_USING_FINSH=y
CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_USING_DESCRIPTION=y
CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_CMD_SIZE=80
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_USING_MSH=y
CONFIG_FINSH_USING_MSH_DEFAULT=y
# CONFIG_FINSH_USING_MSH_ONLY is not set
#
# Device virtual file system
#
CONFIG_RT_USING_DFS=y
CONFIG_DFS_USING_WORKDIR=y
CONFIG_DFS_FILESYSTEMS_MAX=2
CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
CONFIG_DFS_FD_MAX=4
CONFIG_RT_USING_DFS_ELMFAT=y
#
# elm-chan's FatFs, Generic FAT Filesystem Module
#
CONFIG_RT_DFS_ELM_CODE_PAGE=437
CONFIG_RT_DFS_ELM_WORD_ACCESS=y
CONFIG_RT_DFS_ELM_USE_LFN_0=y
# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_3 is not set
CONFIG_RT_DFS_ELM_USE_LFN=0
CONFIG_RT_DFS_ELM_MAX_LFN=255
CONFIG_RT_DFS_ELM_DRIVES=2
CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512
# CONFIG_RT_DFS_ELM_USE_ERASE is not set
CONFIG_RT_DFS_ELM_REENTRANT=y
CONFIG_RT_USING_DFS_DEVFS=y
# CONFIG_RT_USING_DFS_NET is not set
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_RAMFS is not set
# CONFIG_RT_USING_DFS_UFFS is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_USING_SERIAL=y
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_I2C is not set
# CONFIG_RT_USING_PIN is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_WIFI is not set
#
# Using USB
#
# CONFIG_RT_USING_USB_HOST is not set
# CONFIG_RT_USING_USB_DEVICE is not set
#
# POSIX layer and C standard library
#
# CONFIG_RT_USING_LIBC is not set
# CONFIG_RT_USING_PTHREADS is not set
#
# Network stack
#
#
# light weight TCP/IP stack
#
# CONFIG_RT_USING_LWIP is not set
#
# Modbus master and slave stack
#
# CONFIG_RT_USING_MODBUS is not set
#
# RT-Thread UI Engine
#
CONFIG_RT_USING_GUIENGINE=y
CONFIG_RTGUI_NAME_MAX=16
# CONFIG_RTGUI_USING_TTF is not set
CONFIG_RTGUI_USING_FONT16=y
CONFIG_RTGUI_USING_FONT12=y
# CONFIG_RTGUI_USING_FONTHZ is not set
# CONFIG_RTGUI_IMAGE_XPM is not set
CONFIG_RTGUI_IMAGE_JPEG_NONE=y
# CONFIG_RTGUI_IMAGE_JPEG is not set
# CONFIG_RTGUI_IMAGE_TJPGD is not set
# CONFIG_RTGUI_IMAGE_PNG_NONE is not set
# CONFIG_RTGUI_IMAGE_PNG is not set
CONFIG_RTGUI_IMAGE_LODEPNG=y
# CONFIG_RTGUI_IMAGE_BMP is not set
CONFIG_RTGUI_IMAGE_CONTAINER=y
CONFIG_RTGUI_USING_DEMO=y
#
# VBUS(Virtual Software BUS)
#
# CONFIG_RT_USING_VBUS is not set
#
# Utilities
#
# CONFIG_RT_USING_LOGTRACE is not set
# CONFIG_RT_USING_RYM is not set
#
# RT-Thread online packages
#
#
# system packages
#
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
#
# IoT - internet of things
#
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_EZXML is not set
# CONFIG_PKG_USING_NANOPB is not set
#
# security packages
#
# CONFIG_PKG_USING_MBEDTLS is not set
# CONFIG_PKG_USING_libsodium is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
#
# language packages
#
# CONFIG_PKG_USING_JERRYSCRIPT is not set
# CONFIG_PKG_USING_MICROPYTHON is not set
#
# multimedia packages
#
# CONFIG_PKG_USING_OPENMV is not set
#
# tools packages
#
# CONFIG_PKG_USING_CMBACKTRACE is not set
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_IPERF is not set
#
# miscellaneous packages
#
# CONFIG_PKG_USING_FASTLZ is not set
# CONFIG_PKG_USING_MINILZO is not set
#
# example package: hello
#
# CONFIG_PKG_USING_HELLO is not set
#
# Privated Packages of RealThread
#
# CONFIG_PKG_USING_CODEC is not set
# CONFIG_PKG_USING_PLAYER is not set
#
# Network Utilities
#
CONFIG_RT_USING_DFS_WINSHAREDIR=y

25
bsp/simulator/Kconfig Normal file
View File

@ -0,0 +1,25 @@
mainmenu "RT-Thread Configuration"
config $BSP_DIR
string
option env="BSP_ROOT"
default "."
config $RTT_DIR
string
option env="RTT_ROOT"
default "../.."
config $PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
if RT_USING_DFS
config RT_USING_DFS_WINSHAREDIR
bool "Enable shared file system between windows"
default n
endif

7
bsp/simulator/applications/application.c
View File

@ -35,6 +35,13 @@ void rt_init_thread_entry(void *parameter)
platform_init();
mnt_init();
#if defined(RT_USING_GUIENGINE) && defined(RTGUI_USING_DEMO)
{
extern int rt_gui_demo_init(void);
rt_gui_demo_init();
}
#endif
}
int rt_application_init()

10
bsp/simulator/applications/platform.c
View File

@ -29,5 +29,15 @@ int platform_init(void)
#endif /* RT_USING_DFS */
#ifdef RT_USING_GUIENGINE
{
extern void rt_hw_sdl_start(void);
extern int rtgui_system_server_init(void);
rtgui_system_server_init();
rt_hw_sdl_start();
}
#endif
return 0;
}

2
bsp/simulator/drivers/SConscript
View File

@ -8,7 +8,7 @@ LIBPATH = []
CPPPATH = [cwd]
# remove no need file.
if GetDepend('RT_USING_RTGUI') == False:
if GetDepend('RT_USING_GUIENGINE') == False:
SrcRemove(src, 'sdl_fb.c')
else:
LIBS.append('SDL')

1
bsp/simulator/drivers/board.c
View File

@ -86,6 +86,7 @@ void rt_hw_exit(void)
#if defined(RT_USING_FINSH)
#include <finsh.h>
FINSH_FUNCTION_EXPORT_ALIAS(rt_hw_exit, exit, exit rt - thread);
FINSH_FUNCTION_EXPORT_ALIAS(rt_hw_exit, __cmd_quit, exit rt-thread);
#endif /* RT_USING_FINSH */
/**

6
bsp/simulator/drivers/module_win32.c
View File

@ -164,15 +164,15 @@ rt_module_t rt_module_find(const char *name)
struct rt_object *object;
struct rt_list_node *node;
extern struct rt_object_information rt_object_container[];
RT_DEBUG_NOT_IN_INTERRUPT;
/* enter critical */
rt_enter_critical();
/* try to find device object */
information = &rt_object_container[RT_Object_Class_Module];
information = rt_object_get_information(RT_Object_Class_Module);
RT_ASSERT(information != RT_NULL);
for (node = information->object_list.next;
node != &(information->object_list);
node = node->next)

10
bsp/simulator/drivers/sdl_fb.c
View File

@ -306,11 +306,11 @@ static void *sdl_loop(void *lpParam)
break;
}
if (quit)
{
exit(1);
break;
}
if (quit)
{
exit(1);
break;
}
}
rt_hw_exit();

386
bsp/simulator/rtconfig.h
View File

@ -1,241 +1,225 @@
/* RT-Thread config file */
#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
#ifndef __RTTHREAD_CFG_H__
#define __RTTHREAD_CFG_H__
/* Automatically generated file; DO NOT EDIT. */
/* RT-Thread Configuration */
// <RDTConfigurator URL="http://www.rt-thread.com/eclipse">
/* RT-Thread Kernel */
// <integer name="RT_NAME_MAX" description="Maximal size of kernel object name length" default="6" />
#define RT_NAME_MAX 6
// <integer name="RT_ALIGN_SIZE" description="Alignment size for CPU architecture data access" default="4" />
#define RT_ALIGN_SIZE 4
// <integer name="RT_THREAD_PRIORITY_MAX" description="Maximal level of thread priority" default="32">
// <item description="8">8</item>
// <item description="32">32</item>
// <item description="256">256</item>
// </integer>
#define RT_THREAD_PRIORITY_MAX 32
// <integer name="RT_TICK_PER_SECOND" description="OS tick per second" default="100" />
#define RT_TICK_PER_SECOND 100
// <section name="RT_DEBUG" description="Kernel Debug Configuration" default="true" >
#define RT_NAME_MAX 8
#define RT_ALIGN_SIZE 4
/* RT_THREAD_PRIORITY_8 is not set */
#define RT_THREAD_PRIORITY_32
/* RT_THREAD_PRIORITY_256 is not set */
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 100
#define RT_DEBUG
// <bool name="RT_THREAD_DEBUG" description="Thread debug enable" default="false" />
// #define RT_THREAD_DEBUG
// <bool name="RT_USING_OVERFLOW_CHECK" description="Thread stack over flow detect" default="true" />
#define RT_USING_OVERFLOW_CHECK
// </section>
// <bool name="RT_USING_HOOK" description="Using hook functions" default="true" />
#define RT_DEBUG_INIT 0
#define RT_DEBUG_THREAD 0
#define RT_USING_HOOK
// <section name="RT_USING_TIMER_SOFT" description="Using software timer which will start a thread to handle soft-timer" default="true" >
// #define RT_USING_TIMER_SOFT
// <integer name="RT_TIMER_THREAD_PRIO" description="The priority level of timer thread" default="4" />
#define RT_TIMER_THREAD_PRIO 4
// <integer name="RT_TIMER_THREAD_STACK_SIZE" description="The stack size of timer thread" default="512" />
#define RT_TIMER_THREAD_STACK_SIZE 512
// </section>
#define IDLE_THREAD_STACK_SIZE 256
/* RT_USING_TIMER_SOFT is not set */
/* Inter-Thread communication */
// <section name="IPC" description="Inter-Thread communication" default="always" >
// <bool name="RT_USING_SEMAPHORE" description="Using semaphore in the system" default="true" />
#define RT_USING_SEMAPHORE
// <bool name="RT_USING_MUTEX" description="Using mutex in the system" default="true" />
#define RT_USING_MUTEX
// <bool name="RT_USING_EVENT" description="Using event group in the system" default="true" />
#define RT_USING_EVENT
// <bool name="RT_USING_MAILBOX" description="Using mailbox in the system" default="true" />
#define RT_USING_MAILBOX
// <bool name="RT_USING_MESSAGEQUEUE" description="Using message queue in the system" default="true" />
#define RT_USING_MESSAGEQUEUE
// </section>
/* RT_USING_SIGNALS is not set */
/* Memory Management */
// <section name="MM" description="Memory Management" default="always" >
// <bool name="RT_USING_MEMPOOL" description="Using Memory Pool Management in the system" default="true" />
#define RT_USING_MEMPOOL
// <bool name="RT_USING_MEMHEAP" description="Using Memory Heap Object in the system" default="true" />
#define RT_USING_MEMHEAP
// <bool name="RT_USING_HEAP" description="Using Dynamic Heap Management in the system" default="true" />
#define RT_USING_HEAP
// <bool name="RT_USING_SMALL_MEM" description="Optimizing for small memory" default="false" />
/* RT_USING_MEMHEAP is not set */
/* RT_USING_NOHEAP is not set */
#define RT_USING_SMALL_MEM
// <bool name="RT_USING_SLAB" description="Using SLAB memory management for large memory" default="false" />
// #define RT_USING_SLAB
// </section>
/* RT_USING_SLAB is not set */
#define RT_USING_HEAP
/* Kernel Device Object */
// <section name="RT_USING_DEVICE" description="Using Device Driver Framework" default="true" >
#define RT_USING_DEVICE
// <bool name="RT_USING_DEVICE_IPC" description="Using Inter-Thread communication for Device" default="true" >
#define RT_USING_DEVICE_IPC
// <bool name="RT_USING_SERIAL" description="Using serial device framework" default="true">
#define RT_USING_SERIAL
// <bool name="RT_USING_UART0" description="Using UART0" default="true" />
#define RT_USING_UART0
// </section>
// <section name="RT_USING_CONSOLE" description="Using console" default="true" >
/* RT_USING_INTERRUPT_INFO is not set */
#define RT_USING_CONSOLE
// <integer name="RT_CONSOLEBUF_SIZE" description="The buffer size for console output" default="128" />
#define RT_CONSOLEBUF_SIZE 128
// <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart" />
#define RT_CONSOLE_DEVICE_NAME "console"
// </section>
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "console"
/* RT_USING_MODULE is not set */
/* RT-Thread Components */
/* RT_USING_COMPONENTS_INIT is not set */
/* C++ features */
#define RT_USING_CPLUSPLUS
/* Command shell */
// <section name="RT_USING_FINSH" description="Using finsh as shell, which is a C-Express shell" default="true" >
#define RT_USING_FINSH
// <bool name="FINSH_USING_SYMTAB" description="Using symbol table in finsh shell" default="true" />
#define FINSH_USING_HISTORY
#define FINSH_USING_SYMTAB
// <bool name="FINSH_USING_DESCRIPTION" description="Keeping description in symbol table" default="true" />
#define FINSH_USING_DESCRIPTION
// <integer name="FINSH_THREAD_STACK_SIZE" description="The stack size for finsh thread" default="4096" />
#define FINSH_THREAD_STACK_SIZE 4096
// <bool name="FINSH_USING_MSH" description="Enable module shell feature" />
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_CMD_SIZE 80
/* FINSH_USING_AUTH is not set */
#define FINSH_USING_MSH
// <bool name="FINSH_USING_MSH_DEFAULT" description="Use module shell as the default shell" />
#define FINSH_USING_MSH_DEFAULT
// </section>
/* FINSH_USING_MSH_ONLY is not set */
// <section name="LIBC" description="C Runtime library setting" default="always" >
// <bool name="RT_USING_LIBC" description="Using C library" default="true" />
// #define RT_USING_LIBC
// <bool name="RT_USING_PTHREADS" description="Using POSIX threads library" default="true" />
// #define RT_USING_PTHREADS
// <bool name="RT_USING_COMPONENTS_INIT" description="Using automatically component initialization." default="true" />
// #define RT_USING_COMPONENTS_INIT
// <bool name="RT_USING_MODULE" description="Enable Moudle Application" default="true" />
// #define RT_USING_MODULE
// </section>
/* Device virtual file system */
// <section name="RT_USING_DFS" description="Device file system" default="true" >
#define RT_USING_DFS
// <bool name="DFS_USING_WORKDIR" description="Using working directory" default="true" />
#define DFS_USING_WORKDIR
// <integer name="DFS_FILESYSTEMS_MAX" description="The maximal number of mounted file system" default="4" />
#define DFS_FILESYSTEMS_MAX 2
// <integer name="DFS_FD_MAX" description="The maximal number of opened files" default="4" />
#define DFS_FD_MAX 4
// <bool name="RT_USING_DFS_ELMFAT" description="Using ELM FatFs" default="true" />
#define DFS_FILESYSTEMS_MAX 2
#define DFS_FILESYSTEM_TYPES_MAX 2
#define DFS_FD_MAX 4
#define RT_USING_DFS_ELMFAT
// <integer name="RT_DFS_ELM_USE_LFN" description="Support long file name" default="0">
// <item description="LFN with static LFN working buffer">1</item>
// <item description="LFN with dynamic LFN working buffer on the stack">2</item>
// <item description="LFN with dynamic LFN working buffer on the heap">3</item>
// </integer>
#define RT_DFS_ELM_USE_LFN 3
// <integer name="RT_DFS_ELM_CODE_PAGE" description="OEM code page" default="437">
#define RT_DFS_ELM_CODE_PAGE 437
// <integer name="RT_DFS_ELM_MAX_LFN" description="Maximal size of file name length" default="255" />
#define RT_DFS_ELM_MAX_LFN 128
// <bool name="RT_USING_DFS_YAFFS2" description="Using YAFFS2" default="false" />
// #define RT_USING_DFS_YAFFS2
// <bool name="RT_USING_DFS_UFFS" description="Using UFFS" default="false" />
// #define RT_USING_DFS_UFFS
// <bool name="RT_USING_DFS_DEVFS" description="Using devfs for device objects" default="true" />
// #define RT_USING_DFS_DEVFS
// <bool name="RT_USING_DFS_NFS" description="Using NFS v3 client file system" default="false" />
// #define RT_USING_DFS_NFS
// <string name="RT_NFS_HOST_EXPORT" description="NFSv3 host export" default="192.168.1.5:/" />
#define RT_NFS_HOST_EXPORT "192.168.1.5:/"
// <bool name="RT_USING_DFS_WINSHAREDIR" description="shared windows file to rtt" default="false" />
#define RT_USING_DFS_WINSHAREDIR
// </section>
// <section name="RT_USING_LWIP" description="lwip, a lightweight TCP/IP protocol stack" default="true" >
// #define RT_USING_LWIP
// <bool name="RT_LWIP_ICMP" description="Enable ICMP protocol" default="true" />
#define RT_LWIP_ICMP
// <bool name="RT_LWIP_IGMP" description="Enable IGMP protocol" default="false" />
// #define RT_LWIP_IGMP
// <bool name="RT_LWIP_UDP" description="Enable UDP protocol" default="true" />
#define RT_LWIP_UDP
// <bool name="RT_LWIP_TCP" description="Enable TCP protocol" default="true" />
#define RT_LWIP_TCP
// <bool name="RT_LWIP_DNS" description="Enable DNS protocol" default="true" />
#define RT_LWIP_DNS
// <bool name="RT_LWIP_SNMP" description="Enable SNMP protocol" default="false" />
// #define RT_LWIP_SNMP
// <bool name="RT_LWIP_DHCP" description="Enable DHCP client to get IP address" default="false" />
// #define RT_LWIP_DHCP
// <integer name="RT_LWIP_TCPTHREAD_PRIORITY" description="the thread priority of TCP thread" default="128" />
#define RT_LWIP_TCPTHREAD_PRIORITY 12
// <integer name="RT_LWIP_TCPTHREAD_MBOX_SIZE" description="the mail box size of TCP thread to wait for" default="32" />
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
// <integer name="RT_LWIP_TCPTHREAD_STACKSIZE" description="the thread stack size of TCP thread" default="4096" />
#define RT_LWIP_TCPTHREAD_STACKSIZE 4096
// <integer name="RT_LWIP_ETHTHREAD_PRIORITY" description="the thread priority of ethnetif thread" default="144" />
#define RT_LWIP_ETHTHREAD_PRIORITY 14
// <integer name="RT_LWIP_ETHTHREAD_MBOX_SIZE" description="the mail box size of ethnetif thread to wait for" default="8" />
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
// <integer name="RT_LWIP_ETHTHREAD_STACKSIZE" description="the stack size of ethnetif thread" default="512" />
#define RT_LWIP_ETHTHREAD_STACKSIZE 512
// <ipaddr name="RT_LWIP_IPADDR" description="IP address of device" default="192.168.1.30" />
#define RT_LWIP_IPADDR0 192
#define RT_LWIP_IPADDR1 168
#define RT_LWIP_IPADDR2 1
#define RT_LWIP_IPADDR3 30
// <ipaddr name="RT_LWIP_GWADDR" description="Gateway address of device" default="192.168.1.1" />
#define RT_LWIP_GWADDR0 192
#define RT_LWIP_GWADDR1 168
#define RT_LWIP_GWADDR2 1
#define RT_LWIP_GWADDR3 1
// <ipaddr name="RT_LWIP_MSKADDR" description="Mask address of device" default="255.255.255.0" />
#define RT_LWIP_MSKADDR0 255
#define RT_LWIP_MSKADDR1 255
#define RT_LWIP_MSKADDR2 255
#define RT_LWIP_MSKADDR3 0
// </section>
/* elm-chan's FatFs, Generic FAT Filesystem Module */
// <section name="RT_USING_RTGUI" description="RT-Thread/GUI" default="true" >
// #define RT_USING_RTGUI
// <integer name="RTGUI_NAME_MAX" description="the name size of RT-Thread/GUI widget/objects" default="12" />
#define RTGUI_NAME_MAX 12
// <bool name="RTGUI_USING_SMALL_SIZE" description="use small size in RT-Thread/GUI" default="true" />
#define RTGUI_USING_SMALL_SIZE
// <bool name="RTGUI_USING_FONT16" description="support 16 weight font" default="true" />
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_0
/* RT_DFS_ELM_USE_LFN_1 is not set */
/* RT_DFS_ELM_USE_LFN_2 is not set */
/* RT_DFS_ELM_USE_LFN_3 is not set */
#define RT_DFS_ELM_USE_LFN 0
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
/* RT_DFS_ELM_USE_ERASE is not set */
#define RT_DFS_ELM_REENTRANT
#define RT_USING_DFS_DEVFS
/* RT_USING_DFS_NET is not set */
/* RT_USING_DFS_ROMFS is not set */
/* RT_USING_DFS_RAMFS is not set */
/* RT_USING_DFS_UFFS is not set */
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_USING_SERIAL
/* RT_USING_CAN is not set */
/* RT_USING_HWTIMER is not set */
/* RT_USING_I2C is not set */
/* RT_USING_PIN is not set */
/* RT_USING_MTD_NOR is not set */
/* RT_USING_MTD_NAND is not set */
/* RT_USING_RTC is not set */
/* RT_USING_SDIO is not set */
/* RT_USING_SPI is not set */
/* RT_USING_WDT is not set */
/* RT_USING_WIFI is not set */
/* Using USB */
/* RT_USING_USB_HOST is not set */
/* RT_USING_USB_DEVICE is not set */
/* POSIX layer and C standard library */
/* RT_USING_LIBC is not set */
/* RT_USING_PTHREADS is not set */
/* Network stack */
/* light weight TCP/IP stack */
/* RT_USING_LWIP is not set */
/* Modbus master and slave stack */
/* RT_USING_MODBUS is not set */
/* RT-Thread UI Engine */
#define RT_USING_GUIENGINE
#define RTGUI_NAME_MAX 16
/* RTGUI_USING_TTF is not set */
#define RTGUI_USING_FONT16
// <bool name="RTGUI_USING_FONT12" description="support 12 weight font" default="true" />
// #define RTGUI_USING_FONT12
// <bool name="RTGUI_USING_FONTHZ" description="support Chinese font" default="true" />
#define RTGUI_USING_FONTHZ
// <integer name="RTGUI_DEFAULT_FONT_SIZE" description="default font size in RT-Thread/GUI" default="16" />
#define RTGUI_DEFAULT_FONT_SIZE 16
// <bool name="RTGUI_USING_DFS_FILERW" description="use RT-Thread/DFS as file interface" default="true" />
#define RTGUI_USING_DFS_FILERW
// <bool name="RTGUI_USING_HZ_BMP" description="use Chinese font bitmap engine" default="true" />
#define RTGUI_USING_HZ_BMP
// <bool name="RTGUI_IMAGE_XPM" description="Using xpm image in RTGUI" default="true" />
#define RTGUI_IMAGE_XPM
// <bool name="RTGUI_IMAGE_JPEG" description="Using jpeg image in RTGUI" default="true" />
// #define RTGUI_IMAGE_JPEG
// <bool name="RTGUI_IMAGE_PNG" description="Using PNG image in RTGUI" default="true" />
// #define RTGUI_IMAGE_PNG
// <bool name="RTGUI_IMAGE_PNG" description="Using PNG image in RTGUI" default="true" />
#define RTGUI_IMAGE_BMP
// <bool name="RTGUI_USING_HZ_FILE" description="use font file as Chinese font" default="false" />
#define RTGUI_USING_HZ_FILE
// <bool name="RTGUI_USING_MOUSE_CURSOR" description="use mouse cursor" default="false" />
#define RTGUI_USING_MOUSE_CURSOR
// </section>
#define RTGUI_USING_FONT12
/* RTGUI_USING_FONTHZ is not set */
/* RTGUI_IMAGE_XPM is not set */
#define RTGUI_IMAGE_JPEG_NONE
/* RTGUI_IMAGE_JPEG is not set */
/* RTGUI_IMAGE_TJPGD is not set */
/* RTGUI_IMAGE_PNG_NONE is not set */
/* RTGUI_IMAGE_PNG is not set */
#define RTGUI_IMAGE_LODEPNG
/* RTGUI_IMAGE_BMP is not set */
#define RTGUI_IMAGE_CONTAINER
#define RTGUI_USING_DEMO
// </RDTConfigurator>
/* VBUS(Virtual Software BUS) */
#define RT_HEAP_SIZE (1024*1024*2)
/* RT_USING_VBUS is not set */
#if defined(_MSC_VER)
#define NORESOURCE //RT_VESRION in winuser.h
#define _CRT_ERRNO_DEFINED //errno macro redefinition
#define _INC_WTIME_INL//dfs_elm.c time.h conflicts with wtime.inl
#define _INC_TIME_INL //dfs_elm.c time.h conflicts with wtime.inl
/* Utilities */
/* disable some warning in MSC */
#pragma warning(disable:4273) /* to ignore: warning C4273: inconsistent dll linkage */
#pragma warning(disable:4312) /* to ignore: warning C4312: 'type cast' : conversion from 'rt_uint32_t' to 'rt_uint32_t *' */
#pragma warning(disable:4311) /* to ignore: warning C4311: 'type cast' : pointer truncation from 'short *__w64 ' to 'long' */
#pragma warning(disable:4996) /* to ignore: warning C4996: The POSIX name for this item is deprecated. */
#pragma warning(disable:4267) /* to ignore: warning C4267: conversion from 'size_t' to 'rt_size_t', possible loss of data */
#pragma warning(disable:4244) /* to ignore: warning C4244: '=' : conversion from '__w64 int' to 'rt_size_t', possible loss of data */
/* RT_USING_LOGTRACE is not set */
/* RT_USING_RYM is not set */
#elif defined(__GNUC__)
#define RT_USING_NOLIBC
/* RT-Thread online packages */
#endif /* end of _MSC_VER */
/* system packages */
/* PKG_USING_PARTITION is not set */
/* PKG_USING_SQLITE is not set */
/* PKG_USING_RTI is not set */
/* IoT - internet of things */
/* PKG_USING_PAHOMQTT is not set */
/* PKG_USING_WEBCLIENT is not set */
/* PKG_USING_MONGOOSE is not set */
/* PKG_USING_WEBTERMINAL is not set */
/* PKG_USING_CJSON is not set */
/* PKG_USING_EZXML is not set */
/* PKG_USING_NANOPB is not set */
/* security packages */
/* PKG_USING_MBEDTLS is not set */
/* PKG_USING_libsodium is not set */
/* PKG_USING_TINYCRYPT is not set */
/* language packages */
/* PKG_USING_JERRYSCRIPT is not set */
/* PKG_USING_MICROPYTHON is not set */
/* multimedia packages */
/* PKG_USING_OPENMV is not set */
/* tools packages */
/* PKG_USING_CMBACKTRACE is not set */
/* PKG_USING_EASYLOGGER is not set */
/* PKG_USING_SYSTEMVIEW is not set */
/* PKG_USING_IPERF is not set */
/* miscellaneous packages */
/* PKG_USING_FASTLZ is not set */
/* PKG_USING_MINILZO is not set */
/* example package: hello */
/* PKG_USING_HELLO is not set */
/* Privated Packages of RealThread */
/* PKG_USING_CODEC is not set */
/* PKG_USING_PLAYER is not set */
/* Network Utilities */
#define RT_USING_DFS_WINSHAREDIR
#include "rtconfig_project.h"
#endif

25
bsp/simulator/rtconfig_project.h Normal file
View File

@ -0,0 +1,25 @@
#ifndef RTCONFIG_PROJECT_H__
#define RTCONFIG_PROJECT_H__
#define RT_HEAP_SIZE (1024*1024*2)
#if defined(_MSC_VER)
#define NORESOURCE //RT_VESRION in winuser.h
#define _CRT_ERRNO_DEFINED //errno macro redefinition
#define _INC_WTIME_INL//dfs_elm.c time.h conflicts with wtime.inl
#define _INC_TIME_INL //dfs_elm.c time.h conflicts with wtime.inl
/* disable some warning in MSC */
#pragma warning(disable:4273) /* to ignore: warning C4273: inconsistent dll linkage */
#pragma warning(disable:4312) /* to ignore: warning C4312: 'type cast' : conversion from 'rt_uint32_t' to 'rt_uint32_t *' */
#pragma warning(disable:4311) /* to ignore: warning C4311: 'type cast' : pointer truncation from 'short *__w64 ' to 'long' */
#pragma warning(disable:4996) /* to ignore: warning C4996: The POSIX name for this item is deprecated. */
#pragma warning(disable:4267) /* to ignore: warning C4267: conversion from 'size_t' to 'rt_size_t', possible loss of data */
#pragma warning(disable:4244) /* to ignore: warning C4244: '=' : conversion from '__w64 int' to 'rt_size_t', possible loss of data */
#elif defined(__GNUC__)
#define RT_USING_NOLIBC
#endif /* end of _MSC_VER */
#endif

4
bsp/stm32f0x/applications/startup.c
View File

@ -25,10 +25,6 @@
/*@{*/
extern int rt_application_init(void);
#ifdef RT_USING_FINSH
extern int finsh_system_init(void);
extern void finsh_set_device(const char* device);
#endif
#ifdef __CC_ARM
extern int Image$$RW_IRAM1$$ZI$$Limit;

20
bsp/stm32f20x/applications/application.c
View File

@ -20,6 +20,11 @@
#include <board.h>
#include <rtthread.h>
#ifdef RT_USING_FINSH
#include <shell.h>
#include <finsh.h>
#endif
#ifdef RT_USING_DFS
/* dfs init */
#include <dfs.h>
@ -41,6 +46,14 @@ void rt_init_thread_entry(void* parameter)
/* Filesystem Initialization */
#ifdef RT_USING_DFS
{
/* init sdcard driver */
#if STM32_USE_SDIO
rt_hw_sdcard_init();
#else
rt_hw_msd_init();
#endif
/* init the device filesystem */
dfs_init();
@ -75,6 +88,13 @@ void rt_init_thread_entry(void* parameter)
rt_kprintf("TCP/IP initialized!\n");
}
#endif
rt_hw_rtc_init();
#ifdef RT_USING_FINSH
/* init finsh */
finsh_system_init();
#endif
}
int rt_application_init()

21
bsp/stm32f20x/applications/startup.c
View File

@ -25,10 +25,6 @@
/*@{*/
extern int rt_application_init(void);
#ifdef RT_USING_FINSH
extern int finsh_system_init(void);
extern void finsh_set_device(const char* device);
#endif
#ifdef __CC_ARM
extern int Image$$RW_IRAM1$$ZI$$Limit;
@ -96,26 +92,9 @@ void rtthread_startup(void)
/* init scheduler system */
rt_system_scheduler_init();
#ifdef RT_USING_DFS
/* init sdcard driver */
#if STM32_USE_SDIO
rt_hw_sdcard_init();
#else
rt_hw_msd_init();
#endif
#endif
rt_hw_rtc_init();
/* init application */
rt_application_init();
#ifdef RT_USING_FINSH
/* init finsh */
finsh_system_init();
finsh_set_device("uart1");
#endif
/* init timer thread */
rt_system_timer_thread_init();

12
bsp/stm32f40x/applications/application.c
View File

@ -23,6 +23,11 @@
#include "stm32f4xx_eth.h"
#endif
#ifdef RT_USING_FINSH
#include <shell.h>
#include <finsh.h>
#endif
#ifdef RT_USING_GDB
#include <gdb_stub.h>
#endif
@ -50,6 +55,11 @@ void rt_init_thread_entry(void* parameter)
rt_kprintf("TCP/IP initialized!\n");
}
#endif
#ifdef RT_USING_FINSH
/* init finsh */
finsh_system_init();
#endif
}
int rt_application_init()
@ -65,5 +75,3 @@ int rt_application_init()
return 0;
}
/*@}*/

10
bsp/stm32f40x/applications/startup.c
View File

@ -26,10 +26,6 @@
/*@{*/
extern int rt_application_init(void);
#ifdef RT_USING_FINSH
extern int finsh_system_init(void);
extern void finsh_set_device(const char* device);
#endif
#ifdef __CC_ARM
extern int Image$$RW_IRAM1$$ZI$$Limit;
@ -88,12 +84,6 @@ void rtthread_startup(void)
/* init application */
rt_application_init();
#ifdef RT_USING_FINSH
/* init finsh */
finsh_system_init();
finsh_set_device( FINSH_DEVICE_NAME );
#endif
/* init timer thread */
rt_system_timer_thread_init();

4
bsp/stm32f429-apollo/applications/startup.c
View File

@ -26,10 +26,6 @@
/*@{*/
extern int rt_application_init(void);
#ifdef RT_USING_FINSH
extern int finsh_system_init(void);
extern void finsh_set_device(const char* device);
#endif
#ifdef __CC_ARM
extern int Image$$RW_IRAM1$$ZI$$Limit;

2
bsp/stm32f429-apollo/drivers/drv_eth.c
View File

@ -589,4 +589,4 @@ static int rt_hw_stm32_eth_init(void)
return state;
}
INIT_DEVICE_EXPORT(rt_hw_stm32_eth_init);
INIT_APP_EXPORT(rt_hw_stm32_eth_init);

15
bsp/stm32f429-apollo/stm32f429_flash.sct Normal file
View File

@ -0,0 +1,15 @@
; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x08000000 0x00100000 { ; load region size_region
ER_IROM1 0x08000000 0x00100000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 0x20000000 0x00030000 { ; RW data
.ANY (+RW +ZI)
}
}

0
bsp/stm32f429_armfly/Libraries/CMSIS/Device/ST/STM32F4xx/Include/stm32f427xx.h → bsp/stm32f429-armfly/Libraries/CMSIS/Device/ST/STM32F4xx/Include/stm32f427xx.h
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0
bsp/stm32f429_armfly/Libraries/CMSIS/Device/ST/STM32F4xx/Include/stm32f429xx.h → bsp/stm32f429-armfly/Libraries/CMSIS/Device/ST/STM32F4xx/Include/stm32f429xx.h
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0
bsp/stm32f429_armfly/Libraries/CMSIS/Device/ST/STM32F4xx/Include/stm32f437xx.h → bsp/stm32f429-armfly/Libraries/CMSIS/Device/ST/STM32F4xx/Include/stm32f437xx.h
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0
bsp/stm32f429_armfly/Libraries/CMSIS/Device/ST/STM32F4xx/Include/stm32f439xx.h → bsp/stm32f429-armfly/Libraries/CMSIS/Device/ST/STM32F4xx/Include/stm32f439xx.h
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0
bsp/stm32f429_armfly/Libraries/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h → bsp/stm32f429-armfly/Libraries/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h
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0
bsp/stm32f429_armfly/Libraries/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h → bsp/stm32f429-armfly/Libraries/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h
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0
bsp/stm32f429_armfly/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f427xx.s → bsp/stm32f429-armfly/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f427xx.s
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0
bsp/stm32f429_armfly/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f429xx.s → bsp/stm32f429-armfly/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f429xx.s
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0
bsp/stm32f429_armfly/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f437xx.s → bsp/stm32f429-armfly/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f437xx.s
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0
bsp/stm32f429_armfly/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f439xx.s → bsp/stm32f429-armfly/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f439xx.s
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0
bsp/stm32f429_armfly/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f427xx.s → bsp/stm32f429-armfly/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f427xx.s
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0
bsp/stm32f429_armfly/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f429xx.s → bsp/stm32f429-armfly/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f429xx.s
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0
bsp/stm32f429_armfly/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f437xx.s → bsp/stm32f429-armfly/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f437xx.s
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0
bsp/stm32f429_armfly/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f439xx.s → bsp/stm32f429-armfly/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f439xx.s
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0
bsp/stm32f429_armfly/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f427xx_flash.icf → bsp/stm32f429-armfly/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f427xx_flash.icf
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0
bsp/stm32f429_armfly/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f427xx_sram.icf → bsp/stm32f429-armfly/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f427xx_sram.icf
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0
bsp/stm32f429_armfly/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f429xx_flash.icf → bsp/stm32f429-armfly/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f429xx_flash.icf
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0
bsp/stm32f429_armfly/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f429xx_sram.icf → bsp/stm32f429-armfly/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f429xx_sram.icf
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0
bsp/stm32f429_armfly/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f437xx_flash.icf → bsp/stm32f429-armfly/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f437xx_flash.icf
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0
bsp/stm32f429_armfly/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f437xx_sram.icf → bsp/stm32f429-armfly/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/linker/stm32f437xx_sram.icf
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0
bsp/stm32f429_armfly/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f427xx.s → bsp/stm32f429-armfly/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f427xx.s
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0
bsp/stm32f429_armfly/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f429xx.s → bsp/stm32f429-armfly/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f429xx.s
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0
bsp/stm32f429_armfly/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f437xx.s → bsp/stm32f429-armfly/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f437xx.s
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0
bsp/stm32f429_armfly/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f439xx.s → bsp/stm32f429-armfly/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f439xx.s
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0
bsp/stm32f429_armfly/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c → bsp/stm32f429-armfly/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c
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0
bsp/stm32f429_armfly/Libraries/CMSIS/Include/arm_common_tables.h → bsp/stm32f429-armfly/Libraries/CMSIS/Include/arm_common_tables.h
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0
bsp/stm32f429_armfly/Libraries/CMSIS/Include/arm_const_structs.h → bsp/stm32f429-armfly/Libraries/CMSIS/Include/arm_const_structs.h
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0
bsp/stm32f429_armfly/Libraries/CMSIS/Include/arm_math.h → bsp/stm32f429-armfly/Libraries/CMSIS/Include/arm_math.h
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0
bsp/stm32f429_armfly/Libraries/CMSIS/Include/cmsis_armcc.h → bsp/stm32f429-armfly/Libraries/CMSIS/Include/cmsis_armcc.h
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0
bsp/stm32f429_armfly/Libraries/CMSIS/Include/cmsis_armcc_V6.h → bsp/stm32f429-armfly/Libraries/CMSIS/Include/cmsis_armcc_V6.h
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0
bsp/stm32f429_armfly/Libraries/CMSIS/Include/cmsis_gcc.h → bsp/stm32f429-armfly/Libraries/CMSIS/Include/cmsis_gcc.h
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0
bsp/stm32f429_armfly/Libraries/CMSIS/Include/core_cm0.h → bsp/stm32f429-armfly/Libraries/CMSIS/Include/core_cm0.h
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0
bsp/stm32f429_armfly/Libraries/CMSIS/Include/core_cm0plus.h → bsp/stm32f429-armfly/Libraries/CMSIS/Include/core_cm0plus.h
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0
bsp/stm32f429_armfly/Libraries/CMSIS/Include/core_cm3.h → bsp/stm32f429-armfly/Libraries/CMSIS/Include/core_cm3.h
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0
bsp/stm32f429_armfly/Libraries/CMSIS/Include/core_cm4.h → bsp/stm32f429-armfly/Libraries/CMSIS/Include/core_cm4.h
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0
bsp/stm32f429_armfly/Libraries/CMSIS/Include/core_cm7.h → bsp/stm32f429-armfly/Libraries/CMSIS/Include/core_cm7.h
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