diff --git a/README.md b/README.md index 65e9422658..41824d6ca6 100644 --- a/README.md +++ b/README.md @@ -17,13 +17,13 @@ RT-Thread RTOS like a traditional real-time operating system. The kernel has rea * Device Driver; * Component; -* Dyanmic Module +* Dynamic Module The device driver is more like a driver framework, UART, IIC, SPI, SDIO, USB device/host, EMAC, MTD NAND etc. The developer can easily add low level driver and board configuration, then combined with the upper framework, he/she can use lots of features. The Component is a software concept upon RT-Thread kernel, for example a shell (finsh/msh shell), virtual file system (FAT, YAFFS, UFFS, ROM/RAM file system etc), TCP/IP protocol stack (lwIP), POSIX (thread) interface etc. One component must be a directory under RT-Thread/Components and one component can be descripted by a SConscript file (then be compiled and linked into the system). -The Dyanmic Module, formerly named as User Applicaion (UA) is a dyanmic loaded module or library, it can be compiled standalone without Kernel. Each Dyanmic Module has its own object list to manage thread/semaphore/kernel object which was created or initialized inside this UA. More information about UA, please visit another [git repo](https://github.com/RT-Thread/rtthread-apps). +The Dynamic Module, formerly named as User Applicaion (UA) is a dynamic loaded module or library, it can be compiled standalone without Kernel. Each Dynamic Module has its own object list to manage thread/semaphore/kernel object which was created or initialized inside this UA. More information about UA, please visit another [git repo](https://github.com/RT-Thread/rtthread-apps). ## Board Support Package ## diff --git a/bsp/allwinner_tina/libcpu/interrupt.c b/bsp/allwinner_tina/libcpu/interrupt.c index b32a331c60..14f53b6881 100644 --- a/bsp/allwinner_tina/libcpu/interrupt.c +++ b/bsp/allwinner_tina/libcpu/interrupt.c @@ -102,6 +102,7 @@ void rt_hw_interrupt_mask(int vector) } /** + * This function will un-mask a interrupt. * @param vector the interrupt number */ @@ -167,7 +168,7 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, return old_handler; } -void rt_interrupt_dispatch(void) +void rt_interrupt_dispatch(rt_uint32_t fiq_irq) { void *param; int vector; diff --git a/bsp/at91sam9g45/drivers/board.c b/bsp/at91sam9g45/drivers/board.c index c14055f310..59ac3f1ba4 100644 --- a/bsp/at91sam9g45/drivers/board.c +++ b/bsp/at91sam9g45/drivers/board.c @@ -36,8 +36,8 @@ extern int Image$$ER_ZI$$ZI$$Limit; #define HEAP_BEGIN (&Image$$ER_ZI$$ZI$$Limit) #elif (defined (__GNUC__)) -extern unsigned char __bss_end__; -#define HEAP_BEGIN (&__bss_end__) +extern unsigned char __bss_end; +#define HEAP_BEGIN (&__bss_end) #elif (defined (__ICCARM__)) #pragma section=".noinit" #define HEAP_BEGIN (__section_end(".noinit")) diff --git a/bsp/at91sam9g45/link_scripts/at91sam9g45_ram.ld b/bsp/at91sam9g45/link_scripts/at91sam9g45_ram.ld index a0dd88e868..ca159b7cd4 100644 --- a/bsp/at91sam9g45/link_scripts/at91sam9g45_ram.ld +++ b/bsp/at91sam9g45/link_scripts/at91sam9g45_ram.ld @@ -1,6 +1,6 @@ OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") OUTPUT_ARCH(arm) -ENTRY(start) +ENTRY(system_vectors) SECTIONS { . = 0x70000000; @@ -8,7 +8,7 @@ SECTIONS . = ALIGN(4); .text : { - *(.init) + *(.vectors) *(.text) *(.gnu.linkonce.t*) @@ -76,9 +76,9 @@ SECTIONS .nobss : { *(.nobss) } . = ALIGN(4); - __bss_start__ = .; + __bss_start = .; .bss : { *(.bss)} - __bss_end__ = .; + __bss_end = .; /* stabs debugging sections. */ .stab 0 : { *(.stab) } diff --git a/bsp/at91sam9g45/platform/interrupt.c b/bsp/at91sam9g45/platform/interrupt.c index b19bcb3bde..9f7cabf3f8 100644 --- a/bsp/at91sam9g45/platform/interrupt.c +++ b/bsp/at91sam9g45/platform/interrupt.c @@ -332,7 +332,7 @@ void rt_hw_interrupt_umask(int irq) * @return old handler */ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, - void *param, char *name) + void *param, const char *name) { rt_isr_handler_t old_handler = RT_NULL; @@ -419,6 +419,29 @@ void rt_hw_interrupt_ack(rt_uint32_t fiq_irq, rt_uint32_t id) AT91C_BASE_AIC->AIC_EOICR = 0x0; } +void rt_interrupt_dispatch(rt_uint32_t fiq_irq) +{ + rt_isr_handler_t isr_func; + rt_uint32_t irq; + void *param; + + /* get irq number */ + irq = rt_hw_interrupt_get_active(fiq_irq); + + /* get interrupt service routine */ + isr_func = irq_desc[irq].handler; + param = irq_desc[irq].param; + + /* turn to interrupt service routine */ + isr_func(irq, param); + + rt_hw_interrupt_ack(fiq_irq, irq); +#ifdef RT_USING_INTERRUPT_INFO + irq_desc[irq].counter ++; +#endif +} + + #ifdef RT_USING_FINSH #ifdef RT_USING_INTERRUPT_INFO void list_irq(void) diff --git a/bsp/at91sam9g45/rtconfig.py b/bsp/at91sam9g45/rtconfig.py index 3684b54578..bd29b56f4f 100644 --- a/bsp/at91sam9g45/rtconfig.py +++ b/bsp/at91sam9g45/rtconfig.py @@ -10,7 +10,7 @@ if os.getenv('RTT_CC'): if CROSS_TOOL == 'gcc': PLATFORM = 'gcc' - EXEC_PATH = r'D:\arm-2013.11\bin' + EXEC_PATH = '/usr/bin' elif CROSS_TOOL == 'keil': PLATFORM = 'armcc' EXEC_PATH = 'C:/Keil_v5' diff --git a/bsp/es32f0334/drivers/board.h b/bsp/es32f0334/drivers/board.h index d51b0318ed..95f22c2c1c 100644 --- a/bsp/es32f0334/drivers/board.h +++ b/bsp/es32f0334/drivers/board.h @@ -17,7 +17,7 @@ #define ES32F0_SRAM_SIZE 0x8000 #define ES32F0_SRAM_END (0x20000000 + ES32F0_SRAM_SIZE) -#ifdef __CC_ARM +#if defined(__CC_ARM) || defined(__CLANG_ARM) extern int Image$$RW_IRAM1$$ZI$$Limit; #define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) #elif __ICCARM__ diff --git a/bsp/es32f0334/drivers/drv_pm.c b/bsp/es32f0334/drivers/drv_pm.c index f9324d7208..22f2c43073 100644 --- a/bsp/es32f0334/drivers/drv_pm.c +++ b/bsp/es32f0334/drivers/drv_pm.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2019-04-08 wangyq the first version + * 2019-05-06 Zero-Free adapt to the new power management interface */ #include @@ -16,54 +17,28 @@ #ifdef RT_USING_PM -static void _drv_pm_enter(struct rt_pm *pm) +static void _drv_pm_enter(struct rt_pm *pm, uint8_t mode) { - rt_uint32_t mode; - - mode = pm->current_mode; - switch (mode) { - case PM_RUN_MODE_NORMAL: + case PM_SLEEP_MODE_NONE: break; - case PM_SLEEP_MODE_SLEEP: + case PM_SLEEP_MODE_IDLE: __WFI(); break; - case PM_SLEEP_MODE_TIMER: + case PM_SLEEP_MODE_LIGHT: + break; + + case PM_SLEEP_MODE_DEEP: pmu_stop2_enter(); break; - case PM_SLEEP_MODE_SHUTDOWN: + case PM_SLEEP_MODE_STANDBY: pmu_standby_enter(PMU_STANDBY_PORT_NONE); break; - default: - RT_ASSERT(0); - break; - } -} - -static void _drv_pm_exit(struct rt_pm *pm) -{ - rt_uint32_t mode; - - RT_ASSERT(pm != RT_NULL); - - mode = pm->current_mode; - - switch (mode) - { - case PM_RUN_MODE_NORMAL: - break; - - case PM_SLEEP_MODE_SLEEP: - break; - - case PM_SLEEP_MODE_TIMER: - break; - case PM_SLEEP_MODE_SHUTDOWN: break; @@ -73,32 +48,21 @@ static void _drv_pm_exit(struct rt_pm *pm) } } -#if PM_RUN_MODE_COUNT > 1 -static void _drv_pm_frequency_change(struct rt_pm *pm, rt_uint32_t frequency) -{ - return; -} -#endif - static int drv_hw_pm_init(void) { static const struct rt_pm_ops _ops = { _drv_pm_enter, - _drv_pm_exit, - -#if PM_RUN_MODE_COUNT > 1 - _drv_pm_frequency_change, -#endif + RT_NULL, RT_NULL, RT_NULL, RT_NULL }; - rt_uint8_t timer_mask; + rt_uint8_t timer_mask = 0; - /* initialize timer mask */ - timer_mask = 1UL << PM_SLEEP_MODE_TIMER; + /* initialize timer mask(no need tickless) */ + // timer_mask = 1UL << PM_SLEEP_MODE_DEEP; /* initialize system pm module */ rt_system_pm_init(&_ops, timer_mask, RT_NULL); diff --git a/bsp/es32f0654/drivers/board.h b/bsp/es32f0654/drivers/board.h index 08c221a2d9..5b969142ac 100644 --- a/bsp/es32f0654/drivers/board.h +++ b/bsp/es32f0654/drivers/board.h @@ -17,7 +17,7 @@ #define ES32F0_SRAM_SIZE 0x8000 #define ES32F0_SRAM_END (0x20000000 + ES32F0_SRAM_SIZE) -#ifdef __CC_ARM +#if defined(__CC_ARM) || defined(__CLANG_ARM) extern int Image$$RW_IRAM1$$ZI$$Limit; #define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) #elif __ICCARM__ diff --git a/bsp/es32f0654/drivers/drv_pm.c b/bsp/es32f0654/drivers/drv_pm.c index 256634b81d..aa2f07ec68 100644 --- a/bsp/es32f0654/drivers/drv_pm.c +++ b/bsp/es32f0654/drivers/drv_pm.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2019-04-01 wangyq the first version + * 2019-05-06 Zero-Free adapt to the new power management interface */ #include @@ -16,54 +17,28 @@ #ifdef RT_USING_PM -static void _drv_pm_enter(struct rt_pm *pm) +static void _drv_pm_enter(struct rt_pm *pm, uint8_t mode) { - rt_uint32_t mode; - - mode = pm->current_mode; - switch (mode) { - case PM_RUN_MODE_NORMAL: + case PM_SLEEP_MODE_NONE: break; - case PM_SLEEP_MODE_SLEEP: + case PM_SLEEP_MODE_IDLE: __WFI(); break; - case PM_SLEEP_MODE_TIMER: + case PM_SLEEP_MODE_LIGHT: + break; + + case PM_SLEEP_MODE_DEEP: pmu_stop2_enter(); break; - case PM_SLEEP_MODE_SHUTDOWN: + case PM_SLEEP_MODE_STANDBY: pmu_standby_enter(PMU_STANDBY_PORT_NONE); break; - default: - RT_ASSERT(0); - break; - } -} - -static void _drv_pm_exit(struct rt_pm *pm) -{ - rt_uint32_t mode; - - RT_ASSERT(pm != RT_NULL); - - mode = pm->current_mode; - - switch (mode) - { - case PM_RUN_MODE_NORMAL: - break; - - case PM_SLEEP_MODE_SLEEP: - break; - - case PM_SLEEP_MODE_TIMER: - break; - case PM_SLEEP_MODE_SHUTDOWN: break; @@ -73,32 +48,21 @@ static void _drv_pm_exit(struct rt_pm *pm) } } -#if PM_RUN_MODE_COUNT > 1 -static void _drv_pm_frequency_change(struct rt_pm *pm, rt_uint32_t frequency) -{ - return; -} -#endif - static int drv_hw_pm_init(void) { static const struct rt_pm_ops _ops = { _drv_pm_enter, - _drv_pm_exit, - -#if PM_RUN_MODE_COUNT > 1 - _drv_pm_frequency_change, -#endif + RT_NULL, RT_NULL, RT_NULL, RT_NULL }; - rt_uint8_t timer_mask; + rt_uint8_t timer_mask = 0; - /* initialize timer mask */ - timer_mask = 1UL << PM_SLEEP_MODE_TIMER; + /* initialize timer mask(no need tickless) */ + timer_mask = 1UL << PM_SLEEP_MODE_DEEP; /* initialize system pm module */ rt_system_pm_init(&_ops, timer_mask, RT_NULL); diff --git a/bsp/gd32e230k-start/drivers/board.h b/bsp/gd32e230k-start/drivers/board.h index 5097fb169e..abc8743562 100644 --- a/bsp/gd32e230k-start/drivers/board.h +++ b/bsp/gd32e230k-start/drivers/board.h @@ -25,7 +25,7 @@ extern char __ICFEDIT_region_RAM_end__; #define GD32_SRAM_END (0x20000000 + GD32_SRAM_SIZE * 1024) #endif -#ifdef __ARMCC_VERSION +#if defined(__CC_ARM) || defined(__CLANG_ARM) extern int Image$$RW_IRAM1$$ZI$$Limit; #define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) #elif __ICCARM__ diff --git a/bsp/k210/.config b/bsp/k210/.config index c7594a6301..d5d8b9eb1b 100644 --- a/bsp/k210/.config +++ b/bsp/k210/.config @@ -7,6 +7,7 @@ # RT-Thread Kernel # CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set CONFIG_RT_USING_SMP=y CONFIG_RT_CPUS_NR=2 CONFIG_RT_ALIGN_SIZE=8 @@ -19,7 +20,7 @@ CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDEL_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=1024 +CONFIG_IDLE_THREAD_STACK_SIZE=4096 # CONFIG_RT_USING_TIMER_SOFT is not set CONFIG_RT_DEBUG=y CONFIG_RT_DEBUG_COLOR=y @@ -43,7 +44,7 @@ CONFIG_RT_USING_MUTEX=y CONFIG_RT_USING_EVENT=y CONFIG_RT_USING_MAILBOX=y CONFIG_RT_USING_MESSAGEQUEUE=y -# CONFIG_RT_USING_SIGNALS is not set +CONFIG_RT_USING_SIGNALS=y # # Memory Management @@ -139,6 +140,7 @@ CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set CONFIG_RT_USING_SERIAL=y CONFIG_RT_SERIAL_USING_DMA=y CONFIG_RT_SERIAL_RB_BUFSZ=64 @@ -202,6 +204,11 @@ CONFIG_RT_USING_POSIX=y # # CONFIG_RT_USING_SAL is not set +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + # # light weight TCP/IP stack # @@ -225,7 +232,6 @@ CONFIG_RT_USING_POSIX=y # # Utilities # -# CONFIG_RT_USING_LOGTRACE is not set # CONFIG_RT_USING_RYM is not set # CONFIG_RT_USING_ULOG is not set # CONFIG_RT_USING_UTEST is not set @@ -267,6 +273,7 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set # CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set # CONFIG_PKG_USING_WIZNET is not set # @@ -279,6 +286,7 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_TENCENT_IOTKIT is not set # CONFIG_PKG_USING_NIMBLE is not set # CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set # # security packages @@ -299,6 +307,7 @@ CONFIG_RT_USING_POSIX=y # # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set # # tools packages @@ -327,39 +336,34 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_CMSIS is not set # CONFIG_PKG_USING_DFS_YAFFS is not set # CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_THREAD_POOL is not set # # peripheral libraries and drivers # - -# -# sensors drivers -# -# CONFIG_PKG_USING_LSM6DSL is not set -# CONFIG_PKG_USING_LPS22HB is not set -# CONFIG_PKG_USING_HTS221 is not set -# CONFIG_PKG_USING_LSM303AGR is not set -# CONFIG_PKG_USING_BME280 is not set -# CONFIG_PKG_USING_BMA400 is not set -# CONFIG_PKG_USING_BMI160_BMX160 is not set -# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_SHT2X is not set -# CONFIG_PKG_USING_AHT10 is not set # CONFIG_PKG_USING_AP3216C is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ICM20608 is not set # CONFIG_PKG_USING_U8G2 is not set # CONFIG_PKG_USING_BUTTON is not set -# CONFIG_PKG_USING_MPU6XXX is not set # CONFIG_PKG_USING_PCF8574 is not set # CONFIG_PKG_USING_SX12XX is not set -# CONFIG_PKG_USING_SIGNAL_LED is not set CONFIG_PKG_USING_KENDRYTE_SDK=y CONFIG_PKG_KENDRYTE_SDK_PATH="/packages/peripherals/kendryte-sdk" -CONFIG_PKG_USING_KENDRYTE_SDK_V052=y +# CONFIG_PKG_USING_KENDRYTE_SDK_V052 is not set +# CONFIG_PKG_USING_KENDRYTE_SDK_V053 is not set +# CONFIG_PKG_USING_KENDRYTE_SDK_V054 is not set +CONFIG_PKG_USING_KENDRYTE_SDK_V055=y # CONFIG_PKG_USING_KENDRYTE_SDK_LATEST_VERSION is not set -CONFIG_PKG_KENDRYTE_SDK_VER="v0.5.2" +CONFIG_PKG_KENDRYTE_SDK_VER="v0.5.5" +CONFIG_PKG_KENDRYTE_SDK_VERNUM=0x0055 +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set # # miscellaneous packages @@ -385,6 +389,34 @@ CONFIG_PKG_KENDRYTE_SDK_VER="v0.5.2" # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set # CONFIG_PKG_USING_HELLO is not set # CONFIG_PKG_USING_VI is not set + +# +# Privated Packages of RealThread +# +# CONFIG_PKG_USING_CODEC is not set +# CONFIG_PKG_USING_PLAYER is not set +# CONFIG_PKG_USING_MPLAYER is not set +# CONFIG_PKG_USING_PERSIMMON_SRC is not set +# CONFIG_PKG_USING_JS_PERSIMMON is not set +# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set + +# +# Network Utilities +# +# CONFIG_PKG_USING_WICED is not set +# CONFIG_PKG_USING_CLOUDSDK is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_POWER_MANAGER is not set +# CONFIG_PKG_USING_RT_OTA is not set +# CONFIG_PKG_USING_RDBD_SRC is not set +# CONFIG_PKG_USING_RTINSIGHT is not set +# CONFIG_PKG_USING_SMARTCONFIG is not set +# CONFIG_PKG_USING_RTX is not set +# CONFIG_RT_USING_TESTCASE is not set +# CONFIG_PKG_USING_NGHTTP2 is not set +# CONFIG_PKG_USING_AVS is not set +# CONFIG_PKG_USING_STS is not set +# CONFIG_PKG_USING_DLMS is not set CONFIG_BOARD_K210_EVB=y CONFIG_BSP_USING_UART_HS=y # CONFIG_BSP_USING_UART1 is not set diff --git a/bsp/k210/driver/board.h b/bsp/k210/driver/board.h index 0d270abd2b..c1e20e9856 100644 --- a/bsp/k210/driver/board.h +++ b/bsp/k210/driver/board.h @@ -11,6 +11,12 @@ #ifndef BOARD_H__ #define BOARD_H__ +#include + +#if PKG_KENDRYTE_SDK_VERNUM < 0x0054 +#error The version of Kendryte sdk is too old, please update to V0.5.4 or newer +#endif + extern unsigned int __bss_start; extern unsigned int __bss_end; diff --git a/bsp/k210/rtconfig.h b/bsp/k210/rtconfig.h index e23e86aeb8..73a2e8c597 100644 --- a/bsp/k210/rtconfig.h +++ b/bsp/k210/rtconfig.h @@ -7,6 +7,7 @@ /* RT-Thread Kernel */ #define RT_NAME_MAX 8 +/* RT_USING_ARCH_DATA_TYPE is not set */ #define RT_USING_SMP #define RT_CPUS_NR 2 #define RT_ALIGN_SIZE 8 @@ -19,7 +20,7 @@ #define RT_USING_HOOK #define RT_USING_IDLE_HOOK #define RT_IDEL_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 1024 +#define IDLE_THREAD_STACK_SIZE 4096 /* RT_USING_TIMER_SOFT is not set */ #define RT_DEBUG #define RT_DEBUG_COLOR @@ -42,7 +43,7 @@ #define RT_USING_EVENT #define RT_USING_MAILBOX #define RT_USING_MESSAGEQUEUE -/* RT_USING_SIGNALS is not set */ +#define RT_USING_SIGNALS /* Memory Management */ @@ -130,6 +131,7 @@ #define RT_USING_DEVICE_IPC #define RT_PIPE_BUFSZ 512 +/* RT_USING_SYSTEM_WORKQUEUE is not set */ #define RT_USING_SERIAL #define RT_SERIAL_USING_DMA #define RT_SERIAL_RB_BUFSZ 64 @@ -187,6 +189,10 @@ /* RT_USING_SAL is not set */ +/* Network interface device */ + +/* RT_USING_NETDEV is not set */ + /* light weight TCP/IP stack */ /* RT_USING_LWIP is not set */ @@ -205,7 +211,6 @@ /* Utilities */ -/* RT_USING_LOGTRACE is not set */ /* RT_USING_RYM is not set */ /* RT_USING_ULOG is not set */ /* RT_USING_UTEST is not set */ @@ -240,6 +245,7 @@ /* PKG_USING_NOPOLL is not set */ /* PKG_USING_NETUTILS is not set */ /* PKG_USING_AT_DEVICE is not set */ +/* PKG_USING_ATSRV_SOCKET is not set */ /* PKG_USING_WIZNET is not set */ /* IoT Cloud */ @@ -251,6 +257,7 @@ /* PKG_USING_TENCENT_IOTKIT is not set */ /* PKG_USING_NIMBLE is not set */ /* PKG_USING_OTA_DOWNLOADER is not set */ +/* PKG_USING_IPMSG is not set */ /* security packages */ @@ -268,6 +275,7 @@ /* PKG_USING_OPENMV is not set */ /* PKG_USING_MUPDF is not set */ +/* PKG_USING_STEMWIN is not set */ /* tools packages */ @@ -294,34 +302,31 @@ /* PKG_USING_CMSIS is not set */ /* PKG_USING_DFS_YAFFS is not set */ /* PKG_USING_LITTLEFS is not set */ +/* PKG_USING_THREAD_POOL is not set */ /* peripheral libraries and drivers */ -/* sensors drivers */ - -/* PKG_USING_LSM6DSL is not set */ -/* PKG_USING_LPS22HB is not set */ -/* PKG_USING_HTS221 is not set */ -/* PKG_USING_LSM303AGR is not set */ -/* PKG_USING_BME280 is not set */ -/* PKG_USING_BMA400 is not set */ -/* PKG_USING_BMI160_BMX160 is not set */ -/* PKG_USING_SPL0601 is not set */ +/* PKG_USING_SENSORS_DRIVERS is not set */ /* PKG_USING_REALTEK_AMEBA is not set */ /* PKG_USING_SHT2X is not set */ -/* PKG_USING_AHT10 is not set */ /* PKG_USING_AP3216C is not set */ /* PKG_USING_STM32_SDIO is not set */ /* PKG_USING_ICM20608 is not set */ /* PKG_USING_U8G2 is not set */ /* PKG_USING_BUTTON is not set */ -/* PKG_USING_MPU6XXX is not set */ /* PKG_USING_PCF8574 is not set */ /* PKG_USING_SX12XX is not set */ -/* PKG_USING_SIGNAL_LED is not set */ #define PKG_USING_KENDRYTE_SDK -#define PKG_USING_KENDRYTE_SDK_V052 +/* PKG_USING_KENDRYTE_SDK_V052 is not set */ +/* PKG_USING_KENDRYTE_SDK_V053 is not set */ +/* PKG_USING_KENDRYTE_SDK_V054 is not set */ +#define PKG_USING_KENDRYTE_SDK_V055 /* PKG_USING_KENDRYTE_SDK_LATEST_VERSION is not set */ +#define PKG_KENDRYTE_SDK_VERNUM 0x0055 +/* PKG_USING_INFRARED is not set */ +/* PKG_USING_ROSSERIAL is not set */ +/* PKG_USING_AT24CXX is not set */ +/* PKG_USING_MOTIONDRIVER2RTT is not set */ /* miscellaneous packages */ @@ -345,6 +350,32 @@ /* PKG_USING_PERIPHERAL_SAMPLES is not set */ /* PKG_USING_HELLO is not set */ /* PKG_USING_VI is not set */ + +/* Privated Packages of RealThread */ + +/* PKG_USING_CODEC is not set */ +/* PKG_USING_PLAYER is not set */ +/* PKG_USING_MPLAYER is not set */ +/* PKG_USING_PERSIMMON_SRC is not set */ +/* PKG_USING_JS_PERSIMMON is not set */ +/* PKG_USING_JERRYSCRIPT_WIN32 is not set */ + +/* Network Utilities */ + +/* PKG_USING_WICED is not set */ +/* PKG_USING_CLOUDSDK is not set */ +/* PKG_USING_COREMARK is not set */ +/* PKG_USING_POWER_MANAGER is not set */ +/* PKG_USING_RT_OTA is not set */ +/* PKG_USING_RDBD_SRC is not set */ +/* PKG_USING_RTINSIGHT is not set */ +/* PKG_USING_SMARTCONFIG is not set */ +/* PKG_USING_RTX is not set */ +/* RT_USING_TESTCASE is not set */ +/* PKG_USING_NGHTTP2 is not set */ +/* PKG_USING_AVS is not set */ +/* PKG_USING_STS is not set */ +/* PKG_USING_DLMS is not set */ #define BOARD_K210_EVB #define BSP_USING_UART_HS /* BSP_USING_UART1 is not set */ diff --git a/bsp/k210/rtconfig.py b/bsp/k210/rtconfig.py old mode 100644 new mode 100755 index 686f7f7412..b9258cd374 --- a/bsp/k210/rtconfig.py +++ b/bsp/k210/rtconfig.py @@ -15,7 +15,7 @@ if os.getenv('RTT_CC'): if CROSS_TOOL == 'gcc': PLATFORM = 'gcc' - EXEC_PATH = r'/opt/riscv64-unknown-elf/bin' + EXEC_PATH = r'/opt/gnu-mcu-eclipse/riscv-none-gcc/8.2.0-2.1-20190425-1021/bin' else: print('Please make sure your toolchains is GNU GCC!') exit(0) @@ -38,8 +38,8 @@ if PLATFORM == 'gcc': OBJDUMP = PREFIX + 'objdump' OBJCPY = PREFIX + 'objcopy' - DEVICE = ' -mcmodel=medany' - CFLAGS = DEVICE + ' -fno-common -ffunction-sections -fdata-sections -fstrict-volatile-bitfields ' + DEVICE = ' -mcmodel=medany -march=rv64imafdc -mabi=lp64d' + CFLAGS = DEVICE + ' -fno-common -ffunction-sections -fdata-sections -fstrict-volatile-bitfields' AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T link.lds' CPATH = '' diff --git a/bsp/lpc1114/.config b/bsp/lpc1114/.config new file mode 100644 index 0000000000..e6b644f19e --- /dev/null +++ b/bsp/lpc1114/.config @@ -0,0 +1,295 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +# CONFIG_RT_USING_OVERFLOW_CHECK is not set +# CONFIG_RT_USING_HOOK is not set +# CONFIG_RT_USING_IDLE_HOOK is not set +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set +# CONFIG_RT_DEBUG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart" +CONFIG_RT_VER_NUM=0x40001 +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M0=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=512 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +# CONFIG_RT_USING_FINSH is not set + +# +# Device virtual file system +# +# CONFIG_RT_USING_DFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=128 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_MTD is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set + +# +# Using WiFi +# +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +CONFIG_RT_USING_LIBC=y +# CONFIG_RT_USING_PTHREADS is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# Modbus master and slave stack +# +# CONFIG_RT_USING_MODBUS is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_LWP is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_AT_DEVICE is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set + +# +# sample package +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# example package: hello +# +# CONFIG_PKG_USING_HELLO is not set +CONFIG_SOC_LPC1114=y diff --git a/bsp/lpc1114/Kconfig b/bsp/lpc1114/Kconfig new file mode 100644 index 0000000000..8b4bc067f8 --- /dev/null +++ b/bsp/lpc1114/Kconfig @@ -0,0 +1,29 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../.." + +# you can change the RTT_ROOT default "../.." to your rtthread_root, +# example : default "F:/git_repositories/rt-thread" + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" + +config SOC_LPC1114 + bool + select ARCH_ARM_CORTEX_M0 + default y + +#source "$BSP_DIR/drivers/Kconfig" diff --git a/bsp/lpc1114/SConscript b/bsp/lpc1114/SConscript new file mode 100644 index 0000000000..c7ef7659ec --- /dev/null +++ b/bsp/lpc1114/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/lpc1114/SConstruct b/bsp/lpc1114/SConstruct new file mode 100644 index 0000000000..3f3d509e2f --- /dev/null +++ b/bsp/lpc1114/SConstruct @@ -0,0 +1,27 @@ +import os +import sys +import rtconfig + +from rtconfig import RTT_ROOT + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +from building import * + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CC, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/lpc1114/applications/SConscript b/bsp/lpc1114/applications/SConscript new file mode 100644 index 0000000000..e1255c80c8 --- /dev/null +++ b/bsp/lpc1114/applications/SConscript @@ -0,0 +1,9 @@ +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd, str(Dir('#'))] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/lpc1114/applications/main.c b/bsp/lpc1114/applications/main.c new file mode 100644 index 0000000000..ece8a62a1c --- /dev/null +++ b/bsp/lpc1114/applications/main.c @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-05-05 jg1uaa the first version + */ + +#include +#include + +/* for Z111xP board (LED is connected to PIO3_5, low=ON) */ +#define IOCON_PIO3_5 HWREG32(0x40044048) +#define GPIO3DIR HWREG32(0x50038000) +#define GPIO3DATA_5 HWREG32(0x50030080) + +static void led_off(void) +{ + GPIO3DATA_5 = 0x20; +} + +static void led_on(void) +{ + GPIO3DATA_5 = 0x00; +} + +static void led_setup(void) +{ + IOCON_PIO3_5 = 0xd0; // (default) + GPIO3DIR = 0x20; // select output + led_off(); +} + +static void led_demo(void) +{ + led_setup(); + + while (1) { + led_on(); + rt_thread_delay(50); // 500msec, tick@100Hz + led_off(); + rt_thread_delay(50); + } +} + +int main(int argc, char **argv) +{ + rt_kprintf("Hello, world!\n"); + + led_demo(); + + /* NOTREACHED */ + return 0; +} diff --git a/bsp/lpc1114/driver/SConscript b/bsp/lpc1114/driver/SConscript new file mode 100644 index 0000000000..2331e725c9 --- /dev/null +++ b/bsp/lpc1114/driver/SConscript @@ -0,0 +1,16 @@ +from building import * + +cwd = GetCurrentDir() +src = Glob('*.[cs]') +list = os.listdir(cwd) +CPPPATH = [cwd] +objs = [] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) +objs = objs + group +Return('objs') diff --git a/bsp/lpc1114/driver/board.c b/bsp/lpc1114/driver/board.c new file mode 100644 index 0000000000..6f2a4c85a3 --- /dev/null +++ b/bsp/lpc1114/driver/board.c @@ -0,0 +1,182 @@ +/* + * Copyright (c) 2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-05-05 jg1uaa the first version + */ + +#include +#include + +#include "board.h" +#include "drv_uart.h" + +#define SYSCON_BASE 0x40048000 +#define MEMMAP HWREG32(SYSCON_BASE + 0x000) +#define SYSPLLCTRL HWREG32(SYSCON_BASE + 0x008) +#define SYSPLLSTAT HWREG32(SYSCON_BASE + 0x00c) +#define SYSPLLCLKSEL HWREG32(SYSCON_BASE + 0x040) +#define SYSPLLCLKUEN HWREG32(SYSCON_BASE + 0x044) +#define MAINCLKSEL HWREG32(SYSCON_BASE + 0x070) +#define MAINCLKUEN HWREG32(SYSCON_BASE + 0x074) +#define AHBCLKCTRL HWREG32(SYSCON_BASE + 0x080) +#define PDRUNCFG HWREG32(SYSCON_BASE + 0x238) + +#define SCB_BASE 0xe000e000 +#define SYST_CSR HWREG32(SCB_BASE + 0x010) +#define SYST_RVR HWREG32(SCB_BASE + 0x014) +#define NVIC_ISER HWREG32(SCB_BASE + 0x100) +#define NVIC_ICER HWREG32(SCB_BASE + 0x180) +#define NVIC_ISPR HWREG32(SCB_BASE + 0x200) +#define NVIC_ICPR HWREG32(SCB_BASE + 0x280) +#define NVIC_IPR(irqno) HWREG32(SCB_BASE + 0x400 + (((irqno) / 4) << 2)) +#define SCB_SHPR3 HWREG32(SCB_BASE + 0xd20) + +extern unsigned char __bss_end__[]; +extern unsigned char _ram_end[]; + +/** + * This is the timer interrupt service routine. + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +void os_clock_init(void) +{ + /* bump up system clock 12MHz to 48MHz, using IRC (internal RC) osc. */ + + MAINCLKSEL = 0; // main clock: IRC @12MHz (default, for safety) + MAINCLKUEN = 0; + MAINCLKUEN = 1; + + PDRUNCFG &= ~0x80; // power up System PLL + + SYSPLLCLKSEL = 0; // PLL clock source: IRC osc + SYSPLLCLKUEN = 0; + SYSPLLCLKUEN = 1; + + SYSPLLCTRL = 0x23; // Fcco = 2 x P x FCLKOUT + // 192MHz = 2 x 2 x 48MHz + // M = FCLKOUT / FCLKIN + // 4 = 48MHz / 12MHz + + while (!(SYSPLLSTAT & 1)); // wait for lock PLL + + MAINCLKSEL = 3; // main clock: system PLL + MAINCLKUEN = 0; + MAINCLKUEN = 1; + + AHBCLKCTRL |= (1 << 16); // power up IOCON +} + +void SysTick_init(void) +{ + rt_uint32_t shpr3; + + /* set SysTick interrupt priority */ + shpr3 = SCB_SHPR3; + shpr3 &= ~0xff000000; + shpr3 |= 0x40 << 24; + SCB_SHPR3 = shpr3; + + /* start SysTick */ + SYST_CSR = 0x06; // Clock source:Core, SysTick Exception:enable + SYST_RVR = (CPU_CLOCK / RT_TICK_PER_SECOND) - 1; + SYST_CSR = 0x07; // Counter:enable +} + +/** + * This function initializes LPC1114 SoC. + */ +void rt_hw_board_init(void) +{ + os_clock_init(); + + /* init SysTick */ + SysTick_init(); + +#ifdef RT_USING_HEAP + /* initialize system heap */ + rt_system_heap_init((void *)&__bss_end__, (void *)&_ram_end); +#endif + /* initialize uart */ + rt_hw_uart_init(); + +#ifdef RT_USING_CONSOLE + /* set console device */ + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif +} + +/** + * Enable External Interrupt + */ +void NVIC_EnableIRQ(rt_int32_t irqno) +{ + NVIC_ISER = 1UL << (irqno & 0x1f); +} + +/** + * Disable External Interrupt + */ +void NVIC_DisableIRQ(rt_int32_t irqno) +{ + NVIC_ICER = 1UL << (irqno & 0x1f); +} + +/** + * Get Pending Interrupt + * Different from CMSIS implementation, + * returns zero/non-zero, not zero/one. + */ +rt_uint32_t NVIC_GetPendingIRQ(rt_int32_t irqno) +{ + return NVIC_ISPR & (1UL << (irqno & 0x1f)); +} + +/** + * Set Pending Interrupt + */ +void NVIC_SetPendingIRQ(rt_int32_t irqno) +{ + NVIC_ISPR = 1UL << (irqno & 0x1f); +} + +/** + * Clear Pending Interrupt + */ +void NVIC_ClearPendingIRQ(rt_int32_t irqno) +{ + NVIC_ICPR = 1UL << (irqno & 0x1f); +} + +/** + * Set Interrupt Priority + * Different from CMSIS implementation, + * this code supports only external (device specific) interrupt. + */ +void NVIC_SetPriority(rt_int32_t irqno, rt_uint32_t priority) +{ + rt_uint32_t shift, ipr; + + shift = (irqno % 4) * 8; + ipr = NVIC_IPR(irqno); + ipr &= ~(0xffUL << shift); + ipr |= (priority & 0xff) << shift; + NVIC_IPR(irqno) = ipr; +} diff --git a/bsp/lpc1114/driver/board.h b/bsp/lpc1114/driver/board.h new file mode 100644 index 0000000000..a0022a8c59 --- /dev/null +++ b/bsp/lpc1114/driver/board.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-05-05 jg1uaa the first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#define CPU_CLOCK 48000000 // Hz + +void rt_hw_board_init(void); + +void NVIC_EnableIRQ(rt_int32_t irqno); +void NVIC_DisableIRQ(rt_int32_t irqno); +rt_uint32_t NVIC_GetPendingIRQ(rt_int32_t irqno); +void NVIC_SetPendingIRQ(rt_int32_t irqno); +void NVIC_ClearPendingIRQ(rt_int32_t irqno); +void NVIC_SetPriority(rt_int32_t irqno, rt_uint32_t priority); + +#endif /* __BOARD_H__ */ diff --git a/bsp/lpc1114/driver/drv_uart.c b/bsp/lpc1114/driver/drv_uart.c new file mode 100644 index 0000000000..96cf6f760d --- /dev/null +++ b/bsp/lpc1114/driver/drv_uart.c @@ -0,0 +1,177 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2013-05-18 Bernard The first version for LPC40xx + * 2019-05-05 jg1uaa port to LPC1114 + */ + +#include +#include +#include +#include "board.h" // CPU_CLOCK +#include "drv_uart.h" + +#ifdef RT_USING_SERIAL + +#define UART_BASE 0x40008000 // UART (only one) +#define UART_IRQ 21 +#define UART_CLOCK (CPU_CLOCK / 1) // Hz + +#define URBR HWREG32(UART_BASE + 0x00) // R- +#define UTHR HWREG32(UART_BASE + 0x00) // -W +#define UIER HWREG32(UART_BASE + 0x04) // RW +#define UIIR HWREG32(UART_BASE + 0x08) // R- +#define UFCR HWREG32(UART_BASE + 0x08) // -W +#define ULCR HWREG32(UART_BASE + 0x0c) // RW +#define UMCR HWREG32(UART_BASE + 0x10) // RW +#define ULSR HWREG32(UART_BASE + 0x14) // R- +#define UMSR HWREG32(UART_BASE + 0x18) // R- + +#define UDLL HWREG32(UART_BASE + 0x00) // RW +#define UDLM HWREG32(UART_BASE + 0x04) // RW + +#define IOCONFIG_BASE 0x40044000 +#define IOCON_PIO1_6 HWREG32(IOCONFIG_BASE + 0xa4) +#define IOCON_PIO1_7 HWREG32(IOCONFIG_BASE + 0xa8) + +#define SYSCON_BASE 0x40048000 +#define AHBCLKCTRL HWREG32(SYSCON_BASE + 0x80) +#define UARTCLKDIV HWREG32(SYSCON_BASE + 0x98) + +static rt_err_t lpc_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + rt_uint32_t Fdiv = 0; + + RT_ASSERT(serial != RT_NULL); + + /* Initialize UART Configuration parameter structure to default state: + * Baudrate = 115200 bps + * 8 data bit + * 1 Stop bit + * None parity + */ + /* set DLAB=1 */ + ULCR |= 0x80; + /* config uart baudrate */ + Fdiv = UART_CLOCK / (cfg->baud_rate * 16); + UDLM = Fdiv / 256; + UDLL = Fdiv % 256; + /* set DLAB=0 */ + ULCR &= ~0x80; + /* config to 8 data bit,1 Stop bit,None parity */ + ULCR |= 0x03; + + /*enable and reset FIFO*/ + UFCR = 0x07; + + return RT_EOK; +} + +static rt_err_t lpc_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + RT_ASSERT(serial != RT_NULL); + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + UIER &= ~0x01; + break; + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + UIER |= 0x01; + break; + } + + return RT_EOK; +} + +static int lpc_putc(struct rt_serial_device *serial, char c) +{ + while (!(ULSR & 0x20)); + UTHR = c; + + return 1; +} + +static int lpc_getc(struct rt_serial_device *serial) +{ + if (ULSR & 0x01) + return URBR; + else + return -1; +} + +static const struct rt_uart_ops lpc_uart_ops = +{ + lpc_configure, + lpc_control, + lpc_putc, + lpc_getc, +}; + +struct rt_serial_device serial; + +void UART_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + switch (UIIR & 0x0e) + { + case 0x04: + case 0x0C: + rt_hw_serial_isr(&serial, RT_SERIAL_EVENT_RX_IND); + break; + case 0x06: + (void)ULSR; + break; + default: + (void)ULSR; + break; + } + /* leave interrupt */ + rt_interrupt_leave(); +} + +int rt_hw_uart_init(void) +{ + rt_err_t ret = RT_EOK; + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + + serial.ops = &lpc_uart_ops; + serial.config = config; + serial.parent.user_data = NULL; + + /* + * Initialize UART pin connect + * P1.6: U0_RXD + * P1.7: U0_TXD + */ + IOCON_PIO1_6 = 0xc1; + IOCON_PIO1_7 = 0xc1; + + /* setup the uart power and clock */ + UARTCLKDIV = 0x01; // UART PCLK = system clock / 1 + AHBCLKCTRL |= (1 << 12); // UART power-up + + /* priority = 1 */ + NVIC_SetPriority(UART_IRQ, 0x01 << 6); + + /* Enable Interrupt for UART channel */ + NVIC_EnableIRQ(UART_IRQ); + + /* register UART device */ + ret = rt_hw_serial_register(&serial, "uart", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + NULL); + + return ret; +} +INIT_BOARD_EXPORT(rt_hw_uart_init); + +#endif /* RT_USING_SERIAL */ diff --git a/bsp/lpc1114/driver/drv_uart.h b/bsp/lpc1114/driver/drv_uart.h new file mode 100644 index 0000000000..b5de18269b --- /dev/null +++ b/bsp/lpc1114/driver/drv_uart.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-05-05 jg1uaa the first version + */ + +#ifndef __DRV_UART_H__ +#define __DRV_UART_H__ + +int rt_hw_uart_init(void); + +#endif diff --git a/bsp/lpc1114/driver/startup_gcc.s b/bsp/lpc1114/driver/startup_gcc.s new file mode 100644 index 0000000000..b7b951cfe0 --- /dev/null +++ b/bsp/lpc1114/driver/startup_gcc.s @@ -0,0 +1,130 @@ +/* + * Copyright (c) 2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-05-05 jg1uaa the first version + */ + +#include "../rtconfig.h" + +/* Interrupt Vectors */ + .section .isr_vector + .thumb + .align 0 + + .long _estack // MSP default value + .long Reset_Handler + 1 // 1: Reset + .long default_handler + 1 // 2: NMI + .long HardFault_Handler + 1 // 3: HardFault + .long default_handler + 1 // 4: reserved + .long default_handler + 1 // 5: reserved + .long default_handler + 1 // 6: reserved + .long default_handler + 1 // 7: reserved + .long default_handler + 1 // 8: reserved + .long default_handler + 1 // 9: reserved + .long default_handler + 1 // 10: reserved + .long default_handler + 1 // 11: SVCall + .long default_handler + 1 // 12: reserved + .long default_handler + 1 // 13: reserved + .long PendSV_Handler + 1 // 14: PendSV + .long SysTick_Handler + 1 // 15: SysTick + .long default_handler + 1 // 16: External Interrupt(0) + .long default_handler + 1 // 17: External Interrupt(1) + .long default_handler + 1 // 18: External Interrupt(2) + .long default_handler + 1 // 19: External Interrupt(3) + .long default_handler + 1 // 20: External Interrupt(4) + .long default_handler + 1 // 21: External Interrupt(5) + .long default_handler + 1 // 22: External Interrupt(6) + .long default_handler + 1 // 23: External Interrupt(7) + .long default_handler + 1 // 24: External Interrupt(8) + .long default_handler + 1 // 25: External Interrupt(9) + .long default_handler + 1 // 26: External Interrupt(10) + .long default_handler + 1 // 27: External Interrupt(11) + .long default_handler + 1 // 28: External Interrupt(12) + .long default_handler + 1 // 29: External Interrupt(13) C_CAN + .long default_handler + 1 // 30: External Interrupt(14) SPI/SSP1 + .long default_handler + 1 // 31: External Interrupt(15) I2C + .long default_handler + 1 // 32: External Interrupt(16) CT16B0 + .long default_handler + 1 // 33: External Interrupt(17) CT16B1 + .long default_handler + 1 // 34: External Interrupt(18) CT32B0 + .long default_handler + 1 // 35: External Interrupt(19) CT32B1 + .long default_handler + 1 // 36: External Interrupt(20) SPI/SSP0 + .long UART_IRQHandler + 1 // 37: External Interrupt(21) UART + .long default_handler + 1 // 38: External Interrupt(22) + .long default_handler + 1 // 39: External Interrupt(23) + .long default_handler + 1 // 40: External Interrupt(24) ADC + .long default_handler + 1 // 41: External Interrupt(25) WDT + .long default_handler + 1 // 42: External Interrupt(26) BOD + .long default_handler + 1 // 43: External Interrupt(27) + .long default_handler + 1 // 44: External Interrupt(28) PIO_3 + .long default_handler + 1 // 45: External Interrupt(29) PIO_2 + .long default_handler + 1 // 46: External Interrupt(30) PIO_1 + .long default_handler + 1 // 47: External Interrupt(31) PIO_0 + .long default_handler + 1 // 48: External Interrupt(32) + .long default_handler + 1 // 49: External Interrupt(33) + .long default_handler + 1 // 50: External Interrupt(34) + .long default_handler + 1 // 51: External Interrupt(35) + .long default_handler + 1 // 52: External Interrupt(36) + .long default_handler + 1 // 53: External Interrupt(37) + .long default_handler + 1 // 54: External Interrupt(38) + .long default_handler + 1 // 55: External Interrupt(39) + .long default_handler + 1 // 56: External Interrupt(40) + .long default_handler + 1 // 57: External Interrupt(41) + .long default_handler + 1 // 58: External Interrupt(42) + .long default_handler + 1 // 59: External Interrupt(43) + .long default_handler + 1 // 60: External Interrupt(44) + .long default_handler + 1 // 61: External Interrupt(45) + .long default_handler + 1 // 62: External Interrupt(46) + .long default_handler + 1 // 63: External Interrupt(47) + +/* startup */ + .section .text + .thumb + .align 0 + .global Reset_Handler +Reset_Handler: + + /* initialize .data */ +data_init: + ldr r1, =_sidata + ldr r2, =_sdata + ldr r3, =_edata + cmp r2, r3 + beq bss_init +data_loop: + ldrb r0, [r1] + add r1, r1, #1 + strb r0, [r2] + add r2, r2, #1 + cmp r2, r3 + bne data_loop + + /* initialize .bss */ +bss_init: + mov r0, #0 + ldr r2, =_sbss // sbss/ebss is 4byte aligned by link.lds + ldr r3, =_ebss + cmp r2, r3 + beq start_main +bss_loop: + str r0, [r2] + add r2, r2, #4 + cmp r2, r3 + bne bss_loop + + /* launch main() */ +start_main: +#ifdef RT_USING_USER_MAIN + bl entry +#else + bl main +#endif + +default_handler: +die: + b die + + .pool diff --git a/bsp/lpc1114/link.lds b/bsp/lpc1114/link.lds new file mode 100644 index 0000000000..19d0a053cb --- /dev/null +++ b/bsp/lpc1114/link.lds @@ -0,0 +1,138 @@ +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ + CODE (rx) : ORIGIN = 0x00000000, LENGTH = 32k /* 32KB flash */ + DATA (rw) : ORIGIN = 0x10000000, LENGTH = 4k /* 4K sram */ +} +ENTRY(Reset_Handler) +_system_stack_size = 0x100; +_ram_end = ORIGIN(DATA) + LENGTH(DATA); + +SECTIONS +{ + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + . = ALIGN(4); + _etext = .; + } > CODE = 0 + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > CODE + __exidx_end = .; + + /* .data section which is used for initialized data */ + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >DATA + + .stack : + { + . = . + _system_stack_size; + . = ALIGN(4); + _estack = .; + } >DATA + + __bss_start__ = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + + *(.bss.init) + } > DATA + __bss_end__ = .; + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/lpc1114/rtconfig.h b/bsp/lpc1114/rtconfig.h new file mode 100644 index 0000000000..329aef4130 --- /dev/null +++ b/bsp/lpc1114/rtconfig.h @@ -0,0 +1,258 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +/* RT_USING_ARCH_DATA_TYPE is not set */ +/* RT_USING_SMP is not set */ +#define RT_ALIGN_SIZE 4 +/* RT_THREAD_PRIORITY_8 is not set */ +#define RT_THREAD_PRIORITY_32 +/* RT_THREAD_PRIORITY_256 is not set */ +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +/* RT_USING_OVERFLOW_CHECK is not set */ +/* RT_USING_HOOK is not set */ +/* RT_USING_IDLE_HOOK is not set */ +#define IDLE_THREAD_STACK_SIZE 256 +/* RT_USING_TIMER_SOFT is not set */ +/* RT_DEBUG is not set */ + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +/* RT_USING_SIGNALS is not set */ + +/* Memory Management */ + +#define RT_USING_MEMPOOL +/* RT_USING_MEMHEAP is not set */ +/* RT_USING_NOHEAP is not set */ +#define RT_USING_SMALL_MEM +/* RT_USING_SLAB is not set */ +/* RT_USING_MEMTRACE is not set */ +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +/* RT_USING_DEVICE_OPS is not set */ +/* RT_USING_INTERRUPT_INFO is not set */ +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart" +#define RT_VER_NUM 0x40001 +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M0 +/* ARCH_CPU_STACK_GROWS_UPWARD is not set */ + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 512 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + +/* RT_USING_CPLUSPLUS is not set */ + +/* Command shell */ + +/* RT_USING_FINSH is not set */ + +/* Device virtual file system */ + +/* RT_USING_DFS is not set */ + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 128 +/* RT_USING_SYSTEM_WORKQUEUE is not set */ +#define RT_USING_SERIAL +/* RT_SERIAL_USING_DMA is not set */ +#define RT_SERIAL_RB_BUFSZ 64 +/* RT_USING_CAN is not set */ +/* RT_USING_HWTIMER is not set */ +/* RT_USING_CPUTIME is not set */ +/* RT_USING_I2C is not set */ +#define RT_USING_PIN +/* RT_USING_ADC is not set */ +/* RT_USING_PWM is not set */ +/* RT_USING_MTD_NOR is not set */ +/* RT_USING_MTD_NAND is not set */ +/* RT_USING_MTD is not set */ +/* RT_USING_PM is not set */ +/* RT_USING_RTC is not set */ +/* RT_USING_SDIO is not set */ +/* RT_USING_SPI is not set */ +/* RT_USING_WDT is not set */ +/* RT_USING_AUDIO is not set */ +/* RT_USING_SENSOR is not set */ + +/* Using WiFi */ + +/* RT_USING_WIFI is not set */ + +/* Using USB */ + +/* RT_USING_USB_HOST is not set */ +/* RT_USING_USB_DEVICE is not set */ + +/* POSIX layer and C standard library */ + +#define RT_USING_LIBC +/* RT_USING_PTHREADS is not set */ + +/* Network */ + +/* Socket abstraction layer */ + +/* RT_USING_SAL is not set */ + +/* Network interface device */ + +/* RT_USING_NETDEV is not set */ + +/* light weight TCP/IP stack */ + +/* RT_USING_LWIP is not set */ + +/* Modbus master and slave stack */ + +/* RT_USING_MODBUS is not set */ + +/* AT commands */ + +/* RT_USING_AT is not set */ + +/* VBUS(Virtual Software BUS) */ + +/* RT_USING_VBUS is not set */ + +/* Utilities */ + +/* RT_USING_RYM is not set */ +/* RT_USING_ULOG is not set */ +/* RT_USING_UTEST is not set */ +/* RT_USING_LWP is not set */ + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + +/* PKG_USING_PAHOMQTT is not set */ +/* PKG_USING_WEBCLIENT is not set */ +/* PKG_USING_MONGOOSE is not set */ +/* PKG_USING_WEBTERMINAL is not set */ +/* PKG_USING_CJSON is not set */ +/* PKG_USING_JSMN is not set */ +/* PKG_USING_LJSON is not set */ +/* PKG_USING_EZXML is not set */ +/* PKG_USING_NANOPB is not set */ + +/* Wi-Fi */ + +/* Marvell WiFi */ + +/* PKG_USING_WLANMARVELL is not set */ + +/* Wiced WiFi */ + +/* PKG_USING_WLAN_WICED is not set */ +/* PKG_USING_COAP is not set */ +/* PKG_USING_NOPOLL is not set */ +/* PKG_USING_NETUTILS is not set */ +/* PKG_USING_AT_DEVICE is not set */ + +/* IoT Cloud */ + +/* PKG_USING_ONENET is not set */ +/* PKG_USING_GAGENT_CLOUD is not set */ +/* PKG_USING_ALI_IOTKIT is not set */ +/* PKG_USING_AZURE is not set */ + +/* security packages */ + +/* PKG_USING_MBEDTLS is not set */ +/* PKG_USING_libsodium is not set */ +/* PKG_USING_TINYCRYPT is not set */ + +/* language packages */ + +/* PKG_USING_LUA is not set */ +/* PKG_USING_JERRYSCRIPT is not set */ +/* PKG_USING_MICROPYTHON is not set */ + +/* multimedia packages */ + +/* PKG_USING_OPENMV is not set */ +/* PKG_USING_MUPDF is not set */ + +/* tools packages */ + +/* PKG_USING_CMBACKTRACE is not set */ +/* PKG_USING_EASYFLASH is not set */ +/* PKG_USING_EASYLOGGER is not set */ +/* PKG_USING_SYSTEMVIEW is not set */ + +/* system packages */ + +/* PKG_USING_GUIENGINE is not set */ +/* PKG_USING_CAIRO is not set */ +/* PKG_USING_PIXMAN is not set */ +/* PKG_USING_LWEXT4 is not set */ +/* PKG_USING_PARTITION is not set */ +/* PKG_USING_FAL is not set */ +/* PKG_USING_SQLITE is not set */ +/* PKG_USING_RTI is not set */ +/* PKG_USING_LITTLEVGL2RTT is not set */ +/* PKG_USING_CMSIS is not set */ +/* PKG_USING_DFS_YAFFS is not set */ + +/* peripheral libraries and drivers */ + +/* PKG_USING_REALTEK_AMEBA is not set */ +/* PKG_USING_SHT2X is not set */ +/* PKG_USING_AHT10 is not set */ +/* PKG_USING_AP3216C is not set */ +/* PKG_USING_STM32_SDIO is not set */ +/* PKG_USING_ICM20608 is not set */ + +/* miscellaneous packages */ + +/* PKG_USING_LIBCSV is not set */ +/* PKG_USING_OPTPARSE is not set */ +/* PKG_USING_FASTLZ is not set */ +/* PKG_USING_MINILZO is not set */ +/* PKG_USING_QUICKLZ is not set */ +/* PKG_USING_MULTIBUTTON is not set */ +/* PKG_USING_CANFESTIVAL is not set */ +/* PKG_USING_ZLIB is not set */ +/* PKG_USING_DSTR is not set */ + +/* sample package */ + +/* samples: kernel and components samples */ + +/* PKG_USING_KERNEL_SAMPLES is not set */ +/* PKG_USING_FILESYSTEM_SAMPLES is not set */ +/* PKG_USING_NETWORK_SAMPLES is not set */ +/* PKG_USING_PERIPHERAL_SAMPLES is not set */ + +/* example package: hello */ + +/* PKG_USING_HELLO is not set */ +#define SOC_LPC1114 + +#endif diff --git a/bsp/lpc1114/rtconfig.py b/bsp/lpc1114/rtconfig.py new file mode 100644 index 0000000000..4eb53465df --- /dev/null +++ b/bsp/lpc1114/rtconfig.py @@ -0,0 +1,58 @@ +import os + +# toolchains options +ARCH ='arm' +CPU ='cortex-m0' +CROSS_TOOL ='gcc' + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = '../..' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'/usr/bin' +else: + print 'Please make sure your toolchains is GNU GCC!' + exit(0) + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'release' +# BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'g++' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m0 -mthumb -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Wall' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' + LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T link.lds' + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -Os' + + CXXFLAGS = CFLAGS + +DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n' +POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' diff --git a/bsp/ls1cdev/drivers/drv_wdt.c b/bsp/ls1cdev/drivers/drv_wdt.c new file mode 100644 index 0000000000..4a42220000 --- /dev/null +++ b/bsp/ls1cdev/drivers/drv_wdt.c @@ -0,0 +1,199 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-05-06 sundm75 first version + */ + +#include +#include + +#ifdef RT_USING_WDT + +#include +#include "drv_wdt.h" + +#include "ls1c_wdog.h" +#include "ls1c_clock.h" + +typedef enum +{ + RESTENABLE = 0x0, + INTERRUPTENABLE = 0x1, +}wdt_enable_mode; + +static rt_uint32_t heartbeat = 0; + +static rt_err_t wdt_stop(void) +{ + rt_err_t ret = RT_EOK; + + Wdog_Reset(); + ret = (rt_err_t) Wdog_Disable(); + if (ret != RT_EOK) + { + rt_kprintf("Wdog_Disable error!\n"); + return RT_ERROR; + } + return ret; +} + +static rt_err_t wdt_start(int mode) +{ + rt_err_t ret = RT_EOK; + wdt_enable_mode wdt_mode = RESTENABLE; + + ret = (rt_err_t) Wdog_Disable(); + if (ret != RT_EOK) + { + rt_kprintf("Wdog_Disable error!\n"); + return RT_ERROR; + } + + if((mode == RESTENABLE) || (mode == INTERRUPTENABLE)) + { + wdt_mode = mode; + } + Wdog_Enable(); + Wdog_Set(); + if (ret != RT_EOK) + { + rt_kprintf("Wdog_Enable error!\n"); + return RT_ERROR; + } + + return ret; +} + +static rt_err_t wdt_keepalive(void) +{ + rt_err_t ret = RT_EOK; + rt_uint32_t index = 0; + + index = heartbeat * clk_get_apb_rate(); + ret = (rt_err_t) Wdog_LoadValue(index); + Wdog_Set(); + if (ret != 0) + { + rt_kprintf("LS1C_Wdog_ClrTimeout error!\n"); + return RT_ERROR; + } + + return ret; +} + +static rt_uint32_t wdt_get_timeleft(void) +{ + rt_uint32_t cnt = 0; + rt_uint32_t second = 0; + + cnt = (rt_uint32_t) Wdog_GetValue(); + second = cnt/clk_get_apb_rate(); + + return second; +} + +static rt_err_t wdt_set_timeout(rt_uint32_t second) +{ + rt_err_t ret = RT_EOK; + rt_uint32_t index = 0; + + index = second * clk_get_apb_rate(); + ret = (rt_err_t) Wdog_LoadValue(index); + if (ret != RT_EOK) + { + rt_kprintf("Wdog_LoadValue error!\n"); + return RT_ERROR; + } + return ret; +} + +static rt_err_t watchdog_init(rt_watchdog_t *wdt) +{ + struct wdt_driver *wdt_drv = wdt->parent.user_data; + if (wdt_drv->in_use) return -RT_EBUSY; + + Wdog_Init(); + + return RT_EOK; +} + +static rt_err_t watchdog_ctrl(rt_watchdog_t *wdt, int cmd, void *arg) +{ + rt_uint32_t val; + int mode; + + switch (cmd) + { + case RT_DEVICE_CTRL_WDT_START: + mode = *((int *)(arg)); + wdt_start(mode); + break; + + case RT_DEVICE_CTRL_WDT_STOP: + Wdog_Disable(); + break; + + case RT_DEVICE_CTRL_WDT_KEEPALIVE: + wdt_keepalive(); + break; + + case RT_DEVICE_CTRL_WDT_SET_TIMEOUT: + heartbeat = *((rt_uint32_t *)(arg)); + wdt_set_timeout(heartbeat); + break; + + case RT_DEVICE_CTRL_WDT_GET_TIMEOUT: + arg = &heartbeat; + break; + + case RT_DEVICE_CTRL_WDT_GET_TIMELEFT: + val = (rt_uint32_t) wdt_get_timeleft(); + arg = &val; + break; + + default: + return -RT_EIO; + } + return RT_EOK; +} + +struct rt_watchdog_ops watchdog_ops = +{ + .init = &watchdog_init, + .control = &watchdog_ctrl, +}; + +int wdt_exit(void *priv_data) +{ + return 0; +} + +int rt_hw_wdt_init(void) +{ + rt_watchdog_t *wdt_dev; + struct wdt_driver *wdt_drv; + + wdt_drv = (struct wdt_driver *)rt_malloc(sizeof(struct wdt_driver)); + rt_memset(wdt_drv, 0, sizeof(struct wdt_driver)); + + wdt_dev = (rt_watchdog_t *)rt_malloc(sizeof(rt_watchdog_t)); + + if (wdt_dev == RT_NULL) + { + rt_kprintf("ERROR: %s rt_watchdog_t malloc failed\n", __func__); + } + + wdt_dev->ops = &watchdog_ops; + + rt_hw_watchdog_register(wdt_dev, "wdt", RT_DEVICE_OFLAG_RDWR, wdt_drv); + + return 0; +} + +INIT_BOARD_EXPORT(rt_hw_wdt_init); + +#endif diff --git a/bsp/ls1cdev/drivers/drv_wdt.h b/bsp/ls1cdev/drivers/drv_wdt.h new file mode 100644 index 0000000000..a017edb19a --- /dev/null +++ b/bsp/ls1cdev/drivers/drv_wdt.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-05-06 sundm75 first version + */ + +#ifndef WDT_H_ +#define WDT_H_ + +struct wdt_driver +{ + unsigned long in_use; + + void* priv; +}; + +int rt_hw_wdt_init(void); + +#endif /* WDT_H_ */ diff --git a/bsp/ls1cdev/libraries/ls1c_wdog.c b/bsp/ls1cdev/libraries/ls1c_wdog.c new file mode 100644 index 0000000000..4034281d10 --- /dev/null +++ b/bsp/ls1cdev/libraries/ls1c_wdog.c @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-05-06 sundm75 first version + */ + +#include "ls1c.h" +#include "ls1c_wdog.h" + +/* +系统先配置看门狗使能位 WDT_EN; +然后配置看门狗计数器的初始值 WDT_TIMER; +当设置 WDT_SET 后，计数器开始减计数; +当还没有减到 0 时，重置看门狗计数器，系统不会重启; +当看门狗计数器减到 0 时，则系统重启。 +*/ + +static unsigned int WDT_timer = 0; + +/* 暂时为空 */ +unsigned int Wdog_Init(void) +{ + return 0; +} + +/* 配置看门狗使能寄存器(WDT_EN) */ +unsigned int Wdog_Enable(void) +{ + unsigned int ctrl; + ctrl = (WDT_EN); + ctrl |= 0x01; + + WDT_EN = ctrl; + return 0; +} + +/* 配置看门狗失能寄存器(WDT_EN) */ +unsigned int Wdog_Disable(void) +{ + unsigned int ctrl; + ctrl = (WDT_EN); + ctrl &= ~0x01; + WDT_EN = ctrl; + return 0; +} + +/* 配置看门狗设置寄存器 (WDT_SET) */ +unsigned int Wdog_Set(void) +{ + unsigned int ctrl; + ctrl = (WDT_SET); + ctrl |= 0x01; + WDT_SET = ctrl; + return 0; +} + +/* 配置看门狗设置寄存器 (WDT_SET) */ +unsigned int Wdog_Reset(void) +{ + unsigned int ctrl; + ctrl = (WDT_SET); + ctrl &= ~0x01; + WDT_SET = ctrl; + return 0; +} + +/* 获得看门狗计数器(WDT_timer) 的值*/ +unsigned int Wdog_GetValue(void) +{ + unsigned int cnt; + cnt = (WDT_TIMER); + return cnt; +} + +/* 配置看门狗计数器(WDT_timer)的值*/ +unsigned int Wdog_LoadValue(unsigned int cnt) +{ + WDT_TIMER = cnt; + WDT_timer = cnt; + return 0; +} + +/* 获得看门狗计数器设定值 */ +unsigned int Wdog_GetPreValue(void) +{ + return WDT_timer; +} diff --git a/bsp/ls1cdev/libraries/ls1c_wdog.h b/bsp/ls1cdev/libraries/ls1c_wdog.h new file mode 100644 index 0000000000..a4717eedbf --- /dev/null +++ b/bsp/ls1cdev/libraries/ls1c_wdog.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-05-06 sundm75 first version + */ + +#ifndef _LS1C_WDOG_H_ +#define _LS1C_WDOG_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +unsigned int Wdog_Init(void); // 暂时为空 +unsigned int Wdog_Enable(void); // 看门狗使能寄存器（WDT_EN） +unsigned int Wdog_Disable(void); // 看门狗失能寄存器（WDT_EN） +unsigned int Wdog_Set(void); // 看门狗设置寄存器 (WDT_SET) +unsigned int Wdog_Reset(void); // 看门狗设置寄存器 (WDT_SET) +unsigned int Wdog_GetValue(void); // 获得看门狗计数器（WDT_timer） +unsigned int Wdog_LoadValue(unsigned int cnt); // 设置看门狗计数器（WDT_timer） +unsigned int Wdog_GetPreValue(void); // 获得看门狗计数器设定值 + +#ifdef __cplusplus +} +#endif + +#endif /* _LS1C_WDOG_H_ */ + diff --git a/bsp/mm32l07x/drivers/board.h b/bsp/mm32l07x/drivers/board.h index ffb1ce31ee..cfc02d288e 100644 --- a/bsp/mm32l07x/drivers/board.h +++ b/bsp/mm32l07x/drivers/board.h @@ -16,7 +16,7 @@ #define SRAM_SIZE 0x2000 #define SRAM_END (SRAM_BASE + SRAM_SIZE) -#ifdef __CC_ARM +#if defined(__CC_ARM) || defined(__CLANG_ARM) extern int Image$$RW_IRAM1$$ZI$$Limit; #define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) #elif __ICCARM__ diff --git a/bsp/nuvoton_m451/applications/startup.c b/bsp/nuvoton_m451/applications/startup.c index bf50d4d782..b1f57ceb90 100644 --- a/bsp/nuvoton_m451/applications/startup.c +++ b/bsp/nuvoton_m451/applications/startup.c @@ -29,7 +29,7 @@ extern int finsh_system_init(void); extern void finsh_set_device(const char* device); #endif -#ifdef __CC_ARM +#if defined(__CC_ARM) || defined(__CLANG_ARM) extern int Image$$RW_IRAM1$$ZI$$Limit; #define M451_SRAM_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) #elif __ICCARM__ diff --git a/bsp/qemu-vexpress-a9/.cproject b/bsp/qemu-vexpress-a9/.cproject new file mode 100644 index 0000000000..31c328ad90 --- /dev/null +++ b/bsp/qemu-vexpress-a9/.cproject @@ -0,0 +1,175 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/qemu-vexpress-a9/.gitignore b/bsp/qemu-vexpress-a9/.gitignore new file mode 100644 index 0000000000..fba5a7a92e --- /dev/null +++ b/bsp/qemu-vexpress-a9/.gitignore @@ -0,0 +1,44 @@ +*.pyc +*.map +*.dblite +*.elf +*.bin +*.hex +*.axf +*.exe +*.pdb +*.idb +*.ilk +*.old +build +Debug +documentation/html +packages/ +*~ +*.o +*.obj +*.out +*.bak +*.dep +*.lib +*.i +*.d +.DS_Stor* +.config 3 +.config 4 +.config 5 +Midea-X1 +*.uimg +GPATH +GRTAGS +GTAGS +.vscode +JLinkLog.txt +JLinkSettings.ini +DebugConfig/ +RTE/ +settings/ +*.uvguix* +cconfig.h +.settings +drivers/automac.h diff --git a/bsp/qemu-vexpress-a9/.project b/bsp/qemu-vexpress-a9/.project new file mode 100644 index 0000000000..f9f83316f2 --- /dev/null +++ b/bsp/qemu-vexpress-a9/.project @@ -0,0 +1,53 @@ + + + qemu-vexpress-a9 + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + rt-thread + 2 + virtual:/virtual + + + rt-thread/components + 2 + $%7BPARENT-2-PROJECT_LOC%7D/components + + + rt-thread/include + 2 + $%7BPARENT-2-PROJECT_LOC%7D/include + + + rt-thread/libcpu + 2 + $%7BPARENT-2-PROJECT_LOC%7D/libcpu + + + rt-thread/src + 2 + $%7BPARENT-2-PROJECT_LOC%7D/src + + + diff --git a/bsp/qemu-vexpress-a9/drivers/automac.h b/bsp/qemu-vexpress-a9/drivers/automac.h new file mode 100644 index 0000000000..5f08b79a41 --- /dev/null +++ b/bsp/qemu-vexpress-a9/drivers/automac.h @@ -0,0 +1,15 @@ + +#ifndef __MAC_AUTO_GENERATE_H__ +#define __MAC_AUTO_GENERATE_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* mac configure file for RT-Thread qemu */ + +#define AUTOMAC0 0x52 +#define AUTOMAC1 0x54 +#define AUTOMAC2 0x00 +#define AUTOMAC3 0x28 +#define AUTOMAC4 0xae +#define AUTOMAC5 0xeb + +#endif diff --git a/bsp/qemu-vexpress-a9/drivers/drv_sdio.c b/bsp/qemu-vexpress-a9/drivers/drv_sdio.c index 1ecd147289..2628222627 100644 --- a/bsp/qemu-vexpress-a9/drivers/drv_sdio.c +++ b/bsp/qemu-vexpress-a9/drivers/drv_sdio.c @@ -440,14 +440,11 @@ int pl180_init(void) sdhci->priv = pdat; write32(pdat->virt + PL180_POWER, 0xbf); - // rt_kprintf("power:0x%08x\n", read32(pdat->virt + PL180_POWER)); - host->ops = &ops; host->freq_min = 400000; host->freq_max = 50000000; host->valid_ocr = VDD_32_33 | VDD_33_34; - // host->flags = MMCSD_MUTBLKWRITE | MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ | MMCSD_BUSWIDTH_4; - host->flags = MMCSD_MUTBLKWRITE | MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ; + host->flags = MMCSD_MUTBLKWRITE | MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ | MMCSD_BUSWIDTH_4; host->max_seg_size = 2048; host->max_dma_segs = 10; host->max_blk_size = 512; diff --git a/bsp/qemu-vexpress-a9/drivers/drv_smc911x.c b/bsp/qemu-vexpress-a9/drivers/drv_smc911x.c index 715cbfb75e..91a9311255 100644 --- a/bsp/qemu-vexpress-a9/drivers/drv_smc911x.c +++ b/bsp/qemu-vexpress-a9/drivers/drv_smc911x.c @@ -2,6 +2,7 @@ #include #include #include +#include #define MAX_ADDR_LEN 6 #define SMC911X_EMAC_DEVICE(eth) (struct eth_device_smc911x*)(eth) @@ -512,12 +513,12 @@ int smc911x_emac_hw_init(void) smc911x_reg_write(&_emac, INT_CFG, INT_CFG_IRQ_POL | INT_CFG_IRQ_TYPE); /* test MAC address */ - _emac.enetaddr[0] = 0x52; - _emac.enetaddr[1] = 0x54; - _emac.enetaddr[2] = 0x00; - _emac.enetaddr[3] = 0x11; - _emac.enetaddr[4] = 0x22; - _emac.enetaddr[5] = 0x33; + _emac.enetaddr[0] = AUTOMAC0; + _emac.enetaddr[1] = AUTOMAC1; + _emac.enetaddr[2] = AUTOMAC2; + _emac.enetaddr[3] = AUTOMAC3; + _emac.enetaddr[4] = AUTOMAC4; + _emac.enetaddr[5] = AUTOMAC5; #ifdef RT_USING_DEVICE_OPS _emac.parent.parent.ops = &smc911x_emac_ops; diff --git a/bsp/qemu-vexpress-a9/drivers/secondary_cpu.c b/bsp/qemu-vexpress-a9/drivers/secondary_cpu.c index 29bb9ec895..9221ecee87 100644 --- a/bsp/qemu-vexpress-a9/drivers/secondary_cpu.c +++ b/bsp/qemu-vexpress-a9/drivers/secondary_cpu.c @@ -17,6 +17,8 @@ #include "drv_timer.h" #ifdef RT_USING_SMP +#include + static void rt_hw_timer2_isr(int vector, void *param) { rt_tick_increase(); diff --git a/bsp/qemu-vexpress-a9/makefile.targets b/bsp/qemu-vexpress-a9/makefile.targets new file mode 100644 index 0000000000..a00129bd90 --- /dev/null +++ b/bsp/qemu-vexpress-a9/makefile.targets @@ -0,0 +1,4 @@ +clean2: + -$(RM) $(CC_DEPS)$(C++_DEPS)$(C_UPPER_DEPS)$(CXX_DEPS)$(SECONDARY_FLASH)$(SECONDARY_SIZE)$(ASM_DEPS)$(S_UPPER_DEPS)$(C_DEPS)$(CPP_DEPS) + -$(RM) $(OBJS) *.elf + -@echo ' ' \ No newline at end of file diff --git a/bsp/qemu-vexpress-a9/rtconfig.py b/bsp/qemu-vexpress-a9/rtconfig.py index d417673898..77e8d6debb 100644 --- a/bsp/qemu-vexpress-a9/rtconfig.py +++ b/bsp/qemu-vexpress-a9/rtconfig.py @@ -1,5 +1,29 @@ import os +import uuid +def get_mac_address(): + mac=uuid.UUID(int = uuid.getnode()).hex[-12:] + return "#define AUTOMAC".join([str(e/2 + 1) + ' 0x' + mac[e:e+2] + '\n' for e in range(5,11,2)]) + +header = ''' +#ifndef __MAC_AUTO_GENERATE_H__ +#define __MAC_AUTO_GENERATE_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* mac configure file for RT-Thread qemu */ + +#define AUTOMAC0 0x52 +#define AUTOMAC1 0x54 +#define AUTOMAC2 0x00 +#define AUTOMAC''' + +end = ''' +#endif +''' + +with open('drivers/automac.h', 'w') as f: + f.write(header + get_mac_address() + end) + # toolchains options ARCH='arm' CPU='cortex-a' diff --git a/bsp/samd21/applications/startup.c b/bsp/samd21/applications/startup.c index b8c2c83d0d..aaa75d3f1c 100644 --- a/bsp/samd21/applications/startup.c +++ b/bsp/samd21/applications/startup.c @@ -29,7 +29,7 @@ extern void finsh_system_init(void); extern void finsh_set_device(const char* device); #endif -#ifdef __CC_ARM +#if defined(__CC_ARM) || defined(__CLANG_ARM) extern int Image$$RW_IRAM1$$ZI$$Limit; #elif __ICCARM__ #pragma section="HEAP" @@ -78,7 +78,7 @@ void rtthread_startup(void) rt_system_timer_init(); #ifdef RT_USING_HEAP - #ifdef __CC_ARM + #if defined(__CC_ARM) || defined(__CLANG_ARM) rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)CHIP_SRAM_END); #elif __ICCARM__ rt_system_heap_init(__segment_end("HEAP"), (void*)CHIP_SRAM_END); diff --git a/bsp/stm32/libraries/HAL_Drivers/SConscript b/bsp/stm32/libraries/HAL_Drivers/SConscript index dcfbed7bcc..bd409b46f7 100644 --- a/bsp/stm32/libraries/HAL_Drivers/SConscript +++ b/bsp/stm32/libraries/HAL_Drivers/SConscript @@ -27,9 +27,10 @@ if GetDepend(['RT_USING_QSPI']): src += ['drv_qspi.c'] if GetDepend(['RT_USING_I2C', 'RT_USING_I2C_BITOPS']): - src += ['drv_soft_i2c.c'] + if GetDepend('BSP_USING_I2C1') or GetDepend('BSP_USING_I2C2') or GetDepend('BSP_USING_I2C3') or GetDepend('BSP_USING_I2C4'): + src += ['drv_soft_i2c.c'] -if GetDepend('RT_USING_LWIP'): +if GetDepend('BSP_USING_ETH'): src += ['drv_eth.c'] if GetDepend(['RT_USING_ADC']): @@ -38,6 +39,10 @@ if GetDepend(['RT_USING_ADC']): if GetDepend(['RT_USING_CAN']): src += ['drv_can.c'] +if GetDepend(['RT_USING_PM', 'SOC_SERIES_STM32L4']): + src += ['drv_pm.c'] + src += ['drv_lptim.c'] + if GetDepend('BSP_USING_SDRAM'): src += ['drv_sdram.c'] diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_eth.c b/bsp/stm32/libraries/HAL_Drivers/drv_eth.c index 493f4190ad..148a03f45b 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_eth.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_eth.c @@ -91,10 +91,10 @@ static rt_err_t rt_stm32_eth_init(rt_device_t dev) EthHandle.Init.RxMode = ETH_RXINTERRUPT_MODE; #ifdef RT_LWIP_USING_HW_CHECKSUM EthHandle.Init.ChecksumMode = ETH_CHECKSUM_BY_HARDWARE; -#else +#else EthHandle.Init.ChecksumMode = ETH_CHECKSUM_BY_SOFTWARE; #endif - + HAL_ETH_DeInit(&EthHandle); /* configure ethernet peripheral (GPIOs, clocks, MAC, DMA) */ @@ -431,31 +431,34 @@ static void phy_monitor_thread_entry(void *parameter) uint8_t phy_addr = 0xFF; uint8_t phy_speed_new = 0; rt_uint32_t status = 0; + uint8_t detected_count = 0; - /* phy search */ - rt_uint32_t i, temp; - for (i = 0; i <= 0x1F; i++) + while(phy_addr == 0xFF) { - EthHandle.Init.PhyAddress = i; - - HAL_ETH_ReadPHYRegister(&EthHandle, PHY_ID1_REG, (uint32_t *)&temp); - - if (temp != 0xFFFF && temp != 0x00) + /* phy search */ + rt_uint32_t i, temp; + for (i = 0; i <= 0x1F; i++) { - phy_addr = i; - break; + EthHandle.Init.PhyAddress = i; + HAL_ETH_ReadPHYRegister(&EthHandle, PHY_ID1_REG, (uint32_t *)&temp); + + if (temp != 0xFFFF && temp != 0x00) + { + phy_addr = i; + break; + } + } + + detected_count++; + rt_thread_mdelay(1000); + + if (detected_count > 10) + { + LOG_E("No PHY device was detected, please check hardware!"); } } - if (phy_addr == 0xFF) - { - LOG_E("phy not probe!"); - return; - } - else - { - LOG_D("found a phy, address:0x%02X", phy_addr); - } + LOG_D("Found a phy, address:0x%02X", phy_addr); /* RESET PHY */ LOG_D("RESET PHY!"); @@ -667,4 +670,4 @@ __exit: return state; } -INIT_APP_EXPORT(rt_hw_stm32_eth_init); +INIT_DEVICE_EXPORT(rt_hw_stm32_eth_init); diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_gpio.c b/bsp/stm32/libraries/HAL_Drivers/drv_gpio.c index 57442f2739..481d1e3f6b 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_gpio.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_gpio.c @@ -756,6 +756,9 @@ int rt_hw_pin_init(void) #endif #if defined(__HAL_RCC_GPIOG_CLK_ENABLE) + #ifdef SOC_SERIES_STM32L4 + HAL_PWREx_EnableVddIO2(); + #endif __HAL_RCC_GPIOG_CLK_ENABLE(); #endif diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_hwtimer.c b/bsp/stm32/libraries/HAL_Drivers/drv_hwtimer.c index d8ad946fd0..49bb35e7a3 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_hwtimer.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_hwtimer.c @@ -399,7 +399,7 @@ void TIM8_UP_TIM13_IRQHandler(void) } #endif #ifdef BSP_USING_TIM14 -#if defined(SOC_SERIES_STM32F4) +#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) void TIM8_TRG_COM_TIM14_IRQHandler(void) #elif defined(SOC_SERIES_STM32F0) void TIM14_IRQHandler(void) diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_lptim.c b/bsp/stm32/libraries/HAL_Drivers/drv_lptim.c new file mode 100644 index 0000000000..64e602fa52 --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/drv_lptim.c @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-05-06 Zero-Free first version + */ + +#include +#include + +static LPTIM_HandleTypeDef LptimHandle; + +void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim) +{ + if (hlptim->Instance == LPTIM1) + { + /* Peripheral clock enable */ + __HAL_RCC_LPTIM1_CLK_ENABLE(); + } +} + +void LPTIM1_IRQHandler(void) +{ + HAL_LPTIM_IRQHandler(&LptimHandle); +} + +void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +/** + * This function get current count value of LPTIM + * + * @return the count vlaue + */ +rt_uint32_t stm32l4_lptim_get_current_tick(void) +{ + return HAL_LPTIM_ReadCounter(&LptimHandle); +} + +/** + * This function get the max value that LPTIM can count + * + * @return the max count + */ +rt_uint32_t stm32l4_lptim_get_tick_max(void) +{ + return (0xFFFF); +} + +/** + * This function start LPTIM with reload value + * + * @param reload The value that LPTIM count down from + * + * @return RT_EOK + */ +rt_err_t stm32l4_lptim_start(rt_uint32_t reload) +{ + HAL_LPTIM_TimeOut_Start_IT(&LptimHandle, 0xFFFF, reload); + + return (RT_EOK); +} + +/** + * This function stop LPTIM + */ +void stm32l4_lptim_stop(void) +{ + rt_uint32_t _ier; + + _ier = LptimHandle.Instance->IER; + LptimHandle.Instance->ICR = LptimHandle.Instance->ISR & _ier; +} + +/** + * This function get the count clock of LPTIM + * + * @return the count clock frequency in Hz + */ +rt_uint32_t stm32l4_lptim_get_countfreq(void) +{ + return 32000 / 32; +} + +/** + * This function initialize the lptim + */ +int stm32l4_hw_lptim_init(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct = {0}; + + /* Enable LSI clock */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + HAL_RCC_OscConfig(&RCC_OscInitStruct); + + /* Select the LSI clock as LPTIM peripheral clock */ + RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPTIM1; + RCC_PeriphCLKInitStruct.Lptim1ClockSelection = RCC_LPTIM1CLKSOURCE_LSI; + HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInitStruct); + + LptimHandle.Instance = LPTIM1; + LptimHandle.Init.Clock.Source = LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC; + LptimHandle.Init.Clock.Prescaler = LPTIM_PRESCALER_DIV32; + LptimHandle.Init.Trigger.Source = LPTIM_TRIGSOURCE_SOFTWARE; + LptimHandle.Init.OutputPolarity = LPTIM_OUTPUTPOLARITY_HIGH; + LptimHandle.Init.UpdateMode = LPTIM_UPDATE_IMMEDIATE; + LptimHandle.Init.CounterSource = LPTIM_COUNTERSOURCE_INTERNAL; + if (HAL_LPTIM_Init(&LptimHandle) != HAL_OK) + { + return -1; + } + + NVIC_ClearPendingIRQ(LPTIM1_IRQn); + NVIC_SetPriority(LPTIM1_IRQn, 0); + NVIC_EnableIRQ(LPTIM1_IRQn); + + return 0; +} + +INIT_DEVICE_EXPORT(stm32l4_hw_lptim_init); diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_lptim.h b/bsp/stm32/libraries/HAL_Drivers/drv_lptim.h new file mode 100644 index 0000000000..0fd51b5eac --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/drv_lptim.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-05-06 Zero-Free first version + */ + +#ifndef __DRV_PMTIMER_H__ +#define __DRV_PMTIMER_H__ + +#include + +rt_uint32_t stm32l4_lptim_get_countfreq(void); +rt_uint32_t stm32l4_lptim_get_tick_max(void); +rt_uint32_t stm32l4_lptim_get_current_tick(void); + +rt_err_t stm32l4_lptim_start(rt_uint32_t load); +void stm32l4_lptim_stop(void); + +#endif /* __DRV_PMTIMER_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_pm.c b/bsp/stm32/libraries/HAL_Drivers/drv_pm.c new file mode 100644 index 0000000000..84ddf6cd41 --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/drv_pm.c @@ -0,0 +1,248 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-05-06 Zero-Free first version + */ + +#include +#include + +static void uart_console_reconfig(void) +{ + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + + rt_device_control(rt_console_get_device(), RT_DEVICE_CTRL_CONFIG, &config); +} + +/** + * This function will put STM32L4xx into sleep mode. + * + * @param pm pointer to power manage structure + */ +static void sleep(struct rt_pm *pm, uint8_t mode) +{ + switch (mode) + { + case PM_SLEEP_MODE_NONE: + break; + + case PM_SLEEP_MODE_IDLE: + // __WFI(); + break; + + case PM_SLEEP_MODE_LIGHT: + if (pm->run_mode == PM_RUN_MODE_LOW_SPEED) + { + /* Enter LP SLEEP Mode, Enable low-power regulator */ + HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFI); + } + else + { + /* Enter SLEEP Mode, Main regulator is ON */ + HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI); + } + break; + + case PM_SLEEP_MODE_DEEP: + /* Enter STOP 2 mode */ + HAL_PWREx_EnterSTOP2Mode(PWR_STOPENTRY_WFI); + /* Re-configure the system clock */ + SystemClock_ReConfig(pm->run_mode); + break; + + case PM_SLEEP_MODE_STANDBY: + /* Enter STANDBY mode */ + HAL_PWR_EnterSTANDBYMode(); + break; + + case PM_SLEEP_MODE_SHUTDOWN: + /* Enter SHUTDOWNN mode */ + HAL_PWREx_EnterSHUTDOWNMode(); + break; + + default: + RT_ASSERT(0); + break; + } +} + +static uint8_t run_speed[PM_RUN_MODE_MAX][2] = +{ + {80, 0}, + {80, 1}, + {24, 2}, + {2, 3}, +}; + +static void run(struct rt_pm *pm, uint8_t mode) +{ + static uint8_t last_mode; + static char *run_str[] = PM_RUN_MODE_NAMES; + + if (mode == last_mode) + return; + last_mode = mode; + + /* 1. 设置 MSI 作为 SYSCLK 时钟源,以修改 PLL */ + SystemClock_MSI_ON(); + + /* 2. 根据RUN模式切换时钟频率(HSI) */ + switch (mode) + { + case PM_RUN_MODE_HIGH_SPEED: + case PM_RUN_MODE_NORMAL_SPEED: + SystemClock_80M(); + /* Configure the main internal regulator output voltage (Range1 by default)*/ + HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1); + break; + case PM_RUN_MODE_MEDIUM_SPEED: + SystemClock_24M(); + /* Configure the main internal regulator output voltage */ + HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE2); + break; + case PM_RUN_MODE_LOW_SPEED: + SystemClock_2M(); + /* Enter LP RUN mode */ + HAL_PWREx_EnableLowPowerRunMode(); + break; + default: + break; + } + + /* 3. 关闭 MSI 时钟 */ + // SystemClock_MSI_OFF(); + + /* 4. 更新外设时钟 */ + uart_console_reconfig(); + /* Re-Configure the Systick time */ + HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / RT_TICK_PER_SECOND); + /* Re-Configure the Systick */ + HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK); + + rt_kprintf("switch to %s mode, frequency = %d MHz\n", run_str[mode], run_speed[mode][0]); +} + +/** + * This function caculate the PM tick from OS tick + * + * @param tick OS tick + * + * @return the PM tick + */ +static rt_tick_t stm32l4_pm_tick_from_os_tick(rt_tick_t tick) +{ + rt_uint32_t freq = stm32l4_lptim_get_countfreq(); + + return (freq * tick / RT_TICK_PER_SECOND); +} + +/** + * This function caculate the OS tick from PM tick + * + * @param tick PM tick + * + * @return the OS tick + */ +static rt_tick_t stm32l4_os_tick_from_pm_tick(rt_uint32_t tick) +{ + static rt_uint32_t os_tick_remain = 0; + rt_uint32_t ret, freq; + + freq = stm32l4_lptim_get_countfreq(); + ret = (tick * RT_TICK_PER_SECOND + os_tick_remain) / freq; + + os_tick_remain += (tick * RT_TICK_PER_SECOND); + os_tick_remain %= freq; + + return ret; +} + +/** + * This function start the timer of pm + * + * @param pm Pointer to power manage structure + * @param timeout How many OS Ticks that MCU can sleep + */ +static void pm_timer_start(struct rt_pm *pm, rt_uint32_t timeout) +{ + RT_ASSERT(pm != RT_NULL); + RT_ASSERT(timeout > 0); + + if (timeout != RT_TICK_MAX) + { + /* Convert OS Tick to pmtimer timeout value */ + timeout = stm32l4_pm_tick_from_os_tick(timeout); + if (timeout > stm32l4_lptim_get_tick_max()) + { + timeout = stm32l4_lptim_get_tick_max(); + } + + /* Enter PM_TIMER_MODE */ + stm32l4_lptim_start(timeout); + } +} + +/** + * This function stop the timer of pm + * + * @param pm Pointer to power manage structure + */ +static void pm_timer_stop(struct rt_pm *pm) +{ + RT_ASSERT(pm != RT_NULL); + + /* Reset pmtimer status */ + stm32l4_lptim_stop(); +} + +/** + * This function calculate how many OS Ticks that MCU have suspended + * + * @param pm Pointer to power manage structure + * + * @return OS Ticks + */ +static rt_tick_t pm_timer_get_tick(struct rt_pm *pm) +{ + rt_uint32_t timer_tick; + + RT_ASSERT(pm != RT_NULL); + + timer_tick = stm32l4_lptim_get_current_tick(); + + return stm32l4_os_tick_from_pm_tick(timer_tick); +} + +/** + * This function initialize the power manager + */ +int drv_pm_hw_init(void) +{ + static const struct rt_pm_ops _ops = + { + sleep, + run, + pm_timer_start, + pm_timer_stop, + pm_timer_get_tick + }; + + rt_uint8_t timer_mask = 0; + + /* Enable Power Clock */ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* initialize timer mask */ + timer_mask = 1UL << PM_SLEEP_MODE_DEEP; + + /* initialize system pm module */ + rt_system_pm_init(&_ops, timer_mask, RT_NULL); + + return 0; +} + +INIT_BOARD_EXPORT(drv_pm_hw_init); diff --git a/bsp/stm32/libraries/STM32L4xx_HAL/SConscript b/bsp/stm32/libraries/STM32L4xx_HAL/SConscript index baeda8c18d..5eb48c406c 100644 --- a/bsp/stm32/libraries/STM32L4xx_HAL/SConscript +++ b/bsp/stm32/libraries/STM32L4xx_HAL/SConscript @@ -23,7 +23,6 @@ STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rng.c -STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sram.c ''') if GetDepend(['RT_USING_PIN']): @@ -85,11 +84,32 @@ if GetDepend(['RT_USING_MTD_NOR']): if GetDepend(['RT_USING_MTD_NAND']): src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_nand.c'] +if GetDepend(['RT_USING_PM']): + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_lptim.c'] + if GetDepend(['BSP_USING_ON_CHIP_FLASH']): src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c'] src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c'] src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c'] +if GetDepend(['BSP_USING_FMC']): + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_fmc.c'] + +if GetDepend(['BSP_USING_GFXMMU']): + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gfxmmu.c'] + +if GetDepend(['BSP_USING_DSI']): + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dsi.c'] + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma2d.c'] + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_dma2d.c'] + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ltdc.c'] + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ltdc_ex.c'] + +if GetDepend(['BSP_USING_SRAM']): + src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sram.c'] + + + path = [cwd + '/STM32L4xx_HAL_Driver/Inc', cwd + '/CMSIS/Device/ST/STM32L4xx/Include', cwd + '/CMSIS/Include'] diff --git a/bsp/stm32/libraries/templates/stm32f0xx/board/board.h b/bsp/stm32/libraries/templates/stm32f0xx/board/board.h index 3be9e75cfc..fbc2af5ebe 100644 --- a/bsp/stm32/libraries/templates/stm32f0xx/board/board.h +++ b/bsp/stm32/libraries/templates/stm32f0xx/board/board.h @@ -28,7 +28,7 @@ extern "C" { #define STM32_SRAM_SIZE 32 #define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) -#ifdef __CC_ARM +#if defined(__CC_ARM) || defined(__CLANG_ARM) extern int Image$$RW_IRAM1$$ZI$$Limit; #define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) #elif __ICCARM__ diff --git a/bsp/stm32/libraries/templates/stm32f10x/board/board.h b/bsp/stm32/libraries/templates/stm32f10x/board/board.h index a01a233cc2..fc435ee029 100644 --- a/bsp/stm32/libraries/templates/stm32f10x/board/board.h +++ b/bsp/stm32/libraries/templates/stm32f10x/board/board.h @@ -28,7 +28,7 @@ extern "C" { #define STM32_SRAM_SIZE 20 #define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) -#ifdef __CC_ARM +#if defined(__CC_ARM) || defined(__CLANG_ARM) extern int Image$$RW_IRAM1$$ZI$$Limit; #define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) #elif __ICCARM__ diff --git a/bsp/stm32/libraries/templates/stm32l4xx/board/board.h b/bsp/stm32/libraries/templates/stm32l4xx/board/board.h index ba568f0f2c..b5120ac476 100644 --- a/bsp/stm32/libraries/templates/stm32l4xx/board/board.h +++ b/bsp/stm32/libraries/templates/stm32l4xx/board/board.h @@ -29,7 +29,7 @@ extern "C" { #define STM32_SRAM1_START (0x20000000) #define STM32_SRAM1_END (STM32_SRAM1_START + STM32_SRAM1_SIZE * 1024) -#ifdef __CC_ARM +#if defined(__CC_ARM) || defined(__CLANG_ARM) extern int Image$$RW_IRAM1$$ZI$$Limit; #define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) #elif __ICCARM__ diff --git a/bsp/stm32/stm32f091-st-nucleo/board/board.h b/bsp/stm32/stm32f091-st-nucleo/board/board.h index b203d9336a..7a78136471 100644 --- a/bsp/stm32/stm32f091-st-nucleo/board/board.h +++ b/bsp/stm32/stm32f091-st-nucleo/board/board.h @@ -28,7 +28,7 @@ extern "C" { #define STM32_SRAM_SIZE 32 #define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) -#ifdef __CC_ARM +#if defined(__CC_ARM) || defined(__CLANG_ARM) extern int Image$$RW_IRAM1$$ZI$$Limit; #define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) #elif __ICCARM__ diff --git a/bsp/stm32/stm32f103-atk-nano/board/board.h b/bsp/stm32/stm32f103-atk-nano/board/board.h index 33d4e4bc25..a33ef3cd5e 100644 --- a/bsp/stm32/stm32f103-atk-nano/board/board.h +++ b/bsp/stm32/stm32f103-atk-nano/board/board.h @@ -27,7 +27,7 @@ extern "C" { #define STM32_SRAM_SIZE 20 #define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) -#ifdef __CC_ARM +#if defined(__CC_ARM) || defined(__CLANG_ARM) extern int Image$$RW_IRAM1$$ZI$$Limit; #define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) #elif __ICCARM__ diff --git a/bsp/stm32/stm32f103-atk-warshipv3/board/board.h b/bsp/stm32/stm32f103-atk-warshipv3/board/board.h index d106345785..68ac34f5f7 100644 --- a/bsp/stm32/stm32f103-atk-warshipv3/board/board.h +++ b/bsp/stm32/stm32f103-atk-warshipv3/board/board.h @@ -28,7 +28,7 @@ extern "C" { #define STM32_SRAM_SIZE 64 #define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) -#ifdef __CC_ARM +#if defined(__CC_ARM) || defined(__CLANG_ARM) extern int Image$$RW_IRAM1$$ZI$$Limit; #define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) #elif __ICCARM__ diff --git a/bsp/stm32/stm32f103-dofly-M3S/.config b/bsp/stm32/stm32f103-dofly-M3S/.config index 5a9531ed5f..f985cfd166 100644 --- a/bsp/stm32/stm32f103-dofly-M3S/.config +++ b/bsp/stm32/stm32f103-dofly-M3S/.config @@ -106,10 +106,6 @@ CONFIG_FINSH_ARG_MAX=10 # Device virtual file system # # CONFIG_RT_USING_DFS is not set -# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set -# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set -# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set -# CONFIG_RT_DFS_ELM_USE_LFN_3 is not set # # Device Drivers @@ -321,6 +317,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_MPU6XXX is not set # CONFIG_PKG_USING_PCF8574 is not set # CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set # CONFIG_PKG_USING_KENDRYTE_SDK is not set # @@ -347,47 +344,20 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set # CONFIG_PKG_USING_HELLO is not set # CONFIG_PKG_USING_VI is not set - -# -# Privated Packages of RealThread -# -# CONFIG_PKG_USING_CODEC is not set -# CONFIG_PKG_USING_PLAYER is not set -# CONFIG_PKG_USING_MPLAYER is not set -# CONFIG_PKG_USING_PERSIMMON_SRC is not set -# CONFIG_PKG_USING_JS_PERSIMMON is not set -# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set -# CONFIG_PKG_USING_LIBRWS is not set - -# -# Network Utilities -# -# CONFIG_PKG_USING_WICED is not set -# CONFIG_PKG_USING_CLOUDSDK is not set -# CONFIG_PKG_USING_COREMARK is not set -# CONFIG_PKG_USING_POWER_MANAGER is not set -# CONFIG_PKG_USING_RT_OTA is not set -# CONFIG_PKG_USING_RDBD_SRC is not set -# CONFIG_PKG_USING_RTINSIGHT is not set -# CONFIG_PKG_USING_SMARTCONFIG is not set -# CONFIG_PKG_USING_RTX is not set -# CONFIG_RT_USING_TESTCASE is not set -# CONFIG_PKG_USING_NGHTTP2 is not set -# CONFIG_PKG_USING_AVS is not set -# CONFIG_PKG_USING_STS is not set -# CONFIG_PKG_USING_DLMS is not set CONFIG_SOC_FAMILY_STM32=y CONFIG_SOC_SERIES_STM32F1=y # # Hardware Drivers Config # -CONFIG_SOC_STM32F103RB=y +CONFIG_SOC_STM32F103ZE=y # # Onboard Peripheral Drivers # # CONFIG_BSP_USING_SDCARD is not set +# CONFIG_BSP_USING_SPI_FLASH is not set +# CONFIG_BSP_USING_EEPROM is not set # # On-chip Peripheral Drivers @@ -395,6 +365,9 @@ CONFIG_SOC_STM32F103RB=y CONFIG_BSP_USING_GPIO=y CONFIG_BSP_USING_UART=y CONFIG_BSP_USING_UART1=y +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_I2C2 is not set +# CONFIG_BSP_USING_ON_CHIP_FLASH is not set # CONFIG_BSP_USING_SDIO is not set # diff --git a/bsp/stm32/stm32f103-dofly-M3S/README.md b/bsp/stm32/stm32f103-dofly-M3S/README.md index 813106ea16..d17a45983a 100644 --- a/bsp/stm32/stm32f103-dofly-M3S/README.md +++ b/bsp/stm32/stm32f103-dofly-M3S/README.md @@ -23,12 +23,12 @@ STM32F103 德飞莱-尼莫 M3S 是徳飞莱推出的一款基于 ARM Cortex-M3 该开发板常用 **板载资源** 如下： - MCU：STM32F103ZET6，主频 72MHz，512KB FLASH ，64KB RAM -- 外部 RAM：型号24c02，2KB +- 外部 RAM：型号24C02，2KB - 外部 FLASH：型号W25Q64，8MB - 常用外设 - LED：2个，LED2（红色，PE5），LED3（红色，PB5） - 按键：4个，S1（PE4），S2（PE3），S3（PE2），S4（兼具唤醒功能，PA0） -- 常用接口：USB 转串口、SD 卡接口、RS232 接口、LCD 接口、nRF24L01接口等 +- 常用接口：USB 转串口、SD 卡接口、RS232 接口、LCD 接口、NRF24L01接口等 - 调试接口，标准 JTAG/SWD 开发板更多详细信息请参考徳飞莱的 [STM32F103-尼莫M3S 开发板介绍](https://item.taobao.com/item.htm?spm=a1z10.1-c.w4004-1022655459.10.44ae4d22Wa8UIo&id=44835368405)。 @@ -40,12 +40,17 @@ STM32F103 德飞莱-尼莫 M3S 是徳飞莱推出的一款基于 ARM Cortex-M3 | **板载外设** | **支持情况** | **备注** | | :-----: | :-----: | :-----: | | SDCARD | 支持 | | +| SPI FLASH | 支持 | W25Q64，8MB | +| EEPRAM | 支持 | 24c02，2KB | | **片上外设** | **支持情况** | **备注** | | GPIO | 支持 | | | USART | 支持 | USART1 | | SDIO | 支持 | | +| SPI | 支持 | SPI1/2/3 | +| I2C | 支持 | 软件I2C | +| FLASH | 支持 | 已适配 [FAL](https://github.com/RT-Thread-packages/fal) | | **扩展模块** | **支持情况** | **备注** | -| 暂无 | 暂不支持 | 暂不支持 | +| NRF24L01 | 暂不支持 | 即将支持 | ## 使用说明 diff --git a/bsp/stm32/stm32f103-dofly-M3S/board/CubeMX_Config/.mxproject b/bsp/stm32/stm32f103-dofly-M3S/board/CubeMX_Config/.mxproject index d0b9166e50..abdc42cf6f 100644 --- a/bsp/stm32/stm32f103-dofly-M3S/board/CubeMX_Config/.mxproject +++ b/bsp/stm32/stm32f103-dofly-M3S/board/CubeMX_Config/.mxproject @@ -5,9 +5,9 @@ SourcePath=D:/Workspace/RT-Thread/My_GitHub/rt-thread/bsp/stm32/stm32f103-dofly- SourceFiles=stm32f1xx_it.c;stm32f1xx_hal_msp.c;main.c; [PreviousLibFiles] -LibFiles=Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_sdmmc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sd.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_sdmmc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sd.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_sdmmc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sd.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;Drivers/CMSIS/Include/arm_common_tables.h;Drivers/CMSIS/Include/arm_const_structs.h;Drivers/CMSIS/Include/arm_math.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armcc_V6.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cmFunc.h;Drivers/CMSIS/Include/core_cmInstr.h;Drivers/CMSIS/Include/core_cmSimd.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h; +LibFiles=Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_sdmmc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sd.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_spi.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_sdmmc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sd.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_sdmmc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sd.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_spi.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;Drivers/CMSIS/Include/arm_common_tables.h;Drivers/CMSIS/Include/arm_const_structs.h;Drivers/CMSIS/Include/arm_math.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armcc_V6.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cmFunc.h;Drivers/CMSIS/Include/core_cmInstr.h;Drivers/CMSIS/Include/core_cmSimd.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h; [PreviousUsedKeilFiles] -SourceFiles=..\Src\main.c;..\Src\stm32f1xx_it.c;..\Src\stm32f1xx_hal_msp.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_sdmmc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sd.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../\Src/system_stm32f1xx.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_sdmmc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sd.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../\Src/system_stm32f1xx.c;../Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;null; +SourceFiles=..\Src\main.c;..\Src\stm32f1xx_it.c;..\Src\stm32f1xx_hal_msp.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_sdmmc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sd.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../\Src/system_stm32f1xx.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_sdmmc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sd.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../\Src/system_stm32f1xx.c;../Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;null; HeaderPath=..\Drivers\STM32F1xx_HAL_Driver\Inc;..\Drivers\STM32F1xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32F1xx\Include;..\Drivers\CMSIS\Include;..\Inc; diff --git a/bsp/stm32/stm32f103-dofly-M3S/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32f103-dofly-M3S/board/CubeMX_Config/CubeMX_Config.ioc index 5494ead75f..e897be5421 100644 --- a/bsp/stm32/stm32f103-dofly-M3S/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32f103-dofly-M3S/board/CubeMX_Config/CubeMX_Config.ioc @@ -5,27 +5,39 @@ Mcu.Family=STM32F1 Mcu.IP0=NVIC Mcu.IP1=RCC Mcu.IP2=SDIO -Mcu.IP3=SYS -Mcu.IP4=USART1 -Mcu.IPNb=5 +Mcu.IP3=SPI1 +Mcu.IP4=SPI2 +Mcu.IP5=SPI3 +Mcu.IP6=SYS +Mcu.IP7=USART1 +Mcu.IPNb=8 Mcu.Name=STM32F103Z(C-D-E)Tx Mcu.Package=LQFP144 Mcu.Pin0=PC14-OSC32_IN Mcu.Pin1=PC15-OSC32_OUT -Mcu.Pin10=PC10 -Mcu.Pin11=PC11 -Mcu.Pin12=PC12 -Mcu.Pin13=PD2 -Mcu.Pin14=VP_SYS_VS_Systick +Mcu.Pin10=PC8 +Mcu.Pin11=PC9 +Mcu.Pin12=PA9 +Mcu.Pin13=PA10 +Mcu.Pin14=PA13 +Mcu.Pin15=PA14 +Mcu.Pin16=PC10 +Mcu.Pin17=PC11 +Mcu.Pin18=PC12 +Mcu.Pin19=PD2 Mcu.Pin2=OSC_IN +Mcu.Pin20=PB3 +Mcu.Pin21=PB4 +Mcu.Pin22=PB5 +Mcu.Pin23=VP_SYS_VS_Systick Mcu.Pin3=OSC_OUT -Mcu.Pin4=PC8 -Mcu.Pin5=PC9 -Mcu.Pin6=PA9 -Mcu.Pin7=PA10 -Mcu.Pin8=PA13 -Mcu.Pin9=PA14 -Mcu.PinsNb=15 +Mcu.Pin4=PA5 +Mcu.Pin5=PA6 +Mcu.Pin6=PA7 +Mcu.Pin7=PB13 +Mcu.Pin8=PB14 +Mcu.Pin9=PB15 +Mcu.PinsNb=24 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32F103ZETx @@ -51,8 +63,26 @@ PA13.Mode=Serial_Wire PA13.Signal=SYS_JTMS-SWDIO PA14.Mode=Serial_Wire PA14.Signal=SYS_JTCK-SWCLK +PA5.Mode=Full_Duplex_Master +PA5.Signal=SPI1_SCK +PA6.Mode=Full_Duplex_Master +PA6.Signal=SPI1_MISO +PA7.Mode=Full_Duplex_Master +PA7.Signal=SPI1_MOSI PA9.Mode=Asynchronous PA9.Signal=USART1_TX +PB13.Mode=Full_Duplex_Master +PB13.Signal=SPI2_SCK +PB14.Mode=Full_Duplex_Master +PB14.Signal=SPI2_MISO +PB15.Mode=Full_Duplex_Master +PB15.Signal=SPI2_MOSI +PB3.Mode=Full_Duplex_Master +PB3.Signal=SPI3_SCK +PB4.Mode=Full_Duplex_Master +PB4.Signal=SPI3_MISO +PB5.Mode=Full_Duplex_Master +PB5.Signal=SPI3_MOSI PC10.Mode=SD_4_bits_Wide_bus PC10.Signal=SDIO_D2 PC11.Mode=SD_4_bits_Wide_bus @@ -104,7 +134,7 @@ ProjectManager.StackSize=0x400 ProjectManager.TargetToolchain=MDK-ARM V5 ProjectManager.ToolChainLocation= ProjectManager.UnderRoot=false -ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_SDIO_SD_Init-SDIO-false-HAL-true +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_SDIO_SD_Init-SDIO-false-HAL-true,5-MX_SPI1_Init-SPI1-false-HAL-true,6-MX_SPI2_Init-SPI2-false-HAL-true,7-MX_SPI3_Init-SPI3-false-HAL-true RCC.ADCFreqValue=36000000 RCC.AHBFreq_Value=72000000 RCC.APB1CLKDivider=RCC_HCLK_DIV2 @@ -131,6 +161,22 @@ RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK RCC.TimSysFreq_Value=72000000 RCC.USBFreq_Value=72000000 RCC.VCOOutput2Freq_Value=8000000 +SPI1.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_4 +SPI1.CalculateBaudRate=18.0 MBits/s +SPI1.Direction=SPI_DIRECTION_2LINES +SPI1.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,BaudRatePrescaler +SPI1.Mode=SPI_MODE_MASTER +SPI1.VirtualType=VM_MASTER +SPI2.CalculateBaudRate=18.0 MBits/s +SPI2.Direction=SPI_DIRECTION_2LINES +SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate +SPI2.Mode=SPI_MODE_MASTER +SPI2.VirtualType=VM_MASTER +SPI3.CalculateBaudRate=18.0 MBits/s +SPI3.Direction=SPI_DIRECTION_2LINES +SPI3.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate +SPI3.Mode=SPI_MODE_MASTER +SPI3.VirtualType=VM_MASTER USART1.IPParameters=VirtualMode USART1.VirtualMode=VM_ASYNC VP_SYS_VS_Systick.Mode=SysTick diff --git a/bsp/stm32/stm32f103-dofly-M3S/board/CubeMX_Config/Inc/stm32f1xx_hal_conf.h b/bsp/stm32/stm32f103-dofly-M3S/board/CubeMX_Config/Inc/stm32f1xx_hal_conf.h index 7b61da72d7..f4c58b69fe 100644 --- a/bsp/stm32/stm32f103-dofly-M3S/board/CubeMX_Config/Inc/stm32f1xx_hal_conf.h +++ b/bsp/stm32/stm32f103-dofly-M3S/board/CubeMX_Config/Inc/stm32f1xx_hal_conf.h @@ -76,7 +76,7 @@ /*#define HAL_MMC_MODULE_ENABLED */ /*#define HAL_SDRAM_MODULE_ENABLED */ /*#define HAL_SMARTCARD_MODULE_ENABLED */ -/*#define HAL_SPI_MODULE_ENABLED */ +#define HAL_SPI_MODULE_ENABLED /*#define HAL_SRAM_MODULE_ENABLED */ /*#define HAL_TIM_MODULE_ENABLED */ #define HAL_UART_MODULE_ENABLED diff --git a/bsp/stm32/stm32f103-dofly-M3S/board/CubeMX_Config/Src/main.c b/bsp/stm32/stm32f103-dofly-M3S/board/CubeMX_Config/Src/main.c index 95d2d2ca75..36e9f0da50 100644 --- a/bsp/stm32/stm32f103-dofly-M3S/board/CubeMX_Config/Src/main.c +++ b/bsp/stm32/stm32f103-dofly-M3S/board/CubeMX_Config/Src/main.c @@ -44,6 +44,10 @@ /* Private variables ---------------------------------------------------------*/ SD_HandleTypeDef hsd; +SPI_HandleTypeDef hspi1; +SPI_HandleTypeDef hspi2; +SPI_HandleTypeDef hspi3; + UART_HandleTypeDef huart1; /* USER CODE BEGIN PV */ @@ -55,6 +59,9 @@ void SystemClock_Config(void); static void MX_GPIO_Init(void); static void MX_USART1_UART_Init(void); static void MX_SDIO_SD_Init(void); +static void MX_SPI1_Init(void); +static void MX_SPI2_Init(void); +static void MX_SPI3_Init(void); /* USER CODE BEGIN PFP */ /* USER CODE END PFP */ @@ -94,6 +101,9 @@ int main(void) MX_GPIO_Init(); MX_USART1_UART_Init(); MX_SDIO_SD_Init(); + MX_SPI1_Init(); + MX_SPI2_Init(); + MX_SPI3_Init(); /* USER CODE BEGIN 2 */ /* USER CODE END 2 */ @@ -182,6 +192,120 @@ static void MX_SDIO_SD_Init(void) } +/** + * @brief SPI1 Initialization Function + * @param None + * @retval None + */ +static void MX_SPI1_Init(void) +{ + + /* USER CODE BEGIN SPI1_Init 0 */ + + /* USER CODE END SPI1_Init 0 */ + + /* USER CODE BEGIN SPI1_Init 1 */ + + /* USER CODE END SPI1_Init 1 */ + /* SPI1 parameter configuration*/ + hspi1.Instance = SPI1; + hspi1.Init.Mode = SPI_MODE_MASTER; + hspi1.Init.Direction = SPI_DIRECTION_2LINES; + hspi1.Init.DataSize = SPI_DATASIZE_8BIT; + hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; + hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; + hspi1.Init.NSS = SPI_NSS_SOFT; + hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_4; + hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; + hspi1.Init.TIMode = SPI_TIMODE_DISABLE; + hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + hspi1.Init.CRCPolynomial = 10; + if (HAL_SPI_Init(&hspi1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN SPI1_Init 2 */ + + /* USER CODE END SPI1_Init 2 */ + +} + +/** + * @brief SPI2 Initialization Function + * @param None + * @retval None + */ +static void MX_SPI2_Init(void) +{ + + /* USER CODE BEGIN SPI2_Init 0 */ + + /* USER CODE END SPI2_Init 0 */ + + /* USER CODE BEGIN SPI2_Init 1 */ + + /* USER CODE END SPI2_Init 1 */ + /* SPI2 parameter configuration*/ + hspi2.Instance = SPI2; + hspi2.Init.Mode = SPI_MODE_MASTER; + hspi2.Init.Direction = SPI_DIRECTION_2LINES; + hspi2.Init.DataSize = SPI_DATASIZE_8BIT; + hspi2.Init.CLKPolarity = SPI_POLARITY_LOW; + hspi2.Init.CLKPhase = SPI_PHASE_1EDGE; + hspi2.Init.NSS = SPI_NSS_SOFT; + hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB; + hspi2.Init.TIMode = SPI_TIMODE_DISABLE; + hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + hspi2.Init.CRCPolynomial = 10; + if (HAL_SPI_Init(&hspi2) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN SPI2_Init 2 */ + + /* USER CODE END SPI2_Init 2 */ + +} + +/** + * @brief SPI3 Initialization Function + * @param None + * @retval None + */ +static void MX_SPI3_Init(void) +{ + + /* USER CODE BEGIN SPI3_Init 0 */ + + /* USER CODE END SPI3_Init 0 */ + + /* USER CODE BEGIN SPI3_Init 1 */ + + /* USER CODE END SPI3_Init 1 */ + /* SPI3 parameter configuration*/ + hspi3.Instance = SPI3; + hspi3.Init.Mode = SPI_MODE_MASTER; + hspi3.Init.Direction = SPI_DIRECTION_2LINES; + hspi3.Init.DataSize = SPI_DATASIZE_8BIT; + hspi3.Init.CLKPolarity = SPI_POLARITY_LOW; + hspi3.Init.CLKPhase = SPI_PHASE_1EDGE; + hspi3.Init.NSS = SPI_NSS_SOFT; + hspi3.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + hspi3.Init.FirstBit = SPI_FIRSTBIT_MSB; + hspi3.Init.TIMode = SPI_TIMODE_DISABLE; + hspi3.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + hspi3.Init.CRCPolynomial = 10; + if (HAL_SPI_Init(&hspi3) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN SPI3_Init 2 */ + + /* USER CODE END SPI3_Init 2 */ + +} + /** * @brief USART1 Initialization Function * @param None @@ -226,6 +350,7 @@ static void MX_GPIO_Init(void) /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE(); } diff --git a/bsp/stm32/stm32f103-dofly-M3S/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c b/bsp/stm32/stm32f103-dofly-M3S/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c index 43ea3e2d4f..1efbf77d5e 100644 --- a/bsp/stm32/stm32f103-dofly-M3S/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c +++ b/bsp/stm32/stm32f103-dofly-M3S/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c @@ -162,6 +162,170 @@ void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd) } +/** +* @brief SPI MSP Initialization +* This function configures the hardware resources used in this example +* @param hspi: SPI handle pointer +* @retval None +*/ +void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hspi->Instance==SPI1) + { + /* USER CODE BEGIN SPI1_MspInit 0 */ + + /* USER CODE END SPI1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SPI1_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**SPI1 GPIO Configuration + PA5 ------> SPI1_SCK + PA6 ------> SPI1_MISO + PA7 ------> SPI1_MOSI + */ + GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN SPI1_MspInit 1 */ + + /* USER CODE END SPI1_MspInit 1 */ + } + else if(hspi->Instance==SPI2) + { + /* USER CODE BEGIN SPI2_MspInit 0 */ + + /* USER CODE END SPI2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SPI2_CLK_ENABLE(); + + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**SPI2 GPIO Configuration + PB13 ------> SPI2_SCK + PB14 ------> SPI2_MISO + PB15 ------> SPI2_MOSI + */ + GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_15; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_14; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* USER CODE BEGIN SPI2_MspInit 1 */ + + /* USER CODE END SPI2_MspInit 1 */ + } + else if(hspi->Instance==SPI3) + { + /* USER CODE BEGIN SPI3_MspInit 0 */ + + /* USER CODE END SPI3_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SPI3_CLK_ENABLE(); + + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**SPI3 GPIO Configuration + PB3 ------> SPI3_SCK + PB4 ------> SPI3_MISO + PB5 ------> SPI3_MOSI + */ + GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_5; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_4; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* USER CODE BEGIN SPI3_MspInit 1 */ + + /* USER CODE END SPI3_MspInit 1 */ + } + +} + +/** +* @brief SPI MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hspi: SPI handle pointer +* @retval None +*/ +void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) +{ + if(hspi->Instance==SPI1) + { + /* USER CODE BEGIN SPI1_MspDeInit 0 */ + + /* USER CODE END SPI1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SPI1_CLK_DISABLE(); + + /**SPI1 GPIO Configuration + PA5 ------> SPI1_SCK + PA6 ------> SPI1_MISO + PA7 ------> SPI1_MOSI + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7); + + /* USER CODE BEGIN SPI1_MspDeInit 1 */ + + /* USER CODE END SPI1_MspDeInit 1 */ + } + else if(hspi->Instance==SPI2) + { + /* USER CODE BEGIN SPI2_MspDeInit 0 */ + + /* USER CODE END SPI2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SPI2_CLK_DISABLE(); + + /**SPI2 GPIO Configuration + PB13 ------> SPI2_SCK + PB14 ------> SPI2_MISO + PB15 ------> SPI2_MOSI + */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15); + + /* USER CODE BEGIN SPI2_MspDeInit 1 */ + + /* USER CODE END SPI2_MspDeInit 1 */ + } + else if(hspi->Instance==SPI3) + { + /* USER CODE BEGIN SPI3_MspDeInit 0 */ + + /* USER CODE END SPI3_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SPI3_CLK_DISABLE(); + + /**SPI3 GPIO Configuration + PB3 ------> SPI3_SCK + PB4 ------> SPI3_MISO + PB5 ------> SPI3_MOSI + */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5); + + /* USER CODE BEGIN SPI3_MspDeInit 1 */ + + /* USER CODE END SPI3_MspDeInit 1 */ + } + +} + /** * @brief UART MSP Initialization * This function configures the hardware resources used in this example diff --git a/bsp/stm32/stm32f103-dofly-M3S/board/Kconfig b/bsp/stm32/stm32f103-dofly-M3S/board/Kconfig index 09bcdea46e..421b604de3 100644 --- a/bsp/stm32/stm32f103-dofly-M3S/board/Kconfig +++ b/bsp/stm32/stm32f103-dofly-M3S/board/Kconfig @@ -1,6 +1,6 @@ menu "Hardware Drivers Config" -config SOC_STM32F103RB +config SOC_STM32F103ZE bool select SOC_SERIES_STM32F1 default y @@ -14,7 +14,19 @@ menu "Onboard Peripheral Drivers" select RT_USING_DFS_ELMFAT select RT_USING_PIN default n - + + config BSP_USING_SPI_FLASH + bool "Enable SPI FLASH (W25Q64 spi2)" + select BSP_USING_SPI + select BSP_USING_SPI2 + select RT_USING_SFUD + select RT_SFUD_USING_SFDP + default n + + config BSP_USING_EEPROM + bool "Enable I2C EEPROM (i2c2)" + select BSP_USING_I2C2 + default n endmenu menu "On-chip Peripheral Drivers" @@ -35,6 +47,79 @@ menu "On-chip Peripheral Drivers" endif + menuconfig BSP_USING_SPI + bool "Enable SPI BUS" + default n + select RT_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI1 + bool "Enable SPI1 BUS" + default n + + config BSP_SPI1_TX_USING_DMA + bool "Enable SPI1 TX DMA" + depends on BSP_USING_SPI1 + default n + + config BSP_SPI1_RX_USING_DMA + bool "Enable SPI1 RX DMA" + depends on BSP_USING_SPI1 + select BSP_SPI1_TX_USING_DMA + default n + + config BSP_USING_SPI2 + bool "Enable SPI2 BUS" + default n + + config BSP_SPI2_TX_USING_DMA + bool "Enable SPI2 TX DMA" + depends on BSP_USING_SPI2 + default n + + config BSP_SPI2_RX_USING_DMA + bool "Enable SPI2 RX DMA" + depends on BSP_USING_SPI2 + select BSP_SPI2_TX_USING_DMA + default n + + config BSP_USING_SPI3 + bool "Enable SPI3 BUS" + default n + + config BSP_SPI3_TX_USING_DMA + bool "Enable SPI3 TX DMA" + depends on BSP_USING_SPI3 + default n + + config BSP_SPI3_RX_USING_DMA + bool "Enable SPI3 RX DMA" + depends on BSP_USING_SPI3 + select BSP_SPI3_TX_USING_DMA + default n + endif + + menuconfig BSP_USING_I2C2 + bool "Enable I2C2 BUS (software simulation)" + default n + select RT_USING_I2C + select RT_USING_I2C_BITOPS + select RT_USING_PIN + if BSP_USING_I2C2 + comment "Notice: PB10 --> 26; PB11 --> 27" + config BSP_I2C2_SCL_PIN + int "i2c2 scl pin number" + range 0 175 + default 26 + config BSP_I2C2_SDA_PIN + int "i2c2 sda pin number" + range 0 175 + default 27 + endif + + config BSP_USING_ON_CHIP_FLASH + bool "Enable on-chip FLASH" + default n + config BSP_USING_SDIO bool "Enable SDIO" select RT_USING_SDIO diff --git a/bsp/stm32/stm32f103-dofly-M3S/board/SConscript b/bsp/stm32/stm32f103-dofly-M3S/board/SConscript index 305eff1c10..c1cc4eef45 100644 --- a/bsp/stm32/stm32f103-dofly-M3S/board/SConscript +++ b/bsp/stm32/stm32f103-dofly-M3S/board/SConscript @@ -14,6 +14,9 @@ CubeMX_Config/Src/stm32f1xx_hal_msp.c if GetDepend(['BSP_USING_SDCARD']): src += Glob('ports/drv_sdcard.c') + +if GetDepend(['BSP_USING_SPI_FLASH']): + src += Glob('ports/spi_flash_init.c') path = [cwd] path += [cwd + '/CubeMX_Config/Inc'] diff --git a/bsp/stm32/stm32f103-dofly-M3S/board/board.h b/bsp/stm32/stm32f103-dofly-M3S/board/board.h index 537e22e953..62f9030426 100644 --- a/bsp/stm32/stm32f103-dofly-M3S/board/board.h +++ b/bsp/stm32/stm32f103-dofly-M3S/board/board.h @@ -29,7 +29,7 @@ extern "C" { #define STM32_SRAM_SIZE 64 #define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) -#ifdef __CC_ARM +#if defined(__CC_ARM) || defined(__CLANG_ARM) extern int Image$$RW_IRAM1$$ZI$$Limit; #define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) #elif __ICCARM__ diff --git a/bsp/stm32/stm32f103-dofly-M3S/board/ports/fal_cfg.h b/bsp/stm32/stm32f103-dofly-M3S/board/ports/fal_cfg.h new file mode 100644 index 0000000000..5f83366ea0 --- /dev/null +++ b/bsp/stm32/stm32f103-dofly-M3S/board/ports/fal_cfg.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-5 SummerGift first version + */ + +#ifndef _FAL_CFG_H_ +#define _FAL_CFG_H_ + +#include +#include + +extern const struct fal_flash_dev stm32_onchip_flash; + +/* flash device table */ +#define FAL_FLASH_DEV_TABLE \ +{ \ + &stm32_onchip_flash, \ +} +/* ====================== Partition Configuration ========================== */ +#ifdef FAL_PART_HAS_TABLE_CFG + +/* partition table */ +#define FAL_PART_TABLE \ +{ \ + {FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 496 * 1024, 0}, \ + {FAL_PART_MAGIC_WROD, "param", "onchip_flash", 496* 1024 , 16 * 1024, 0}, \ +} +#endif /* FAL_PART_HAS_TABLE_CFG */ +#endif /* _FAL_CFG_H_ */ diff --git a/bsp/stm32/stm32f103-dofly-M3S/board/ports/spi_flash_init.c b/bsp/stm32/stm32f103-dofly-M3S/board/ports/spi_flash_init.c new file mode 100644 index 0000000000..060c6d59b4 --- /dev/null +++ b/bsp/stm32/stm32f103-dofly-M3S/board/ports/spi_flash_init.c @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-27 SummerGift add spi flash port file + */ + +#include +#include "spi_flash.h" +#include "spi_flash_sfud.h" +#include "drv_spi.h" + +#if defined(BSP_USING_SPI_FLASH) +static int rt_hw_spi_flash_init(void) +{ + __HAL_RCC_GPIOA_CLK_ENABLE(); + rt_hw_spi_device_attach("spi2", "spi20", GPIOB, GPIO_PIN_12); + + if (RT_NULL == rt_sfud_flash_probe("W25Q64", "spi20")) + { + return -RT_ERROR; + }; + + return RT_EOK; +} +INIT_COMPONENT_EXPORT(rt_hw_spi_flash_init); +#endif + diff --git a/bsp/stm32/stm32f103-dofly-M3S/project.uvoptx b/bsp/stm32/stm32f103-dofly-M3S/project.uvoptx index 818ec4ab96..c6d74a9049 100644 --- a/bsp/stm32/stm32f103-dofly-M3S/project.uvoptx +++ b/bsp/stm32/stm32f103-dofly-M3S/project.uvoptx @@ -178,6 +178,7 @@ 1 + 0 0 2 10000000 @@ -186,731 +187,11 @@ - Kernel + Source Group 1 0 0 0 0 - - 1 - 1 - 1 - 0 - 0 - 0 - ..\..\..\src\clock.c - clock.c - 0 - 0 - - - 1 - 2 - 1 - 0 - 0 - 0 - ..\..\..\src\components.c - components.c - 0 - 0 - - - 1 - 3 - 1 - 0 - 0 - 0 - ..\..\..\src\cpu.c - cpu.c - 0 - 0 - - - 1 - 4 - 1 - 0 - 0 - 0 - ..\..\..\src\device.c - device.c - 0 - 0 - - - 1 - 5 - 1 - 0 - 0 - 0 - ..\..\..\src\idle.c - idle.c - 0 - 0 - - - 1 - 6 - 1 - 0 - 0 - 0 - ..\..\..\src\ipc.c - ipc.c - 0 - 0 - - - 1 - 7 - 1 - 0 - 0 - 0 - ..\..\..\src\irq.c - irq.c - 0 - 0 - - - 1 - 8 - 1 - 0 - 0 - 0 - ..\..\..\src\kservice.c - kservice.c - 0 - 0 - - - 1 - 9 - 1 - 0 - 0 - 0 - ..\..\..\src\mem.c - mem.c - 0 - 0 - - - 1 - 10 - 1 - 0 - 0 - 0 - ..\..\..\src\mempool.c - mempool.c - 0 - 0 - - - 1 - 11 - 1 - 0 - 0 - 0 - ..\..\..\src\object.c - object.c - 0 - 0 - - - 1 - 12 - 1 - 0 - 0 - 0 - ..\..\..\src\scheduler.c - scheduler.c - 0 - 0 - - - 1 - 13 - 1 - 0 - 0 - 0 - ..\..\..\src\signal.c - signal.c - 0 - 0 - - - 1 - 14 - 1 - 0 - 0 - 0 - ..\..\..\src\thread.c - thread.c - 0 - 0 - - - 1 - 15 - 1 - 0 - 0 - 0 - ..\..\..\src\timer.c - timer.c - 0 - 0 - - - - - Applications - 0 - 0 - 0 - 0 - - 2 - 16 - 1 - 0 - 0 - 0 - applications\main.c - main.c - 0 - 0 - - - - - Drivers - 0 - 0 - 0 - 0 - - 3 - 17 - 1 - 0 - 0 - 0 - board\board.c - board.c - 0 - 0 - - - 3 - 18 - 1 - 0 - 0 - 0 - board\CubeMX_Config\Src\stm32f1xx_hal_msp.c - stm32f1xx_hal_msp.c - 0 - 0 - - - 3 - 19 - 2 - 0 - 0 - 0 - ..\libraries\STM32F1xx_HAL\CMSIS\Device\ST\STM32F1xx\Source\Templates\arm\startup_stm32f103xe.s - startup_stm32f103xe.s - 0 - 0 - - - 3 - 20 - 1 - 0 - 0 - 0 - ..\libraries\HAL_Drivers\drv_gpio.c - drv_gpio.c - 0 - 0 - - - 3 - 21 - 1 - 0 - 0 - 0 - ..\libraries\HAL_Drivers\drv_usart.c - drv_usart.c - 0 - 0 - - - 3 - 22 - 1 - 0 - 0 - 0 - ..\libraries\HAL_Drivers\drv_common.c - drv_common.c - 0 - 0 - - - - - cpu - 0 - 0 - 0 - 0 - - 4 - 23 - 1 - 0 - 0 - 0 - ..\..\..\libcpu\arm\common\backtrace.c - backtrace.c - 0 - 0 - - - 4 - 24 - 1 - 0 - 0 - 0 - ..\..\..\libcpu\arm\common\div0.c - div0.c - 0 - 0 - - - 4 - 25 - 1 - 0 - 0 - 0 - ..\..\..\libcpu\arm\common\showmem.c - showmem.c - 0 - 0 - - - 4 - 26 - 1 - 0 - 0 - 0 - ..\..\..\libcpu\arm\cortex-m3\cpuport.c - cpuport.c - 0 - 0 - - - 4 - 27 - 2 - 0 - 0 - 0 - ..\..\..\libcpu\arm\cortex-m3\context_rvds.S - context_rvds.S - 0 - 0 - - - - - DeviceDrivers - 0 - 0 - 0 - 0 - - 5 - 28 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\misc\pin.c - pin.c - 0 - 0 - - - 5 - 29 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\serial\serial.c - serial.c - 0 - 0 - - - 5 - 30 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\src\completion.c - completion.c - 0 - 0 - - - 5 - 31 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\src\dataqueue.c - dataqueue.c - 0 - 0 - - - 5 - 32 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\src\pipe.c - pipe.c - 0 - 0 - - - 5 - 33 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\src\ringblk_buf.c - ringblk_buf.c - 0 - 0 - - - 5 - 34 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\src\ringbuffer.c - ringbuffer.c - 0 - 0 - - - 5 - 35 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\src\waitqueue.c - waitqueue.c - 0 - 0 - - - 5 - 36 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\src\workqueue.c - workqueue.c - 0 - 0 - - - - - finsh - 0 - 0 - 0 - 0 - - 6 - 37 - 1 - 0 - 0 - 0 - ..\..\..\components\finsh\shell.c - shell.c - 0 - 0 - - - 6 - 38 - 1 - 0 - 0 - 0 - ..\..\..\components\finsh\symbol.c - symbol.c - 0 - 0 - - - 6 - 39 - 1 - 0 - 0 - 0 - ..\..\..\components\finsh\cmd.c - cmd.c - 0 - 0 - - - 6 - 40 - 1 - 0 - 0 - 0 - ..\..\..\components\finsh\msh.c - msh.c - 0 - 0 - - - 6 - 41 - 1 - 0 - 0 - 0 - ..\..\..\components\finsh\msh_cmd.c - msh_cmd.c - 0 - 0 - - - 6 - 42 - 1 - 0 - 0 - 0 - ..\..\..\components\finsh\msh_file.c - msh_file.c - 0 - 0 - - - - - STM32_HAL - 0 - 0 - 0 - 0 - - 7 - 43 - 1 - 0 - 0 - 0 - ..\libraries\STM32F1xx_HAL\CMSIS\Device\ST\STM32F1xx\Source\Templates\system_stm32f1xx.c - system_stm32f1xx.c - 0 - 0 - - - 7 - 44 - 1 - 0 - 0 - 0 - ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_dma.c - stm32f1xx_hal_dma.c - 0 - 0 - - - 7 - 45 - 1 - 0 - 0 - 0 - ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_cortex.c - stm32f1xx_hal_cortex.c - 0 - 0 - - - 7 - 46 - 1 - 0 - 0 - 0 - ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_crc.c - stm32f1xx_hal_crc.c - 0 - 0 - - - 7 - 47 - 1 - 0 - 0 - 0 - ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_pwr.c - stm32f1xx_hal_pwr.c - 0 - 0 - - - 7 - 48 - 1 - 0 - 0 - 0 - ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc.c - stm32f1xx_hal_rcc.c - 0 - 0 - - - 7 - 49 - 1 - 0 - 0 - 0 - ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc_ex.c - stm32f1xx_hal_rcc_ex.c - 0 - 0 - - - 7 - 50 - 1 - 0 - 0 - 0 - ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal.c - stm32f1xx_hal.c - 0 - 0 - - - 7 - 51 - 1 - 0 - 0 - 0 - ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_cec.c - stm32f1xx_hal_cec.c - 0 - 0 - - - 7 - 52 - 1 - 0 - 0 - 0 - ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_sram.c - stm32f1xx_hal_sram.c - 0 - 0 - - - 7 - 53 - 1 - 0 - 0 - 0 - ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio.c - stm32f1xx_hal_gpio.c - 0 - 0 - - - 7 - 54 - 1 - 0 - 0 - 0 - ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio_ex.c - stm32f1xx_hal_gpio_ex.c - 0 - 0 - - - 7 - 55 - 1 - 0 - 0 - 0 - ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_uart.c - stm32f1xx_hal_uart.c - 0 - 0 - - - 7 - 56 - 1 - 0 - 0 - 0 - ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_usart.c - stm32f1xx_hal_usart.c - 0 - 0 - diff --git a/bsp/stm32/stm32f103-dofly-M3S/project.uvprojx b/bsp/stm32/stm32f103-dofly-M3S/project.uvprojx index ae7a4abef5..d786685471 100644 --- a/bsp/stm32/stm32f103-dofly-M3S/project.uvprojx +++ b/bsp/stm32/stm32f103-dofly-M3S/project.uvprojx @@ -1,10 +1,7 @@ - 2.1 -
### uVision Project, (C) Keil Software
- rt-thread @@ -16,31 +13,31 @@ STM32F103ZE STMicroelectronics - Keil.STM32F1xx_DFP.2.2.0 + Keil.STM32F1xx_DFP.2.3.0 http://www.keil.com/pack/ IRAM(0x20000000,0x00010000) IROM(0x08000000,0x00080000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE - - + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_512 -FS08000000 -FL080000 -FP0($$Device:STM32F103ZE$Flash\STM32F10x_512.FLM)) 0 $$Device:STM32F103ZE$Device\Include\stm32f10x.h - - - - - - - - - + + + + + + + + + $$Device:STM32F103ZE$SVD\STM32F103xx.svd 0 0 - - - - - + + + + + 0 0 @@ -62,8 +59,8 @@ 0 0 - - + + 0 0 0 @@ -72,8 +69,8 @@ 0 0 - - + + 0 0 0 @@ -83,14 +80,14 @@ 1 0 fromelf --bin !L --output rtthread.bin - + 0 0 0 0 0 - + 0 @@ -104,8 +101,8 @@ 0 0 3 - - + + 1 @@ -114,7 +111,7 @@ DCM.DLL -pCM3 SARMCM3.DLL - + TCM.DLL -pCM3 @@ -138,11 +135,11 @@ 1 BIN\UL2CM3.DLL - - - - - + + + + + 0 @@ -175,7 +172,7 @@ 0 0 "Cortex-M3" - + 0 0 0 @@ -184,6 +181,7 @@ 0 0 0 + 0 0 0 8 @@ -307,7 +305,7 @@ 0x0 - + 1 @@ -334,9 +332,9 @@ 0 0 - + USE_HAL_DRIVER, STM32F103xE - + .;..\..\..\include;applications;board;board\CubeMX_Config\Inc;board\ports;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m3;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\libraries\STM32F1xx_HAL\CMSIS\Device\ST\STM32F1xx\Include;..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Inc;..\libraries\STM32F1xx_HAL\CMSIS\Include @@ -352,10 +350,10 @@ 0 0 - - - - + + + + @@ -367,13 +365,13 @@ 0 0x08000000 0x20000000 - + .\board\linker_scripts\link.sct - - - - - + + + + + @@ -386,71 +384,99 @@ 1 ..\..\..\src\clock.c + + components.c 1 ..\..\..\src\components.c + + cpu.c 1 ..\..\..\src\cpu.c + + device.c 1 ..\..\..\src\device.c + + idle.c 1 ..\..\..\src\idle.c + + ipc.c 1 ..\..\..\src\ipc.c + + irq.c 1 ..\..\..\src\irq.c + + kservice.c 1 ..\..\..\src\kservice.c + + mem.c 1 ..\..\..\src\mem.c + + mempool.c 1 ..\..\..\src\mempool.c + + object.c 1 ..\..\..\src\object.c + + scheduler.c 1 ..\..\..\src\scheduler.c + + signal.c 1 ..\..\..\src\signal.c + + thread.c 1 ..\..\..\src\thread.c + + timer.c 1 @@ -476,26 +502,36 @@ 1 board\board.c + + stm32f1xx_hal_msp.c 1 board\CubeMX_Config\Src\stm32f1xx_hal_msp.c + + startup_stm32f103xe.s 2 ..\libraries\STM32F1xx_HAL\CMSIS\Device\ST\STM32F1xx\Source\Templates\arm\startup_stm32f103xe.s + + drv_gpio.c 1 ..\libraries\HAL_Drivers\drv_gpio.c + + drv_usart.c 1 ..\libraries\HAL_Drivers\drv_usart.c + + drv_common.c 1 @@ -511,21 +547,29 @@ 1 ..\..\..\libcpu\arm\common\backtrace.c + + div0.c 1 ..\..\..\libcpu\arm\common\div0.c + + showmem.c 1 ..\..\..\libcpu\arm\common\showmem.c + + cpuport.c 1 ..\..\..\libcpu\arm\cortex-m3\cpuport.c + + context_rvds.S 2 @@ -541,41 +585,57 @@ 1 ..\..\..\components\drivers\misc\pin.c + + serial.c 1 ..\..\..\components\drivers\serial\serial.c + + completion.c 1 ..\..\..\components\drivers\src\completion.c + + dataqueue.c 1 ..\..\..\components\drivers\src\dataqueue.c + + pipe.c 1 ..\..\..\components\drivers\src\pipe.c + + ringblk_buf.c 1 ..\..\..\components\drivers\src\ringblk_buf.c + + ringbuffer.c 1 ..\..\..\components\drivers\src\ringbuffer.c + + waitqueue.c 1 ..\..\..\components\drivers\src\waitqueue.c + + workqueue.c 1 @@ -591,26 +651,36 @@ 1 ..\..\..\components\finsh\shell.c + + symbol.c 1 ..\..\..\components\finsh\symbol.c + + cmd.c 1 ..\..\..\components\finsh\cmd.c + + msh.c 1 ..\..\..\components\finsh\msh.c + + msh_cmd.c 1 ..\..\..\components\finsh\msh_cmd.c + + msh_file.c 1 @@ -626,66 +696,92 @@ 1 ..\libraries\STM32F1xx_HAL\CMSIS\Device\ST\STM32F1xx\Source\Templates\system_stm32f1xx.c + + stm32f1xx_hal_dma.c 1 ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_dma.c + + stm32f1xx_hal_cortex.c 1 ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_cortex.c + + stm32f1xx_hal_crc.c 1 ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_crc.c + + stm32f1xx_hal_pwr.c 1 ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_pwr.c + + stm32f1xx_hal_rcc.c 1 ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc.c + + stm32f1xx_hal_rcc_ex.c 1 ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc_ex.c + + stm32f1xx_hal.c 1 ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal.c + + stm32f1xx_hal_cec.c 1 ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_cec.c + + stm32f1xx_hal_sram.c 1 ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_sram.c + + stm32f1xx_hal_gpio.c 1 ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio.c + + stm32f1xx_hal_gpio_ex.c 1 ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio_ex.c + + stm32f1xx_hal_uart.c 1 ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_uart.c + + stm32f1xx_hal_usart.c 1 @@ -696,11 +792,9 @@ - - - - + + + - diff --git a/bsp/stm32/stm32f103-dofly-M3S/rtconfig.h b/bsp/stm32/stm32f103-dofly-M3S/rtconfig.h index b5c72f4f36..e3d1f1b647 100644 --- a/bsp/stm32/stm32f103-dofly-M3S/rtconfig.h +++ b/bsp/stm32/stm32f103-dofly-M3S/rtconfig.h @@ -155,18 +155,12 @@ /* samples: kernel and components samples */ - -/* Privated Packages of RealThread */ - - -/* Network Utilities */ - #define SOC_FAMILY_STM32 #define SOC_SERIES_STM32F1 /* Hardware Drivers Config */ -#define SOC_STM32F103RB +#define SOC_STM32F103ZE /* Onboard Peripheral Drivers */ diff --git a/bsp/stm32/stm32f103-dofly-lyc8/board/board.h b/bsp/stm32/stm32f103-dofly-lyc8/board/board.h index 134a0a3e6e..ae6f2c67e8 100644 --- a/bsp/stm32/stm32f103-dofly-lyc8/board/board.h +++ b/bsp/stm32/stm32f103-dofly-lyc8/board/board.h @@ -23,7 +23,7 @@ #define STM32_SRAM_SIZE 20 #define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) -#ifdef __CC_ARM +#if defined(__CC_ARM) || defined(__CLANG_ARM) extern int Image$$RW_IRAM1$$ZI$$Limit; #define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) #elif __ICCARM__ diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/board.h b/bsp/stm32/stm32f103-fire-arbitrary/board/board.h index e99fbbee4b..968ac8e2e5 100644 --- a/bsp/stm32/stm32f103-fire-arbitrary/board/board.h +++ b/bsp/stm32/stm32f103-fire-arbitrary/board/board.h @@ -28,7 +28,7 @@ extern "C" { #define STM32_FLASH_SIZE (512 * 1024) #define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE)) -#ifdef __CC_ARM +#if defined(__CC_ARM) || defined(__CLANG_ARM) extern int Image$$RW_IRAM1$$ZI$$Limit; #define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) #elif __ICCARM__ diff --git a/bsp/stm32/stm32f103-hw100k-ibox/board/board.h b/bsp/stm32/stm32f103-hw100k-ibox/board/board.h index f1fdd55578..fe3ea19e77 100644 --- a/bsp/stm32/stm32f103-hw100k-ibox/board/board.h +++ b/bsp/stm32/stm32f103-hw100k-ibox/board/board.h @@ -28,7 +28,7 @@ extern "C" { #define STM32_SRAM_SIZE 64 #define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) -#ifdef __CC_ARM +#if defined(__CC_ARM) || defined(__CLANG_ARM) extern int Image$$RW_IRAM1$$ZI$$Limit; #define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) #elif __ICCARM__ diff --git a/bsp/stm32/stm32f103-mini-system/board/board.h b/bsp/stm32/stm32f103-mini-system/board/board.h index a8ee7bfa02..7f0ae67d48 100644 --- a/bsp/stm32/stm32f103-mini-system/board/board.h +++ b/bsp/stm32/stm32f103-mini-system/board/board.h @@ -28,7 +28,7 @@ extern "C" { #define STM32_SRAM_SIZE 20 #define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) -#ifdef __CC_ARM +#if defined(__CC_ARM) || defined(__CLANG_ARM) extern int Image$$RW_IRAM1$$ZI$$Limit; #define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) #elif __ICCARM__ diff --git a/bsp/stm32/stm32f107-uc-eval/board/board.h b/bsp/stm32/stm32f107-uc-eval/board/board.h index cfcfe1c51b..98df6d51ff 100644 --- a/bsp/stm32/stm32f107-uc-eval/board/board.h +++ b/bsp/stm32/stm32f107-uc-eval/board/board.h @@ -28,7 +28,7 @@ extern "C" { #define STM32_SRAM_SIZE 64 #define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) -#ifdef __CC_ARM +#if defined(__CC_ARM) || defined(__CLANG_ARM) extern int Image$$RW_IRAM1$$ZI$$Limit; #define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) #elif __ICCARM__ diff --git a/bsp/stm32/stm32f407-atk-explorer/board/board.h b/bsp/stm32/stm32f407-atk-explorer/board/board.h index 339b3faaaf..70a4c0ed19 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/board.h +++ b/bsp/stm32/stm32f407-atk-explorer/board/board.h @@ -27,7 +27,7 @@ extern "C" { #define STM32_FLASH_SIZE (1024 * 1024) #define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE)) -#ifdef __CC_ARM +#if defined(__CC_ARM) || defined(__CLANG_ARM) extern int Image$$RW_IRAM1$$ZI$$Limit; #define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) #elif __ICCARM__ diff --git a/bsp/stm32/stm32f767-atk-apollo/board/Kconfig b/bsp/stm32/stm32f767-atk-apollo/board/Kconfig index 04033b2424..77d2f5eaf8 100644 --- a/bsp/stm32/stm32f767-atk-apollo/board/Kconfig +++ b/bsp/stm32/stm32f767-atk-apollo/board/Kconfig @@ -24,7 +24,7 @@ menu "Onboard Peripheral Drivers" default n config BSP_USING_QSPI_FLASH - bool "Enable QSPI FLASH (w25q128 qspi)" + bool "Enable QSPI FLASH (W25Q256 qspi)" select BSP_USING_QSPI select RT_USING_SFUD select RT_SFUD_USING_QSPI diff --git a/bsp/stm32/stm32f767-atk-apollo/board/ports/drv_qspi_flash.c b/bsp/stm32/stm32f767-atk-apollo/board/ports/drv_qspi_flash.c index 36ecb754e9..5cabc9d4d2 100644 --- a/bsp/stm32/stm32f767-atk-apollo/board/ports/drv_qspi_flash.c +++ b/bsp/stm32/stm32f767-atk-apollo/board/ports/drv_qspi_flash.c @@ -64,14 +64,14 @@ static int rt_hw_qspi_flash_with_sfud_init(void) { stm32_qspi_bus_attach_device("qspi1", "qspi10", RT_NULL, 4, w25qxx_enter_qspi_mode, RT_NULL); - /* init w25q128 */ - if (RT_NULL == rt_sfud_flash_probe("W25Q128", "qspi10")) + /* init W25Q256 */ + if (RT_NULL == rt_sfud_flash_probe("W25Q256", "qspi10")) { return -RT_ERROR; } return RT_EOK; } -INIT_COMPONENT_EXPORT(rt_hw_qspi_flash_with_sfud_init); +INIT_DEVICE_EXPORT(rt_hw_qspi_flash_with_sfud_init); #endif/* BSP_USING_QSPI_FLASH */ diff --git a/bsp/stm32/stm32g071-st-nucleo/board/board.h b/bsp/stm32/stm32g071-st-nucleo/board/board.h index 4abb1e6089..f0345a1293 100644 --- a/bsp/stm32/stm32g071-st-nucleo/board/board.h +++ b/bsp/stm32/stm32g071-st-nucleo/board/board.h @@ -28,7 +28,7 @@ extern "C" { #define STM32_SRAM_SIZE 36 #define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) -#ifdef __CC_ARM +#if defined(__CC_ARM) || defined(__CLANG_ARM) extern int Image$$RW_IRAM1$$ZI$$Limit; #define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) #elif __ICCARM__ diff --git a/bsp/stm32/stm32l053-st-nucleo/board/board.h b/bsp/stm32/stm32l053-st-nucleo/board/board.h index c34b2fc117..016e4ec4e3 100644 --- a/bsp/stm32/stm32l053-st-nucleo/board/board.h +++ b/bsp/stm32/stm32l053-st-nucleo/board/board.h @@ -28,7 +28,7 @@ extern "C" { #define STM32_SRAM_SIZE 8 #define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) -#ifdef __CC_ARM +#if defined(__CC_ARM) || defined(__CLANG_ARM) extern int Image$$RW_IRAM1$$ZI$$Limit; #define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) #elif __ICCARM__ diff --git a/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Inc/stm32l4xx_hal_conf.h b/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Inc/stm32l4xx_hal_conf.h index 9fd2fdbd86..5a4d494431 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Inc/stm32l4xx_hal_conf.h +++ b/bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Inc/stm32l4xx_hal_conf.h @@ -69,7 +69,7 @@ #define HAL_IWDG_MODULE_ENABLED /*#define HAL_LTDC_MODULE_ENABLED */ /*#define HAL_LCD_MODULE_ENABLED */ -/*#define HAL_LPTIM_MODULE_ENABLED */ +#define HAL_LPTIM_MODULE_ENABLED /*#define HAL_NAND_MODULE_ENABLED */ /*#define HAL_NOR_MODULE_ENABLED */ /*#define HAL_OPAMP_MODULE_ENABLED */ diff --git a/bsp/stm32/stm32l475-atk-pandora/board/Kconfig b/bsp/stm32/stm32l475-atk-pandora/board/Kconfig index 90cf83801f..f167be8b1f 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/Kconfig +++ b/bsp/stm32/stm32l475-atk-pandora/board/Kconfig @@ -29,6 +29,24 @@ menu "Onboard Peripheral Drivers" select RT_USING_DFS_ELMFAT default n + config BSP_USING_ICM20608 + bool "Enable icm20608 (i2c3)" + select BSP_USING_I2C + select BSP_USING_I2C3 + select PKG_USING_SENSORS_DRIVERS + select PKG_USING_MPU6XXX + select PKG_USING_MPU6XXX_LATEST_VERSION + default n + + config BSP_USING_AHT10 + bool "Enable aht10 (i2c4)" + select BSP_USING_I2C + select BSP_USING_I2C4 + select PKG_USING_SENSORS_DRIVERS + select PKG_USING_AHT10 + select PKG_USING_AHT10_LATEST_VERSION + default n + endmenu menu "On-chip Peripheral Drivers" @@ -112,55 +130,42 @@ menu "On-chip Peripheral Drivers" bool "Enable QSPI DMA support" default n - menuconfig BSP_USING_I2C1 - bool "Enable I2C1 BUS (software simulation)" + menuconfig BSP_USING_I2C + bool "Enable I2C BUS" default n select RT_USING_I2C select RT_USING_I2C_BITOPS select RT_USING_PIN - if BSP_USING_I2C1 - config BSP_I2C1_SCL_PIN - int "i2c1 scl pin number" - range 1 176 - default 15 - config BSP_I2C1_SDA_PIN - int "I2C1 sda pin number" - range 1 176 - default 16 - endif + if BSP_USING_I2C + menuconfig BSP_USING_I2C3 + bool "Enable I2C3 BUS (software simulation)" + default y + if BSP_USING_I2C3 + comment "Notice: PC0 --> 32; PC1 --> 33" + config BSP_I2C3_SCL_PIN + int "i2c3 scl pin number" + range 1 176 + default 32 + config BSP_I2C3_SDA_PIN + int "I2C3 sda pin number" + range 1 176 + default 33 + endif - menuconfig BSP_USING_I2C2 - bool "Enable I2C2 BUS (software simulation)" - default n - select RT_USING_I2C - select RT_USING_I2C_BITOPS - select RT_USING_PIN - if BSP_USING_I2C2 - config BSP_I2C2_SCL_PIN - int "i2c2 scl pin number" - range 1 176 - default 47 - config BSP_I2C2_SDA_PIN - int "I2C2 sda pin number" - range 1 176 - default 48 - endif - - menuconfig BSP_USING_I2C3 - bool "Enable I2C3 BUS (software simulation)" - default n - select RT_USING_I2CS - select RT_USING_I2C_BITOPS - select RT_USING_PIN - if BSP_USING_I2C3 - config BSP_I2C3_SCL_PIN - int "i2c3 scl pin number" - range 1 176 - default 92 - config BSP_I2C3_SDA_PIN - int "I2C3 sda pin number" - range 1 176 - default 93 + menuconfig BSP_USING_I2C4 + bool "Enable I2C4 BUS (AHT10)" + default n + if BSP_USING_I2C4 + comment "Notice: PC1 --> 33; PD6 --> 54" + config BSP_I2C4_SCL_PIN + int "i2c4 scl pin number" + range 1 176 + default 54 + config BSP_I2C4_SDA_PIN + int "I2C4 sda pin number" + range 1 176 + default 33 + endif endif menuconfig BSP_USING_TIM diff --git a/bsp/stm32/stm32l475-atk-pandora/board/SConscript b/bsp/stm32/stm32l475-atk-pandora/board/SConscript index fb51c3cc0a..a525708b65 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/SConscript +++ b/bsp/stm32/stm32l475-atk-pandora/board/SConscript @@ -18,6 +18,9 @@ if GetDepend(['BSP_USING_QSPI_FLASH']): if GetDepend(['BSP_USING_SDCARD']): src += Glob('ports/sdcard_port.c') +if GetDepend(['BSP_USING_ICM20608']) or GetDepend(['BSP_USING_AHT10']): + src += Glob('ports/sensor_port.c') + path = [cwd] path += [cwd + '/CubeMX_Config/Inc'] path += [cwd + '/ports'] diff --git a/bsp/stm32/stm32l475-atk-pandora/board/board.c b/bsp/stm32/stm32l475-atk-pandora/board/board.c index 3ec895bb7d..b0cec153e7 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/board.c +++ b/bsp/stm32/stm32l475-atk-pandora/board/board.c @@ -10,55 +10,222 @@ * Change Logs: * Date Author Notes * 2009-01-05 Bernard first implementation + * 2019-05-09 Zero-Free Adding multiple configurations for system clock frequency */ #include +#include void SystemClock_Config(void) { - RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - /**Initializes the CPU, AHB and APB busses clocks - */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSEState = RCC_HSE_ON; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = 1; - RCC_OscInitStruct.PLL.PLLN = 20; - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7; - RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; - RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) - { - Error_Handler(); - } - /**Initializes the CPU, AHB and APB busses clocks - */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK - |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + /**Initializes the CPU, AHB and APB busses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 1; + RCC_OscInitStruct.PLL.PLLN = 20; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7; + RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; + RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + /**Initializes the CPU, AHB and APB busses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) - { - Error_Handler(); - } - PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1|RCC_PERIPHCLK_USART2; - PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2; - PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) - { - Error_Handler(); - } - /**Configure the main internal regulator output voltage - */ - if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) - { - Error_Handler(); - } + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) + { + Error_Handler(); + } + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2; + PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2; + PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + /**Configure the main internal regulator output voltage + */ + if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) + { + Error_Handler(); + } } + +#ifdef RT_USING_PM + +void SystemClock_MSI_ON(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + /* Initializes the CPU, AHB and APB busses clocks */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.MSIState = RCC_MSI_ON; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + RT_ASSERT(0); + } + + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) + { + Error_Handler(); + } +} + +void SystemClock_MSI_OFF(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.HSIState = RCC_MSI_OFF; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; /* No update on PLL */ + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } +} + +void SystemClock_80M(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_ClkInitTypeDef RCC_ClkInitStruct; + + /**Initializes the CPU, AHB and APB busses clocks */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 1; + RCC_OscInitStruct.PLL.PLLN = 20; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7; + RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; + RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /**Initializes the CPU, AHB and APB busses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) + { + Error_Handler(); + } +} + +void SystemClock_24M(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_ClkInitTypeDef RCC_ClkInitStruct; + + /** Initializes the CPU, AHB and APB busses clocks */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 1; + RCC_OscInitStruct.PLL.PLLN = 12; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7; + RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; + RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV4; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + /** Initializes the CPU, AHB and APB busses clocks */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) + { + Error_Handler(); + } +} + +void SystemClock_2M(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + + /* MSI is enabled after System reset, update MSI to 2Mhz (RCC_MSIRANGE_5) */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.MSIState = RCC_MSI_ON; + RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_5; + RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + /* Initialization Error */ + Error_Handler(); + } + + /* Select MSI as system clock source and configure the HCLK, PCLK1 and PCLK2 + clocks dividers */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) + { + /* Initialization Error */ + Error_Handler(); + } +} + +/** + * @brief Configures system clock after wake-up from STOP: enable HSI, PLL + * and select PLL as system clock source. + * @param None + * @retval None + */ +void SystemClock_ReConfig(uint8_t mode) +{ + SystemClock_MSI_ON(); + + switch (mode) + { + case PM_RUN_MODE_HIGH_SPEED: + case PM_RUN_MODE_NORMAL_SPEED: + SystemClock_80M(); + break; + case PM_RUN_MODE_MEDIUM_SPEED: + SystemClock_24M(); + break; + case PM_RUN_MODE_LOW_SPEED: + SystemClock_2M(); + break; + default: + break; + } + + // SystemClock_MSI_OFF(); +} + +#endif diff --git a/bsp/stm32/stm32l475-atk-pandora/board/board.h b/bsp/stm32/stm32l475-atk-pandora/board/board.h index 54139616c1..83886f429d 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/board.h +++ b/bsp/stm32/stm32l475-atk-pandora/board/board.h @@ -32,6 +32,12 @@ extern "C" { #define HEAP_END STM32_SRAM1_END void SystemClock_Config(void); +void SystemClock_MSI_ON(void); +void SystemClock_MSI_OFF(void); +void SystemClock_80M(void); +void SystemClock_24M(void); +void SystemClock_2M(void); +void SystemClock_ReConfig(uint8_t mode); #ifdef __cplusplus } diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_qspi_flash.c b/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_qspi_flash.c index 36ecb754e9..aef2226239 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_qspi_flash.c +++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_qspi_flash.c @@ -74,4 +74,37 @@ static int rt_hw_qspi_flash_with_sfud_init(void) } INIT_COMPONENT_EXPORT(rt_hw_qspi_flash_with_sfud_init); -#endif/* BSP_USING_QSPI_FLASH */ +#if defined(RT_USING_DFS_ELMFAT) && !defined(BSP_USING_SDCARD) +#include + +#define BLK_DEV_NAME "W25Q128" + +int mnt_init(void) +{ + rt_thread_delay(RT_TICK_PER_SECOND); + + if (dfs_mount(BLK_DEV_NAME, "/", "elm", 0, 0) == 0) + { + rt_kprintf("file system initialization done!\n"); + } + else + { + if(dfs_mkfs("elm", BLK_DEV_NAME) == 0) + { + if (dfs_mount(BLK_DEV_NAME, "/", "elm", 0, 0) == 0) + { + rt_kprintf("file system initialization done!\n"); + } + else + { + rt_kprintf("file system initialization failed!\n"); + } + } + } + + return 0; +} +INIT_ENV_EXPORT(mnt_init); + +#endif /* defined(RT_USING_DFS_ELMFAT) && !defined(BSP_USING_SDCARD) */ +#endif /* BSP_USING_QSPI_FLASH */ diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/sensor_port.c b/bsp/stm32/stm32l475-atk-pandora/board/ports/sensor_port.c new file mode 100644 index 0000000000..d253cc179e --- /dev/null +++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/sensor_port.c @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-05-08 flaybreak add sensor port file + */ + +#include + +#ifdef BSP_USING_ICM20608 +#include "sensor_inven_mpu6xxx.h" + +int sensor_init(void) +{ + struct rt_sensor_config cfg; + + cfg.intf.type = RT_SENSOR_INTF_I2C; + cfg.intf.dev_name = "i2c3"; + cfg.intf.user_data = (void *)MPU6XXX_ADDR_DEFAULT; + cfg.irq_pin.pin = RT_PIN_NONE; + + rt_hw_mpu6xxx_init("icm", &cfg); + + return 0; +} +INIT_ENV_EXPORT(sensor_init); + +#endif + +#ifdef BSP_USING_AHT10 +#include "sensor_asair_aht10.h" + +#define AHT10_I2C_BUS "i2c4" + +int rt_hw_aht10_port(void) +{ + struct rt_sensor_config cfg; + + cfg.intf.dev_name = AHT10_I2C_BUS; + cfg.intf.user_data = (void *)AHT10_I2C_ADDR; + + rt_hw_aht10_init("aht10", &cfg); + + return RT_EOK; +} +INIT_ENV_EXPORT(rt_hw_aht10_port); +#endif diff --git a/bsp/stm32/stm32l476-st-nucleo/.config b/bsp/stm32/stm32l476-st-nucleo/.config index 0731ce4782..460cc52d06 100644 --- a/bsp/stm32/stm32l476-st-nucleo/.config +++ b/bsp/stm32/stm32l476-st-nucleo/.config @@ -7,6 +7,7 @@ # RT-Thread Kernel # CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set # CONFIG_RT_USING_SMP is not set CONFIG_RT_ALIGN_SIZE=4 # CONFIG_RT_THREAD_PRIORITY_8 is not set @@ -18,7 +19,7 @@ CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDEL_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=256 +CONFIG_IDLE_THREAD_STACK_SIZE=1024 # CONFIG_RT_USING_TIMER_SOFT is not set CONFIG_RT_DEBUG=y CONFIG_RT_DEBUG_COLOR=y @@ -111,6 +112,7 @@ CONFIG_FINSH_ARG_MAX=10 # CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set CONFIG_RT_USING_SERIAL=y CONFIG_RT_SERIAL_USING_DMA=y CONFIG_RT_SERIAL_RB_BUFSZ=64 @@ -124,13 +126,15 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set # CONFIG_RT_USING_MTD is not set -# CONFIG_RT_USING_PM is not set +CONFIG_RT_USING_PM=y CONFIG_RT_USING_RTC=y +# CONFIG_RT_USING_ALARM is not set # CONFIG_RT_USING_SOFT_RTC is not set # CONFIG_RT_USING_SDIO is not set # CONFIG_RT_USING_SPI is not set # CONFIG_RT_USING_WDT is not set # CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set # # Using WiFi @@ -158,6 +162,11 @@ CONFIG_RT_USING_LIBC=y # # CONFIG_RT_USING_SAL is not set +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + # # light weight TCP/IP stack # @@ -181,16 +190,9 @@ CONFIG_RT_USING_LIBC=y # # Utilities # -# CONFIG_RT_USING_LOGTRACE is not set # CONFIG_RT_USING_RYM is not set # CONFIG_RT_USING_ULOG is not set # CONFIG_RT_USING_UTEST is not set - -# -# ARM CMSIS -# -# CONFIG_RT_USING_CMSIS_OS is not set -# CONFIG_RT_USING_RTT_CMSIS is not set # CONFIG_RT_USING_LWP is not set # @@ -202,10 +204,12 @@ CONFIG_RT_USING_LIBC=y # # CONFIG_PKG_USING_PAHOMQTT is not set # CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set # CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set # CONFIG_PKG_USING_LJSON is not set # CONFIG_PKG_USING_EZXML is not set # CONFIG_PKG_USING_NANOPB is not set @@ -223,6 +227,7 @@ CONFIG_RT_USING_LIBC=y # Wiced WiFi # # CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set @@ -236,6 +241,9 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_GAGENT_CLOUD is not set # CONFIG_PKG_USING_ALI_IOTKIT is not set # CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOTKIT is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set # # security packages @@ -256,6 +264,7 @@ CONFIG_RT_USING_LIBC=y # # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set # # tools packages @@ -267,6 +276,7 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_RDB is not set # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ADBD is not set # # system packages @@ -283,10 +293,13 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_LITTLEVGL2RTT is not set # CONFIG_PKG_USING_CMSIS is not set # CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_THREAD_POOL is not set # # peripheral libraries and drivers # +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_SHT2X is not set # CONFIG_PKG_USING_AHT10 is not set @@ -294,6 +307,16 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ICM20608 is not set # CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AT24CXX is not set # # miscellaneous packages @@ -308,10 +331,7 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set - -# -# sample package -# +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set # # samples: kernel and components samples @@ -320,11 +340,9 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set # CONFIG_PKG_USING_NETWORK_SAMPLES is not set # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set - -# -# example package: hello -# # CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_NNOM is not set CONFIG_SOC_FAMILY_STM32=y CONFIG_SOC_SERIES_STM32L4=y diff --git a/bsp/stm32/stm32l476-st-nucleo/board/CubeMX_Config/Inc/stm32l4xx_hal_conf.h b/bsp/stm32/stm32l476-st-nucleo/board/CubeMX_Config/Inc/stm32l4xx_hal_conf.h index b663dfd264..9cf0bbaca2 100644 --- a/bsp/stm32/stm32l476-st-nucleo/board/CubeMX_Config/Inc/stm32l4xx_hal_conf.h +++ b/bsp/stm32/stm32l476-st-nucleo/board/CubeMX_Config/Inc/stm32l4xx_hal_conf.h @@ -69,7 +69,7 @@ /*#define HAL_IWDG_MODULE_ENABLED */ /*#define HAL_LTDC_MODULE_ENABLED */ /*#define HAL_LCD_MODULE_ENABLED */ -/*#define HAL_LPTIM_MODULE_ENABLED */ +#define HAL_LPTIM_MODULE_ENABLED /*#define HAL_NAND_MODULE_ENABLED */ /*#define HAL_NOR_MODULE_ENABLED */ /*#define HAL_OPAMP_MODULE_ENABLED */ diff --git a/bsp/stm32/stm32l476-st-nucleo/board/board.c b/bsp/stm32/stm32l476-st-nucleo/board/board.c index b4fcfe0a84..88600d4b4f 100644 --- a/bsp/stm32/stm32l476-st-nucleo/board/board.c +++ b/bsp/stm32/stm32l476-st-nucleo/board/board.c @@ -5,62 +5,237 @@ * * Change Logs: * Date Author Notes - * 2019-02-05 gw first version + * 2019-02-05 gw first version + * 2019-05-05 Zero-Free Adding multiple configurations for system clock frequency */ #include void SystemClock_Config(void) { - RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; #ifdef BSP_USING_ONCHIP_RTC - /**Configure LSE Drive Capability - */ - HAL_PWR_EnableBkUpAccess(); - __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); -#endif - /**Initializes the CPU, AHB and APB busses clocks - */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; - RCC_OscInitStruct.HSIState = RCC_HSI_ON; - RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; - RCC_OscInitStruct.PLL.PLLM = 1; - RCC_OscInitStruct.PLL.PLLN = 10; - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7; - RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; - RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) - { - Error_Handler(); - } - /**Initializes the CPU, AHB and APB busses clocks - */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK - |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + /**Configure LSE Drive Capability + */ + HAL_PWR_EnableBkUpAccess(); + __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); +#endif + /**Initializes the CPU, AHB and APB busses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLM = 1; + RCC_OscInitStruct.PLL.PLLN = 10; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7; + RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; + RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + /**Initializes the CPU, AHB and APB busses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) - { - Error_Handler(); - } - PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART2; - PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) - { - Error_Handler(); - } - /**Configure the main internal regulator output voltage - */ - if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) - { - Error_Handler(); - } + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) + { + Error_Handler(); + } + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART2; + PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + /**Configure the main internal regulator output voltage + */ + if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) + { + Error_Handler(); + } } + +#ifdef RT_USING_PM + +void SystemClock_MSI_ON(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + /* Initializes the CPU, AHB and APB busses clocks */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.MSIState = RCC_MSI_ON; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + RT_ASSERT(0); + } + + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) + { + Error_Handler(); + } +} + +void SystemClock_MSI_OFF(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.HSIState = RCC_MSI_OFF; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; /* No update on PLL */ + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } +} + +void SystemClock_80M(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_ClkInitTypeDef RCC_ClkInitStruct; + + /**Initializes the CPU, AHB and APB busses clocks */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = 16; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLM = 1; + RCC_OscInitStruct.PLL.PLLN = 10; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7; + RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; + RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /**Initializes the CPU, AHB and APB busses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) + { + Error_Handler(); + } +} + +void SystemClock_24M(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_PeriphCLKInitTypeDef PeriphClkInit; + + /** Initializes the CPU, AHB and APB busses clocks */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = 16; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLM = 1; + RCC_OscInitStruct.PLL.PLLN = 12; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7; + RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; + RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV8; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + /** Initializes the CPU, AHB and APB busses clocks */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) + { + Error_Handler(); + } + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART2; + PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } +} + +void SystemClock_2M(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + + /* MSI is enabled after System reset, update MSI to 2Mhz (RCC_MSIRANGE_5) */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.MSIState = RCC_MSI_ON; + RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_5; + RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + /* Initialization Error */ + Error_Handler(); + } + + /* Select MSI as system clock source and configure the HCLK, PCLK1 and PCLK2 + clocks dividers */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) + { + /* Initialization Error */ + Error_Handler(); + } +} + +/** + * @brief Configures system clock after wake-up from STOP: enable HSI, PLL + * and select PLL as system clock source. + * @param None + * @retval None + */ +void SystemClock_ReConfig(uint8_t mode) +{ + SystemClock_MSI_ON(); + + switch (mode) + { + case PM_RUN_MODE_HIGH_SPEED: + case PM_RUN_MODE_NORMAL_SPEED: + SystemClock_80M(); + break; + case PM_RUN_MODE_MEDIUM_SPEED: + SystemClock_24M(); + break; + case PM_RUN_MODE_LOW_SPEED: + SystemClock_2M(); + break; + default: + break; + } + + // SystemClock_MSI_OFF(); +} + +#endif diff --git a/bsp/stm32/stm32l476-st-nucleo/board/board.h b/bsp/stm32/stm32l476-st-nucleo/board/board.h index f5e2db4e1b..b59fe1b3b6 100644 --- a/bsp/stm32/stm32l476-st-nucleo/board/board.h +++ b/bsp/stm32/stm32l476-st-nucleo/board/board.h @@ -33,6 +33,17 @@ extern "C" { void SystemClock_Config(void); +#ifdef RT_USING_PM + +void SystemClock_MSI_ON(void); +void SystemClock_MSI_OFF(void); +void SystemClock_80M(void); +void SystemClock_24M(void); +void SystemClock_2M(void); +void SystemClock_ReConfig(uint8_t mode); + +#endif + #ifdef __cplusplus } #endif diff --git a/bsp/stm32/stm32l476-st-nucleo/project.uvprojx b/bsp/stm32/stm32l476-st-nucleo/project.uvprojx index c4775ff651..bd3252b612 100644 --- a/bsp/stm32/stm32l476-st-nucleo/project.uvprojx +++ b/bsp/stm32/stm32l476-st-nucleo/project.uvprojx @@ -369,7 +369,7 @@ .\board\linker_scripts\link.sct - --keep *.o(.rti_fn.*) --keep *.o(FSymTab) + @@ -533,9 +533,16 @@ - drv_soft_i2c.c + drv_pm.c 1 - ..\libraries\HAL_Drivers\drv_soft_i2c.c + ..\libraries\HAL_Drivers\drv_pm.c + + + + + drv_lptim.c + 1 + ..\libraries\HAL_Drivers\drv_lptim.c @@ -586,27 +593,6 @@ DeviceDrivers - - - i2c_core.c - 1 - ..\..\..\components\drivers\i2c\i2c_core.c - - - - - i2c_dev.c - 1 - ..\..\..\components\drivers\i2c\i2c_dev.c - - - - - i2c-bit-ops.c - 1 - ..\..\..\components\drivers\i2c\i2c-bit-ops.c - - pin.c @@ -614,6 +600,13 @@ ..\..\..\components\drivers\misc\pin.c + + + pm.c + 1 + ..\..\..\components\drivers\pm\pm.c + + rtc.c @@ -875,13 +868,6 @@ ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rng.c - - - stm32l4xx_hal_sram.c - 1 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_sram.c - - stm32l4xx_hal_gpio.c @@ -917,20 +903,6 @@ ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_usart_ex.c - - - stm32l4xx_hal_i2c.c - 1 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c.c - - - - - stm32l4xx_hal_i2c_ex.c - 1 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c_ex.c - - stm32l4xx_hal_rtc.c @@ -945,6 +917,13 @@ ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rtc_ex.c + + + stm32l4xx_hal_lptim.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_lptim.c + + diff --git a/bsp/stm32/stm32l476-st-nucleo/rtconfig.h b/bsp/stm32/stm32l476-st-nucleo/rtconfig.h index afeaf369c0..380c3c3280 100644 --- a/bsp/stm32/stm32l476-st-nucleo/rtconfig.h +++ b/bsp/stm32/stm32l476-st-nucleo/rtconfig.h @@ -15,7 +15,7 @@ #define RT_USING_HOOK #define RT_USING_IDLE_HOOK #define RT_IDEL_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 256 +#define IDLE_THREAD_STACK_SIZE 1024 #define RT_DEBUG #define RT_DEBUG_COLOR @@ -79,7 +79,10 @@ #define RT_PIPE_BUFSZ 512 #define RT_USING_SERIAL #define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 #define RT_USING_PIN +#define RT_USING_PM +#define RT_USING_RTC /* Using WiFi */ @@ -96,6 +99,9 @@ /* Socket abstraction layer */ +/* Network interface device */ + + /* light weight TCP/IP stack */ @@ -111,9 +117,6 @@ /* Utilities */ -/* ARM CMSIS */ - - /* RT-Thread online packages */ /* IoT - internet of things */ @@ -151,13 +154,8 @@ /* miscellaneous packages */ -/* sample package */ - /* samples: kernel and components samples */ - -/* example package: hello */ - #define SOC_FAMILY_STM32 #define SOC_SERIES_STM32L4 diff --git a/bsp/stm32/stm32l496-ali-developer/board/board.h b/bsp/stm32/stm32l496-ali-developer/board/board.h index bf1b6d2831..78cc07314b 100644 --- a/bsp/stm32/stm32l496-ali-developer/board/board.h +++ b/bsp/stm32/stm32l496-ali-developer/board/board.h @@ -39,7 +39,7 @@ extern "C" { #define STM32_FLASH_SIZE (1024 * 1024) #define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE)) -#ifdef __CC_ARM +#if defined(__CC_ARM) || defined(__CLANG_ARM) extern int Image$$RW_IRAM1$$ZI$$Limit; #define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) #elif __ICCARM__ diff --git a/bsp/stm32/stm32l4r9-st-eval/.config b/bsp/stm32/stm32l4r9-st-eval/.config index be436fe5ab..35f6c41bf7 100644 --- a/bsp/stm32/stm32l4r9-st-eval/.config +++ b/bsp/stm32/stm32l4r9-st-eval/.config @@ -48,11 +48,11 @@ CONFIG_RT_USING_MESSAGEQUEUE=y # Memory Management # CONFIG_RT_USING_MEMPOOL=y -# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_MEMHEAP=y # CONFIG_RT_USING_NOHEAP is not set -CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SMALL_MEM is not set # CONFIG_RT_USING_SLAB is not set -# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_MEMHEAP_AS_HEAP=y CONFIG_RT_USING_HEAP=y # @@ -119,7 +119,8 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set -# CONFIG_RT_USING_I2C is not set +CONFIG_RT_USING_I2C=y +CONFIG_RT_USING_I2C_BITOPS=y CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_PWM is not set @@ -160,6 +161,11 @@ CONFIG_RT_USING_PIN=y # # CONFIG_RT_USING_SAL is not set +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + # # light weight TCP/IP stack # @@ -193,32 +199,20 @@ CONFIG_RT_USING_PIN=y # RT-Thread online packages # -# -# system packages -# - -# -# RT-Thread GUI Engine -# -# CONFIG_PKG_USING_GUIENGINE is not set -# CONFIG_PKG_USING_PERSIMMON is not set -# CONFIG_PKG_USING_LWEXT4 is not set -# CONFIG_PKG_USING_PARTITION is not set -# CONFIG_PKG_USING_SQLITE is not set -# CONFIG_PKG_USING_RTI is not set - # # IoT - internet of things # # CONFIG_PKG_USING_PAHOMQTT is not set # CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set # CONFIG_PKG_USING_LJSON is not set # CONFIG_PKG_USING_EZXML is not set # CONFIG_PKG_USING_NANOPB is not set -# CONFIG_PKG_USING_GAGENT_CLOUD is not set # # Wi-Fi @@ -233,9 +227,23 @@ CONFIG_RT_USING_PIN=y # Wiced WiFi # # CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOTKIT is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set # # security packages @@ -247,6 +255,7 @@ CONFIG_RT_USING_PIN=y # # language packages # +# CONFIG_PKG_USING_LUA is not set # CONFIG_PKG_USING_JERRYSCRIPT is not set # CONFIG_PKG_USING_MICROPYTHON is not set @@ -254,27 +263,86 @@ CONFIG_RT_USING_PIN=y # multimedia packages # # CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set # # tools packages # # CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set # CONFIG_PKG_USING_EASYLOGGER is not set # CONFIG_PKG_USING_SYSTEMVIEW is not set -# CONFIG_PKG_USING_IPERF is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ADBD is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_THREAD_POOL is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AT24CXX is not set # # miscellaneous packages # +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set # CONFIG_PKG_USING_FASTLZ is not set # CONFIG_PKG_USING_MINILZO is not set # CONFIG_PKG_USING_QUICKLZ is not set # CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set # -# example package: hello +# samples: kernel and components samples # +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set # CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_NNOM is not set CONFIG_SOC_FAMILY_STM32=y CONFIG_SOC_SERIES_STM32L4=y @@ -286,6 +354,13 @@ CONFIG_SOC_STM32L4R9AI=y # # Onboard Peripheral Drivers # +CONFIG_BSP_USING_STLINK_TO_USART=y +# CONFIG_BSP_USING_DSI is not set + +# +# Enable Touch +# +# CONFIG_BSP_USING_TOUCH is not set # # On-chip Peripheral Drivers @@ -293,6 +368,10 @@ CONFIG_SOC_STM32L4R9AI=y CONFIG_BSP_USING_GPIO=y CONFIG_BSP_USING_UART=y CONFIG_BSP_USING_UART3=y +# CONFIG_BSP_USING_SRAM is not set +# CONFIG_BSP_USING_I2C1 is not set +# CONFIG_BSP_USING_GFXMMU is not set +# CONFIG_BSP_USING_FMC is not set # # Board extended module Drivers diff --git a/bsp/stm32/stm32l4r9-st-eval/README.md b/bsp/stm32/stm32l4r9-st-eval/README.md index 4999a9a25b..e91aced25c 100644 --- a/bsp/stm32/stm32l4r9-st-eval/README.md +++ b/bsp/stm32/stm32l4r9-st-eval/README.md @@ -2,7 +2,7 @@ ## 简介 -STM32L4R9I-EVAL 开发板提供的 BSP (板级支持包) 说明。 +由 JHB 为 STM32L4R9I-EVAL 开发板提供的 BSP (板级支持包) 说明。 主要内容如下： @@ -34,12 +34,19 @@ STM32L4R9I-EVAL 开发板提供的 BSP (板级支持包) 说明。 本 BSP 目前对外设的支持情况如下： -| **板载外设** | **支持情况** | **备注** | -| :----------------- | :----------: | :------------------------------------- | -| 板载 ST-LINK 转串口 | 支持 | PB10 PB11 USART3 | | -| **片上外设** | **支持情况** | **备注** | -| GPIO | 支持 | PA0, PA1... PK15 ---> PIN: 0, 1...176 | -| UART | 支持 | USART3 | +| **板载外设** | **支持情况** | **备注** | +| :----------------- | :----------: | :-----------------------------------------| +| 板载 ST-LINK 转串口 | 支持 | PB10 PB11 USART3 | +| LCD | 支持 | DSI mode round lcd | +| TOUCH | 支持 | touch for round lcd | +| SRAM | 支持 | | +| **片上外设** | **支持情况** | **备注** | +| GPIO | 支持 | | +| UART | 支持 | USART3 | + + + + ## 使用说明 @@ -99,12 +106,12 @@ msh > - 调试串口为串口3 映射到PB10 PB11 -- RAM 分为三部分 +- stm32L4R9 共有三块内部RAM区域 具体使用情况入如下 ``` RAM1 (rw) : ORIGIN = 0x20000000, LENGTH = 192k /* 192K sram 用于程序定义全局变量 静态变量存放*/ - RAM2 (rw) : ORIGIN = 0x10000000, LENGTH = 64k /* 64K sram 用于程序定义全局变量 静态变量存放 */ - RAM3 (rw) : ORIGIN = 0x20040000, LENGTH = 384k /* 384K sram 用于heap*/ + RAM2 (rw) : ORIGIN = 0x10000000, LENGTH = 64k /* 64K sram 用于程序定义全局变量 静态变量存放 */ + RAM3 (rw) : ORIGIN = 0x20040000, LENGTH = 384k /* 384K sram 用于heap空间*/ ``` diff --git a/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/.mxproject b/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/.mxproject index 9461890e7b..c20f846330 100644 --- a/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/.mxproject +++ b/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/.mxproject @@ -1,13 +1,13 @@ [PreviousGenFiles] -HeaderPath=E:/rt-thread/bsp/stm32/stm32l4xx/board/CubeMX_Config/Inc -HeaderFiles=stm32l4xx_it.h;stm32l4xx_hal_conf.h;main.h; -SourcePath=E:/rt-thread/bsp/stm32/stm32l4xx/board/CubeMX_Config/Src +HeaderPath=E:/0423/rt-thread/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/Inc +HeaderFiles=stm32l4xx_it.h;stm32l4xx_hal_conf.h;main.h;gfxmmu_lut.h; +SourcePath=E:/0423/rt-thread/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/Src SourceFiles=stm32l4xx_it.c;stm32l4xx_hal_msp.c;main.c; [PreviousLibFiles] -LibFiles=Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h;Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h;Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4r9xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;Drivers/CMSIS/Include/arm_common_tables.h;Drivers/CMSIS/Include/arm_const_structs.h;Drivers/CMSIS/Include/arm_math.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armcc_V6.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cmFunc.h;Drivers/CMSIS/Include/core_cmInstr.h;Drivers/CMSIS/Include/core_cmSimd.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h; +LibFiles=Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma2d.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dsi.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_fmc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sram.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gfxmmu.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_ltdc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_ltdc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h;Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma2d.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dsi.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_fmc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sram.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gfxmmu.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ltdc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ltdc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma2d.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dsi.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_fmc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sram.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gfxmmu.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_ltdc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_ltdc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h;Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4r9xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;Drivers/CMSIS/Include/arm_common_tables.h;Drivers/CMSIS/Include/arm_const_structs.h;Drivers/CMSIS/Include/arm_math.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armcc_V6.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cmFunc.h;Drivers/CMSIS/Include/core_cmInstr.h;Drivers/CMSIS/Include/core_cmSimd.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h; [PreviousUsedKeilFiles] -SourceFiles=..\Src\main.c;..\Src\stm32l4xx_it.c;..\Src\stm32l4xx_hal_msp.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;../\Src/system_stm32l4xx.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;../\Src/system_stm32l4xx.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;null; +SourceFiles=..\Src\main.c;..\Src\stm32l4xx_it.c;..\Src\stm32l4xx_hal_msp.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma2d.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dsi.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_fmc.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sram.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gfxmmu.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ltdc.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ltdc_ex.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;../\Src/system_stm32l4xx.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma2d.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dsi.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_fmc.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sram.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gfxmmu.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ltdc.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ltdc_ex.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;../\Src/system_stm32l4xx.c;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;E:/0423/rt-thread/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config//MDK-ARM/startup_stm32l4r9xx.s; HeaderPath=C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers\STM32L4xx_HAL_Driver\Inc;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers\STM32L4xx_HAL_Driver\Inc\Legacy;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers\CMSIS\Device\ST\STM32L4xx\Include;C:\Users\RT-Thread\STM32Cube\Repository\STM32Cube_FW_L4_V1.13.0\Drivers\CMSIS\Include;..\Inc; diff --git a/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/CubeMX_Config.ioc index 7fdbf9d920..1ded20f423 100644 --- a/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/CubeMX_Config.ioc @@ -1,22 +1,91 @@ #MicroXplorer Configuration settings - do not modify +DSIHOST_CKN.Mode=DSIHost_Standalone +DSIHOST_CKN.Signal=DSIHOST_CKN +DSIHOST_CKP.Mode=DSIHost_Standalone +DSIHOST_CKP.Signal=DSIHOST_CKP +DSIHOST_D0N.Mode=DSIHost_Standalone +DSIHOST_D0N.Signal=DSIHOST_D0N +DSIHOST_D0P.Mode=DSIHost_Standalone +DSIHOST_D0P.Signal=DSIHOST_D0P +DSIHOST_D1N.Mode=DSIHost_Standalone +DSIHOST_D1N.Signal=DSIHOST_D1N +DSIHOST_D1P.Mode=DSIHost_Standalone +DSIHOST_D1P.Signal=DSIHOST_D1P File.Version=6 KeepUserPlacement=false Mcu.Family=STM32L4 -Mcu.IP0=LTDC -Mcu.IP1=NVIC -Mcu.IP2=RCC -Mcu.IP3=SYS -Mcu.IP4=USART3 -Mcu.IPNb=5 +Mcu.IP0=DMA2D +Mcu.IP1=DSIHOST +Mcu.IP2=FMC +Mcu.IP3=GFXMMU +Mcu.IP4=LTDC +Mcu.IP5=NVIC +Mcu.IP6=RCC +Mcu.IP7=SYS +Mcu.IP8=USART3 +Mcu.IPNb=9 Mcu.Name=STM32L4R9A(G-I)Ix Mcu.Package=UFBGA169 -Mcu.Pin0=PH0-OSC_IN (PH0) -Mcu.Pin1=PB11 -Mcu.Pin2=PH1-OSC_OUT (PH1) -Mcu.Pin3=PB10 -Mcu.Pin4=VP_LTDC_DSIMode -Mcu.Pin5=VP_SYS_VS_Systick -Mcu.PinsNb=6 +Mcu.Pin0=PE0 +Mcu.Pin1=PE1 +Mcu.Pin10=PF2 +Mcu.Pin11=PF1 +Mcu.Pin12=PF0 +Mcu.Pin13=PD7 +Mcu.Pin14=PC15-OSC32_OUT (PC15) +Mcu.Pin15=PF3 +Mcu.Pin16=PF4 +Mcu.Pin17=PF5 +Mcu.Pin18=PG4 +Mcu.Pin19=PG3 +Mcu.Pin2=PD0 +Mcu.Pin20=PG5 +Mcu.Pin21=PH0-OSC_IN (PH0) +Mcu.Pin22=PG1 +Mcu.Pin23=PE10 +Mcu.Pin24=PB11 +Mcu.Pin25=PD13 +Mcu.Pin26=PG2 +Mcu.Pin27=PD15 +Mcu.Pin28=PD14 +Mcu.Pin29=PH1-OSC_OUT (PH1) +Mcu.Pin3=PD4 +Mcu.Pin30=PG0 +Mcu.Pin31=PE9 +Mcu.Pin32=PE15 +Mcu.Pin33=PD12 +Mcu.Pin34=PD11 +Mcu.Pin35=PD10 +Mcu.Pin36=DSIHOST_D1P +Mcu.Pin37=DSIHOST_D1N +Mcu.Pin38=PF15 +Mcu.Pin39=PE8 +Mcu.Pin4=PD1 +Mcu.Pin40=PE14 +Mcu.Pin41=PD9 +Mcu.Pin42=PD8 +Mcu.Pin43=DSIHOST_CKP +Mcu.Pin44=DSIHOST_CKN +Mcu.Pin45=PF14 +Mcu.Pin46=PE7 +Mcu.Pin47=PE13 +Mcu.Pin48=DSIHOST_D0P +Mcu.Pin49=DSIHOST_D0N +Mcu.Pin5=PE4 +Mcu.Pin50=PF13 +Mcu.Pin51=PE12 +Mcu.Pin52=PF12 +Mcu.Pin53=PE11 +Mcu.Pin54=PB10 +Mcu.Pin55=VP_DMA2D_VS_DMA2D +Mcu.Pin56=VP_GFXMMU_VS_GFXMMU +Mcu.Pin57=VP_LTDC_DSIMode +Mcu.Pin58=VP_SYS_VS_Systick +Mcu.Pin6=PE3 +Mcu.Pin7=PD5 +Mcu.Pin8=PE5 +Mcu.Pin9=PC14-OSC32_IN (PC14) +Mcu.PinsNb=59 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32L4R9AIIx @@ -38,6 +107,10 @@ PB10.Signal=USART3_TX PB11.Locked=true PB11.Mode=Asynchronous PB11.Signal=USART3_RX +PC14-OSC32_IN\ (PC14).Mode=LSE-External-Oscillator +PC14-OSC32_IN\ (PC14).Signal=RCC_OSC32_IN +PC15-OSC32_OUT\ (PC15).Mode=LSE-External-Oscillator +PC15-OSC32_OUT\ (PC15).Signal=RCC_OSC32_OUT PCC.Checker=true PCC.Line=STM32L4R9/S9 PCC.MCU=STM32L4R9A(G-I)Ix @@ -46,6 +119,52 @@ PCC.Seq0=0 PCC.Series=STM32L4 PCC.Temperature=25 PCC.Vdd=null +PD0.Signal=FMC_D2_DA2 +PD1.Signal=FMC_D3_DA3 +PD10.Signal=FMC_D15_DA15 +PD11.Signal=FMC_A16_CLE +PD12.Signal=FMC_A17_ALE +PD13.Signal=FMC_A18 +PD14.Signal=FMC_D0_DA0 +PD15.Signal=FMC_D1_DA1 +PD4.Signal=FMC_NOE +PD5.Signal=FMC_NWE +PD7.Mode=NorPsramChipSelect1_1 +PD7.Signal=FMC_NE1 +PD8.Signal=FMC_D13_DA13 +PD9.Signal=FMC_D14_DA14 +PE0.Locked=true +PE0.Signal=FMC_NBL0 +PE1.Locked=true +PE1.Signal=FMC_NBL1 +PE10.Signal=FMC_D7_DA7 +PE11.Signal=FMC_D8_DA8 +PE12.Signal=FMC_D9_DA9 +PE13.Signal=FMC_D10_DA10 +PE14.Signal=FMC_D11_DA11 +PE15.Signal=FMC_D12_DA12 +PE3.Signal=FMC_A19 +PE4.Signal=FMC_A20 +PE5.Signal=FMC_A21 +PE7.Signal=FMC_D4_DA4 +PE8.Signal=FMC_D5_DA5 +PE9.Signal=FMC_D6_DA6 +PF0.Signal=FMC_A0 +PF1.Signal=FMC_A1 +PF12.Signal=FMC_A6 +PF13.Signal=FMC_A7 +PF14.Signal=FMC_A8 +PF15.Signal=FMC_A9 +PF2.Signal=FMC_A2 +PF3.Signal=FMC_A3 +PF4.Signal=FMC_A4 +PF5.Signal=FMC_A5 +PG0.Signal=FMC_A10 +PG1.Signal=FMC_A11 +PG2.Signal=FMC_A12 +PG3.Signal=FMC_A13 +PG4.Signal=FMC_A14 +PG5.Signal=FMC_A15 PH0-OSC_IN\ (PH0).Mode=HSE-External-Oscillator PH0-OSC_IN\ (PH0).Signal=RCC_OSC_IN PH1-OSC_OUT\ (PH1).Mode=HSE-External-Oscillator @@ -78,7 +197,7 @@ ProjectManager.StackSize=0x400 ProjectManager.TargetToolchain=MDK-ARM V5 ProjectManager.ToolChainLocation= ProjectManager.UnderRoot=false -ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART3_UART_Init-USART3-false-HAL-true,4-MX_LTDC_Init-LTDC-false-HAL-true +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART3_UART_Init-USART3-false-HAL-true,4-MX_LTDC_Init-LTDC-false-HAL-true,5-MX_FMC_Init-FMC-false-HAL-true,6-MX_DMA2D_Init-DMA2D-false-HAL-true,7-MX_DSIHOST_DSI_Init-DSIHOST-false-HAL-true,8-MX_GFXMMU_Init-GFXMMU-false-HAL-true RCC.ADCFreq_Value=64000000 RCC.AHBFreq_Value=120000000 RCC.APB1Freq_Value=120000000 @@ -88,9 +207,9 @@ RCC.APB2TimFreq_Value=120000000 RCC.CRSFreq_Value=48000000 RCC.CortexFreq_Value=120000000 RCC.DFSDMFreq_Value=120000000 -RCC.DSIFreq_Value=40000000 -RCC.DSIRXEscFreq_Value=40000000 -RCC.DSITXEscFreq_Value=10000000 +RCC.DSIFreq_Value=20000000 +RCC.DSIRXEscFreq_Value=20000000 +RCC.DSITXEscFreq_Value=5000000 RCC.FCLKCortexFreq_Value=120000000 RCC.FamilyName=M RCC.HCLKFreq_Value=120000000 @@ -101,20 +220,21 @@ RCC.I2C1Freq_Value=120000000 RCC.I2C2Freq_Value=120000000 RCC.I2C3Freq_Value=120000000 RCC.I2C4Freq_Value=120000000 -RCC.IPParameters=ADCFreq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CRSFreq_Value,CortexFreq_Value,DFSDMFreq_Value,DSIFreq_Value,DSIRXEscFreq_Value,DSITXEscFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,LCDTFTFreq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,MSI_VALUE,OCTOSPIMFreq_Value,PLLDSIFreq_Value,PLLDSIVCOFreq_Value,PLLM1,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PLLSAI1PoutputFreq_Value,PLLSAI1QoutputFreq_Value,PLLSAI1RoutputFreq_Value,PLLSAI2PoutputFreq_Value,PLLSAI2QoutputFreq_Value,PLLSAI2RoutputFreq_Value,PLLSourceVirtual,PWRFreq_Value,RNGFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMCFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,UART5Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USBFreq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAI1OutputFreq_Value,VCOSAI2OutputFreq_Value -RCC.LCDTFTFreq_Value=32000000 +RCC.IPParameters=ADCFreq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CRSFreq_Value,CortexFreq_Value,DFSDMFreq_Value,DSIFreq_Value,DSIRXEscFreq_Value,DSITXEscFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,LCDTFTFreq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSI_VALUE,MCO1PinFreq_Value,MSI_VALUE,OCTOSPIMFreq_Value,PLLDSIFreq_Value,PLLDSIODF,PLLDSIVCOFreq_Value,PLLM1,PLLM3,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PLLSAI1PoutputFreq_Value,PLLSAI1QoutputFreq_Value,PLLSAI1RoutputFreq_Value,PLLSAI2PoutputFreq_Value,PLLSAI2QoutputFreq_Value,PLLSAI2RoutputFreq_Value,PLLSourceVirtual,PWRFreq_Value,RNGFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMCFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,UART5Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USBFreq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAI1OutputFreq_Value,VCOSAI2OutputFreq_Value +RCC.LCDTFTFreq_Value=16000000 RCC.LPTIM1Freq_Value=120000000 RCC.LPTIM2Freq_Value=120000000 RCC.LPUART1Freq_Value=120000000 RCC.LSCOPinFreq_Value=32000 -RCC.LSE_VALUE=32768 RCC.LSI_VALUE=32000 RCC.MCO1PinFreq_Value=120000000 RCC.MSI_VALUE=4000000 RCC.OCTOSPIMFreq_Value=120000000 -RCC.PLLDSIFreq_Value=320000000 +RCC.PLLDSIFreq_Value=160000000 +RCC.PLLDSIODF=DSI_PLL_OUT_DIV2 RCC.PLLDSIVCOFreq_Value=640000000 RCC.PLLM1=2 +RCC.PLLM3=2 RCC.PLLN=30 RCC.PLLPoutputFreq_Value=120000000 RCC.PLLQoutputFreq_Value=120000000 @@ -122,9 +242,9 @@ RCC.PLLRCLKFreq_Value=120000000 RCC.PLLSAI1PoutputFreq_Value=64000000 RCC.PLLSAI1QoutputFreq_Value=64000000 RCC.PLLSAI1RoutputFreq_Value=64000000 -RCC.PLLSAI2PoutputFreq_Value=64000000 -RCC.PLLSAI2QoutputFreq_Value=64000000 -RCC.PLLSAI2RoutputFreq_Value=64000000 +RCC.PLLSAI2PoutputFreq_Value=32000000 +RCC.PLLSAI2QoutputFreq_Value=32000000 +RCC.PLLSAI2RoutputFreq_Value=32000000 RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE RCC.PWRFreq_Value=120000000 RCC.RNGFreq_Value=64000000 @@ -140,13 +260,101 @@ RCC.USART2Freq_Value=120000000 RCC.USART3Freq_Value=120000000 RCC.USBFreq_Value=64000000 RCC.VCOInput2Freq_Value=16000000 -RCC.VCOInput3Freq_Value=16000000 +RCC.VCOInput3Freq_Value=8000000 RCC.VCOInputFreq_Value=8000000 RCC.VCOOutputFreq_Value=240000000 RCC.VCOSAI1OutputFreq_Value=128000000 -RCC.VCOSAI2OutputFreq_Value=128000000 +RCC.VCOSAI2OutputFreq_Value=64000000 +SH.FMC_A0.0=FMC_A0,22b-a1 +SH.FMC_A0.ConfNb=1 +SH.FMC_A1.0=FMC_A1,22b-a1 +SH.FMC_A1.ConfNb=1 +SH.FMC_A10.0=FMC_A10,22b-a1 +SH.FMC_A10.ConfNb=1 +SH.FMC_A11.0=FMC_A11,22b-a1 +SH.FMC_A11.ConfNb=1 +SH.FMC_A12.0=FMC_A12,22b-a1 +SH.FMC_A12.ConfNb=1 +SH.FMC_A13.0=FMC_A13,22b-a1 +SH.FMC_A13.ConfNb=1 +SH.FMC_A14.0=FMC_A14,22b-a1 +SH.FMC_A14.ConfNb=1 +SH.FMC_A15.0=FMC_A15,22b-a1 +SH.FMC_A15.ConfNb=1 +SH.FMC_A16_CLE.0=FMC_A16,22b-a1 +SH.FMC_A16_CLE.ConfNb=1 +SH.FMC_A17_ALE.0=FMC_A17,22b-a1 +SH.FMC_A17_ALE.ConfNb=1 +SH.FMC_A18.0=FMC_A18,22b-a1 +SH.FMC_A18.ConfNb=1 +SH.FMC_A19.0=FMC_A19,22b-a1 +SH.FMC_A19.ConfNb=1 +SH.FMC_A2.0=FMC_A2,22b-a1 +SH.FMC_A2.ConfNb=1 +SH.FMC_A20.0=FMC_A20,22b-a1 +SH.FMC_A20.ConfNb=1 +SH.FMC_A21.0=FMC_A21,22b-a1 +SH.FMC_A21.ConfNb=1 +SH.FMC_A3.0=FMC_A3,22b-a1 +SH.FMC_A3.ConfNb=1 +SH.FMC_A4.0=FMC_A4,22b-a1 +SH.FMC_A4.ConfNb=1 +SH.FMC_A5.0=FMC_A5,22b-a1 +SH.FMC_A5.ConfNb=1 +SH.FMC_A6.0=FMC_A6,22b-a1 +SH.FMC_A6.ConfNb=1 +SH.FMC_A7.0=FMC_A7,22b-a1 +SH.FMC_A7.ConfNb=1 +SH.FMC_A8.0=FMC_A8,22b-a1 +SH.FMC_A8.ConfNb=1 +SH.FMC_A9.0=FMC_A9,22b-a1 +SH.FMC_A9.ConfNb=1 +SH.FMC_D0_DA0.0=FMC_D0,16b-d1 +SH.FMC_D0_DA0.ConfNb=1 +SH.FMC_D10_DA10.0=FMC_D10,16b-d1 +SH.FMC_D10_DA10.ConfNb=1 +SH.FMC_D11_DA11.0=FMC_D11,16b-d1 +SH.FMC_D11_DA11.ConfNb=1 +SH.FMC_D12_DA12.0=FMC_D12,16b-d1 +SH.FMC_D12_DA12.ConfNb=1 +SH.FMC_D13_DA13.0=FMC_D13,16b-d1 +SH.FMC_D13_DA13.ConfNb=1 +SH.FMC_D14_DA14.0=FMC_D14,16b-d1 +SH.FMC_D14_DA14.ConfNb=1 +SH.FMC_D15_DA15.0=FMC_D15,16b-d1 +SH.FMC_D15_DA15.ConfNb=1 +SH.FMC_D1_DA1.0=FMC_D1,16b-d1 +SH.FMC_D1_DA1.ConfNb=1 +SH.FMC_D2_DA2.0=FMC_D2,16b-d1 +SH.FMC_D2_DA2.ConfNb=1 +SH.FMC_D3_DA3.0=FMC_D3,16b-d1 +SH.FMC_D3_DA3.ConfNb=1 +SH.FMC_D4_DA4.0=FMC_D4,16b-d1 +SH.FMC_D4_DA4.ConfNb=1 +SH.FMC_D5_DA5.0=FMC_D5,16b-d1 +SH.FMC_D5_DA5.ConfNb=1 +SH.FMC_D6_DA6.0=FMC_D6,16b-d1 +SH.FMC_D6_DA6.ConfNb=1 +SH.FMC_D7_DA7.0=FMC_D7,16b-d1 +SH.FMC_D7_DA7.ConfNb=1 +SH.FMC_D8_DA8.0=FMC_D8,16b-d1 +SH.FMC_D8_DA8.ConfNb=1 +SH.FMC_D9_DA9.0=FMC_D9,16b-d1 +SH.FMC_D9_DA9.ConfNb=1 +SH.FMC_NBL0.0=FMC_NBL0 +SH.FMC_NBL0.ConfNb=1 +SH.FMC_NBL1.0=FMC_NBL1 +SH.FMC_NBL1.ConfNb=1 +SH.FMC_NOE.0=FMC_NOE,Sram1 +SH.FMC_NOE.ConfNb=1 +SH.FMC_NWE.0=FMC_NWE,Sram1 +SH.FMC_NWE.ConfNb=1 USART3.IPParameters=VirtualMode-Asynchronous USART3.VirtualMode-Asynchronous=VM_ASYNC +VP_DMA2D_VS_DMA2D.Mode=DMA2D_Activate +VP_DMA2D_VS_DMA2D.Signal=DMA2D_VS_DMA2D +VP_GFXMMU_VS_GFXMMU.Mode=GFXMMU_Activate +VP_GFXMMU_VS_GFXMMU.Signal=GFXMMU_VS_GFXMMU VP_LTDC_DSIMode.Mode=RGB888 VP_LTDC_DSIMode.Signal=LTDC_DSIMode VP_SYS_VS_Systick.Mode=SysTick diff --git a/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/Inc/stm32l4xx_hal_conf.h b/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/Inc/stm32l4xx_hal_conf.h index aae861d9b1..9a78d0cd72 100644 --- a/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/Inc/stm32l4xx_hal_conf.h +++ b/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/Inc/stm32l4xx_hal_conf.h @@ -57,17 +57,17 @@ /*#define HAL_CRYP_MODULE_ENABLED */ /*#define HAL_DAC_MODULE_ENABLED */ /*#define HAL_DCMI_MODULE_ENABLED */ -/*#define HAL_DMA2D_MODULE_ENABLED */ +#define HAL_DMA2D_MODULE_ENABLED /*#define HAL_DFSDM_MODULE_ENABLED */ -/*#define HAL_DSI_MODULE_ENABLED */ +#define HAL_DSI_MODULE_ENABLED /*#define HAL_FIREWALL_MODULE_ENABLED */ -/*#define HAL_GFXMMU_MODULE_ENABLED */ +#define HAL_GFXMMU_MODULE_ENABLED /*#define HAL_HCD_MODULE_ENABLED */ /*#define HAL_HASH_MODULE_ENABLED */ /*#define HAL_I2S_MODULE_ENABLED */ /*#define HAL_IRDA_MODULE_ENABLED */ /*#define HAL_IWDG_MODULE_ENABLED */ -/*#define HAL_LTDC_MODULE_ENABLED */ +#define HAL_LTDC_MODULE_ENABLED /*#define HAL_LCD_MODULE_ENABLED */ /*#define HAL_LPTIM_MODULE_ENABLED */ /*#define HAL_NAND_MODULE_ENABLED */ @@ -85,7 +85,7 @@ /*#define HAL_SMBUS_MODULE_ENABLED */ /*#define HAL_SMARTCARD_MODULE_ENABLED */ /*#define HAL_SPI_MODULE_ENABLED */ -/*#define HAL_SRAM_MODULE_ENABLED */ +#define HAL_SRAM_MODULE_ENABLED /*#define HAL_SWPMI_MODULE_ENABLED */ /*#define HAL_TIM_MODULE_ENABLED */ /*#define HAL_TSC_MODULE_ENABLED */ diff --git a/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/Src/main.c b/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/Src/main.c index 9bc3ba4672..22a78d5058 100644 --- a/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/Src/main.c +++ b/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/Src/main.c @@ -6,7 +6,7 @@ ****************************************************************************** ** This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether + * USER CODE END. Other portions of this file, whether * inserted by the user or by software development tools * are owned by their respective copyright owners. * @@ -40,6 +40,7 @@ /* Includes ------------------------------------------------------------------*/ #include "main.h" +#include "gfxmmu_lut.h" /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ @@ -62,8 +63,18 @@ /* USER CODE END PM */ /* Private variables ---------------------------------------------------------*/ +DMA2D_HandleTypeDef hdma2d; + +DSI_HandleTypeDef hdsi; + +GFXMMU_HandleTypeDef hgfxmmu; + +LTDC_HandleTypeDef hltdc; + UART_HandleTypeDef huart3; +SRAM_HandleTypeDef hsram1; + /* USER CODE BEGIN PV */ /* USER CODE END PV */ @@ -72,6 +83,11 @@ UART_HandleTypeDef huart3; void SystemClock_Config(void); static void MX_GPIO_Init(void); static void MX_USART3_UART_Init(void); +static void MX_LTDC_Init(void); +static void MX_FMC_Init(void); +static void MX_DMA2D_Init(void); +static void MX_DSIHOST_DSI_Init(void); +static void MX_GFXMMU_Init(void); /* USER CODE BEGIN PFP */ /* USER CODE END PFP */ @@ -87,42 +103,47 @@ static void MX_USART3_UART_Init(void); */ int main(void) { - /* USER CODE BEGIN 1 */ + /* USER CODE BEGIN 1 */ - /* USER CODE END 1 */ + /* USER CODE END 1 */ - /* MCU Configuration--------------------------------------------------------*/ + /* MCU Configuration--------------------------------------------------------*/ - /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ - HAL_Init(); + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); - /* USER CODE BEGIN Init */ + /* USER CODE BEGIN Init */ - /* USER CODE END Init */ + /* USER CODE END Init */ - /* Configure the system clock */ - SystemClock_Config(); + /* Configure the system clock */ + SystemClock_Config(); - /* USER CODE BEGIN SysInit */ + /* USER CODE BEGIN SysInit */ - /* USER CODE END SysInit */ + /* USER CODE END SysInit */ - /* Initialize all configured peripherals */ - MX_GPIO_Init(); - MX_USART3_UART_Init(); - /* USER CODE BEGIN 2 */ + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_USART3_UART_Init(); + MX_LTDC_Init(); + MX_FMC_Init(); + MX_DMA2D_Init(); + MX_DSIHOST_DSI_Init(); + MX_GFXMMU_Init(); + /* USER CODE BEGIN 2 */ - /* USER CODE END 2 */ + /* USER CODE END 2 */ - /* Infinite loop */ - /* USER CODE BEGIN WHILE */ - while (1) - { - /* USER CODE END WHILE */ + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + /* USER CODE END WHILE */ - /* USER CODE BEGIN 3 */ - } - /* USER CODE END 3 */ + /* USER CODE BEGIN 3 */ + } + /* USER CODE END 3 */ } /** @@ -131,50 +152,318 @@ int main(void) */ void SystemClock_Config(void) { - RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - /**Configure the main internal regulator output voltage - */ - if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) != HAL_OK) - { - Error_Handler(); - } - /**Initializes the CPU, AHB and APB busses clocks - */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSEState = RCC_HSE_ON; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = 2; - RCC_OscInitStruct.PLL.PLLN = 30; - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; - RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; - RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) - { - Error_Handler(); - } - /**Initializes the CPU, AHB and APB busses clocks - */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK - |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + /**Configure the main internal regulator output voltage + */ + if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) != HAL_OK) + { + Error_Handler(); + } + /**Initializes the CPU, AHB and APB busses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 2; + RCC_OscInitStruct.PLL.PLLN = 30; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; + RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + /**Initializes the CPU, AHB and APB busses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) + { + Error_Handler(); + } + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART3|RCC_PERIPHCLK_DSI + |RCC_PERIPHCLK_LTDC; + PeriphClkInit.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1; + PeriphClkInit.DsiClockSelection = RCC_DSICLKSOURCE_DSIPHY; + PeriphClkInit.LtdcClockSelection = RCC_LTDCCLKSOURCE_PLLSAI2_DIV2; + PeriphClkInit.PLLSAI2.PLLSAI2Source = RCC_PLLSOURCE_HSE; + PeriphClkInit.PLLSAI2.PLLSAI2M = 2; + PeriphClkInit.PLLSAI2.PLLSAI2N = 8; + PeriphClkInit.PLLSAI2.PLLSAI2P = RCC_PLLP_DIV2; + PeriphClkInit.PLLSAI2.PLLSAI2R = RCC_PLLR_DIV2; + PeriphClkInit.PLLSAI2.PLLSAI2Q = RCC_PLLQ_DIV2; + PeriphClkInit.PLLSAI2.PLLSAI2ClockOut = RCC_PLLSAI2_LTDCCLK; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } +} + +/** + * @brief DMA2D Initialization Function + * @param None + * @retval None + */ +static void MX_DMA2D_Init(void) +{ + + /* USER CODE BEGIN DMA2D_Init 0 */ + + /* USER CODE END DMA2D_Init 0 */ + + /* USER CODE BEGIN DMA2D_Init 1 */ + + /* USER CODE END DMA2D_Init 1 */ + hdma2d.Instance = DMA2D; + hdma2d.Init.Mode = DMA2D_M2M; + hdma2d.Init.ColorMode = DMA2D_OUTPUT_ARGB8888; + hdma2d.Init.OutputOffset = 0; + hdma2d.Init.BytesSwap = DMA2D_BYTES_REGULAR; + hdma2d.Init.LineOffsetMode = DMA2D_LOM_PIXELS; + hdma2d.LayerCfg[1].InputOffset = 0; + hdma2d.LayerCfg[1].InputColorMode = DMA2D_INPUT_ARGB8888; + hdma2d.LayerCfg[1].AlphaMode = DMA2D_NO_MODIF_ALPHA; + hdma2d.LayerCfg[1].InputAlpha = 0; + hdma2d.LayerCfg[1].AlphaInverted = DMA2D_REGULAR_ALPHA; + hdma2d.LayerCfg[1].RedBlueSwap = DMA2D_RB_REGULAR; + if (HAL_DMA2D_Init(&hdma2d) != HAL_OK) + { + Error_Handler(); + } + if (HAL_DMA2D_ConfigLayer(&hdma2d, 1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN DMA2D_Init 2 */ + + /* USER CODE END DMA2D_Init 2 */ + +} + +/** + * @brief DSIHOST Initialization Function + * @param None + * @retval None + */ +static void MX_DSIHOST_DSI_Init(void) +{ + + /* USER CODE BEGIN DSIHOST_Init 0 */ + + /* USER CODE END DSIHOST_Init 0 */ + + DSI_PLLInitTypeDef PLLInit = {0}; + DSI_HOST_TimeoutTypeDef HostTimeouts = {0}; + DSI_PHY_TimerTypeDef PhyTimings = {0}; + DSI_LPCmdTypeDef LPCmd = {0}; + + /* USER CODE BEGIN DSIHOST_Init 1 */ + + /* USER CODE END DSIHOST_Init 1 */ + hdsi.Instance = DSI; + hdsi.Init.AutomaticClockLaneControl = DSI_AUTO_CLK_LANE_CTRL_DISABLE; + hdsi.Init.TXEscapeCkdiv = 4; + hdsi.Init.NumberOfLanes = DSI_ONE_DATA_LANE; + PLLInit.PLLNDIV = 20; + PLLInit.PLLIDF = DSI_PLL_IN_DIV1; + PLLInit.PLLODF = DSI_PLL_OUT_DIV2; + if (HAL_DSI_Init(&hdsi, &PLLInit) != HAL_OK) + { + Error_Handler(); + } + HostTimeouts.TimeoutCkdiv = 1; + HostTimeouts.HighSpeedTransmissionTimeout = 0; + HostTimeouts.LowPowerReceptionTimeout = 0; + HostTimeouts.HighSpeedReadTimeout = 0; + HostTimeouts.LowPowerReadTimeout = 0; + HostTimeouts.HighSpeedWriteTimeout = 0; + HostTimeouts.HighSpeedWritePrespMode = DSI_HS_PM_DISABLE; + HostTimeouts.LowPowerWriteTimeout = 0; + HostTimeouts.BTATimeout = 0; + if (HAL_DSI_ConfigHostTimeouts(&hdsi, &HostTimeouts) != HAL_OK) + { + Error_Handler(); + } + PhyTimings.ClockLaneHS2LPTime = 17; + PhyTimings.ClockLaneLP2HSTime = 12; + PhyTimings.DataLaneHS2LPTime = 8; + PhyTimings.DataLaneLP2HSTime = 8; + PhyTimings.DataLaneMaxReadTime = 0; + PhyTimings.StopWaitTime = 0; + + if (HAL_DSI_ConfigPhyTimer(&hdsi, &PhyTimings) != HAL_OK) + { + Error_Handler(); + } + if (HAL_DSI_ConfigFlowControl(&hdsi, DSI_FLOW_CONTROL_BTA) != HAL_OK) + { + Error_Handler(); + } + if (HAL_DSI_SetLowPowerRXFilter(&hdsi, 10000) != HAL_OK) + { + Error_Handler(); + } + if (HAL_DSI_ConfigErrorMonitor(&hdsi, HAL_DSI_ERROR_NONE) != HAL_OK) + { + Error_Handler(); + } + LPCmd.LPGenShortWriteNoP = DSI_LP_GSW0P_DISABLE; + LPCmd.LPGenShortWriteOneP = DSI_LP_GSW1P_DISABLE; + LPCmd.LPGenShortWriteTwoP = DSI_LP_GSW2P_DISABLE; + LPCmd.LPGenShortReadNoP = DSI_LP_GSR0P_DISABLE; + LPCmd.LPGenShortReadOneP = DSI_LP_GSR1P_DISABLE; + LPCmd.LPGenShortReadTwoP = DSI_LP_GSR2P_DISABLE; + LPCmd.LPGenLongWrite = DSI_LP_GLW_DISABLE; + LPCmd.LPDcsShortWriteNoP = DSI_LP_DSW0P_DISABLE; + LPCmd.LPDcsShortWriteOneP = DSI_LP_DSW1P_DISABLE; + LPCmd.LPDcsShortReadNoP = DSI_LP_DSR0P_DISABLE; + LPCmd.LPDcsLongWrite = DSI_LP_DLW_DISABLE; + LPCmd.LPMaxReadPacket = DSI_LP_MRDP_DISABLE; + LPCmd.AcknowledgeRequest = DSI_ACKNOWLEDGE_DISABLE; + if (HAL_DSI_ConfigCommand(&hdsi, &LPCmd) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN DSIHOST_Init 2 */ + + /* USER CODE END DSIHOST_Init 2 */ + +} + +/** + * @brief GFXMMU Initialization Function + * @param None + * @retval None + */ +static void MX_GFXMMU_Init(void) +{ + + /* USER CODE BEGIN GFXMMU_Init 0 */ + + /* USER CODE END GFXMMU_Init 0 */ + + /* USER CODE BEGIN GFXMMU_Init 1 */ + + /* USER CODE END GFXMMU_Init 1 */ + hgfxmmu.Instance = GFXMMU; + hgfxmmu.Init.BlocksPerLine = GFXMMU_192BLOCKS; + hgfxmmu.Init.DefaultValue = 0; + hgfxmmu.Init.Buffers.Buf0Address = 0; + hgfxmmu.Init.Buffers.Buf1Address = 0; + hgfxmmu.Init.Buffers.Buf2Address = 0; + hgfxmmu.Init.Buffers.Buf3Address = 0; + hgfxmmu.Init.Interrupts.Activation = ENABLE; + if (HAL_GFXMMU_Init(&hgfxmmu) != HAL_OK) + { + Error_Handler(); + } + if (HAL_GFXMMU_ConfigLut(&hgfxmmu, GFXMMU_LUT_FIRST, GFXMMU_LUT_SIZE, (uint32_t)gfxmmu_lut_config) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN GFXMMU_Init 2 */ + + /* USER CODE END GFXMMU_Init 2 */ + +} + +/** + * @brief LTDC Initialization Function + * @param None + * @retval None + */ +static void MX_LTDC_Init(void) +{ + + /* USER CODE BEGIN LTDC_Init 0 */ + + /* USER CODE END LTDC_Init 0 */ + + LTDC_LayerCfgTypeDef pLayerCfg = {0}; + LTDC_LayerCfgTypeDef pLayerCfg1 = {0}; + + /* USER CODE BEGIN LTDC_Init 1 */ + + /* USER CODE END LTDC_Init 1 */ + hltdc.Instance = LTDC; + hltdc.Init.HSPolarity = LTDC_HSPOLARITY_AL; + hltdc.Init.VSPolarity = LTDC_VSPOLARITY_AL; + hltdc.Init.DEPolarity = LTDC_DEPOLARITY_AL; + hltdc.Init.PCPolarity = LTDC_PCPOLARITY_IPC; + hltdc.Init.HorizontalSync = 7; + hltdc.Init.VerticalSync = 3; + hltdc.Init.AccumulatedHBP = 14; + hltdc.Init.AccumulatedVBP = 5; + hltdc.Init.AccumulatedActiveW = 654; + hltdc.Init.AccumulatedActiveH = 485; + hltdc.Init.TotalWidth = 660; + hltdc.Init.TotalHeigh = 487; + hltdc.Init.Backcolor.Blue = 0; + hltdc.Init.Backcolor.Green = 0; + hltdc.Init.Backcolor.Red = 0; + if (HAL_LTDC_Init(&hltdc) != HAL_OK) + { + Error_Handler(); + } + pLayerCfg.WindowX0 = 0; + pLayerCfg.WindowX1 = 0; + pLayerCfg.WindowY0 = 0; + pLayerCfg.WindowY1 = 0; + pLayerCfg.PixelFormat = LTDC_PIXEL_FORMAT_ARGB8888; + pLayerCfg.Alpha = 0; + pLayerCfg.Alpha0 = 0; + pLayerCfg.BlendingFactor1 = LTDC_BLENDING_FACTOR1_CA; + pLayerCfg.BlendingFactor2 = LTDC_BLENDING_FACTOR2_CA; + pLayerCfg.FBStartAdress = GFXMMU_VIRTUAL_BUFFER0_BASE; + pLayerCfg.ImageWidth = 0; + pLayerCfg.ImageHeight = 0; + pLayerCfg.Backcolor.Blue = 0; + pLayerCfg.Backcolor.Green = 0; + pLayerCfg.Backcolor.Red = 0; + if (HAL_LTDC_ConfigLayer(&hltdc, &pLayerCfg, 0) != HAL_OK) + { + Error_Handler(); + } + pLayerCfg1.WindowX0 = 0; + pLayerCfg1.WindowX1 = 0; + pLayerCfg1.WindowY0 = 0; + pLayerCfg1.WindowY1 = 0; + pLayerCfg1.PixelFormat = LTDC_PIXEL_FORMAT_ARGB8888; + pLayerCfg1.Alpha = 0; + pLayerCfg1.Alpha0 = 0; + pLayerCfg1.BlendingFactor1 = LTDC_BLENDING_FACTOR1_CA; + pLayerCfg1.BlendingFactor2 = LTDC_BLENDING_FACTOR2_CA; + pLayerCfg1.FBStartAdress = GFXMMU_VIRTUAL_BUFFER0_BASE; + pLayerCfg1.ImageWidth = 0; + pLayerCfg1.ImageHeight = 0; + pLayerCfg1.Backcolor.Blue = 0; + pLayerCfg1.Backcolor.Green = 0; + pLayerCfg1.Backcolor.Red = 0; + if (HAL_LTDC_ConfigLayer(&hltdc, &pLayerCfg1, 1) != HAL_OK) + { + Error_Handler(); + } + if (HAL_LTDC_SetPitch(&hltdc, 768, 0) != HAL_OK) + { + Error_Handler(); + } + if (HAL_LTDC_SetPitch(&hltdc, 768, 1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN LTDC_Init 2 */ + + /* USER CODE END LTDC_Init 2 */ - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) - { - Error_Handler(); - } - PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART3; - PeriphClkInit.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) - { - Error_Handler(); - } } /** @@ -185,43 +474,87 @@ void SystemClock_Config(void) static void MX_USART3_UART_Init(void) { - /* USER CODE BEGIN USART3_Init 0 */ + /* USER CODE BEGIN USART3_Init 0 */ - /* USER CODE END USART3_Init 0 */ + /* USER CODE END USART3_Init 0 */ - /* USER CODE BEGIN USART3_Init 1 */ + /* USER CODE BEGIN USART3_Init 1 */ - /* USER CODE END USART3_Init 1 */ - huart3.Instance = USART3; - huart3.Init.BaudRate = 115200; - huart3.Init.WordLength = UART_WORDLENGTH_8B; - huart3.Init.StopBits = UART_STOPBITS_1; - huart3.Init.Parity = UART_PARITY_NONE; - huart3.Init.Mode = UART_MODE_TX_RX; - huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE; - huart3.Init.OverSampling = UART_OVERSAMPLING_16; - huart3.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; - huart3.Init.ClockPrescaler = UART_PRESCALER_DIV1; - huart3.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; - if (HAL_UART_Init(&huart3) != HAL_OK) - { - Error_Handler(); - } - if (HAL_UARTEx_SetTxFifoThreshold(&huart3, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) - { - Error_Handler(); - } - if (HAL_UARTEx_SetRxFifoThreshold(&huart3, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) - { - Error_Handler(); - } - if (HAL_UARTEx_DisableFifoMode(&huart3) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN USART3_Init 2 */ + /* USER CODE END USART3_Init 1 */ + huart3.Instance = USART3; + huart3.Init.BaudRate = 115200; + huart3.Init.WordLength = UART_WORDLENGTH_8B; + huart3.Init.StopBits = UART_STOPBITS_1; + huart3.Init.Parity = UART_PARITY_NONE; + huart3.Init.Mode = UART_MODE_TX_RX; + huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart3.Init.OverSampling = UART_OVERSAMPLING_16; + huart3.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + huart3.Init.ClockPrescaler = UART_PRESCALER_DIV1; + huart3.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + if (HAL_UART_Init(&huart3) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_SetTxFifoThreshold(&huart3, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_SetRxFifoThreshold(&huart3, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_DisableFifoMode(&huart3) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART3_Init 2 */ - /* USER CODE END USART3_Init 2 */ + /* USER CODE END USART3_Init 2 */ + +} + +/* FMC initialization function */ +static void MX_FMC_Init(void) +{ + FMC_NORSRAM_TimingTypeDef Timing; + + /** Perform the SRAM1 memory initialization sequence + */ + hsram1.Instance = FMC_NORSRAM_DEVICE; + hsram1.Extended = FMC_NORSRAM_EXTENDED_DEVICE; + /* hsram1.Init */ + hsram1.Init.NSBank = FMC_NORSRAM_BANK1; + hsram1.Init.DataAddressMux = FMC_DATA_ADDRESS_MUX_DISABLE; + hsram1.Init.MemoryType = FMC_MEMORY_TYPE_SRAM; + hsram1.Init.MemoryDataWidth = FMC_NORSRAM_MEM_BUS_WIDTH_16; + hsram1.Init.BurstAccessMode = FMC_BURST_ACCESS_MODE_DISABLE; + hsram1.Init.WaitSignalPolarity = FMC_WAIT_SIGNAL_POLARITY_LOW; + hsram1.Init.WaitSignalActive = FMC_WAIT_TIMING_BEFORE_WS; + hsram1.Init.WriteOperation = FMC_WRITE_OPERATION_DISABLE; + hsram1.Init.WaitSignal = FMC_WAIT_SIGNAL_DISABLE; + hsram1.Init.ExtendedMode = FMC_EXTENDED_MODE_DISABLE; + hsram1.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE; + hsram1.Init.WriteBurst = FMC_WRITE_BURST_DISABLE; + hsram1.Init.ContinuousClock = FMC_CONTINUOUS_CLOCK_SYNC_ONLY; + hsram1.Init.WriteFifo = FMC_WRITE_FIFO_ENABLE; + hsram1.Init.NBLSetupTime = 0; + hsram1.Init.PageSize = FMC_PAGE_SIZE_NONE; + /* Timing */ + Timing.AddressSetupTime = 15; + Timing.AddressHoldTime = 15; + Timing.DataSetupTime = 255; + Timing.DataHoldTime = 0; + Timing.BusTurnAroundDuration = 15; + Timing.CLKDivision = 16; + Timing.DataLatency = 17; + Timing.AccessMode = FMC_ACCESS_MODE_A; + /* ExtTiming */ + + if (HAL_SRAM_Init(&hsram1, &Timing, NULL) != HAL_OK) + { + Error_Handler( ); + } } @@ -233,9 +566,15 @@ static void MX_USART3_UART_Init(void) static void MX_GPIO_Init(void) { - /* GPIO Ports Clock Enable */ - __HAL_RCC_GPIOH_CLK_ENABLE(); - __HAL_RCC_GPIOB_CLK_ENABLE(); + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOE_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOF_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + HAL_PWREx_EnableVddIO2(); + __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); } @@ -249,10 +588,10 @@ static void MX_GPIO_Init(void) */ void Error_Handler(void) { - /* USER CODE BEGIN Error_Handler_Debug */ - /* User can add his own implementation to report the HAL error return state */ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ - /* USER CODE END Error_Handler_Debug */ + /* USER CODE END Error_Handler_Debug */ } #ifdef USE_FULL_ASSERT @@ -264,11 +603,11 @@ void Error_Handler(void) * @retval None */ void assert_failed(char *file, uint32_t line) -{ - /* USER CODE BEGIN 6 */ - /* User can add his own implementation to report the file name and line number, - tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ - /* USER CODE END 6 */ +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ } #endif /* USE_FULL_ASSERT */ diff --git a/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c b/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c index 6183ad926f..0cdb9babc3 100644 --- a/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c +++ b/bsp/stm32/stm32l4r9-st-eval/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c @@ -11,7 +11,7 @@ * inserted by the user or by software development tools * are owned by their respective copyright owners. * - * COPYRIGHT(c) 2019 STMicroelectronics + * COPYRIGHT(c) 2018 STMicroelectronics * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -97,6 +97,194 @@ void HAL_MspInit(void) /* USER CODE END MspInit 1 */ } +/** +* @brief DMA2D MSP Initialization +* This function configures the hardware resources used in this example +* @param hdma2d: DMA2D handle pointer +* @retval None +*/ +void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d) +{ + + if(hdma2d->Instance==DMA2D) + { + /* USER CODE BEGIN DMA2D_MspInit 0 */ + + /* USER CODE END DMA2D_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_DMA2D_CLK_ENABLE(); + /* USER CODE BEGIN DMA2D_MspInit 1 */ + + /* USER CODE END DMA2D_MspInit 1 */ + } + +} + +/** +* @brief DMA2D MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hdma2d: DMA2D handle pointer +* @retval None +*/ + +void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d) +{ + + if(hdma2d->Instance==DMA2D) + { + /* USER CODE BEGIN DMA2D_MspDeInit 0 */ + + /* USER CODE END DMA2D_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_DMA2D_CLK_DISABLE(); + /* USER CODE BEGIN DMA2D_MspDeInit 1 */ + + /* USER CODE END DMA2D_MspDeInit 1 */ + } + +} + +/** +* @brief DSI MSP Initialization +* This function configures the hardware resources used in this example +* @param hdsi: DSI handle pointer +* @retval None +*/ +void HAL_DSI_MspInit(DSI_HandleTypeDef* hdsi) +{ + + if(hdsi->Instance==DSI) + { + /* USER CODE BEGIN DSI_MspInit 0 */ + + /* USER CODE END DSI_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_DSI_CLK_ENABLE(); + /* USER CODE BEGIN DSI_MspInit 1 */ + + /* USER CODE END DSI_MspInit 1 */ + } + +} + +/** +* @brief DSI MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hdsi: DSI handle pointer +* @retval None +*/ + +void HAL_DSI_MspDeInit(DSI_HandleTypeDef* hdsi) +{ + + if(hdsi->Instance==DSI) + { + /* USER CODE BEGIN DSI_MspDeInit 0 */ + + /* USER CODE END DSI_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_DSI_CLK_DISABLE(); + /* USER CODE BEGIN DSI_MspDeInit 1 */ + + /* USER CODE END DSI_MspDeInit 1 */ + } + +} + +/** +* @brief GFXMMU MSP Initialization +* This function configures the hardware resources used in this example +* @param hgfxmmu: GFXMMU handle pointer +* @retval None +*/ +void HAL_GFXMMU_MspInit(GFXMMU_HandleTypeDef* hgfxmmu) +{ + + if(hgfxmmu->Instance==GFXMMU) + { + /* USER CODE BEGIN GFXMMU_MspInit 0 */ + + /* USER CODE END GFXMMU_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_GFXMMU_CLK_ENABLE(); + /* USER CODE BEGIN GFXMMU_MspInit 1 */ + + /* USER CODE END GFXMMU_MspInit 1 */ + } + +} + +/** +* @brief GFXMMU MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hgfxmmu: GFXMMU handle pointer +* @retval None +*/ + +void HAL_GFXMMU_MspDeInit(GFXMMU_HandleTypeDef* hgfxmmu) +{ + + if(hgfxmmu->Instance==GFXMMU) + { + /* USER CODE BEGIN GFXMMU_MspDeInit 0 */ + + /* USER CODE END GFXMMU_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_GFXMMU_CLK_DISABLE(); + /* USER CODE BEGIN GFXMMU_MspDeInit 1 */ + + /* USER CODE END GFXMMU_MspDeInit 1 */ + } + +} + +/** +* @brief LTDC MSP Initialization +* This function configures the hardware resources used in this example +* @param hltdc: LTDC handle pointer +* @retval None +*/ +void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) +{ + + if(hltdc->Instance==LTDC) + { + /* USER CODE BEGIN LTDC_MspInit 0 */ + + /* USER CODE END LTDC_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_LTDC_CLK_ENABLE(); + /* USER CODE BEGIN LTDC_MspInit 1 */ + + /* USER CODE END LTDC_MspInit 1 */ + } + +} + +/** +* @brief LTDC MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hltdc: LTDC handle pointer +* @retval None +*/ + +void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc) +{ + + if(hltdc->Instance==LTDC) + { + /* USER CODE BEGIN LTDC_MspDeInit 0 */ + + /* USER CODE END LTDC_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_LTDC_CLK_DISABLE(); + /* USER CODE BEGIN LTDC_MspDeInit 1 */ + + /* USER CODE END LTDC_MspDeInit 1 */ + } + +} + /** * @brief UART MSP Initialization * This function configures the hardware resources used in this example @@ -165,6 +353,207 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) } +static uint32_t FMC_Initialized = 0; + +static void HAL_FMC_MspInit(void){ + /* USER CODE BEGIN FMC_MspInit 0 */ + + /* USER CODE END FMC_MspInit 0 */ + GPIO_InitTypeDef GPIO_InitStruct; + if (FMC_Initialized) { + return; + } + FMC_Initialized = 1; + /* Peripheral clock enable */ + __HAL_RCC_FMC_CLK_ENABLE(); + + /** FMC GPIO Configuration + PE0 ------> FMC_NBL0 + PE1 ------> FMC_NBL1 + PD0 ------> FMC_D2 + PD4 ------> FMC_NOE + PD1 ------> FMC_D3 + PE4 ------> FMC_A20 + PE3 ------> FMC_A19 + PD5 ------> FMC_NWE + PE5 ------> FMC_A21 + PF2 ------> FMC_A2 + PF1 ------> FMC_A1 + PF0 ------> FMC_A0 + PD7 ------> FMC_NE1 + PF3 ------> FMC_A3 + PF4 ------> FMC_A4 + PF5 ------> FMC_A5 + PG4 ------> FMC_A14 + PG3 ------> FMC_A13 + PG5 ------> FMC_A15 + PG1 ------> FMC_A11 + PE10 ------> FMC_D7 + PD13 ------> FMC_A18 + PG2 ------> FMC_A12 + PD15 ------> FMC_D1 + PD14 ------> FMC_D0 + PG0 ------> FMC_A10 + PE9 ------> FMC_D6 + PE15 ------> FMC_D12 + PD12 ------> FMC_A17 + PD11 ------> FMC_A16 + PD10 ------> FMC_D15 + PF15 ------> FMC_A9 + PE8 ------> FMC_D5 + PE14 ------> FMC_D11 + PD9 ------> FMC_D14 + PD8 ------> FMC_D13 + PF14 ------> FMC_A8 + PE7 ------> FMC_D4 + PE13 ------> FMC_D10 + PF13 ------> FMC_A7 + PE12 ------> FMC_D9 + PF12 ------> FMC_A6 + PE11 ------> FMC_D8 + */ + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_3 + |GPIO_PIN_5|GPIO_PIN_10|GPIO_PIN_9|GPIO_PIN_15 + |GPIO_PIN_8|GPIO_PIN_14|GPIO_PIN_7|GPIO_PIN_13 + |GPIO_PIN_12|GPIO_PIN_11; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_FMC; + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_4|GPIO_PIN_1|GPIO_PIN_5 + |GPIO_PIN_7|GPIO_PIN_13|GPIO_PIN_15|GPIO_PIN_14 + |GPIO_PIN_12|GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_9 + |GPIO_PIN_8; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_FMC; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_1|GPIO_PIN_0|GPIO_PIN_3 + |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_15|GPIO_PIN_14 + |GPIO_PIN_13|GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_FMC; + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_3|GPIO_PIN_5|GPIO_PIN_1 + |GPIO_PIN_2|GPIO_PIN_0; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_FMC; + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + + /* USER CODE BEGIN FMC_MspInit 1 */ + + /* USER CODE END FMC_MspInit 1 */ +} + +void HAL_SRAM_MspInit(SRAM_HandleTypeDef* hsram){ + /* USER CODE BEGIN SRAM_MspInit 0 */ + + /* USER CODE END SRAM_MspInit 0 */ + HAL_FMC_MspInit(); + /* USER CODE BEGIN SRAM_MspInit 1 */ + + /* USER CODE END SRAM_MspInit 1 */ +} + +static uint32_t FMC_DeInitialized = 0; + +static void HAL_FMC_MspDeInit(void){ + /* USER CODE BEGIN FMC_MspDeInit 0 */ + + /* USER CODE END FMC_MspDeInit 0 */ + if (FMC_DeInitialized) { + return; + } + FMC_DeInitialized = 1; + /* Peripheral clock enable */ + __HAL_RCC_FMC_CLK_DISABLE(); + + /** FMC GPIO Configuration + PE0 ------> FMC_NBL0 + PE1 ------> FMC_NBL1 + PD0 ------> FMC_D2 + PD4 ------> FMC_NOE + PD1 ------> FMC_D3 + PE4 ------> FMC_A20 + PE3 ------> FMC_A19 + PD5 ------> FMC_NWE + PE5 ------> FMC_A21 + PF2 ------> FMC_A2 + PF1 ------> FMC_A1 + PF0 ------> FMC_A0 + PD7 ------> FMC_NE1 + PF3 ------> FMC_A3 + PF4 ------> FMC_A4 + PF5 ------> FMC_A5 + PG4 ------> FMC_A14 + PG3 ------> FMC_A13 + PG5 ------> FMC_A15 + PG1 ------> FMC_A11 + PE10 ------> FMC_D7 + PD13 ------> FMC_A18 + PG2 ------> FMC_A12 + PD15 ------> FMC_D1 + PD14 ------> FMC_D0 + PG0 ------> FMC_A10 + PE9 ------> FMC_D6 + PE15 ------> FMC_D12 + PD12 ------> FMC_A17 + PD11 ------> FMC_A16 + PD10 ------> FMC_D15 + PF15 ------> FMC_A9 + PE8 ------> FMC_D5 + PE14 ------> FMC_D11 + PD9 ------> FMC_D14 + PD8 ------> FMC_D13 + PF14 ------> FMC_A8 + PE7 ------> FMC_D4 + PE13 ------> FMC_D10 + PF13 ------> FMC_A7 + PE12 ------> FMC_D9 + PF12 ------> FMC_A6 + PE11 ------> FMC_D8 + */ + HAL_GPIO_DeInit(GPIOE, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_3 + |GPIO_PIN_5|GPIO_PIN_10|GPIO_PIN_9|GPIO_PIN_15 + |GPIO_PIN_8|GPIO_PIN_14|GPIO_PIN_7|GPIO_PIN_13 + |GPIO_PIN_12|GPIO_PIN_11); + + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_0|GPIO_PIN_4|GPIO_PIN_1|GPIO_PIN_5 + |GPIO_PIN_7|GPIO_PIN_13|GPIO_PIN_15|GPIO_PIN_14 + |GPIO_PIN_12|GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_9 + |GPIO_PIN_8); + + HAL_GPIO_DeInit(GPIOF, GPIO_PIN_2|GPIO_PIN_1|GPIO_PIN_0|GPIO_PIN_3 + |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_15|GPIO_PIN_14 + |GPIO_PIN_13|GPIO_PIN_12); + + HAL_GPIO_DeInit(GPIOG, GPIO_PIN_4|GPIO_PIN_3|GPIO_PIN_5|GPIO_PIN_1 + |GPIO_PIN_2|GPIO_PIN_0); + + /* USER CODE BEGIN FMC_MspDeInit 1 */ + + /* USER CODE END FMC_MspDeInit 1 */ +} + +void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef* hsram){ + /* USER CODE BEGIN SRAM_MspDeInit 0 */ + + /* USER CODE END SRAM_MspDeInit 0 */ + HAL_FMC_MspDeInit(); + /* USER CODE BEGIN SRAM_MspDeInit 1 */ + + /* USER CODE END SRAM_MspDeInit 1 */ +} + /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ diff --git a/bsp/stm32/stm32l4r9-st-eval/board/Kconfig b/bsp/stm32/stm32l4r9-st-eval/board/Kconfig index 601a9097af..09c1ff58ca 100644 --- a/bsp/stm32/stm32l4r9-st-eval/board/Kconfig +++ b/bsp/stm32/stm32l4r9-st-eval/board/Kconfig @@ -7,6 +7,39 @@ config SOC_STM32L4R9AI menu "Onboard Peripheral Drivers" + config BSP_USING_STLINK_TO_USART + bool "Enable STLINK TO USART (uart3)" + select BSP_USING_UART + select BSP_USING_UART3 + default y + + config BSP_USING_DSI + bool "Enable LCD" + select BSP_USING_SRAM + select BSP_USING_GFXMMU + default n + + menu "Enable Touch" + + config BSP_USING_TOUCH + bool "Enable Touch drivers" + select BSP_USING_I2C1 + default n + if BSP_USING_TOUCH + config BSP_TOUCH_INT_PIN + int "Touch interrupt pin" + default 34 + config BSP_I2C1_NAME + string "I2C1 Name for Touch" + default i2c1 + endif + + config TOUCH_IC_FT3X67 + bool "FT3X67" + depends on BSP_USING_TOUCH + default n + + endmenu endmenu menu "On-chip Peripheral Drivers" @@ -21,10 +54,40 @@ menu "On-chip Peripheral Drivers" default y select RT_USING_SERIAL if BSP_USING_UART - config BSP_USING_UART3 - bool "Enable UART3" - default y + config BSP_USING_UART3 + bool "Enable UART3" + default y endif + + config BSP_USING_SRAM + bool "Enable SRAM" + select BSP_USING_FMC + default n + + menuconfig BSP_USING_I2C1 + bool "Enable I2C1 BUS (software simulation)" + default n + select RT_USING_I2C + select RT_USING_I2C_BITOPS + select RT_USING_PIN + if BSP_USING_I2C1 + config BSP_I2C1_SCL_PIN + int "i2c1 scl pin number" + range 1 216 + default 116 + config BSP_I2C1_SDA_PIN + int "I2C1 sda pin number" + range 1 216 + default 117 + endif + + config BSP_USING_GFXMMU + bool + default n + + config BSP_USING_FMC + bool + default n endmenu diff --git a/bsp/stm32/stm32l4r9-st-eval/board/SConscript b/bsp/stm32/stm32l4r9-st-eval/board/SConscript index 4fd82e867f..21e3276788 100644 --- a/bsp/stm32/stm32l4r9-st-eval/board/SConscript +++ b/bsp/stm32/stm32l4r9-st-eval/board/SConscript @@ -12,8 +12,19 @@ board.c CubeMX_Config/Src/stm32l4xx_hal_msp.c ''') +if GetDepend(['BSP_USING_DSI']): + src += Glob('ports/drv_lcd_dsi.c') + +if GetDepend(['BSP_USING_SRAM']): + src += Glob('ports/drv_sram.c') + +if GetDepend(['BSP_USING_TOUCH']): + src += Glob('ports/drv_touch.c') + src += Glob('ports/drv_touch_ft.c') + path = [cwd] path += [cwd + '/CubeMX_Config/Inc'] +path += [cwd + '/ports/include'] startup_path_prefix = SDK_LIB diff --git a/bsp/stm32/stm32l4r9-st-eval/board/board.c b/bsp/stm32/stm32l4r9-st-eval/board/board.c index 3e173615bb..af69f12729 100644 --- a/bsp/stm32/stm32l4r9-st-eval/board/board.c +++ b/bsp/stm32/stm32l4r9-st-eval/board/board.c @@ -6,54 +6,62 @@ * Change Logs: * Date Author Notes * 2018-11-06 SummerGift first version - * 2019-04-09 jhb */ #include "board.h" + void SystemClock_Config(void) { - RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - /**Configure the main internal regulator output voltage - */ - if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) != HAL_OK) - { - Error_Handler(); - } - /**Initializes the CPU, AHB and APB busses clocks - */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSEState = RCC_HSE_ON; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = 2; - RCC_OscInitStruct.PLL.PLLN = 30; - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; - RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; - RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) - { - Error_Handler(); - } - /**Initializes the CPU, AHB and APB busses clocks - */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK - |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + /**Configure the main internal regulator output voltage + */ + if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) != HAL_OK) + { + Error_Handler(); + } + /**Initializes the CPU, AHB and APB busses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 2; + RCC_OscInitStruct.PLL.PLLN = 30; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; + RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + /**Initializes the CPU, AHB and APB busses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) - { - Error_Handler(); - } - PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART3; - PeriphClkInit.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) - { - Error_Handler(); - } + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) + { + Error_Handler(); + } + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART3|RCC_PERIPHCLK_DSI|RCC_PERIPHCLK_LTDC; + PeriphClkInit.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1; + PeriphClkInit.DsiClockSelection = RCC_DSICLKSOURCE_DSIPHY; + PeriphClkInit.LtdcClockSelection = RCC_LTDCCLKSOURCE_PLLSAI2_DIV2; + PeriphClkInit.PLLSAI2.PLLSAI2Source = RCC_PLLSOURCE_HSE; + PeriphClkInit.PLLSAI2.PLLSAI2M = 2; + PeriphClkInit.PLLSAI2.PLLSAI2N = 8; + PeriphClkInit.PLLSAI2.PLLSAI2P = RCC_PLLP_DIV2; + PeriphClkInit.PLLSAI2.PLLSAI2R = RCC_PLLR_DIV2; + PeriphClkInit.PLLSAI2.PLLSAI2Q = RCC_PLLQ_DIV2; + PeriphClkInit.PLLSAI2.PLLSAI2ClockOut = RCC_PLLSAI2_LTDCCLK; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } } diff --git a/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_lcd_dsi.c b/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_lcd_dsi.c new file mode 100644 index 0000000000..8e926d7e2d --- /dev/null +++ b/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_lcd_dsi.c @@ -0,0 +1,725 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-01-10 zylx first version + */ + +#include +#include +#include + +#ifdef BSP_USING_DSI +#include +#include +#include "drv_gpio.h" +#include "gfxmmu_lut_390x390_24bpp.h" + +#define DRV_DEBUG +#define LOG_TAG "drv.lcd" +#include + +static DSI_HandleTypeDef DsiHandle; + +struct drv_lcd_dsi_device +{ + struct rt_device parent; + + struct rt_device_graphic_info lcd_info; + + struct rt_semaphore lcd_lock; + + rt_uint8_t *front_buf; +}; + +struct drv_lcd_dsi_device _lcd; + +static DMA2D_HandleTypeDef Dma2dHandle; +static void CopyInVirtualBuffer(uint32_t *pSrc, uint32_t *pDst, uint16_t x, uint16_t y, uint16_t xsize, uint16_t ysize) +{ + uint32_t destination = (uint32_t)pDst + (y * 390 + x) * 4; + uint32_t source = (uint32_t)pSrc; + + Dma2dHandle.Instance = DMA2D; + + /*##-1- Configure the DMA2D Mode, Color Mode and output offset #############*/ + Dma2dHandle.Init.Mode = DMA2D_M2M_PFC; + Dma2dHandle.Init.ColorMode = DMA2D_OUTPUT_RGB888; + Dma2dHandle.Init.OutputOffset = 1024 - 390; + /* No Output Alpha Inversion */ + Dma2dHandle.Init.AlphaInverted = DMA2D_REGULAR_ALPHA; + /* No Output Red & Blue swap */ + Dma2dHandle.Init.RedBlueSwap = DMA2D_RB_REGULAR; + /* Regular output byte order */ + Dma2dHandle.Init.BytesSwap = DMA2D_BYTES_REGULAR; + /* Pixel mode */ + Dma2dHandle.Init.LineOffsetMode = DMA2D_LOM_PIXELS; + + /*##-2- Foreground Configuration ###########################################*/ + Dma2dHandle.LayerCfg[1].InputColorMode = DMA2D_INPUT_ARGB8888; + Dma2dHandle.LayerCfg[1].InputOffset = 0; + Dma2dHandle.LayerCfg[1].AlphaMode = DMA2D_NO_MODIF_ALPHA; + /* Not used */ + Dma2dHandle.LayerCfg[1].InputAlpha = 0xFF; + /* No ForeGround Red/Blue swap */ + Dma2dHandle.LayerCfg[1].RedBlueSwap = DMA2D_RB_REGULAR; + /* No ForeGround Alpha inversion */ + Dma2dHandle.LayerCfg[1].AlphaInverted = DMA2D_REGULAR_ALPHA; + + /* DMA2D Initialization */ + if (HAL_DMA2D_Init(&Dma2dHandle) == HAL_OK) + { + if (HAL_DMA2D_ConfigLayer(&Dma2dHandle, 1) == HAL_OK) + { + if (HAL_DMA2D_Start(&Dma2dHandle, source, destination, xsize, ysize) == HAL_OK) + { + /* Polling For DMA transfer */ + HAL_DMA2D_PollForTransfer(&Dma2dHandle, 100); + } + } + } +} + +static rt_err_t drv_lcd_init(struct rt_device *device) +{ + struct drv_lcd_dsi_device *lcd = (struct drv_lcd_dsi_device *)device; + /* nothing, right now */ + lcd = lcd; + return RT_EOK; +} + +static rt_err_t drv_lcd_control(struct rt_device *device, int cmd, void *args) +{ + struct drv_lcd_dsi_device *lcd = (struct drv_lcd_dsi_device *)device; + rt_uint8_t color = 0; + switch (cmd) + { + case RTGRAPHIC_CTRL_RECT_UPDATE: + { + /* update */ + rt_sem_take(&_lcd.lcd_lock, RT_TICK_PER_SECOND / 20); + CopyInVirtualBuffer((uint32_t *)_lcd.lcd_info.framebuffer, (uint32_t *)LAYER_ADDRESS, 0, 0, 390, 390); + HAL_DSI_Refresh(&DsiHandle); + } + break; + + case RTGRAPHIC_CTRL_GET_INFO: + { + struct rt_device_graphic_info *info = (struct rt_device_graphic_info *)args; + + RT_ASSERT(info != RT_NULL); + info->pixel_format = lcd->lcd_info.pixel_format; + info->bits_per_pixel = 32; + info->width = lcd->lcd_info.width; + info->height = lcd->lcd_info.height; + info->framebuffer = lcd->lcd_info.framebuffer; + } + break; + } + + return RT_EOK; +} + +LTDC_HandleTypeDef LtdcHandle; +rt_err_t stm32_lcd_init(struct drv_lcd_dsi_device *lcd) +{ + DSI_PLLInitTypeDef dsiPllInit = {0}; + DSI_PHY_TimerTypeDef PhyTimings = {0}; + DSI_HOST_TimeoutTypeDef HostTimeouts = {0}; + DSI_LPCmdTypeDef LPCmd = {0}; + DSI_CmdCfgTypeDef CmdCfg = {0}; + GFXMMU_HandleTypeDef GfxmmuHandle = {0}; + LTDC_LayerCfgTypeDef LayerCfg = {0}; + + /* GFXMMU CONFIGURATION */ + __HAL_GFXMMU_RESET_HANDLE_STATE(&GfxmmuHandle); + GfxmmuHandle.Instance = GFXMMU; + GfxmmuHandle.Init.BlocksPerLine = GFXMMU_192BLOCKS; + GfxmmuHandle.Init.DefaultValue = 0xFFFFFFFF; + GfxmmuHandle.Init.Buffers.Buf0Address = (uint32_t)lcd->front_buf; + GfxmmuHandle.Init.Buffers.Buf1Address = 0; + GfxmmuHandle.Init.Buffers.Buf2Address = 0; + GfxmmuHandle.Init.Buffers.Buf3Address = 0; + GfxmmuHandle.Init.Interrupts.Activation = DISABLE; + GfxmmuHandle.Init.Interrupts.UsedInterrupts = GFXMMU_AHB_MASTER_ERROR_IT; + if (HAL_OK != HAL_GFXMMU_Init(&GfxmmuHandle)) + { + return -RT_ERROR; + } + + /* Initialize LUT */ + if (HAL_OK != HAL_GFXMMU_ConfigLut(&GfxmmuHandle, 0, 390, (uint32_t) gfxmmu_lut_config_rgb888)) + { + return -RT_ERROR; + } + + /* Disable non visible lines : from line 390 to 1023 (634 lines) */ + if (HAL_OK != HAL_GFXMMU_DisableLutLines(&GfxmmuHandle, 390, 634)) + { + return -RT_ERROR; + } + + /**********************/ + /* LTDC CONFIGURATION */ + /**********************/ + /* LTDC initialization */ + __HAL_LTDC_RESET_HANDLE_STATE(&LtdcHandle); + LtdcHandle.Instance = LTDC; + LtdcHandle.Init.HSPolarity = LTDC_HSPOLARITY_AL; + LtdcHandle.Init.VSPolarity = LTDC_VSPOLARITY_AL; + LtdcHandle.Init.DEPolarity = LTDC_DEPOLARITY_AL; + LtdcHandle.Init.PCPolarity = LTDC_PCPOLARITY_IPC; + /* HSYNC width - 1 */ + LtdcHandle.Init.HorizontalSync = 0; + /* VSYNC width - 1 */ + LtdcHandle.Init.VerticalSync = 0; + /* HSYNC width + HBP - 1 */ + LtdcHandle.Init.AccumulatedHBP = 1; + /* VSYNC width + VBP - 1 */ + LtdcHandle.Init.AccumulatedVBP = 1; + /* HSYNC width + HBP + Active width - 1 */ + LtdcHandle.Init.AccumulatedActiveW = 391; + /* VSYNC width + VBP + Active height - 1 */ + LtdcHandle.Init.AccumulatedActiveH = 391; + /* HSYNC width + HBP + Active width + HFP - 1 */ + LtdcHandle.Init.TotalWidth = 392; + /* VSYNC width + VBP + Active height + VFP - 1 */ + LtdcHandle.Init.TotalHeigh = 392; + LtdcHandle.Init.Backcolor.Red = 0; + LtdcHandle.Init.Backcolor.Green = 0; + LtdcHandle.Init.Backcolor.Blue = 0; + LtdcHandle.Init.Backcolor.Reserved = 0xFF; + if (HAL_LTDC_Init(&LtdcHandle) != HAL_OK) + { + return -RT_ERROR; + } + + /* LTDC layer 1 configuration */ + LayerCfg.WindowX0 = 0; + LayerCfg.WindowX1 = 390; + LayerCfg.WindowY0 = 0; + LayerCfg.WindowY1 = 390; + LayerCfg.PixelFormat = LTDC_PIXEL_FORMAT_RGB888; + LayerCfg.Alpha = 0xFF; + LayerCfg.Alpha0 = 0; + LayerCfg.BlendingFactor1 = LTDC_BLENDING_FACTOR1_PAxCA; + LayerCfg.BlendingFactor2 = LTDC_BLENDING_FACTOR2_PAxCA; + LayerCfg.FBStartAdress = LAYER_ADDRESS; + /* virtual frame buffer contains 768 pixels per line for 24bpp */ + /* (192 blocs * 16) / (24bpp/3) = 1024 pixels per ligne */ + LayerCfg.ImageWidth = 1024; + LayerCfg.ImageHeight = 390; + LayerCfg.Backcolor.Red = 0; + LayerCfg.Backcolor.Green = 0; + LayerCfg.Backcolor.Blue = 0; + LayerCfg.Backcolor.Reserved = 0xFF; + if (HAL_LTDC_ConfigLayer(&LtdcHandle, &LayerCfg, LTDC_LAYER_1) != HAL_OK) + { + return -RT_ERROR; + } + + /*********************/ + /* DSI CONFIGURATION */ + /*********************/ + + /* DSI initialization */ + __HAL_DSI_RESET_HANDLE_STATE(&DsiHandle); + DsiHandle.Instance = DSI; + DsiHandle.Init.AutomaticClockLaneControl = DSI_AUTO_CLK_LANE_CTRL_DISABLE; + /* We have 1 data lane at 500Mbps => lane byte clock at 500/8 = 62,5 MHZ */ + /* We want TX escape clock at arround 20MHz and under 20MHz so clock division is set to 4 */ + DsiHandle.Init.TXEscapeCkdiv = 4; + DsiHandle.Init.NumberOfLanes = DSI_ONE_DATA_LANE; + /* We have HSE value at 16 Mhz and we want data lane at 500Mbps */ + dsiPllInit.PLLNDIV = 20; + dsiPllInit.PLLIDF = DSI_PLL_IN_DIV1; + dsiPllInit.PLLODF = DSI_PLL_OUT_DIV2; + if (HAL_DSI_Init(&DsiHandle, &dsiPllInit) != HAL_OK) + { + return -RT_ERROR; + } + /* Tclk-post + Tclk-trail + Ths-exit = [(60ns + 52xUI) + (60ns) + (300ns)]/16ns */ + PhyTimings.ClockLaneHS2LPTime = 33; + /* Tlpx + (Tclk-prepare + Tclk-zero) + Tclk-pre = [150ns + 300ns + 8xUI]/16ns */ + PhyTimings.ClockLaneLP2HSTime = 30; + /* Ths-trail + Ths-exit = [(60ns + 4xUI) + 100ns]/16ns */ + PhyTimings.DataLaneHS2LPTime = 11; + /* Tlpx + (Ths-prepare + Ths-zero) + Ths-sync = [150ns + (145ns + 10xUI) + 8xUI]/16ns */ + PhyTimings.DataLaneLP2HSTime = 21; + PhyTimings.DataLaneMaxReadTime = 0; + PhyTimings.StopWaitTime = 7; + if (HAL_DSI_ConfigPhyTimer(&DsiHandle, &PhyTimings) != HAL_OK) + { + return -RT_ERROR; + } + + HostTimeouts.TimeoutCkdiv = 1; + HostTimeouts.HighSpeedTransmissionTimeout = 0; + HostTimeouts.LowPowerReceptionTimeout = 0; + HostTimeouts.HighSpeedReadTimeout = 0; + HostTimeouts.LowPowerReadTimeout = 0; + HostTimeouts.HighSpeedWriteTimeout = 0; + HostTimeouts.HighSpeedWritePrespMode = 0; + HostTimeouts.LowPowerWriteTimeout = 0; + HostTimeouts.BTATimeout = 0; + if (HAL_DSI_ConfigHostTimeouts(&DsiHandle, &HostTimeouts) != HAL_OK) + { + return -RT_ERROR; + } + + LPCmd.LPGenShortWriteNoP = DSI_LP_GSW0P_ENABLE; + LPCmd.LPGenShortWriteOneP = DSI_LP_GSW1P_ENABLE; + LPCmd.LPGenShortWriteTwoP = DSI_LP_GSW2P_ENABLE; + LPCmd.LPGenShortReadNoP = DSI_LP_GSR0P_ENABLE; + LPCmd.LPGenShortReadOneP = DSI_LP_GSR1P_ENABLE; + LPCmd.LPGenShortReadTwoP = DSI_LP_GSR2P_ENABLE; + LPCmd.LPGenLongWrite = DSI_LP_GLW_DISABLE; + LPCmd.LPDcsShortWriteNoP = DSI_LP_DSW0P_ENABLE; + LPCmd.LPDcsShortWriteOneP = DSI_LP_DSW1P_ENABLE; + LPCmd.LPDcsShortReadNoP = DSI_LP_DSR0P_ENABLE; + LPCmd.LPDcsLongWrite = DSI_LP_DLW_DISABLE; + LPCmd.LPMaxReadPacket = DSI_LP_MRDP_DISABLE; + LPCmd.AcknowledgeRequest = DSI_ACKNOWLEDGE_DISABLE; + if (HAL_DSI_ConfigCommand(&DsiHandle, &LPCmd) != HAL_OK) + { + return -RT_ERROR; + } + + CmdCfg.VirtualChannelID = 0; +#if LCD_BITS_PER_PIXEL == 16 + CmdCfg.ColorCoding = DSI_RGB565; +#else + CmdCfg.ColorCoding = DSI_RGB888; +#endif + CmdCfg.CommandSize = 390; + CmdCfg.TearingEffectSource = DSI_TE_DSILINK; + CmdCfg.TearingEffectPolarity = DSI_TE_FALLING_EDGE; + CmdCfg.HSPolarity = DSI_HSYNC_ACTIVE_LOW; + CmdCfg.VSPolarity = DSI_VSYNC_ACTIVE_LOW; + CmdCfg.DEPolarity = DSI_DATA_ENABLE_ACTIVE_HIGH; + CmdCfg.VSyncPol = DSI_VSYNC_FALLING; + CmdCfg.AutomaticRefresh = DSI_AR_ENABLE; + CmdCfg.TEAcknowledgeRequest = DSI_TE_ACKNOWLEDGE_ENABLE; + if (HAL_DSI_ConfigAdaptedCommandMode(&DsiHandle, &CmdCfg) != HAL_OK) + { + return -RT_ERROR; + } + + /* Disable the Tearing Effect interrupt activated by default on previous function */ + __HAL_DSI_DISABLE_IT(&DsiHandle, DSI_IT_TE); + + if (HAL_DSI_ConfigFlowControl(&DsiHandle, DSI_FLOW_CONTROL_BTA) != HAL_OK) + { + return -RT_ERROR; + } + + /* Enable DSI */ + __HAL_DSI_ENABLE(&DsiHandle); + + /*************************/ + /* LCD POWER ON SEQUENCE */ + /*************************/ + /* Step 1 */ + /* Go to command 2 */ + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0xFE, 0x01); + /* IC Frame rate control, set power, sw mapping, mux swithc timing command */ + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x06, 0x62); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x0E, 0x80); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x0F, 0x80); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x10, 0x71); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x13, 0x81); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x14, 0x81); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x15, 0x82); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x16, 0x82); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x18, 0x88); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x19, 0x55); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x1A, 0x10); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x1C, 0x99); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x1D, 0x03); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x1E, 0x03); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x1F, 0x03); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x20, 0x03); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x25, 0x03); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x26, 0x8D); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x2A, 0x03); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x2B, 0x8D); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x36, 0x00); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x37, 0x10); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x3A, 0x00); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x3B, 0x00); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x3D, 0x20); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x3F, 0x3A); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x40, 0x30); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x41, 0x1A); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x42, 0x33); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x43, 0x22); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x44, 0x11); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x45, 0x66); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x46, 0x55); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x47, 0x44); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x4C, 0x33); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x4D, 0x22); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x4E, 0x11); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x4F, 0x66); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x50, 0x55); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x51, 0x44); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x57, 0x33); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x6B, 0x1B); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x70, 0x55); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x74, 0x0C); + + /* Go to command 3 */ + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0xFE, 0x02); + /* Set the VGMP/VGSP coltage control */ + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x9B, 0x40); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x9C, 0x00); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x9D, 0x20); + + /* Go to command 4 */ + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0xFE, 0x03); + /* Set the VGMP/VGSP coltage control */ + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x9B, 0x40); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x9C, 0x00); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x9D, 0x20); + + /* Go to command 5 */ + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0xFE, 0x04); + /* VSR command */ + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x5D, 0x10); + /* VSR1 timing set */ + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x00, 0x8D); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x01, 0x00); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x02, 0x01); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x03, 0x01); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x04, 0x10); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x05, 0x01); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x06, 0xA7); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x07, 0x20); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x08, 0x00); + /* VSR2 timing set */ + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x09, 0xC2); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x0A, 0x00); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x0B, 0x02); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x0C, 0x01); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x0D, 0x40); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x0E, 0x06); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x0F, 0x01); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x10, 0xA7); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x11, 0x00); + /* VSR3 timing set */ + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x12, 0xC2); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x13, 0x00); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x14, 0x02); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x15, 0x01); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x16, 0x40); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x17, 0x07); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x18, 0x01); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x19, 0xA7); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x1A, 0x00); + /* VSR4 timing set */ + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x1B, 0x82); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x1C, 0x00); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x1D, 0xFF); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x1E, 0x05); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x1F, 0x60); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x20, 0x02); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x21, 0x01); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x22, 0x7C); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x23, 0x00); + /* VSR5 timing set */ + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x24, 0xC2); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x25, 0x00); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x26, 0x04); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x27, 0x02); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x28, 0x70); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x29, 0x05); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x2A, 0x74); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x2B, 0x8D); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x2D, 0x00); + /* VSR6 timing set */ + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x2F, 0xC2); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x30, 0x00); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x31, 0x04); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x32, 0x02); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x33, 0x70); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x34, 0x07); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x35, 0x74); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x36, 0x8D); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x37, 0x00); + /* VSR marping command */ + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x5E, 0x20); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x5F, 0x31); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x60, 0x54); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x61, 0x76); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x62, 0x98); + + /* Go to command 6 */ + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0xFE, 0x05); + /* Set the ELVSS voltage */ + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x05, 0x17); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x2A, 0x04); + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x91, 0x00); + + /* Go back in standard commands */ + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0xFE, 0x00); + + /* Set the Pixel format */ + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x3A, 0x07); + + /* Set tear off */ + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, DSI_SET_TEAR_OFF, 0x0); + + /* Set DSI mode to internal timing added vs ORIGINAL for Command mode */ + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0xC2, 0x0); + + /* Set memory address MODIFIED vs ORIGINAL */ + { + uint8_t InitParam1[4] = {0x00, 0x04, 0x01, 0x89}; + uint8_t InitParam2[4] = {0x00, 0x00, 0x01, 0x85}; + + HAL_DSI_LongWrite(&DsiHandle, 0, DSI_DCS_LONG_PKT_WRITE, 4, DSI_SET_COLUMN_ADDRESS, InitParam1); + HAL_DSI_LongWrite(&DsiHandle, 0, DSI_DCS_LONG_PKT_WRITE, 4, DSI_SET_PAGE_ADDRESS, InitParam2); + } + + /* Sleep out */ + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P0, DSI_EXIT_SLEEP_MODE, 0x0); + + HAL_Delay(120); + + /* Set default Brightness */ + HAL_DSI_ShortWrite(&DsiHandle, 0, DSI_DCS_SHORT_PKT_WRITE_P1, 0x51, BRIGHTNESS_NORMAL); + + /* Set display on */ + if (HAL_DSI_ShortWrite(&DsiHandle, + 0, + DSI_DCS_SHORT_PKT_WRITE_P0, + DSI_SET_DISPLAY_ON, + 0x0) != HAL_OK) + { + LOG_E("set display on failed"); + return -RT_ERROR; + } + + /* Enable DSI Wrapper */ + __HAL_DSI_WRAPPER_ENABLE(&DsiHandle); + + /* NVIC configuration for DSI interrupt that is now enabled */ + HAL_NVIC_SetPriority(DSI_IRQn, 3, 0); + HAL_NVIC_EnableIRQ(DSI_IRQn); + + HAL_DSI_Refresh(&DsiHandle); + LOG_D("LCD init success"); + + return RT_EOK; +} + +#if defined(LCD_BACKLIGHT_USING_PWM) +void turn_on_lcd_backlight(void) +{ + struct rt_device_pwm *pwm_dev; + + /* turn on the LCD backlight */ + pwm_dev = (struct rt_device_pwm *)rt_device_find(PWM_DEV_NAME); + /* pwm frequency:100K = 10000ns */ + rt_pwm_set(pwm_dev, PWM_DEV_CHANNEL, 10000, 10000); + rt_pwm_enable(pwm_dev, PWM_DEV_CHANNEL); +} +#elif defined(LCD_BACKLIGHT_USING_GPIO) +void turn_on_lcd_backlight(void) +{ + rt_pin_mode(LCD_BL_GPIO_NUM, PIN_MODE_OUTPUT); + + rt_pin_write(LCD_BL_GPIO_NUM, PIN_HIGH); +} +#endif + +void DSI_IRQHandler(void) +{ + HAL_DSI_IRQHandler(&DsiHandle); +} + +void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi) +{ + rt_sem_release(&_lcd.lcd_lock); +} + +#ifdef RT_USING_DEVICE_OPS +const static struct rt_device_ops lcd_ops = +{ + drv_lcd_init, + RT_NULL, + RT_NULL, + RT_NULL, + RT_NULL, + drv_lcd_control +}; +#endif + +int drv_lcd_hw_init(void) +{ + rt_err_t result = RT_EOK; + struct rt_device *device = &_lcd.parent; + + /* memset _lcd to zero */ + memset(&_lcd, 0x00, sizeof(_lcd)); + + /* init lcd_lock semaphore */ + result = rt_sem_init(&_lcd.lcd_lock, "lcd_lock", 0, RT_IPC_FLAG_FIFO); + if (result != RT_EOK) + { + LOG_E("init semaphore failed!\n"); + result = -RT_ENOMEM; + goto __exit; + } + + /* config LCD dev info */ + _lcd.lcd_info.height = LCD_HEIGHT; + _lcd.lcd_info.width = LCD_WIDTH; + _lcd.lcd_info.bits_per_pixel = LCD_BITS_PER_PIXEL; + _lcd.lcd_info.pixel_format = LCD_PIXEL_FORMAT; + + /* malloc memory */ + _lcd.lcd_info.framebuffer = rt_malloc_align(LCD_DSI_BUF_SIZE, 16); + _lcd.front_buf = rt_malloc_align(LCD_DSI_BUF_SIZE_ROUND, 16); + if (_lcd.lcd_info.framebuffer == RT_NULL || _lcd.front_buf == RT_NULL) + { + LOG_E("init frame buffer failed!\n"); + result = -RT_ENOMEM; + goto __exit; + } + + /* memset buff to 0xFF */ + memset(_lcd.lcd_info.framebuffer, 0xFF, LCD_DSI_BUF_SIZE); + memset(_lcd.front_buf, 0xFF, LCD_DSI_BUF_SIZE_ROUND); + + device->type = RT_Device_Class_Graphic; +#ifdef RT_USING_DEVICE_OPS + device->ops = &lcd_ops; +#else + device->init = drv_lcd_init; + device->control = drv_lcd_control; +#endif + + /* register lcd device */ + rt_device_register(device, "lcd_dsi", RT_DEVICE_FLAG_RDWR); + + /* init stm32 LTDC */ + if (stm32_lcd_init(&_lcd) != RT_EOK) + { + result = -RT_ERROR; + goto __exit; + } + else + { + turn_on_lcd_backlight(); + } + +__exit: + if (result != RT_EOK) + { + rt_sem_delete(&_lcd.lcd_lock); + + if (_lcd.lcd_info.framebuffer) + { + rt_free(_lcd.lcd_info.framebuffer); + } + + if (_lcd.front_buf) + { + + rt_free(_lcd.front_buf); + } + } + return result; +} +INIT_DEVICE_EXPORT(drv_lcd_hw_init); + +#if defined(PKG_USING_GUIENGINE) + +#include +int graphic_device_init(void) +{ + struct rt_device *device; + device = rt_device_find("lcd_dsi"); + if (device) + { + rtgui_graphic_set_device(device); + } + + return 0; +} +INIT_ENV_EXPORT(graphic_device_init); +#endif + +#ifdef DRV_DEBUG +#ifdef FINSH_USING_MSH +int lcd_dsi_test() +{ + struct drv_lcd_dsi_device *lcd; + lcd = (struct drv_lcd_dsi_device *)rt_device_find("lcd_dsi"); + rt_uint8_t *ptr = lcd->lcd_info.framebuffer; + while (1) + { + /* red */ + for (unsigned long long i = 0; i < LCD_DSI_BUF_SIZE/4; i++) + { + ptr[4 * i] = 0x00; + ptr[4 * i + 1] = 0x00; + ptr[4 * i + 2] = 0xFF; + ptr[4 * i + 3] = 0xFF; + } + rt_device_control(&lcd->parent, RTGRAPHIC_CTRL_RECT_UPDATE, RT_NULL); + rt_thread_mdelay(1000); + + /* green */ + for (int i = 0; i < LCD_DSI_BUF_SIZE/4; i++) + { + ptr[4 * i] = 0x00; + ptr[4 * i + 1] = 0xFF; + ptr[4 * i + 2] = 0x00; + ptr[4 * i + 3] = 0xFF; + } + rt_device_control(&lcd->parent, RTGRAPHIC_CTRL_RECT_UPDATE, RT_NULL); + rt_thread_mdelay(1000); + + /* blue */ + for (int i = 0; i < LCD_DSI_BUF_SIZE/4; i++) + { + ptr[4 * i] = 0xFF; + ptr[4 * i + 1] = 0x00; + ptr[4 * i + 2] = 0x00; + ptr[4 * i + 3] = 0xFF; + } + rt_device_control(&lcd->parent, RTGRAPHIC_CTRL_RECT_UPDATE, RT_NULL); + rt_thread_mdelay(1000); + } +} +MSH_CMD_EXPORT(lcd_dsi_test, lcd_dsi_test); + +//draw a line in screen +void line() +{ + struct drv_lcd_dsi_device *lcd; + lcd = (struct drv_lcd_dsi_device *)rt_device_find("lcd_dsi"); + rt_uint8_t *ptr = lcd->lcd_info.framebuffer; + + /* red */ + for (unsigned long long i = LCD_DSI_BUF_SIZE/4/2; i parent, RTGRAPHIC_CTRL_RECT_UPDATE, RT_NULL); + + +} +MSH_CMD_EXPORT(line, line); + +#endif /* FINSH_USING_MSH */ +#endif /* DRV_DEBUG */ +#endif /* BSP_USING_LCD */ diff --git a/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_sram.c b/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_sram.c new file mode 100644 index 0000000000..f77fa05aee --- /dev/null +++ b/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_sram.c @@ -0,0 +1,163 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-04 zylx first version + */ + +#include +#include +#include + +#ifdef BSP_USING_SRAM +#include + +#define DRV_DEBUG +#define LOG_TAG "drv.sram" +#include + +static SRAM_HandleTypeDef hsram; +static FMC_NORSRAM_TimingTypeDef SRAM_Timing; +#ifdef RT_USING_MEMHEAP_AS_HEAP +static struct rt_memheap system_heap; +#endif + +static int SRAM_Init(void) +{ + int result = RT_EOK; + + /* SRAM device configuration */ + hsram.Instance = FMC_NORSRAM_DEVICE; + hsram.Extended = FMC_NORSRAM_EXTENDED_DEVICE; + + /* SRAM device configuration */ + SRAM_Timing.AddressSetupTime = ADDRESSSETUPTIME; + SRAM_Timing.AddressHoldTime = ADDRESSHOLDTIME; /* Min value, Don't care on SRAM Access mode A */ + SRAM_Timing.DataSetupTime = DATASETUPTIME; + SRAM_Timing.DataHoldTime = DATAHOLDTIME; + SRAM_Timing.BusTurnAroundDuration = BUSTURNAROUNDDURATION; + SRAM_Timing.CLKDivision = CLKDIVISION; /* Min value, Don't care on SRAM Access mode A */ + SRAM_Timing.DataLatency = DATALATENCY; /* Min value, Don't care on SRAM Access mode A */ + SRAM_Timing.AccessMode = ACCESSMODE; + + hsram.Init.NSBank = FMC_NORSRAM_BANK1; + hsram.Init.DataAddressMux = FMC_DATA_ADDRESS_MUX_DISABLE; + hsram.Init.MemoryType = FMC_MEMORY_TYPE_SRAM; +#if SRAM_DATA_WIDTH == 8 + hsram.Init.MemoryDataWidth = FMC_NORSRAM_MEM_BUS_WIDTH_8; +#elif SRAM_DATA_WIDTH == 16 + hsram.Init.MemoryDataWidth = FMC_NORSRAM_MEM_BUS_WIDTH_16; +#else + hsram.Init.MemoryDataWidth = FMC_NORSRAM_MEM_BUS_WIDTH_32; +#endif + hsram.Init.BurstAccessMode = FMC_BURST_ACCESS_MODE_DISABLE; + hsram.Init.WriteOperation = FMC_WRITE_OPERATION_ENABLE; + hsram.Init.WaitSignal = FMC_WAIT_SIGNAL_DISABLE; + hsram.Init.WaitSignalActive = FMC_WAIT_TIMING_BEFORE_WS; + hsram.Init.WaitSignalPolarity = FMC_WAIT_SIGNAL_POLARITY_LOW; + hsram.Init.ExtendedMode = FMC_EXTENDED_MODE_DISABLE; + hsram.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE; + hsram.Init.WriteBurst = FMC_WRITE_BURST_DISABLE; + hsram.Init.ContinuousClock = FMC_CONTINUOUS_CLOCK_SYNC_ONLY; + hsram.Init.WriteFifo = FMC_WRITE_FIFO_DISABLE; + hsram.Init.NBLSetupTime = 0; + hsram.Init.PageSize = FMC_PAGE_SIZE_NONE; + + /* Initialize the SRAM controller */ + if (HAL_SRAM_Init(&hsram, &SRAM_Timing, &SRAM_Timing) != HAL_OK) + { + LOG_E("SRAM init failed!"); + result = -RT_ERROR; + } + else + { + LOG_D("sram init success, mapped at 0x%X, size is %d bytes, data width is %d", SRAM_BANK_ADDR, SRAM_SIZE, SRAM_DATA_WIDTH); +#ifdef RT_USING_MEMHEAP_AS_HEAP + /* If RT_USING_MEMHEAP_AS_HEAP is enabled, SRAM is initialized to the heap */ + rt_memheap_init(&system_heap, "sram", (void *)SRAM_BANK_ADDR, SRAM_SIZE); +#endif + } + + return result; +} +INIT_BOARD_EXPORT(SRAM_Init); + +#ifdef DRV_DEBUG +#ifdef FINSH_USING_MSH +int sram_test(void) +{ + int i = 0; + uint32_t start_time = 0, time_cast = 0; +#if SRAM_DATA_WIDTH == 8 + char data_width = 1; + uint8_t data = 0; + uint8_t *ptr = (uint8_t *)SRAM_BANK_ADDR; +#elif SRAM_DATA_WIDTH == 16 + char data_width = 2; + uint16_t data = 0; + uint16_t *ptr = (uint16_t *)SRAM_BANK_ADDR; +#else + char data_width = 4; + uint32_t data = 0; + uint32_t *ptr = (uint32_t *)SRAM_BANK_ADDR; +#endif + + /* write data */ + LOG_D("Writing the %ld bytes data, waiting....", SRAM_SIZE); + start_time = rt_tick_get(); + for (i = 0; i < SRAM_SIZE / data_width; i++) + { +#if SRAM_DATA_WIDTH == 8 + ((__IO uint8_t *)ptr)[i] = (uint8_t)0x55; +#elif SRAM_DATA_WIDTH == 16 + ((__IO uint16_t *)ptr)[i] = (uint16_t)0x5555; +#else + ((__IO uint32_t *)ptr)[i] = (uint32_t)0x55555555; +#endif + } + time_cast = rt_tick_get() - start_time; + LOG_D("Write data success, total time: %d.%03dS.", time_cast / RT_TICK_PER_SECOND, + time_cast % RT_TICK_PER_SECOND / ((RT_TICK_PER_SECOND * 1 + 999) / 1000)); + + /* read data */ + LOG_D("start Reading and verifying data, waiting...."); + for (i = 0; i < SRAM_SIZE / data_width; i++) + { +#if SRAM_DATA_WIDTH == 8 + data = ((__IO uint8_t *)ptr)[i]; + if (data != 0x55) + { + LOG_E("SRAM test failed!"); + break; + } +#elif SRAM_DATA_WIDTH == 16 + data = ((__IO uint16_t *)ptr)[i]; + if (data != 0x5555) + { + LOG_E("SRAM test failed!"); + break; + } +#else + data = ((__IO uint32_t *)ptr)[i]; + if (data != 0x55555555) + { + LOG_E("SRAM test failed!"); + break; + } +#endif + } + + if (i >= SRAM_SIZE / data_width) + { + LOG_D("SRAM test success!"); + } + + return RT_EOK; +} +MSH_CMD_EXPORT(sram_test, sram test); +#endif /* FINSH_USING_MSH */ +#endif /* DRV_DEBUG */ +#endif /* BSP_USING_SRAM */ diff --git a/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_touch.c b/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_touch.c new file mode 100644 index 0000000000..314b1d707f --- /dev/null +++ b/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_touch.c @@ -0,0 +1,194 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-02-08 Zhangyihong the first version + */ +#include "drv_touch.h" +#include +#ifdef BSP_USING_TOUCH +#ifdef PKG_USING_GUIENGINE +#include +#include +#elif defined(PKG_USING_LITTLEVGL2RTT) +#include +#endif +#define BSP_TOUCH_SAMPLE_HZ (50) + +#define DBG_ENABLE +#define DBG_SECTION_NAME "TOUCH" +#define DBG_LEVEL DBG_ERROR +#define DBG_COLOR +#include + +static rt_list_t driver_list; + + +void rt_touch_drivers_register(touch_drv_t drv) +{ + rt_list_insert_before(&driver_list, &drv->list); +} + +static void post_down_event(rt_uint16_t x, rt_uint16_t y, rt_tick_t ts) +{ +#ifdef PKG_USING_GUIENGINE + struct rtgui_event_mouse emouse; + + emouse.parent.sender = RT_NULL; + emouse.wid = RT_NULL; + + emouse.parent.type = RTGUI_EVENT_MOUSE_BUTTON; + emouse.button = RTGUI_MOUSE_BUTTON_LEFT | RTGUI_MOUSE_BUTTON_DOWN; + emouse.x = x; + emouse.y = y; + emouse.ts = rt_tick_get(); + emouse.id = ts; + rtgui_server_post_event(&emouse.parent, sizeof(emouse)); +#elif defined(PKG_USING_LITTLEVGL2RTT) + littlevgl2rtt_send_input_event(x, y, LITTLEVGL2RTT_INPUT_DOWN); +#endif +} + +static void post_motion_event(rt_uint16_t x, rt_uint16_t y, rt_tick_t ts) +{ +#ifdef PKG_USING_GUIENGINE + struct rtgui_event_mouse emouse; + + emouse.parent.sender = RT_NULL; + emouse.wid = RT_NULL; + + emouse.button = RTGUI_MOUSE_BUTTON_LEFT | RTGUI_MOUSE_BUTTON_DOWN; + emouse.parent.type = RTGUI_EVENT_MOUSE_MOTION; + emouse.x = x; + emouse.y = y; + emouse.ts = rt_tick_get(); + emouse.id = ts; + rtgui_server_post_event(&emouse.parent, sizeof(emouse)); +#elif defined(PKG_USING_LITTLEVGL2RTT) + littlevgl2rtt_send_input_event(x, y, LITTLEVGL2RTT_INPUT_MOVE); +#endif +} + +static void post_up_event(rt_uint16_t x, rt_uint16_t y, rt_tick_t ts) +{ +#ifdef PKG_USING_GUIENGINE + struct rtgui_event_mouse emouse; + + emouse.parent.sender = RT_NULL; + emouse.wid = RT_NULL; + + emouse.parent.type = RTGUI_EVENT_MOUSE_BUTTON; + emouse.button = RTGUI_MOUSE_BUTTON_LEFT | RTGUI_MOUSE_BUTTON_UP; + emouse.x = x; + emouse.y = y; + emouse.ts = rt_tick_get(); + emouse.id = ts; + rtgui_server_post_event(&emouse.parent, sizeof(emouse)); +#elif defined(PKG_USING_LITTLEVGL2RTT) + littlevgl2rtt_send_input_event(x, y, LITTLEVGL2RTT_INPUT_MOVE); +#endif +} + +static void touch_thread_entry(void *parameter) +{ + touch_drv_t touch = (touch_drv_t)parameter; + struct touch_message msg; + rt_tick_t emouse_id = 0; + touch->ops->isr_enable(RT_TRUE); + while (1) + { + + if (rt_sem_take(touch->isr_sem, 10) != RT_EOK) + { + continue; + } + while(touch->ops->read_point(&msg) == RT_EOK) + { + switch (msg.event) + { + case TOUCH_EVENT_UP: + post_up_event(msg.x, msg.y, emouse_id); + break; + case TOUCH_EVENT_DOWN: + emouse_id = rt_tick_get(); + post_down_event(msg.x, msg.y, emouse_id); + break; + case TOUCH_EVENT_MOVE: + post_motion_event(msg.x, msg.y, emouse_id); + break; + default: + break; + } + rt_thread_delay(RT_TICK_PER_SECOND / BSP_TOUCH_SAMPLE_HZ); + } + touch->ops->isr_enable(RT_TRUE); + } +} + +static int rt_touch_driver_init(void) +{ + rt_list_init(&driver_list); + return 0; +} +INIT_BOARD_EXPORT(rt_touch_driver_init); + +static struct rt_i2c_bus_device *i2c_bus = RT_NULL; +static int rt_touch_thread_init(void) +{ + rt_list_t *l; + touch_drv_t current_driver; + rt_thread_t tid = RT_NULL; + i2c_bus = (struct rt_i2c_bus_device *)rt_device_find(BSP_I2C1_NAME); + RT_ASSERT(i2c_bus); + current_driver = RT_NULL; + if (rt_device_open((rt_device_t)i2c_bus, RT_DEVICE_OFLAG_RDWR) != RT_EOK) + return -1; + for (l = driver_list.next; l != &driver_list; l = l->next) + { + if (rt_list_entry(l, struct touch_drivers, list)->probe(i2c_bus)) + { + current_driver = rt_list_entry(l, struct touch_drivers, list); + break; + } + } + if (current_driver == RT_NULL) + { + LOG_E("no touch screen or do not have driver\r\n"); + rt_device_close((rt_device_t)i2c_bus); + return -1; + } + current_driver->ops->init(i2c_bus); + LOG_I("touch screen found driver\r\n"); + tid = rt_thread_create("touch", touch_thread_entry, current_driver, 2048, 27, 20); + if (tid == RT_NULL) + { + current_driver->ops->deinit(); + rt_device_close((rt_device_t)i2c_bus); + return -1; + } + rt_thread_startup(tid); + return 0; +} + +static void touch_init_thread_entry(void *parameter) +{ + rt_touch_thread_init(); +} +static int touc_bg_init(void) +{ + rt_thread_t tid = RT_NULL; + tid = rt_thread_create("touchi", touch_init_thread_entry, RT_NULL, 2048, 28, 20); + if (tid == RT_NULL) + { + return -1; + } + rt_thread_startup(tid); + return 0; +} +INIT_APP_EXPORT(touc_bg_init); + + +#endif diff --git a/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_touch_ft.c b/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_touch_ft.c new file mode 100644 index 0000000000..726be84e0d --- /dev/null +++ b/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_touch_ft.c @@ -0,0 +1,218 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-08-08 Yang the first version + */ + +#include +#include +#include +#include "drv_touch.h" +#include + +#ifdef BSP_USING_TOUCH + +#define DBG_ENABLE +#define DBG_SECTION_NAME "TOUCH.ft" +#define DBG_LEVEL TOUCH_DBG_LEVEL +#define DBG_COLOR +#include + + +#ifdef TOUCH_IC_FT3X67 +#define CHIP_ID_REG 0xA8U +#define CHIP_ID_VALUE 0x11U +#define TOUCH_SLAVE_ADDR 0x38U +#else +#error "Please define at least one TOUCH DEVICE" +/* this driver can be disabled at menuconfig → RT-Thread Components → Device Drivers */ +#endif + +static struct rt_i2c_bus_device *ft_i2c_bus; +static struct touch_drivers ft_driver; + +static int ft_read(struct rt_i2c_bus_device *i2c_bus, rt_uint8_t addr, rt_uint8_t *buffer, rt_size_t length) +{ + int ret = -1; + int retries = 0; + + struct rt_i2c_msg msgs[] = + { + { + .addr = ft_driver.address, + .flags = RT_I2C_WR, + .len = 1, + .buf = &addr, + }, + { + .addr = ft_driver.address, + .flags = RT_I2C_RD, + .len = length, + .buf = buffer, + }, + }; + + while (retries < IIC_RETRY_NUM) + { + ret = rt_i2c_transfer(i2c_bus, msgs, 2); + if (ret == 2)break; + retries++; + } + + if (retries >= IIC_RETRY_NUM) + { + LOG_E("%s i2c read error: %d", __func__, ret); + return -1; + } + + return ret; +} + +static void ft_write(touch_drv_t driver, struct rt_i2c_bus_device *i2c_bus, rt_uint8_t addr, rt_uint8_t *buffer, rt_size_t length) +{ + + rt_uint8_t *send_buffer = rt_malloc(length + 1); + + RT_ASSERT(send_buffer); + + send_buffer[0] = addr; + memcpy(send_buffer + 1, buffer, length); + + struct rt_i2c_msg msgs[] = + { + { + .addr = ft_driver.address, + .flags = RT_I2C_WR, + .len = length + 1, + .buf = send_buffer, + } + }; + + length = rt_i2c_transfer(i2c_bus, msgs, 1); + rt_free(send_buffer); + send_buffer = RT_NULL; +} + +static void ft_isr_enable(rt_bool_t enable) +{ + rt_pin_irq_enable(BSP_TOUCH_INT_PIN, enable); +} + +static void ft_touch_isr(void *parameter) +{ + ft_isr_enable(RT_FALSE); + rt_sem_release(ft_driver.isr_sem); +} + +static rt_err_t ft_read_point(touch_msg_t msg) +{ + int ret = -1; + uint8_t point_num = 0; + static uint8_t s_tp_down = 0; + uint8_t point[6]; + ret = ft_read(ft_i2c_bus, 0x02, &point_num, 1); + if (ret < 0) + { + return RT_ERROR; + } + + if (point_num == 0) + { + if (s_tp_down) + { + s_tp_down = 0; + msg->event = TOUCH_EVENT_UP; + return RT_EOK; + } + msg->event = TOUCH_EVENT_NONE; + return RT_ERROR; + } + + ret = ft_read(ft_i2c_bus, 0x03, point, 6); + if (ret < 0) + { + return RT_ERROR; + } + + msg->y = (point[0]&0x0F) << 8 | point[1]; + msg->x = (point[2]&0x0F) << 8 | point[3]; + if (s_tp_down) + { + msg->event = TOUCH_EVENT_MOVE; + return RT_EOK; + } + msg->event = TOUCH_EVENT_DOWN; + s_tp_down = 1; + + return RT_EOK; +} + +static void ft_init(struct rt_i2c_bus_device *i2c_bus) +{ + if (ft_i2c_bus == RT_NULL) + { + ft_i2c_bus = i2c_bus; + } + ft_driver.isr_sem = rt_sem_create("ft", 0, RT_IPC_FLAG_FIFO); + RT_ASSERT(ft_driver.isr_sem); + + rt_pin_mode(BSP_TOUCH_INT_PIN, PIN_MODE_INPUT_PULLUP); + rt_pin_attach_irq(BSP_TOUCH_INT_PIN, PIN_IRQ_MODE_FALLING, ft_touch_isr, RT_NULL); + + rt_thread_mdelay(200); +} + +static void ft_deinit(void) +{ + if (ft_driver.isr_sem) + { + rt_sem_delete(ft_driver.isr_sem); + ft_driver.isr_sem = RT_NULL; + } +} + +struct touch_ops ft_ops = +{ + ft_isr_enable, + ft_read_point, + ft_init, + ft_deinit, +}; + +static rt_bool_t ft_probe(struct rt_i2c_bus_device *i2c_bus) +{ + int err = 0; + uint8_t cid = 0xFF; + + ft_i2c_bus = i2c_bus; + err = ft_read(ft_i2c_bus, CHIP_ID_REG, (uint8_t *)&cid, 1); + if (err < 0) + { + LOG_E("%s failed: %d", __func__, err); + return RT_FALSE; + } + LOG_I("touch CID:%02X", cid); + if(cid == CHIP_ID_VALUE) + { + return RT_TRUE; + } + return RT_FALSE; +} + +int ft_driver_register(void) +{ + ft_driver.address = TOUCH_SLAVE_ADDR; + ft_driver.probe = ft_probe; + ft_driver.ops = &ft_ops; + ft_driver.user_data = RT_NULL; + rt_touch_drivers_register(&ft_driver); + return 0; +} + +INIT_DEVICE_EXPORT(ft_driver_register); + +#endif diff --git a/bsp/stm32/stm32l4r9-st-eval/board/ports/include/drv_touch.h b/bsp/stm32/stm32l4r9-st-eval/board/ports/include/drv_touch.h new file mode 100644 index 0000000000..0e0cfae502 --- /dev/null +++ b/bsp/stm32/stm32l4r9-st-eval/board/ports/include/drv_touch.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-02-08 Zhangyihong the first version + */ +#ifndef __DRV_TOUCH_H__ +#define __DRV_TOUCH_H__ + +#include "rtthread.h" +#include "rtdevice.h" + +#define TOUCH_DBG_LEVEL DBG_ERROR + +#define IIC_RETRY_NUM 2 + +#define TOUCH_EVENT_UP (0x01) +#define TOUCH_EVENT_DOWN (0x02) +#define TOUCH_EVENT_MOVE (0x03) +#define TOUCH_EVENT_NONE (0x80) + +struct touch_message +{ + rt_uint16_t x; + rt_uint16_t y; + rt_uint8_t event; +}; +typedef struct touch_message *touch_msg_t; + +struct touch_ops +{ + void (* isr_enable)(rt_bool_t); + rt_err_t (* read_point)(touch_msg_t); + void (* init)(struct rt_i2c_bus_device *); + void (* deinit)(void); +}; +typedef struct touch_ops *touch_ops_t; + +struct touch_drivers +{ + rt_list_t list; + unsigned char address; + rt_bool_t (*probe)(struct rt_i2c_bus_device *i2c_bus); + rt_sem_t isr_sem; + touch_ops_t ops; + void *user_data; +}; +typedef struct touch_drivers *touch_drv_t; + +extern void rt_touch_drivers_register(touch_drv_t drv); +#endif diff --git a/bsp/stm32/stm32l4r9-st-eval/board/ports/include/lcd_port_dsi.h b/bsp/stm32/stm32l4r9-st-eval/board/ports/include/lcd_port_dsi.h new file mode 100644 index 0000000000..fbc56b4a44 --- /dev/null +++ b/bsp/stm32/stm32l4r9-st-eval/board/ports/include/lcd_port_dsi.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-01-08 zylx first version + */ + +#ifndef __LCD_PORT_DSI_H__ +#define __LCD_PORT_DSI_H__ + +#define LCD_HEIGHT 390 +#define LCD_WIDTH 390 +#define LCD_BITS_PER_PIXEL 24 +#define LCD_PIXEL_FORMAT RTGRAPHIC_PIXEL_FORMAT_ARGB888 +#define LCD_DSI_BUF_SIZE 608400 +#define LCD_DSI_BUF_SIZE_ROUND 365040 + +#define LAYER_ADDRESS GFXMMU_VIRTUAL_BUFFER0_BASE +#define BRIGHTNESS_MIN 50 +#define BRIGHTNESS_NORMAL 200 + +#define LCD_BACKLIGHT_USING_GPIO +#define LCD_BL_GPIO_NUM GET_PIN(B, 14) + +#endif /* __LCD_PORT_DSI_H__ */ diff --git a/bsp/stm32/stm32l4r9-st-eval/board/ports/include/sram_port.h b/bsp/stm32/stm32l4r9-st-eval/board/ports/include/sram_port.h new file mode 100644 index 0000000000..a5d89f1d80 --- /dev/null +++ b/bsp/stm32/stm32l4r9-st-eval/board/ports/include/sram_port.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-04 zylx The first version for STM32F4xx + */ + +#ifndef __SDRAM_PORT_H__ +#define __SDRAM_PORT_H__ + +/* parameters for sdram peripheral */ +/* Bank1 */ +#define SRAM_TARGET_BANK 1 +/* stm32f4 Bank1:0x60000000 */ +#define SRAM_BANK_ADDR ((uint32_t)0x60000000) +/* data width: 8, 16, 32 */ +#define SRAM_DATA_WIDTH 16 +/* sram size */ +#define SRAM_SIZE ((uint32_t)0x200000) + +/* Timing configuration for IS61WV102416BLL-10MLI */ +#define ADDRESSSETUPTIME 2 +#define ADDRESSHOLDTIME 1 +#define DATASETUPTIME 1 +#define DATAHOLDTIME 1 +#define BUSTURNAROUNDDURATION 0 +#define CLKDIVISION 2 +#define DATALATENCY 2 +#define ACCESSMODE FMC_ACCESS_MODE_A +/* Timing configuration for IS61WV102416BLL-10MLI */ + +#endif diff --git a/bsp/stm32/stm32l4r9-st-eval/project.uvoptx b/bsp/stm32/stm32l4r9-st-eval/project.uvoptx index 58e01bfff9..d8f3ae1d5a 100644 --- a/bsp/stm32/stm32l4r9-st-eval/project.uvoptx +++ b/bsp/stm32/stm32l4r9-st-eval/project.uvoptx @@ -73,7 +73,7 @@ 0 - 1 + 0 0 1 @@ -117,26 +117,6 @@ STLink\ST-LINKIII-KEIL_SWO.dll - - 0 - ARMRTXEVENTFLAGS - -L70 -Z18 -C0 -M0 -T1 - - - 0 - DLGTARM - (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) - - - 0 - ARMDBGFLAGS - - - - 0 - DLGUARM - (105=-1,-1,-1,-1,0) - 0 UL2CM3 @@ -145,7 +125,7 @@ 0 ST-LINKIII-KEIL_SWO - -U0668FF504955857567074018 -O206 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P2 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32L4Rx_2048.FLM -FS08000000 -FL0200000 -FP0($$Device:STM32L4R9AIIx$CMSIS\Flash\STM32L4Rx_2048.FLM) + -U0668FF504955857567074018 -O206 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P2 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO31 -FD20000000 -FC1000 -FN1 -FF0STM32L4Rx_2048.FLM -FS08000000 -FL0200000 -FP0($$Device:STM32L4R9AIIx$CMSIS\Flash\STM32L4Rx_2048.FLM) @@ -155,12 +135,12 @@ 0 0 - 1 + 0 0 0 0 0 - 1 + 0 0 0 0 @@ -310,8 +290,8 @@ 0 0 0 - ..\..\..\src\mem.c - mem.c + ..\..\..\src\memheap.c + memheap.c 0 0 @@ -411,7 +391,7 @@ Drivers - 1 + 0 0 0 0 @@ -570,6 +550,42 @@ 0 0 0 + ..\..\..\components\drivers\i2c\i2c_core.c + i2c_core.c + 0 + 0 + + + 5 + 29 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\i2c\i2c_dev.c + i2c_dev.c + 0 + 0 + + + 5 + 30 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\i2c\i2c-bit-ops.c + i2c-bit-ops.c + 0 + 0 + + + 5 + 31 + 1 + 0 + 0 + 0 ..\..\..\components\drivers\misc\pin.c pin.c 0 @@ -577,7 +593,7 @@ 5 - 29 + 32 1 0 0 @@ -589,7 +605,7 @@ 5 - 30 + 33 1 0 0 @@ -601,7 +617,7 @@ 5 - 31 + 34 1 0 0 @@ -613,7 +629,7 @@ 5 - 32 + 35 1 0 0 @@ -625,7 +641,7 @@ 5 - 33 + 36 1 0 0 @@ -637,7 +653,7 @@ 5 - 34 + 37 1 0 0 @@ -649,7 +665,7 @@ 5 - 35 + 38 1 0 0 @@ -661,7 +677,7 @@ 5 - 36 + 39 1 0 0 @@ -681,7 +697,7 @@ 0 6 - 37 + 40 1 0 0 @@ -693,7 +709,7 @@ 6 - 38 + 41 1 0 0 @@ -705,7 +721,7 @@ 6 - 39 + 42 1 0 0 @@ -717,7 +733,7 @@ 6 - 40 + 43 1 0 0 @@ -729,7 +745,7 @@ 6 - 41 + 44 1 0 0 @@ -741,7 +757,7 @@ 6 - 42 + 45 1 0 0 @@ -761,7 +777,7 @@ 0 7 - 43 + 46 1 0 0 @@ -773,7 +789,7 @@ 7 - 44 + 47 1 0 0 @@ -785,7 +801,7 @@ 7 - 45 + 48 1 0 0 @@ -797,7 +813,7 @@ 7 - 46 + 49 1 0 0 @@ -809,7 +825,7 @@ 7 - 47 + 50 1 0 0 @@ -821,7 +837,7 @@ 7 - 48 + 51 1 0 0 @@ -833,7 +849,7 @@ 7 - 49 + 52 1 0 0 @@ -845,7 +861,7 @@ 7 - 50 + 53 1 0 0 @@ -857,7 +873,7 @@ 7 - 51 + 54 1 0 0 @@ -869,7 +885,7 @@ 7 - 52 + 55 1 0 0 @@ -881,7 +897,7 @@ 7 - 53 + 56 1 0 0 @@ -893,7 +909,7 @@ 7 - 54 + 57 1 0 0 @@ -905,7 +921,7 @@ 7 - 55 + 58 1 0 0 @@ -917,7 +933,7 @@ 7 - 56 + 59 1 0 0 @@ -929,7 +945,7 @@ 7 - 57 + 60 1 0 0 @@ -941,7 +957,7 @@ 7 - 58 + 61 1 0 0 @@ -953,19 +969,7 @@ 7 - 59 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_sram.c - stm32l4xx_hal_sram.c - 0 - 0 - - - 7 - 60 + 62 1 0 0 @@ -977,7 +981,7 @@ 7 - 61 + 63 1 0 0 @@ -989,7 +993,7 @@ 7 - 62 + 64 1 0 0 @@ -1001,7 +1005,7 @@ 7 - 63 + 65 1 0 0 @@ -1013,7 +1017,7 @@ 7 - 64 + 66 1 0 0 @@ -1023,6 +1027,30 @@ 0 0 + + 7 + 67 + 1 + 0 + 0 + 0 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c.c + stm32l4xx_hal_i2c.c + 0 + 0 + + + 7 + 68 + 1 + 0 + 0 + 0 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c_ex.c + stm32l4xx_hal_i2c_ex.c + 0 + 0 + diff --git a/bsp/stm32/stm32l4r9-st-eval/project.uvprojx b/bsp/stm32/stm32l4r9-st-eval/project.uvprojx index cf0b8e1ce0..16152353be 100644 --- a/bsp/stm32/stm32l4r9-st-eval/project.uvprojx +++ b/bsp/stm32/stm32l4r9-st-eval/project.uvprojx @@ -49,7 +49,7 @@ 1 .\build\keil\Obj\ - rt-thread + rtthread 1 0 0 @@ -338,7 +338,7 @@ USE_HAL_DRIVER, STM32L4R9xx - .;..\..\..\include;applications\E;applications\:;..\..\..\..;applications\r;applications\t;applications\-;applications\t;applications\h;applications\r;applications\e;applications\a;applications\d;..\..\..\..;applications\b;applications\s;applications\p;..\..\..\..;applications\s;applications\t;applications\m;applications\3;applications\2;..\..\..\..;applications\s;applications\t;applications\m;applications\3;applications\2;applications\l;applications\4;applications\r;applications\9;applications\-;applications\s;applications\t;applications\-;applications\e;applications\v;applications\a;applications\l;..\..\..\..;applications\a;applications\p;applications\p;applications\l;applications\i;applications\c;applications\a;applications\t;applications\i;applications\o;applications\n;applications\s;board;board\CubeMX_Config\Inc;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Inc;..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Include;..\libraries\STM32L4xx_HAL\CMSIS\Include + .;..\..\..\include;applications;board;board\CubeMX_Config\Inc;board\ports\include;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Inc;..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Include;..\libraries\STM32L4xx_HAL\CMSIS\Include @@ -423,9 +423,9 @@ ..\..\..\src\kservice.c - mem.c + memheap.c 1 - ..\..\..\src\mem.c + ..\..\..\src\memheap.c mempool.c @@ -537,6 +537,21 @@ DeviceDrivers + + i2c_core.c + 1 + ..\..\..\components\drivers\i2c\i2c_core.c + + + i2c_dev.c + 1 + ..\..\..\components\drivers\i2c\i2c_dev.c + + + i2c-bit-ops.c + 1 + ..\..\..\components\drivers\i2c\i2c-bit-ops.c + pin.c 1 @@ -702,11 +717,6 @@ 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rng.c - - stm32l4xx_hal_sram.c - 1 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_sram.c - stm32l4xx_hal_gpio.c 1 @@ -732,6 +742,16 @@ 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_usart_ex.c + + stm32l4xx_hal_i2c.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c.c + + + stm32l4xx_hal_i2c_ex.c + 1 + ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c_ex.c + diff --git a/bsp/stm32/stm32l4r9-st-eval/rtconfig.h b/bsp/stm32/stm32l4r9-st-eval/rtconfig.h index 0b2087cb58..985a57e64d 100644 --- a/bsp/stm32/stm32l4r9-st-eval/rtconfig.h +++ b/bsp/stm32/stm32l4r9-st-eval/rtconfig.h @@ -30,7 +30,8 @@ /* Memory Management */ #define RT_USING_MEMPOOL -#define RT_USING_SMALL_MEM +#define RT_USING_MEMHEAP +#define RT_USING_MEMHEAP_AS_HEAP #define RT_USING_HEAP /* Kernel Device Object */ @@ -80,6 +81,8 @@ #define RT_USING_SERIAL #define RT_SERIAL_USING_DMA #define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_I2C +#define RT_USING_I2C_BITOPS #define RT_USING_PIN /* Using WiFi */ @@ -96,6 +99,9 @@ /* Socket abstraction layer */ +/* Network interface device */ + + /* light weight TCP/IP stack */ @@ -113,11 +119,6 @@ /* RT-Thread online packages */ -/* system packages */ - -/* RT-Thread GUI Engine */ - - /* IoT - internet of things */ @@ -129,6 +130,9 @@ /* Wiced WiFi */ +/* IoT Cloud */ + + /* security packages */ @@ -141,10 +145,16 @@ /* tools packages */ +/* system packages */ + + +/* peripheral libraries and drivers */ + + /* miscellaneous packages */ -/* example package: hello */ +/* samples: kernel and components samples */ #define SOC_FAMILY_STM32 #define SOC_SERIES_STM32L4 @@ -155,6 +165,11 @@ /* Onboard Peripheral Drivers */ +#define BSP_USING_STLINK_TO_USART + +/* Enable Touch */ + + /* On-chip Peripheral Drivers */ #define BSP_USING_GPIO diff --git a/bsp/stm32/stm32l4r9-st-eval/template.uvoptx b/bsp/stm32/stm32l4r9-st-eval/template.uvoptx index de630d9118..ca63bbdf5f 100644 --- a/bsp/stm32/stm32l4r9-st-eval/template.uvoptx +++ b/bsp/stm32/stm32l4r9-st-eval/template.uvoptx @@ -125,7 +125,7 @@ 0 ST-LINKIII-KEIL_SWO - -U0668FF504955857567074018 -O206 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P2 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32L4Rx_2048 -FS08000000 -FL0200000 -FP0($$Device:STM32L4R9AIIx$CMSIS\Flash\STM32L4Rx_2048.FLM) + -U0668FF504955857567074018 -O206 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P2 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO31 -FD20000000 -FC1000 -FN1 -FF0STM32L4Rx_2048.FLM -FS08000000 -FL0200000 -FP0($$Device:STM32L4R9AIIx$CMSIS\Flash\STM32L4Rx_2048.FLM) diff --git a/bsp/stm32/stm32l4r9-st-eval/template.uvprojx b/bsp/stm32/stm32l4r9-st-eval/template.uvprojx index a306fd3265..ed79259e7d 100644 --- a/bsp/stm32/stm32l4r9-st-eval/template.uvprojx +++ b/bsp/stm32/stm32l4r9-st-eval/template.uvprojx @@ -49,7 +49,7 @@ 1 .\build\keil\Obj\ - rt-thread + rtthread 1 0 0 diff --git a/bsp/swm320-lq100/drivers/board.h b/bsp/swm320-lq100/drivers/board.h index 702ef43e75..a754b5b8d1 100644 --- a/bsp/swm320-lq100/drivers/board.h +++ b/bsp/swm320-lq100/drivers/board.h @@ -24,7 +24,7 @@ #endif #define SRAM_END (SRAM_BASE + SRAM_SIZE) -#ifdef __CC_ARM +#if defined(__CC_ARM) || defined(__CLANG_ARM) extern int Image$$RW_IRAM1$$ZI$$Limit; #define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) #elif __ICCARM__ diff --git a/components/drivers/include/drivers/pm.h b/components/drivers/include/drivers/pm.h index 94d4c8559b..e35b21cd48 100644 --- a/components/drivers/include/drivers/pm.h +++ b/components/drivers/include/drivers/pm.h @@ -7,6 +7,7 @@ * Date Author Notes * 2012-06-02 Bernard the first version * 2018-08-02 Tanek split run and sleep modes, support custom mode + * 2019-04-28 Zero-Free improve PM mode and device ops interface */ #ifndef __PM_H__ @@ -16,96 +17,67 @@ #ifndef PM_HAS_CUSTOM_CONFIG -/* All modes used for rt_pm_request() adn rt_pm_release() */ +/* All modes used for rt_pm_request() and rt_pm_release() */ enum { - /* run modes */ - PM_RUN_MODE_NORMAL = 0, - /* sleep modes */ - PM_SLEEP_MODE_SLEEP, - PM_SLEEP_MODE_TIMER, + PM_SLEEP_MODE_NONE = 0, + PM_SLEEP_MODE_IDLE, + PM_SLEEP_MODE_LIGHT, + PM_SLEEP_MODE_DEEP, + PM_SLEEP_MODE_STANDBY, PM_SLEEP_MODE_SHUTDOWN, + PM_SLEEP_MODE_MAX, }; +enum +{ + /* run modes*/ + PM_RUN_MODE_HIGH_SPEED = 0, + PM_RUN_MODE_NORMAL_SPEED, + PM_RUN_MODE_MEDIUM_SPEED, + PM_RUN_MODE_LOW_SPEED, + PM_RUN_MODE_MAX, +}; + +enum +{ + RT_PM_FREQUENCY_PENDING = 0x01, +}; + +#define RT_PM_DEFAULT_SLEEP_MODE PM_SLEEP_MODE_IDLE +#define RT_PM_DEFAULT_RUN_MODE PM_RUN_MODE_NORMAL_SPEED + /* The name of all modes used in the msh command "pm_dump" */ -#define PM_MODE_NAMES \ +#define PM_SLEEP_MODE_NAMES \ { \ - "Running Mode", \ - \ - "Sleep Mode", \ - "Timer Mode", \ + "None Mode", \ + "Idle Mode", \ + "LightSleep Mode", \ + "DeepSleep Mode", \ + "Standby Mode", \ "Shutdown Mode", \ } -/* run mode count : 1 */ -#define PM_RUN_MODE_COUNT 1 -/* sleep mode count : 3 */ -#define PM_SLEEP_MODE_COUNT 3 - -/* support redefining default run mode */ -#ifndef PM_RUN_MODE_DEFAULT -#define PM_RUN_MODE_DEFAULT 0 -#endif - -/* support redefining default sleep mode */ -#ifndef PM_SLEEP_MODE_DEFAULT -#define PM_SLEEP_MODE_DEFAULT (PM_SLEEP_MODE_START) -#endif - -/* support redefining the minimum tick into sleep mode */ -#ifndef PM_MIN_ENTER_SLEEP_TICK -#define PM_MIN_ENTER_SLEEP_TICK (1) -#endif +#define PM_RUN_MODE_NAMES \ +{ \ + "High Speed", \ + "Normal Speed", \ + "Medium Speed", \ + "Low Mode", \ +} #else /* PM_HAS_CUSTOM_CONFIG */ #include -#ifndef PM_RUN_MODE_COUNT -#error "You must defined PM_RUN_MODE_COUNT on pm_cfg.h" -#endif - -#ifndef PM_SLEEP_MODE_COUNT -#error "You must defined PM_SLEEP_MODE_COUNT on pm_cfg.h" -#endif - -#ifndef PM_MODE_DEFAULT -#error "You must defined PM_MODE_DEFAULT on pm_cfg.h" -#endif - -#ifndef PM_MODE_NAMES -#error "You must defined PM_MODE_NAMES on pm_cfg.h" -#endif - -#ifndef PM_RUN_MODE_DEFAULT -#error "You must defined PM_RUN_MODE_DEFAULT on pm_cfg.h" -#endif - -/* The default sleep mode(PM_SLEEP_MODE_DEFAULT) are not required. - * If the default mode is defined, it is requested once in rt_system_pm_init() - */ - #endif /* PM_HAS_CUSTOM_CONFIG */ -/* run mode must start at 0 */ -#define PM_RUN_MODE_START 0 -/* the values of the run modes and sleep mode must be consecutive */ -#define PM_SLEEP_MODE_START PM_RUN_MODE_COUNT -/* all mode count */ -#define PM_MODE_COUNT (PM_RUN_MODE_COUNT + PM_SLEEP_MODE_COUNT) -/* The last mode, will be request in rt_system_pm_init() */ -#define PM_MODE_MAX (PM_RUN_MODE_COUNT + PM_SLEEP_MODE_COUNT - 1) - -#if PM_MODE_COUNT > 32 -#error "The number of modes cannot exceed 32" -#endif - /** * device control flag to request or release power */ #define RT_PM_DEVICE_CTRL_REQUEST 0x01 -#define RT_PM_DEVICE_CTRL_RELEASE 0x02 +#define RT_PM_DEVICE_CTRL_RELEASE 0x00 struct rt_pm; @@ -114,13 +86,8 @@ struct rt_pm; */ struct rt_pm_ops { - void (*enter)(struct rt_pm *pm); - void (*exit)(struct rt_pm *pm); - -#if PM_RUN_MODE_COUNT > 1 - void (*frequency_change)(struct rt_pm *pm, rt_uint32_t frequency); -#endif - + void (*sleep)(struct rt_pm *pm, uint8_t mode); + void (*run)(struct rt_pm *pm, uint8_t mode); void (*timer_start)(struct rt_pm *pm, rt_uint32_t timeout); void (*timer_stop)(struct rt_pm *pm); rt_tick_t (*timer_get_tick)(struct rt_pm *pm); @@ -128,18 +95,15 @@ struct rt_pm_ops struct rt_device_pm_ops { -#if PM_RUN_MODE_COUNT > 1 - void (*frequency_change)(const struct rt_device* device); -#endif - - void (*suspend)(const struct rt_device* device); - void (*resume) (const struct rt_device* device); + int (*suspend)(const struct rt_device *device, uint8_t mode); + void (*resume)(const struct rt_device *device, uint8_t mode); + int (*frequency_change)(const struct rt_device *device, uint8_t mode); }; struct rt_device_pm { - const struct rt_device* device; - const struct rt_device_pm_ops* ops; + const struct rt_device *device; + const struct rt_device_pm_ops *ops; }; /** @@ -150,32 +114,45 @@ struct rt_pm struct rt_device parent; /* modes */ - rt_uint8_t modes[PM_MODE_COUNT]; - rt_uint8_t current_mode; /* current pm mode */ - rt_uint8_t exit_count; + rt_uint8_t modes[PM_SLEEP_MODE_MAX]; + rt_uint8_t sleep_mode; /* current sleep mode */ + rt_uint8_t run_mode; /* current running mode */ /* the list of device, which has PM feature */ rt_uint8_t device_pm_number; - struct rt_device_pm* device_pm; - struct rt_semaphore device_lock; + struct rt_device_pm *device_pm; /* if the mode has timer, the corresponding bit is 1*/ - rt_uint32_t timer_mask; + rt_uint8_t timer_mask; + rt_uint8_t flags; const struct rt_pm_ops *ops; }; -void rt_pm_enter(void); -void rt_pm_exit(void); +enum +{ + RT_PM_ENTER_SLEEP = 0, + RT_PM_EXIT_SLEEP, +}; -void rt_pm_request(rt_ubase_t mode); -void rt_pm_release(rt_ubase_t mode); +struct rt_pm_notify +{ + void (*notify)(uint8_t event, uint8_t mode, void *data); + void *data; +}; -void rt_pm_register_device(struct rt_device* device, const struct rt_device_pm_ops* ops); -void rt_pm_unregister_device(struct rt_device* device); +void rt_pm_request(uint8_t sleep_mode); +void rt_pm_release(uint8_t sleep_mode); +int rt_pm_run_enter(uint8_t run_mode); + +void rt_pm_device_register(struct rt_device *device, const struct rt_device_pm_ops *ops); +void rt_pm_device_unregister(struct rt_device *device); + +void rt_pm_notify_set(void (*notify)(uint8_t event, uint8_t mode, void *data), void *data); +void rt_pm_default_set(uint8_t sleep_mode); void rt_system_pm_init(const struct rt_pm_ops *ops, - rt_uint8_t timer_mask, - void *user_data); + uint8_t timer_mask, + void *user_data); #endif /* __PM_H__ */ diff --git a/components/drivers/include/ipc/workqueue.h b/components/drivers/include/ipc/workqueue.h index 31dbb53ee3..354a30c04e 100644 --- a/components/drivers/include/ipc/workqueue.h +++ b/components/drivers/include/ipc/workqueue.h @@ -74,6 +74,8 @@ rt_inline void rt_work_init(struct rt_work *work, void (*work_func)(struct rt_wo rt_list_init(&(work->list)); work->work_func = work_func; work->work_data = work_data; + work->flags = 0; + work->type = 0; } void rt_delayed_work_init(struct rt_delayed_work *work, void (*work_func)(struct rt_work *work, diff --git a/components/drivers/pm/pm.c b/components/drivers/pm/pm.c index c300414444..3e9cf56c76 100644 --- a/components/drivers/pm/pm.c +++ b/components/drivers/pm/pm.c @@ -7,6 +7,7 @@ * Date Author Notes * 2012-06-02 Bernard the first version * 2018-08-02 Tanek split run and sleep modes, support custom mode + * 2019-04-28 Zero-Free improve PM mode and device ops interface */ #include @@ -16,27 +17,46 @@ #ifdef RT_USING_PM static struct rt_pm _pm; +static uint8_t _pm_default_sleep = RT_PM_DEFAULT_SLEEP_MODE; +static struct rt_pm_notify _pm_notify; +static uint8_t _pm_init_flag = 0; + +#define RT_PM_TICKLESS_THRESH (2) + +RT_WEAK uint32_t rt_pm_enter_critical(uint8_t sleep_mode) +{ + return rt_hw_interrupt_disable(); +} + +RT_WEAK void rt_pm_exit_critical(uint32_t ctx, uint8_t sleep_mode) +{ + rt_hw_interrupt_enable(ctx); +} /** * This function will suspend all registered devices */ -static void _pm_device_suspend(void) +static int _pm_device_suspend(uint8_t mode) { - int index; + int index, ret = RT_EOK; for (index = 0; index < _pm.device_pm_number; index++) { if (_pm.device_pm[index].ops->suspend != RT_NULL) { - _pm.device_pm[index].ops->suspend(_pm.device_pm[index].device); + ret = _pm.device_pm[index].ops->suspend(_pm.device_pm[index].device, mode); + if(ret != RT_EOK) + break; } } + + return ret; } /** * This function will resume all registered devices */ -static void _pm_device_resume(void) +static void _pm_device_resume(uint8_t mode) { int index; @@ -44,16 +64,15 @@ static void _pm_device_resume(void) { if (_pm.device_pm[index].ops->resume != RT_NULL) { - _pm.device_pm[index].ops->resume(_pm.device_pm[index].device); + _pm.device_pm[index].ops->resume(_pm.device_pm[index].device, mode); } } } -#if PM_RUN_MODE_COUNT > 1 /** * This function will update the frequency of all registered devices */ -static void _pm_device_frequency_change(void) +static void _pm_device_frequency_change(uint8_t mode) { rt_uint32_t index; @@ -61,152 +80,151 @@ static void _pm_device_frequency_change(void) for (index = 0; index < _pm.device_pm_number; index ++) { if (_pm.device_pm[index].ops->frequency_change != RT_NULL) - _pm.device_pm[index].ops->frequency_change(_pm.device_pm[index].device); + _pm.device_pm[index].ops->frequency_change(_pm.device_pm[index].device, mode); + } +} + +/** + * This function will update the system clock frequency when idle + */ +static void _pm_frequency_scaling(struct rt_pm *pm) +{ + rt_base_t level; + + if (pm->flags & RT_PM_FREQUENCY_PENDING) + { + level = rt_hw_interrupt_disable(); + /* change system runing mode */ + pm->ops->run(pm, pm->run_mode); + /* changer device frequency */ + _pm_device_frequency_change(pm->run_mode); + pm->flags &= ~RT_PM_FREQUENCY_PENDING; + rt_hw_interrupt_enable(level); + } +} + +/** + * This function selects the sleep mode according to the rt_pm_request/rt_pm_release count. + */ +static uint8_t _pm_select_sleep_mode(struct rt_pm *pm) +{ + int index; + uint8_t mode; + + mode = _pm_default_sleep; + for (index = PM_SLEEP_MODE_NONE; index < PM_SLEEP_MODE_MAX; index ++) + { + if (pm->modes[index]) + { + mode = index; + break; + } + } + pm->sleep_mode = mode; + + return mode; +} + +/** + * This function changes the power sleep mode base on the result of selection + */ +static void _pm_change_sleep_mode(struct rt_pm *pm, uint8_t mode) +{ + rt_tick_t timeout_tick, delta_tick; + rt_base_t level; + int ret = RT_EOK; + + if (mode == PM_SLEEP_MODE_NONE) + { + pm->sleep_mode = mode; + pm->ops->sleep(pm, PM_SLEEP_MODE_NONE); + } + else + { + level = rt_pm_enter_critical(mode); + + /* Notify app will enter sleep mode */ + if (_pm_notify.notify) + _pm_notify.notify(RT_PM_ENTER_SLEEP, mode, _pm_notify.data); + + /* Suspend all peripheral device */ + ret = _pm_device_suspend(mode); + if (ret != RT_EOK) + { + _pm_device_resume(mode); + if (_pm_notify.notify) + _pm_notify.notify(RT_PM_EXIT_SLEEP, mode, _pm_notify.data); + rt_pm_exit_critical(level, mode); + + return; + } + + /* Tickless*/ + if (pm->timer_mask & (0x01 << mode)) + { + timeout_tick = rt_timer_next_timeout_tick(); + if (timeout_tick == RT_TICK_MAX) + { + if (pm->ops->timer_start) + { + pm->ops->timer_start(pm, RT_TICK_MAX); + } + } + else + { + timeout_tick = timeout_tick - rt_tick_get(); + if (timeout_tick < RT_PM_TICKLESS_THRESH) + { + mode = PM_SLEEP_MODE_IDLE; + } + else + { + pm->ops->timer_start(pm, timeout_tick); + } + } + } + + /* enter lower power state */ + pm->ops->sleep(pm, mode); + + /* wake up from lower power state*/ + if (pm->timer_mask & (0x01 << mode)) + { + delta_tick = pm->ops->timer_get_tick(pm); + pm->ops->timer_stop(pm); + if (delta_tick) + { + rt_tick_set(rt_tick_get() + delta_tick); + rt_timer_check(); + } + } + + /* resume all device */ + _pm_device_resume(pm->sleep_mode); + + if (_pm_notify.notify) + _pm_notify.notify(RT_PM_EXIT_SLEEP, mode, _pm_notify.data); + + rt_pm_exit_critical(level, mode); } } -#endif /** * This function will enter corresponding power mode. */ -void rt_pm_enter(void) +void rt_system_power_manager(void) { - rt_ubase_t level; - struct rt_pm *pm; - rt_uint32_t index; - rt_tick_t timeout_tick; + uint8_t mode; - pm = &_pm; + if (_pm_init_flag == 0) + return; - /* disable interrupt before check run modes */ - level = rt_hw_interrupt_disable(); - /* check each run mode, and decide to swithc to run mode or sleep mode */ - for (index = 0; index < PM_RUN_MODE_COUNT; index++) - { - if (pm->modes[index]) - { - if (index > pm->current_mode) - { - pm->ops->exit(pm); - pm->current_mode = index; - pm->ops->enter(pm); -#if PM_RUN_MODE_COUNT > 1 - pm->ops->frequency_change(pm, 0); - _pm_device_frequency_change(); -#endif - } + /* CPU frequency scaling according to the runing mode settings */ + _pm_frequency_scaling(&_pm); - rt_hw_interrupt_enable(level); - /* The current mode is run mode, no need to check sleep mode */ - return ; - } - } - /* enable interrupt after check run modes */ - rt_hw_interrupt_enable(level); - - level = rt_hw_interrupt_disable(); - /* check each sleep mode to decide which mode can system sleep. */ - for (index = PM_SLEEP_MODE_START; index < PM_SLEEP_MODE_START + PM_SLEEP_MODE_COUNT; index++) - { - if (pm->modes[index]) - { - /* let mcu sleep when system is idle */ - - /* run mode to sleep mode */ - if (pm->current_mode < PM_SLEEP_MODE_START) - { - /* exit run mode */ - pm->ops->exit(pm); - } - - /* set current power mode */ - pm->current_mode = index; - pm->exit_count = 1; - - /* suspend all of devices with PM feature */ - _pm_device_suspend(); - - /* should start pm timer */ - if (pm->timer_mask & (1 << index)) - { - /* get next os tick */ - timeout_tick = rt_timer_next_timeout_tick(); - if (timeout_tick != RT_TICK_MAX) - { - timeout_tick -= rt_tick_get(); - -#if defined(PM_MIN_ENTER_SLEEP_TICK) && PM_MIN_ENTER_SLEEP_TICK > 0 - if (timeout_tick < PM_MIN_ENTER_SLEEP_TICK) - { - rt_hw_interrupt_enable(level); - /* limit the minimum time to enter timer sleep mode */ - return ; - } -#endif - } - /* startup pm timer */ - pm->ops->timer_start(pm, timeout_tick); - } - - /* enter sleep and wait to be waken up */ - pm->ops->enter(pm); - - /* exit from low power mode */ - rt_pm_exit(); - - rt_hw_interrupt_enable(level); - return ; - } - } - - rt_hw_interrupt_enable(level); -} - -/** - * This function exits from sleep mode. - */ -void rt_pm_exit(void) -{ - rt_ubase_t level; - struct rt_pm *pm; - rt_tick_t delta_tick; - - pm = &_pm; - - level = rt_hw_interrupt_disable(); - - if (pm->exit_count) - { - pm->exit_count = 0; - - if (pm->current_mode >= PM_SLEEP_MODE_START) - { - /* sleep mode with timer */ - if (pm->timer_mask & (1 << pm->current_mode)) - { - /* get the tick of pm timer */ - delta_tick = pm->ops->timer_get_tick(pm); - - /* stop pm timer */ - pm->ops->timer_stop(pm); - - if (delta_tick) - { - /* adjust OS tick */ - rt_tick_set(rt_tick_get() + delta_tick); - /* check system timer */ - rt_timer_check(); - } - } - - /* exit from sleep mode */ - pm->ops->exit(pm); - /* resume the device with PM feature */ - _pm_device_resume(); - } - } - - rt_hw_interrupt_enable(level); + /* Low Power Mode Processing */ + mode = _pm_select_sleep_mode(&_pm); + _pm_change_sleep_mode(&_pm, mode); } /** @@ -215,60 +233,21 @@ void rt_pm_exit(void) * * @param parameter the parameter of run mode or sleep mode */ -void rt_pm_request(rt_ubase_t mode) +void rt_pm_request(uint8_t mode) { - rt_ubase_t level; + rt_base_t level; struct rt_pm *pm; - pm = &_pm; + if (_pm_init_flag == 0) + return; - if (mode > PM_MODE_MAX) + if (mode > (PM_SLEEP_MODE_MAX - 1)) return; level = rt_hw_interrupt_disable(); - - /* update pm modes table */ - pm->modes[mode] ++; - - /* request higter mode with a smaller mode value*/ - if (mode < pm->current_mode) - { - /* the old current mode is RUN mode, need to all pm->ops->exit(), - * if not, it has already called in rt_pm_exit() - */ - if (pm->current_mode < PM_SLEEP_MODE_START) - { - pm->ops->exit(pm); - } - else if (pm->exit_count) - { - /* call exeit when global interrupt is disable */ - pm->ops->exit(pm); - pm->exit_count = 0; - } - - /* update current mode */ - pm->current_mode = mode; - - /* current mode is higher run mode */ - if (mode < PM_SLEEP_MODE_START) - { - /* enter run mode */ - pm->ops->enter(pm); -#if PM_RUN_MODE_COUNT > 1 - /* frequency change */ - pm->ops->frequency_change(pm, 0); - _pm_device_frequency_change(); -#endif - } - else - { - /* do nothing when request higher sleep mode, - * and swithc to new sleep mode in rt_pm_enter() - */ - } - } - + pm = &_pm; + if (pm->modes[mode] < 255) + pm->modes[mode] ++; rt_hw_interrupt_enable(level); } @@ -279,21 +258,21 @@ void rt_pm_request(rt_ubase_t mode) * @param parameter the parameter of run mode or sleep mode * */ -void rt_pm_release(rt_ubase_t mode) +void rt_pm_release(uint8_t mode) { rt_ubase_t level; struct rt_pm *pm; - pm = &_pm; + if (_pm_init_flag == 0) + return; - if (mode > PM_MODE_MAX) + if (mode > (PM_SLEEP_MODE_MAX - 1)) return; level = rt_hw_interrupt_disable(); - + pm = &_pm; if (pm->modes[mode] > 0) pm->modes[mode] --; - rt_hw_interrupt_enable(level); } @@ -303,9 +282,9 @@ void rt_pm_release(rt_ubase_t mode) * @param device the device with PM feature * @param ops the PM ops for device */ -void rt_pm_register_device(struct rt_device *device, const struct rt_device_pm_ops *ops) +void rt_pm_device_register(struct rt_device *device, const struct rt_device_pm_ops *ops) { - rt_ubase_t level; + rt_base_t level; struct rt_device_pm *device_pm; RT_DEBUG_NOT_IN_INTERRUPT; @@ -322,8 +301,6 @@ void rt_pm_register_device(struct rt_device *device, const struct rt_device_pm_o _pm.device_pm_number += 1; } - rt_sem_release(&(_pm.device_lock)); - rt_hw_interrupt_enable(level); } @@ -332,7 +309,7 @@ void rt_pm_register_device(struct rt_device *device, const struct rt_device_pm_o * * @param device the device with PM feature */ -void rt_pm_unregister_device(struct rt_device *device) +void rt_pm_device_unregister(struct rt_device *device) { rt_ubase_t level; rt_uint32_t index; @@ -362,6 +339,23 @@ void rt_pm_unregister_device(struct rt_device *device) rt_hw_interrupt_enable(level); } +/** + * This function set notification callback for application + */ +void rt_pm_notify_set(void (*notify)(uint8_t event, uint8_t mode, void *data), void *data) +{ + _pm_notify.notify = notify; + _pm_notify.data = data; +} + +/** + * This function set default sleep mode when no pm_request + */ +void rt_pm_default_set(uint8_t sleep_mode) +{ + _pm_default_sleep = sleep_mode; +} + /** * RT-Thread device interface for PM device */ @@ -377,7 +371,7 @@ static rt_size_t _rt_pm_device_read(rt_device_t dev, pm = (struct rt_pm *)dev; RT_ASSERT(pm != RT_NULL); - if (pos <= PM_MODE_MAX) + if (pos < PM_SLEEP_MODE_MAX) { int mode; @@ -399,11 +393,11 @@ static rt_size_t _rt_pm_device_write(rt_device_t dev, { /* get request */ request = *(unsigned char *)buffer; - if (request == '1') + if (request == 0x01) { rt_pm_request(pos); } - else if (request == '0') + else if (request == 0x00) { rt_pm_release(pos); } @@ -434,6 +428,36 @@ static rt_err_t _rt_pm_device_control(rt_device_t dev, return RT_EOK; } +int rt_pm_run_enter(uint8_t mode) +{ + rt_base_t level; + struct rt_pm *pm; + + if (_pm_init_flag == 0) + return -RT_EIO; + + if (mode > PM_RUN_MODE_MAX) + return -RT_EINVAL; + + level = rt_hw_interrupt_disable(); + pm = &_pm; + if (mode < pm->run_mode) + { + /* change system runing mode */ + pm->ops->run(pm, mode); + /* changer device frequency */ + _pm_device_frequency_change(mode); + } + else + { + pm->flags |= RT_PM_FREQUENCY_PENDING; + } + pm->run_mode = mode; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + /** * This function will initialize power management. * @@ -466,12 +490,9 @@ void rt_system_pm_init(const struct rt_pm_ops *ops, /* register PM device to the system */ rt_device_register(device, "pm", RT_DEVICE_FLAG_RDWR); - /* todo : add to kernel source code */ - rt_thread_idle_sethook(rt_pm_enter); - rt_memset(pm->modes, 0, sizeof(pm->modes)); - pm->current_mode = PM_RUN_MODE_DEFAULT; - + pm->sleep_mode = _pm_default_sleep; + pm->run_mode = RT_PM_DEFAULT_RUN_MODE; pm->timer_mask = timer_mask; pm->ops = ops; @@ -479,24 +500,15 @@ void rt_system_pm_init(const struct rt_pm_ops *ops, pm->device_pm = RT_NULL; pm->device_pm_number = 0; - /* initialize semaphore */ - rt_sem_init(&(pm->device_lock), "pm", 1, RT_IPC_FLAG_FIFO); - - /* request in default running mode */ - rt_pm_request(PM_RUN_MODE_DEFAULT); - -#ifdef PM_SLEEP_MODE_DEFAULT - /* request in default sleep mode */ - rt_pm_request(PM_SLEEP_MODE_DEFAULT); -#endif - - /* must hold on deep shutdown mode */ - rt_pm_request(PM_MODE_MAX); + _pm_init_flag = 1; } #ifdef RT_USING_FINSH #include +static const char *_pm_sleep_str[] = PM_SLEEP_MODE_NAMES; +static const char *_pm_run_str[] = PM_RUN_MODE_NAMES; + static void rt_pm_release_mode(int argc, char **argv) { int mode = 0; @@ -521,9 +533,20 @@ static void rt_pm_request_mode(int argc, char **argv) } MSH_CMD_EXPORT_ALIAS(rt_pm_request_mode, pm_request, request power management mode); +static void rt_pm_run_mode_switch(int argc, char **argv) +{ + int mode = 0; + if (argc >= 2) + { + mode = atoi(argv[1]); + } + + rt_pm_run_enter(mode); +} +MSH_CMD_EXPORT_ALIAS(rt_pm_run_mode_switch, pm_run, switch power management run mode); + static void rt_pm_dump_status(void) { - static const char *pm_str[] = PM_MODE_NAMES; rt_uint32_t index; struct rt_pm *pm; @@ -531,17 +554,18 @@ static void rt_pm_dump_status(void) rt_kprintf("| Power Management Mode | Counter | Timer |\n"); rt_kprintf("+-----------------------+---------+-------+\n"); - for (index = 0; index <= PM_MODE_MAX; index ++) + for (index = 0; index < PM_SLEEP_MODE_MAX; index ++) { int has_timer = 0; if (pm->timer_mask & (1 << index)) has_timer = 1; - rt_kprintf("| %021s | %7d | %5d |\n", pm_str[index], pm->modes[index], has_timer); + rt_kprintf("| %021s | %7d | %5d |\n", _pm_sleep_str[index], pm->modes[index], has_timer); } rt_kprintf("+-----------------------+---------+-------+\n"); - rt_kprintf("pm current mode: %s\n", pm_str[pm->current_mode]); + rt_kprintf("pm current sleep mode: %s\n", _pm_sleep_str[pm->sleep_mode]); + rt_kprintf("pm current run mode: %s\n", _pm_run_str[pm->run_mode]); } FINSH_FUNCTION_EXPORT_ALIAS(rt_pm_dump_status, pm_dump, dump power management status); MSH_CMD_EXPORT_ALIAS(rt_pm_dump_status, pm_dump, dump power management status); diff --git a/components/drivers/sdio/sd.c b/components/drivers/sdio/sd.c index 3e7ad1cd16..183eba169d 100644 --- a/components/drivers/sdio/sd.c +++ b/components/drivers/sdio/sd.c @@ -264,7 +264,7 @@ static rt_int32_t mmcsd_switch(struct rt_mmcsd_card *card) if ((buf[16] & 0xF) != 1) { - LOG_E("switching card to high speed failed!"); + LOG_I("switching card to high speed failed!"); goto err; } diff --git a/components/drivers/sensors/sensor.h b/components/drivers/sensors/sensor.h index 4f8ee47eb8..a9b6684457 100755 --- a/components/drivers/sensors/sensor.h +++ b/components/drivers/sensors/sensor.h @@ -19,7 +19,7 @@ extern "C" { #endif #ifdef RT_USING_RTC -#define rt_sensor_get_ts() time() /* API for the sensor to get the timestamp */ +#define rt_sensor_get_ts() time(RT_NULL) /* API for the sensor to get the timestamp */ #else #define rt_sensor_get_ts() rt_tick_get() /* API for the sensor to get the timestamp */ #endif diff --git a/components/drivers/sensors/sensor_cmd.c b/components/drivers/sensors/sensor_cmd.c index 2760892cfe..6babf12db3 100755 --- a/components/drivers/sensors/sensor_cmd.c +++ b/components/drivers/sensors/sensor_cmd.c @@ -24,13 +24,13 @@ static void sensor_show_data(rt_size_t num, rt_sensor_t sensor, struct rt_sensor switch (sensor->info.type) { case RT_SENSOR_CLASS_ACCE: - LOG_I("num:%3d, x:%5d, y:%5d, z:%5d, timestamp:%5d", num, sensor_data->data.acce.x, sensor_data->data.acce.y, sensor_data->data.acce.z, sensor_data->timestamp); + LOG_I("num:%3d, x:%5d, y:%5d, z:%5d mg, timestamp:%5d", num, sensor_data->data.acce.x, sensor_data->data.acce.y, sensor_data->data.acce.z, sensor_data->timestamp); break; case RT_SENSOR_CLASS_GYRO: - LOG_I("num:%3d, x:%8d, y:%8d, z:%8d, timestamp:%5d", num, sensor_data->data.gyro.x, sensor_data->data.gyro.y, sensor_data->data.gyro.z, sensor_data->timestamp); + LOG_I("num:%3d, x:%8d, y:%8d, z:%8d dps, timestamp:%5d", num, sensor_data->data.gyro.x / 1000, sensor_data->data.gyro.y / 1000, sensor_data->data.gyro.z / 1000, sensor_data->timestamp); break; case RT_SENSOR_CLASS_MAG: - LOG_I("num:%3d, x:%5d, y:%5d, z:%5d, timestamp:%5d", num, sensor_data->data.mag.x, sensor_data->data.mag.y, sensor_data->data.mag.z, sensor_data->timestamp); + LOG_I("num:%3d, x:%5d, y:%5d, z:%5d mGauss, timestamp:%5d", num, sensor_data->data.mag.x, sensor_data->data.mag.y, sensor_data->data.mag.z, sensor_data->timestamp); break; case RT_SENSOR_CLASS_HUMI: LOG_I("num:%3d, humi:%3d.%d%%, timestamp:%5d", num, sensor_data->data.humi / 10, sensor_data->data.humi % 10, sensor_data->timestamp); @@ -39,7 +39,7 @@ static void sensor_show_data(rt_size_t num, rt_sensor_t sensor, struct rt_sensor LOG_I("num:%3d, temp:%3d.%dC, timestamp:%5d", num, sensor_data->data.temp / 10, sensor_data->data.temp % 10, sensor_data->timestamp); break; case RT_SENSOR_CLASS_BARO: - LOG_I("num:%3d, press:%5d, timestamp:%5d", num, sensor_data->data.baro, sensor_data->timestamp); + LOG_I("num:%3d, press:%5d pa, timestamp:%5d", num, sensor_data->data.baro, sensor_data->timestamp); break; case RT_SENSOR_CLASS_STEP: LOG_I("num:%3d, step:%5d, timestamp:%5d", num, sensor_data->data.step, sensor_data->timestamp); diff --git a/components/drivers/serial/serial.c b/components/drivers/serial/serial.c index d4cf35414c..c3e96fc77b 100644 --- a/components/drivers/serial/serial.c +++ b/components/drivers/serial/serial.c @@ -675,6 +675,8 @@ static rt_err_t rt_serial_open(struct rt_device *dev, rt_uint16_t oflag) serial->serial_tx = tx_dma; dev->open_flag |= RT_DEVICE_FLAG_DMA_TX; + /* configure low level device */ + serial->ops->control(serial, RT_DEVICE_CTRL_CONFIG, (void *)RT_DEVICE_FLAG_DMA_TX); } #endif /* RT_SERIAL_USING_DMA */ else diff --git a/components/libc/Kconfig b/components/libc/Kconfig index b2abe69850..43d9330102 100644 --- a/components/libc/Kconfig +++ b/components/libc/Kconfig @@ -8,6 +8,12 @@ config RT_USING_PTHREADS bool "Enable pthreads APIs" default n +if RT_USING_PTHREADS + config PTHREAD_NUM_MAX + int "Maximum number of pthreads" + default 8 +endif + if RT_USING_LIBC && RT_USING_DFS config RT_USING_POSIX bool "Enable POSIX layer for poll/select, stdin etc" diff --git a/components/libc/pthreads/pthread.c b/components/libc/pthreads/pthread.c index 55f46c0caa..7ecf304038 100644 --- a/components/libc/pthreads/pthread.c +++ b/components/libc/pthreads/pthread.c @@ -10,10 +10,121 @@ * 2019-02-07 Bernard Add _pthread_destroy to release pthread resource. */ +#include #include #include #include "pthread_internal.h" +RT_DEFINE_SPINLOCK(pth_lock); +_pthread_data_t *pth_table[PTHREAD_NUM_MAX] = {NULL}; + +_pthread_data_t *_pthread_get_data(pthread_t thread) +{ + RT_DECLARE_SPINLOCK(pth_lock); + _pthread_data_t *ptd; + + if (thread >= PTHREAD_NUM_MAX) return NULL; + + rt_hw_spin_lock(&pth_lock); + ptd = pth_table[thread]; + rt_hw_spin_unlock(&pth_lock); + + if (ptd && ptd->magic == PTHREAD_MAGIC) return ptd; + + return NULL; +} + +pthread_t _pthread_data_get_pth(_pthread_data_t *ptd) +{ + int index; + RT_DECLARE_SPINLOCK(pth_lock); + + rt_hw_spin_lock(&pth_lock); + for (index = 0; index < PTHREAD_NUM_MAX; index ++) + { + if (pth_table[index] == ptd) break; + } + rt_hw_spin_unlock(&pth_lock); + + return index; +} + +pthread_t _pthread_data_create(void) +{ + int index; + _pthread_data_t *ptd = NULL; + RT_DECLARE_SPINLOCK(pth_lock); + + ptd = (_pthread_data_t*)rt_malloc(sizeof(_pthread_data_t)); + if (!ptd) return PTHREAD_NUM_MAX; + + memset(ptd, 0x0, sizeof(_pthread_data_t)); + ptd->canceled = 0; + ptd->cancelstate = PTHREAD_CANCEL_DISABLE; + ptd->canceltype = PTHREAD_CANCEL_DEFERRED; + ptd->magic = PTHREAD_MAGIC; + + rt_hw_spin_lock(&pth_lock); + for (index = 0; index < PTHREAD_NUM_MAX; index ++) + { + if (pth_table[index] == NULL) + { + pth_table[index] = ptd; + break; + } + } + rt_hw_spin_unlock(&pth_lock); + + /* full of pthreads, clean magic and release ptd */ + if (index == PTHREAD_NUM_MAX) + { + ptd->magic = 0x0; + rt_free(ptd); + } + + return index; +} + +void _pthread_data_destroy(pthread_t pth) +{ + RT_DECLARE_SPINLOCK(pth_lock); + + _pthread_data_t *ptd = _pthread_get_data(pth); + if (ptd) + { + /* remove from pthread table */ + rt_hw_spin_lock(&pth_lock); + pth_table[pth] = NULL; + rt_hw_spin_unlock(&pth_lock); + + /* delete joinable semaphore */ + if (ptd->joinable_sem != RT_NULL) + rt_sem_delete(ptd->joinable_sem); + + /* release thread resource */ + if (ptd->attr.stackaddr == RT_NULL) + { + /* release thread allocated stack */ + rt_free(ptd->tid->stack_addr); + } + /* clean stack addr pointer */ + ptd->tid->stack_addr = RT_NULL; + + /* + * if this thread create the local thread data, + * delete it + */ + if (ptd->tls != RT_NULL) rt_free(ptd->tls); + rt_free(ptd->tid); + + /* clean magic */ + ptd->magic = 0x0; + + /* free ptd */ + rt_free(ptd); + } +} + int pthread_system_init(void) { /* initialize key area */ @@ -29,26 +140,11 @@ INIT_COMPONENT_EXPORT(pthread_system_init); static void _pthread_destroy(_pthread_data_t *ptd) { - /* delete joinable semaphore */ - if (ptd->joinable_sem != RT_NULL) - rt_sem_delete(ptd->joinable_sem); - - /* release thread resource */ - if (ptd->attr.stack_base == RT_NULL) + pthread_t pth = _pthread_data_get_pth(ptd); + if (pth != PTHREAD_NUM_MAX) { - /* release thread allocated stack */ - rt_free(ptd->tid->stack_addr); + _pthread_data_destroy(pth); } - /* clean stack addr pointer */ - ptd->tid->stack_addr = RT_NULL; - - /* - * if this thread create the local thread data, - * delete it - */ - if (ptd->tls != RT_NULL) rt_free(ptd->tls); - rt_free(ptd->tid); - rt_free(ptd); return; } @@ -56,7 +152,10 @@ static void _pthread_destroy(_pthread_data_t *ptd) static void _pthread_cleanup(rt_thread_t tid) { _pthread_data_t *ptd; - ptd = _pthread_get_data(tid); + + /* get pthread data from user data of thread */ + ptd = (_pthread_data_t *)tid->user_data; + RT_ASSERT(ptd != RT_NULL); /* clear cleanup function */ tid->cleanup = RT_NULL; @@ -84,29 +183,30 @@ static void pthread_entry_stub(void *parameter) ptd->return_value = value; } -int pthread_create(pthread_t *tid, +int pthread_create(pthread_t *pid, const pthread_attr_t *attr, void *(*start)(void *), void *parameter) { - int result; + int ret = 0; void *stack; char name[RT_NAME_MAX]; static rt_uint16_t pthread_number = 0; + + pthread_t pth_id; _pthread_data_t *ptd; - /* tid shall be provided */ - RT_ASSERT(tid != RT_NULL); + /* pid shall be provided */ + RT_ASSERT(pid != RT_NULL); /* allocate posix thread data */ - ptd = (_pthread_data_t *)rt_malloc(sizeof(_pthread_data_t)); - if (ptd == RT_NULL) - return ENOMEM; - /* clean posix thread data memory */ - rt_memset(ptd, 0, sizeof(_pthread_data_t)); - ptd->canceled = 0; - ptd->cancelstate = PTHREAD_CANCEL_DISABLE; - ptd->canceltype = PTHREAD_CANCEL_DEFERRED; - ptd->magic = PTHREAD_MAGIC; + pth_id = _pthread_data_create(); + if (pth_id == PTHREAD_NUM_MAX) + { + ret = ENOMEM; + goto __exit; + } + /* get pthread data */ + ptd = _pthread_get_data(pth_id); if (attr != RT_NULL) { @@ -119,31 +219,27 @@ int pthread_create(pthread_t *tid, } rt_snprintf(name, sizeof(name), "pth%02d", pthread_number ++); - if (ptd->attr.stack_base == 0) + if (ptd->attr.stackaddr == 0) { - stack = (void *)rt_malloc(ptd->attr.stack_size); + stack = (void *)rt_malloc(ptd->attr.stacksize); } else { - stack = (void *)(ptd->attr.stack_base); + stack = (void *)(ptd->attr.stackaddr); } if (stack == RT_NULL) { - rt_free(ptd); - - return ENOMEM; + ret = ENOMEM; + goto __exit; } /* pthread is a static thread object */ ptd->tid = (rt_thread_t) rt_malloc(sizeof(struct rt_thread)); if (ptd->tid == RT_NULL) { - if (ptd->attr.stack_base == 0) - rt_free(stack); - rt_free(ptd); - - return ENOMEM; + ret = ENOMEM; + goto __exit; } if (ptd->attr.detachstate == PTHREAD_CREATE_JOINABLE) @@ -151,11 +247,8 @@ int pthread_create(pthread_t *tid, ptd->joinable_sem = rt_sem_create(name, 0, RT_IPC_FLAG_FIFO); if (ptd->joinable_sem == RT_NULL) { - if (ptd->attr.stack_base != 0) - rt_free(stack); - rt_free(ptd); - - return ENOMEM; + ret = ENOMEM; + goto __exit; } } else @@ -169,40 +262,32 @@ int pthread_create(pthread_t *tid, /* initial this pthread to system */ if (rt_thread_init(ptd->tid, name, pthread_entry_stub, ptd, - stack, ptd->attr.stack_size, - ptd->attr.priority, 5) != RT_EOK) + stack, ptd->attr.stacksize, + ptd->attr.schedparam.sched_priority, 5) != RT_EOK) { - if (ptd->attr.stack_base == 0) - rt_free(stack); - if (ptd->joinable_sem != RT_NULL) - rt_sem_delete(ptd->joinable_sem); - rt_free(ptd); - - return EINVAL; + ret = EINVAL; + goto __exit; } /* set pthread id */ - *tid = ptd->tid; + *pid = pth_id; /* set pthread cleanup function and ptd data */ - (*tid)->cleanup = _pthread_cleanup; - (*tid)->user_data = (rt_uint32_t)ptd; + ptd->tid->cleanup = _pthread_cleanup; + ptd->tid->user_data = (rt_uint32_t)ptd; /* start thread */ - result = rt_thread_startup(*tid); - if (result == RT_EOK) + if (rt_thread_startup(ptd->tid) == RT_EOK) return 0; /* start thread failed */ rt_thread_detach(ptd->tid); - if (ptd->attr.stack_base == 0) - rt_free(stack); - if (ptd->joinable_sem != RT_NULL) - rt_sem_delete(ptd->joinable_sem); + ret = EINVAL; - rt_free(ptd); - - return EINVAL; +__exit: + if (pth_id != PTHREAD_NUM_MAX) + _pthread_data_destroy(pth_id); + return ret; } RTM_EXPORT(pthread_create); @@ -221,7 +306,7 @@ int pthread_detach(pthread_t thread) goto __exit; } - if ((thread->stat & RT_THREAD_STAT_MASK) == RT_THREAD_CLOSE) + if ((ptd->tid->stat & RT_THREAD_STAT_MASK) == RT_THREAD_CLOSE) { /* this defunct pthread is not handled by idle */ if (rt_sem_trytake(ptd->joinable_sem) != RT_EOK) @@ -270,13 +355,13 @@ int pthread_join(pthread_t thread, void **value_ptr) _pthread_data_t *ptd; rt_err_t result; - if (thread == rt_thread_self()) + ptd = _pthread_get_data(thread); + if (ptd && ptd->tid == rt_thread_self()) { /* join self */ return EDEADLK; } - ptd = _pthread_get_data(thread); if (ptd->attr.detachstate == PTHREAD_CREATE_DETACHED) return EINVAL; /* join on a detached pthread */ @@ -299,13 +384,32 @@ int pthread_join(pthread_t thread, void **value_ptr) } RTM_EXPORT(pthread_join); +pthread_t pthread_self (void) +{ + rt_thread_t tid; + _pthread_data_t *ptd; + + tid = rt_thread_self(); + if (tid == NULL) return PTHREAD_NUM_MAX; + + /* get pthread data from user data of thread */ + ptd = (_pthread_data_t *)rt_thread_self()->user_data; + RT_ASSERT(ptd != RT_NULL); + + return _pthread_data_get_pth(ptd); +} +RTM_EXPORT(pthread_self); + void pthread_exit(void *value) { _pthread_data_t *ptd; _pthread_cleanup_t *cleanup; extern _pthread_key_data_t _thread_keys[PTHREAD_KEY_MAX]; - ptd = _pthread_get_data(rt_thread_self()); + if (rt_thread_self() == NULL) return; + + /* get pthread data from user data of thread */ + ptd = (_pthread_data_t *)rt_thread_self()->user_data; rt_enter_critical(); /* disable cancel */ @@ -382,7 +486,15 @@ RTM_EXPORT(pthread_atfork); int pthread_kill(pthread_t thread, int sig) { #ifdef RT_USING_SIGNALS - return rt_thread_kill(thread, sig); + _pthread_data_t *ptd; + + ptd = _pthread_get_data(thread); + if (ptd) + { + return rt_thread_kill(ptd->tid, sig); + } + + return EINVAL; #else return ENOSYS; #endif @@ -401,8 +513,10 @@ void pthread_cleanup_pop(int execute) _pthread_data_t *ptd; _pthread_cleanup_t *cleanup; - /* get posix thread data */ - ptd = _pthread_get_data(rt_thread_self()); + if (rt_thread_self() == NULL) return; + + /* get pthread data from user data of thread */ + ptd = (_pthread_data_t *)rt_thread_self()->user_data; RT_ASSERT(ptd != RT_NULL); if (execute) @@ -428,8 +542,10 @@ void pthread_cleanup_push(void (*routine)(void *), void *arg) _pthread_data_t *ptd; _pthread_cleanup_t *cleanup; - /* get posix thread data */ - ptd = _pthread_get_data(rt_thread_self()); + if (rt_thread_self() == NULL) return; + + /* get pthread data from user data of thread */ + ptd = (_pthread_data_t *)rt_thread_self()->user_data; RT_ASSERT(ptd != RT_NULL); cleanup = (_pthread_cleanup_t *)rt_malloc(sizeof(_pthread_cleanup_t)); @@ -478,8 +594,10 @@ int pthread_setcancelstate(int state, int *oldstate) { _pthread_data_t *ptd; - /* get posix thread data */ - ptd = _pthread_get_data(rt_thread_self()); + if (rt_thread_self() == NULL) return EINVAL; + + /* get pthread data from user data of thread */ + ptd = (_pthread_data_t *)rt_thread_self()->user_data; RT_ASSERT(ptd != RT_NULL); if ((state == PTHREAD_CANCEL_ENABLE) || (state == PTHREAD_CANCEL_DISABLE)) @@ -499,8 +617,10 @@ int pthread_setcanceltype(int type, int *oldtype) { _pthread_data_t *ptd; - /* get posix thread data */ - ptd = _pthread_get_data(rt_thread_self()); + if (rt_thread_self() == NULL) return EINVAL; + + /* get pthread data from user data of thread */ + ptd = (_pthread_data_t *)rt_thread_self()->user_data; RT_ASSERT(ptd != RT_NULL); if ((type != PTHREAD_CANCEL_DEFERRED) && (type != PTHREAD_CANCEL_ASYNCHRONOUS)) @@ -519,8 +639,10 @@ void pthread_testcancel(void) int cancel = 0; _pthread_data_t *ptd; - /* get posix thread data */ - ptd = _pthread_get_data(rt_thread_self()); + if (rt_thread_self() == NULL) return; + + /* get pthread data from user data of thread */ + ptd = (_pthread_data_t *)rt_thread_self()->user_data; RT_ASSERT(ptd != RT_NULL); if (ptd->cancelstate == PTHREAD_CANCEL_ENABLE) @@ -534,14 +656,14 @@ int pthread_cancel(pthread_t thread) { _pthread_data_t *ptd; - /* cancel self */ - if (thread == rt_thread_self()) - return 0; - /* get posix thread data */ ptd = _pthread_get_data(thread); RT_ASSERT(ptd != RT_NULL); + /* cancel self */ + if (ptd->tid == rt_thread_self()) + return 0; + /* set canceled */ if (ptd->cancelstate == PTHREAD_CANCEL_ENABLE) { @@ -555,10 +677,11 @@ int pthread_cancel(pthread_t thread) * thread (pthread_cleanup), it will move to defunct * thread list and wait for handling in idle thread. */ - rt_thread_detach(thread); + rt_thread_detach(ptd->tid); } } return 0; } RTM_EXPORT(pthread_cancel); + diff --git a/components/libc/pthreads/pthread.h b/components/libc/pthreads/pthread.h index f9a0a92b68..7bb72b726c 100644 --- a/components/libc/pthreads/pthread.h +++ b/components/libc/pthreads/pthread.h @@ -32,7 +32,7 @@ extern "C" { #define PTHREAD_EXPLICIT_SCHED 0 #define PTHREAD_INHERIT_SCHED 1 -typedef rt_thread_t pthread_t; +typedef long pthread_t; typedef long pthread_condattr_t; typedef long pthread_rwlockattr_t; typedef long pthread_mutexattr_t; @@ -76,15 +76,21 @@ enum #define PTHREAD_SCOPE_PROCESS 0 #define PTHREAD_SCOPE_SYSTEM 1 +struct sched_param +{ + int sched_priority; +}; + struct pthread_attr { - void* stack_base; - rt_uint32_t stack_size; /* stack size of thread */ + void* stackaddr; /* stack address of thread */ + int stacksize; /* stack size of thread */ - rt_uint8_t priority; /* priority of thread */ - rt_uint8_t detachstate; /* detach state */ - rt_uint8_t policy; /* scheduler policy */ - rt_uint8_t inheritsched; /* Inherit parent prio/policy */ + int inheritsched; /* Inherit parent prio/policy */ + int schedpolicy; /* scheduler policy */ + struct sched_param schedparam; /* sched parameter */ + + int detachstate; /* detach state */ }; typedef struct pthread_attr pthread_attr_t; @@ -131,11 +137,6 @@ struct pthread_barrier }; typedef struct pthread_barrier pthread_barrier_t; -struct sched_param -{ - int sched_priority; -}; - /* pthread thread interface */ int pthread_attr_destroy(pthread_attr_t *attr); int pthread_attr_init(pthread_attr_t *attr); @@ -171,10 +172,7 @@ rt_inline int pthread_equal (pthread_t t1, pthread_t t2) return t1 == t2; } -rt_inline pthread_t pthread_self (void) -{ - return rt_thread_self(); -} +pthread_t pthread_self (void); void pthread_exit (void *value_ptr); int pthread_once(pthread_once_t * once_control, void (*init_routine) (void)); diff --git a/components/libc/pthreads/pthread_attr.c b/components/libc/pthreads/pthread_attr.c index 8eed35932f..2294599bf3 100644 --- a/components/libc/pthreads/pthread_attr.c +++ b/components/libc/pthreads/pthread_attr.c @@ -20,10 +20,13 @@ const pthread_attr_t pthread_default_attr = { 0, /* stack base */ DEFAULT_STACK_SIZE, /* stack size */ - DEFAULT_PRIORITY, /* priority */ - PTHREAD_CREATE_JOINABLE, /* detach state */ + + PTHREAD_INHERIT_SCHED, /* Inherit parent prio/policy */ SCHED_FIFO, /* scheduler policy */ - PTHREAD_INHERIT_SCHED /* Inherit parent prio/policy */ + { + DEFAULT_PRIORITY, /* scheduler priority */ + }, + PTHREAD_CREATE_JOINABLE, /* detach state */ }; int pthread_attr_init(pthread_attr_t *attr) @@ -73,7 +76,7 @@ int pthread_attr_setschedpolicy(pthread_attr_t *attr, int policy) { RT_ASSERT(attr != RT_NULL); - attr->policy = policy; + attr->schedpolicy = policy; return 0; } @@ -83,7 +86,7 @@ int pthread_attr_getschedpolicy(pthread_attr_t const *attr, int *policy) { RT_ASSERT(attr != RT_NULL); - *policy = (int)attr->policy; + *policy = (int)attr->schedpolicy; return 0; } @@ -95,7 +98,7 @@ int pthread_attr_setschedparam(pthread_attr_t *attr, RT_ASSERT(attr != RT_NULL); RT_ASSERT(param != RT_NULL); - attr->priority = param->sched_priority; + attr->schedparam.sched_priority = param->sched_priority; return 0; } @@ -107,7 +110,7 @@ int pthread_attr_getschedparam(pthread_attr_t const *attr, RT_ASSERT(attr != RT_NULL); RT_ASSERT(param != RT_NULL); - param->sched_priority = attr->priority; + param->sched_priority = attr->schedparam.sched_priority; return 0; } @@ -117,7 +120,7 @@ int pthread_attr_setstacksize(pthread_attr_t *attr, size_t stack_size) { RT_ASSERT(attr != RT_NULL); - attr->stack_size = stack_size; + attr->stacksize = stack_size; return 0; } @@ -127,7 +130,7 @@ int pthread_attr_getstacksize(pthread_attr_t const *attr, size_t *stack_size) { RT_ASSERT(attr != RT_NULL); - *stack_size = attr->stack_size; + *stack_size = attr->stacksize; return 0; } @@ -155,8 +158,8 @@ int pthread_attr_setstack(pthread_attr_t *attr, { RT_ASSERT(attr != RT_NULL); - attr->stack_base = stack_base; - attr->stack_size = RT_ALIGN_DOWN(stack_size, RT_ALIGN_SIZE); + attr->stackaddr = stack_base; + attr->stacksize = RT_ALIGN_DOWN(stack_size, RT_ALIGN_SIZE); return 0; } @@ -168,8 +171,8 @@ int pthread_attr_getstack(pthread_attr_t const *attr, { RT_ASSERT(attr != RT_NULL); - *stack_base = attr->stack_base; - *stack_size = attr->stack_size; + *stack_base = attr->stackaddr; + *stack_size = attr->stacksize; return 0; } diff --git a/components/libc/pthreads/pthread_cond.c b/components/libc/pthreads/pthread_cond.c index d3c4ac7637..38dc697469 100644 --- a/components/libc/pthreads/pthread_cond.c +++ b/components/libc/pthreads/pthread_cond.c @@ -189,7 +189,7 @@ rt_err_t _pthread_cond_timedwait(pthread_cond_t *cond, pthread_cond_init(cond, RT_NULL); /* The mutex was not owned by the current thread at the time of the call. */ - if (mutex->lock.owner != pthread_self()) + if (mutex->lock.owner != rt_thread_self()) return -RT_ERROR; /* unlock a mutex failed */ if (pthread_mutex_unlock(mutex) != 0) diff --git a/components/libc/pthreads/pthread_internal.h b/components/libc/pthreads/pthread_internal.h index 3e94e867d7..a6706ca091 100644 --- a/components/libc/pthreads/pthread_internal.h +++ b/components/libc/pthreads/pthread_internal.h @@ -30,6 +30,10 @@ struct _pthread_key_data }; typedef struct _pthread_key_data _pthread_key_data_t; +#ifndef PTHREAD_NUM_MAX +#define PTHREAD_NUM_MAX 32 +#endif + #define PTHREAD_MAGIC 0x70746873 struct _pthread_data { @@ -56,17 +60,7 @@ struct _pthread_data }; typedef struct _pthread_data _pthread_data_t; -rt_inline _pthread_data_t *_pthread_get_data(pthread_t thread) -{ - _pthread_data_t *ptd; - RT_ASSERT(thread != RT_NULL); - - ptd = (_pthread_data_t *)thread->user_data; - RT_ASSERT(ptd != RT_NULL); - RT_ASSERT(ptd->magic == PTHREAD_MAGIC); - - return ptd; -} +_pthread_data_t *_pthread_get_data(pthread_t thread); int clock_time_to_tick(const struct timespec *time); diff --git a/components/libc/pthreads/pthread_tls.c b/components/libc/pthreads/pthread_tls.c index c6d0bca155..4b97d796d9 100644 --- a/components/libc/pthreads/pthread_tls.c +++ b/components/libc/pthreads/pthread_tls.c @@ -22,7 +22,10 @@ void *pthread_getspecific(pthread_key_t key) { struct _pthread_data* ptd; - ptd = _pthread_get_data(rt_thread_self()); + if (rt_thread_self() == NULL) return NULL; + + /* get pthread data from user data of thread */ + ptd = (_pthread_data_t *)rt_thread_self()->user_data; RT_ASSERT(ptd != NULL); if (ptd->tls == NULL) @@ -39,7 +42,10 @@ int pthread_setspecific(pthread_key_t key, const void *value) { struct _pthread_data* ptd; - ptd = _pthread_get_data(rt_thread_self()); + if (rt_thread_self() == NULL) return EINVAL; + + /* get pthread data from user data of thread */ + ptd = (_pthread_data_t *)rt_thread_self()->user_data; RT_ASSERT(ptd != NULL); /* check tls area */ diff --git a/components/net/Kconfig b/components/net/Kconfig index a719f7be6f..68737176ed 100644 --- a/components/net/Kconfig +++ b/components/net/Kconfig @@ -5,6 +5,7 @@ menu "Socket abstraction layer" config RT_USING_SAL bool "Enable socket abstraction layer" select RT_USING_NETDEV + select RT_USING_LIBC select RT_USING_SYSTEM_WORKQUEUE default n @@ -36,7 +37,6 @@ config RT_USING_SAL bool "Enable BSD socket operated by file system API" default n select RT_USING_DFS - select RT_USING_LIBC select RT_USING_POSIX help Let BSD socket operated by file system API, such as read/write and involveed in select/poll POSIX APIs. @@ -73,6 +73,9 @@ config RT_USING_NETDEV bool "Enable netstat features" default y + config NETDEV_USING_AUTO_DEFAULT + bool "Enable default netdev automatic change features" + default y endif endmenu diff --git a/components/net/freemodbus/port/portserial.c b/components/net/freemodbus/port/portserial.c index 7c546a1691..cbd846d7ff 100644 --- a/components/net/freemodbus/port/portserial.c +++ b/components/net/freemodbus/port/portserial.c @@ -52,6 +52,8 @@ static void serial_soft_trans_irq(void* parameter); BOOL xMBPortSerialInit(UCHAR ucPORT, ULONG ulBaudRate, UCHAR ucDataBits, eMBParity eParity) { + rt_device_t dev = RT_NULL; + char uart_name[20]; /** * set 485 mode receive and transmit control IO * @note MODBUS_SLAVE_RT_CONTROL_PIN_INDEX need be defined by user @@ -60,22 +62,19 @@ BOOL xMBPortSerialInit(UCHAR ucPORT, ULONG ulBaudRate, UCHAR ucDataBits, rt_pin_mode(MODBUS_SLAVE_RT_CONTROL_PIN_INDEX, PIN_MODE_OUTPUT); #endif /* set serial name */ - if (ucPORT == 1) { -#if defined(RT_USING_UART1) || defined(RT_USING_REMAP_UART1) - extern struct rt_serial_device serial1; - serial = &serial1; -#endif - } else if (ucPORT == 2) { -#if defined(RT_USING_UART2) - extern struct rt_serial_device serial2; - serial = &serial2; -#endif - } else if (ucPORT == 3) { -#if defined(RT_USING_UART3) - extern struct rt_serial_device serial3; - serial = &serial3; -#endif + rt_snprintf(uart_name,sizeof(uart_name), "uart%d", ucPORT); + + dev = rt_device_find(uart_name); + if(dev == RT_NULL) + { + /* can not find uart */ + return FALSE; } + else + { + serial = (struct rt_serial_device*)dev; + } + /* set serial configure parameter */ serial->config.baud_rate = ulBaudRate; serial->config.stop_bits = STOP_BITS_1; diff --git a/components/net/freemodbus/port/portserial_m.c b/components/net/freemodbus/port/portserial_m.c index f68794a617..47a70dd905 100644 --- a/components/net/freemodbus/port/portserial_m.c +++ b/components/net/freemodbus/port/portserial_m.c @@ -53,6 +53,9 @@ static void serial_soft_trans_irq(void* parameter); BOOL xMBMasterPortSerialInit(UCHAR ucPORT, ULONG ulBaudRate, UCHAR ucDataBits, eMBParity eParity) { + rt_device_t dev = RT_NULL; + char uart_name[20]; + /** * set 485 mode receive and transmit control IO * @note MODBUS_MASTER_RT_CONTROL_PIN_INDEX need be defined by user @@ -60,24 +63,20 @@ BOOL xMBMasterPortSerialInit(UCHAR ucPORT, ULONG ulBaudRate, UCHAR ucDataBits, #if defined(RT_MODBUS_MASTER_USE_CONTROL_PIN) rt_pin_mode(MODBUS_MASTER_RT_CONTROL_PIN_INDEX, PIN_MODE_OUTPUT); #endif - /* set serial name */ - if (ucPORT == 1) { -#if defined(RT_USING_UART1) || defined(RT_USING_REMAP_UART1) - extern struct rt_serial_device serial1; - serial = &serial1; -#endif - } else if (ucPORT == 2) { -#if defined(RT_USING_UART2) - extern struct rt_serial_device serial2; - serial = &serial2; -#endif - } else if (ucPORT == 3) { -#if defined(RT_USING_UART3) - extern struct rt_serial_device serial3; - serial = &serial3; -#endif + rt_snprintf(uart_name,sizeof(uart_name), "uart%d", ucPORT); + + dev = rt_device_find(uart_name); + if(dev == RT_NULL) + { + /* can not find uart */ + return FALSE; } + else + { + serial = (struct rt_serial_device*)dev; + } + /* set serial configure parameter */ serial->config.baud_rate = ulBaudRate; serial->config.stop_bits = STOP_BITS_1; diff --git a/components/net/lwip-2.0.2/src/api/api_lib.c b/components/net/lwip-2.0.2/src/api/api_lib.c index 3c1d6a6c27..7d9c12768d 100644 --- a/components/net/lwip-2.0.2/src/api/api_lib.c +++ b/components/net/lwip-2.0.2/src/api/api_lib.c @@ -175,12 +175,12 @@ netconn_delete(struct netconn *conn) API_MSG_VAR_ALLOC(msg); API_MSG_VAR_REF(msg).conn = conn; +#if LWIP_TCP #if LWIP_SO_SNDTIMEO || LWIP_SO_LINGER /* get the time we started, which is later compared to sys_now() + conn->send_timeout */ API_MSG_VAR_REF(msg).msg.sd.time_started = sys_now(); #else /* LWIP_SO_SNDTIMEO || LWIP_SO_LINGER */ -#if LWIP_TCP API_MSG_VAR_REF(msg).msg.sd.polls_left = ((LWIP_TCP_CLOSE_TIMEOUT_MS_DEFAULT + TCP_SLOW_INTERVAL - 1) / TCP_SLOW_INTERVAL) + 1; #endif /* LWIP_TCP */ diff --git a/components/net/lwip-2.1.0/src/api/api_lib.c b/components/net/lwip-2.1.0/src/api/api_lib.c index e03b8b7451..5e9ceafa53 100644 --- a/components/net/lwip-2.1.0/src/api/api_lib.c +++ b/components/net/lwip-2.1.0/src/api/api_lib.c @@ -201,12 +201,12 @@ netconn_prepare_delete(struct netconn *conn) API_MSG_VAR_ALLOC(msg); API_MSG_VAR_REF(msg).conn = conn; +#if LWIP_TCP #if LWIP_SO_SNDTIMEO || LWIP_SO_LINGER /* get the time we started, which is later compared to sys_now() + conn->send_timeout */ API_MSG_VAR_REF(msg).msg.sd.time_started = sys_now(); #else /* LWIP_SO_SNDTIMEO || LWIP_SO_LINGER */ -#if LWIP_TCP API_MSG_VAR_REF(msg).msg.sd.polls_left = ((LWIP_TCP_CLOSE_TIMEOUT_MS_DEFAULT + TCP_SLOW_INTERVAL - 1) / TCP_SLOW_INTERVAL) + 1; #endif /* LWIP_TCP */ diff --git a/components/net/netdev/include/netdev.h b/components/net/netdev/include/netdev.h index 5ea8e96080..e9d8e38658 100644 --- a/components/net/netdev/include/netdev.h +++ b/components/net/netdev/include/netdev.h @@ -133,7 +133,7 @@ int netdev_register(struct netdev *netdev, const char *name, void *user_data); int netdev_unregister(struct netdev *netdev); /* Get network interface device object */ -struct netdev *netdev_get_first_link_up(void); +struct netdev *netdev_get_first_by_flags(uint16_t flags); struct netdev *netdev_get_by_ipaddr(ip_addr_t *ip_addr); struct netdev *netdev_get_by_name(const char *name); #ifdef RT_USING_SAL diff --git a/components/net/netdev/src/netdev.c b/components/net/netdev/src/netdev.c index bfefc2d1de..71b1ec7ccd 100644 --- a/components/net/netdev/src/netdev.c +++ b/components/net/netdev/src/netdev.c @@ -134,12 +134,14 @@ int netdev_unregister(struct netdev *netdev) /** * This function will get the first network interface device - * with the link_up status in network interface device list. + * with the flags in network interface device list. + * + * @param flags the network interface device flags * * @return != NULL: network interface device object * NULL: get failed */ -struct netdev *netdev_get_first_link_up(void) +struct netdev *netdev_get_first_by_flags(uint16_t flags) { rt_base_t level; rt_slist_t *node = RT_NULL; @@ -155,7 +157,7 @@ struct netdev *netdev_get_first_link_up(void) for (node = &(netdev_list->list); node; node = rt_slist_next(node)) { netdev = rt_slist_entry(node, struct netdev, list); - if (netdev && netdev_is_up(netdev) && netdev_is_link_up(netdev)) + if (netdev && (netdev->flags & flags) != 0) { rt_hw_interrupt_enable(level); return netdev; @@ -269,7 +271,7 @@ struct netdev *netdev_get_by_family(int family) { netdev = rt_slist_entry(node, struct netdev, list); pf = (struct sal_proto_family *) netdev->sal_user_data; - if (pf && pf->skt_ops && pf->family == family && netdev_is_up(netdev) && netdev_is_link_up(netdev)) + if (pf && pf->skt_ops && pf->family == family && netdev_is_up(netdev)) { rt_hw_interrupt_enable(level); return netdev; @@ -671,6 +673,23 @@ void netdev_low_level_set_dns_server(struct netdev *netdev, uint8_t dns_num, con } } +#ifdef NETDEV_USING_AUTO_DEFAULT +/* Change to the first link_up network interface device automatically */ +static void netdev_auto_change_default(struct netdev *netdev) +{ + struct netdev *new_netdev = RT_NULL; + + if (rt_memcmp(netdev, netdev_default, sizeof(struct netdev)) == 0) + { + new_netdev = netdev_get_first_by_flags(NETDEV_FLAG_LINK_UP); + if (new_netdev) + { + netdev_set_default(new_netdev); + } + } +} +#endif /* NETDEV_USING_AUTO_DEFAULT */ + /** * This function will set network interface device status. * @NOTE it can only be called in the network interface device driver. @@ -689,6 +708,11 @@ void netdev_low_level_set_status(struct netdev *netdev, rt_bool_t is_up) else { netdev->flags &= ~NETDEV_FLAG_UP; + +#ifdef NETDEV_USING_AUTO_DEFAULT + /* change to the first link_up network interface device automatically */ + netdev_auto_change_default(netdev); +#endif /* NETDEV_USING_AUTO_DEFAULT */ } /* execute network interface device status change callback function */ @@ -728,6 +752,11 @@ void netdev_low_level_set_link_status(struct netdev *netdev, rt_bool_t is_up) /* set network interface device flags to internet down */ netdev->flags &= ~NETDEV_FLAG_INTERNET_UP; + +#ifdef NETDEV_USING_AUTO_DEFAULT + /* change to the first link_up network interface device automatically */ + netdev_auto_change_default(netdev); +#endif /* NETDEV_USING_AUTO_DEFAULT */ } /* execute link status change callback function */ @@ -937,7 +966,7 @@ static int netdev_cmd_ping(char* target_name, rt_uint32_t times, rt_size_t size) else { /* using first internet up status network interface device */ - netdev = netdev_get_first_link_up(); + netdev = netdev_get_first_by_flags(NETDEV_FLAG_LINK_UP); if (netdev == RT_NULL || NETDEV_PING_IS_COMMONICABLE(netdev) == 0) { rt_kprintf("ping: network interface device get error.\n"); diff --git a/components/net/sal_socket/dfs_net/dfs_net.c b/components/net/sal_socket/dfs_net/dfs_net.c index 37db186eff..f1a3d777a1 100644 --- a/components/net/sal_socket/dfs_net/dfs_net.c +++ b/components/net/sal_socket/dfs_net/dfs_net.c @@ -35,7 +35,9 @@ int dfs_net_getsocket(int fd) static int dfs_net_ioctl(struct dfs_fd* file, int cmd, void* args) { - return -EIO; + int socket = (int) file->data; + + return sal_ioctlsocket(socket, cmd, args); } static int dfs_net_read(struct dfs_fd* file, void *buf, size_t count) diff --git a/components/net/sal_socket/impl/af_inet_lwip.c b/components/net/sal_socket/impl/af_inet_lwip.c index cb271a55e0..95e7633635 100644 --- a/components/net/sal_socket/impl/af_inet_lwip.c +++ b/components/net/sal_socket/impl/af_inet_lwip.c @@ -217,6 +217,19 @@ static int inet_getsockname(int socket, struct sockaddr *name, socklen_t *namele return lwip_getsockname(socket, name, namelen); } +int inet_ioctlsocket(int socket, long cmd, void *arg) +{ + switch (cmd) + { + case F_GETFL: + case F_SETFL: + return lwip_fcntl(socket, cmd, (int) arg); + + default: + return lwip_ioctl(socket, cmd, arg); + } +} + #ifdef SAL_USING_POSIX static int inet_poll(struct dfs_fd *file, struct rt_pollreq *req) { @@ -278,7 +291,7 @@ static const struct sal_socket_ops lwip_socket_ops = lwip_shutdown, lwip_getpeername, inet_getsockname, - lwip_ioctl, + inet_ioctlsocket, #ifdef SAL_USING_POSIX inet_poll, #endif diff --git a/components/net/sal_socket/include/sal_socket.h b/components/net/sal_socket/include/sal_socket.h index 066258eac9..d72f1e4c3c 100644 --- a/components/net/sal_socket/include/sal_socket.h +++ b/components/net/sal_socket/include/sal_socket.h @@ -97,6 +97,10 @@ typedef uint16_t in_port_t; #define MSG_DONTWAIT 0x08 /* Nonblocking i/o for this operation only */ #define MSG_MORE 0x10 /* Sender will send more */ +/* Options for level IPPROTO_IP */ +#define IP_TOS 1 +#define IP_TTL 2 + /* Options for level IPPROTO_TCP */ #define TCP_NODELAY 0x01 /* don't delay send to coalesce packets */ #define TCP_KEEPALIVE 0x02 /* send KEEPALIVE probes when idle for pcb->keep_idle milliseconds */ @@ -107,6 +111,10 @@ typedef uint16_t in_port_t; /* Options and types related to multicast membership */ #define IP_ADD_MEMBERSHIP 3 #define IP_DROP_MEMBERSHIP 4 +/* Options and types for UDP multicast traffic handling */ +#define IP_MULTICAST_TTL 5 +#define IP_MULTICAST_IF 6 +#define IP_MULTICAST_LOOP 7 typedef struct ip_mreq { @@ -114,6 +122,27 @@ typedef struct ip_mreq struct in_addr imr_interface; /* local IP address of interface */ } ip_mreq; +/* The Type of Service provides an indication of the abstract parameters of the quality of service desired */ +#define IPTOS_TOS_MASK 0x1E +#define IPTOS_TOS(tos) ((tos) & IPTOS_TOS_MASK) +#define IPTOS_LOWDELAY 0x10 +#define IPTOS_THROUGHPUT 0x08 +#define IPTOS_RELIABILITY 0x04 +#define IPTOS_LOWCOST 0x02 +#define IPTOS_MINCOST IPTOS_LOWCOST + +/* The Network Control precedence designation is intended to be used within a network only */ +#define IPTOS_PREC_MASK 0xe0 +#define IPTOS_PREC(tos) ((tos) & IPTOS_PREC_MASK) +#define IPTOS_PREC_NETCONTROL 0xe0 +#define IPTOS_PREC_INTERNETCONTROL 0xc0 +#define IPTOS_PREC_CRITIC_ECP 0xa0 +#define IPTOS_PREC_FLASHOVERRIDE 0x80 +#define IPTOS_PREC_FLASH 0x60 +#define IPTOS_PREC_IMMEDIATE 0x40 +#define IPTOS_PREC_PRIORITY 0x20 +#define IPTOS_PREC_ROUTINE 0x00 + /* Options for shatdown type */ #ifndef SHUT_RD #define SHUT_RD 0 diff --git a/components/net/sal_socket/src/sal_socket.c b/components/net/sal_socket/src/sal_socket.c index 008a29e252..8f3149abd5 100644 --- a/components/net/sal_socket/src/sal_socket.c +++ b/components/net/sal_socket/src/sal_socket.c @@ -70,9 +70,9 @@ do { } \ }while(0) \ -#define SAL_NETDEV_IS_COMMONICABLE(netdev) \ +#define SAL_NETDEV_IS_UP(netdev) \ do { \ - if (!netdev_is_up(netdev) || !netdev_is_link_up(netdev)){ \ + if (!netdev_is_up(netdev)) { \ return -1; \ } \ }while(0) \ @@ -86,9 +86,9 @@ do { }while(0) \ #define SAL_NETDEV_NETDBOPS_VALID(netdev, pf, ops) \ -((netdev) && netdev_is_up(netdev) && netdev_is_link_up(netdev) && \ + ((netdev) && netdev_is_up(netdev) && \ ((pf) = (struct sal_proto_family *) (netdev)->sal_user_data) != RT_NULL && \ - (pf)->netdb_ops->ops) \ + (pf)->netdb_ops->ops) \ /** * SAL (Socket Abstraction Layer) initialize. @@ -387,14 +387,7 @@ static int socket_init(int family, int type, int protocol, struct sal_socket **r sock->type = type; sock->protocol = protocol; - /* get socket operations from network interface device */ - if (netdv_def == RT_NULL) - { - LOG_E("not find default network interface device for socket create."); - return -3; - } - - if (netdev_is_up(netdv_def) && netdev_is_link_up(netdv_def)) + if (netdv_def && netdev_is_up(netdv_def)) { /* check default network interface device protocol family */ pf = (struct sal_proto_family *) netdv_def->sal_user_data; @@ -755,8 +748,8 @@ int sal_connect(int socket, const struct sockaddr *name, socklen_t namelen) /* get the socket object by socket descriptor */ SAL_SOCKET_OBJ_GET(sock, socket); - /* check the network interface is commonicable */ - SAL_NETDEV_IS_COMMONICABLE(sock->netdev); + /* check the network interface is up status */ + SAL_NETDEV_IS_UP(sock->netdev); /* check the network interface socket opreation */ SAL_NETDEV_SOCKETOPS_VALID(sock->netdev, pf, connect); @@ -799,8 +792,8 @@ int sal_recvfrom(int socket, void *mem, size_t len, int flags, /* get the socket object by socket descriptor */ SAL_SOCKET_OBJ_GET(sock, socket); - /* check the network interface is commonicable */ - SAL_NETDEV_IS_COMMONICABLE(sock->netdev); + /* check the network interface is up status */ + SAL_NETDEV_IS_UP(sock->netdev); /* check the network interface socket opreation */ SAL_NETDEV_SOCKETOPS_VALID(sock->netdev, pf, recvfrom); @@ -833,8 +826,8 @@ int sal_sendto(int socket, const void *dataptr, size_t size, int flags, /* get the socket object by socket descriptor */ SAL_SOCKET_OBJ_GET(sock, socket); - /* check the network interface is commonicable */ - SAL_NETDEV_IS_COMMONICABLE(sock->netdev); + /* check the network interface is up status */ + SAL_NETDEV_IS_UP(sock->netdev); /* check the network interface socket opreation */ SAL_NETDEV_SOCKETOPS_VALID(sock->netdev, pf, sendto); @@ -972,8 +965,8 @@ int sal_poll(struct dfs_fd *file, struct rt_pollreq *req) /* get the socket object by socket descriptor */ SAL_SOCKET_OBJ_GET(sock, socket); - /* check the network interface is commonicable */ - SAL_NETDEV_IS_COMMONICABLE(sock->netdev); + /* check the network interface is up status */ + SAL_NETDEV_IS_UP(sock->netdev); /* check the network interface socket opreation */ SAL_NETDEV_SOCKETOPS_VALID(sock->netdev, pf, poll); @@ -992,8 +985,8 @@ struct hostent *sal_gethostbyname(const char *name) } else { - /* get the first network interface device with the link up status */ - netdev = netdev_get_first_link_up(); + /* get the first network interface device with up status */ + netdev = netdev_get_first_by_flags(NETDEV_FLAG_UP); if (SAL_NETDEV_NETDBOPS_VALID(netdev, pf, gethostbyname)) { return pf->netdb_ops->gethostbyname(name); @@ -1015,8 +1008,8 @@ int sal_gethostbyname_r(const char *name, struct hostent *ret, char *buf, } else { - /* get the first network interface device with the link up status */ - netdev = netdev_get_first_link_up(); + /* get the first network interface device with up status */ + netdev = netdev_get_first_by_flags(NETDEV_FLAG_UP); if (SAL_NETDEV_NETDBOPS_VALID(netdev, pf, gethostbyname_r)) { return pf->netdb_ops->gethostbyname_r(name, ret, buf, buflen, result, h_errnop); @@ -1040,8 +1033,8 @@ int sal_getaddrinfo(const char *nodename, } else { - /* get the first network interface device with the link up status */ - netdev = netdev_get_first_link_up(); + /* get the first network interface device with up status */ + netdev = netdev_get_first_by_flags(NETDEV_FLAG_UP); if (SAL_NETDEV_NETDBOPS_VALID(netdev, pf, getaddrinfo)) { return pf->netdb_ops->getaddrinfo(nodename, servname, hints, res); @@ -1062,8 +1055,8 @@ void sal_freeaddrinfo(struct addrinfo *ai) } else { - /* get the first network interface device with the link up status */ - netdev = netdev_get_first_link_up(); + /* get the first network interface device with up status */ + netdev = netdev_get_first_by_flags(NETDEV_FLAG_UP); if (SAL_NETDEV_NETDBOPS_VALID(netdev, pf, freeaddrinfo)) { pf->netdb_ops->freeaddrinfo(ai); diff --git a/components/utilities/ulog/ulog.c b/components/utilities/ulog/ulog.c index 87d0932506..36d5ac275f 100644 --- a/components/utilities/ulog/ulog.c +++ b/components/utilities/ulog/ulog.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2019, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -403,15 +403,15 @@ void ulog_output_to_all_backend(rt_uint32_t level, const char *tag, rt_bool_t is else { /* recalculate the log start address and log size when backend not supported color */ - rt_size_t color_info_len = rt_strlen(color_output_info[level]); + rt_size_t color_info_len = rt_strlen(color_output_info[level]), output_size = size; if (color_info_len) { rt_size_t color_hdr_len = rt_strlen(CSI_START) + color_info_len; log += color_hdr_len; - size -= (color_hdr_len + (sizeof(CSI_END) - 1)); + output_size -= (color_hdr_len + (sizeof(CSI_END) - 1)); } - backend->output(backend, level, tag, is_raw, log, size); + backend->output(backend, level, tag, is_raw, log, output_size); } #endif /* !defined(ULOG_USING_COLOR) || defined(ULOG_USING_SYSLOG) */ } diff --git a/examples/nanopb/SConscript b/examples/nanopb/SConscript deleted file mode 100644 index 7c8bce9f26..0000000000 --- a/examples/nanopb/SConscript +++ /dev/null @@ -1,13 +0,0 @@ -Import('RTT_ROOT') -Import('rtconfig') -from building import * - -src = Split(''' -simple.c -simple.pb.c -''') -CPPPATH = [RTT_ROOT + '/examples/nanopb'] - -group = DefineGroup('Nanopb_test', src, depend = ['RT_USING_NANOPB'], CPPPATH = CPPPATH) - -Return('group') \ No newline at end of file diff --git a/examples/nanopb/simple.c b/examples/nanopb/simple.c deleted file mode 100644 index 2b793c014f..0000000000 --- a/examples/nanopb/simple.c +++ /dev/null @@ -1,73 +0,0 @@ -#include -#include -#include -#include -#include "simple.pb.h" - -int nanopb_test() -{ - /* This is the buffer where we will store our message. */ - uint8_t buffer[128]; - size_t message_length; - bool status; - - /* Encode our message */ - { - /* Allocate space on the stack to store the message data. - * - * Nanopb generates simple struct definitions for all the messages. - * - check out the contents of simple.pb.h! */ - SimpleMessage message = SimpleMessage_init_zero; - - /* Create a stream that will write to our buffer. */ - pb_ostream_t stream = pb_ostream_from_buffer(buffer, sizeof(buffer)); - - /* Fill in the lucky number */ - message.lucky_number = 13; - - /* Now we are ready to encode the message! */ - status = pb_encode(&stream, SimpleMessage_fields, &message); - message_length = stream.bytes_written; - - /* Then just check for any errors.. */ - if (!status) - { - rt_kprintf("Encoding failed: %s\n", PB_GET_ERROR(&stream)); - return 1; - } - } - - /* Now we could transmit the message over network, store it in a file or - * wrap it to a pigeon's leg. - */ - - /* But because we are lazy, we will just decode it immediately. */ - - { - /* Allocate space for the decoded message. */ - SimpleMessage message; - - /* Create a stream that reads from the buffer. */ - pb_istream_t stream = pb_istream_from_buffer(buffer, message_length); - - /* Now we are ready to decode the message. */ - status = pb_decode(&stream, SimpleMessage_fields, &message); - - /* Check for errors... */ - if (!status) - { - rt_kprintf("Decoding failed: %s\n", PB_GET_ERROR(&stream)); - return 1; - } - - /* Print the data contained in the message. */ - rt_kprintf("Your lucky number was %d!\n", message.lucky_number); - } - - return 0; -} - -#ifdef RT_USING_FINSH -#include -FINSH_FUNCTION_EXPORT(nanopb_test, nanopb encode/decode test.) -#endif diff --git a/examples/nanopb/simple.options b/examples/nanopb/simple.options deleted file mode 100644 index 90960d0d34..0000000000 --- a/examples/nanopb/simple.options +++ /dev/null @@ -1 +0,0 @@ -SimpleMessage.name max_size:16 \ No newline at end of file diff --git a/examples/nanopb/simple.pb.c b/examples/nanopb/simple.pb.c deleted file mode 100644 index eaf09e58da..0000000000 --- a/examples/nanopb/simple.pb.c +++ /dev/null @@ -1,18 +0,0 @@ -/* Automatically generated nanopb constant definitions */ -/* Generated by nanopb-0.3.1 at Tue Mar 10 01:16:15 2015. */ - -#include "simple.pb.h" - -#if PB_PROTO_HEADER_VERSION != 30 -#error Regenerate this file with the current version of nanopb generator. -#endif - - - -const pb_field_t SimpleMessage_fields[3] = { - PB_FIELD( 1, INT32 , REQUIRED, STATIC , FIRST, SimpleMessage, lucky_number, lucky_number, 0), - PB_FIELD( 2, BYTES , REQUIRED, STATIC , OTHER, SimpleMessage, name, lucky_number, 0), - PB_LAST_FIELD -}; - - diff --git a/examples/nanopb/simple.pb.h b/examples/nanopb/simple.pb.h deleted file mode 100644 index 47521dee69..0000000000 --- a/examples/nanopb/simple.pb.h +++ /dev/null @@ -1,45 +0,0 @@ -/* Automatically generated nanopb header */ -/* Generated by nanopb-0.3.1 at Tue Mar 10 01:16:15 2015. */ - -#ifndef PB_SIMPLE_PB_H_INCLUDED -#define PB_SIMPLE_PB_H_INCLUDED -#include - -#if PB_PROTO_HEADER_VERSION != 30 -#error Regenerate this file with the current version of nanopb generator. -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/* Enum definitions */ -/* Struct definitions */ -typedef PB_BYTES_ARRAY_T(16) SimpleMessage_name_t; - -typedef struct _SimpleMessage { - int32_t lucky_number; - SimpleMessage_name_t name; -} SimpleMessage; - -/* Default values for struct fields */ - -/* Initializer values for message structs */ -#define SimpleMessage_init_default {0, {0, {0}}} -#define SimpleMessage_init_zero {0, {0, {0}}} - -/* Field tags (for use in manual encoding/decoding) */ -#define SimpleMessage_lucky_number_tag 1 -#define SimpleMessage_name_tag 2 - -/* Struct field encoding specification for nanopb */ -extern const pb_field_t SimpleMessage_fields[3]; - -/* Maximum encoded size of messages (where known) */ -#define SimpleMessage_size 29 - -#ifdef __cplusplus -} /* extern "C" */ -#endif - -#endif diff --git a/examples/nanopb/simple.proto b/examples/nanopb/simple.proto deleted file mode 100644 index 1905d0e50b..0000000000 --- a/examples/nanopb/simple.proto +++ /dev/null @@ -1,10 +0,0 @@ -// A very simple protocol definition, consisting of only -// one message. - -message SimpleMessage { - required int32 lucky_number = 1; - required bytes name = 2; -} - - - diff --git a/examples/pm/timer_app.c b/examples/pm/timer_app.c index 5c20d0f690..b7ff675b39 100644 --- a/examples/pm/timer_app.c +++ b/examples/pm/timer_app.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2018-08-07 Tanek first implementation + * 2019-05-06 Zero-Free adapt to the new power management interface */ #include @@ -39,7 +40,7 @@ static int timer_app_init(void) rt_timer_start(timer1); /* keep in timer mode */ - rt_pm_request(PM_SLEEP_MODE_TIMER); + rt_pm_request(PM_SLEEP_MODE_DEEP); return 0; } diff --git a/examples/pm/wakeup_app.c b/examples/pm/wakeup_app.c new file mode 100644 index 0000000000..0d4c42a997 --- /dev/null +++ b/examples/pm/wakeup_app.c @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-05-09 Zero-Free first implementation + */ + +#include +#include +#include + +#ifdef RT_USING_PM + +#define WAKEUP_EVENT_BUTTON (1 << 0) +#define PIN_LED_R GET_PIN(E, 7) +#define WAKEUP_PIN GET_PIN(C, 13) +#define WAKEUP_APP_THREAD_STACK_SIZE 1024 + +static rt_event_t wakeup_event; + +static void wakeup_callback(void *args) +{ + rt_event_send(wakeup_event, WAKEUP_EVENT_BUTTON); +} + +static void wakeup_init(void) +{ + rt_pin_mode(WAKEUP_PIN, PIN_MODE_INPUT_PULLUP); + rt_pin_attach_irq(WAKEUP_PIN, PIN_IRQ_MODE_FALLING, wakeup_callback, RT_NULL); + rt_pin_irq_enable(WAKEUP_PIN, 1); +} + +static void wakeup_app_entry(void *parameter) +{ + wakeup_init(); + rt_pm_request(PM_SLEEP_MODE_DEEP); + + while (1) + { + if (rt_event_recv(wakeup_event, + WAKEUP_EVENT_BUTTON, + RT_EVENT_FLAG_AND | RT_EVENT_FLAG_CLEAR, + RT_WAITING_FOREVER, RT_NULL) == RT_EOK) + { + rt_pm_request(PM_SLEEP_MODE_NONE); + + rt_pin_mode(PIN_LED_R, PIN_MODE_OUTPUT); + rt_pin_write(PIN_LED_R, 0); + rt_thread_delay(rt_tick_from_millisecond(500)); + rt_pin_write(PIN_LED_R, 1); + + rt_pm_release(PM_SLEEP_MODE_NONE); + } + } +} + +static int wakeup_app(void) +{ + rt_thread_t tid; + + wakeup_event = rt_event_create("wakup", RT_IPC_FLAG_FIFO); + RT_ASSERT(wakeup_event != RT_NULL); + + tid = rt_thread_create("wakeup_app", wakeup_app_entry, RT_NULL, + WAKEUP_APP_THREAD_STACK_SIZE, RT_MAIN_THREAD_PRIORITY, 20); + RT_ASSERT(tid != RT_NULL); + + rt_thread_startup(tid); + + return 0; +} +INIT_APP_EXPORT(wakeup_app); + +#endif diff --git a/include/rtdef.h b/include/rtdef.h index 743b91d959..2aff4afdb0 100644 --- a/include/rtdef.h +++ b/include/rtdef.h @@ -492,9 +492,10 @@ typedef siginfo_t rt_siginfo_t; #define RT_THREAD_CLOSE 0x04 /**< Closed status */ #define RT_THREAD_STAT_MASK 0x0f -#define RT_THREAD_STAT_SIGNAL 0x10 +#define RT_THREAD_STAT_SIGNAL 0x10 /**< task hold signals */ #define RT_THREAD_STAT_SIGNAL_READY (RT_THREAD_STAT_SIGNAL | RT_THREAD_READY) -#define RT_THREAD_STAT_SIGNAL_WAIT 0x20 +#define RT_THREAD_STAT_SIGNAL_WAIT 0x20 /**< task is waiting for signals */ +#define RT_THREAD_STAT_SIGNAL_PENDING 0x40 /**< signals is held and it has not been procressed */ #define RT_THREAD_STAT_SIGNAL_MASK 0xf0 /** @@ -596,7 +597,9 @@ struct rt_thread rt_sigset_t sig_pending; /**< the pending signals */ rt_sigset_t sig_mask; /**< the mask bits of signal */ +#ifndef RT_USING_SMP void *sig_ret; /**< the return stack pointer from signal */ +#endif rt_sighandler_t *sig_vectors; /**< vectors of signal handler */ void *si_list; /**< the signal infor list */ #endif diff --git a/include/rthw.h b/include/rthw.h index dee10b0bee..ef3dc087ad 100644 --- a/include/rthw.h +++ b/include/rthw.h @@ -153,10 +153,11 @@ extern rt_hw_spinlock_t _rt_critical_lock; #define __RT_HW_SPIN_LOCK_INITIALIZER(lockname) {0} -#define __RT_HW_SPIN_LOCK_UNLOCKED(lockname) \ - (struct rt_hw_spinlock ) __RT_HW_SPIN_LOCK_INITIALIZER(lockname) +#define __RT_HW_SPIN_LOCK_UNLOCKED(lockname) \ + (rt_hw_spinlock_t) __RT_HW_SPIN_LOCK_INITIALIZER(lockname) -#define RT_DEFINE_SPINLOCK(x) struct rt_hw_spinlock x = __RT_HW_SPIN_LOCK_UNLOCKED(x) +#define RT_DEFINE_SPINLOCK(x) rt_hw_spinlock_t x = __RT_HW_SPIN_LOCK_UNLOCKED(x) +#define RT_DECLARE_SPINLOCK(x) /** * ipi function @@ -172,6 +173,13 @@ void rt_hw_secondary_cpu_up(void); * secondary cpu idle function */ void rt_hw_secondary_cpu_idle_exec(void); +#else + +#define RT_DEFINE_SPINLOCK(x) +#define RT_DECLARE_SPINLOCK(x) rt_ubase_t x + +#define rt_hw_spin_lock(lock) *(lock) = rt_hw_interrupt_disable() +#define rt_hw_spin_unlock(lock) rt_hw_interrupt_enable(*(lock)) #endif diff --git a/libcpu/arm/arm926/trap.c b/libcpu/arm/arm926/trap.c index de04c3f8cb..9e7ba48037 100644 --- a/libcpu/arm/arm926/trap.c +++ b/libcpu/arm/arm926/trap.c @@ -197,14 +197,14 @@ void rt_hw_trap_resv(struct rt_hw_register *regs) rt_hw_cpu_shutdown(); } -extern void rt_interrupt_dispatch(void); +extern void rt_interrupt_dispatch(rt_uint32_t fiq_irq); void rt_hw_trap_irq(void) { - rt_interrupt_dispatch(); + rt_interrupt_dispatch(INT_IRQ); } void rt_hw_trap_fiq(void) { - rt_interrupt_dispatch(); + rt_interrupt_dispatch(INT_FIQ); } diff --git a/libcpu/arm/cortex-a/context_gcc.S b/libcpu/arm/cortex-a/context_gcc.S index b009630fa8..dff7a1de68 100644 --- a/libcpu/arm/cortex-a/context_gcc.S +++ b/libcpu/arm/cortex-a/context_gcc.S @@ -34,8 +34,9 @@ rt_hw_interrupt_enable: bx lr /* - * void rt_hw_context_switch_to(rt_uint32 to); - * r0 --> to + * void rt_hw_context_switch_to(rt_uint32 to, struct rt_thread *to_thread); + * r0 --> to (thread stack) + * r1 --> to_thread */ .globl rt_hw_context_switch_to rt_hw_context_switch_to: @@ -45,16 +46,7 @@ rt_hw_context_switch_to: mov r0, r1 bl rt_cpus_lock_status_restore #endif /*RT_USING_SMP*/ - -#ifdef RT_USING_LWP - ldmfd sp, {r13, r14}^ @ pop usr_sp usr_lr - add sp, #8 -#endif - - ldmfd sp!, {r4} @ pop new task spsr - msr spsr_cxsf, r4 - - ldmfd sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc + b rt_hw_context_switch_exit .section .bss.share.isr _guest_switch_lvl: @@ -64,9 +56,10 @@ _guest_switch_lvl: .section .text.isr, "ax" /* - * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); - * r0 --> from - * r1 --> to + * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to, struct rt_thread *to_thread); + * r0 --> from (from_thread stack) + * r1 --> to (to_thread stack) + * r2 --> to_thread */ .globl rt_hw_context_switch rt_hw_context_switch: @@ -91,15 +84,7 @@ rt_hw_context_switch: mov r0, r2 bl rt_cpus_lock_status_restore #endif /*RT_USING_SMP*/ - -#ifdef RT_USING_LWP - ldmfd sp, {r13, r14}^ @ pop usr_sp usr_lr - add sp, #8 -#endif - - ldmfd sp!, {r4} @ pop new task cpsr to spsr - msr spsr_cxsf, r4 - ldmfd sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc, copy spsr to cpsr + b rt_hw_context_switch_exit /* * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); @@ -121,51 +106,19 @@ rt_hw_context_switch: .globl rt_hw_context_switch_interrupt rt_hw_context_switch_interrupt: #ifdef RT_USING_SMP - /* r0 :irq_mod context + /* r0 :svc_mod context * r1 :addr of from_thread's sp * r2 :addr of to_thread's sp * r3 :to_thread's tcb */ - @ r0 point to {r0-r3} in stack - push {r1 - r3} - mov r1, r0 - add r0, r0, #4*4 - ldmfd r0!, {r4-r12,lr}@ reload saved registers - mrs r3, spsr @ get cpsr of interrupt thread - sub r2, lr, #4 @ save old task's pc to r2 - msr cpsr_c, #I_Bit|F_Bit|Mode_SVC - - stmfd sp!, {r2} @ push old task's pc - stmfd sp!, {r4-r12,lr}@ push old task's lr,r12-r4 - ldmfd r1, {r4-r7} @ restore r0-r3 of the interrupt thread - stmfd sp!, {r4-r7} @ push old task's r0-r3 - stmfd sp!, {r3} @ push old task's cpsr - -#ifdef RT_USING_LWP - stmfd sp, {r13,r14}^ @push usr_sp usr_lr - sub sp, #8 -#endif - - msr cpsr_c, #I_Bit|F_Bit|Mode_IRQ - pop {r1 - r3} - mov sp, r0 - msr cpsr_c, #I_Bit|F_Bit|Mode_SVC - str sp, [r1] + str r0, [r1] ldr sp, [r2] mov r0, r3 bl rt_cpus_lock_status_restore -#ifdef RT_USING_LWP - ldmfd sp, {r13,r14}^ @pop usr_sp usr_lr - add sp, #8 -#endif - - ldmfd sp!, {r4} @ pop new task's cpsr to spsr - msr spsr_cxsf, r4 - - ldmfd sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr + b rt_hw_context_switch_exit #else /*RT_USING_SMP*/ ldr r2, =rt_thread_switch_interrupt_flag @@ -181,3 +134,25 @@ _reswitch: str r1, [r2] bx lr #endif /*RT_USING_SMP*/ + +.global rt_hw_context_switch_exit +rt_hw_context_switch_exit: + +#ifdef RT_USING_SMP +#ifdef RT_USING_SIGNALS + mov r0, sp + cps #Mode_IRQ + bl rt_signal_check + cps #Mode_SVC + mov sp, r0 +#endif +#endif + +#ifdef RT_USING_LWP + ldmfd sp, {r13, r14}^ /* usr_sp, usr_lr */ + add sp, #8 +#endif + ldmfd sp!, {r1} + msr spsr_cxsf, r1 /* original mode */ + ldmfd sp!, {r0-r12,lr,pc}^ /* irq return */ + diff --git a/libcpu/arm/cortex-a/interrupt.h b/libcpu/arm/cortex-a/interrupt.h index 31f79cc66e..442187edee 100644 --- a/libcpu/arm/cortex-a/interrupt.h +++ b/libcpu/arm/cortex-a/interrupt.h @@ -17,6 +17,8 @@ #define INT_IRQ 0x00 #define INT_FIQ 0x01 +void rt_hw_vector_init(void); + void rt_hw_interrupt_control(int vector, int priority, int route); void rt_hw_interrupt_init(void); diff --git a/libcpu/arm/cortex-a/start_gcc.S b/libcpu/arm/cortex-a/start_gcc.S index 51026b7ed5..014846f3aa 100644 --- a/libcpu/arm/cortex-a/start_gcc.S +++ b/libcpu/arm/cortex-a/start_gcc.S @@ -11,7 +11,6 @@ */ #include "rtconfig.h" - .equ Mode_USR, 0x10 .equ Mode_FIQ, 0x11 .equ Mode_IRQ, 0x12 @@ -158,20 +157,48 @@ vector_fiq: vector_irq: #ifdef RT_USING_SMP clrex + + stmfd sp!, {r0, r1} + cps #Mode_SVC + mov r0, sp /* svc_sp */ + mov r1, lr /* svc_lr */ + + cps #Mode_IRQ + sub lr, #4 + stmfd r0!, {r1, lr} /* svc_lr, svc_pc */ + stmfd r0!, {r2 - r12} + ldmfd sp!, {r1, r2} /* original r0, r1 */ + stmfd r0!, {r1 - r2} + mrs r1, spsr /* original mode */ + stmfd r0!, {r1} + +#ifdef RT_USING_LWP + stmfd r0, {r13, r14}^ /* usr_sp, usr_lr */ + sub r0, #8 #endif + /* now irq stack is clean */ + /* r0 is task svc_sp */ + /* backup r0 -> r8 */ + mov r8, r0 + + bl rt_interrupt_enter + bl rt_hw_trap_irq + bl rt_interrupt_leave + + cps #Mode_SVC + mov sp, r8 + mov r0, r8 + bl rt_scheduler_do_irq_switch + + b rt_hw_context_switch_exit + +#else stmfd sp!, {r0-r12,lr} bl rt_interrupt_enter bl rt_hw_trap_irq bl rt_interrupt_leave -#ifdef RT_USING_SMP - mov r0, sp - bl rt_scheduler_do_irq_switch - - ldmfd sp!, {r0-r12,lr} - subs pc, lr, #4 -#else @ if rt_thread_switch_interrupt_flag set, jump to @ rt_hw_context_switch_interrupt_do and don't return ldr r0, =rt_thread_switch_interrupt_flag diff --git a/libcpu/risc-v/common/context_gcc.S b/libcpu/risc-v/common/context_gcc.S index 62e64d8104..f28b15319b 100644 --- a/libcpu/risc-v/common/context_gcc.S +++ b/libcpu/risc-v/common/context_gcc.S @@ -49,45 +49,9 @@ rt_hw_context_switch_to: mv a0, a1 jal rt_cpus_lock_status_restore #endif - - /* load epc from stack */ - LOAD a0, 0 * REGBYTES(sp) - csrw mepc, a0 - LOAD x1, 1 * REGBYTES(sp) - /* load mstatus from stack */ LOAD a0, 2 * REGBYTES(sp) csrw mstatus, a0 - LOAD x4, 4 * REGBYTES(sp) - LOAD x5, 5 * REGBYTES(sp) - LOAD x6, 6 * REGBYTES(sp) - LOAD x7, 7 * REGBYTES(sp) - LOAD x8, 8 * REGBYTES(sp) - LOAD x9, 9 * REGBYTES(sp) - LOAD x10, 10 * REGBYTES(sp) - LOAD x11, 11 * REGBYTES(sp) - LOAD x12, 12 * REGBYTES(sp) - LOAD x13, 13 * REGBYTES(sp) - LOAD x14, 14 * REGBYTES(sp) - LOAD x15, 15 * REGBYTES(sp) - LOAD x16, 16 * REGBYTES(sp) - LOAD x17, 17 * REGBYTES(sp) - LOAD x18, 18 * REGBYTES(sp) - LOAD x19, 19 * REGBYTES(sp) - LOAD x20, 20 * REGBYTES(sp) - LOAD x21, 21 * REGBYTES(sp) - LOAD x22, 22 * REGBYTES(sp) - LOAD x23, 23 * REGBYTES(sp) - LOAD x24, 24 * REGBYTES(sp) - LOAD x25, 25 * REGBYTES(sp) - LOAD x26, 26 * REGBYTES(sp) - LOAD x27, 27 * REGBYTES(sp) - LOAD x28, 28 * REGBYTES(sp) - LOAD x29, 29 * REGBYTES(sp) - LOAD x30, 30 * REGBYTES(sp) - LOAD x31, 31 * REGBYTES(sp) - - addi sp, sp, 32 * REGBYTES - mret + j rt_hw_context_switch_exit /* * #ifdef RT_USING_SMP @@ -102,7 +66,6 @@ rt_hw_context_switch_to: */ .globl rt_hw_context_switch rt_hw_context_switch: - /* saved from thread context * x1/ra -> sp(0) * x1/ra -> sp(1) @@ -163,48 +126,7 @@ save_mpie: jal rt_cpus_lock_status_restore #endif /*RT_USING_SMP*/ - /* resw ra to mepc */ - LOAD a1, 0 * REGBYTES(sp) - csrw mepc, a1 - LOAD x1, 1 * REGBYTES(sp) - - /* force to machin mode(MPP=11) */ - li a1, 0x00001800; - csrs mstatus, a1 - LOAD a1, 2 * REGBYTES(sp) - csrs mstatus, a1 - - LOAD x4, 4 * REGBYTES(sp) - LOAD x5, 5 * REGBYTES(sp) - LOAD x6, 6 * REGBYTES(sp) - LOAD x7, 7 * REGBYTES(sp) - LOAD x8, 8 * REGBYTES(sp) - LOAD x9, 9 * REGBYTES(sp) - LOAD x10, 10 * REGBYTES(sp) - LOAD x11, 11 * REGBYTES(sp) - LOAD x12, 12 * REGBYTES(sp) - LOAD x13, 13 * REGBYTES(sp) - LOAD x14, 14 * REGBYTES(sp) - LOAD x15, 15 * REGBYTES(sp) - LOAD x16, 16 * REGBYTES(sp) - LOAD x17, 17 * REGBYTES(sp) - LOAD x18, 18 * REGBYTES(sp) - LOAD x19, 19 * REGBYTES(sp) - LOAD x20, 20 * REGBYTES(sp) - LOAD x21, 21 * REGBYTES(sp) - LOAD x22, 22 * REGBYTES(sp) - LOAD x23, 23 * REGBYTES(sp) - LOAD x24, 24 * REGBYTES(sp) - LOAD x25, 25 * REGBYTES(sp) - LOAD x26, 26 * REGBYTES(sp) - LOAD x27, 27 * REGBYTES(sp) - LOAD x28, 28 * REGBYTES(sp) - LOAD x29, 29 * REGBYTES(sp) - LOAD x30, 30 * REGBYTES(sp) - LOAD x31, 31 * REGBYTES(sp) - - addi sp, sp, 32 * REGBYTES - mret + j rt_hw_context_switch_exit #ifdef RT_USING_SMP /* @@ -220,26 +142,42 @@ rt_hw_context_switch_interrupt: STORE a0, 0(a1) - csrr a1, mepc - STORE a1, 0 * REGBYTES(a0) - - csrr a1, mstatus - STORE a1, 2 * REGBYTES(a0) - LOAD sp, 0(a2) move a0, a3 call rt_cpus_lock_status_restore + j rt_hw_context_switch_exit + +#endif + +.global rt_hw_context_switch_exit +rt_hw_context_switch_exit: +#ifdef RT_USING_SMP +#ifdef RT_USING_SIGNALS + mv a0, sp + + csrr t0, mhartid + /* switch interrupt stack of current cpu */ + la sp, __stack_start__ + addi t1, t0, 1 + li t2, __STACKSIZE__ + mul t1, t1, t2 + add sp, sp, t1 /* sp = (cpuid + 1) * __STACKSIZE__ + __stack_start__ */ + + call rt_signal_check + mv sp, a0 +#endif +#endif /* resw ra to mepc */ - LOAD a1, 0 * REGBYTES(sp) - csrw mepc, a1 + LOAD a0, 0 * REGBYTES(sp) + csrw mepc, a0 + LOAD x1, 1 * REGBYTES(sp) - /* force to machin mode(MPP=11) */ - li a1, 0x00001800; - csrs mstatus, a1 - LOAD a1, 2 * REGBYTES(sp) - csrs mstatus, a1 + li t0, 0x00001800 + csrs mstatus, t0 + LOAD a0, 2 * REGBYTES(sp) + csrs mstatus, a0 LOAD x4, 4 * REGBYTES(sp) LOAD x5, 5 * REGBYTES(sp) @@ -272,5 +210,3 @@ rt_hw_context_switch_interrupt: addi sp, sp, 32 * REGBYTES mret - -#endif diff --git a/libcpu/risc-v/k210/interrupt_gcc.S b/libcpu/risc-v/k210/interrupt_gcc.S index aeda72ab31..0393ea51f8 100644 --- a/libcpu/risc-v/k210/interrupt_gcc.S +++ b/libcpu/risc-v/k210/interrupt_gcc.S @@ -20,8 +20,12 @@ trap_entry: addi sp, sp, -32 * REGBYTES STORE x1, 1 * REGBYTES(sp) - li t0, 0x80 - STORE t0, 2 * REGBYTES(sp) + + csrr x1, mstatus + STORE x1, 2 * REGBYTES(sp) + + csrr x1, mepc + STORE x1, 0 * REGBYTES(sp) STORE x4, 4 * REGBYTES(sp) STORE x5, 5 * REGBYTES(sp) @@ -75,9 +79,11 @@ trap_entry: #ifdef RT_USING_SMP /* s0 --> sp */ + mv sp, s0 mv a0, s0 call rt_scheduler_do_irq_switch - mv sp, s0 + j rt_hw_context_switch_exit + #else /* switch to from_thread stack */ @@ -89,9 +95,6 @@ trap_entry: beqz s2, spurious_interrupt sw zero, 0(s0) - csrr a0, mepc - STORE a0, 0 * REGBYTES(sp) - la s0, rt_interrupt_from_thread LOAD s1, 0(s0) STORE sp, 0(s1) @@ -100,47 +103,7 @@ trap_entry: LOAD s1, 0(s0) LOAD sp, 0(s1) - LOAD a0, 0 * REGBYTES(sp) - csrw mepc, a0 #endif spurious_interrupt: - LOAD x1, 1 * REGBYTES(sp) - - /* Remain in M-mode after mret */ - li t0, 0x00001800 - csrs mstatus, t0 - LOAD t0, 2 * REGBYTES(sp) - csrs mstatus, t0 - - LOAD x4, 4 * REGBYTES(sp) - LOAD x5, 5 * REGBYTES(sp) - LOAD x6, 6 * REGBYTES(sp) - LOAD x7, 7 * REGBYTES(sp) - LOAD x8, 8 * REGBYTES(sp) - LOAD x9, 9 * REGBYTES(sp) - LOAD x10, 10 * REGBYTES(sp) - LOAD x11, 11 * REGBYTES(sp) - LOAD x12, 12 * REGBYTES(sp) - LOAD x13, 13 * REGBYTES(sp) - LOAD x14, 14 * REGBYTES(sp) - LOAD x15, 15 * REGBYTES(sp) - LOAD x16, 16 * REGBYTES(sp) - LOAD x17, 17 * REGBYTES(sp) - LOAD x18, 18 * REGBYTES(sp) - LOAD x19, 19 * REGBYTES(sp) - LOAD x20, 20 * REGBYTES(sp) - LOAD x21, 21 * REGBYTES(sp) - LOAD x22, 22 * REGBYTES(sp) - LOAD x23, 23 * REGBYTES(sp) - LOAD x24, 24 * REGBYTES(sp) - LOAD x25, 25 * REGBYTES(sp) - LOAD x26, 26 * REGBYTES(sp) - LOAD x27, 27 * REGBYTES(sp) - LOAD x28, 28 * REGBYTES(sp) - LOAD x29, 29 * REGBYTES(sp) - LOAD x30, 30 * REGBYTES(sp) - LOAD x31, 31 * REGBYTES(sp) - - addi sp, sp, 32 * REGBYTES - mret + j rt_hw_context_switch_exit diff --git a/src/cpu.c b/src/cpu.c index 3e2d65dfb9..fe3ba21bb0 100644 --- a/src/cpu.c +++ b/src/cpu.c @@ -42,12 +42,16 @@ rt_base_t rt_cpus_lock(void) pcpu = rt_cpu_self(); if (pcpu->current_thread != RT_NULL) { - if (pcpu->current_thread->cpus_lock_nest++ == 0) + register rt_uint16_t lock_nest = pcpu->current_thread->cpus_lock_nest; + + pcpu->current_thread->cpus_lock_nest++; + if (lock_nest == 0) { pcpu->current_thread->scheduler_lock_nest++; rt_hw_spin_lock(&_cpus_lock); } } + return level; } RTM_EXPORT(rt_cpus_lock); @@ -61,7 +65,9 @@ void rt_cpus_unlock(rt_base_t level) if (pcpu->current_thread != RT_NULL) { - if (--pcpu->current_thread->cpus_lock_nest == 0) + pcpu->current_thread->cpus_lock_nest--; + + if (pcpu->current_thread->cpus_lock_nest == 0) { pcpu->current_thread->scheduler_lock_nest--; rt_hw_spin_unlock(&_cpus_lock); diff --git a/src/idle.c b/src/idle.c index e685a7ddfc..77b0424892 100644 --- a/src/idle.c +++ b/src/idle.c @@ -228,6 +228,7 @@ void rt_thread_idle_excute(void) } } +extern void rt_system_power_manager(void); static void rt_thread_idle_entry(void *parameter) { #ifdef RT_USING_SMP @@ -255,6 +256,9 @@ static void rt_thread_idle_entry(void *parameter) #endif rt_thread_idle_excute(); +#ifdef RT_USING_PM + rt_system_power_manager(); +#endif } } diff --git a/src/ipc.c b/src/ipc.c index 74faf6ac7e..0df4f05f23 100644 --- a/src/ipc.c +++ b/src/ipc.c @@ -753,8 +753,8 @@ __again: if (thread->error != RT_EOK) { - /* interrupt by signal, try it again */ - if (thread->error == -RT_EINTR) goto __again; + /* interrupt by signal, try it again */ + if (thread->error == -RT_EINTR) goto __again; /* return error */ return thread->error; diff --git a/src/scheduler.c b/src/scheduler.c index be29d9a7e0..b487bd4b60 100644 --- a/src/scheduler.c +++ b/src/scheduler.c @@ -128,17 +128,9 @@ static struct rt_thread* _get_highest_priority_thread(rt_ubase_t *highest_prio) register struct rt_thread *highest_priority_thread; register rt_ubase_t highest_ready_priority, local_highest_ready_priority; struct rt_cpu* pcpu = rt_cpu_self(); - #if RT_THREAD_PRIORITY_MAX > 32 register rt_ubase_t number; - if (rt_thread_ready_priority_group == 0 && pcpu->priority_group == 0) - { - *highest_prio = pcpu->current_thread->current_priority; - /* only local IDLE is readly */ - return pcpu->current_thread; - } - number = __rt_ffs(rt_thread_ready_priority_group) - 1; highest_ready_priority = (number << 3) + __rt_ffs(rt_thread_ready_table[number]) - 1; number = __rt_ffs(pcpu->priority_group) - 1; @@ -322,8 +314,23 @@ void rt_schedule(void) if (pcpu->irq_nest) { pcpu->irq_switch_flag = 1; + rt_hw_interrupt_enable(level); + goto __exit; } - else if (current_thread->scheduler_lock_nest == 1) /* whether lock scheduler */ + +#ifdef RT_USING_SIGNALS + if ((current_thread->stat & RT_THREAD_STAT_MASK) == RT_THREAD_SUSPEND) + { + /* if current_thread signal is in pending */ + + if ((current_thread->stat & RT_THREAD_STAT_SIGNAL_MASK) & RT_THREAD_STAT_SIGNAL_PENDING) + { + rt_thread_resume(current_thread); + } + } +#endif + + if (current_thread->scheduler_lock_nest == 1) /* whether lock scheduler */ { rt_ubase_t highest_ready_priority; @@ -366,27 +373,32 @@ void rt_schedule(void) _rt_scheduler_stack_check(to_thread); #endif - { - extern void rt_thread_handle_sig(rt_bool_t clean_state); - - rt_hw_context_switch((rt_ubase_t)¤t_thread->sp, - (rt_ubase_t)&to_thread->sp, to_thread); - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - -#ifdef RT_USING_SIGNALS - /* check signal status */ - rt_thread_handle_sig(RT_TRUE); -#endif - goto __exit; - } + rt_hw_context_switch((rt_ubase_t)¤t_thread->sp, + (rt_ubase_t)&to_thread->sp, to_thread); } } } +#ifdef RT_USING_SIGNALS + if (current_thread->stat & RT_THREAD_STAT_SIGNAL_PENDING) + { + extern void rt_thread_handle_sig(rt_bool_t clean_state); + + current_thread->stat &= ~RT_THREAD_STAT_SIGNAL_PENDING; + + rt_hw_interrupt_enable(level); + + /* check signal status */ + rt_thread_handle_sig(RT_TRUE); + } + else + { + rt_hw_interrupt_enable(level); + } +#else /* enable interrupt */ rt_hw_interrupt_enable(level); +#endif __exit: return ; @@ -465,13 +477,25 @@ void rt_schedule(void) rt_hw_context_switch((rt_ubase_t)&from_thread->sp, (rt_ubase_t)&to_thread->sp); +#ifdef RT_USING_SIGNALS + if (rt_current_thread->stat & RT_THREAD_STAT_SIGNAL_PENDING) + { + extern void rt_thread_handle_sig(rt_bool_t clean_state); + rt_current_thread->stat &= ~RT_THREAD_STAT_SIGNAL_PENDING; + + rt_hw_interrupt_enable(level); + + /* check signal status */ + rt_thread_handle_sig(RT_TRUE); + } + else + { + rt_hw_interrupt_enable(level); + } +#else /* enable interrupt */ rt_hw_interrupt_enable(level); - -#ifdef RT_USING_SIGNALS - /* check signal status */ - rt_thread_handle_sig(RT_TRUE); #endif goto __exit; } @@ -519,6 +543,18 @@ void rt_scheduler_do_irq_switch(void *context) pcpu = rt_cpu_index(cpu_id); current_thread = pcpu->current_thread; +#ifdef RT_USING_SIGNALS + if ((current_thread->stat & RT_THREAD_STAT_MASK) == RT_THREAD_SUSPEND) + { + /* if current_thread signal is in pending */ + + if ((current_thread->stat & RT_THREAD_STAT_SIGNAL_MASK) & RT_THREAD_STAT_SIGNAL_PENDING) + { + rt_thread_resume(current_thread); + } + } +#endif + if (pcpu->irq_switch_flag == 0) { rt_hw_interrupt_enable(level); diff --git a/src/signal.c b/src/signal.c index 06c2055d26..bea3615d34 100644 --- a/src/signal.c +++ b/src/signal.c @@ -23,7 +23,7 @@ #endif #define DBG_TAG "SIGN" -#define DBG_LVL DBG_INFO +#define DBG_LVL DBG_WARNING #include #define sig_mask(sig_no) (1u << sig_no) @@ -52,17 +52,28 @@ static void _signal_entry(void *parameter) /* handle signal */ rt_thread_handle_sig(RT_FALSE); - /* never come back... */ - rt_hw_interrupt_disable(); +#ifdef RT_USING_SMP + { + struct rt_cpu* pcpu = rt_cpu_self(); + + pcpu->current_thread->cpus_lock_nest--; + if (pcpu->current_thread->cpus_lock_nest == 0) + { + pcpu->current_thread->scheduler_lock_nest--; + } + + } +#else /* return to thread */ tid->sp = tid->sig_ret; tid->sig_ret = RT_NULL; +#endif LOG_D("switch back to: 0x%08x\n", tid->sp); tid->stat &= ~RT_THREAD_STAT_SIGNAL; #ifdef RT_USING_SMP - rt_hw_context_switch_to((rt_ubase_t)&(tid->sp), tid); + rt_hw_context_switch_to((rt_base_t)¶meter, tid); #else rt_hw_context_switch_to((rt_ubase_t)&(tid->sp)); #endif /*RT_USING_SMP*/ @@ -82,16 +93,21 @@ static void _signal_deliver(rt_thread_t tid) { rt_ubase_t level; - /* thread is not interested in pended signals */ - if (!(tid->sig_pending & tid->sig_mask)) return; - level = rt_hw_interrupt_disable(); + + /* thread is not interested in pended signals */ + if (!(tid->sig_pending & tid->sig_mask)) + { + rt_hw_interrupt_enable(level); + return; + } + if ((tid->stat & RT_THREAD_STAT_MASK) == RT_THREAD_SUSPEND) { /* resume thread to handle signal */ rt_thread_resume(tid); /* add signal state */ - tid->stat |= RT_THREAD_STAT_SIGNAL; + tid->stat |= (RT_THREAD_STAT_SIGNAL | RT_THREAD_STAT_SIGNAL_PENDING); rt_hw_interrupt_enable(level); @@ -108,17 +124,36 @@ static void _signal_deliver(rt_thread_t tid) rt_hw_interrupt_enable(level); /* do signal action in self thread context */ - rt_thread_handle_sig(RT_TRUE); + if (rt_interrupt_get_nest() == 0) + { + rt_thread_handle_sig(RT_TRUE); + } } else if (!((tid->stat & RT_THREAD_STAT_SIGNAL_MASK) & RT_THREAD_STAT_SIGNAL)) { /* add signal state */ - tid->stat |= RT_THREAD_STAT_SIGNAL; + tid->stat |= (RT_THREAD_STAT_SIGNAL | RT_THREAD_STAT_SIGNAL_PENDING); +#ifdef RT_USING_SMP + { + int cpu_id; + + cpu_id = tid->oncpu; + if ((cpu_id != RT_CPU_DETACHED) && (cpu_id != rt_hw_cpu_id())) + { + rt_uint32_t cpu_mask; + + cpu_mask = RT_CPU_MASK ^ (1 << cpu_id); + rt_hw_ipi_send(RT_SCHEDULE_IPI, cpu_mask); + } + } +#else /* point to the signal handle entry */ + tid->stat &= ~RT_THREAD_STAT_SIGNAL_PENDING; tid->sig_ret = tid->sp; tid->sp = rt_hw_stack_init((void *)_signal_entry, RT_NULL, (void *)((char *)tid->sig_ret - 32), RT_NULL); +#endif rt_hw_interrupt_enable(level); LOG_D("signal stack pointer @ 0x%08x", tid->sp); @@ -133,14 +168,53 @@ static void _signal_deliver(rt_thread_t tid) } } +#ifdef RT_USING_SMP +void *rt_signal_check(void* context) +{ + rt_base_t level; + int cpu_id; + struct rt_cpu* pcpu; + struct rt_thread *current_thread; + + level = rt_hw_interrupt_disable(); + cpu_id = rt_hw_cpu_id(); + pcpu = rt_cpu_index(cpu_id); + current_thread = pcpu->current_thread; + + if (pcpu->irq_nest) + { + rt_hw_interrupt_enable(level); + return context; + } + + if (current_thread->cpus_lock_nest == 1) + { + if (current_thread->stat & RT_THREAD_STAT_SIGNAL_PENDING) + { + void *sig_context; + + current_thread->stat &= ~RT_THREAD_STAT_SIGNAL_PENDING; + + rt_hw_interrupt_enable(level); + sig_context = rt_hw_stack_init((void *)_signal_entry, context, + (void *)(context - 32), RT_NULL); + return sig_context; + } + } + rt_hw_interrupt_enable(level); + return context; +} +#endif + rt_sighandler_t rt_signal_install(int signo, rt_sighandler_t handler) { + rt_base_t level; rt_sighandler_t old = RT_NULL; rt_thread_t tid = rt_thread_self(); if (!sig_valid(signo)) return SIG_ERR; - rt_enter_critical(); + level = rt_hw_interrupt_disable(); if (tid->sig_vectors == RT_NULL) { rt_thread_alloc_sig(tid); @@ -154,7 +228,7 @@ rt_sighandler_t rt_signal_install(int signo, rt_sighandler_t handler) else if (handler == SIG_DFL) tid->sig_vectors[signo] = _signal_default_handler; else tid->sig_vectors[signo] = handler; } - rt_exit_critical(); + rt_hw_interrupt_enable(level); return old; } @@ -272,7 +346,20 @@ __done: LOG_D("sigwait: %d sig raised!", signo); if (si_prev) si_prev->list.next = si_node->list.next; - else tid->si_list = si_node->list.next; + else + { + struct siginfo_node *node_next; + + if (si_node->list.next) + { + node_next = (void *)rt_slist_entry(si_node->list.next, struct siginfo_node, list); + tid->si_list = node_next; + } + else + { + tid->si_list = RT_NULL; + } + } /* clear pending */ tid->sig_pending &= ~sig_mask(signo); @@ -281,7 +368,14 @@ __done: } si_prev = si_node; - si_node = (void *)rt_slist_entry(si_node->list.next, struct siginfo_node, list); + if (si_node->list.next) + { + si_node = (void *)rt_slist_entry(si_node->list.next, struct siginfo_node, list); + } + else + { + si_node = RT_NULL; + } } __done_int: @@ -320,13 +414,13 @@ void rt_thread_handle_sig(rt_bool_t clean_state) signo = si_node->si.si_signo; handler = tid->sig_vectors[signo]; + tid->sig_pending &= ~sig_mask(signo); rt_hw_interrupt_enable(level); LOG_D("handle signal: %d, handler 0x%08x", signo, handler); if (handler) handler(signo); level = rt_hw_interrupt_disable(); - tid->sig_pending &= ~sig_mask(signo); error = -RT_EINTR; rt_mp_free(si_node); /* release this siginfo node */ @@ -335,10 +429,16 @@ void rt_thread_handle_sig(rt_bool_t clean_state) } /* whether clean signal status */ - if (clean_state == RT_TRUE) tid->stat &= ~RT_THREAD_STAT_SIGNAL; + if (clean_state == RT_TRUE) + { + tid->stat &= ~RT_THREAD_STAT_SIGNAL; + } + else + { + return; + } } } - rt_hw_interrupt_enable(level); } @@ -364,30 +464,30 @@ void rt_thread_alloc_sig(rt_thread_t tid) void rt_thread_free_sig(rt_thread_t tid) { rt_base_t level; - struct siginfo_node *si_list; + struct siginfo_node *si_node; rt_sighandler_t *sig_vectors; level = rt_hw_interrupt_disable(); - si_list = (struct siginfo_node *)tid->si_list; + si_node = (struct siginfo_node *)tid->si_list; tid->si_list = RT_NULL; sig_vectors = tid->sig_vectors; tid->sig_vectors = RT_NULL; rt_hw_interrupt_enable(level); - if (si_list) + if (si_node) { struct rt_slist_node *node; - struct siginfo_node *si_node; + struct rt_slist_node *node_to_free; LOG_D("free signal info list"); - node = &(si_list->list); + node = &(si_node->list); do { - si_node = rt_slist_entry(node, struct siginfo_node, list); - rt_mp_free(si_node); - + node_to_free = node; node = node->next; + si_node = rt_slist_entry(node_to_free, struct siginfo_node, list); + rt_mp_free(si_node); } while (node); } @@ -418,30 +518,23 @@ int rt_thread_kill(rt_thread_t tid, int sig) struct rt_slist_node *node; struct siginfo_node *entry; - node = (struct rt_slist_node *)tid->si_list; - rt_hw_interrupt_enable(level); + si_node = (struct siginfo_node *)tid->si_list; + if (si_node) + node = (struct rt_slist_node *)&si_node->list; + else + node = RT_NULL; /* update sig info */ - rt_enter_critical(); for (; (node) != RT_NULL; node = node->next) { entry = rt_slist_entry(node, struct siginfo_node, list); if (entry->si.si_signo == sig) { memcpy(&(entry->si), &si, sizeof(siginfo_t)); - rt_exit_critical(); + rt_hw_interrupt_enable(level); return 0; } } - rt_exit_critical(); - - /* disable interrupt to protect tcb */ - level = rt_hw_interrupt_disable(); - } - else - { - /* a new signal */ - tid->sig_pending |= sig_mask(sig); } rt_hw_interrupt_enable(level); @@ -452,14 +545,22 @@ int rt_thread_kill(rt_thread_t tid, int sig) memcpy(&(si_node->si), &si, sizeof(siginfo_t)); level = rt_hw_interrupt_disable(); - if (!tid->si_list) tid->si_list = si_node; - else + + if (tid->si_list) { struct siginfo_node *si_list; si_list = (struct siginfo_node *)tid->si_list; rt_slist_append(&(si_list->list), &(si_node->list)); } + else + { + tid->si_list = si_node; + } + + /* a new signal */ + tid->sig_pending |= sig_mask(sig); + rt_hw_interrupt_enable(level); } else diff --git a/src/thread.c b/src/thread.c index 0f2e1dc3d0..276bba9938 100644 --- a/src/thread.c +++ b/src/thread.c @@ -191,7 +191,9 @@ static rt_err_t _rt_thread_init(struct rt_thread *thread, thread->sig_mask = 0x00; thread->sig_pending = 0x00; +#ifndef RT_USING_SMP thread->sig_ret = RT_NULL; +#endif thread->sig_vectors = RT_NULL; thread->si_list = RT_NULL; #endif diff --git a/tools/building.py b/tools/building.py index 4da64f6fcf..c037c2d068 100644 --- a/tools/building.py +++ b/tools/building.py @@ -830,6 +830,10 @@ def GenTargetProject(program = None): from makefile import TargetMakefile TargetMakefile(Env) + if GetOption('target') == 'eclipse': + from eclipse import TargetEclipse + TargetEclipse(Env) + def EndBuilding(target, program = None): import rtconfig diff --git a/tools/eclipse.py b/tools/eclipse.py index dc86c7be5a..78acc8904e 100644 --- a/tools/eclipse.py +++ b/tools/eclipse.py @@ -1,3 +1,14 @@ +# +# Copyright (c) 2006-2019, RT-Thread Development Team +# +# SPDX-License-Identifier: Apache-2.0 +# +# Change Logs: +# Date Author Notes +# 2019-03-21 Bernard the first version +# 2019-04-15 armink fix project update error +# + import os import sys import glob @@ -25,6 +36,8 @@ def OSPath(path): else: return [item.replace('\\', '/') for item in path] + +# collect the build source code path and parent path def CollectPaths(paths): all_paths = [] @@ -87,6 +100,8 @@ def ExcludeFiles(infiles, files): return exl_files + +# caluclate the exclude path for project def ExcludePaths(filepath, paths): ret = [] @@ -106,12 +121,18 @@ def ExcludePaths(filepath, paths): return ret -def HandleToolOption(tools, env): - project = ProjectInfo(env) + +def ConverToEclipsePathFormat(path): + if path.startswith('.'): + path = path[1:] + return '"${workspace_loc:/${ProjName}/' + path + '}"' + + +def HandleToolOption(tools, env, project): BSP_ROOT = os.path.abspath(env['BSP_ROOT']) CPPDEFINES = project['CPPDEFINES'] - paths = ['${ProjDirPath}/' + _make_path_relative(BSP_ROOT, os.path.normpath(i)).replace('\\', '/') for i in project['CPPPATH']] + paths = [ConverToEclipsePathFormat(RelativeProjectPath(env, os.path.normpath(i)).replace('\\', '/')) for i in project['CPPPATH']] for tool in tools: if tool.get('id').find('c.compile') != 1: @@ -157,9 +178,8 @@ def HandleToolOption(tools, env): items = env['LINKFLAGS'].split(' ') if '-T' in items: linker_script = items[items.index('-T') + 1] - linker_script = '${ProjDirPath}/' + linker_script + linker_script = ConverToEclipsePathFormat(linker_script) - # print('c.linker.scriptfile') listOptionValue = option.find('listOptionValue') if listOptionValue != None: listOptionValue.set('value', linker_script) @@ -174,7 +194,7 @@ def HandleToolOption(tools, env): return -def HandleRTTRoot(env): +def UpdateProjectStructure(env): bsp_root = env['BSP_ROOT'] rtt_root = env['RTT_ROOT'] @@ -185,62 +205,54 @@ def HandleRTTRoot(env): # always use '/' path separator rtt_root = rtt_root.replace('\\', '/') - project = etree.parse('.project') - root = project.getroot() + # TODO create the virtual folder - linkedResources = root.find('linkedResources') - if linkedResources == None: - # add linkedResources - linkedResources = SubElement(root, 'linkedResources') - # print('add linkedResources') - else: - links = linkedResources.findall('link') - # search exist 'rt-thread' virtual folder - for link in links: - if link.find('name').text == 'rt-thread': - # handle location - to_SubElement = False - location = link.find('location') - location.text = rtt_root - - if to_SubElement: - # print('to subelement for virtual folder') - link = SubElement(linkedResources, 'link') - name = SubElement(link, 'name') - name.text = 'rt-thread' - type = SubElement(link, 'type') - type.text = '2' - location = SubElement(link, 'location') - location.text = rtt_root - - out = open('.project', 'w') - out.write('\n') - xml_indent(root) - out.write(etree.tostring(root, encoding='utf-8')) - out.close() +# project = etree.parse('.project') +# root = project.getroot() +# +# linkedResources = root.find('linkedResources') +# if linkedResources == None: +# # add linkedResources +# linkedResources = SubElement(root, 'linkedResources') +# # print('add linkedResources') +# else: +# links = linkedResources.findall('link') +# # search exist 'rt-thread' virtual folder +# for link in links: +# if link.find('name').text == 'rt-thread': +# # handle location +# to_SubElement = False +# location = link.find('location') +# location.text = rtt_root +# +# if to_SubElement: +# # print('to subelement for virtual folder') +# link = SubElement(linkedResources, 'link') +# name = SubElement(link, 'name') +# name.text = 'rt-thread' +# type = SubElement(link, 'type') +# type.text = '2' +# location = SubElement(link, 'location') +# location.text = rtt_root +# +# out = open('.project', 'w') +# out.write('\n') +# xml_indent(root) +# out.write(etree.tostring(root, encoding='utf-8')) +# out.close() return -def TargetEclipse(env): - global source_pattern +def GenExcluding(env, project): + rtt_root = os.path.abspath(env['RTT_ROOT']) + coll_dirs = CollectPaths(project['DIRS']) + all_paths = [OSPath(path) for path in coll_dirs] - print('Update eclipse setting...') + exclude_paths = ExcludePaths(rtt_root, all_paths) - if not os.path.exists('.cproject'): - print('no eclipse CDT project found!') - return - - HandleRTTRoot(env) - - project = ProjectInfo(env) - - all_paths = [OSPath(path) for path in CollectPaths(project['DIRS'])] - # print(all_paths) - bsp_root = os.path.abspath(env['BSP_ROOT']) - - exclude_paths = ExcludePaths(bsp_root, all_paths) paths = exclude_paths exclude_paths = [] + # remove the folder which not has source code by source_pattern for path in paths: # add bsp and libcpu folder and not collect source files (too more files) if path.endswith('rt-thread\\bsp') or path.endswith('rt-thread\\libcpu'): @@ -251,15 +263,37 @@ def TargetEclipse(env): if len(set): exclude_paths += [path] - exclude_paths = [_make_path_relative(bsp_root, path).replace('\\', '/') for path in exclude_paths] + exclude_paths = [RelativeProjectPath(env, path).replace('\\', '/') for path in exclude_paths] env['ExPaths'] = exclude_paths all_files = CollectFiles(all_paths, source_pattern) src_files = project['FILES'] exclude_files = ExcludeFiles(all_files, src_files) - exclude_files = [_make_path_relative(bsp_root, file).replace('\\', '/') for file in exclude_files] + exclude_files = [RelativeProjectPath(env, file).replace('\\', '/') for file in exclude_files] env['ExFiles'] = exclude_files + + return exclude_paths + exclude_files + + +def RelativeProjectPath(env, path): + project_root = os.path.abspath(env['BSP_ROOT']) + rtt_root = os.path.abspath(env['RTT_ROOT']) + + if path.startswith(project_root): + return _make_path_relative(project_root, path) + + if path.startswith(rtt_root): + return 'rt-thread/' + _make_path_relative(rtt_root, path) + + # TODO add others folder + print('ERROR: the ' + path + 'not support') + + return path + + +def UpdateCproject(env, project, excluding): + excluding = sorted(excluding) cproject = etree.parse('.cproject') @@ -267,24 +301,21 @@ def TargetEclipse(env): cconfigurations = root.findall('storageModule/cconfiguration') for cconfiguration in cconfigurations: tools = cconfiguration.findall('storageModule/configuration/folderInfo/toolChain/tool') - HandleToolOption(tools, env) + HandleToolOption(tools, env, project) sourceEntries = cconfiguration.find('storageModule/configuration/sourceEntries') entry = sourceEntries.find('entry') if entry != None: sourceEntries.remove(entry) - excluding = exclude_paths + exclude_files - excluding = sorted(excluding) value = '' for item in excluding: if value == '': value = item else: value += '|' + item - excluding = value - SubElement(sourceEntries, 'entry', {'excluding': excluding, 'flags': 'VALUE_WORKSPACE_PATH|RESOLVED', 'kind':'sourcePath', 'name':""}) + SubElement(sourceEntries, 'entry', {'excluding': value, 'flags': 'VALUE_WORKSPACE_PATH|RESOLVED', 'kind':'sourcePath', 'name':""}) # write back to .cproject out = open('.cproject', 'w') @@ -294,6 +325,27 @@ def TargetEclipse(env): out.write(etree.tostring(root, encoding='utf-8')) out.close() + +def TargetEclipse(env): + global source_pattern + + print('Update eclipse setting...') + + if not os.path.exists('.cproject'): + print('no eclipse CDT project found!') + return + + project = ProjectInfo(env) + + # update the project file structure info on '.project' file + UpdateProjectStructure(env) + + # generate the exclude paths and files + excluding = GenExcluding(env, project) + + # update the project configuration on '.cproject' file + UpdateCproject(env, project, excluding) + print('done!') return diff --git a/tools/keil.py b/tools/keil.py index 59da254430..b096917a42 100644 --- a/tools/keil.py +++ b/tools/keil.py @@ -56,6 +56,7 @@ def _get_filetype(fn): def MDK4AddGroupForFN(ProjectFiles, parent, name, filename, project_path): group = SubElement(parent, 'Group') + group.text = name group_name = SubElement(group, 'GroupName') group_name.text = name @@ -244,9 +245,13 @@ def MDK45Project(tree, target, script): lib_path = full_path if lib_path != '': - if (group_tree != None): - MDK4AddLibToGroup(ProjectFiles, group_tree, group['name'], lib_path, project_path) - else: + need_create = 1 + for neighbor in groups.iter('Group'): + if neighbor.text == group['name']: + MDK4AddLibToGroup(ProjectFiles, neighbor, group['name'], lib_path, project_path) + need_create = 0 + break + if (need_create != 0): MDK4AddGroupForFN(ProjectFiles, groups, group['name'], lib_path, project_path) # write include path, definitions and link flags diff --git a/tools/menuconfig.py b/tools/menuconfig.py index 2550424802..049bc4f2ac 100644 --- a/tools/menuconfig.py +++ b/tools/menuconfig.py @@ -23,6 +23,7 @@ # 2018-07-31 weety Support pyconfig import os +import re import sys import shutil @@ -75,7 +76,7 @@ def mk_rtconfig(filename): if setting[1] == 'y': rtconfig.write('#define %s\n' % setting[0]) else: - rtconfig.write('#define %s %s\n' % (setting[0], setting[1])) + rtconfig.write('#define %s %s\n' % (setting[0], re.findall(r"^.*?=(.*)$",line)[0])) if os.path.isfile('rtconfig_project.h'): rtconfig.write('#include "rtconfig_project.h"\n') diff --git a/tools/utils.py b/tools/utils.py index 6dc56322a5..9459396544 100644 --- a/tools/utils.py +++ b/tools/utils.py @@ -24,6 +24,7 @@ import sys import os +import re def splitall(loc): """ @@ -245,10 +246,11 @@ def ProjectInfo(env): return proj def VersionCmp(ver1, ver2): - la=[]; + la=[] if ver1: - la = ver1.split('.') - lb = ver2.split('.') + la = re.split("[. ]", ver1) + lb = re.split("[. ]", ver2) + f = 0 if len(la) > len(lb): f = len(la) @@ -262,7 +264,7 @@ def VersionCmp(ver1, ver2): continue else: return -1 - except IndexError as e: + except (IndexError, ValueError) as e: if len(la) > len(lb): return 1 else: @@ -274,7 +276,7 @@ def GCCC99Patch(cflags): gcc_version = building.GetDepend('GCC_VERSION') if gcc_version: gcc_version = gcc_version.replace('"', '') - if VersionCmp(gcc_version, "4.8.0"): + if VersionCmp(gcc_version, "4.8.0") == 1: # remove -std=c99 after GCC 4.8.x cflags = cflags.replace('-std=c99', '')